pax_global_header00006660000000000000000000000064152366200470014517gustar00rootroot0000000000000052 comment=790013b076ecde4522e651c0e0a394e1a4f5f9c2 .gitattributes000066400000000000000000000003051523662004700137540ustar00rootroot00000000000000# These files are text and should be normalized (convert crlf => lf) *.lyx text # Images should be treated as binary # (binary is a macro for -text -diff) *.png binary *.gif binary .gitignore000066400000000000000000000005611523662004700130550ustar00rootroot00000000000000# NOTE! Please use 'git ls-files -i --exclude-standard' # command after changing this file, to see if there are # any tracked files which get ignored after the change. # # (compile "git ls-files -i --exclude-standard") Makefile Makefile.in *.orig *~ \#*# *.log /autom4te.cache /config.guess /config.log /config.status /config.sub /configure /aclocal.m4 /manual.pdf AUTHORS000066400000000000000000000002261523662004700121330ustar00rootroot00000000000000Giles Atkinson Paolo Nenzi Holger Vogt Dietmar Warning and many other contributors who provided the original spice3, CIDER and XSPICE documentation. Bug-LyX.txt000066400000000000000000000005441523662004700130560ustar00rootroot00000000000000LyX 2.4.4 seems to have a bug: the reply to the -version command line option is an empty string using the MS Windows version and calling 'LyX -version' in a CygWin or MINGW bash window. This leads to failure when checking for the version during ./configure. Therefore the file configure-nocheck.ac may be renamed to configure.ac to skip the version check. COPYING000066400000000000000000000021161523662004700121160ustar00rootroot0000000000000012345678901234567890123456789012345678901234567890123456789012345678901234567890 Ngspice-45 Documentation Copyright (c) 2025, Holger Vogt, Giles Atkinson, Dietmar Warning, Paolo Nenzi All rights reserved. Foreword: The name "Spice" was originally chosen at the University of California, Berkeley. As it is the basis of almost all circuit simulators, the major part of the analogue and mixed signals simulation code is designed to fit with it. The *spices (generic name for its forks) are heterogeneous in many points due to the work of researchers, electronic designers, software editors, etc. The Ngspice team has collected work from the different sources and then contributes new functionalities. Thus, the material we manipulate is heterogeneous in licenses, as reflected by the license for the ngspice manual. License for the ngspice manual: This document is covered by the Creative Commons Attribution Share-Alike (CC-BY-SA) v4.0 (see https://creativecommons.org/licenses/by-sa/4.0/). Parts of chapters 12 and 21-25 are in the public domain. Chapter 26 on CIDER is covered by New BSD. ChangeLog000066400000000000000000000262001523662004700126350ustar00rootroot00000000000000ChangeLog is no longer maintained since switching to the git repository. Please see http://ngspice.git.sourceforge.net/git/gitweb.cgi?p=ngspice/ngspice-manuals;a=summary for the manual code history. 2012-02-20 Holger Vogt * new commands mdump, mrdump, small updates, Lyx 1.6 2012-02-19 Dietmar Warning * temperature model for asrc, expression based resistor, capacitor and inductor 2012-02-17 Holger Vogt * update chapt. 32 2012-02-11 Holger Vogt * update chapt. 16.4 2012-02-03 Holger Vogt * small update chapt. 2.2.4 ============================ ngspice-24 ================================== 2012-01-28 Robert Larice fix incompatibility with lyx 1.6 caused by an empty layout section: \begin_layout Standard \end_layout 2012-01-27 Holger Vogt * small updates, prepare release 24 2012-01-15 Holger Vogt * 16.11 2012-01-01 Holger Vogt * 16.11, 31.2.7 2012-01-01 Holger Vogt * 2.10, 16.13 2011-12-26 Holger Vogt * floor, ceil functions 2011-12-25 Holger Vogt * compatibility chapt. 16.13 2011-12-21 Holger Vogt * usage of int_ic in s_xfer chapt. 12.2.16 * update chapts. 5.2, 5.3: E- or G-Source with TABLE 2011-12-17 Holger Vogt * error handling chapt. 18.5 * chapt. 5.2, 5.3 2011-12-10 Holger Vogt * updates to chapts. 15 and 17 2011-12-07 Holger Vogt * new 12.2.9 multi_input_pwl block 2011-11-27 Holger Vogt * new 17.4.44 Remcirc 2011-11-26 Holger Vogt * new 17.7.8 Output redirection 2011-11-20 Holger Vogt * small update in intro 2011-11-05 Holger Vogt * small update to chapt. 31, 32 2011-11-01 Holger Vogt * small update to chapt. 31 2011-10-30 Holger Vogt * hisim_hv 1.2.2 in chapt. 11.2.14 2011-10-29 Holger Vogt * small updates to chapts. 2 and 6 2011-10-22 Holger Vogt * bug no. 3426444 * conversion to lyx16 improved 2011-10-17 Holger Vogt * moved back to lyx16 format for compatibility with debian stable * small addition to 17.4.40 2011-10-03 Holger Vogt * small corrections 2011-10-02 Holger Vogt * chapt. 17.4.4 altermod updated * chapt. 22.5.2 ASCO inv updated 2011-09-18 Holger Vogt * chapt. 17.4.4 altermod updated 2011-09-16 Holger Vogt * chapt. 22 updated 2011-09-15 Holger Vogt * chapt. 17.4.59 60 update on show, showmod 2011-09-14 Holger Vogt * chapt. 17.4.4 update on altermod 2011-09-11 Holger Vogt * chapt. 22 extended by op-amp example 2011-09-09 Holger Vogt * new chapt. 22 on circuit optimization inserted * several typos removed 2011-08-30 Holger Vogt * chapt. 26.4 2011-08-29 Holger Vogt * chapt. 26 2011-08-28 Holger Vogt * chapt. 23, 26 * images/XSPICE-Toplevel.gif 2011-08-27 Holger Vogt * chapt. 24.3 on how to create new code models * chapt. 26 on how to create new code models 2011-08-26 Holger Vogt * 29 device parameters from nested subcircuits 2011-08-09 Holger Vogt * 18.6 on Gnuplot added 2011-08-09 Holger Vogt * 15.3 uic to end of line 2011-08-06 Holger Vogt * add fcn cph(vector) to chapt. 17.1 2011-08-04 Paolo Nenzi * Added manual entries for PSS as written by Stefano Perticaroli and added * Stefano to ngspice contributors. * lyx updated to version 2.0 (not backward compatible). 2011-07-17 Holger Vogt * new fcns sinh, cosh, tanh chapt. 17 2011-07-16 Holger Vogt * Update chapt. 18 2011-07-10 Holger Vogt * 17.1 add NGSPICE_INPUT_DIR 2011-07-09 Holger Vogt * Update to chapters 20, 25 2011-07-03 Holger Vogt * 7.3 2011-06-23 Holger Vogt * new code model 'filesource' 2011-06-23 Holger Vogt * BSIM4.7 2011-06-05 Holger Vogt * update command 'destroy' ============================ ngspice-23 ================================== 2011-06-01 Holger Vogt * bug no. 3310132 fixed 2011-05-29 Holger Vogt * prepare for release 23 2011-05-24 Holger Vogt * update to MOS models (HiSIM) 2011-05-07 Dietmar Warning * MOS instance parameter delvto and mulu0 * First binning description 2011-05-04 Dietmar Warning * update of MOS table, add HiSIM HV model 2011-04-12 Dietmar Warning * update of MOS table 2011-03-18 Dietmar Warning * bjt nkf introduction 2011-03-16 Holger Vogt * 17.4.33 par('expression') not applicable 2011-03-05 Holger Vogt * 24.2.1.4 supply ramping updated 2011-02-22 Dietmar Warning * diode & bjt temperature model update 2011-02-22 Holger Vogt * Parameter sweep 17.7 2011-02-19 Holger Vogt * .measure 15.4 2011-02-15 Holger Vogt * CIDER manual, chapt. 28 2011-02-12 Holger Vogt * chapt. 21 on statistical analyis, various updates * new images added 2011-01-23 Holger Vogt * add 2 images, chapt. 27 2011-01-21 Holger Vogt * chapt. 22 update 2011-01-19 Holger Vogt * chapt. 25, example 3 update 2011-01-16 Holger Vogt * 4.1.8 TRRANDOM option to voltage source added 2011-01-11 Holger Vogt * 15.4.7 .width 2011-01-09 Holger Vogt * small updates 2011-01-08 Holger Vogt * 17.4.9 command 'cdump' 2011-01-03 Holger Vogt * small updates 2011-01-01 Holger Vogt * small updates 2011-01-01 Holger Vogt * new format (12 pt, Times Roman) * several updates 2010-12-29 Holger Vogt * 2.8.5 new functions for numparam 2010-12-25 Holger Vogt * 16.3.10 update to RTS transient noise 2010-12-18 Holger Vogt * 4.2.6, 16.3.10 RTS transient noise 2010-12-17 Holger Vogt * update 4.2.6 2010-12-13 Holger Vogt * chapt. 4.2.6 2010-12-11 Holger Vogt * chapt. 6.1 2010-11-27 Holger Vogt * 13.2.21 controlled one-shot * 4.2.6, 16.3.10 transient noise 2010-11-13 Holger Vogt * 3.2.14, 3.2.15 switch * 13.2.21 controlled one-shot 2010-11-01 Holger Vogt * 10.2.2 Modified Parker Skellern model 2010-10-31 Dietmar Warning * few corrections in 16.1.3 2010-10-25 Holger Vogt * 'linearize' only in ngspice 2010-10-25 Holger Vogt * scattering parameters in chapt. 18.9.2 2010-10-16 Holger Vogt * scattering parameters in chapt. 18.9 * new command wrs2p in chapt. 18.4.75 2010-10-15 Holger Vogt * more on licenses (now chapt. 32) 2010-10-13 Dietmar Warning * trtol setting if xspice enabled and no 'A' devices 2010-10-12 Holger Vogt * on licenses (readline linking) 2010-10-09 Holger Vogt * more on Monte Carlo (18.8) 2010-10-05 Dietmar Warning * small corrections regarding mos9 and adms 2010-10-03 Holger Vogt * decription on .ac and ac 2010-09-23 Holger Vogt * ngspice-22 2010-09-20 Holger Vogt * chapt. 2.8.1 2010-09-19 Holger Vogt * MINGW 64 bit support 2010-09-11 Holger Vogt * more on .measure 16.3.10 2010-09-08 Holger Vogt * start with .measure 16.3.10 2010-09-06 Holger Vogt * still version 21plus * 18.4.35 plot alli allv ally 2010-09-06 Holger Vogt * Version 22 2010-09-05 Holger Vogt * 18.4.50 Setscale 2010-09-02 Holger Vogt * 18.8 Monte-Carlo Simulation 2010-08-28 Holger Vogt * update 18.4, 18.7 2010-08-25 Holger Vogt * update 2.10 2010-08-24 Holger Vogt * tf, pipe, server etc. 2010-08-22 Holger Vogt * JFET, MESFET 2010-08-19 Holger Vogt * 17.2 Where to get ngspice 2010-08-17 Holger Vogt * Add a new chapter 14 on adms 2010-07-17 Holger Vogt * deftype 17.4.13 (already existing in ngspice) 2010-07-11 Holger Vogt * Chapt. 15.1.6 on options, new command 'option' 17.4.33 2010-07-11 Holger Vogt * Chapt. 16.7 update on trtol 2010-07-10 Holger Vogt * Chapt. 15.4.6 par('expression'): Algebraic expressions for output 2010-07-08 Holger Vogt * Chapt. 16.7 on simulation time added 2010-07-02 Holger Vogt * Chapt. 17.7.5 Example script 'spectrum' 2010-07-02 Holger Vogt * Chapt. 2.2.1 .TITLE added * Chapt. 16 BSOI OpenMP added * Chapt. 2.10 on parameters, non-linear sources and control scripts 2010-06-28 Holger Vogt * Chapt. 16.7 on OpenMP BSIM4 added 2010-06-22 Holger Vogt * version 21plus ****************** rework-21 ******************* 2010-06-20 Holger Vogt * manual.lyx, COPYING: copyright updates * NEWS small intro 2010-06-20 Robert Larice * Makefile: removed * .cvsignore, * AUTHORS, COPYING, NEWS, README, * INSTALL, * config/install-sh, config/missing, * Makefile.am, configure.ac, new files ng-spice-manual is a package of its own now. 2010-06-20 Holger Vogt * SOI stag model level number added 2010-06-16 Holger Vogt * Some corrections to chap. 16 2010-06-14 Holger Vogt * Final Update version 21, add chapter on environmental variables 2010-06-12 Robert Larice * Add capability to generate the pdf * Add capability to upload the pdf 2010-06-12 Holger Vogt * Remove pdf binary 2010-06-10 Holger Vogt * Version 21 2010-06-05 Holger Vogt * various updates (chapts. 1, 2 e.a.) 2010-06-05 Holger Vogt * update on spinit, .spiceinit and command line options 2010-06-04 Holger Vogt * chapt. 17.4.44 small update on 'save' command 2010-05-27 Holger Vogt * chapt. 6.1 new example 2010-05-26 Holger Vogt * chapt. 27 update on XSPICE api using cm_analog_alloc() and cm_event_alloc() 2010-05-18 Holger Vogt * update on enabling XSPICE 2010-05-13 Holger Vogt * update on vectors, new links added 2010-05-09 Holger Vogt * variable ngbehavior, some updates 2010-05-08 Holger Vogt * non linear sources (E, G) and non-linear elements (R, C, L) 2010-04-06 Holger Vogt * update Chapt. 6 (thanks to R. Larice) 2010-04-04 Holger Vogt * update .lib, .global, resistor 2010-03-29 Holger Vogt * updates in chapt. 17.4 2010-03-27 Holger Vogt * reshuffling of chapter, errors removed * ngspice start options explained 2010-03-20 Holger Vogt * hertz for B source 2010-03-07 Holger Vogt * time and temper for B source 2010-03-06 Holger Vogt * small updates, fixes 2010-03-02 Holger Vogt * option 'param' added to command 'listing' * pdf with hyperlinks inside the text 2010-03-01 Dietmar Warning * update fft window functions 2010-02-28 Holger Vogt * ternary function in B source (chapt. 5.6) 2010-02-27 Holger Vogt * Independent voltage source PWL update, Chapt. 4.2.4 * new command wrdata 2010-01-12 Holger Vogt * some updates on the fft and noise commands, section on plots added. 2010-01-27 Dietmar Warning * update kspice transmissionline chapter 2010-01-02 Holger Vogt * compose command added xfont, wfont, wfont_size variables added 2010-01-01 Holger Vogt * gnuplot command added 2009-12-31 Holger Vogt * update on availabilty and description of internal variables 2009-12-30 Holger Vogt * update on variable plotstyle 2009-12-28 Holger Vogt * some formatting, update to manual.pdf chapters 15, 16 reorganized, started to describe scripting spinit, strcmp added 2009-12-22 Dietmar Warning * a bit more precise B pwl description 2009-12-19 Holger Vogt * update on chapt. 14 .measure * update on chapt. 15 save * formatting various sections 2009-12-15 Holger Vogt * chapt. 14 start describing .measure 2009-12-07 Holger Vogt * chapt. 15 command line options updated 2009-12-06 Holger Vogt * chapt. 15.3 alter and altermod modified 2009-12-04 Dietmar Warning * first trx and cpl descriptions - but more as a placeholder 2009-11-21 Holger Vogt * description of .func in chap. 2.9 added. * chapter 26 on installation updated 2009-11-21 Holger Vogt * chapter 16 on GUIs introduced 2009-11-21 Holger Vogt * formatting the output (still much to be done!) chapter 15.1 functions added 2009-11-20 Holger Vogt * chapter 15.5 description postscript variables updated 2009-11-19 Holger Vogt * variable hcopypscolor 2009-11-07 Holger Vogt * replace . by _ in several codemodel descriptions of chapter 12 INSTALL000066400000000000000000000004321523662004700121130ustar00rootroot00000000000000Installation Instructions ************************* Install Lyx 2.4 or newer Run the commands: aclocal autoconf automake ./configure make make install to generate manual.pdf. Alternatively you may load manual.lyx directly into Lyx and export a pdf file (e.g. with PDF XeTex). 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Please see README and COPYING for # terms of use. # # SPDX-License-Identifier: CC-BY-SA-4.0 ## Additional targets that will be processed by the distcheck target. installcheck-am: check-lyx-files check-png-files # dist EXTRA_DIST = manual.lyx Tables Images MAINTAINERCLEANFILES = manual.pdf ## Needed PNG files for the documentation. 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'$${entry}' not found in \$$(LYX_FILES)!" ;\ ERROR=1 ;\ fi ;\ done ;\ if [ "$${ERROR}" == "1" ]; then \ echo "" ;\ echo -e " \033[1;93mWARNING!!!" ;\ echo " At least one '*.lyx' file was found in the folder '$(top_srcdir)/Tables' that is not added to \$$(LYX_FILES) in '$(top_srcdir)/Makefile.am'!" ;\ echo -e " You might have forgotten to add these files?\e[0m" ;\ echo "" ;\ else \ echo "All files found." ;\ fi ## Some sanity checks for the PNG files. ## This target will get called by the 'distcheck' target, The intention is ## to check for completeness of the files referenced by $(GRAPHIC_FILES). check-png-files: @echo -e "\nChecking availability of listed files in \$$(GRAPHIC_FILES)..." @for file in $(GRAPHIC_FILES); do \ NOT_FOUND=0 ;\ if [ ! -f $${file} ]; then \ echo $${file} not found! ;\ NOT_FOUND=1 ;\ fi \ done ;\ if [ "$${NOT_FOUND}" -eq "1" ]; then \ echo "At least one file from \$$(GRAPHICS_FILES) could not be found!" ;\ else \ echo "All files found." ;\ fi @echo -e "\nChecking for existing files that are *not* listed in \$$(GRAPHICS_FILES)..." @FOUND_GRAPHICS_FILES=`find $(top_srcdir)/Images -type f -name "*.png" | sort` ;\ ERROR=0 ;\ for entry in $${FOUND_GRAPHICS_FILES}; do \ FOUND_FILE=`basename $${entry}` ;\ echo "Checking $${FOUND_FILE} from $(top_srcdir)/Tables" ;\ for listed_lyx_file in $(GRAPHICS_FILES); do \ GIVEN_FILE=`basename $${listed_graphics_file}` ;\ FOUND=0 ;\ if [ "$${FOUND_FILE}" == "$${GIVEN_FILE}" ]; then \ FOUND=1 ;\ break ;\ fi ;\ done ;\ if [ "$${FOUND}" == "0" ]; then \ echo "Ooops! '$${entry}' not found in \$$(GRAPHICS_FILES)!" ;\ ERROR=1 ;\ fi ;\ done ;\ if [ "$${ERROR}" == "1" ]; then \ echo "" ;\ echo -e " \033[1;93mWARNING!!!" ;\ echo " At least one '*.png' file was found in the folder '$(top_srcdir)/Images' that is not added to \$$(GRAPHICS_FILES) in '$(top_srcdir)/Makefile.am'!" ;\ echo -e " You might have forgotten to add these files?\e[0m" ;\ echo "" ;\ else \ echo "All files found." ;\ fi install-data-am: install-pdf-am install-html-am uninstall-am: rm -rf $(DESTDIR)$(docdir) $(DESTDIR)$(htmldir) clean-local: rm -rf $(top_builddir)/$(BUILD_PDF) rm -rf $(top_builddir)/$(BUILD_HTML) distclean-local: clean-local upload: chmod 664 $(top_builddir)/$(BUILD_PDF)/manual.pdf scp $(top_builddir)/$(BUILD_PDF)/manual.pdf web.sourceforge.net:htdocs/docs echo "ls -l htdocs/docs" | sftp web.sourceforge.net NEWS000066400000000000000000000004741523662004700115670ustar00rootroot00000000000000The manual for ngspice-45 is here! Since ngspice-21, we provide an elaborate manual. It's source is a Lyx file plus tables and pictures, it's standard distribution is a pdf file. A xhtml version may be compiled as well. The manual actually uses Lyx 2.4 as its text processor, and Tex Live 2025 for background data. README000066400000000000000000000012351523662004700117440ustar00rootroot00000000000000This Package contains the `Ngspice Users Manual' DESCRIPTION: ============ The Manual is composed from several LyX and image files. This Package provides rules to: * generate a pdf file from those. * generate a HTML based documentation. * install the pdf somewhere. * build a tar-ball for distribution. USAGE: ====== eventually run: autoreconf [--verbose] --install To `install' do something like: ./configure [--prefix=DIR] ; make ; make install Please read `INSTALL' for detailed instructions. REQUIREMENTS: ============= You need: `LyX 2.4' `TeX' and something like `texlive-lang-greek' You need: `GNU make' Tables/000077500000000000000000000000001523662004700122755ustar00rootroot00000000000000Tables/ASRC.lyx000066400000000000000000000256771523662004700136040ustar00rootroot00000000000000#LyX 2.1 created this file. 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program, script, or datafile scriptversion=2006-12-25.00 # This originates from X11R5 (mit/util/scripts/install.sh), which was # later released in X11R6 (xc/config/util/install.sh) with the # following copyright and license. # # Copyright (C) 1994 X Consortium # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to # deal in the Software without restriction, including without limitation the # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or # sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN # AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC- # TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # # Except as contained in this notice, the name of the X Consortium shall not # be used in advertising or otherwise to promote the sale, use or other deal- # ings in this Software without prior written authorization from the X Consor- # tium. # # # FSF changes to this file are in the public domain. # # Calling this script install-sh is preferred over install.sh, to prevent # `make' implicit rules from creating a file called install from it # when there is no Makefile. # # This script is compatible with the BSD install script, but was written # from scratch. nl=' ' IFS=" "" $nl" # set DOITPROG to echo to test this script # Don't use :- since 4.3BSD and earlier shells don't like it. doit=${DOITPROG-} if test -z "$doit"; then doit_exec=exec else doit_exec=$doit fi # Put in absolute file names if you don't have them in your path; # or use environment vars. chgrpprog=${CHGRPPROG-chgrp} chmodprog=${CHMODPROG-chmod} chownprog=${CHOWNPROG-chown} cmpprog=${CMPPROG-cmp} cpprog=${CPPROG-cp} mkdirprog=${MKDIRPROG-mkdir} mvprog=${MVPROG-mv} rmprog=${RMPROG-rm} stripprog=${STRIPPROG-strip} posix_glob='?' initialize_posix_glob=' test "$posix_glob" != "?" || { if (set -f) 2>/dev/null; then posix_glob= else posix_glob=: fi } ' posix_mkdir= # Desired mode of installed file. mode=0755 chgrpcmd= chmodcmd=$chmodprog chowncmd= mvcmd=$mvprog rmcmd="$rmprog -f" stripcmd= src= dst= dir_arg= dst_arg= copy_on_change=false no_target_directory= usage="\ Usage: $0 [OPTION]... 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Some to-dos are listed in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:To-Do" nolink "false" \end_inset . More is surely needed. You are invited to report bugs, missing items, wrongly described items, bad English style, etc. The preferred place for such reports is our \begin_inset CommandInset href LatexCommand href name "bug tracker" target "https://sourceforge.net/p/ngspice/bugs/" literal "false" \end_inset . \end_layout \begin_layout Section* How to use this Manual \end_layout \begin_layout Standard The manual is a \begin_inset Quotes eld \end_inset work in progress. \begin_inset Quotes erd \end_inset It may accompany a specific ngspice release, e.g. ngspice-44 as manual version 44. If its name contains `Version xxplus', it describes the actual code status, found at the date of issue in the Git Source Code Management (SCM) tool. This manual is intended to provide a complete description of ngspice's functionality, features, commands, and procedures. This manual is not a book about learning SPICE usage, however the novice user may find some hints how to start using ngspice. Chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:AC-coupled-transistor" nolink "false" \end_inset gives a short introduction how to set up and simulate a small circuit. Chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Compilation-notes" nolink "false" \end_inset is about compiling and installing ngspice from a tarball or the actual Git source code, which you may find on the \begin_inset CommandInset href LatexCommand href name "ngspice web pages" target "http://ngspice.sourceforge.net/download.html" literal "false" \end_inset . If you are running a specific Linux distribution, you may check if it provides ngspice as part of the package. Some are listed \begin_inset CommandInset href LatexCommand href name "here" target "http://ngspice.sourceforge.net/packages.html" literal "false" \end_inset . \end_layout \begin_layout Section* License \end_layout \begin_layout Standard This document is covered by the \begin_inset CommandInset href LatexCommand href name "Creative Commons Attribution Share-Alike (CC-BY-SA) v4.0." target "https://creativecommons.org/licenses/by-sa/4.0/" literal "false" \end_inset . \end_layout \begin_layout Standard Part of chapters 12 and 25-29 are in the public domain. \end_layout \begin_layout Standard Chapter 30 is covered by New BSD (chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:`Modified'-BSD-license" nolink "false" \end_inset ). \end_layout \begin_layout Standard \begin_inset Newpage newpage \end_inset \end_layout \begin_layout Standard \begin_inset CommandInset toc LatexCommand tableofcontents \end_inset \end_layout \begin_layout Subsection* \begin_inset Newpage newpage \end_inset \end_layout \begin_layout Part Ngspice User's Manual \end_layout \begin_layout Chapter* Prefaces \end_layout \begin_layout Section* Preface to the first edition \end_layout \begin_layout Standard This manual has been assembled from different sources: \end_layout \begin_layout Enumerate The spice3f5 manual, \end_layout \begin_layout Enumerate the XSPICE user's manual, \end_layout \begin_layout Enumerate the CIDER user's manual \end_layout \begin_layout Standard and some original material needed to describe the new features and the newly implemented models. This cut and paste approach, while not being orthodox, allowed ngspice to have a full manual in a fraction of the time that writing a completely new text would have required. The use of \begin_inset ERT status open \begin_layout Plain Layout LaTex \end_layout \end_inset and \SpecialChar LyX instead of \begin_inset ERT status open \begin_layout Plain Layout TeX \end_layout \end_inset info, which was the original encoding for the manual, further helped to reduce the writing effort and improved the quality of the result, at the expense of an on-line version of the manual but, due to the complexity of the software I hardly think that users will ever want to read an on-line text version. \end_layout \begin_layout Standard In writing this text I followed the spice3f5 manual, both in the chapter sequence and presentation of material, mostly because that was already the user manual of SPICE. \end_layout \begin_layout Standard Ngspice is an open source software, users can download the source code, compile, and run it. This manual has an entire chapter describing program compilation and available options to help users in building ngspice (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Compilation-notes" nolink "false" \end_inset ). The source package already comes with all `safe' options enabled by default, and activating the others can produce unpredictable results and thus is recommended to expert users only. This is the first ngspice manual and I have removed all the historical material that described the differences between ngspice and spice3, since it was of no use for the user and not so useful for the developer who can look for it in the Changelogs of in the revision control system. \end_layout \begin_layout Standard I want to acknowledge the work done by Emmanuel Rouat and Arno W. Peters for converting the original spice3f documentation to \SpecialChar TeX info. Their effort gave ngspice users the only available documentation that described the changes for many years. A good source of ideas for this manual came from the on-line spice3f manual written by Charles D.H. Williams ( \begin_inset CommandInset href LatexCommand href name "Spice3f5 User Guide" target "http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/index.html#toc" literal "false" \end_inset ), constantly updated and useful for its many insights. \end_layout \begin_layout Standard As always, errors, omissions and unreadable phrases are only my fault. \end_layout \begin_layout Standard Paolo Nenzi \end_layout \begin_layout Standard Roma, March 24th 2001 \end_layout \begin_layout Quotation Indeed. At the end of the day, this is engineering, and one learns to live \end_layout \begin_layout Quotation within the limitations of the tools. \end_layout \begin_layout Standard Kevin Aylward, Warden of the King's Ale \end_layout \begin_layout Section* Preface to the current edition (as of Mar 2026) \end_layout \begin_layout Standard Due to the wealth of new material and options in ngspice the actual order of chapters has been revised. Several new chapters have been added. The \SpecialChar LyX text processor has allowed adding internal cross references. The PDF format has become the standard format for distribution of the manual. There is also a \begin_inset CommandInset href LatexCommand href name "xhtml" target "http://ngspice.sourceforge.net/docs/ngspice-html-manual/manual.xhtml" literal "false" \end_inset version available. Within each new ngspice distribution a manual edition is provided reflecting the ngspice status at the time of distribution. At the same time, located at \begin_inset CommandInset href LatexCommand href name "ngspice manuals" target "http://ngspice.cvs.sourceforge.net/viewvc/ngspice/ngspice/ng-spice-manuals/" literal "false" \end_inset , the manual is constantly updated. Every new ngspice feature should enter this manual as soon as it has been made available in the Git source code master branch. \end_layout \begin_layout Standard Holger Vogt \end_layout \begin_layout Standard Mülheim, 2026 \end_layout \begin_layout Chapter* Acknowledgments \end_layout \begin_layout Section* ngspice contributors \end_layout \begin_layout Standard Spice3 and CIDER were originally written at The University of California at Berkeley (USA). \end_layout \begin_layout Standard XSPICE has been provided by Georgia Institute of Technology, Atlanta (USA). \end_layout \begin_layout Standard Since then, there have been many people working on the software, most of them releasing patches to the original code through the Internet. \end_layout \begin_layout Standard The following people have contributed in some way: \end_layout \begin_layout Quotation Vera Albrecht, \end_layout \begin_layout Quotation Cecil Aswell, \end_layout \begin_layout Quotation Giles Atkinson, \end_layout \begin_layout Quotation Giles C. Billingsley, \end_layout \begin_layout Quotation Phil Barker, \end_layout \begin_layout Quotation Steven Borley, \end_layout \begin_layout Quotation Stuart Brorson, \end_layout \begin_layout Quotation Alessio Cacciatori, \end_layout \begin_layout Quotation Mansun Chan, \end_layout \begin_layout Quotation Wayne A. Christopher, \end_layout \begin_layout Quotation Al Davis, \end_layout \begin_layout Quotation Glao S. Dezai, \end_layout \begin_layout Quotation Jon Engelbert, \end_layout \begin_layout Quotation Daniele Foci, \end_layout \begin_layout Quotation Noah Friedman, \end_layout \begin_layout Quotation David A. Gates, \end_layout \begin_layout Quotation Alan Gillespie, \end_layout \begin_layout Quotation John Heidemann, \end_layout \begin_layout Quotation Marcel Hendrix, \end_layout \begin_layout Quotation Seth Hillebrand, \end_layout \begin_layout Quotation Jeffrey M. Hsu, \end_layout \begin_layout Quotation JianHui Huang, \end_layout \begin_layout Quotation S. Hwang, \end_layout \begin_layout Quotation Chris Inbody, \end_layout \begin_layout Quotation Gordon M. Jacobs, \end_layout \begin_layout Quotation Min-Chie Jeng, \end_layout \begin_layout Quotation Beorn Johnson, \end_layout \begin_layout Quotation Stefan Jones, \end_layout \begin_layout Quotation Kenneth H. Keller, \end_layout \begin_layout Quotation Francesco Lannutti, \end_layout \begin_layout Quotation Robert Larice, \end_layout \begin_layout Quotation Mathew Lew, \end_layout \begin_layout Quotation Robert Lindsell, \end_layout \begin_layout Quotation Weidong Liu, \end_layout \begin_layout Quotation Kartikeya Mayaram, \end_layout \begin_layout Quotation Richard D. McRoberts, \end_layout \begin_layout Quotation Manfred Metzger, \end_layout \begin_layout Quotation Jim Monte, \end_layout \begin_layout Quotation Wolfgang Muees, \end_layout \begin_layout Quotation Paolo Nenzi, \end_layout \begin_layout Quotation Gary W. Ng, \end_layout \begin_layout Quotation Hong June Park, \end_layout \begin_layout Quotation Stefano Perticaroli, \end_layout \begin_layout Quotation Arno Peters, \end_layout \begin_layout Quotation Serban-Mihai Popescu, \end_layout \begin_layout Quotation Georg Post, \end_layout \begin_layout Quotation Thomas L. Quarles, \end_layout \begin_layout Quotation Emmanuel Rouat, \end_layout \begin_layout Quotation Jean-Marc Routure, \end_layout \begin_layout Quotation Jaijeet S. Roychowdhury, \end_layout \begin_layout Quotation Lionel Sainte Cluque, \end_layout \begin_layout Quotation Takayasu Sakurai, \end_layout \begin_layout Quotation Amakawa Shuhei, \end_layout \begin_layout Quotation Kanwar Jit Singh, \end_layout \begin_layout Quotation Bill Swartz, \end_layout \begin_layout Quotation Hitoshi Tanaka, \end_layout \begin_layout Quotation Brian Taylor, \end_layout \begin_layout Quotation Steve Tell, \end_layout \begin_layout Quotation Linus Torvalds, \end_layout \begin_layout Quotation Andrew Tuckey, \end_layout \begin_layout Quotation Andreas Unger, \end_layout \begin_layout Quotation Holger Vogt, \end_layout \begin_layout Quotation Dietmar Warning, \end_layout \begin_layout Quotation Michael Widlok, \end_layout \begin_layout Quotation Charles D.H. Williams, \end_layout \begin_layout Quotation Antony Wilson, \end_layout \begin_layout Standard and many others... \end_layout \begin_layout Standard If someone helped in the development and has not been inserted in this list then this omission was unintentional. If you feel you should be on this list then please write to < \begin_inset CommandInset href LatexCommand href target "ngspice-devel@lists.sourceforge.net" type "mailto:" literal "false" \end_inset >. Do not be shy, we would like to make a list as complete as possible. \end_layout \begin_layout Chapter Introduction \end_layout \begin_layout Standard Ngspice is a general-purpose circuit simulation program for nonlinear and linear analyses. Circuits may contain resistors, capacitors, inductors, mutual inductors, independent or dependent voltage and current sources, loss-less and lossy transmission lines, switches, uniform distributed RC lines, and the five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs, and MOSFETs. \end_layout \begin_layout Standard The most common way to use Ngspice is to start it from the OS command prompt, passing the name of a netlist file: one containing the definition of a circuit. The largest part of this manual is the description of such files. For a full description of starting options see Chapter \begin_inset CommandInset ref LatexCommand ref reference "chap:Starting-ngspice" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . Input files may also contain scripts written in Ngspice's command language \begin_inset CommandInset ref LatexCommand eqref reference "chap:Interactive-Interpreter" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . Interactive user interfaces are described in Chapter \begin_inset CommandInset ref LatexCommand ref reference "chap:Ngspice-User-Interfaces" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . \end_layout \begin_layout Standard Some introductory remarks on how to use ngspice may be found in Chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Example-Circuits" nolink "false" \end_inset . \end_layout \begin_layout Standard Ngspice is an update of Spice3f5, the last Berkeley's release of Spice3 simulator family. Ngspice is being developed to include new features to existing Spice3f5 and to fix its bugs. Improving a complex software like a circuit simulator is a very hard task and, while some improvements have been made, most of the work has been done on bug fixing and code refactoring. \end_layout \begin_layout Standard Ngspice has built-in models for the semiconductor devices, and the user need specify only the pertinent model parameter values. \end_layout \begin_layout Standard Ngspice supports mixed-level simulation and provides a direct link between technology parameters and circuit performance. A mixed-level circuit and device simulator can provide greater simulation accuracy than a stand-alone circuit or device simulator by numerically modeling the critical devices in a circuit. Compact models can be used for all other devices. The mixed-level extensions to ngspice is CIDER, a mixed-level circuit and device simulator integrated into ngspice code. \end_layout \begin_layout Standard Ngspice supports mixed-signal simulation through the integration of XSPICE code. XSPICE software, developed as an extension to Spice3C1 by GeorgiaTech, has been enhanced and ported to ngspice to provide `board' level and mixed-signal simulation. Digital Verilog modules, compiled with Verilator or Icarus Verilog, can be attached. Communication with (C coded) processes via pipes may be established. \end_layout \begin_layout Standard The XSPICE extension enables pure digital simulation as well. \end_layout \begin_layout Standard New devices can be added to ngspice by several means: behavioral B-, E- or G-sources, the XSPICE code-model interface for C-like device coding, and Verilog-A models, when compiled with OpenVAF, via the OSDI interface. \end_layout \begin_layout Standard Finally, numerous small bugs have been discovered and fixed, and the program has been ported to a wider variety of computing platforms. \end_layout \begin_layout Section Simulation Algorithms \end_layout \begin_layout Standard Computer-based circuit simulation is often used as a tool by designers, test engineers, and others who want to analyze the operation of a design without examining the physical circuit. Simulation allows you to change quickly the parameters of many of the circuit elements to determine how they affect the circuit response. Often it is difficult or impossible to change these parameters in a physical circuit. \end_layout \begin_layout Standard However, to be practical, a simulator must execute in a reasonable amount of time. The key to efficient execution is choosing the proper level of modeling abstraction for a given problem. To support a given modeling abstraction, the simulator must provide appropriate algorithms. \end_layout \begin_layout Standard Historically, circuit simulators have supported either an analog simulation algorithm or a digital simulation algorithm. Ngspice inherits the XSPICE framework and supports both analog and digital algorithms and is a `mixed-mode' simulator. \end_layout \begin_layout Subsection Analog Simulation \end_layout \begin_layout Standard Analog simulation focuses on the linear and non-linear behavior of a circuit over a continuous time or frequency interval. The circuit response is obtained by iteratively solving Kirchhoff's Laws for the circuit at time steps selected to ensure the solution has converged to a stable value and that numerical approximations of integrations are sufficiently accurate. Since Kirchhoff's laws form a set of simultaneous equations, the simulator operates by solving a matrix of equations at each time point. This matrix processing generally results in slower simulation times when compared to digital circuit simulators. \end_layout \begin_layout Standard The response of a circuit is a function of the applied sources. Ngspice offers a variety of source types including DC, sine-wave, and pulse. In addition to specifying sources, the user must define the type of simulation to be run. This is termed the `mode of analysis'. Analysis modes include DC analysis, AC analysis, and transient analysis. For DC analysis, the time-varying behavior of reactive elements is neglected and the simulator calculates the DC solution of the circuit. Swept DC analysis may also be accomplished with ngspice. This is simply the repeated application of DC analysis over a range of DC levels for the input sources. For AC analysis, the simulator determines the response of the circuit, including reactive elements to small-signal sinusoidal inputs over a range of frequencies. The simulator output in this case includes amplitudes and phases as a function of frequency. For transient analysis, the circuit response, including reactive elements, is analyzed to calculate the behavior of the circuit as a function of time. \end_layout \begin_layout Subsection Matrix solvers \end_layout \begin_layout Standard Since version 42 ngspice offers two matrix solvers. Spice3f5 originally has used the solver Sparse 1.3, which has proven to be robust for all simulation tasks \begin_inset CommandInset citation LatexCommand cite key "key-26" literal "false" \end_inset . It is especially suited for simulating behavioral models. Optionally, to speed up the simulation of large circuits with thousands of transistors, the KLU matrix solver \begin_inset CommandInset citation LatexCommand cite key "key-27,key-28" literal "false" \end_inset may be selected (see chapter \begin_inset CommandInset ref LatexCommand ref reference "subsec:General-Options" nolink "false" \end_inset ). \end_layout \begin_layout Subsection Device Models for Analog Simulation \end_layout \begin_layout Standard There are three models for bipolar junction transistors, all based on the integral-charge model of Gummel and Poon; however, if the Gummel-Poon parameters are not specified, the basic model (BJT) reduces to the simpler Ebers-Moll model. In either case and in either model, charge storage effects, ohmic resistances, and a current-dependent output conductance may be included. The second bipolar model BJT2 adds dc current computation in the substrate diode. The third model (VBIC) contains further enhancements for advanced bipolar devices. \end_layout \begin_layout Standard The semiconductor diode model can be used for either junction diodes or Schottky barrier diodes. There are two models for JFET: the first (JFET) is based on the model of Shichman and Hodges, the second (JFET2) is based on the Parker-Skellern model. All the original six MOSFET models are implemented: MOS1 is described by a square-law I-V characteristic, MOS2 \begin_inset CommandInset citation LatexCommand cite key "key-28" literal "false" \end_inset is an analytical model, while MOS3 \begin_inset CommandInset citation LatexCommand cite key "key-28" literal "false" \end_inset is a semi-empirical model; MOS6 \begin_inset CommandInset citation LatexCommand cite key "key-2" literal "false" \end_inset is a simple analytic model accurate in the short channel region; MOS9, is a slightly modified Level 3 MOSFET model - not to confuse with Philips level 9; BSIM 1 \begin_inset CommandInset citation LatexCommand cite key "key-3,key-4" literal "false" \end_inset ; BSIM2 \begin_inset CommandInset citation LatexCommand cite key "key-5" literal "false" \end_inset are the old BSIM (Berkeley Short-channel IGFET Model) models. MOS2, MOS3, and BSIM include second-order effects such as channel-length modulation, subthreshold conduction, scattering-limited velocity saturation, small-size effects, and charge controlled capacitances. The recent MOS models for submicron devices are the BSIM3 ( \begin_inset CommandInset href LatexCommand href name "Berkeley BSIM3 web page" target "http://bsim.berkeley.edu/models/bsim3/" literal "false" \end_inset ) and BSIM4 ( \begin_inset CommandInset href LatexCommand href name "Berkeley BSIM4 web page" target "http://bsim.berkeley.edu/models/bsim4/" literal "false" \end_inset ) models. Silicon-on-insulator MOS transistors are described by the SOI models from the BSIMSOI family ( \begin_inset CommandInset href LatexCommand href name "Berkeley BSIMSOI web page" target "http://bsim.berkeley.edu/models/bsimsoi/" literal "false" \end_inset ) and the STAG \begin_inset CommandInset citation LatexCommand cite key "key-18" literal "false" \end_inset model. There is some support for a couple of HFET models and one model for MESA devices. Verilog-A models are made available via the OpenVAF/OSDI interface (see chapter \begin_inset CommandInset ref LatexCommand ref reference "chap:Verilog-A-Compact-Device" nolink "false" \end_inset ). \end_layout \begin_layout Subsection Digital Simulation \end_layout \begin_layout Standard Digital circuit simulation differs from analog circuit simulation in several respects. A primary difference is that a solution of Kirchhoff's laws is not required. Instead, the simulator must only determine whether a change in the logic state of a node has occurred and propagate this change to connected elements. Such a change is called an `event'. \end_layout \begin_layout Standard When an event occurs, the simulator examines only those circuit elements that are affected by the event. As a result, matrix analysis is not required in digital simulators. By comparison, analog simulators must iteratively solve for the behavior of the entire circuit because of the forward and reverse transmission properties of analog components. This difference results in a considerable computational advantage for digital circuit simulators, which is reflected in the significantly greater speed of digital simulations. \end_layout \begin_layout Subsection Mixed-Signal Simulation \end_layout \begin_layout Standard Modern circuits often contain a mix of analog and digital circuits. To simulate such circuits efficiently and accurately, a mix of analog and digital simulation techniques is required. When analog simulation algorithms are combined with digital simulation algorithms, the result is termed `mixed-mode simulation'. \end_layout \begin_layout Standard Two basic methods of implementing mixed-mode simulation used in practice are the `native mode' and `glued mode' approaches. Native mode simulators implement both an analog algorithm and a digital algorithm in the same executable. Glued mode simulators actually use two simulators, one of which is analog and the other digital. This type of simulator must define an input/output protocol so that the two executables can communicate with each other effectively. The communication constraints tend to reduce the speed, and sometimes the accuracy, of the complete simulator. On the other hand, the use of a glued mode simulator allows the component models developed for the separate executables to be used without modification. \end_layout \begin_layout Standard Ngspice is a native mode simulator providing both analog and event-based simulation in the same executable. The underlying algorithms of ngspice (coming from XSPICE and its Code Model Subsystem) allow use of all the standard SPICE models, provide a pre-defined collection of the most common analog and digital functions, and provide an extensible base on which to build additional models. \end_layout \begin_layout Subsubsection User-Defined Nodes \end_layout \begin_layout Standard Ngspice supports creation of `User-Defined Node' types. User-Defined Node types allow you to specify nodes that propagate data other than voltages, currents, and digital states. Like digital nodes, User-Defined Nodes use event-driven simulation, but the state value may be an arbitrary data type. A simple example application of User-Defined Nodes is the simulation of a digital signal processing filter algorithm. In this application, each node could assume a real or integer value. More complex applications may define types that involve complex data such as digital data vectors or even non-electronic data. \end_layout \begin_layout Standard Ngspice digital simulation is actually implemented as a special case of this User-Defined Node capability where the digital state is defined by a data structure that holds a Boolean logic state and a strength value. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Mixed-Level-Simulation-(Electron" \end_inset Mixed-Level Simulation (Electronic and TCAD) \end_layout \begin_layout Standard Ngspice implements mixed-level simulation through the merging of its code with CIDER (details see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:CIDER-User’s-Manual" nolink "false" \end_inset ). \end_layout \begin_layout Standard CIDER is a mixed-level circuit and device simulator that provides a direct link between technology parameters and circuit performance. A mixed-level circuit and device simulator can provide greater simulation accuracy than a stand-alone circuit or device simulator by numerically modeling the critical devices in a circuit. Compact models can be used for noncritical devices. \end_layout \begin_layout Standard CIDER couples ngspice to a internal C-based device simulator, thus providing circuit analyses, compact models for semiconductor devices, and an interactive user interface. CIDER provides accurate, one- and two-dimensional numerical device models based on the solution of Poisson's equation, and the electron and hole current-continuity equations. CIDER incorporates many of the same basic physical models found in the the Stanford two-dimensional device simulator PISCES [PINT85]. Input to CIDER consists of a SPICE-like description of the circuit and its compact models, and PISCES-like descriptions of the structures of numerically modeled devices. As a result, CIDER should seem familiar to designers already accustomed to these two tools. \end_layout \begin_layout Standard The CIDER input format has great flexibility and allows increased access to physical model parameters. New physical models have been added to allow simulation of state-of-the-art devices. These include transverse field mobility degradation [GATE90] that is important in scaled-down MOSFETs and a polysilicon model for poly-emitter bipolar transistors. Temperature dependence has been included for most physical models over the range from -50°C to 150°C. The numerical models can be used to simulate all the basic types of semiconductor devices: resistors, MOS capacitors, diodes, BJTs, JFETs and MOSFETs. BJTs and JFETs can be modeled with or without a substrate contact. Support has been added for the management of device internal states. Post-processing of device states can be performed using the control language user interface of ngspice. Previously computed states can be loaded into the program to provide accurate initial guesses for subsequent analyses. \end_layout \begin_layout Standard Details of the basic semiconductor equations and the physical models used by CIDER are not provided in this manual. Unfortunately, no other single source exists that describes all of the relevant background material. Comprehensive reviews of device simulation can be found in [PINT90] and the book [SELB84]. CODECS (predecessor to CIDER) and its inversion-layer mobility model are described in [MAYA88] and [LGATE90], respectively. PISCES and its models are described in [PINT85]. Temperature dependencies for the PISCES models used by CIDER are available in [SOLL90]. \end_layout \begin_layout Standard For Linux users the cooperation of the TCAD software GSS with ngspice might be of interest, see \begin_inset CommandInset href LatexCommand href target "https://ngspice.sourceforge.io/gss.html" literal "false" \end_inset . This project is no longer maintained however, but has moved into the Genius simulator, still available as open source \begin_inset CommandInset href LatexCommand href name "cogenda genius" target "http://www.cogenda.com/article/download" literal "false" \end_inset . \end_layout \begin_layout Section Supported Analyses \end_layout \begin_layout Standard The ngspice simulator supports the following different types of analysis: \end_layout \begin_layout Enumerate DC Analysis (Operating Point and DC Sweep) ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.DC:-DC-Transfer" plural "false" caps "false" noprefix "false" nolink "false" \end_inset and \begin_inset CommandInset ref LatexCommand ref reference "subsec:.OP:-Operating-Point" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) \end_layout \begin_layout Enumerate AC Small-Signal Analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.AC:-Small-Signal-AC" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) \end_layout \begin_layout Enumerate Transient Analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.TRAN:-Transient-Analysis" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) \end_layout \begin_layout Enumerate Pole-Zero Analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.PZ:-Pole-Zero-Analysis" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) \end_layout \begin_layout Enumerate Small-Signal Distortion Analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.DISTO:-Distortion-Analysis" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) \end_layout \begin_layout Enumerate Sensitivity Analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.SENS" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) \end_layout \begin_layout Enumerate Noise Analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.NOISE:-Noise-Analysis" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) \end_layout \begin_layout Standard The different types of analysis are described below, the cross-references above are to the netlist directives used to request them. Applications that are exclusively analog can make use of all analysis modes with the exception of the Code Model subsystem that does not implement Pole-Zero, Distortion, Sensitivity and Noise analyses. Event-driven applications that include digital and User-Defined Node types may make use of DC (operating point and DC sweep) and Transient only. \end_layout \begin_layout Standard In order to understand the relationship between the different analyses and the two underlying simulation algorithms of ngspice, it is important to understand what is meant by each analysis type. This is detailed below. \end_layout \begin_layout Subsection DC Analysis \end_layout \begin_layout Standard The DC analysis portion of ngspice determines the dc operating point of the circuit with inductors shorted and capacitors opened. DC analysis options are specified on the \family typewriter .DC \family default , \family typewriter .TF \family default , and \family typewriter .OP \family default control lines. \end_layout \begin_layout Standard DC analysis does not consider any time dependence on any of the sources within the system description. The simulator algorithm subdivides the circuit into those portions that require the analog simulator algorithm and those that require the event-driven algorithm. Each subsystem block is then iterated to solution, with the interfaces between analog nodes and event-driven nodes iterated for consistency across the entire system. \end_layout \begin_layout Standard Once stable values are obtained for all nodes in the system, the analysis halts and the results may be displayed or printed out as you request them. \end_layout \begin_layout Standard A dc analysis is automatically performed prior to a transient analysis to determine the transient initial conditions, and prior to an ac small-signal analysis to determine the linearized, small-signal models for nonlinear devices. If requested, the DC small-signal value of a transfer function (ratio of output variable to input source), input resistance, and output resistance is also computed as a part of the DC solution. DC analysis can also be used to generate DC transfer curves: a specified independent voltage, current source, resistor or temperature is stepped over a user-specified range and the DC output variables are stored for each sequential source value. \end_layout \begin_layout Subsection AC Small-Signal Analysis \end_layout \begin_layout Standard AC analysis is limited to analog nodes and represents the small signal, sinusoidal solution of the analog system described at a particular frequency or set of frequencies. This analysis is similar to the DC analysis in that it represents the steady-state behavior of the described system with a single input node \shape italic at a given set of stimulus frequencies \shape default . \end_layout \begin_layout Standard The program first computes the dc operating point of the circuit and determines linearized, small-signal models for all of the nonlinear devices in the circuit. The resultant linear circuit is then analyzed over a user-specified range of frequencies. The desired output of an ac small-signal analysis is usually a transfer function (voltage gain, transimpedance, etc). If the circuit has only one ac input, it is convenient to set that input to unity and zero phase, so that output variables have the same value as the transfer function of the output variable with respect to the input. \end_layout \begin_layout Subsection Transient Analysis \end_layout \begin_layout Standard Transient analysis is an extension of DC analysis to the time domain. A transient analysis first obtains a DC solution to provide a point of departure for simulating time-varying behavior. Once the DC solution is obtained, the time-dependent aspects of the system are reintroduced, and the two simulator algorithms incrementally solve for the time varying behavior of the entire system. Inconsistencies in node values are resolved by the two simulation algorithms such that the time-dependent waveforms created by the analysis are consistent across the entire simulated time interval. Resulting time-varying descriptions of node behavior for the specified time interval are accessible to you. \end_layout \begin_layout Standard All sources that are not time dependent (for example, power supplies) are set to their dc value. The transient time interval is specified on a \family typewriter .TRAN \family default control line. \end_layout \begin_layout Subsection Pole-Zero Analysis \end_layout \begin_layout Standard Pole-zero analysis in ngspice computes the poles and/or zeros in the small-signal ac transfer function. Ngspice first computes the dc operating point and then determines the linearized, small-signal models for all the nonlinear devices in the circuit. The small-signal circuit model is then used to find the poles and zeros of the transfer function. Two types of transfer functions are allowed: one of the form (output voltage)/(input voltage) and the other of the form (output voltage)/(input current). These two types of transfer functions cover all the cases and one can find the poles/zeros of functions like input/output impedance and voltage gain. The input and output ports are specified as two pairs of nodes. The pole-zero analysis works with resistors, capacitors, inductors, linear-controlled sources, independent sources, BJTs, MOSFETs, JFETs and diodes. Transmission lines are not supported. \end_layout \begin_layout Standard The method used in the analysis is a sub-optimal numerical search. For large circuits it may take a considerable time or fail to find all poles and zeros. Please note, that for some circuits, the method becomes \begin_inset Quotes eld \end_inset lost \begin_inset Quotes erd \end_inset and may find an excessive number of poles or zeros. \end_layout \begin_layout Subsection Small-Signal Distortion Analysis \end_layout \begin_layout Standard Distortion analysis in ngspice computes steady-state harmonic and intermodulation products for small input signal magnitudes. If signals of a single frequency are specified as the input to the circuit, the complex values of the second and third harmonics are determined at every point in the circuit. If there are signals of two frequencies input to the circuit, the analysis finds out the complex values of the circuit variables at the sum and difference of the input frequencies, and at the difference of the smaller frequency from the second harmonic of the larger frequency. Distortion analysis is supported for the following nonlinear devices: \end_layout \begin_layout Itemize Diodes (DIO), \end_layout \begin_layout Itemize BJT, \end_layout \begin_layout Itemize JFET (level 1), \end_layout \begin_layout Itemize MOSFETs (levels 1, 2, 3, 9, and BSIM1), \end_layout \begin_layout Itemize MESFET (level 1). \end_layout \begin_layout Standard All linear devices are automatically supported by distortion analysis. If there are switches present in the circuit, the analysis continues to be accurate provided the switches do not change state under the small excitations used for distortion calculations. \end_layout \begin_layout Standard If a device model does not support direct small signal distortion analysis, please use the Fourier of FFT statements and evaluate the output per scripting. \end_layout \begin_layout Subsection Sensitivity Analysis \end_layout \begin_layout Standard Ngspice can calculate either the DC operating-point sensitivity or the AC small-signal sensitivity of an output variable with respect to all circuit variables, including model parameters. Ngspice calculates the difference in an output variable (either a node voltage or a branch current) by perturbing each parameter of each device independently. Since the method is a numerical approximation, the results may demonstrate second order effects in highly sensitive parameters, or may fail to show very low but non-zero sensitivity. \end_layout \begin_layout Standard Since each variable is perturbed by a small fraction of its value, zero-valued parameters are not analyzed, reducing what is usually a very large amount of data. \end_layout \begin_layout Subsection Noise Analysis \end_layout \begin_layout Standard Noise analysis in ngspice measures the device-generated noise for a given circuit. When provided with an input source and an output port, the analysis calculates the noise contributions of each device, and each noise generator within each device, as measured as a voltage at the output port. Noise analysis also calculates the equivalent input noise of the circuit, based on the output noise. This is done for every frequency point in a specified range - the calculated value of the noise corresponds to the spectral density of the circuit variable viewed as a stationary Gaussian stochastic process. After calculating the spectral densities, noise analysis integrates these values over the specified frequency range to arrive at the total noise voltage and current over this frequency range. The calculated values correspond to the variance of the circuit variables viewed as stationary Gaussian processes. \end_layout \begin_layout Subsection Periodic Steady State Analysis \end_layout \begin_layout Standard \emph on Experimental code. \end_layout \begin_layout Standard PSS is a radio frequency periodical large-signal dedicated analysis. The implementation is based on a time domain shooting method that make use of transient analysis. As it is in early development stage, PSS performs analysis only on autonomous circuits, meaning that it is able to predict fundamental frequency and (harmonic) amplitude(s) for oscillators, VCOs, etc.. The algorithm is based on a search of the minimum error vector defined as the difference of RHS vectors between two occurrences of an estimated period. Convergence is reached when the mean of this error vector decreases below a given threshold parameter. Results of PSS are the basis of periodical large-signal analyses like PAC or PNoise. \end_layout \begin_layout Section Analysis at Different Temperatures \begin_inset Note Note status open \begin_layout Plain Layout Need review \end_layout \end_inset \end_layout \begin_layout Subsection Introduction \end_layout \begin_layout Standard Temperature, in ngspice, is a property associated to the entire circuit, rather than an analysis option. Circuit temperature has a default (nominal) value of 27°C (300.15 K) that can be changed using the \family typewriter \series bold TEMP \family default \series default option in an \family typewriter .option \family default control line (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:General-Options" nolink "false" \end_inset ) or by the \family typewriter .TEMP \family default line (see \begin_inset CommandInset ref LatexCommand ref reference "sec:.temp" nolink "false" \end_inset ), which has precedence over the \family typewriter .option TEMP \family default line. All analyses are, thus, performed at circuit temperature, and if you want to simulate circuit behavior at different temperatures you should prepare a netlist for each temperature. \end_layout \begin_layout Standard All input data for ngspice is assumed to have been measured at the circuit nominal temperature. This value can further be overridden for any device that models temperature effects by specifying the \family typewriter \series bold TNOM \family default \series default parameter on the \family typewriter .model \family default itself. Individual instances may further override the circuit temperature through the specification of \family typewriter \series bold TEMP \family default \series default and \family typewriter \series bold DTEMP \family default \series default parameters on the instance. The two options are not independent even if you can specify both on the instance line, the \family typewriter \series bold TEMP \family default \series default option overrides \family typewriter \series bold DTEMP \family default \series default . The algorithm to compute instance temperature is described below: \end_layout \begin_layout Standard \begin_inset Float algorithm placement H alignment document wide false sideways false status open \begin_layout Plain Layout \begin_inset Box Doublebox position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout IF TEMP is specified THEN \end_layout \begin_layout Plain Layout instance_temperature = TEMP \end_layout \begin_layout Plain Layout ELSE \end_layout \begin_layout Plain Layout instance_temperature = circuit_temperature + DTEMP \end_layout \begin_layout Plain Layout END IF \end_layout \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout Instance temperature computation \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Temperature dependent support is provided for all devices except voltage and current sources (either independent and controlled) and BSIM models. BSIM MOSFETs have an alternate temperature dependency scheme that adjusts all of the model parameters before input to ngspice. \end_layout \begin_layout Standard For details of the BSIM temperature adjustment, see \begin_inset CommandInset citation LatexCommand cite key "key-6" literal "true" \end_inset and \begin_inset CommandInset citation LatexCommand cite key "key-7" literal "true" \end_inset . Temperature appears explicitly in the exponential terms of the BJT and diode model equations. In addition, saturation currents have a built-in temperature dependence. The temperature dependence of the saturation current in the BJT models is determined by: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} I_{S}\left(T_{1}\right)=I_{S}\left(T_{0}\right)\left(\frac{T_{1}}{T_{0}}\right)^{XTI}\exp\left(\frac{E_{g}q\left(T_{1}-T_{0}\right)}{k\left(T_{1}T_{0}\right)}\right) \end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $k$ \end_inset is Boltzmann's constant, \begin_inset Formula $q$ \end_inset is the electronic charge, \begin_inset Formula $E_{g}$ \end_inset is the energy gap model parameter, and \begin_inset Formula $XTI$ \end_inset is the saturation current temperature exponent (also a model parameter, and usually equal to 3). \end_layout \begin_layout Standard The temperature dependence of forward and reverse beta is according to the formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} B\left(T_{1}\right)=B\left(T_{0}\right)\left(\frac{T_{1}}{T_{0}}\right)^{XTB} \end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $T_{0}$ \end_inset and \begin_inset Formula $T_{1}$ \end_inset are in degrees Kelvin, and \begin_inset Formula $XTB$ \end_inset is a user-supplied model parameter. Temperature effects on beta are carried out by appropriate adjustment to the values of \begin_inset Formula $B_{F}$ \end_inset , \begin_inset Formula $I_{SE}$ \end_inset , \begin_inset Formula $B_{R}$ \end_inset , and \begin_inset Formula $I_{SC}$ \end_inset (SPICE model parameters BF, ISE, BR, and ISC, respectively). \end_layout \begin_layout Standard Temperature dependence of the saturation current in the junction diode model is determined by: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} I_{S}\left(T_{1}\right)=I_{S}\left(T_{0}\right)\left(\frac{T_{1}}{T_{0}}\right)^{\frac{XTI}{N}}\exp\left(\frac{E_{g}q\left(T_{1}-T_{0}\right)}{Nk\left(T_{1}T_{0}\right)}\right) \end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $N$ \end_inset is the emission coefficient model parameter, and the other symbols have the same meaning as above. Note that for Schottky barrier diodes, the value of the saturation current temperature exponent, \begin_inset Formula $XTI$ \end_inset , is usually 2. Temperature appears explicitly in the value of junction potential, U (in Ngspice PHI), for all the device models. \end_layout \begin_layout Standard The temperature dependence is determined by: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} U\left(T\right)=\frac{kT}{q}\ln\left(\frac{N_{a}N_{d}}{N_{i}\left(T\right)^{2}}\right) \end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $k$ \end_inset is Boltzmann's constant, \begin_inset Formula $q$ \end_inset is the electronic charge, \begin_inset Formula $N_{a}$ \end_inset is the acceptor impurity density, \begin_inset Formula $N_{d}$ \end_inset is the donor impurity density, \begin_inset Formula $N_{i}$ \end_inset is the intrinsic carrier concentration, and \begin_inset Formula $E_{g}$ \end_inset is the energy gap. Temperature appears explicitly in the value of surface mobility, \begin_inset Formula $M_{0}$ \end_inset (or \begin_inset Formula $U_{0}$ \end_inset ), for the MOSFET model. \end_layout \begin_layout Standard The temperature dependence is determined by: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} M_{0}\left(T\right)=\frac{M_{0}\left(T_{0}\right)}{\left(\frac{T}{T_{0}}\right)^{1.5}} \end{equation} \end_inset \end_layout \begin_layout Standard The effects of temperature on resistors, capacitor and inductors is modeled by the formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} R\left(T\right)=R\left(T_{0}\right)\left[1+TC_{1}\left(T-T_{0}\right)+TC_{2}\left(T-T_{0}\right)^{2}\right]\label{eq:R-Temp-quad} \end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $T$ \end_inset is the circuit temperature, \begin_inset Formula $T_{0}$ \end_inset is the nominal temperature, and \begin_inset Formula $TC_{1}$ \end_inset and \begin_inset Formula $TC_{2}$ \end_inset are the first and second order temperature coefficients. \end_layout \begin_layout Subsection Controlling the temperature \end_layout \begin_layout Standard The default temperature is set to 27 °C. \end_layout \begin_layout LyX-Code .temp 40 \end_layout \begin_layout Standard will set the overall temperature to 40 °C ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.temp" nolink "false" \end_inset ). The command \end_layout \begin_layout LyX-Code .options temp=60 \end_layout \begin_layout Standard will set the overall temperature to 60 °C ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:General-Options" nolink "false" \end_inset ). Both commands are equivalent, however \family typewriter .temp \family default will override \family typewriter .options temp \family default . \end_layout \begin_layout Standard The temperature of an individual device may be determined by the instance parameters \family typewriter temp \family default or \family typewriter dtemp \family default . \end_layout \begin_layout LyX-Code M1 d g s b MOSN temp=35 \end_layout \begin_layout Standard will set the temperature of the specific MOS device to 35 °C. \end_layout \begin_layout LyX-Code M2 d g s b MOSN dtemp=20 \end_layout \begin_layout Standard will set the temperature of device \family typewriter M2 \family default at a delta of 20° above the overall temperature. \end_layout \begin_layout Standard The temperatures thus set are static throughout the simulation. It is possible, however, to sweep the temperature by a command like \end_layout \begin_layout LyX-Code .dc temp 25 49 2 \end_layout \begin_layout Standard starting at 25 °C, stopping at 49 °C with a step of 2° (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:.DC:-DC-Transfer" nolink "false" \end_inset ). \end_layout \begin_layout Standard The current overall temperature may be assessed by the variable \family typewriter TEMPER \family default , which can be used as part of an equation in B sources ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Special-B-Source-Variables" nolink "false" \end_inset ) or behavioral E, G, R, L, C sources (e.g. \begin_inset CommandInset ref LatexCommand ref reference "sec:E-source-(non-linear" nolink "false" \end_inset ). A typical example may look like \end_layout \begin_layout LyX-Code Bt1 1 2 V='5 + TEMPER*TEMPER' \end_layout \begin_layout Standard The nominal temperature, a reference temperature where device model parameters have been measured, is called \family typewriter tnom \family default . \end_layout \begin_layout LyX-Code .options tnom=25 \end_layout \begin_layout Standard will set the nominal temperature for all devices to 25 °C ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:General-Options" nolink "false" \end_inset ). \family typewriter Tnom \family default sometimes may be set as a model parameter in a \family typewriter .model \family default line ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Instance-and-model" nolink "false" \end_inset ), depending on the specific class of devices and its model parameter set. \end_layout \begin_layout Section Convergence \end_layout \begin_layout Standard Ngspice uses the Newton-Raphson algorithm to solve nonlinear equations arising from circuit description. The NR algorithm is interactive and terminates when both of the following conditions hold: \end_layout \begin_layout Enumerate The nonlinear branch currents converge to within a tolerance of 0.1% or 1 picoamp (1.0e-12 Amp), whichever is larger. \end_layout \begin_layout Enumerate The node voltages converge to within a tolerance of 0.1% or 1 microvolt (1.0e-6 Volt), whichever is larger. \end_layout \begin_layout Subsection Voltage convergence criterion \end_layout \begin_layout Standard The algorithm has reached convergence when the difference between the last iteration \begin_inset Formula $k$ \end_inset and the current one ( \begin_inset Formula $k+1)$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \left|v_{n}^{(k+1)}-v_{n}^{(k)}\right|\leq\mathtt{RELTOL}\:v_{n_{max}}+\mathtt{VNTOL}, \end{equation} \end_inset \end_layout \begin_layout Standard where \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} v_{n_{max}}=\max\left(\left|v_{n}^{(k+1)}\right|,\left|v_{n}^{(k)}\right|\right). \end{equation} \end_inset \end_layout \begin_layout Standard The \family typewriter RELTOL \family default (RELative TOLerance) parameter, which default value is \begin_inset Formula $10^{-3}$ \end_inset , specifies how small the solution update must be, relative to the node voltage, to consider the solution to have converged. The \family typewriter VNTOL \family default (absolute convergence) parameter, which has \begin_inset Formula $1\mu V$ \end_inset as default value, becomes important when node voltages have near zero values. The relative parameter alone, in such case, would need too strict tolerances, perhaps lower than computer round-off error, and thus convergence would never be achieved. \family typewriter VNTOL \family default forces the algorithm to consider as converged any node whose solution update is lower than its value. \end_layout \begin_layout Subsection Current convergence criterion \end_layout \begin_layout Standard Ngspice checks the convergence on the non-linear functions that describe the non-linear branches in circuit elements. In semiconductor devices the functions defines currents through the device and thus the name of the criterion. \end_layout \begin_layout Standard Ngspice computes the difference between the value of the nonlinear function computed for the last voltage and the linear approximation of the same current computed with the actual voltage \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \left|\widehat{i_{branch}^{(k+1)}}-i_{branch}^{(k)}\right|\leq\mathtt{RELTOL}\:i_{br_{max}}+\mathtt{ABSTOL}, \end{equation} \end_inset \end_layout \begin_layout Standard where \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} i_{br_{max}}=\max\left(\widehat{i_{branch}^{(k+1)}},i_{branch}^{(k)}\right). \end{equation} \end_inset \end_layout \begin_layout Standard In the two expressions above, the \begin_inset Formula $\widehat{i_{branch}}$ \end_inset indicates the linear approximation of the current. \end_layout \begin_layout Subsection Convergence failure \end_layout \begin_layout Standard Although the algorithm used in ngspice has been found to be very reliable, in some cases it fails to converge to a solution. When this failure occurs, the program terminates the job. Failure to converge in dc analysis is usually due to an error in specifying circuit connections, element values, or model parameter values. Regenerative switching circuits or circuits with positive feedback probably will not converge in the dc analysis unless the \family typewriter \series bold OFF \family default \series default option is used for some of the devices in the feedback path, \family typewriter .nodeset \family default control line is used to force the circuit to converge to the desired state. \end_layout \begin_layout Chapter Circuit Description \end_layout \begin_layout Section General Structure and Conventions \end_layout \begin_layout Subsection Input file structure \begin_inset Index idx range none pageformat default status collapsed \begin_layout Plain Layout Netlists \end_layout \end_inset \end_layout \begin_layout Standard The circuit to be analyzed is described to ngspice by a set of element instance lines, which define the circuit topology and element instance values, and a set of control lines, which define the model parameters and the run controls. All lines are assembled in an input file to be read by ngspice. Two lines are essential: \end_layout \begin_layout Itemize The first line in the input file must be the title, which is the only comment line that does not need any special character in the first place. \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Netlists ! title line \end_layout \end_inset \end_layout \begin_layout Itemize The last line must be \family typewriter .end \family default , plus a newline delimiter. \end_layout \begin_layout Standard The order of the remaining lines is alomost arbitrary (except, of course, that continuation lines must immediately follow the line being continued, \family typewriter .subckt \family default ... \family typewriter .ends \family default , \family typewriter .if \family default ... \family typewriter .endif \family default , or \family typewriter .control \family default ... \family typewriter .endc \family default have to enclose their specific lines). Leading white spaces in a line are ignored, as well as empty lines. \end_layout \begin_layout Standard The lines described in sections 2.1 to 2.12 are typically used in the core of the input file, outside of a \family typewriter .control \family default section (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Interactive-mode-with" nolink "false" \end_inset ). An exception is the \family typewriter .include includefile \family default line ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.INCLUDE" nolink "false" \end_inset ) that may be placed anywhere in the input file. The contents of \family typewriter includefile \family default will be inserted exactly in place of the \family typewriter .include \family default line. \end_layout \begin_layout Subsection Syntax check \end_layout \begin_layout Standard A very preliminary syntax check has been added to the input parser. \end_layout \begin_layout Subsubsection Valid utf-8 characters \end_layout \begin_layout Standard The input file will be scanned for valid utf-8 characters. If non-valid characters are found, reading the input is stopped. \end_layout \begin_layout Subsubsection Special characters leading a line \end_layout \begin_layout Standard If the first character in a netlist or .control line is one of =[]?()&%$§ \backslash "!:, then ngspice replaces it by '*' and issues a warning. Command \family typewriter set strict_errorhandling \family default will force ngspice to exit. \end_layout \begin_layout Subsubsection Dot command couple completion \end_layout \begin_layout Standard Check for \family typewriter .control ... .endc \family default , \family typewriter .subckt ... .ends \family default , \family typewriter .if ... .endif \family default . \end_layout \begin_layout Subsection Some naming conventions \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Netlists ! syntax conventions \end_layout \end_inset \end_layout \begin_layout Subsubsection Lines \end_layout \begin_layout Standard Fields on a line are separated by one or more blanks, a comma, an equal ( \family typewriter = \family default ) sign, or a left or right parenthesis; extra spaces are ignored. A line may be continued by entering a ` \family typewriter + \family default ' (plus) in column 1 of the following line; ngspice continues reading beginning with column 2. Lines may also be continued in Unix shell style, when the final two characters are backslashes. A device name field must begin with a letter (A through Z) and cannot contain any delimiters. \end_layout \begin_layout Subsubsection Numbers \end_layout \begin_layout Standard A number field may be an integer field (12, -44), a floating point field (3.14159), either an integer or floating point number followed by an integer exponent (1e-14, 2.65e3), or either an integer or a floating point number followed by one of the following scale factors: \end_layout \begin_layout Standard \begin_inset Float table placement H alignment document wide false sideways false status open \begin_layout Plain Layout \align center \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Suffix \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout T \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Tera \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{12}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout G \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Giga \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{9}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Meg \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mega \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{6}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout K \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Kilo \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{3}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout mil \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mil \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $25.4\times10^{-6}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout m \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout milli \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{-3}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout u \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout micro \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{-6}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout n \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout nano \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{-9}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout p \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout pico \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{-12}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout f \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout femto \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{-15}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout a \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout atto \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{-18}$ \end_inset \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout Ngspice scale factors \end_layout \end_inset \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \begin_layout Subsubsection Letters following a number \end_layout \begin_layout Standard Letters immediately following a number that are not scale factors are ignored, and letters immediately following a scale factor are ignored. Hence, 10, 10V, 10Volts, and 10Hz all represent the same number, and M, MA, MSec, and MMhos all represent the same scale factor. Note that 1000, 1000.0, 1000Hz, 1e3, 1.0e3, 1kHz, and 1k all represent the same number. Note that \emph on `M' \emph default or \emph on `m' \emph default denote `milli', i.e. \begin_inset Formula $10^{-3}$ \end_inset . Suffix \emph on meg \emph default has to be used for \family roman \series medium \shape up \size normal \emph off \bar no \strikeout off \uuline off \uwave off \noun off \color none \begin_inset Formula $10^{6}$ \end_inset . If compatibility mode LT ( \family default \series default \shape default \size default \emph default \bar default \strikeout default \uuline default \uwave default \noun default \color inherit \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode-1-1" nolink "false" \end_inset ) is set, ngspice will accept the RKM notation for entering resistance or capacitance values, e.g. 2K7 or 100R. \end_layout \begin_layout Subsubsection Node names \end_layout \begin_layout Standard Node names may be arbitrary character strings (exceptions see below) and are case insensitive, if ngspice is used in batch mode ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Batch-mode" nolink "false" \end_inset ). If in interactive ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Interactive-mode" nolink "false" \end_inset ) or control ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Interactive-mode-with" nolink "false" \end_inset ) mode, node names may either be plain numbers or arbitrary character strings, \series bold not \series default starting with a number. The following characters = % ( ) , [ ] < > ~ are not allowed in a node name, especially when XSPICE code models are used (they have their special meanings then and act as string delimiters). \end_layout \begin_layout Subsubsection Ground node \end_layout \begin_layout Standard The ground node must be named ` \family typewriter \series medium 0 \family default \series default ' (zero). For compatibility reason \family typewriter gnd \family default is accepted as ground node, and will internally be treated as a global node and be converted to ` \family typewriter \series medium 0 \family default \series default '. If this is not feasible, you may switch the conversion off by setting \family typewriter set no_auto_gnd \family default in one of the configuration files spinit or .spiceinit. \emph on Each circuit has to have a ground node (gnd or 0)! \emph default Note the difference in ngspice where the nodes are treated as character strings and not evaluated as numbers, thus ` \family typewriter \series medium 0 \family default \series default ' and \family typewriter 00 \family default are distinct nodes in ngspice but not in SPICE2. \end_layout \begin_layout Subsection Topological constraints \end_layout \begin_layout Standard Ngspice requires that the following topological constraints are satisfied: \end_layout \begin_layout Itemize The circuit cannot contain a loop of voltage sources and/or inductors and cannot contain a cut-set of current sources and/or capacitors. \end_layout \begin_layout Itemize Each node in the circuit must have a dc path to ground. \end_layout \begin_layout Itemize Every node must have at least two connections except for transmission line nodes (to permit unterminated transmission lines) and MOSFET substrate nodes (which have two internal connections anyway). \end_layout \begin_layout Section Dot \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Dot commands \end_layout \end_inset \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Netlists ! dot commands \end_layout \end_inset commands \end_layout \begin_layout Standard This section summarizes all dot commands available in ngspice, with links to their detailed presentation, in alphabetical order. Control section (or interactive) commands are listed and explained in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" nolink "false" \end_inset . \end_layout \begin_layout Description \family typewriter .AC \family default start an ac simulation ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.AC:-Small-Signal-AC" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .CONTROL \family default start a .control section ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Interactive-mode-with" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .CSPARAM \family default define parameter(s) made available in a control section ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.csparam" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .DC \family default start a dc simulation ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.DC:-DC-Transfer" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .DISTO \family default start a distortion analysis simulation ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.DISTO:-Distortion-Analysis" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .ELSE \family default conditional branching in the netlist ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.IF-Condition-Controlled-Netlist" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .ELSEIF \family default conditional branching in the netlist ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.IF-Condition-Controlled-Netlist" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .END \family default end of the netlist ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.END-Line" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .ENDC \family default end of the .control section ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Interactive-mode-with" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .ENDIF \family default conditional branching in the netlist ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.IF-Condition-Controlled-Netlist" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .ENDS \family default end of subcircuit definition ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.ENDS-Line" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .FOUR \family default Fourier analysis of transient simulation output ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.FOUR:-Fourier-Analysis" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .FUNC \family default define a function ( \begin_inset CommandInset ref LatexCommand ref reference "sec:func" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .GLOBAL \family default define global nodes ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.GLOBAL" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .IC \family default set initial conditions ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.IC:-Set-Initial" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .IF \family default conditional branching in the netlist ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.IF-Condition-Controlled-Netlist" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .INCLUDE \family default include part of the netlist ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.INCLUDE" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .INCPSLT \family default include part of the netlist with compatibility mode \family typewriter 'pslt' \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.INCPSLT-1" nolink "false" \end_inset , \begin_inset CommandInset ref LatexCommand ref reference "subsec:.incpslt" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .LIB \family default include a library ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.LIB" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .MEAS \family default measurements during the simulation ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.MEAS" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .MODEL \family default list of device model parameters ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Device-Models" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .NODESET \family default set initial conditions ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.NODESET" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .NOISE \family default start a noise simulation ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.NOISE:-Noise-Analysis" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .OP \family default start an operating point simulation ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.OP:-Operating-Point" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .OPTIONS \family default set simulator options ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Simulator-Variables" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .PARAM \family default define parameter(s) ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.PARAM-Parametric-netlists" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .PLOT \family default printer plot during batch simulation ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.PLOT-Lines" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .PRINT \family default tabular listing during batch simulation ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.PRINT-Lines" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .PROBE \family default save device currents, voltages and differential voltages ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.PROBE:-Name-vector(s)" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .PSS \family default start a periodic steady state analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.PSS:-Periodic_Steady_State-Analysis" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .PZ \family default start a pole-zero analysis simulation ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.PZ:-Pole-Zero-Analysis" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .SAVE \family default name simulation result vectors to be saved ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.SAVE-Lines" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .SENS \family default start a sensitivity analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.SENS" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .SNDPARAM \family default provide data for writing a sound file ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.SNDPARAM-.SNDPRINT-Write" \end_inset ). \end_layout \begin_layout Description \family typewriter .SNDPRINT \family default write a sound file ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.SNDPARAM-.SNDPRINT-Write" \end_inset ). \end_layout \begin_layout Description \family typewriter .SP \family default S parameter analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.SP-S-Parameter" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .SUBCKT \family default start of subcircuit definitions ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.SUBCKT-Subcircuits" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .TEMP \family default set the ciruit temperature ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.temp" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .TF \family default start a transfer function analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.TF:-Transfer-Function" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .TITLE \family default title of the netlist ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.TITLE-line" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .TRAN \family default start a transient simulation ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.TRAN:-Transient-Analysis" nolink "false" \end_inset ). \end_layout \begin_layout Description \family typewriter .WIDTH \family default width of printer plot ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.width" nolink "false" \end_inset ). \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "subsec:Circuit-elements-(device" \end_inset Circuit elements \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Netlists ! devices instances \end_layout \end_inset (device instances) \end_layout \begin_layout Standard Each element in the circuit is a device instance specified by an \series bold instance line \series default that contains: \end_layout \begin_layout Itemize the element instance name, \end_layout \begin_layout Itemize the circuit nodes to which the element is connected, \end_layout \begin_layout Itemize and the values of the parameters that determine the electrical characteristics of the element. \end_layout \begin_layout Standard The first letter of the element instance name specifies the element type. The format for the ngspice element types is given in the following manual chapters, e.g. BZZZZ. The tokens \family typewriter XXXXXXX \family default , \family typewriter YYYYYYY \family default , and \family typewriter ZZZZZZZ \family default denote arbitrary alphanumeric strings. \end_layout \begin_layout Standard For example, a resistor instance name must begin with the letter \family typewriter R \family default and can contain one or more characters. Hence, \family typewriter R \family default , \family typewriter R1 \family default , \family typewriter \series bold \series default RSE \family default , \family typewriter ROUT \family default , and \family typewriter R3AC2ZY \family default are valid resistor names. Details of each type of device are supplied in a following section \begin_inset CommandInset ref LatexCommand ref reference "cha:Circuit-Elements-and" nolink "false" \end_inset . Table \begin_inset CommandInset ref LatexCommand ref reference "tab:ngspice-element-types" nolink "false" \end_inset lists the element types available in ngspice, sorted by their first letter. \end_layout \begin_layout Standard \begin_inset Float table placement H alignment document wide false sideways false status open \begin_layout Plain Layout \align center \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout First letter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Element description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Comments, links \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XSPICE code model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "cha:Behavioral-Modeling" nolink "false" \end_inset \begin_inset Newline linebreak \end_inset analog ( \begin_inset CommandInset ref LatexCommand ref reference "sec:XSPICE-Analog-Models" nolink "false" \end_inset ) \begin_inset Newline linebreak \end_inset digital ( \begin_inset CommandInset ref LatexCommand ref reference "sec:XSPICE-Digital-Models" nolink "false" \end_inset ) \begin_inset Newline linebreak \end_inset mixed signal ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Hybrid-Models" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Behavioral (arbitrary) source \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Capacitors" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout D \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "cha:Device Models" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout E \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Voltage-controlled voltage source (VCVS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout linear ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Exxxx:-Linear-Voltage-Controlled" nolink "false" \end_inset ), \begin_inset Newline linebreak \end_inset non-linear ( \begin_inset CommandInset ref LatexCommand ref reference "sec:E-source-(non-linear" nolink "false" \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout F \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Current-controlled current source (CCCs) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout linear ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Fxxxx:-Linear-Current-Controlled" nolink "false" \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout G \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Voltage-controlled current source (VCCS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout linear ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Gxxxx:-Linear-Voltage-Controlled" nolink "false" \end_inset ), \begin_inset Newline linebreak \end_inset non-linear ( \begin_inset CommandInset ref LatexCommand ref reference "sec:G-source-(non-linear" nolink "false" \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout H \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Current-controlled voltage source (CCVS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout linear ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Hxxxx:-Linear-Current-Controlled" nolink "false" \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout I \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Current source \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "sec:Independent-Sources-for" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout J \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Junction field effect transistor (JFET) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "sec:JFETs" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout K \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coupled (Mutual) Inductors \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Coupled-(Mutual)-Inductors" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout L \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Inductor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Inductors" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout M \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Metal oxide field effect transistor (MOSFET) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "sec:MOSFETs" nolink "false" \end_inset \begin_inset Newline linebreak \end_inset BSIM3 ( \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM3-model" nolink "false" \end_inset ) \begin_inset Newline linebreak \end_inset BSIM4 ( \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM4-model" nolink "false" \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Verilog-A Compact Device Models \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "chap:Verilog-A-Compact-Device" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout O \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lossy transmission line \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "sec:Lossy-Transmission-Lines" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout P \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coupled multiconductor line (CPL) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Coupled-Multiconductor-Line" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Q \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bipolar junction transistor (BJT) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "sec:BJTs" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout R \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Resistor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Resistors" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout S \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Switch (voltage-controlled) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Switches" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout T \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lossless transmission line \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "sec:Lossless-Transmission-Lines" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout U \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Uniformly distributed RC line \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "sec:Uniform-Distributed-RC" nolink "false" \end_inset * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout U \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Basic digital building blocks using XSPICE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "chap:Digital-Device-Models" nolink "false" \end_inset * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Voltage source \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "sec:Independent-Sources-for" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout W \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Switch (current-controlled) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Switches" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Subcircuit \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Subcircuit-Calls" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Y \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Single lossy transmission line (TXL) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Single-Lossy-Transmission" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Z \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Metal semiconductor field effect transistor (MESFET) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "sec:MESFETs" nolink "false" \end_inset \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "tab:ngspice-element-types" \end_inset ngspice element types \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard *) For a disambiguation see chapter \begin_inset CommandInset ref LatexCommand ref reference "subsec:URC-transmission-line" nolink "false" \end_inset . \end_layout \begin_layout Section Basic lines \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.TITLE-line" \end_inset .TITLE line \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "basicstyle={\ttfamily}" inline false status open \begin_layout Plain Layout POWER AMPLIFIER CIRCUIT \end_layout \begin_layout Plain Layout * additional lines following \end_layout \begin_layout Plain Layout *... \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout Test of CAM cell \end_layout \begin_layout Plain Layout * additional lines following \end_layout \begin_layout Plain Layout *... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The title line must be the first in the input file. Its contents are printed verbatim as the heading for each section of output. \end_layout \begin_layout Standard As an alternative, you may place a \family typewriter .TITLE \family default line anywhere in your input deck. The first line of your input deck will be overridden by the contents of this line following the .TITLE statement. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout .TITLE line example: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "basicstyle={\ttfamily}" inline false status open \begin_layout Plain Layout ****************************** \end_layout \begin_layout Plain Layout * additional lines following \end_layout \begin_layout Plain Layout *... \end_layout \begin_layout Plain Layout .TITLE Test of CAM cell \end_layout \begin_layout Plain Layout * additional lines following \end_layout \begin_layout Plain Layout *... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard will internally be replaced by \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Internal input deck: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "basicstyle={\ttfamily}" inline false status open \begin_layout Plain Layout Test of CAM cell \end_layout \begin_layout Plain Layout * additional lines following \end_layout \begin_layout Plain Layout *... \end_layout \begin_layout Plain Layout *TITLE Test of CAM cell \end_layout \begin_layout Plain Layout * additional lines following \end_layout \begin_layout Plain Layout *... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.END-Line" \end_inset .END Line \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "basicstyle={\ttfamily}" inline false status open \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .end \family default line must always be the last in the input file. Note that the period is an integral part of the name. \end_layout \begin_layout Subsection Comments \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Netlists ! comments \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "basicstyle={\ttfamily}" inline false status open \begin_layout Plain Layout * \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "basicstyle={\ttfamily}" inline false status open \begin_layout Plain Layout * RF=1K Gain should be 100 \end_layout \begin_layout Plain Layout * Check open-loop gain and phase margin \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The asterisk in the first column indicates that this line is a comment line. Comment lines may be placed anywhere in the circuit description. \end_layout \begin_layout Subsection End-of-line comments \end_layout \begin_layout Standard General Form: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "basicstyle={\ttfamily}" inline false status open \begin_layout Plain Layout $ \end_layout \begin_layout Plain Layout ; \end_layout \end_inset \end_layout \begin_layout Standard Examples: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "basicstyle={\ttfamily}" inline false status open \begin_layout Plain Layout RF2=1K $ Gain should be 100 \end_layout \begin_layout Plain Layout C1=10p ; Check open-loop gain and phase margin \end_layout \begin_layout Plain Layout .param n1=1 //new value \end_layout \end_inset \end_layout \begin_layout Standard ngspice supports comments that begin with double characters ` \family typewriter $ \family default ' (dollar plus space) or ` \family typewriter // \family default '. For readability you should precede each comment character with a space. ngspice will accept the single character ` \family typewriter $ \family default '. \end_layout \begin_layout Standard Please note that the `$' character is not a valid end-of-line comment delimiter, if the PSPICE compatibility mode ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode-1" nolink "false" \end_inset ) has been chosen. Then '$' becomes an ordinary character. \end_layout \begin_layout Subsection Continuation lines \end_layout \begin_layout Standard General Form: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "basicstyle={\ttfamily}" inline false status open \begin_layout Plain Layout \end_layout \begin_layout Plain Layout + ; some comment \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Standard If input lines get overly long, they may be split into two or more lines (e.g. for better readability). Internally they will be merged into a single line. Each follow-up line starts with character '+' plus additional space. Follow-up lines have to follow immediately after each other. End-of-line comments will be ignored. Lines may also be continued by ending the line with two backslashes, as used in Unix shells. The following lines do not allow using continuation lines: \family typewriter .title \family default , \family typewriter .lib \family default , and \family typewriter .include \family default . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Device-Models" \end_inset .MODEL Device Models \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Parameters ! model parameters \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .model mname type(pname1=pval1 pname2=pval2 ... ) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .model MOD1 npn (bf=50 is=1e-13 vbf=50) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Most simple circuit elements typically require only a few parameter values. However, some devices (semiconductor devices in particular) that are included in ngspice require many parameter values. Often, many devices in a circuit are defined by the same set of device model parameters. For these reasons, a set of device model parameters is defined on a separate \family typewriter .model \family default line and assigned a unique model name. The device element lines in ngspice then refer to the model name. \end_layout \begin_layout Standard For these more complex device types, each device element line contains the device name, the nodes the device is connected to, and the device model name. In addition, other optional parameters may be specified for some devices: geometric factors and an initial condition (see the following section on Transistors ( \begin_inset CommandInset ref LatexCommand ref reference "sec:BJTs" nolink "false" \end_inset to \begin_inset CommandInset ref LatexCommand ref reference "sec:MOSFETs" nolink "false" \end_inset ) and Diodes ( \begin_inset CommandInset ref LatexCommand ref reference "cha:Device Models" nolink "false" \end_inset ) for more details). \family typewriter mname \family default in the above is the model name, and type is one of the following fifteen types: \end_layout \begin_layout Standard \begin_inset Float table placement h alignment document wide false sideways false status open \begin_layout Plain Layout \align center \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Code \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Model Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout R \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Semiconductor resistor model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Semiconductor capacitor model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout L \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Inductor model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Voltage controlled switch \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Current controlled switch \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout URC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Uniform distributed RC model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LTRA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lossy transmission line model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout D \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Diode model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NPN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NPN BJT model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PNP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PNP BJT model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NJF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N-channel JFET model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PJF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout P-channel JFET model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NMOS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N-channel MOSFET model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PMOS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout P-channel MOSFET model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NMF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N-channel MESFET model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PMF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout P-channel MESFET model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VDMOS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Power MOS model \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "tab:Ngspice-model-types" \end_inset Ngspice model types \end_layout \end_inset \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \begin_layout Standard Parameter values are defined by appending the parameter name followed by an equal sign and the parameter value. Model parameters that are not given a value are assigned the default values given below for each model type. Models are listed in the section on each device along with the description of device element lines. Model parameters and their default values are given in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Model-and-Device" nolink "false" \end_inset . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:.SUBCKT-Subcircuits" \end_inset .SUBCKT Subcircuits \end_layout \begin_layout Standard Subcircuits consisting of ngspice elements can be defined and used similarly to device models. Subcircuits are the way ngspice implements hierarchical modeling and make circuits with repeated sections easier to represent. During parsing of a SPICE deck, each subcircuit instance is replaced by its definition using text expansion and the hierarchy is not present after input processing. \end_layout \begin_layout Standard The subcircuit is defined in the input deck by a grouping of element cards delimited by the \family typewriter .subckt \family default and the \family typewriter .ends \family default cards (or the keywords defined by the \family typewriter substart \family default and \family typewriter subend \family default options (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset )); the program then automatically inserts the defined group of elements wherever the subcircuit is referenced. Instances of subcircuits within a larger circuit are defined through the use of an instance card that begins with the letter ` \family typewriter X \family default '. A complete example of all three of these cards follows: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * The following is the instance card: \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout xdiv1 10 7 0 vdivide \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * The following are the subcircuit definition cards: \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .subckt vdivide 1 2 3 \end_layout \begin_layout Plain Layout r1 1 2 10K \end_layout \begin_layout Plain Layout r2 2 3 5K \end_layout \begin_layout Plain Layout .ends \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The above specifies a subcircuit with ports numbered `1', `2' and `3': \end_layout \begin_layout Itemize Resistor `R1' is connected from port `1' to port `2', and has value 10 kOhms. \end_layout \begin_layout Itemize Resistor `R2' is connected from port `2' to port `3', and has value 5 kOhms. \end_layout \begin_layout Standard The instance card, when placed in an ngspice deck, will cause subcircuit port `1' to be equated to circuit node `10', while port `2' will be equated to node `7' and port `3' will equated to node ` \family typewriter \series medium 0 \family default \series default '. \end_layout \begin_layout Standard There is no limit on the size or complexity of subcircuits, and subcircuits may contain other subcircuits. An example of subcircuit usage is given in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:MOS-Four-Bit" nolink "false" \end_inset . \end_layout \begin_layout Subsection .SUBCKT Line \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .SUBCKT subnam N1 \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .SUBCKT OPAMP 1 2 3 4 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard A circuit definition is begun with a \family typewriter .SUBCKT \family default line. \family sans subnam \family default is the subcircuit name, and N1, N2, ... are the external nodes, which cannot be zero. The group of element lines that immediately follow the \family typewriter .SUBCKT \family default line define the subcircuit. The last line in a subcircuit definition is the \family typewriter .ENDS \family default line (see below). Control lines may not appear within a subcircuit definition; however, subcircuit definitions may contain anything else, including other subcircuit definitions, device models, and subcircuit calls (see below). Note that any device models or subcircuit definitions included as part of a subcircuit definition are strictly local (i.e., such models and definitions are not known outside the subcircuit definition). Also, any element nodes not included on the \family typewriter .SUBCKT \family default line are strictly local, with the exception of 0 (ground) and any other nodes that have been declared as global. If you use parameters, the \family typewriter .SUBCKT \family default line will be extended (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Subcircuit-parameters" nolink "false" \end_inset ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.ENDS-Line" \end_inset .ENDS Line \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .ENDS \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .ENDS OPAMP \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .ENDS \family default line must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being terminated, but is not checked. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Subcircuit-Calls" \end_inset Subcircuit Calls \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout XYYYYYYY N1 SUBNAM \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout X1 2 4 17 3 1 MULTI \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Subcircuits are used in ngspice by specifying pseudo-elements beginning with the letter X, followed by the circuit nodes to be used in expanding the subcircuit. If you use parameters, the subcircuit call will be modified (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Subcircuit-parameters" nolink "false" \end_inset ). \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:.GLOBAL" \end_inset .GLOBAL \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .GLOBAL nodename1 [ nodename2 ... ] \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .GLOBAL gnd vcc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Nodes defined in the .GLOBAL statement are available to all circuit and subcircuit blocks independently from any circuit hierarchy. After parsing the circuit, these nodes are accessible from top level. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:.INCLUDE" \end_inset .INCLUDE \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .INCLUDE filename \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .INCLUDE /users/spice/common/bsim3-param.mod \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Frequently, portions of circuit descriptions will be reused in several input files, particularly with common models and subcircuits. In any ngspice input file, the \family typewriter .INCLUDE \family default line may be used to copy some other file as if that second file appeared in place of the \family typewriter .INCLUDE \family default line in the original file. \end_layout \begin_layout Standard If the filename is a relative path and the file is not found, it is searched for in the locations given by variable sourcepath \begin_inset CommandInset ref LatexCommand eqref reference "sourcepath" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . There is no restriction on the file name imposed by ngspice beyond those imposed by the local operating system. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:.INCPSLT-1" \end_inset .INCPSLT \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .INCPSLT filename \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .INCPSLT /users/spice/models/OPA1641.lib \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard A special form of including a portion of a netlist: The included part is treated as if its compatibility mode had been set to \family typewriter 'pslt' \family default , even if the main netlist has a different compatibility mode. See also chapter \begin_inset CommandInset ref LatexCommand ref reference "subsec:.incpslt" nolink "false" \end_inset . \end_layout \begin_layout Standard If the filename is a relative path and the file is not found, it is searched for in the locations given by variable sourcepath \begin_inset CommandInset ref LatexCommand eqref reference "sourcepath" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . There is no restriction on the file name imposed by ngspice beyond those imposed by the local operating system. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:.LIB" \end_inset .LIB \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .LIB filename libname \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .LIB /users/spice/common/mosfets.lib mos1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .LIB \family default statement allows including library descriptions into the input file. Inside the *.lib file a library \series bold libname \series default will be selected. The statements of each library inside the *.lib file are enclosed in \family typewriter .LIB libname <...> .ENDL \family default statements. The file is searched for in the same way as for .include. \end_layout \begin_layout Standard If the compatibility mode ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Compatibility" nolink "false" \end_inset ) is set to \family typewriter 'ps' \family default by \family typewriter set ngbehavior=ps \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset ) in \family sans spinit \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" nolink "false" \end_inset ) or \family sans .spiceinit \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" nolink "false" \end_inset ), then a simplified syntax \family typewriter .LIB filename \family default is available: a warning is issued and \family sans filename \family default is simply included as described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:.INCLUDE" nolink "false" \end_inset . \end_layout \begin_layout Section \begin_inset Index idx range none pageformat default status collapsed \begin_layout Plain Layout Parameters ! numparam parameters \end_layout \end_inset \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Parsers for expressions ! parametric netlists, numparam parser \end_layout \end_inset \begin_inset CommandInset label LatexCommand label name "sec:.PARAM-Parametric-netlists" \end_inset .PARAM Parametric netlists \end_layout \begin_layout Standard Ngspice allows for the definition of parametric attributes in the netlists. This is an enhancement of the ngspice front-end that adds arithmetic functionality to the circuit description language. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.param" \end_inset .param line \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .param = = ... \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .param pippo=5 \end_layout \begin_layout Plain Layout .param po=6 pp=7.8 pap={AGAUSS(pippo, 1, 1.67)} \end_layout \begin_layout Plain Layout .param pippp={pippo + pp} \end_layout \begin_layout Plain Layout .param p={pp} \end_layout \begin_layout Plain Layout .param pop='pp+p' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This line assigns numerical values to identifiers. More than one assignment per line is possible using a separating space. Parameter identifier names must begin with an alphabetic character. The other characters must be either alphabetic, a number, or \family typewriter ! # $ % [ ] \family default \family typewriter _ \family default as special characters. The variables \series bold time \series default , \series bold temper \series default , and \series bold hertz \series default (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Syntax-and-usage" nolink "false" \end_inset ) are not valid identifier names. Other restrictions on naming conventions apply as well, see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Reserved-words" nolink "false" \end_inset . \end_layout \begin_layout Standard The \family typewriter .param \family default lines inside subcircuits are copied per call, like any other line. All assignments are executed sequentially through the expanded circuit. Before its first use, a parameter name must have been assigned a value. Expressions defining a parameter should be put within braces \family typewriter {p+p2} \family default , or alternatively within single quotes \family typewriter 'AGAUSS(pippo, 1, 1.67)' \family default . An assignment cannot be self-referential, something like \family typewriter .param pip = 'pip+3' \family default will not work. \end_layout \begin_layout Standard The current ngspice version does not always need quotes or braces in expressions, especially when spaces are used sparingly. However, it is recommended to do so, as the following examples demonstrate. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .param a = 123 * 3 b = sqrt(9) $ doesn't work, a <= 123 \end_layout \begin_layout Plain Layout .param a = '123 * 3' b = sqrt(9) $ ok. \end_layout \begin_layout Plain Layout .param c = a + 123 $ won't work \end_layout \begin_layout Plain Layout .param c = 'a + 123' $ ok. \end_layout \begin_layout Plain Layout .param c = a+123 $ ok. \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Parameters may also have string values, but support is limited. String-valued parameters can be defined by \family typewriter .param \family default and used in the same ways as numeric parameters. The only operation on string values is concatenation and that is possible only in top-level \family typewriter .param \family default assignments. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .param str1= \begin_inset Quotes erd \end_inset first \begin_inset Quotes erd \end_inset str2= \begin_inset Quotes erd \end_inset second \begin_inset Quotes erd \end_inset \end_layout \begin_layout Plain Layout .param both={str1} \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset str2 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Brace-expressions" \end_inset Brace expressions in circuit elements: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout { } \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \end_inset \end_layout \begin_layout Standard These are allowed in \family typewriter .model \family default lines and in device lines. A SPICE number is a floating point number with an optional scaling suffix, immediately glued to the numeric tokens (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Syntax-of-expressions" nolink "false" \end_inset ). Brace expressions ({..}) cannot be used to parameterize node names or parts of names. All identifiers used within an \family typewriter \family default must have known values at the time when the line is evaluated, else an error is flagged. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Subcircuit-parameters" \end_inset Subcircuit parameters \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .subckt node node ... = = ... \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .subckt myfilter in out rval=100k cval=100nF \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold \family default \series default is the name of the subcircuit given by the user. \family typewriter \series bold node \family default \series default is an integer number or an identifier, for one of the external nodes. The first \family typewriter \series bold = \family default \series default introduces an optional section of the line. Each \family typewriter \series bold \family default \series default is a formal parameter, and each \family typewriter \series bold \family default \series default is either a SPICE number or a brace expression. Inside the \family typewriter .subckt \family default ... \family typewriter .ends \family default context, each formal parameter may be used like any identifier that was defined on a \family typewriter .param \family default control line. The \family typewriter \series bold \family default \series default parts are default values of the parameters. \end_layout \begin_layout Standard The syntax of a subcircuit call (invocation) is: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout X node node ... = = ... \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout X1 input output myfilter rval=1k \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Here \family typewriter \series bold \family default \series default is the symbolic name given to that instance of the subcircuit, \family typewriter \series bold \family default \series default is the name of a subcircuit defined beforehand. \family typewriter \series bold node node ... \family default \series default is the list of actual nodes where the subcircuit is connected. \family typewriter \series bold \family default \series default is either a SPICE number or a brace expression \family typewriter \series bold { } \family default \series default . \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Subcircuit example with parameters: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * Param-example \end_layout \begin_layout Plain Layout .param amplitude= 1V \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .subckt myfilter in out rval=100k cval=100nF \end_layout \begin_layout Plain Layout Ra in p1 {2*rval} \end_layout \begin_layout Plain Layout Rb p1 out {2*rval} \end_layout \begin_layout Plain Layout C1 p1 0 {2*cval} \end_layout \begin_layout Plain Layout Ca in p2 {cval} \end_layout \begin_layout Plain Layout Cb p2 out {cval} \end_layout \begin_layout Plain Layout R1 p2 0 {rval} \end_layout \begin_layout Plain Layout .ends myfilter \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout X1 input output myfilter rval=1k cval=1n \end_layout \begin_layout Plain Layout V1 input 0 AC {amplitude} \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Symbol scope \end_layout \begin_layout Standard \emph on All subcircuit and model names are considered global and must be unique. \emph default The \family typewriter .param \family default symbols that are defined outside of any \family typewriter .subckt \family default ... \family typewriter .ends \family default section are global. Inside such a section, the pertaining \family typewriter params: \family default symbols and any \family typewriter .param \family default assignments are considered local: they mask any global identical names, until the \family typewriter .ends \family default line is encountered. You cannot reassign to a global number inside a \family typewriter .subckt \family default , a local copy is created instead. Scope nesting works up to a level of 10. For example, if the main circuit calls A that has a formal parameter xx, A calls B that has a param. xx, and B calls C that also has a formal param. xx, there will be three versions of `xx' in the symbol table but only the most local one - belonging to C - is visible. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Syntax-of-expressions" \end_inset Syntax of expressions \end_layout \begin_layout LyX-Code ( optional parts within [...] ) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout An expression may be one of: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout where is either a spice number or an identifier \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout ( [ , ...] ) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout ( ) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard As expected, atoms, built-in function calls and stuff within parentheses are evaluated before the other operators. The operators are evaluated following a list of precedence close to the one of the C language. For equal precedence binary ops, evaluation goes left to right. Most functions operate on real values only! \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Operator \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Alias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Precedence \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout unary - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter ! \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout unary not \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter ** \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter ^ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout power, like pwr \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout multiply \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter / \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout divide \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter % \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout modulo \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter \backslash \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout integer divide \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter + \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout add \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout subtract \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter == \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout equality \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter != \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter <> \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout non-equal \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter <= \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout less or equal \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter >= \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout greater or equal \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter < \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout less than \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter > \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout greater than \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter && \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout boolean and \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter || \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout boolean or \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter c?x:y \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 8 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ternary operator \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The evaluation of the power functions ** or ^ depends on the compatibility mode ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode" nolink "false" \end_inset ) chosen. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Power function source code implementation: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout compatmode hs: x>0 pow(x, y); x<0 pow(x, round(y)); X=0 0 \end_layout \begin_layout Plain Layout compatmode lt: x>0 pow(x, y); x<0 pow(x, y) \end_layout \begin_layout Plain Layout if y is close to integer; else 0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The number zero is used to represent boolean False. Any other number represents boolean True. The result of logical operators is 1 or 0. An example input file is shown below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example input file with logical operators: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * Logical operators \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout v1or 1 0 {1 || 0} \end_layout \begin_layout Plain Layout v1and 2 0 {1 && 0} \end_layout \begin_layout Plain Layout v1not 3 0 {! 1} \end_layout \begin_layout Plain Layout v1mod 4 0 {5 % 3} \end_layout \begin_layout Plain Layout v1div 5 0 {5 \backslash 3} \end_layout \begin_layout Plain Layout v0not 6 0 {! 0} \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout op \end_layout \begin_layout Plain Layout print allv \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .end \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Built-in function \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Notes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sqrt(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter y = sqrt(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sin(x), cos(x), tan(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sinh(x), cosh(x), tanh(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout asin(x), acos(x), atan(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout asinh(x), acosh(x), atanh(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout arctan(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter atan(x) \family default , kept for compatibility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout exp(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ln(x), log(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout abs(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout nint(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Nearest integer, half integers towards even \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout int(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Nearest integer rounded towards 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout floor(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Nearest integer rounded towards \family typewriter -∞ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ceil(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Nearest integer rounded towards \family typewriter +∞ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout pow(x,y) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout x raised to the power of y (pow from C runtime library) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout pwr(x,y) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter pow(fabs(x), y) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout min(x, y) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout max(x, y) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sgn(x) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 1.0 for x > 0, 0.0 for x == 0, -1.0 for x < 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ternary_fcn(x, y, z) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter x ? y : z \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout gauss(nom, rvar, sigma) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout nominal value plus variation drawn from Gaussian distribution with mean 0 and standard deviation rvar (relative to nominal), divided by sigma \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout agauss(nom, avar, sigma) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout nominal value plus variation drawn from Gaussian distribution with mean 0 and standard deviation avar (absolute), divided by sigma \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout unif(nom, rvar) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout nominal value plus relative variation (to nominal) uniformly distributed between +/-rvar \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout aunif(nom, avar) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout nominal value plus absolute variation uniformly distributed between +/-avar \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout limit(nom, avar) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout nominal value +/-avar, depending on random number in [-1, 1[ being \family typewriter > 0 \family default or \family typewriter < 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout var(name) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout returns the value of an interpreter variable, or zero if the variable does not exist. The argument is evaluated as a string expression, but used directly if that fails. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout vec(name) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout similar to var(), but returns the first value of a vector in the current plot, or the const plot if that fails. It may be used to access the named constants from the const plot, for example \begin_inset Quotes eld \end_inset vec(pi) \begin_inset Quotes erd \end_inset . \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The scaling suffixes (any decorative alphanumeric string may follow): \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout suffix \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout g \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout meg \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout k \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout m \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout u \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout n \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout p \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-12 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout f \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-15 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Note: there are intentional redundancies in expression syntax, e.g. \family typewriter x^y \family default , \family typewriter x**y \family default and \family typewriter pwr(x,y) \family default all have nearly the same result. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Reserved-words" \end_inset Reserved words \end_layout \begin_layout Standard In addition to the above function names and to the verbose operators ( \family typewriter not and or div mod \family default ), other words are reserved and cannot be used as parameter names: \family typewriter or \family default , \family typewriter defined \family default , \family typewriter sqr \family default , \family typewriter sqrt \family default , \family typewriter sin \family default , \family typewriter cos \family default , \family typewriter exp \family default , \family typewriter ln \family default , \family typewriter log, log10, arctan \family default , \family typewriter abs \family default , \family typewriter pwr \family default , \family typewriter time \family default , \family typewriter temper \family default , \family typewriter hertz \family default . \end_layout \begin_layout Subsection \begin_inset Index idx range none pageformat default status collapsed \begin_layout Plain Layout Parsers for expressions \end_layout \end_inset A word of caution on the three ngspice expression parsers \end_layout \begin_layout Standard The historical parameter notation using \family typewriter & \family default as the first character of a line as equivalence to \family typewriter .param \family default . is deprecated and will be removed in a coming release. \end_layout \begin_layout Standard Confusion may arise in ngspice because of its multiple numerical expression features. The \family typewriter .param \family default lines and the brace expressions (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:.param" plural "false" caps "false" noprefix "false" nolink "false" \end_inset and \begin_inset CommandInset ref LatexCommand ref reference "subsec:Brace-expressions" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) are evaluated in the front-end, that is, just after the subcircuit expansion. (Technically, the X lines are kept as comments in the expanded circuit so that the actual parameters can be correctly substituted). Therefore, after the netlist expansion and before the internal data setup, all number attributes in the circuit are known constants. However, there are circuit elements in Spice that accept arithmetic expressions \emph on not \emph default evaluated at this point, but only later during circuit analysis. These are the arbitrary current and voltage sources (B-sources, \begin_inset CommandInset ref LatexCommand ref reference "sec:Non-linear-Dependent-Sources" nolink "false" \end_inset ), as well as E- and G-sources and R-, L-, or C-devices. The syntactic difference is that `compile-time' expressions are within braces, but `run-time' expressions have no braces. To make things more complicated, the back-end ngspice scripting language accepts arithmetic/logic expressions that operate only on its own scalar or vector data sets ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Expressions,-Functions,-and" nolink "false" \end_inset ). Please see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Parameters,-functions,-expressions," nolink "false" \end_inset . \end_layout \begin_layout Standard It would be desirable to have the same expression syntax, operator and function set, and precedence rules, for the three contexts mentioned above. In the current Numparam implementation, that goal is not achieved. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:func" \end_inset .FUNC \end_layout \begin_layout Standard This keyword defines a function. The syntax of the expression is the same as for a \family typewriter .param \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Syntax-of-expressions" nolink "false" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .func { } \end_layout \begin_layout Plain Layout .func = { } \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .func icos(x) {cos(x) - 1} \end_layout \begin_layout Plain Layout .func f(x,y) {x*y} \end_layout \begin_layout Plain Layout .func foo(a,b) = {a + b} \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter .func \family default will initiate a replacement operation. After reading the input files, and before parameters are evaluated, all occurrences of the \family typewriter icos(x) \family default function will be replaced by \family typewriter cos(x)-1 \family default . All occurrences of \family typewriter f(x,y) \family default will be replaced by \family typewriter x*y \family default . Function statements may be nested to a depth of t.b.d.. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:.csparam" \end_inset .CSPARAM \end_layout \begin_layout Standard Create a constant vector (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Vectors" nolink "false" \end_inset ) from a parameter in \family typewriter plot \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Plots" nolink "false" \end_inset ) \family typewriter const \family default . \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .csparam = \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .param pippo=5 \end_layout \begin_layout Plain Layout .param pp=6 \end_layout \begin_layout Plain Layout .csparam pippp={pippo + pp} \end_layout \begin_layout Plain Layout .param p={pp} \end_layout \begin_layout Plain Layout .csparam pap='pp+p' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard In the example shown, vectors pippp, and pap are added to the constants that already reside in \family typewriter plot \family default \family typewriter const \family default , having length one and real values. These vectors are generated during circuit parsing and thus cannot be changed later (same as with ordinary parameters). They may be used in ngspice scripts and \family typewriter .control \family default sections (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "chap:Interactive-Interpreter" nolink "false" \end_inset ). \end_layout \begin_layout Standard The use of \family typewriter .csparam \family default is still experimental and has to be tested. A simple usage is shown below. \end_layout \begin_layout LyX-Code * test csparam \end_layout \begin_layout LyX-Code .param TEMPS = 27 \end_layout \begin_layout LyX-Code .csparam newt = {3*TEMPS} \end_layout \begin_layout LyX-Code .csparam mytemp = '2 + TEMPS' \end_layout \begin_layout LyX-Code .control \end_layout \begin_layout LyX-Code echo $&newt $&mytemp \end_layout \begin_layout LyX-Code .endc \end_layout \begin_layout LyX-Code .end \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:.temp" \end_inset .TEMP \end_layout \begin_layout Standard Sets the circuit temperature in degrees Celsius. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .temp value \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .temp 27 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This card overrides the circuit temperature given in an \family typewriter .option \family default line ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:General-Options" nolink "false" \end_inset ). \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:.IF-Condition-Controlled-Netlist" \end_inset .IF Condition-Controlled Netlist \end_layout \begin_layout Standard A simple \family typewriter .IF-.ELSE(IF) \family default block allows condition-controlling of the netlist. \family typewriter boolean expression \family default is any expression according to Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Syntax-of-expressions" nolink "false" \end_inset that evaluates parameters and returns a boolean 1 or 0. The netlist block in between the \series bold .if \series default ... \series bold .endif \series default statements may contain device instances or \family typewriter .model \family default cards that are selected according to the logic condition. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .if(boolean expression) \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout .elseif(boolean expression) \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout .else \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout .endif \end_layout \end_inset \end_layout \begin_layout Plain Layout Example 1: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * device instance in IF-ELSE block \end_layout \begin_layout Plain Layout .param ok=0 ok2=1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout v1 1 0 1 \end_layout \begin_layout Plain Layout R1 1 0 2 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .if (ok && ok2) \end_layout \begin_layout Plain Layout R11 1 0 2 \end_layout \begin_layout Plain Layout .else \end_layout \begin_layout Plain Layout R11 1 0 0.5 $ <-- selected \end_layout \begin_layout Plain Layout .endif \end_layout \end_inset \end_layout \begin_layout Plain Layout Example 2: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * .model in IF-ELSE block \end_layout \begin_layout Plain Layout .param m0=0 m1=1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout M1 1 2 3 4 N1 W=1 L=0.5 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .if(m0==1) \end_layout \begin_layout Plain Layout .model N1 NMOS level=49 Version=3.1 \end_layout \begin_layout Plain Layout .elseif(m1==1) \end_layout \begin_layout Plain Layout .model N1 NMOS level=49 Version=3.2.4 $ <-- selected \end_layout \begin_layout Plain Layout .else \end_layout \begin_layout Plain Layout .model N1 NMOS level=49 Version=3.3.0 \end_layout \begin_layout Plain Layout .endif \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Nesting of \family typewriter .IF-.ELSE(IF)-.ENDIF \family default blocks is possible. Several \family typewriter .elseif \family default (but of course only one \family typewriter .else) \family default are allowed per block (please see example \family sans ngspice/tests/regression/misc/if-elseif.cir \family default ). However some restrictions apply, as the following netlist components are \emph on not \emph default supported within the \family typewriter .IF-.ENDIF \family default block: \family typewriter .SUBCKT \family default , \family typewriter .INC \family default , \family typewriter .LIB \family default , and \family typewriter .PARAM \family default . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Parameters,-functions,-expressions," \end_inset Parameters, functions, expressions, and command scripts \end_layout \begin_layout Standard In ngspice there are several ways to describe functional dependencies. In fact there are three independent function parsers, being active before, during, and after the simulation. So it might be due to have a few words on their interdependence. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Parameters" \end_inset Parameters \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Parameters ! numparam parameters \end_layout \end_inset \end_layout \begin_layout Standard Parameters (Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.param" nolink "false" \end_inset ) and functions, either defined within the \family typewriter .param \family default statement or with the \family typewriter .func \family default statement (Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:func" nolink "false" \end_inset ) are evaluated \series bold before \series default any simulation is started, that is during the setup of the input and the circuit. Therefore these statements may not contain any simulation output (voltage or current vectors), because it is simply not yet available. The syntax is described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Syntax-of-expressions" nolink "false" \end_inset . During the circuit setup all functions are evaluated, all parameters are replaced by their resulting numerical values. Thus it will not be possible to get feedback from a later stage (during or after simulation) to change any of the parameters. \end_layout \begin_layout Subsection Nonlinear sources \end_layout \begin_layout Standard During the simulation, the B source (Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Non-linear-Dependent-Sources" nolink "false" \end_inset ) and their associated E and G sources, as well as some devices (R, C, L) may contain expressions. These expressions may contain parameters from above (evaluated immediately upon ngspice start up), numerical data, predefined functions, but also node voltages and branch currents resulting from the simulation. The source or device values are continuously updated \series bold during \series default the simulation. Therefore the sources are powerful tools to define non-linear behavior, you may even create new `devices' by yourself. Unfortunately the expression syntax (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" nolink "false" \end_inset ) and the predefined functions may deviate from the ones for parameters listed in \begin_inset CommandInset ref LatexCommand ref reference "subsec:.param" nolink "false" \end_inset . \end_layout \begin_layout Subsection Control commands, Command scripts \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Netlists ! .control sections \end_layout \end_inset \end_layout \begin_layout Standard Commands, as described in detail in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" nolink "false" \end_inset , may be used interactively, but also as a command script enclosed in \family typewriter .control ... .endc \family default lines. The scripts may contain expressions (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Expressions,-Functions,-and" nolink "false" \end_inset ). The expressions may work upon simulation output vectors (of node voltages, branch currents), as well as upon predefined or user defined vectors and variables, and are invoked \series bold after \series default the simulation. Parameters from \begin_inset CommandInset ref LatexCommand ref reference "subsec:.param" nolink "false" \end_inset defined by the \family typewriter .param \family default statement are not allowed in these expressions. However you may define such parameters with \family typewriter .csparam \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.csparam" nolink "false" \end_inset ). Again the expression syntax (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Expressions,-Functions,-and" nolink "false" \end_inset ) will deviate from the one for parameters or B sources listed in \begin_inset CommandInset ref LatexCommand ref reference "subsec:.param" nolink "false" \end_inset and \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" nolink "false" \end_inset . \end_layout \begin_layout Standard If you want to use parameters from \begin_inset CommandInset ref LatexCommand ref reference "subsec:.param" nolink "false" \end_inset inside your control script, you may use \family typewriter .csparam \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.csparam" nolink "false" \end_inset ) or apply a trick by defining a voltage source with the parameter as its value, and then have it available as a vector (e.g. after a transient simulation) with a then constant output (the parameter). A feedback from here back into parameters ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Parameters" nolink "false" \end_inset ) is never possible. Also you cannot access non-linear sources of the preceding simulation. However you may start a first simulation inside your control script, then evaluate its output using expressions, change some of the element or model parameters with the \family typewriter alter \family default and \family typewriter altermod \family default statements (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Alter*:-Change-a" nolink "false" \end_inset ) and then automatically start a new simulation. \end_layout \begin_layout Standard Expressions and scripting are powerful tools within ngspice, and we will enhance the examples given in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Example-Circuits" nolink "false" \end_inset continuously to describe these features. \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:Circuit-Elements-and" \end_inset Circuit Elements and Models \end_layout \begin_layout Standard Data fields that are enclosed in less-than and greater-than signs (` \family typewriter < > \family default ') are optional. All indicated punctuation (parentheses, equal signs, etc.) is optional but indicate the presence of any delimiter. Further, future implementations may require the punctuation as stated. A consistent style adhering to the punctuation shown here makes the input easier to understand. With respect to branch voltages and currents, ngspice uniformly uses the associated reference convention (current flows in the direction of voltage drop). \end_layout \begin_layout Section About netlists, device instances, models and model parameters \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Parameters ! model parameters \end_layout \end_inset \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Netlists \end_layout \end_inset \end_layout \begin_layout Standard The input to ngspice is a netlist, which lists all circuit elements, their interconnects and model parameters. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Netlist example of a simple bipolar amplifier: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout bipolar amplifier \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout R3 vcc intc 10k \end_layout \begin_layout Plain Layout R1 vcc intb 68k \end_layout \begin_layout Plain Layout R2 intb 0 10k \end_layout \begin_layout Plain Layout Cout out intc 10u \end_layout \begin_layout Plain Layout Cin intb in 10u \end_layout \begin_layout Plain Layout RLoad out 0 100k \end_layout \begin_layout Plain Layout Q1 intc intb 0 BC546B \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout VCC vcc 0 5 \end_layout \begin_layout Plain Layout Vin in 0 dc 0 ac 1 sin(0 1m 500) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .model BC546B npn ( IS=7.59E-15 VAF=73.4 BF=480 IKF=0.0962 \end_layout \begin_layout Plain Layout + NE=1.2665 ISE=3.278E-15 IKR=0.03 ISC=2.00E-13 NC=1.2 NR=1 \end_layout \begin_layout Plain Layout + BR=5 RC=0.25 CJC=6.33E-12 FC=0.5 MJC=0.33 VJC=0.65 \end_layout \begin_layout Plain Layout + CJE=1.25E-11 MJE=0.55 VJE=0.65 TF=4.26E-10 ITF=0.6 VTF=3 \end_layout \begin_layout Plain Layout + XTF=20 RB=100 IRB=0.0001 RBM=10 RE=0.5 TR=1.50E-07) \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard After the first line, which is always a title line only, the netlist starts. Each line here is a device instance (except for lines starting with a dot '.'). We have simple circuit elements that consist of a single line only, e.g. resistors like R3. In its simplest implementation, the resistor model does not need any model parameters except for the resistance value (same for capacitors like Cout). Netlist lines like \family sans R3 vcc intc 10k \family default are called instance lines, as each line is the representation of an instance of a generic model hard-coded into the ngspice simulator (here: resistor). R3 denotes the device name. Its first character \family sans R \family default denotes a resistor. The next two tokens \family sans vcc intc \family default are the two nodes of the resistor, \family sans 10k \family default is the resistance value. Equal node names on different devices denote a connection between these nodes. \end_layout \begin_layout Standard A more complex device is described by the instance line \family sans Q1 intc intb 0 BC546B \family default . \family sans Q \family default denotes a bipolar transistor, \family sans intc intb 0 \family default are the three nodes collector, base, and emitter. \family sans BC546B \family default is the name of a model parameter set, named after a real transistor and describing (together with the implemented bipolar transistor model) its electrical behavior. The associated model parameters are given in the line \family sans .model BC546B npn (IS=7.59E-15 ...) \family default . This is not an instance line, because starting with a dot. It contains the model parameters as supplied by the device manufacturer or by people having them extracted from the electrical behavior and data sheet (to be found e.g. on his or her web pages). \family sans BC546B \family default is the name of the model parameter set and relates it to the device instance. \family sans npn \family default is the type of the device. The parameters ( \family sans name=value \family default ) are given in brackets. \end_layout \begin_layout Standard The instance \family sans Q1... \family default requires model parameters. For a quick test one may do without device maker's model parameters. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Simplified bipolar transistor instance and model parameter set: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Q1 intc intb 0 defaultmod \end_layout \begin_layout Plain Layout .model defaultmod npn \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If you enter the bipolar transistor instance as shown above, you make use of a default model parameter set supplied by ngspice. \family sans defaultmod \family default is an arbitrary name. This procedure models a generic bipolar transistor, not resembling any commercial device. The default parameter values may be assessed by the command \family sans showmod Q1 \family default . \end_layout \begin_layout Standard You will get more information on devices, instances and models in the following chapters 3.3 to 12. \end_layout \begin_layout Section General options \end_layout \begin_layout Subsection Paralleling devices with multiplier m \end_layout \begin_layout Standard When it is needed to simulate several devices of the same kind in parallel, use the ` \family typewriter m \family default ' (parallel multiplier) instance parameter available for the devices listed in Table \begin_inset CommandInset ref LatexCommand ref reference "tab:multiplier" nolink "false" \end_inset . This multiplies the value of the element's matrix stamp with \family typewriter m \family default 's value. The netlist below shows how to correctly use the parallel multiplier: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Multiple device example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout d1 2 0 mydiode m=10 \end_layout \begin_layout Plain Layout d01 1 0 mydiode \end_layout \begin_layout Plain Layout d02 1 0 mydiode \end_layout \begin_layout Plain Layout d03 1 0 mydiode \end_layout \begin_layout Plain Layout d04 1 0 mydiode \end_layout \begin_layout Plain Layout d05 1 0 mydiode \end_layout \begin_layout Plain Layout d06 1 0 mydiode \end_layout \begin_layout Plain Layout d07 1 0 mydiode \end_layout \begin_layout Plain Layout d08 1 0 mydiode \end_layout \begin_layout Plain Layout d09 1 0 mydiode \end_layout \begin_layout Plain Layout d10 1 0 mydiode \end_layout \begin_layout Plain Layout ... \end_layout \end_inset \end_layout \begin_layout Plain Layout The \family typewriter d1 \family default instance connected between nodes 2 and 0 is equivalent to the 10 parallel devices \family typewriter d01-d10 \family default connected between nodes 1 and 0. \end_layout \end_inset \end_layout \begin_layout Standard The following devices support the multiplier m: \end_layout \begin_layout Standard \begin_inset Float table placement H alignment document wide false sideways false status open \begin_layout Plain Layout \align center \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout First letter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Element description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout D \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout F \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Current-controlled current source (CCCs) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout G \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Voltage-controlled current source (VCCS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout I \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Current source \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout J \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Junction field effect transistor (JFET) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout L \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Inductor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout M \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Metal oxide field effect transistor (MOSFET) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Q \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bipolar junction transistor (BJT) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout R \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Resistor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Subcircuit (for details see below) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Z \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Metal semiconductor field effect transistor (MESFET) \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "tab:multiplier" \end_inset ngspice elements supporting multiplier 'm' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard When the X line (e.g. \family typewriter x1 a b sub1 m=5 \family default ) contains the token \family typewriter m=value \family default (as shown) or \family typewriter m=expression \family default , subcircuit invocation is done in a special way. If an instance line of the subcircuit \family typewriter sub1 \family default contains any of the elements shown in table \begin_inset CommandInset ref LatexCommand ref reference "tab:multiplier" nolink "false" \end_inset , then these elements are instantiated with the additional parameter \family typewriter m \family default (in this example having the value 5). If such an element already has an \family typewriter m \family default multiplier parameter, the element \family typewriter m \family default is multiplied with the \family typewriter m \family default derived from the X line. This works recursively, meaning that if a subcircuit contains another subcircuit (a nested X line), then the latter \family typewriter m \family default parameter will be multiplied by the former one, and so on. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example 1: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .param madd = 6 \end_layout \begin_layout Plain Layout X1 a b sub1 m=5 \end_layout \begin_layout Plain Layout .subckt sub1 a1 b1 \end_layout \begin_layout Plain Layout Cs1 a1 b1 C=5p m='madd-2' \end_layout \begin_layout Plain Layout .ends \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard In example 1, the capacitance between nodes a and b will be \family typewriter C = 5pF*(madd-2)*5 = 100pF \family default . \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example 2: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .param madd = 4 \end_layout \begin_layout Plain Layout X1 a b sub1 m=3 \end_layout \begin_layout Plain Layout .subckt sub1 a1 b1 \end_layout \begin_layout Plain Layout X2 a1 b1 sub2 m='madd-2' \end_layout \begin_layout Plain Layout .ends \end_layout \begin_layout Plain Layout .subckt sub2 a2 b2 \end_layout \begin_layout Plain Layout Cs2 a2 b2 3p m=2 \end_layout \begin_layout Plain Layout .ends \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard In example 2, the capacitance between nodes a and b is \family typewriter C = 3pF*2*(madd-2)*3 = 36pF \family default . \end_layout \begin_layout Standard Using \family typewriter m \family default may fail to correctly describe geometrical properties for real devices like MOS transistors. \end_layout \begin_layout Standard \family typewriter M1 d g s nmos W=0.3u L=0.18u m=20 \end_layout \begin_layout Standard is probably not be the same as \end_layout \begin_layout Standard \family typewriter M1 d g s nmos W=6u L=0.18u \end_layout \begin_layout Standard because the former may suffer from small width (or edge) effects, whereas the latter is simply a wide transistor. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Instance-and-model" \end_inset Instance and model parameters \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Parameters ! instance parameters \end_layout \end_inset \end_layout \begin_layout Standard The simple device example below consists of two lines: The device is defined on the instance line, starting with Lload ...: The first letter determines the device type (an inductor in this example). Following the device name are two nodes 1 and 2, then the inductance value 1u is set. The model name ind1 is a connection to the respective model line. Finally we have a parameter on the instance line, together with its value dtemp=5. Parameters on an instance line are called instance parameters. \end_layout \begin_layout Standard The model line starts with the token .model, followed by the model name, the model type and at least one model parameter, here tc1=0.001. There are complex models with more than 100 model parameters. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Lload 1 2 1u ind1 dtemp=5 \end_layout \begin_layout Plain Layout .MODEL ind1 L tc1=0.001 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Instance parameters are listed in each of the following device descriptions. Model parameters sometimes are given below as well, for complex models like the BSIM transistor models, they are available in the model makers \begin_inset CommandInset href LatexCommand href name "documentation" target "http://ngspice.sourceforge.net/literature.html" literal "false" \end_inset . Instance parameters may also be placed in the .model line. Thus they are recognized by each device instance referring to that model. Their values may be overridden for a specific instance of a device by placing them additionally onto its instance line. \end_layout \begin_layout Subsection Model binning \end_layout \begin_layout Standard Binning is a kind of range partitioning for geometry dependent models like MOSFET's. The purpose is to cover larger geometry ranges (Width and Length) with higher accuracy than the model built-in geometry formulas. Each size range described by the additional model parameters LMIN, LMAX, WMIN and WMAX has its own model parameter set. These model cards are defined by a number extension, like `nch.1'. ngspice has an algorithm to choose the right model card by the requested W and L. \end_layout \begin_layout Standard This is implemented for BSIM3 ( \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM3-model" nolink "false" \end_inset ) and BSIM4 ( \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM4-model" nolink "false" \end_inset ) models. \end_layout \begin_layout Subsection Initial conditions \end_layout \begin_layout Standard Two different forms of initial conditions may be specified for some devices. The first form is included to improve the dc convergence for circuits that contain more than one stable state. If a device is specified \family typewriter \series bold OFF \family default \series default , the dc operating point is determined with the terminal voltages for that device set to zero. After convergence is obtained, the program continues to iterate to obtain the exact value for the terminal voltages. If a circuit has more than one dc stable state, the \family typewriter \series bold OFF \family default \series default option can be used to force the solution to correspond to a desired state. If a device is specified \family typewriter \series bold OFF \family default \series default when in reality the device is conducting, the program still obtains the correct solution (assuming the solutions converge) but more iterations are required since the program must independently converge to two separate solutions. \end_layout \begin_layout Standard The \family typewriter .NODESET \family default control line (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.NODESET" nolink "false" \end_inset ) serves a similar purpose as the \family typewriter \series bold OFF \family default \series default option. The \family typewriter .NODESET \family default option is easier to apply and is the preferred means to aid convergence. The second form of initial conditions are specified for use with the transient analysis. These are true `initial conditions' as opposed to the convergence aids above. See the description of the \family typewriter .IC \family default control line (Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.IC:-Set-Initial" nolink "false" \end_inset ) and the \family typewriter .TRAN \family default control line (Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.TRAN:-Transient-Analysis" nolink "false" \end_inset ) for a detailed explanation of initial conditions. \end_layout \begin_layout Section Elementary Devices \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Resistors" \end_inset Resistors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout RXXXXXXX n+ n- value \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout R1 1 2 100 \end_layout \begin_layout Plain Layout RC1 12 17 1K \end_layout \begin_layout Plain Layout R2 5 7 1K ac=2K \end_layout \begin_layout Plain Layout RL 1 4 2K m=2 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Ngspice has a fairly complex model for resistors. It can simulate both discrete and semiconductor resistors. Semiconductor resistors in ngspice means: resistors described by geometrical parameters. So, do not expect detailed modeling of semiconductor effects. \family typewriter \end_layout \begin_layout Standard \family typewriter n+ \family default and \family typewriter n- \family default are the two element nodes, \family typewriter value \family default is the resistance (in ohms) and may be positive or negative \begin_inset Foot status collapsed \begin_layout Plain Layout A negative resistor modeling an active element can cause convergence problems, please avoid it. \end_layout \end_inset but not zero. If value resistance 0 is given, it will be automatically set to 1e-12. \end_layout \begin_layout Standard \begin_inset Box Boxed position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "80col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Simulating small valued resistors: If you need to simulate very small resistors (0.001 Ohm or less), you should use CCVS (transresistance). It is less efficient but improves overall numerical accuracy. Consider a small resistance as a large conductance. \end_layout \end_inset \end_layout \begin_layout Standard Ngspice can assign a resistor instance a different value for AC analysis, specified using the \family typewriter \series bold ac \family default \series default keyword. This value must not be zero as described above. The AC resistance is used in AC analysis only (neither Pole-Zero nor Noise). If you do not specify the \family typewriter \series bold ac \family default \series default parameter, it is defaulted to \family typewriter \series bold value \family default \series default . \end_layout \begin_layout Standard Ngspice calculates the nominal resistance as \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \begin{alignedat}{1}\begin{array}{cc} R_{nom}= & \frac{{{\mathrm{VALUE}}\:{\mathrm{scale}}}}{m}\\ \\R_{acnom}= & \frac{{{\mathrm{ac}}\:{\mathrm{scale}}}}{m}. \end{array}\end{alignedat} \end{equation} \end_inset \end_layout \begin_layout Standard If you want to simulate temperature dependence of a resistor, you need to specify its temperature coefficients, using a \family typewriter .model \family default line or as instance parameters, like in the examples below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout RE1 1 2 800 newres dtemp=5 \end_layout \begin_layout Plain Layout .MODEL newres R tc1=0.001 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout RE2 a b 1.4k tc1=2m tc2=1.4u \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout RE3 n1 n2 1Meg tce=700m \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The temperature coefficients \family typewriter tc1 \family default and \family typewriter tc2 \family default describe a quadratic temperature dependence (see equation \begin_inset CommandInset ref LatexCommand ref reference "eq:R-Temp-quad" nolink "false" \end_inset ) of the resistance. If given in the instance line (the R... line) their values will override the \family typewriter tc1 \family default and \family typewriter tc2 \family default of the \family typewriter .model \family default line ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Semiconductor-Resistor-Model" nolink "false" \end_inset ). Ngspice has an additional temperature model equation \begin_inset CommandInset ref LatexCommand ref reference "eq:R-Temp-expo" nolink "false" \end_inset parameterized by \family typewriter tce \family default given in model or instance line. If all parameters are given (quadratic and exponential) the exponential temperature model is chosen. \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} R\left(T\right)=R\left(T_{0}\right)\left[1.01^{TCE\cdot(T-T_{0})}\right]\label{eq:R-Temp-expo} \end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $T$ \end_inset is the circuit temperature, \begin_inset Formula $T_{0}$ \end_inset is the nominal temperature, and \begin_inset Formula $TCE$ \end_inset is the exponential temperature coefficients. \end_layout \begin_layout Standard Instance temperature is useful even if resistance does not vary with it, since the thermal noise generated by a resistor depends on its absolute temperature. Resistors in ngspice generates two different noises: thermal and flicker. While thermal noise is always generated in the resistor, to add a flicker noise \begin_inset Foot status collapsed \begin_layout Plain Layout Flicker noise can be used to model carbon resistors. \end_layout \end_inset source you have to add a \family typewriter .model \family default card defining the flicker noise parameters. It is possible to simulate resistors that do not generate any kind of noise using the \family typewriter \series bold noisy (or noise) \family default \series default keyword and assigning zero to it, as in the following example: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Rmd 134 57 1.5k noisy=0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If you are interested in temperature effects or noise equations, read the next section on semiconductor resistors. \end_layout \begin_layout Subsection Semiconductor Resistors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout RXXXXXXX n+ n- \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout RLOAD 2 10 10K \end_layout \begin_layout Plain Layout RMOD 3 7 RMODEL L=10u W=1u \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This is the more general form of the resistor presented before ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Resistors" nolink "false" \end_inset ) and allows the modeling of temperature effects and for the calculation of the actual resistance value from strictly geometric information and the specifications of the process. If \family typewriter \series bold value \family default \series default is specified, it overrides the geometric information and defines the resistance. If \family typewriter \series bold mname \family default \series default is specified, then the resistance may be calculated from the process information in the model \family typewriter \series bold mname \family default \series default and the given \family typewriter \series bold length \family default \series default and \family typewriter \series bold width \family default \series default . If \family typewriter \series bold value \family default \series default is not specified, then \family typewriter \series bold mname \family default \series default and \family typewriter \series bold length \family default \series default must be specified. If \family typewriter \series bold width \family default \series default is not specified, then it is taken from the default width given in the model. \end_layout \begin_layout Standard The (optional) \family typewriter \series bold temp \family default \series default value is the temperature at which this device is to operate, and overrides the temperature specification on the \family typewriter .option \family default control line and the value specified in \family typewriter \series bold dtemp \family default \series default . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Semiconductor-Resistor-Model" \end_inset Semiconductor Resistor Model (R) \end_layout \begin_layout Standard The resistor model consists of process-related device data that allow the resistance to be calculated from geometric information and to be corrected for temperature. The parameters available are as follows: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TC1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout first order temperature coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TC2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout second order temperature coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RSH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sheet resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{\square}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DEFW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout default width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NARROW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout narrowing due to side etching \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SHORT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout shortening due to side etching \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout parameter measurement temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 27 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flicker noise coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-25 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flicker noise exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout WF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flicker noise width exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flicker noise length exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout EF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flicker noise frequency exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout R (RES) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout default value if element value not given \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1000 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The sheet resistance is used with the narrowing parameter and \family typewriter \series bold l \family default \series default and \family typewriter \series bold w \family default \series default from the resistor device to determine the nominal resistance by the formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} R_{nom}={\mathrm{rsh}}\frac{l-{\mathrm{SHORT}}}{w-{\mathrm{NARROW}}} \end{equation} \end_inset \end_layout \begin_layout Standard \family typewriter \series bold DEFW \family default \series default is used to supply a default value for \family typewriter \series bold w \family default \series default if one is not specified for the device. If either \family typewriter \series bold rsh \family default \series default or \family typewriter \series bold l \family default \series default is not specified, then the standard default resistance value of 1 mOhm is used. \family typewriter \series bold TNOM \family default \series default is used to override the circuit-wide value given on the \family typewriter .options \family default control line where the parameters of this model have been measured at a different temperature. After the nominal resistance is calculated, it is adjusted for temperature by the formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} R(T)=R({\mathrm{TNOM}})\:\Bigl(1+TC_{1}(T-{\mathrm{TNOM}})+TC_{2}(T-{\mathrm{TNOM}})^{2}\Bigr) \end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $R({\mathrm{TNOM}})=R_{nom}\vert R_{acnom}$ \end_inset . In the above formula, ` \begin_inset Formula $T$ \end_inset ' represents the instance temperature, which can be explicitly set using the \family typewriter \series bold temp \family default \series default keyword or calculated using the circuit temperature and \family typewriter \series bold dtemp \family default \series default , if present. If both \family typewriter \series bold temp \family default \series default and \family typewriter \series bold dtemp \family default \series default are specified, the latter is ignored. Ngspice improves SPICE's resistors noise model, adding flicker noise ( \begin_inset Formula $\nicefrac{1}{f}$ \end_inset ) to it and the \family typewriter \series bold noisy (or noise) \family default \series default keyword to simulate noiseless resistors. The thermal noise in resistors is modeled according to the equation: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \bar{i_{R}^{2}}=\frac{{4kT}}{R}\Delta f \end{equation} \end_inset \end_layout \begin_layout Standard where ` \begin_inset Formula $k$ \end_inset ' is the Boltzmann's constant, and ` \begin_inset Formula $T$ \end_inset ' the instance temperature. \end_layout \begin_layout Standard Flicker noise model is: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \bar{i_{Rfn}^{2}}=\frac{{\mathrm{KF}}I_{R}^{{\mathrm{AF}}}}{W^{WF}L^{LF}f^{EF}}\Delta f \end{equation} \end_inset \end_layout \begin_layout Standard A small list of sheet resistances (in \begin_inset Formula $\nicefrac{\Omega}{\square}$ \end_inset ) for conductors is shown below. The table represents typical values for MOS processes in the 0.5 - 1 um \end_layout \begin_layout Standard range. The table is taken from: \emph on N. Weste, K. Eshraghian - Principles of CMOS VLSI Design 2nd Edition, Addison Wesley \emph default . \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Material \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Min. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Typ. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Max. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Inter-metal (metal1 - metal2) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.005 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.007 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Top-metal (metal3) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.003 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.004 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.05 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Polysilicon (poly) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 20 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 30 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Silicide \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Diffusion (n+, p+) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 25 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Silicided diffusion \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout n-well \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1000 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2000 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5000 \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Resistors,-dependent-on" \end_inset Resistors, dependent on expressions (behavioral resistor) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout RXXXXXXX n+ n- R = 'expression' \end_layout \begin_layout Plain Layout RXXXXXXX n+ n- 'expression' \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout R1 rr 0 r = 'V(rr) < {Vt} ? {R0} : {2*R0}' tc1=2e-03 tc2=3.3e-06 \end_layout \begin_layout Plain Layout R2 r2 rr r = {5k + 50*TEMPER} \end_layout \begin_layout Plain Layout .param rp1 = 20 \end_layout \begin_layout Plain Layout R3 no1 no2 r = '5k * rp1' noisy=1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold Expression \series default may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" nolink "false" \end_inset . It may contain parameters ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.param" nolink "false" \end_inset ) and the special variables \family typewriter time \family default , \family typewriter temper \family default , and \family typewriter hertz \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Special-B-Source-Variables" nolink "false" \end_inset ). An example file is given below. Small signal noise in the resistor ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.NOISE:-Noise-Analysis" nolink "false" \end_inset ) may be evaluated as white noise, depending on resistance, temperature and tc1, tc2. To enable noise calculation, add the flag \family typewriter noisy=1 \family default to the instance line. As a default the behavioral resistor is noiseless. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example input file for non-linear resistor: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Non-linear resistor \end_layout \begin_layout Plain Layout .param R0=1k Vi=1 Vt=0.5 \end_layout \begin_layout Plain Layout * resistor depending on control voltage V(rr) \end_layout \begin_layout Plain Layout R1 rr 0 r = 'V(rr) < {Vt} ? {R0} : {2*R0}' \end_layout \begin_layout Plain Layout * control voltage \end_layout \begin_layout Plain Layout V1 rr 0 PWL(0 0 100u {Vi}) \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout unset askquit \end_layout \begin_layout Plain Layout tran 100n 100u uic \end_layout \begin_layout Plain Layout plot i(V1) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Resistor with nonlinear r2_cmc or r3_cmc models \end_layout \begin_layout Standard 2-terminal resistor models developed by the resistor subcommittee of the CMC are made available via the OSDI interface by loading OpenVAF-compiled Verilog-A models (see chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:OSDI/OpenVAF" nolink "false" \end_inset for details). The goal was to have a standard 2-terminal resistor model with standard parameter names and a standard, numerically well behaved nonlinearity model. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Capacitors" \end_inset Capacitors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout CXXXXXXX n+ n- \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout CBYP 13 0 1UF \end_layout \begin_layout Plain Layout COSC 17 23 10U IC=3V \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Ngspice provides a detailed model for capacitors. Capacitors in the netlist can be specified giving their capacitance or their geometrical and physical characteristics. Following the original SPICE3 `convention', capacitors specified by their geometrical or physical characteristics are called `semiconductor capacitors' and are described in the next section. \end_layout \begin_layout Standard In this first form \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive and negative element nodes, respectively and \family typewriter \series bold value \family default \series default is the capacitance in Farads. \end_layout \begin_layout Standard Capacitance can be specified in the instance line as in the examples above or in a \family typewriter .model \family default line, as in the example below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout C1 15 5 cstd \end_layout \begin_layout Plain Layout C2 2 7 cstd \end_layout \begin_layout Plain Layout .model cstd C cap=3n \end_layout \end_inset \end_layout \begin_layout Plain Layout Both capacitors have a capacitance of 3nF. \end_layout \end_inset \end_layout \begin_layout Standard If you want to simulate temperature dependence of a capacitor, you need to specify its temperature coefficients, using a \family typewriter .model \family default line, like in the example below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout CEB 1 2 1u cap1 dtemp=5 \end_layout \begin_layout Plain Layout .MODEL cap1 C tc1=0.001 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The (optional) initial condition is the initial (time zero) value of capacitor voltage (in Volts). Note that the initial conditions (if any) apply only if the \family typewriter \series bold uic \family default \series default option is specified on the \family typewriter .tran \family default control line. \end_layout \begin_layout Standard Ngspice calculates the nominal capacitance as described below: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} C_{nom}={{{\mathrm{value}}\cdot{\mathrm{scale}}}\cdot m} \end{equation} \end_inset \end_layout \begin_layout Standard The temperature coefficients \family typewriter tc1 \family default and \family typewriter tc2 \family default describe a quadratic temperature dependence (see equation \begin_inset CommandInset ref LatexCommand ref reference "eq:" nolink "false" \end_inset ) of the capacitance. If given in the instance line (the C... line) their values will override the \family typewriter tc1 \family default and \family typewriter tc2 \family default of the \family typewriter .model \family default line ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Semiconductor-Capacitor-Model" nolink "false" \end_inset ). \end_layout \begin_layout Subsection Semiconductor Capacitors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout CXXXXXXX n+ n- \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout CLOAD 2 10 10P \end_layout \begin_layout Plain Layout CMOD 3 7 CMODEL L=10u W=1u \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This is the more general form of the Capacitor presented in section ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Capacitors" nolink "false" \end_inset ), and allows for the calculation of the actual capacitance value from strictly geometric information and the specifications of the process. If \family typewriter \series bold value \family default \series default is specified, it defines the capacitance and both process and geometrical information are discarded. If \family typewriter \series bold value \family default \series default is not specified, the capacitance is calculated from information contained model \family typewriter \series bold mname \family default \series default and the given length and width ( \family typewriter \series bold l \family default \series default , \family typewriter \series bold w \family default \series default keywords, respectively). \end_layout \begin_layout Standard It is possible to specify \family typewriter \series bold mname \family default \series default only, without geometrical dimensions and set the capacitance in the \family typewriter .model \family default line ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Capacitors" nolink "false" \end_inset ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Semiconductor-Capacitor-Model" \end_inset Semiconductor Capacitor Model (C) \end_layout \begin_layout Standard The capacitor model contains process information that may be used to compute the capacitance from strictly geometric information. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CAP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout model capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout junction bottom capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout junction sidewall capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2e-11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DEFW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout default device width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DEFL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout default device length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NARROW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout narrowing due to side etching \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SHORT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout shortening due to side etching \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TC1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout first order temperature coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.001 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TC2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout second order temperature coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0001 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout parameter measurement temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 27 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout relative dielectric constant \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout THICK \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout insulator thickness \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-9 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The capacitor has a capacitance computed as: \end_layout \begin_layout Standard If \family typewriter \series bold value \family default \series default is specified on the instance line then \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} C_{nom}={{{\mathrm{value}}\cdot{\mathrm{scale}}}\cdot m} \end{equation} \end_inset \end_layout \begin_layout Standard If model capacitance is specified then \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} C_{nom}={{{\mathrm{CAP}}\cdot{\mathrm{scale}}}\cdot m} \end{equation} \end_inset \end_layout \begin_layout Standard If neither \family typewriter \series bold value \family default \series default nor \family typewriter \series bold CAP \family default \series default are specified, then geometrical and physical parameters are take into account: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} {\mathrm{C}_{0}}={\mathrm{CJ}}(l-{\mathrm{SHORT}})(w-{\mathrm{NARROW}})+2{\mathrm{CJSW}}(l-{\mathrm{SHORT}}+w-{\mathrm{NARROW}}) \end{equation} \end_inset \end_layout \begin_layout Standard \family typewriter \series bold CJ \family default \series default can be explicitly given on the \family typewriter .model \family default line or calculated by physical parameters. When \family typewriter \series bold CJ \family default \series default is not given, is calculated as: \end_layout \begin_layout Standard If \family typewriter \series bold THICK \family default \series default is not zero: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \begin{array}{cc} {\mathrm{C}J}=\frac{{{\mathrm{DI}}\:\epsilon_{0}}}{{\mathrm{THICK}}} & \mathrm{if\:DI\:is\:specified,}\\ \\{\mathrm{CJ}}=\frac{{\epsilon_{SiO_{2}}}}{{\mathrm{THICK}}} & \mathrm{otherwise.} \end{array} \end{equation} \end_inset \end_layout \begin_layout Standard If the relative dielectric constant is not specified the one for SiO2 is used. The values of the constants are \begin_inset Formula $\epsilon_{0}=8.854214871e-12\frac{F}{m}$ \end_inset and \begin_inset Formula $\epsilon_{SiO_{2}}=3.4531479969e-11\frac{F}{m}$ \end_inset . The nominal capacitance is then computed as: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} C_{nom}={C_{0}\:{\mathrm{scale}}\:m} \end{equation} \end_inset \end_layout \begin_layout Standard After the nominal capacitance is calculated, it is adjusted for temperature by the formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} C(T)=C({\mathrm{TNOM}})\:\Bigl(1+TC_{1}(T-{\mathrm{TNOM}})+TC_{2}(T-{\mathrm{TNOM}})^{2}\Bigr) \end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $C({\mathrm{TNOM}})=C_{nom}$ \end_inset . \end_layout \begin_layout Standard In the above formula, ` \begin_inset Formula $T$ \end_inset ' represents the instance temperature, which can be explicitly set using the \family typewriter \series bold temp \family default \series default keyword or calculated using the circuit temperature and \family typewriter \series bold dtemp \family default \series default , if present. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Capacitors,-dependent-on" \end_inset Capacitors, dependent on expressions (behavioral capacitor) \end_layout \begin_layout Standard There are two forms for behavioral capacitors allowed: \end_layout \begin_layout Enumerate Capacitance formulated expressions C = 'expression' \end_layout \begin_layout Enumerate Charge formulated expressions Q = 'expression' \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout CXXXXXXX n+ n- C = 'expression' \end_layout \begin_layout Plain Layout CXXXXXXX n+ n- 'expression' \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout CXXXXXXX n+ n- Q = 'expression' \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout C1 cc 0 c = 'V(cc) < {Vt} ? {C1} : {Ch}' tc1=-1e-03 tc2=1.3e-05 \end_layout \begin_layout Plain Layout C1 a b q = '1u*(4*atan(V(a,b)/4)*2+V(a,b))/3' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold Expression \series default may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" nolink "false" \end_inset . It may contain parameters ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.param" nolink "false" \end_inset ) and the special variables \family typewriter time \family default , \family typewriter temper \family default , and \family typewriter hertz \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Special-B-Source-Variables" nolink "false" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example input file: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Behavioral Capacitor \end_layout \begin_layout Plain Layout .param Cl=5n Ch=1n Vt=1m Il=100n \end_layout \begin_layout Plain Layout .ic v(cc) = 0 v(cc2) = 0 \end_layout \begin_layout Plain Layout * capacitor depending on control voltage V(cc) \end_layout \begin_layout Plain Layout C1 cc 0 c = 'V(cc) < {Vt} ? {Cl} : {Ch}' \end_layout \begin_layout Plain Layout I1 0 1 {Il} \end_layout \begin_layout Plain Layout Exxx n1-copy n2 n2 cc2 1 \end_layout \begin_layout Plain Layout Cxxx n1-copy n2 1 \end_layout \begin_layout Plain Layout Bxxx cc2 n2 I = '(V(cc2) < {Vt} ? {Cl} : {Ch})' * i(Exxx) \end_layout \begin_layout Plain Layout I2 n2 22 {Il} \end_layout \begin_layout Plain Layout vn2 n2 0 DC 0 \end_layout \begin_layout Plain Layout * measure charge by integrating current \end_layout \begin_layout Plain Layout aint1 %id(1 cc) 2 time_count \end_layout \begin_layout Plain Layout aint2 %id(22 cc2) 3 time_count \end_layout \begin_layout Plain Layout .model time_count int(in_offset=0.0 gain=1.0 \end_layout \begin_layout Plain Layout + out_lower_limit=-1e12 out_upper_limit=1e12 \end_layout \begin_layout Plain Layout + limit_range=1e-9 out_ic=0.0) \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout unset askquit \end_layout \begin_layout Plain Layout tran 100n 100u \end_layout \begin_layout Plain Layout plot v(2) \end_layout \begin_layout Plain Layout plot v(cc) v(cc2) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Inductors" \end_inset Inductors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout LYYYYYYY n+ n- \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout LLINK 42 69 1UH \end_layout \begin_layout Plain Layout LSHUNT 23 51 10U IC=15.7MA \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The inductor device implemented into ngspice has many enhancements over the original one. \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive and negative element nodes, respectively. \family typewriter \series bold value \family default \series default is the inductance in Henry. The initial condition (a curremt through L) becomes effective when the \family typewriter uic \family default parameter is set on the \family typewriter .tran \family default line. Inductance can be specified in the instance line as in the examples above or in a \family typewriter .model \family default line, as in the example below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout L1 15 5 indmod1 \end_layout \begin_layout Plain Layout L2 2 7 indmod1 \end_layout \begin_layout Plain Layout .model indmod1 L ind=3n \end_layout \end_inset \end_layout \begin_layout Plain Layout Both inductors have an inductance of 3nH. \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter \series bold nt \family default \series default is used in conjunction with a \family typewriter .model \family default line, and is used to specify the number of turns of the inductor. If you want to simulate temperature dependence of an inductor, you need to specify its temperature coefficients, using a \family typewriter .model \family default line, like in the example below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Lload 1 2 1u ind1 dtemp=5 \end_layout \begin_layout Plain Layout .MODEL ind1 L tc1=0.001 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The (optional) initial condition is the initial (time zero) value of inductor current (in Amps) that flows from \family typewriter \series bold n+ \family default \series default , through the inductor, to \family typewriter \series bold n- \family default \series default . Note that the initial conditions (if any) apply only if the \family typewriter \series bold UIC \family default \series default option is specified on the \family typewriter .tran \family default analysis line. \end_layout \begin_layout Standard Ngspice calculates the nominal inductance as described below: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} L_{nom}=\frac{{{\mathrm{value}}\:{\mathrm{scale}}}}{m} \end{equation} \end_inset \end_layout \begin_layout Subsection Inductor model \end_layout \begin_layout Standard The inductor model contains physical and geometrical information that may be used to compute the inductance of some common topologies like solenoids and toroids, wound in air or other material with constant magnetic permeability. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IND \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout model inductance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $H$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CSECT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout cross section \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m^{2}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DIA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout coil diameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LENGTH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TC1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout first order temperature coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{H}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.001 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TC2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout second order temperature coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{H}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0001 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout parameter measurement temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 27 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout number of turns \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MU \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout relative magnetic permeability \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The inductor's inductance is computed as follows: \end_layout \begin_layout Standard If \family typewriter \series bold value \family default \series default is specified on the instance line then \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} L_{nom}=\frac{{{\mathrm{value}}\:{\mathrm{scale}}}}{m} \end{equation} \end_inset \end_layout \begin_layout Standard If model inductance is specified then \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} L_{nom}=\frac{{{\mathrm{IND}}\:{\mathrm{scale}}}}{m} \end{equation} \end_inset \end_layout \begin_layout Standard If neither \family typewriter \series bold value \family default \series default nor \family typewriter \series bold IND \family default \series default are specified, then geometrical and physical parameters are taken into account. In the following formulas \end_layout \begin_layout Standard \family typewriter \series bold NT \family default \series default refers to both instance and model parameter (instance parameter overrides model parameter): \end_layout \begin_layout Standard If \family typewriter \series bold LENGTH \family default \series default is not zero: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \begin{cases} L_{nom}=\frac{{{\mathrm{MU}}\:\mu_{0}\:{\mathrm{NT}}^{2}\:\pi\:{\mathrm{DIA}}^{2}}}{4\:{\mathrm{LENGTH}}} & \mathrm{if\:}{\mathrm{DIA}\mathrm{\:is\:specified,}}\\ L_{nom}=\frac{{{\mathrm{MU}}\:\mu_{0}\:{\mathrm{NT}}^{2}\:{\mathrm{CSECT}}}}{{\mathrm{LENGTH}}} & \mathrm{otherwise.} \end{cases} \end{equation} \end_inset \end_layout \begin_layout Standard with \begin_inset Formula $\mu_{0}=1.25663706143592\frac{\mu H}{m}$ \end_inset . \family typewriter DIA \family default takes preference over \family typewriter CSECT \family default . \begin_inset Formula $kl$ \end_inset is the geometry correction factor according to Lundin (see \begin_inset CommandInset href LatexCommand href name "D. W. Knight" target "https://g3ynh.info/zdocs/magnetics/Solenoids.pdf" literal "false" \end_inset , pp. 35-36), which is important when inductor length and diameter have the same order of magnitude. After the nominal inductance is calculated, it is adjusted for temperature by the formula \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} L(T)=L({\mathrm{TNOM}})\:\Bigl(1+TC_{1}(T-{\mathrm{TNOM}})+TC_{2}(T-{\mathrm{TNOM}})^{2}\Bigr), \end{equation} \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $L({\mathrm{TNOM}})=L_{nom}$ \end_inset . In the above formula, ` \begin_inset Formula $T$ \end_inset ' represents the instance temperature, which can be explicitly set using the \family typewriter \series bold temp \family default \series default keyword or calculated using the circuit temperature and \family typewriter \series bold dtemp \family default \series default , if present. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Coupled-(Mutual)-Inductors" \end_inset Coupled (Mutual) Inductors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout KXXXXXXX LYYYYYYY LZZZZZZZ value \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout K43 LAA LBB 0.999 \end_layout \begin_layout Plain Layout KXFRMR L1 L2 0.87 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard LYYYYYYY and LZZZZZZZ are the names of the two coupled inductors, and \family typewriter \series bold value \family default \series default is the coefficient of coupling, K, which must be greater than 0 and less than or equal to 1. Using the `dot' convention for drawing the coupled inductors, place a `dot' on the first node of each inductor. If you have more than two inductors interacting, pairwise coupling is supported. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Pairwise coupling of more than two inductors: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout L1 1 0 10u \end_layout \begin_layout Plain Layout L2 2 0 11u \end_layout \begin_layout Plain Layout L3 3 0 10u \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout K12 L1 L2 0.99 \end_layout \begin_layout Plain Layout K23 L2 L3 0.99 \end_layout \begin_layout Plain Layout K13 L1 L3 0.98 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard When there are more than two inductors coupled for interaction, some combinations of coupling constants are not possible physically because the magnetic fields then would violate energy conservation. ngspice checks the coupling matrix for such conditions and issues a warning. \end_layout \begin_layout Standard Coupling of more than two inductors in a single K statement is supported as well. All coupling constants are then equal. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Coupling of more than two inductors in a single statement: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout L1 1 0 10u \end_layout \begin_layout Plain Layout L2 2 0 11u \end_layout \begin_layout Plain Layout L3 3 0 10u \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout K123 L1 L2 L3 0.97 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Inductors,-dependent-on" \end_inset Inductors, dependent on expressions (behavioral inductor) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout LXXXXXXX n+ n- L = 'expression' \end_layout \begin_layout Plain Layout LXXXXXXX n+ n- 'expression' \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout L1 l2 lll L = 'i(Vm) < {It} ? {Ll} : {Lh}' tc1=-4e-03 tc2=6e-05 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold Expression \series default may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" nolink "false" \end_inset . It may contain parameters ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.param" nolink "false" \end_inset ) and the special variables \family typewriter time \family default , \family typewriter temper \family default , and \family typewriter hertz \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Special-B-Source-Variables" nolink "false" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example input file: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Variable inductor \end_layout \begin_layout Plain Layout .param Ll=0.5m Lh=5m It=50u Vi=2m \end_layout \begin_layout Plain Layout .ic v(int21) = 0 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * variable inductor depending on control current i(Vm) \end_layout \begin_layout Plain Layout L1 l2 lll L = 'i(Vm) < {It} ? {Ll} : {Lh}' \end_layout \begin_layout Plain Layout * measure current through inductor \end_layout \begin_layout Plain Layout vm lll 0 dc 0 \end_layout \begin_layout Plain Layout * voltage on inductor \end_layout \begin_layout Plain Layout V1 l2 0 {Vi} \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * fixed inductor \end_layout \begin_layout Plain Layout L3 33 331 {Ll} \end_layout \begin_layout Plain Layout * measure current through inductor \end_layout \begin_layout Plain Layout vm33 331 0 dc 0 \end_layout \begin_layout Plain Layout * voltage on inductor \end_layout \begin_layout Plain Layout V3 33 0 {Vi} \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * non linear inductor (discrete setup) \end_layout \begin_layout Plain Layout F21 int21 0 B21 -1 \end_layout \begin_layout Plain Layout L21 int21 0 1 \end_layout \begin_layout Plain Layout B21 n1 n2 V = '(i(Vm21) < {It} ? {Ll} : {Lh})' * v(int21) \end_layout \begin_layout Plain Layout * measure current through inductor \end_layout \begin_layout Plain Layout vm21 n2 0 dc 0 \end_layout \begin_layout Plain Layout V21 n1 0 {Vi} \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout unset askquit \end_layout \begin_layout Plain Layout tran 1u 100u uic \end_layout \begin_layout Plain Layout plot i(Vm) i(vm33) \end_layout \begin_layout Plain Layout plot i(vm21) i(vm33) \end_layout \begin_layout Plain Layout plot i(vm)-i(vm21) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Capacitor or inductor with initial conditions \end_layout \begin_layout Standard The simulator supports the specification of voltage and current initial conditions on capacitor and inductor models, respectively. \emph on These models are not the standard ones supplied with SPICE3, but are in fact code models that can be substituted for the SPICE models when realistic initial conditions are required \emph default . For details please refer to Chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Behavioral-Modeling" nolink "false" \end_inset . A XSPICE deck example using these models is shown below: \end_layout \begin_layout LyX-Code * \end_layout \begin_layout LyX-Code * This circuit contains a capacitor and an inductor with \end_layout \begin_layout LyX-Code * initial conditions on them. Each of the components \end_layout \begin_layout LyX-Code * has a parallel resistor so that an exponential decay \end_layout \begin_layout LyX-Code * of the initial condition occurs with a time constant of \end_layout \begin_layout LyX-Code * 1 second. \end_layout \begin_layout LyX-Code * \end_layout \begin_layout LyX-Code a1 1 0 cap \end_layout \begin_layout LyX-Code .model cap capacitoric (c=1000uf ic=1) \end_layout \begin_layout LyX-Code r1 1 0 1k \end_layout \begin_layout LyX-Code * \end_layout \begin_layout LyX-Code a2 2 0 ind \end_layout \begin_layout LyX-Code .model ind inductoric (l=1H ic=1) \end_layout \begin_layout LyX-Code r2 2 0 1.0 \end_layout \begin_layout LyX-Code * \end_layout \begin_layout LyX-Code .control \end_layout \begin_layout LyX-Code tran 0.01 3 \end_layout \begin_layout LyX-Code plot v(1) v(2) \end_layout \begin_layout LyX-Code .endc \end_layout \begin_layout LyX-Code .end \end_layout \begin_layout LyX-Code \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Switches" \end_inset Switches \end_layout \begin_layout Standard Two types of switches are available: a voltage controlled switch (type SXXXXXX, model SW) and a current controlled switch (type WXXXXXXX, model CSW). A switching hysteresis may be defined, as well as on- and off-resistances ( \begin_inset Formula $0 \end_layout \begin_layout Plain Layout WYYYYYYY N+ N- VNAM MODEL \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout s1 1 2 3 4 switch1 ON \end_layout \begin_layout Plain Layout s2 5 6 3 0 sm2 off \end_layout \begin_layout Plain Layout Switch1 1 2 10 0 smodel1 \end_layout \begin_layout Plain Layout w1 1 2 vclock switchmod1 \end_layout \begin_layout Plain Layout W2 3 0 vramp sm1 ON \end_layout \begin_layout Plain Layout wreset 5 6 vclck lossyswitch OFF \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Nodes 1 and 2 are the nodes between which the switch terminals are connected. The model name is mandatory while the initial conditions are optional. For the voltage controlled switch, nodes 3 and 4 are the positive and negative controlling nodes respectively. For the current controlled switch, the controlling current is that through the specified voltage source. The direction of positive controlling current flow is from the positive node, through the source, to the negative node. \end_layout \begin_layout Standard The instance parameters ON or OFF are required, when the controlling voltage (current) starts inside the range of the hysteresis loop (different outputs during forward vs. backward voltage or current ramp). Then ON or OFF determine the initial state of the switch. \end_layout \begin_layout Subsection Switch Model (SW/CSW) \end_layout \begin_layout Standard The switch model allows an almost ideal switch to be described in ngspice. The switch is not quite ideal, in that the resistance can not change from 0 to infinity, but must always have a finite positive value. By proper selection of the on and off resistances, they can be effectively zero and infinity in comparison to other circuit elements. The parameters available are shown below. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Switch model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout threshold voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout threshold current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout hysteresis voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout hysteresis current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RON \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout on resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SW,CSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ROFF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout off resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e+12 (*) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SW,CSW \end_layout \end_inset \end_inset \end_layout \begin_layout Standard (*) Or \begin_inset Formula $1/GMIN$ \end_inset , if you have set \begin_inset Formula $GMIN$ \end_inset to any other value, see the \family typewriter .OPTIONS \family default control line ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:DC-Solution-Options" nolink "false" \end_inset ) for a description of \begin_inset Formula $GMIN$ \end_inset , its default value results in an off-resistance of 1.0e+12 ohms. \end_layout \begin_layout Standard The use of an ideal element that is highly nonlinear such as a switch can cause large discontinuities to occur in the circuit node voltages. A rapid change such as that associated with a switch changing state can cause numerical round-off or tolerance problems leading to erroneous results or time step difficulties. The user of switches can improve the situation by taking the following steps: \end_layout \begin_layout Itemize First, it is wise to set the ideal switch impedance just high or low enough to be negligible with respect to other circuit elements. Using switch impedances that are close to `ideal' in all cases aggravates the problem of discontinuities mentioned above. Of course, when modeling real devices such as MOSFETS, the on resistance should be adjusted to a realistic level depending on the size of the device being modeled. \end_layout \begin_layout Itemize If a wide range of ON to OFF resistance must be used in the switches (ROFF/RON \family typewriter > 1e+12 \family default ), then the tolerance on errors allowed during transient analysis should be decreased by using the \family typewriter .OPTIONS \family default control line and specifying \family typewriter \series bold TRTOL \family default \series default to be less than the default value of 7.0. \end_layout \begin_layout Itemize When switches are placed around capacitors, then the option \family typewriter \series bold CHGTOL \family default \series default should also be reduced. Suggested values for these two options are 1.0 and 1e-16 respectively. These changes inform ngspice to be more careful around the switch points so that no errors are made due to the rapid change in the circuit. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example input file: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Switch test \end_layout \begin_layout Plain Layout .tran 2us 5ms \end_layout \begin_layout Plain Layout *switch control voltage \end_layout \begin_layout Plain Layout v1 1 0 DC 0.0 PWL(0 0 2e-3 2 4e-3 0) \end_layout \begin_layout Plain Layout *switch control voltage starting inside hysteresis window \end_layout \begin_layout Plain Layout *please note influence of instance parameters ON, OFF \end_layout \begin_layout Plain Layout v2 2 0 DC 0.0 PWL(0 0.9 2e-3 2 4e-3 0.4) \end_layout \begin_layout Plain Layout *switch control current \end_layout \begin_layout Plain Layout i3 3 0 DC 0.0 PWL(0 0 2e-3 2m 4e-3 0) $ <--- switch control current \end_layout \begin_layout Plain Layout *load voltage \end_layout \begin_layout Plain Layout v4 4 0 DC 2.0 \end_layout \begin_layout Plain Layout *input load for current source i3 \end_layout \begin_layout Plain Layout r3 3 33 10k \end_layout \begin_layout Plain Layout vm3 0 33 dc 0 $ <--- measure the current \end_layout \begin_layout Plain Layout * ouput load resistors \end_layout \begin_layout Plain Layout r10 4 10 10k \end_layout \begin_layout Plain Layout r20 4 20 10k \end_layout \begin_layout Plain Layout r30 4 30 10k \end_layout \begin_layout Plain Layout r40 4 40 10k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout s1 10 0 1 0 switch1 OFF \end_layout \begin_layout Plain Layout s2 20 0 2 0 switch1 OFF \end_layout \begin_layout Plain Layout s3 30 0 2 0 switch1 ON \end_layout \begin_layout Plain Layout .model switch1 sw vt=1 vh=0.2 ron=1 roff=10k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout w1 40 0 vm3 wswitch1 off \end_layout \begin_layout Plain Layout .model wswitch1 csw it=1m ih=0.2m ron=1 roff=10k \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout set xbrushwidth=3 \end_layout \begin_layout Plain Layout plot v(1) v(10) \end_layout \begin_layout Plain Layout plot v(10) vs v(1) retraceplot $ <-- get hysteresis loop \end_layout \begin_layout Plain Layout plot v(2) v(20) $ <--- different initial values \end_layout \begin_layout Plain Layout plot v(20) vs v(2) retraceplot $ <-- get hysteresis loop \end_layout \begin_layout Plain Layout plot v(2) v(30) $ <--- different initial values \end_layout \begin_layout Plain Layout plot v(30) vs v(2) retraceplot $ <-- get hysteresis loop \end_layout \begin_layout Plain Layout plot v(40) vs vm3#branch retraceplot $ <--- current controlled switch hysteresis \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Chapter Voltage and Current Sources \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Independent-Sources-for" \end_inset Independent Sources for Voltage or Current \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout VXXXXXXX N+ N- < DC/TRAN VALUE> >> \end_layout \begin_layout Plain Layout + >> >> \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout IYYYYYYY N+ N- < DC/TRAN VALUE> >> \end_layout \begin_layout Plain Layout + >> >> \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout VCC 10 0 DC 6 \end_layout \begin_layout Plain Layout VIN 13 2 0.001 AC 1 SIN(0 1 1MEG) \end_layout \begin_layout Plain Layout ISRC 23 21 AC 0.333 45.0 SFFM(0 1 10K 5 1K) \end_layout \begin_layout Plain Layout VMEAS 12 9 \end_layout \begin_layout Plain Layout VCARRIER 1 0 DISTOF1 0.1 -90.0 \end_layout \begin_layout Plain Layout VMODULATOR 2 0 DISTOF2 0.01 \end_layout \begin_layout Plain Layout IIN1 1 5 AC 1 DISTOF1 DISTOF2 0.001 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive and negative nodes, respectively. Note that voltage sources need not be grounded. Positive current is assumed to flow from the positive node, through the source, to the negative node. A current source of positive value forces current to flow out of the \family typewriter \series bold n+ \family default \series default node, through the source, and into the \family typewriter \series bold n- \family default \series default node. Voltage sources, in addition to being used for circuit excitation, are the `ammeters' for ngspice, that is, zero valued voltage sources may be inserted into the circuit for the purpose of measuring current. They of course have no effect on circuit operation since they represent short-circuits. \end_layout \begin_layout Standard \family typewriter \series bold DC \family default \series default / \family typewriter \series bold TRAN \family default \series default is the dc and transient analysis value of the source. If the source value is zero both for dc and transient analyses, this value may be omitted. If the source value is time-invariant (e.g., a power supply), then the value may optionally be preceded by the letters DC. \end_layout \begin_layout Standard The keyword \family typewriter \series bold AC \family default \series default together with its value \family typewriter \series bold ACMAG \family default \series default (and optional value \family typewriter \series bold ACPHASE \family default \series default ) are required when the voltage or current source is intended to become the small signal source in an ac simulation. \family typewriter \series bold ACMAG \family default \series default is the ac magnitude and \family typewriter \series bold ACPHASE \family default \series default is the ac phase. The voltage or current source then will become a reference for all nodes. All small signal node amplitude values obtained after the simulation have been divided by the reference \family typewriter \series bold ACMAG \family default \series default . A typcal \family typewriter \series bold ACMAG \family default \series default value thus may be unity. Any measured phase has been shifted by \family typewriter \series bold ACPHASE \family default \series default . If \family typewriter \series bold ACPHASE \family default \series default is omitted, a value of zero is assumed. If the source is not an ac small-signal input, the keyword \family typewriter \series bold AC \family default \series default and the ac values are to be avoided. \end_layout \begin_layout Standard \family typewriter \series bold DISTOF1 \family default \series default and \family typewriter \series bold DISTOF2 \family default \series default are the keywords that specify that the independent source has distortion inputs at the frequencies \family typewriter \series bold F1 \family default \series default and \family typewriter \series bold F2 \family default \series default respectively (see the description of the \family typewriter .DISTO \family default control line). The keywords may be followed by an optional magnitude and phase. The default values of the magnitude and phase are 1.0 and 0.0 respectively. \end_layout \begin_layout Standard Any independent source can be assigned a time-dependent value for transient analysis. If a source is assigned a time-dependent value, the time-zero value is used for dc analysis. There are nine independent source functions: \end_layout \begin_layout Itemize pulse, \end_layout \begin_layout Itemize exponential, \end_layout \begin_layout Itemize sinusoidal, \end_layout \begin_layout Itemize piece-wise linear, \end_layout \begin_layout Itemize single-frequency FM, \end_layout \begin_layout Itemize AM, \end_layout \begin_layout Itemize transient noise, \end_layout \begin_layout Itemize random voltages or currents, \end_layout \begin_layout Itemize external data (only with ngspice shared library), \end_layout \begin_layout Itemize and RF port \end_layout \begin_layout Standard If parameters other than source values are omitted or set to zero, the default values shown are assumed. \family typewriter \series bold TSTEP \family default \series default is the printing increment and \family typewriter \series bold TSTOP \family default \series default is the final time – see the \family typewriter .TRAN \family default control line for an explanation. \end_layout \begin_layout Subsection Pulse \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout PULSE(V1 V2 TD TR TF PW PER NP) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout VIN 3 0 PULSE(-1 1 2NS 2NS 2NS 50NS 100NS 5) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default Value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Initial value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Pulsed value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Delay time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Rise time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTEP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Fall time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTEP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Pulse width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTOP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PER \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Period \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTOP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number of Pulses *) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout unlimited \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \end_inset \end_layout \begin_layout Standard A single pulse, without repetition count or phase offset, is described by the following table: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD+TR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD+TR+PW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD+TR+PW+TF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTOP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V1 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Intermediate points are determined by linear interpolation. \end_layout \begin_layout Standard *) \family sans NP \family default set to 0 or omitted denotes unlimited pulses. If compatibility mode (see \family sans \family default \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode" nolink "false" \end_inset ) \family sans set ngbehavior=xs \family default is set in .spiceinit, the 8th parameter is the phase of the pulse signal (in degrees), which results in forward running (pos. value) or a delay (neg. value) of the pulse sequence. \end_layout \begin_layout Subsection Sinusoidal \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout SIN(VO VA FREQ TD THETA PHASE) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout VIN 3 0 SIN(0 1 100MEG 1NS 1E10) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default Value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Offset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Amplitude \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FREQ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Frequency \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{TSTOP}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Delay \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout THETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Damping factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PHASE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Phase \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout degrees \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The shape of the waveform is described by the following formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} V\left(t\right)=\begin{cases} V0 & \mathrm{if\;0\leq t} \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default Value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Initial value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout pulsed value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout rise delay time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TAU1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout rise time constant \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTEP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout fall delay time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD1+TSTEP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TAU2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout fall time constant \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TSTEP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The shape of the waveform is described by the following formula: \end_layout \begin_layout Standard Let \begin_inset Formula $V21=V2-V1\text{,}\:V12=V1-V2$ \end_inset : \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} V\left(t\right)=\begin{cases} V1 & \mathrm{if}\;0\leq t) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout VCLOCK 7 5 PWL(0 -7 10NS -7 11NS -3 17NS -3 18NS -7 50NS -7) \end_layout \begin_layout Plain Layout + r=0 td=15NS \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Each pair of values ( \begin_inset Formula $T_{i}$ \end_inset , \begin_inset Formula $V_{i}$ \end_inset ) specifies that the value of the source is \begin_inset Formula $V_{i}$ \end_inset (in Volts or Amps) at time = \begin_inset Formula $T_{i}$ \end_inset . The value of the source at intermediate values of time is determined by using linear interpolation on the input values. The parameter \emph on r \emph default determines a repeat time point. If \emph on r \emph default is set to -1 or is not given, the whole sequence of values ( \begin_inset Formula $T_{i}$ \end_inset , \begin_inset Formula $V_{i}$ \end_inset ) is issued once only, then the output stays at its final value. If \shape italic r = 0 \shape default , the whole sequence from time 0 to time \shape italic Tn \shape default is repeated forever. If \shape italic r = 10ns \shape default , the sequence between 10ns and 50ns is repeated forever. The \emph on r \emph default value has to be one of the time points T1 to T(n-1) of the PWL sequence, not the last point Tn. If \emph on td \emph default is given, the whole PWL sequence is delayed by the value of \shape italic td \shape default . Please note that for now \emph on r \emph default and \emph on td \emph default are available only with the voltage source, not with the current source. \end_layout \begin_layout Subsection Single-Frequency FM \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout SFFM(VO VA FC MDI FM TD PHASEM PHASEC) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout V1 12 0 SFFM(0 2 20 45 1k 1m 0 0) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Offset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Amplitude \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Carrier frequency \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{500}{TSTOP}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MDI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Modulation index \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 90 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Modulating frequency \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{5}{TSTOP}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Signal delay \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $s$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PHASEM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Modulation signal phase \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout degrees \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PHASEC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Carrier signal phase \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout degrees \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The shape of the waveform is described by the following equation: \end_layout \begin_layout Standard \begin_inset Formula \begin{multline} V(t)=V_{O}+V_{A}\cdot\\ \sin\left(2\pi\cdot FC\cdot(t-TD)+MDI\:\sin\left(2\pi\cdot FM\cdot(t-TD)+PHASEM\right)+PHASEC\right) \end{multline} \end_inset \end_layout \begin_layout Standard with \begin_inset Formula $t>TD$ \end_inset , else \begin_inset Formula $V(t)=0$ \end_inset . \end_layout \begin_layout Standard MDI is limited to \begin_inset Formula $0<=MDI<=FC/FM$ \end_inset . VO and VA have to be given always. \end_layout \begin_layout Subsection Amplitude modulated source (AM) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout AM(VO VMO VMA FM FC TD PHASEM PHASEC) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout V1 12 0 AM(0.5 2 1.8 20K 5MEG 1m) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Overall offset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VMO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Modulation signal offset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VMA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Modulation signal amplitude \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Modulation signal frequency \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{5}{TSTOP}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Carrier signal frequency \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{500}{TSTOP}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Overall delay \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $s$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PHASEM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Modulation signal phase \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout degrees \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PHASEC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Carrier signal phase \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout degrees \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The shape of the waveform is described by the following equation: \end_layout \begin_layout Standard \begin_inset Formula \begin{multline} V(t)=VO+\left(VMO+VMA\cdot\sin\left(2\pi\cdot FM\cdot(t-TD)+PHASEM\right)\right)\cdot\\ \sin\left(2\pi\cdot FC\cdot(t-TD)+PHASEC\right) \end{multline} \end_inset \end_layout \begin_layout Standard with \begin_inset Formula $t>TD$ \end_inset , else \begin_inset Formula $V(t)=0$ \end_inset . \end_layout \begin_layout Standard VO and VMO have to be given always. \end_layout \begin_layout Standard With the modulation depth, given by \begin_inset Formula $VMA/VMO$ \end_inset , varied between 0 and 1, a standard amplitude modulated signal is provided. VMO then also acts as overall multiplier to the signal. On the other hand one may set VMO to 0, then obtaining a signal with double side band and suppressed carrier. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Transient-noise-source" \end_inset Transient noise source \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout TRNOISE(NA NT NALPHA NAMP RTSAM RTSCAPT RTSEMT) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout VNoiw 1 0 DC 0 TRNOISE(20n 0.5n 0 0) $ white \end_layout \begin_layout Plain Layout VNoi1of 1 0 DC 0 TRNOISE(0 10p 1.1 12p) $ 1/f \end_layout \begin_layout Plain Layout VNoiw1of 1 0 DC 0 TRNOISE(20 10p 1.1 12p) $ white and 1/f \end_layout \begin_layout Plain Layout IALL 10 0 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u) \end_layout \begin_layout Plain Layout $ white, 1/f, RTS \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Transient noise is an experimental feature allowing (low frequency) transient noise injection and analysis. See Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Transient-noise-analysis" nolink "false" \end_inset for a detailed description. \family typewriter NA \family default is the Gaussian noise rms voltage amplitude, \family typewriter NT \family default is the time between sample values (breakpoints will be enforced on multiples of this value). \family typewriter NALPHA \family default (exponent to the frequency dependency), \family typewriter NAMP \family default (rms voltage or current amplitude) are the parameters for 1/f noise, \family typewriter RTSAM \family default the random telegraph signal amplitude, \family typewriter RTSCAPT \family default the mean of the exponential distribution of the trap capture time, and \family typewriter RTSEMT \family default its emission time mean. White Gaussian, 1/f, and \family typewriter RTS \family default noise may be combined into a single statement. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Rms noise amplitude (Gaussian) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Time step \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $sec$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NALPHA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1/f exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $0<\alpha<2$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NAMP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Amplitude (1/f) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RTSAM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Amplitude \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset , \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RTSCAPT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Trap capture time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $sec$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RTSEMT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Trap emission time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $sec$ \end_inset \end_layout \end_inset \end_inset \end_layout \begin_layout Standard If you set \family typewriter NT \family default and \family typewriter RTSAM \family default to 0, the noise option \family typewriter TRNOISE \family default ... is ignored. Thus you may switch off the noise contribution of an individual voltage source \family typewriter VNOI \family default by the command \end_layout \begin_layout Standard \family typewriter alter @vnoi[trnoise] = [ 0 0 0 0 ] $ no noise \end_layout \begin_layout Standard \family typewriter alter @vrts[trnoise] = [ 0 0 0 0 0 0 0] $ no noise \end_layout \begin_layout Standard See Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Alter*:-Change-a" nolink "false" \end_inset for the alter command. \end_layout \begin_layout Standard You may switch off all \family typewriter TRNOISE \family default noise sources by setting \end_layout \begin_layout Standard \family typewriter set notrnoise \end_layout \begin_layout Standard to your \family sans .spiceinit \family default file (for all your simulations) or into your control section in front of the next run or tran command (for this specific and all following simulations). The command \end_layout \begin_layout Standard \family typewriter unset notrnoise \end_layout \begin_layout Standard will reinstate all noise sources. \end_layout \begin_layout Standard The noise generators are implemented into the independent \series bold voltage \series default (vsrc) and \series bold current \series default (isrc) sources. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Random-voltage-source" \end_inset Random voltage source \end_layout \begin_layout Standard The \family typewriter TRRANDOM \family default option yields statistically distributed voltage values, derived from the ngspice random number generator. These values may be used in the transient simulation directly within a circuit, e.g. for generating a specific noise voltage, but especially they may be used in the control of behavioral sources (B, E, G sources \begin_inset CommandInset ref LatexCommand ref reference "sec:Non-linear-Dependent-Sources" nolink "false" \end_inset , voltage controllable A sources \begin_inset CommandInset ref LatexCommand ref reference "cha:Behavioral-Modeling" nolink "false" \end_inset , capacitors \begin_inset CommandInset ref LatexCommand ref reference "subsec:Capacitors,-dependent-on" nolink "false" \end_inset , inductors \begin_inset CommandInset ref LatexCommand ref reference "subsec:Inductors,-dependent-on" nolink "false" \end_inset , or resistors \begin_inset CommandInset ref LatexCommand ref reference "subsec:Resistors,-dependent-on" nolink "false" \end_inset ) to simulate the circuit dependence on statistically varying device parameters. A Monte-Carlo simulation may thus be handled in a single simulation run. \end_layout \begin_layout Standard General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout TRRANDOM(TYPE TS >>) \end_layout \end_inset \end_layout \begin_layout Standard Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout VR1 r1 0 dc 0 trrandom (2 10m 0 1) ; Gaussian with mean 0 \end_layout \begin_layout Plain Layout V1 1 0 dc 0 trrandom (1 1u 0.5u 0.5 0.5) ; Uniform between 0 and 1 \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter TYPE \family default determines the random variates generated: 1 is uniformly distributed, 2 Gaussian, 3 exponential, 4 Poisson. \family typewriter TS \family default is the duration of an individual voltage value. \family typewriter TD \family default is a time delay with the output staying at the Offset or Mean value, before the random voltage values start up. \end_layout \begin_layout Standard \family typewriter PARAM1 \family default and \family typewriter PARAM2 \family default depend on the type selected. The uniform distribution issues values in the range of ± \family typewriter PARAM1 \family default around the offset \family typewriter PARAM2 \family default . The Gaussian distribution issues values with the standard deviation of \family typewriter PARAM1 \family default around the mean \family typewriter PARAM2 \family default . \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout TYPE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PARAM1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PARAM2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Uniform \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Range \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Offset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gaussian \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Standard Dev. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mean \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Exponential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mean \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Offset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Poisson \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lambda \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Offset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:External-voltage-or" \end_inset External voltage or current input \end_layout \begin_layout Standard General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout EXTERNAL \end_layout \end_inset \end_layout \begin_layout Standard Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Vex 1 0 dc 0 external \end_layout \begin_layout Plain Layout Iex i1 i2 dc 0 external \end_layout \end_inset \end_layout \begin_layout Standard Voltages or currents may be set from the calling process, if ngspice is compiled as a shared library and loaded by the process. See Chapter \begin_inset CommandInset ref LatexCommand ref reference "chap:ngspice-as-shared" plural "false" caps "false" noprefix "false" nolink "false" \end_inset and \begin_inset CommandInset ref LatexCommand ref reference "GetVSRCData" plural "false" caps "false" noprefix "false" nolink "false" \end_inset for an explanation. \end_layout \begin_layout Subsection Arbitrary Phase Sources \end_layout \begin_layout Standard ngspice supports arbitrary phase independent sources that output at TIME=0.0 a value corresponding to some specified phase shift. Other versions of SPICE use the TD (delay time) parameter to set phase-shifted sources to their time-zero value until the delay time has elapsed. The ngspice phase parameter is specified in degrees and is included after the SPICE3 parameters normally used to specify an independent source. Partial examples of usage for pulse and sine waveforms are shown below: \end_layout \begin_layout LyX-Code * Phase shift is specified as final parameter \end_layout \begin_layout LyX-Code * on the independent source cards. Phase shift for both of the \end_layout \begin_layout LyX-Code * following is specified as +45 degrees \end_layout \begin_layout LyX-Code * \end_layout \begin_layout LyX-Code v1 1 0 0.0 sin(0 1 1k 0 0 45.0) \end_layout \begin_layout LyX-Code r1 1 0 1k \end_layout \begin_layout LyX-Code * \end_layout \begin_layout LyX-Code v2 2 0 0.0 pulse(-1 1 0 1e-5 1e-5 5e-4 1e-3 45.0) \end_layout \begin_layout LyX-Code r2 2 0 1k \end_layout \begin_layout LyX-Code * \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:RF-Port" \end_inset RF Port \end_layout \begin_layout Standard A voltage source VSRC may be defined as RF Port. To do so, there are at least two more parameters required. The first is portnum (integer) which defines the VSRC as a RF Port. Portnum of all VSRCs defined as RF ports must start from 1 and count up to the number of RF ports. You cannot have duplicate portnums. Then you have Z0 (real) which defines the internal impedance. If not provided, its default value is 50Ohm. When declaring a RF ports, the VSRC now become a VSRC with Z0 Ohm in series. This extra resistor affects all simulations. \end_layout \begin_layout Standard General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout DC 0 AC 1 portnum n1 \end_layout \end_inset \end_layout \begin_layout Standard Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout V1 in 0 dc 0 ac 1 portnum 1 z0 100 \end_layout \end_inset \end_layout \begin_layout Standard At least two ports are required for the S-parameter simulation with the command \family typewriter .sp \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.SP-S-Parameter" nolink "false" \end_inset ). If portnum is not provided, the voltage source VRSC behaves as normal. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Linear-Dependent-Sources" \end_inset Linear Dependent Sources \end_layout \begin_layout Standard Ngspice allows circuits to contain linear dependent sources characterized by any of the four equations \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $i=gv$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $v=ev$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $i=fi$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $v=hi$ \end_inset \end_layout \end_inset \end_inset \end_layout \begin_layout Standard where \begin_inset Formula $g$ \end_inset , \begin_inset Formula $e$ \end_inset , \begin_inset Formula $f$ \end_inset , and \begin_inset Formula $h$ \end_inset are constants representing transconductance, voltage gain, current gain, and transresistance, respectively. Non-linear dependent sources for voltages or currents (B, E, G) are described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Non-linear-Dependent-Sources" nolink "false" \end_inset . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Gxxxx:-Linear-Voltage-Controlled" \end_inset Gxxxx: Linear Voltage-Controlled Current Sources (VCCS) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout GXXXXXXX N+ N- NC+ NC- VALUE \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout G1 2 0 5 0 0.1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive and negative nodes, respectively. Current flow is from the positive node, through the source, to the negative \end_layout \begin_layout Standard node. \family typewriter \series bold nc+ \family default \series default and \family typewriter \series bold nc- \family default \series default are the positive and negative controlling nodes, respectively. \family typewriter \series bold value \family default \series default is the transconductance (in mhos). \family typewriter m \family default is an optional multiplier to the output current. \family typewriter val \family default may be a numerical value or an expression according to \begin_inset CommandInset ref LatexCommand ref reference "subsec:Syntax-of-expressions" nolink "false" \end_inset containing references to other parameters. Instance parameters are listed in chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Gxxxx:-Voltage-Controlled-Curren" nolink "false" \end_inset . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Exxxx:-Linear-Voltage-Controlled" \end_inset Exxxx: Linear Voltage-Controlled Voltage Sources (VCVS) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout EXXXXXXX N+ N- NC+ NC- VALUE \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout E1 2 3 14 1 2.0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n+ \family default \series default is the positive node, and \family typewriter \series bold n- \family default \series default is the negative node. \family typewriter \series bold nc+ \family default \series default and \family typewriter \series bold nc- \family default \series default are the positive and negative controlling nodes, respectively. \family typewriter \series bold value \family default \series default is the voltage gain. Instance parameters are listed in chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Exxxx:-Voltage-Controlled-Voltag" nolink "false" \end_inset . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Fxxxx:-Linear-Current-Controlled" \end_inset Fxxxx: Linear Current-Controlled Current Sources (CCCS) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout FXXXXXXX N+ N- VNAM VALUE \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout F1 13 5 VSENS 5 m=2 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive and negative nodes, respectively. Current flow is from the positive node, through the source, to the negative node. \family typewriter \series bold vnam \family default \series default is the name of a voltage source through which the controlling current flows. The direction of positive controlling current flow is from the positive node, through the source, to the negative node of \family typewriter \series bold vnam \family default \series default . \family typewriter \series bold value \family default \series default is the current gain. \family typewriter m \family default is an optional multiplier to the output current. Instance parameters are listed in chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Fxxxx:-Current-Controlled-Curren" nolink "false" \end_inset . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Hxxxx:-Linear-Current-Controlled" \end_inset Hxxxx: Linear Current-Controlled Voltage Sources (CCVS) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout HXXXXXXX N+ N- VNAM VALUE \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout HX 5 17 VZ 0.5K \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive and negative nodes, respectively. \family typewriter \series bold vnam \family default \series default is the name of a voltage source through which the controlling current flows. The direction of positive controlling current flow is from the positive node, through the source, to the negative node of \family typewriter \series bold vnam \family default \series default . \family typewriter \series bold value \family default \series default is the transresistance (in ohms). Instance parameters are listed in chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Hxxxx:-Current-Controlled-Voltag" nolink "false" \end_inset . \end_layout \begin_layout Subsection Polynomial Source Compatibility \end_layout \begin_layout Standard Dependent polynomial sources available in SPICE2G6 are fully supported in ngspice using the XSPICE extension ( \begin_inset CommandInset ref LatexCommand ref reference "sec:ngspice-with-the" nolink "false" \end_inset ). The form used to specify these sources is shown in Table \begin_inset CommandInset ref LatexCommand ref reference "cap:Dependent-Polynomial-Sources" nolink "false" \end_inset . For details on its usage please see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:POLY" nolink "false" \end_inset . \end_layout \begin_layout Standard \begin_inset Float table placement h alignment document wide false sideways false status open \begin_layout Plain Layout \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Dependent Polynomial Sources \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Source Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Instance Card \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none POLYNOMIAL VCVS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none EXXXXXXX N+ N- POLY(ND) NC1+ NC1- P0 (P1...) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none POLYNOMIAL VCCS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none GXXXXXXX N+ N- POLY(ND) NC1+ NC1- P0 (P1...) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none POLYNOMIAL CCCS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none FXXXXXXX N+ N- POLY(ND) VNAM1 !VNAM2...? P0 (P1...) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none POLYNOMIAL CCVS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none HXXXXXXX N+ N- POLY(ND) VNAM1 !VNAM2...? P0 (P1...) \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "cap:Dependent-Polynomial-Sources" \end_inset Dependent Polynomial Sources \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "sec:Non-linear-Dependent-Sources" \end_inset Non-linear Dependent Sources (Behavioral Sources) \end_layout \begin_layout Standard The non-linear dependent sources B ( see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" nolink "false" \end_inset ), E (see \begin_inset CommandInset ref LatexCommand ref reference "sec:E-source-(non-linear" nolink "false" \end_inset ), G see ( \begin_inset CommandInset ref LatexCommand ref reference "sec:G-source-(non-linear" nolink "false" \end_inset ) described in this chapter allow the generation of voltages or currents that result from evaluating a mathematical expression. Internally E and G sources are converted to the more general B source. All three sources may be used to introduce behavioral modeling and analysis. \end_layout \begin_layout Section \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Parsers for expressions ! B source parser \end_layout \end_inset \begin_inset CommandInset label LatexCommand label name "sec:B-source-(ASRC)" \end_inset Bxxxx: Nonlinear dependent source (ASRC) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Syntax-and-usage" \end_inset Syntax and usage \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout BXXXXXXX n+ n- \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout B1 0 1 I=cos(v(1))+sin(v(2)) \end_layout \begin_layout Plain Layout B2 0 1 V=ln(cos(log(v(1,2)^2)))-v(3)^4+v(2)^v(1) \end_layout \begin_layout Plain Layout B3 3 4 I=17 \end_layout \begin_layout Plain Layout B4 3 4 V=exp(pi^i(vdd)) \end_layout \begin_layout Plain Layout B5 2 0 V = V(1) < {Vlow} ? {Vlow} : \end_layout \begin_layout Plain Layout + V(1) > {Vhigh} ? {Vhigh} : V(1) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n+ \family default \series default is the positive node, and \family typewriter \series bold n- \family default \series default is the negative node. The values of the \family typewriter \series bold V \family default \series default and \family typewriter \series bold I \family default \series default parameters determine the voltages and currents across and through the device, respectively. If \family typewriter \series bold I \family default \series default is given then the device is a current source, and if \family typewriter \series bold V \family default \series default is given the device is a voltage source. One and only one of these parameters must be given. All instance parameters are listed in chapter \begin_inset CommandInset ref LatexCommand ref reference "subsec:Bxxx---Arbitrary" nolink "false" \end_inset . \end_layout \begin_layout Standard A simple model is implemented for temperature behavior by the formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} I(T)=I({\mathrm{TNOM}})\:\Bigl(1+TC_{1}(T-{\mathrm{TNOM}})+TC_{2}(T-{\mathrm{TNOM}})^{2}\Bigr) \end{equation} \end_inset \end_layout \begin_layout Standard or \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} V(T)=V({\mathrm{TNOM}})\Bigl(1+TC_{1}(T-{\mathrm{TNOM}})+TC_{2}(T-{\mathrm{TNOM}})^{2}\Bigr) \end{equation} \end_inset \end_layout \begin_layout Standard In the above formula, ` \begin_inset Formula $T$ \end_inset ' represents the instance temperature, which can be explicitly set using the \family typewriter \series bold temp \family default \series default keyword or calculated using the circuit temperature and \family typewriter \series bold dtemp \family default \series default , if present. If both \family typewriter \series bold temp \family default \series default and \family typewriter \series bold dtemp \family default \series default are specified, the latter is ignored. \end_layout \begin_layout Standard The small-signal AC behavior of the nonlinear source is a linear dependent source (or sources) with a proportionality constant equal to the derivative (or derivatives) of the source at the DC operating point. The expressions given for \family typewriter \series bold V \family default \series default and \family typewriter \series bold I \family default \series default may be any function of voltages and currents through voltage sources in the system. \end_layout \begin_layout Standard The following functions of a single real variable are defined: \end_layout \begin_layout Description Trigonometric \begin_inset space ~ \end_inset functions: cos, sin, tan, acos, asin, atan \end_layout \begin_layout Description Hyperbolic \begin_inset space ~ \end_inset functions: cosh, sinh, acosh, asinh, atanh \end_layout \begin_layout Description Exponential \begin_inset space ~ \end_inset and \begin_inset space ~ \end_inset logarithmic: exp, ln, log, log10 (ln, log with base e, log10 with base 10) \end_layout \begin_layout Description Other: abs, sqrt, u, u2, uramp, floor, ceil, i \end_layout \begin_layout Description Functions of two variables are min, max, pow, **, pwr, ^ \end_layout \begin_layout Description Functions of three variables are a ? b:c \end_layout \begin_layout Standard For convergence reasons the `exp' function has a limit of 14 for its argument, beyond that value it will increase linearily. The function ` \family typewriter u \family default ' is the unit step function, with a value of one for arguments greater than zero, a value of 0.5 at zero, and a value of zero for arguments less than zero. The function ` \family typewriter u2 \family default ' returns a value of zero for arguments less than zero, one for arguments greater than one and assumes the value of the argument between these limits. The function ` \family typewriter uramp \family default ' is the integral of the unit step: for an input x, the value is zero if x is less than zero, or, if x is greater than or equal to zero, the value is x. These three functions are useful in synthesizing piece-wise non-linear functions, though convergence may be adversely affected. \end_layout \begin_layout Standard The function \family typewriter i(xyz) \family default returns the current through the first node of device instance xyz. \end_layout \begin_layout Standard The following standard operators are defined: \family typewriter + \family default , \family typewriter - \family default , \family typewriter * \family default , \family typewriter / \family default , \family typewriter ^ \family default , unary \family typewriter - \end_layout \begin_layout Standard Logical operators are \family typewriter != \family default , \family typewriter <> \family default , \family typewriter >= \family default , \family typewriter <= \family default , \family typewriter == \family default , \family typewriter > \family default , \family typewriter < \family default , \family typewriter || \family default , \family typewriter && \family default , \family typewriter ! \family default . \end_layout \begin_layout Standard A ternary function is defined as \family typewriter a ? b : c \family default , which means \family typewriter IF a, THEN b, ELSE c \family default . Be sure to place a space in front of ` \family typewriter ? \family default ' to allow the parser distinguishing it from other tokens. \end_layout \begin_layout Standard The B source functions \family typewriter pow \family default , \family typewriter ** \family default , \family typewriter ^ \family default , and \family typewriter pwr \family default need some special care to avoid undefined regions in \family typewriter x1 \family default , as they differ from the common mathematical usage (and from the functions depicted in chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Syntax-of-expressions" nolink "false" \end_inset ). \end_layout \begin_layout Standard The functions \family typewriter y = pow \family default (x1,x2), \family typewriter x1** \family default x2, and \family typewriter x1^x2 \family default , all of them describing \begin_inset Formula $y=x1^{x2}$ \end_inset , resolve to the following: \end_layout \begin_layout LyX-Code y = pow(fabs(x1), x2) \end_layout \begin_layout Standard \family typewriter pow \family default in the preceding line is the standard C math library function. \end_layout \begin_layout Standard The function \family typewriter y = pwr(x1,x2) \family default resolves to \end_layout \begin_layout LyX-Code if (x1 < 0.0) \end_layout \begin_layout LyX-Code y = (-pow(-x1, x2)); \end_layout \begin_layout LyX-Code else \end_layout \begin_layout LyX-Code y = (pow(x1, x2)); \end_layout \begin_layout Standard \family typewriter pow \family default here again is the standard C math library function. \end_layout \begin_layout Standard \begin_inset VSpace 0.5cm \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: Ternary function \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * B source test Clamped voltage source \end_layout \begin_layout Plain Layout * C. P. Basso "Switched-mode power supplies", New York, 2008 \end_layout \begin_layout Plain Layout .param Vhigh = 4.6 \end_layout \begin_layout Plain Layout .param Vlow = 0.4 \end_layout \begin_layout Plain Layout Vin1 1 0 DC 0 PWL(0 0 1u 5) \end_layout \begin_layout Plain Layout Bcl 2 0 V = V(1) < Vlow ? Vlow : V(1) > Vhigh ? Vhigh : V(1) \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout unset askquit \end_layout \begin_layout Plain Layout tran 5n 1u \end_layout \begin_layout Plain Layout plot V(2) vs V(1) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If the argument of log, ln, or sqrt becomes less than zero, the absolute value of the argument is used. If a divisor becomes zero or the argument of log or ln becomes zero, an error will result. Other problems may occur when the argument for a function in a partial derivative enters a region where that function is undefined. \end_layout \begin_layout Standard Parameters may be used like {Vlow} shown in the example above. Parameters will be evaluated upon set up of the circuit, vectors like V(1) will be evaluated during the simulation. \end_layout \begin_layout Standard To get time into the expression you can integrate the current from a constant current source with a capacitor and use the resulting voltage (don't forget to set the initial voltage across the capacitor). \end_layout \begin_layout Standard Non-linear resistors, capacitors, and inductors may be synthesized with the nonlinear dependent source. Nonlinear resistors, capacitors and inductors are implemented with their linear counterparts by a change of variables implemented with the nonlinear dependent source. The following subcircuit will implement a nonlinear capacitor: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: Non linear capacitor \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .Subckt nlcap pos neg \end_layout \begin_layout Plain Layout * Bx: calculate f(input voltage) \end_layout \begin_layout Plain Layout Bx 1 0 v = f(v(pos,neg)) \end_layout \begin_layout Plain Layout * Cx: linear capacitance \end_layout \begin_layout Plain Layout Cx 2 0 1 \end_layout \begin_layout Plain Layout * Vx: Ammeter to measure current into the capacitor \end_layout \begin_layout Plain Layout Vx 2 1 DC 0Volts \end_layout \begin_layout Plain Layout * Drive the current through Cx back into the circuit \end_layout \begin_layout Plain Layout Fx pos neg Vx 1 \end_layout \begin_layout Plain Layout .ends \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example for f(v(pos,neg)): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Bx 1 0 V = v(pos,neg)*v(pos,neg) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Non-linear resistors or inductors may be described in a similar manner. An example for a nonlinear resistor using this template is shown below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: Non linear resistor \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * use of 'hertz' variable in nonlinear resistor \end_layout \begin_layout Plain Layout *.param rbase=1k \end_layout \begin_layout Plain Layout * some tests \end_layout \begin_layout Plain Layout B1 1 0 V = hertz*v(33) \end_layout \begin_layout Plain Layout B2 2 0 V = v(33)*hertz \end_layout \begin_layout Plain Layout b3 3 0 V = 6.283e3/(hertz+6.283e3)*v(33) \end_layout \begin_layout Plain Layout V1 33 0 DC 0 AC 1 \end_layout \begin_layout Plain Layout *** Translate R1 10 0 R='1k/sqrt(HERTZ)' to B source *** \end_layout \begin_layout Plain Layout .Subckt nlres pos neg rb=rbase \end_layout \begin_layout Plain Layout * Bx: calculate f(input voltage) \end_layout \begin_layout Plain Layout Bx 1 0 v = -1 / {rb} / sqrt(HERTZ) * v(pos, neg) \end_layout \begin_layout Plain Layout * Rx: linear resistance \end_layout \begin_layout Plain Layout Rx 2 0 1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: Non linear resistor (continued) \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * Vx: Ammeter to measure current into the resistor \end_layout \begin_layout Plain Layout Vx 2 1 DC 0Volts \end_layout \begin_layout Plain Layout * Drive the current through Rx back into the circuit \end_layout \begin_layout Plain Layout Fx pos neg Vx 1 \end_layout \begin_layout Plain Layout .ends \end_layout \begin_layout Plain Layout Xres 33 10 nlres rb=1k \end_layout \begin_layout Plain Layout *Rres 33 10 1k \end_layout \begin_layout Plain Layout Vres 10 0 DC 0 \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout define check(a,b) vecmax(abs(a - b)) \end_layout \begin_layout Plain Layout ac lin 10 100 1k \end_layout \begin_layout Plain Layout * some checks \end_layout \begin_layout Plain Layout print v(1) v(2) v(3) \end_layout \begin_layout Plain Layout if check(v(1), frequency) < 1e-12 \end_layout \begin_layout Plain Layout echo "INFO: ok" \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout plot vres#branch \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Special-B-Source-Variables" \end_inset Special B-Source Variables time, temper, hertz \end_layout \begin_layout Standard The special variables \series bold time \series default and \series bold temper \series default are available in a transient analysis, reflecting the actual simulation time and circuit temperature. \series bold temper \series default returns the circuit temperature, given in degree C (see \begin_inset CommandInset ref LatexCommand ref reference "sec:.temp" nolink "false" \end_inset ). The variable \series bold hertz \series default is available in an AC analysis. \series bold time \series default is zero in the AC analysis, \series bold hertz \series default is zero during transient analysis. Using the variable \series bold hertz \series default may cost some CPU time if you have a large circuit, because for each frequency the operating point has to be determined before calculating the AC response. \end_layout \begin_layout Subsection par( \series medium \shape italic 'expression' \series default \shape default ) \end_layout \begin_layout Standard The B source syntax may also be used in output lines like \family typewriter .plot \family default as algebraic expressions for output (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:par('expression'):-Algebraic-expressions" nolink "false" \end_inset ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:PiecewiseLinearFunction:-pwl" \end_inset Piecewise \begin_inset space ~ \end_inset Linear \begin_inset space ~ \end_inset Function: pwl \end_layout \begin_layout Standard Both B source types may contain a piece-wise linear dependency of one network variable: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \family typewriter pwl_current \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Bdio 1 0 I = pwl(v(A), 0,0, 33,10m, 100,33m, 200,50m) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard v(A) is the independent variable x. Each pair of values following describes the x,y functional relation: In this example at node A voltage of 0V the current of 0A is generated - next pair gives 10mA flowing from ground to node 1 at 33V on node A and so forth. \end_layout \begin_layout Standard The same is possible for voltage sources: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \family typewriter pwl_voltage \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Blimit b 0 V = pwl(v(1), -4,0, -2,2, 2,4, 4,5, 6,5) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Monotony of the independent variable in the pwl definition is checked - non-monotonic x entries will stop the program execution. \family typewriter v(1) \family default may be replaced by a controlling current source, or it may be replaced by \family typewriter time \family default (for transient simulations). v(1) may also be replaced by an expression, e.g. \begin_inset Formula $-2*i(V_{in})$ \end_inset . The value pairs may also be parameters, and have to be predefined by a \family typewriter .param \family default statement. An example for the pwl function using all of these options is shown below. \end_layout \begin_layout Standard \begin_inset Float figure placement H alignment document wide false sideways false status open \begin_layout Plain Layout \noindent \align center \begin_inset Graphics filename Images/Btest-pwl.png width 70line% \end_inset \begin_inset Caption Standard \begin_layout Plain Layout pwl (piece-wise linear) B source \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: pwl function in B source \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Demonstrates usage of the pwl function in an B source (ASRC) \end_layout \begin_layout Plain Layout * Also emulates the TABLE function with limits \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .param x0=-4 y0=0 \end_layout \begin_layout Plain Layout .param x1=-2 y1=2 \end_layout \begin_layout Plain Layout .param x2=2 y2=-2 \end_layout \begin_layout Plain Layout .param x3=4 y3=1 \end_layout \begin_layout Plain Layout .param xx0=x0-1 \end_layout \begin_layout Plain Layout .param xx3=x3+1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout Vin ctrl 0 DC=0V \end_layout \begin_layout Plain Layout R1 ctrl 0 2 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * no limits outside of the tabulated x values \end_layout \begin_layout Plain Layout * (continues linearily) \end_layout \begin_layout Plain Layout Btest2 2 0 I = pwl(v(ctrl),'x0','y0','x1','y1','x2','y2', \end_layout \begin_layout Plain Layout + 'x3','y3') \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * like TABLE function with limits: \end_layout \begin_layout Plain Layout Btest3 3 0 I = (v(ctrl) < 'x0') ? 'y0' : (v(ctrl) < 'x3') \end_layout \begin_layout Plain Layout + ? pwl(v(1),'x0','y0','x1','y1','x2','y2','x3','y3') : 'y3' \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * more efficient and elegant TABLE function with limits \end_layout \begin_layout Plain Layout *(voltage controlled): \end_layout \begin_layout Plain Layout Btest4 4 0 I = pwl(v(ctrl), \end_layout \begin_layout Plain Layout + 'xx0','y0', 'x0','y0', \end_layout \begin_layout Plain Layout + 'x1','y1', \end_layout \begin_layout Plain Layout + 'x2','y2', \end_layout \begin_layout Plain Layout + 'x3','y3', 'xx3','y3') \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout * more efficient and elegant TABLE function with limits \end_layout \begin_layout Plain Layout * (controlled by current): \end_layout \begin_layout Plain Layout Btest5 5 0 I = pwl(-2*i(Vin), \end_layout \begin_layout Plain Layout + 'xx0','y0', 'x0','y0', \end_layout \begin_layout Plain Layout + 'x1','y1', \end_layout \begin_layout Plain Layout + 'x2','y2', \end_layout \begin_layout Plain Layout + 'x3','y3', 'xx3','y3') \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout Rint2 2 0 1 \end_layout \begin_layout Plain Layout Rint3 3 0 1 \end_layout \begin_layout Plain Layout Rint4 4 0 1 \end_layout \begin_layout Plain Layout Rint5 5 0 1 \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout dc Vin -6 6 0.2 \end_layout \begin_layout Plain Layout plot v(2) v(3) v(4)-0.5 v(5)+0.5 \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard One characteristic to note: What happens when the controlling input ( \family typewriter V(1) \family default or \begin_inset Formula $-2*i(V_{in})$ \end_inset ) is outside of the given limits, e.g. smaller than x0 or larger than x3 in the example given above? New y values outside of the given range will be determined by adding x,y pairs calculated by extending the slope of the output curve, e.g. with \begin_inset Formula $(y3-y2)/(x3-x2)$ \end_inset , as seen with \family typewriter v(2) \family default from example \family typewriter Btest2 \family default . If you want to limit the function, keeping the last y value, e.g. y3, you have to add another point (x,y pair) with slightly extended x and y kept constant, e.g. \begin_inset Formula $x3+1$ \end_inset ,y3. \end_layout \begin_layout Standard This gets important when we are for example using a behavioral resistor with pwl. In the example below, RR1 quickly moves towards (and beyond) 0, which is unphysical and leads the transient simulation to fail, because the current through RR1 is unbounded. RR2 with its limit given by the 15.1ms,1 couple avoids such malfunctioning. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: pwl function in behavioral resistor \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * pwl for behavioral R, transient sim \end_layout \begin_layout Plain Layout VU1 3 0 DC 9 \end_layout \begin_layout Plain Layout RR1 3 0 R = pwl(time, 0,1, 7m,1, 8m,1.19, 14m,1.19, 15m,1) \end_layout \begin_layout Plain Layout RR2 3 0 R = pwl(time, 0,1, 7m,1, 8m,1.19, 14m,1.19, 15m,1, \end_layout \begin_layout Plain Layout + 15.1m,1) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .tran 100u 20m 0 \end_layout \begin_layout Plain Layout .probe alli \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout option noinit \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout display \end_layout \begin_layout Plain Layout set xbrushwidth=2 \end_layout \begin_layout Plain Layout plot rr1#branch rr2#branch ylimit 7 17 \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:E-source-(non-linear" \end_inset Exxxx: non-linear voltage source \end_layout \begin_layout Subsection VOL \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout EXXXXXXX n+ n- vol='expr' \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout E41 4 0 vol = 'V(3)*V(3)-Offs' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold Expression \series default may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" nolink "false" \end_inset . It may contain parameters ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.param" nolink "false" \end_inset ) and the special variables \family typewriter time \family default , \family typewriter temper \family default , \family typewriter hertz \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Special-B-Source-Variables" nolink "false" \end_inset ). \family typewriter ' \family default or \family typewriter { } \family default may be used to delimit the function. \end_layout \begin_layout Subsection VALUE \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Optional syntax: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout EXXXXXXX n+ n- value={expr} \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout E41 4 0 value = {V(3)*V(3)-Offs} \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The '=' sign is optional. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:table" \end_inset TABLE \end_layout \begin_layout Standard Data may be entered from the listings of a data table similar to the pwl B-Source ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:PiecewiseLinearFunction:-pwl" nolink "false" \end_inset ). Data are grouped into x, y pairs. \series bold Expression \series default may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" nolink "false" \end_inset . It may contain parameters ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.param" nolink "false" \end_inset ). \family typewriter ' \family default or \family typewriter { \family default \family typewriter } \family default may be used to delimit the function. \series bold Expression \series default delivers the x-value, which is used to generate a corresponding y-value according to the tabulated value pairs, using linear interpolation. If the x-value is below x0 , y0 is returned, above x2 y2 is returned (limiting function). The value pairs have to be real numbers, parameters are \emph on not \emph default allowed. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Syntax for data entry from table: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Exxx n1 n2 TABLE {expression} = (x0, y0) (x1, y1) (x2, y2) \end_layout \end_inset \end_layout \begin_layout Plain Layout Example (simple comparator): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ECMP 11 0 TABLE {V(10,9)} = (-5mV, 0V) (5mV, 5V) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard An '=' sign may follow the keyword \family typewriter TABLE \family default . \end_layout \begin_layout Standard An alternative syntax is available as well: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Alternative syntax for data entry from table: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Exxx n1 n2 nc1 nc2 TABLE = (x0, y0, x1, y1, x2, y2) \end_layout \end_inset \end_layout \begin_layout Plain Layout Example (nonlinear gain): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Egain out11 0 in1 in2 TABLE = (0, 0, 1, 1, 2, 4) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection POLY \end_layout \begin_layout Standard see E-Source at Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:POLY" nolink "false" \end_inset . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:LAPLACE" \end_inset LAPLACE \end_layout \begin_layout Standard Currently ngspice does not offer a direct E-Source element with the LAPLACE option. There is however a XSPICE code model equivalent called \series bold s_xfer \series default (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:S-Domain-Transfer-Function" nolink "false" \end_inset ), which you may invoke manually. The XSPICE option has to be enabled ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Ngspice-Installation-under" nolink "false" \end_inset ). AC ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.AC:-Small-Signal-AC" nolink "false" \end_inset ) and transient analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.TRAN:-Transient-Analysis" nolink "false" \end_inset ) is supported. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout The following E-Source: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ELOPASS 4 0 LAPLACE {V(1)} \end_layout \begin_layout Plain Layout + {5 * (s/100 + 1) / (s^2/42000 + s/60 + 1)} \end_layout \end_inset \end_layout \begin_layout Plain Layout may be replaced by: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout AELOPASS 1 int_4 filter1 \end_layout \begin_layout Plain Layout .model filter1 s_xfer(gain=5 \end_layout \begin_layout Plain Layout + num_coeff=[{1/100} 1] \end_layout \begin_layout Plain Layout + den_coeff=[{1/42000} {1/60} 1] \end_layout \begin_layout Plain Layout + int_ic=[0 0]) \end_layout \begin_layout Plain Layout ELOPASS 4 0 int_4 0 1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard where you have the voltage of node 1 as input, an intermediate output node int_4 and an E-source as buffer to keep the name `ELOPASS' available if further processing is required. \end_layout \begin_layout Standard If the controlling expression is more complex than just a voltage node, you may add a B-Source ( \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" nolink "false" \end_inset ) for evaluating the expression before entering the A-device. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout E-Source with complex controlling expression: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ELOPASS 4 0 LAPLACE {V(1)*v(2)} {10 / (s/6800 + 1)} \end_layout \end_inset \end_layout \begin_layout Plain Layout may be replaced by: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout BELOPASS int_1 0 V=V(1)*v(2) \end_layout \begin_layout Plain Layout AELOPASS int_1 int_4 filter1 \end_layout \begin_layout Plain Layout .model filter1 s_xfer(gain=10 \end_layout \begin_layout Plain Layout + num_coeff=[1] \end_layout \begin_layout Plain Layout + den_coeff=[{1/6800} 1] \end_layout \begin_layout Plain Layout + int_ic=[0]) \end_layout \begin_layout Plain Layout ELOPASS 4 0 int_4 0 1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:FREQ" \end_inset FREQ \end_layout \begin_layout Standard Currently ngspice does not offer a direct E-Source element with the FREQ option but it is implemented by a XSPICE code model equivalent called \series bold xfer \series default (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:PWL-Transfer-Function" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) that is automatically invoked by rewriting the netlist. The XSPICE option has to be enabled ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Ngspice-Installation-under" nolink "false" \end_inset ) and only AC ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.AC:-Small-Signal-AC" nolink "false" \end_inset ) analysis is supported. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout This E-Source: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout EXFER 1 0 FREQ {V(20,21)}= DB \end_layout \begin_layout Plain Layout +(1.000000e+07Hz, 1.633257e-07, -1.859873e+01) \end_layout \begin_layout Plain Layout +(1.025641e+08Hz, -4.165672e+00, -4.076855e+02) \end_layout \begin_layout Plain Layout +(2.000000e+08Hz, -2.798303e-05, -7.519027e+02) \end_layout \end_inset \end_layout \begin_layout Plain Layout produces a complex voltage determined by multiplying an input differential voltage (v(20, 21)) by a complex-valued PWL function of the simulation frequency (transfer function). The DB keyword indicates that the second column is gain in db and the third is phase in degrees. Alternative keywords are MAG (linear gain), RAD (phase in radians), DEG (phase in degrees, already the default) or R_I (real and imaginary parts). \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:AND/OR/NAND/NOR" \end_inset AND/OR/NAND/NOR \end_layout \begin_layout Standard This form of E-source provides simple behavioural implementations of basic logic gates with analog inputs and output. It is implemented by a XSPICE code model called \series bold multi_input_pwl \series default (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:multi_input_pwl_block" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) that is automatically invoked by rewriting the netlist. The XSPICE option has to be enabled ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Ngspice-Installation-under" nolink "false" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout This E-Source: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout EAND out1 out0 and(2) in1 0 in2 0 (0.5, 0) (2.8, 3.3) \end_layout \end_inset \end_layout \begin_layout Plain Layout produces a differential output voltage determined by selecting the smallest of any number of differential input voltages, and applying a PWL output function. Here \begin_inset Quotes eld \end_inset and(2) \begin_inset Quotes erd \end_inset determines the logic function and number of PWL points: output is zero for minimum input voltage less than 0.5 and 3.3 for inputs greater than 2.8, with a linear ramp between. The other three functions are similar: \begin_inset Quotes eld \end_inset or \begin_inset Quotes erd \end_inset selects the maximum input and \begin_inset Quotes eld \end_inset nand/nor \begin_inset Quotes erd \end_inset reverse the order of PWL points. Only two points are supported. \end_layout \end_inset \end_layout \begin_layout Standard An example circuit can be found at examples/digital/compare/adder_esource.cir. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:G-source-(non-linear" \end_inset Gxxxx: non-linear current source \end_layout \begin_layout Subsection CUR \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout GXXXXXXX n+ n- cur='expr' \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout G51 55 225 cur = 'V(3)*V(3)-Offs' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold Expression \series default may be an equation or an expression containing node voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source and described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" nolink "false" \end_inset . It may contain parameters ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.param" nolink "false" \end_inset ) and special variables ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Special-B-Source-Variables" nolink "false" \end_inset ). \family typewriter m \family default is an optional multiplier to the output current. \family typewriter val \family default may be a numerical value or an expression according to \begin_inset CommandInset ref LatexCommand ref reference "subsec:Syntax-of-expressions" nolink "false" \end_inset containing only references to other parameters (no node voltages or branch currents!), because it is evaluated before the simulation commences. \end_layout \begin_layout Subsection VALUE \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Optional syntax: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout GXXXXXXX n+ n- value='expr' \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout G51 55 225 value = 'V(3)*V(3)-Offs' \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The '=' sign is optional. \end_layout \begin_layout Subsection TABLE \end_layout \begin_layout Standard A data entry by a tabulated listing is available with syntax similar to the E-Source (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:table" nolink "false" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Syntax for data entry from table: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Gxxx n1 n2 TABLE {expression} = \end_layout \begin_layout Plain Layout + (x0, y0) (x1, y1) (x2, y2) \end_layout \end_inset \end_layout \begin_layout Plain Layout Example (simple comparator with current output and voltage control): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout GCMP 0 11 TABLE {V(10,9)} = (-5MV, 0V) (5MV, 5V) \end_layout \begin_layout Plain Layout R 11 0 1k \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter m \family default is an optional multiplier to the output current. \family typewriter val \family default may be a numerical value or an expression according to \begin_inset CommandInset ref LatexCommand ref reference "subsec:Syntax-of-expressions" nolink "false" \end_inset containing only references to other parameters (no node voltages or branch currents!), because it is evaluated before the simulation commences. An '=' sign may follow the keyword \family typewriter TABLE \family default . \end_layout \begin_layout Subsection POLY \end_layout \begin_layout Standard see E-Source at Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:POLY" nolink "false" \end_inset . \end_layout \begin_layout Subsection LAPLACE \end_layout \begin_layout Standard See E-Source, Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:LAPLACE" nolink "false" \end_inset , for an equivalent code model replacement. \end_layout \begin_layout Subsection FREQ \end_layout \begin_layout Standard See E-Source, Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:FREQ" nolink "false" \end_inset , for an equivalent code model replacement. \end_layout \begin_layout Subsection Example \end_layout \begin_layout Standard An example file is given below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example input file: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout VCCS, VCVS, non-linear dependency \end_layout \begin_layout Plain Layout .param Vi=1 \end_layout \begin_layout Plain Layout .param Offs='0.01*Vi' \end_layout \begin_layout Plain Layout * VCCS depending on V(3) \end_layout \begin_layout Plain Layout B21 int1 0 V = V(3)*V(3) \end_layout \begin_layout Plain Layout G1 21 22 int1 0 1 \end_layout \begin_layout Plain Layout * measure current through VCCS \end_layout \begin_layout Plain Layout vm 22 0 dc 0 \end_layout \begin_layout Plain Layout R21 21 0 1 \end_layout \begin_layout Plain Layout * new VCCS depending on V(3) \end_layout \begin_layout Plain Layout G51 55 225 cur = 'V(3)*V(3)-Offs' \end_layout \begin_layout Plain Layout * measure current through VCCS \end_layout \begin_layout Plain Layout vm5 225 0 dc 0 \end_layout \begin_layout Plain Layout R51 55 0 1 \end_layout \begin_layout Plain Layout * VCVS depending on V(3) \end_layout \begin_layout Plain Layout B31 int2 0 V = V(3)*V(3) \end_layout \begin_layout Plain Layout E1 1 0 int2 0 1 \end_layout \begin_layout Plain Layout R1 1 0 1 \end_layout \begin_layout Plain Layout * new VCVS depending on V(3) \end_layout \begin_layout Plain Layout E41 4 0 vol = 'V(3)*V(3)-Offs' \end_layout \begin_layout Plain Layout R4 4 0 1 \end_layout \begin_layout Plain Layout * control voltage \end_layout \begin_layout Plain Layout V1 3 0 PWL(0 0 100u {Vi}) \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout unset askquit \end_layout \begin_layout Plain Layout tran 10n 100u uic \end_layout \begin_layout Plain Layout plot i(E1) i(E41) \end_layout \begin_layout Plain Layout plot i(vm) i(vm5) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Debugging-a-behavioral" \end_inset Debugging a behavioral source \end_layout \begin_layout Standard The B, E, G, sources and the behavioral R, C, L elements are powerful tools to set up user defined models. Unfortunately debugging these models is not very comfortable. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example input file with bug (log(-2)): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout B source debugging \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout V1 1 0 1 \end_layout \begin_layout Plain Layout V2 2 0 -2 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout E41 4 0 vol = 'V(1)*log(V(2))' \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout tran 1 1 \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The input file given above results in an error message: \end_layout \begin_layout Standard \family typewriter Error: -2 out of range for log \end_layout \begin_layout Standard In this trivial example, the reason and location for the bug is obvious. However, if you have several equations using behavioral sources, and several occurrences of the log function, then debugging is nearly impossible. \end_layout \begin_layout Standard However, if the variable \series bold ngdebug \series default (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset ) is set (e.g. in file \family sans .spiceinit \family default ), a more distinctive error message is issued that (after some closer investigation) will reveal the location and value of the buggy parameter. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Detailed error message for input file with bug (log(-2)): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Error: -2 out of range for log \end_layout \begin_layout Plain Layout calling PTeval, tree = \end_layout \begin_layout Plain Layout (v0) * (log (v1)) \end_layout \begin_layout Plain Layout d / d v0 : log (v1) \end_layout \begin_layout Plain Layout d / d v1 : (v0) * ((0.434294) / (v1)) \end_layout \begin_layout Plain Layout values: var0 = 1 \end_layout \begin_layout Plain Layout var1 = -2 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If variable \family typewriter strict_errorhandling \family default (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset ) is set, ngspice exits after this message. If not, gmin and source stepping may be started, typically without success. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "subsec:POLY" \end_inset POLY Sources \end_layout \begin_layout Standard Polynomial sources are only available when the XSPICE option (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Compilation-notes" nolink "false" \end_inset ) is not disabled. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:E-voltage-source" \end_inset E voltage source, G current source \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout EXXXX N+ N- POLY(ND) NC1+ NC1- (NC2+ NC2-...) P0 (P1...) \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ENONLIN 100 101 POLY(2) 3 0 4 0 0.0 13.6 0.2 0.005 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard POLY(ND) Specifies the number of dimensions of the polynomial. The number of pairs of controlling nodes must be equal to the number of dimensions. \end_layout \begin_layout Standard (N+) and (N-) nodes are output nodes. Positive current flows from the (+) node through the source to the (-) node. \end_layout \begin_layout Standard The \family typewriter \family default and \family typewriter \family default are in pairs and define a set of controlling voltages. A particular node can appear more than once, and the output and controlling nodes need not be different. \end_layout \begin_layout Standard The example yields a voltage output controlled by two input voltages v(3,0) and v(4,0). Four polynomial coefficients are given. The equivalent function to generate the output is: \end_layout \begin_layout LyX-Code 0 + 13.6 * v(3) + 0.2 * v(4) + 0.005 * v(3) * v(3) \end_layout \begin_layout Standard Generally you will set the equation according to \end_layout \begin_layout LyX-Code POLY(1) y = p0 + p1*X1 + p2*X1*X1 + p3*X1*X1*X1 + ... \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code POLY(2) y = p0 + p1*X1 + p2*X2 + \end_layout \begin_layout LyX-Code + p3*X1*X1 + p4*X2*X1 + p5*X2*X2 + \end_layout \begin_layout LyX-Code + p6*X1*X1*X1 + p7*X2*X1*X1 + p8*X2*X2*X1 + \end_layout \begin_layout LyX-Code + p9*X2*X2*X2 + ... \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code POLY(3) y = p0 + p1*X1 + p2*X2 + p3*X3 + \end_layout \begin_layout LyX-Code + p4*X1*X1 + p5*X2*X1 + p6*X3*X1 + \end_layout \begin_layout LyX-Code + p7*X2*X2 + p8*X2*X3 + p9*X3*X3 + ... \end_layout \begin_layout Standard where X1 is the voltage difference of the first input node pair, X2 of the second pair and so on. Keeping track of all polynomial coefficient is rather tedious for large polynomials. \end_layout \begin_layout Subsection F voltage source, H current source \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout FXXXX N+ N- POLY(ND) V1 (V2 V3 ...) P0 (P1...) \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout FNONLIN 100 101 POLY(2) VDD Vxx 0 0.0 13.6 0.2 0.005 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard POLY(ND) Specifies the number of dimensions of the polynomial. The number of controlling sources must be equal to the number of dimensions. \end_layout \begin_layout Standard (N+) and (N-) nodes are output nodes. Positive current flows from the (+) node through the source to the (-) node. \end_layout \begin_layout Standard V1 (V2 V3 ...) are the controlling voltage sources. Control variable is the current through these sources. \end_layout \begin_layout Standard P0 (P1...) are the coefficients, as have been described in \begin_inset CommandInset ref LatexCommand ref reference "subsec:E-voltage-source" nolink "false" \end_inset . \end_layout \begin_layout Chapter Transmission Lines \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Device models ! transmission lines \end_layout \end_inset \end_layout \begin_layout Standard Ngspice implements both the original SPICE3f5 transmission lines models and the one introduced with KSPICE. The latter provide an improved transient analysis of lossy transmission lines. Unlike SPICE models that use the state-based approach to simulate lossy transmission lines, KSPICE simulates lossy transmission lines and coupled multiconductor line systems using the recursive convolution method. The impulse response of an arbitrary transfer function can be determined by deriving a recursive convolution from the Pade approximations of the function. We use this approach for simulating each transmission line's characteristics and each multiconductor line's modal functions. This method of lossy transmission line simulation has been proved to give a speedup of one to two orders of magnitude over SPICE3f5. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Lossless-Transmission-Lines" \end_inset Lossless Transmission Lines \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout TXXXXXXX N1 N2 N3 N4 Z0=VALUE \end_layout \begin_layout Plain Layout + > \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout T1 1 0 2 0 Z0=50 TD=10NS \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n1 \family default \series default and \family typewriter \series bold n2 \family default \series default are the nodes at port 1; \family typewriter \series bold n3 \family default \series default and \family typewriter \series bold n4 \family default \series default are the nodes at port 2. \family typewriter \series bold z0 \family default \series default is the characteristic impedance. The length of the line may be expressed in either of two forms. The transmission delay, \family typewriter \series bold td \family default \series default , may be specified directly (as td=10ns, for example). Alternatively, a frequency \family typewriter \series bold f \family default \series default may be given, together with \family typewriter \series bold nl \family default \series default , the normalized electrical length of the transmission line with respect to the wavelength in the line at the frequency \family typewriter \series bold f \family default \series default . The transmission delay then is calculated as \begin_inset Formula $t_{d}=nl/f.$ \end_inset If a frequency is specified but \family typewriter \series bold nl \family default \series default is omitted, 0.25 is assumed (that is, the frequency is assumed to be the quarter-wave frequency). Note that although both forms for expressing the line length are indicated as optional, one of the two must be specified. \end_layout \begin_layout Standard No \family typewriter .model \family default line is required for this element. \end_layout \begin_layout Standard Note that this element models only one propagating mode. If all four nodes are distinct in the actual circuit, then two modes may be excited. To simulate such a situation, two transmission-line elements are required. (see the example in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Transmission-Line-Inverter" nolink "false" \end_inset for further clarification.) The (optional) initial condition specification consists of the voltage and current at each of the transmission line ports. Note that the initial conditions (if any) apply \emph on only \emph default if the \family typewriter \series bold UIC \family default \series default option is specified on the \family typewriter .TRAN \family default control line. \end_layout \begin_layout Standard Note that a lossy transmission line (see below) with zero loss may be more accurate than the lossless transmission line due to implementation details. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Lossy-Transmission-Lines" \end_inset Lossy Transmission Lines \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout OXXXXXXX n1 n2 n3 n4 mname \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout O23 1 0 2 0 LOSSYMOD \end_layout \begin_layout Plain Layout .model LOSSYMOD ltra rel=1 r=12.45 g=0 l=8.972e-9 c=0.468e-12 \end_layout \begin_layout Plain Layout +len=16 steplimit compactrel=1.0e-3 compactabs=1.0e-14 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout OCONNECT 10 5 20 5 INTERCONNECT \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This is a two-port convolution model for single conductor lossy transmission lines. \family typewriter \series bold n1 \family default \series default and \family typewriter \series bold n2 \family default \series default are the nodes at port 1; \family typewriter \series bold n3 \family default \series default and \family typewriter \series bold n4 \family default \series default are the nodes at port 2. Note that a lossy transmission line with zero loss may be more accurate than the lossless transmission line due to implementation details. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Lossy-Transmission-Line" \end_inset Lossy Transmission Line Model (LTRA) \end_layout \begin_layout Standard The uniform RLC/RC/LC/RG transmission line model (referred to as the LTRA model henceforth) models a uniform constant-parameter distributed transmission line. The RC and LC cases may also be modeled using the URC and TRA models; however, the newer LTRA model is usually faster and more accurate than the others. The operation of the LTRA model is based on the convolution of the transmission line's impulse responses with its inputs (see [8]). The LTRA model takes a number of parameters, some of which must be given and some of which are optional. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units/Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout R \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout resistance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout L \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout inductance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{H}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 9.13e-9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout G \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout conductance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{mhos}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout capacitance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.65e-12 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LEN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout length of line \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $unit$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout no default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout REL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout breakpoint control \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout arbitrary unit \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ABS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout breakpoint control \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NOSTEPLIMIT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout don't limit time-step to less than line delay \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NO CONTROL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout don't do complex time-step control \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LININTERP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout use linear interpolation \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MIXEDINTERP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout use linear when quadratic seems bad \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout COMPACTREL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout special reltol for history compaction \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RELTOL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout COMPACTABS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout special abstol for history compaction \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ABSTOL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRUNCNR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout use Newton-Raphson method for time-step control \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRUNCDONTCUT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout don't limit time-step to keep impulse-response errors low \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not set \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout set \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The following types of lines have been implemented so far: \end_layout \begin_layout Itemize RLC (uniform transmission line with series loss only), \end_layout \begin_layout Itemize RC (uniform RC line), \end_layout \begin_layout Itemize LC (lossless transmission line), \end_layout \begin_layout Itemize RG (distributed series resistance and parallel conductance only). \end_layout \begin_layout Standard Any other combination will yield erroneous results and should not be tried. The length \family typewriter \series bold LEN \family default \series default of the line must be specified. \family typewriter \series bold NOSTEPLIMIT \family default \series default is a flag that will remove the default restriction of limiting time-steps to less than the line delay in the RLC case. \family typewriter \series bold NO CONTROL \family default \series default is a flag that prevents the default limiting of the time-step based on convolution error criteria in the RLC and RC cases. This speeds up simulation but may in some cases reduce the accuracy of results. \family typewriter \series bold LININTERP \family default \series default is a flag that, when specified, will use linear interpolation instead of the default quadratic interpolation for calculating delayed signals. \family typewriter \series bold MIXEDINTERP \family default \series default is a flag that, when specified, uses a metric for judging whether quadratic interpolation is not applicable and if so uses linear interpolation; otherwise it uses the default quadratic interpolation. \family typewriter \series bold TRUNCDONTCUT \family default \series default is a flag that removes the default cutting of the time-step to limit errors in the actual calculation of impulse-response related quantities. \family typewriter \series bold COMPACTREL \family default \series default and \family typewriter \series bold COMPACTABS \family default \series default are quantities that control the compaction of the past history of values stored for convolution. Larger values of these lower accuracy but usually increase simulation speed. These are to be used with the \family typewriter \series bold TRYTOCOMPACT \family default \series default option, described in the . \family typewriter \series bold OPTIONS \family default \series default section. \family typewriter \series bold TRUNCNR \family default \series default is a flag that turns on the use of Newton-Raphson iterations to determine an appropriate time-step in the time-step control routines. The default is a trial and error procedure by cutting the previous time-step in half. \family typewriter \series bold REL \family default \series default and \family typewriter \series bold ABS \family default \series default are quantities that control the setting of breakpoints. \end_layout \begin_layout Standard The option most worth experimenting with for increasing the speed of simulation is \family typewriter \series bold REL \family default \series default . The default value of 1 is usually safe from the point of view of accuracy but occasionally increases computation time. A value greater than 2 eliminates all breakpoints and may be worth trying depending on the nature of the rest of the circuit, keeping in mind that it might not be safe from the viewpoint of accuracy. \end_layout \begin_layout Standard Breakpoints may usually be entirely eliminated if it is expected the circuit will not display sharp discontinuities. Values between 0 and 1 are usually not required but may be used for setting many breakpoints. \end_layout \begin_layout Standard \family typewriter \series bold COMPACTREL \family default \series default may also be experimented with when the option \family typewriter \series bold TRYTOCOMPACT \family default \series default is specified in a \family typewriter .OPTIONS \family default card. The legal range is between 0 and 1. Larger values usually decrease the accuracy of the simulation but in some cases improve speed. If \family typewriter \series bold TRYTOCOMPACT \family default \series default is not specified on a \family typewriter .OPTIONS \family default card, history compaction is not attempted and accuracy is high. \end_layout \begin_layout Standard \family typewriter \series bold NO CONTROL \family default \series default , \family typewriter \series bold TRUNCDONTCUT \family default \series default and \family typewriter \series bold NOSTEPLIMIT \family default \series default also tend to increase speed at the expense of accuracy. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Uniform-Distributed-RC" \end_inset Uniform Distributed RC Lines \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout UXXXXXXX n1 n2 n3 mname l=len \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout U1 1 2 0 URCMOD L=50U \end_layout \begin_layout Plain Layout .model URCMOD URC CPERL=100p RPERL=100k FMAX=10G \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout URC2 1 12 2 UMODL l=1MIL N=6 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n1 \family default \series default and \family typewriter \series bold n2 \family default \series default are the two element nodes the RC line connects, while \family typewriter \series bold n3 \family default \series default is the node the capacitances are connected to. \family typewriter \series bold mname \family default \series default is the model name, \family typewriter \series bold len \family default \series default is the length of the RC line in meters. \family typewriter \series bold lumps \family default \series default , if specified, is the number of lumped segments to use in modeling the RC line (see the model description for the action taken if this parameter is omitted). \end_layout \begin_layout Subsection Uniform Distributed RC Model (URC) \end_layout \begin_layout Standard The URC model is derived from a model proposed by L. Gertzberg in 1974. The model is accomplished by a subcircuit type expansion of the URC line into a network of lumped RC segments with internally generated nodes. The RC segments are in a geometric progression, increasing toward the middle of the URC line, with \begin_inset Formula $K$ \end_inset as a proportionality constant. The number of lumped segments used, if not specified for the URC line device, is determined by the following formula: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} N=\frac{\log\left|F_{{\mathrm{max}}}\frac{R}{L}\frac{C}{L}2\pi L^{2}\left|\frac{(K-1)}{K}\right|^{2}\right|}{\log K} \end{equation} \end_inset The URC line is made up strictly of resistor and capacitor segments unless the \family typewriter \series bold ISPERL \family default \series default parameter is given a nonzero value, in which case the capacitors are replaced with reverse biased diodes with a zero-bias junction capacitance equivalent to the capacitance replaced, and with a saturation current of \family typewriter \series bold ISPERL \family default \series default amps per meter of transmission line and an optional series resistance equivalent to \family typewriter \series bold RSPERL \family default \series default ohms per meter. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout K \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Propagation Constant \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FMAX \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Maximum Frequency of interest \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 G \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 6.5 Meg \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RPERL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Resistance per unit length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1000 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CPERL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitance per unit length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10e-15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 p \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ISPERL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturation Current per unit length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{A}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RSPERL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Resistance per unit length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \end_inset \end_layout \begin_layout Section KSPICE Lossy Transmission Lines \end_layout \begin_layout Standard Unlike SPICE3, which uses the state-based approach to simulate lossy transmission lines, KSPICE simulates lossy transmission lines and coupled multiconductor line systems using the recursive convolution method. The impulse response of an arbitrary transfer function can be determined by deriving a recursive convolution from the Pade approximations of the function. ngspice is using this approach for simulating each transmission line's characteristics and each multiconductor line's modal functions. This method of lossy transmission line simulation has shown to give a sigificant speedup. Please note that the following two models will support only \series bold transient simulation \series default , no ac. \end_layout \begin_layout Standard Additional Documentation Available: \end_layout \begin_layout Itemize S. Lin and E. S. Kuh, `Pade Approximation Applied to Transient Simulation of Lossy Coupled Transmission Lines,' Proc. IEEE Multi-Chip Module Conference, 1992, pp. 52-55. \end_layout \begin_layout Itemize S. Lin, M. Marek-Sadowska, and E. S. Kuh, `SWEC: A StepWise Equivalent Conductance Timing Simulator for CMOS VLSI Circuits,' European Design Automation Conf., February 1991, pp. 142-148. \end_layout \begin_layout Itemize S. Lin and E. S. Kuh, `Transient Simulation of Lossy Interconnect,' Proc. Design Automation Conference, Anaheim, CA, June 1992, pp. 81-86. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Single-Lossy-Transmission" \end_inset Single Lossy Transmission Line (TXL) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout YXXXXXXX N1 0 N2 0 mname \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Y1 1 0 2 0 ymod LEN=2 \end_layout \begin_layout Plain Layout .MODEL ymod txl R=12.45 L=8.972e-9 G=0 C=0.468e-12 length=16 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold n1 \family default \series default and \family typewriter \series bold n2 \family default \series default are the nodes of the two ports. The optional instance parameter \family typewriter \series bold len \family default \series default is the length of the line and may be expressed in multiples of [ \begin_inset Formula $unit$ \end_inset ]. Typically \begin_inset Formula $unit$ \end_inset is given in meters. \family typewriter \series bold len \family default \series default will override the model parameter \family typewriter \series bold length \family default \series default for the specific instance only. \end_layout \begin_layout Standard The TXL model takes a number of parameters: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units/Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout R \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout resistance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout L \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout inductance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{H}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 9.13e-9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout G \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout conductance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{mhos}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout capacitance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.65e-12 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LENGTH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout length of line \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $unit$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout no default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Model parameter \family typewriter \series bold length \family default \series default must be specified as a multiple of \begin_inset Formula $unit$ \end_inset . Typically \begin_inset Formula $unit$ \end_inset is given in [m]. For transient simulation only. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Coupled-Multiconductor-Line" \end_inset Coupled Multiconductor Line (CPL) \end_layout \begin_layout Standard The CPL multiconductor line model is in theory similar to the RLGC model, but without frequency dependent loss (neither skin effect nor frequency-dependent dielectric loss). Up to 8 coupled lines are supported in ngspice. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout PXXXXXXX NI1 NI2...NIX GND1 NO1 NO2...NOX GND2 mname \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout P1 in1 in2 0 b1 b2 0 PLINE \end_layout \begin_layout Plain Layout .model PLINE CPL length={Len} \end_layout \begin_layout Plain Layout +R=1 0 1 \end_layout \begin_layout Plain Layout +L={L11} {L12} {L22} \end_layout \begin_layout Plain Layout +G=0 0 0 \end_layout \begin_layout Plain Layout +C={C11} {C12} {C22} \end_layout \begin_layout Plain Layout .param Len=1 Rs=0 \end_layout \begin_layout Plain Layout + C11=9.143579E-11 C12=-9.78265E-12 C22=9.143578E-11 \end_layout \begin_layout Plain Layout + L11=3.83572E-7 L12=8.26253E-8 L22=3.83572E-7 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold ni1 \family default \series default ... \family typewriter \series bold nix \family default \series default are the nodes at port 1 with gnd1; \family typewriter \series bold no1 \family default \series default ... \family typewriter \series bold nox \family default \series default are the nodes at port 2 with gnd2. The optional instance parameter \family typewriter \series bold len \family default \series default is the length of the line and may be expressed in multiples of [ \begin_inset Formula $unit$ \end_inset ]. Typically \begin_inset Formula $unit$ \end_inset is given in meters. \family typewriter \series bold len \family default \series default will override the model parameter \family typewriter \series bold length \family default \series default for the specific instance only. \end_layout \begin_layout Standard The CPL model takes a number of parameters: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units/Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout R \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout resistance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout L \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout inductance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{H}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 9.13e-9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout G \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout conductance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{mhos}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout capacitance/length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{unit}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.65e-12 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LENGTH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout length of line \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $unit$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout no default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard All RLGC parameters are given in Maxwell matrix form. For the R and G matrices the diagonal elements must be specified, for L and C matrices the lower or upper triangular elements must specified. The parameter LENGTH is a scalar and is mandatory. For transient simulation only. \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:Device Models" \end_inset Device Models \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Device models \end_layout \end_inset \end_layout \begin_layout Section Instance lines and .model lines \end_layout \begin_layout Standard Adding a device to the ngspice netlist as described in this chapter will require two lines: the instance line and a .model line. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Instance line: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout QXXXXXXX node1 node2 node3 modelname \end_layout \end_inset \end_layout \begin_layout Plain Layout .model line: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .model modelname modeltype mpar1=val mpar2=val ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The first letter of the instance line (e.g. Q for bipolar) will select the device (see \begin_inset CommandInset ref LatexCommand ref reference "tab:ngspice-element-types" nolink "false" \end_inset ), \family typewriter QXXXXXXX \family default denotes a unique name. Next there are the device nodes. \family typewriter modelname \family default is a user-given reference to a specific \family typewriter .model \family default line. Instance parameters (specific to the device, often optional) may follow. \end_layout \begin_layout Standard The \family typewriter .model \family default line adds a set of model parameters. After the \family typewriter .model \family default token the \family typewriter modelname \family default sets the link to the devices calling this model parameter set. \family typewriter modeltype \family default links the parameter set to a specific model type, e.g. NPN or PNP for bipolar transistors (see \begin_inset CommandInset ref LatexCommand ref reference "tab:Ngspice-model-types" nolink "false" \end_inset for model types available in ngspice). Model parameters may follow.Their number may differ. If no parameters is given, default parameters hardcoded into ngspice are selected. Complex device models may require several hundred parameters. \family typewriter level \family default and \family typewriter version \family default parameters allow to access sub-categories of a specific device model. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example (integrated NMOS transistor, BSIM3): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout M1 dnode1 gnode1 snode1 bnode1 mosnb3 L=0.35u W=2u \end_layout \begin_layout Plain Layout .model mosnb3 NMOS level=8 version=3.3.0 tox=6.5n nch=2.4e17 nsub=5e16 vth0=0.3 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Junction-Diodes" \end_inset \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Device models ! Diode \end_layout \end_inset Junction Diodes \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout DXXXXXXX n+ n- mname \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout DBRIDGE 2 10 DIODE1 \end_layout \begin_layout Plain Layout DCLMP aa cc DMOD AREA=3.0 IC=0.2 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The pn junction (diode) implemented in ngspice expands the one found in SPICE3f5. Perimeter effects and high injection level have been introduced into the original model and temperature dependence of some parameters has been added. \family typewriter \series bold n+ \family default \series default and \family typewriter \series bold n- \family default \series default are the positive (anode) and negative (cathode) nodes, respectively. \family typewriter \series bold mname \family default \series default is the model name. Instance parameters may follow, dedicated to only the diode described on the respective line. \family typewriter \series bold area \family default \series default is the area scale factor, which may scale the saturation current given by the model parameters (and others, see table below). \family typewriter \series bold pj (perim) \family default \series default is the perimeter scale factor, scaling the sidewall saturation current and its associated capacitance. \family typewriter \series bold m \family default \series default is a multiplier of area and perimeter, and \family typewriter \series bold off \family default \series default indicates an (optional) starting condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification using \family typewriter \series bold ic \family default \series default is intended for use with the \family typewriter \series bold uic \family default \series default option on the \family typewriter .tran \family default control line, when a transient analysis is desired starting from other than the quiescent operating point. You should supply the initial voltage across the diode there. The (optional) \family typewriter \series bold temp \family default \series default value is the temperature at which this device is to operate, and overrides the temperature specification on the \family typewriter .option \family default control line. The temperature of each instance can be specified as an offset to the circuit temperature with the \family typewriter \series bold dtemp \family default \series default option. \end_layout \begin_layout Standard To fulfill requirements of modern process design kits (PDK) the basic spice3 model was extended with the capability of modeling parasitic effects like sidewall junction currents and capacitances, tunnel currents and metal and polysilicon overlap capacitances. Latter effect can be activated by \family typewriter \series bold LEVEL=3 \family default \series default model parameter or by setting element parameters \family typewriter \series bold lm \family default \series default , \family typewriter \series bold wm \family default \series default , \family typewriter \series bold lp \family default \series default and \family typewriter \series bold wp \family default \series default . If both are given, element parameters have priority. \end_layout \begin_layout Standard With the (new in ngspice-39) OpenVAF/OSDI approach (see \begin_inset CommandInset ref LatexCommand ref reference "chap:Verilog-A-Compact-Device" nolink "false" \end_inset ), all modern diode models, written in Verilog-A, become available, like JUNCAP etc.. \end_layout \begin_layout Subsection Diode Model (D) \end_layout \begin_layout Standard Diode models may be described in the netlist input file (or an file included by .inc) according to the following example: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .model mname type(pname1=pval1 pname2=pval2 ... ) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .model DIODE1 D (bv=50 is=1e-13 n=1.05) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard with a user defined model name \family typewriter mname \family default , and the model type \family typewriter D \family default . \end_layout \begin_layout Standard A basic model statement using only the internal default model parameters is \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Basic model statement: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .model DMOD D \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The dc characteristics of the diode are determined by the parameters \family typewriter \series bold IS \family default \series default and \family typewriter \series bold N \family default \series default . An ohmic resistance, \family typewriter \series bold RS \family default \series default , is included. Charge storage effects are modeled by a transit time, \family typewriter \series bold TT \family default \series default , and a nonlinear depletion layer capacitance that is determined by the parameters \family typewriter \series bold CJO \family default \series default , \family typewriter \series bold VJ \family default \series default , and \family typewriter \series bold M \family default \series default . The temperature dependence of the saturation current is defined by the parameters \family typewriter \series bold EG \family default \series default , the energy, and \family typewriter \series bold XTI \family default \series default , the saturation current temperature exponent. The nominal temperature where these parameters were measured is \family typewriter \series bold TNOM \family default \series default , which defaults to the circuit-wide value specified on the \family typewriter .options \family default control line. Reverse breakdown is modeled by an exponential increase in the reverse diode current and is determined by the parameters \family typewriter \series bold BV \family default \series default and \family typewriter \series bold IBV \family default \series default (both of which are positive numbers). \end_layout \begin_layout Subsubsection* Junction DC parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IS (JS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-14 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-16 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout JSW (ISW) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sidewall saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout perimeter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Emission coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Series resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{area}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Series resistance sidewall \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{perim}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BV (VB,VRB,VAR) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Reverse breakdown voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\infty$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 40 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IBV (IB) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Current at breakdown voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NBV (NZ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Breakdown Emission Coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IKF (IK) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Forward knee current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IKR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Reverse knee current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IKP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Forward knee current sidewall \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout JTUN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Tunneling saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout JTUNSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Tunneling sidewall saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout perimeter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NTUN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Tunneling emission coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 30 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XTITUN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Tunneling saturation current exponential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KEG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout EG correction factor for tunneling \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ISR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Recombination saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-14 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1pA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Recombination current emission coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Subsubsection* Junction capacitance parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJO (CJ0) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias junction bottom-wall capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJP (CJSW) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias junction sidewall capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout .1pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout perimeter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coefficient for forward-bias depletion bottom-wall capacitance formula \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FCS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coefficient for forward-bias depletion sidewall capacitance formula \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout M (MJ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Area junction grading coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MJSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Periphery junction grading coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.33 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VJ (PB) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Junction potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PHP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Periphery junction potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Transit-time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.1ns \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Soft reverse recovery parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Subsubsection* Metal and Polysilicon Overlap Capacitances (level=3) \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Length of metal capacitor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4um \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SCALE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Length of polysilicon capacitor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5um \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SCALE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout WM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Width of metal capacitor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2um \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SCALE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout WP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Width of polysilicon capacitor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4um \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SCALE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XOM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Thickness of the metal to bulk oxide \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Å \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10k \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XOI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Thickness of the polysilicon to bulk oxide \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Å \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10k \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Masking and etching effects in metal \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Masking and etching effects in polysilicon \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Masking and etching effects \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout m \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Subsubsection* Temperature effects \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout EG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Activation energy \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $eV$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\begin{array}{cc} 1.11 & \mathrm{Si}\\ 0.69 & \mathrm{Sbd}\\ 0.67 & \mathrm{Ge} \end{array}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout GAP1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout First bandgap correction factor (TLEV=2) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout eV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 7.02e-4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout GAP2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Secnd bandgap correction factor (TLEV=2) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1108 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM (TREF) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter measurement temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 27 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRS1 (TRS) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order tempco for RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRS2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order tempco for RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TM1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order tempco for MJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TM2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order tempco for MJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TTT1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order tempco for TT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TTT2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order tempco for TT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XTI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturation current temperature exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\begin{array}{cc} 3.0 & \mathrm{pn}\\ 2.0 & \mathrm{Sbd} \end{array}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TLEV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Diode temperature equation selector (0,1,2) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TLEVC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Diode capac. temperature equation selector \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CTA (CTC) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Area junct. cap. temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CTP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Perimeter junct. cap. temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TCV (TBV1) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Breakdown voltage temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \end_inset \end_layout \begin_layout Subsubsection* Noise modeling \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold \shape italic Scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection Diode Equations \begin_inset CommandInset label LatexCommand label name "subsec:Diode-Equations" \end_inset \end_layout \begin_layout Standard The junction diode is the basic semiconductor device and the simplest one in ngspice, but its model is quite complex, even when not all the physical phenomena affecting a pn junction are handled. The diode is modeled in three different regions: \end_layout \begin_layout Itemize \emph on Forward bias \emph default : the anode is more positive than the cathode, the diode is `on' and can conduct large currents. To avoid convergence problems and unrealistic high current, it is prudent to specify a series resistance to limit current with the \family typewriter \series bold RS \family default \series default model parameter. \end_layout \begin_layout Itemize \emph on Reverse bias \emph default : the cathode is more positive than the anode and the diode is `off'. A reverse bias diode conducts a small leakage current. \end_layout \begin_layout Itemize \emph on Breakdown \emph default : the breakdown region is modeled only if the \family typewriter \series bold BV \family default \series default model parameter is given. When a diode enters breakdown the current increases exponentially (remember to limit it); \family typewriter \series bold BV \family default \series default is a positive value. \end_layout \begin_layout Subsubsection* Parameters Scaling \end_layout \begin_layout Standard Model parameters are scaled using the unit-less parameters \family typewriter \series bold area \family default \series default and \family typewriter \series bold pj \family default \series default and the multiplier \family typewriter \series bold m \family default \series default as depicted below: \end_layout \begin_layout Standard \begin_inset Formula $AREA_{eff}={\mathrm{AREA}}\:m$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $PJ_{eff}={\mathrm{PJ}}\:m$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $IS_{eff}={\mathrm{IS}}\:AREA_{eff}+{\mathrm{JSW}}\:PJ_{eff}$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $IBV_{eff}={\mathrm{IBV}}\:AREA_{eff}$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $IK_{eff}={\mathrm{IK}}\:AREA_{eff}$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $IKR_{eff}={\mathrm{IKR}}\:AREA_{eff}$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $CJ_{eff}={\mathrm{CJ0}}\:AREA_{eff}$ \end_inset \end_layout \begin_layout Standard \begin_inset Formula $CJP_{eff}={\mathrm{CJP}}\:PJ_{eff}$ \end_inset \end_layout \begin_layout Subsubsection* Diode DC, Transient and AC model equations \end_layout \begin_layout Standard The diode model has certain dc currents for bottom and sidewall components. Exemplary here is the equation for the bottom part: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} I_{D}=\begin{cases} IS_{eff}(e^{\frac{qV_{D}}{NkT}}-1)+V_{D}\cdot GMIN, & \mathrm{if}\;V_{D}\geq-3\frac{NkT}{q}\\ -IS_{eff}[1+(\frac{3NkT}{qV_{D}e})^{3}]+V_{D}\cdot GMIN, & \mathrm{if}\;-BV_{eff} 0 and \family typewriter \series bold TT \family default \series default > 0. The model based on the publication by K.J. Tseng and S. Pan \shape italic Modified charge-control equation for simulation of diode reverse recovery \shape default , Electronics Letters, 15th February 1996, Vol. 32, No. 4 with following description of the dynamic charge behavior: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} Q_{P}=TT\left[IS_{eff}(e^{\frac{-q\mathrm{V_{_{D}}}}{NkT}}-1)-VP\frac{dQ_{P}}{dt}\right] \end{equation} \end_inset \end_layout \begin_layout Subsubsection* Temperature dependence \end_layout \begin_layout Standard The temperature affects many of the parameters in the equations above, and the following equations show how. One of the most significant parameters that varies with the temperature for a semiconductor is the band-gap energy: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} EG_{nom}=1.16-7.02e^{-4}\frac{{\mathrm{TNOM}}^{2}}{{{\mathrm{TNOM}}+1108.0}} \end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} EG(T)=1.16-7.02e^{-4}\frac{T^{2}}{{{\mathrm{TNOM}}+1108.0}} \end{equation} \end_inset \end_layout \begin_layout Standard The leakage current temperature's dependence is: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} IS(T)={\mathrm{IS}}\:e^{\frac{logfactor}{{\mathrm{N}}}} \end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} JSW(T)={\mathrm{JSW}}\:e^{\frac{logfactor}{{\mathrm{N}}}} \end{equation} \end_inset \end_layout \begin_layout Standard where `logfactor' is defined as \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} logfactor=\frac{{\mathrm{EG}}}{V_{t}({\mathrm{TNOM}})}-\frac{{\mathrm{EG}}}{V_{t}(T)}+{\mathrm{XTI}}\:\ln(\frac{T}{{\mathrm{TNOM}}}) \end{equation} \end_inset \end_layout \begin_layout Standard The contact potentials (bottom-wall an sidewall) temperature dependence is: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} VJ(T)={\mathrm{VJ}}(\frac{T}{{\mathrm{TNOM}}})-V_{t}(T)\left[3\cdot\ln(\frac{T}{{\mathrm{TNOM}}})+\frac{{\mathrm{EG}_{nom}}}{V_{t}({\mathrm{TNOM}})}-\frac{{\mathrm{EG}(T)}}{V_{t}(T)}\right] \end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} PHP(T)={\mathrm{PHP}}(\frac{T}{{\mathrm{TNOM}}})-V_{t}(T)\left[3\cdot\ln(\frac{T}{{\mathrm{TNOM}}})+\frac{{\mathrm{EG}_{nom}}}{V_{t}({\mathrm{TNOM}})}-\frac{{\mathrm{EG}(T)}}{V_{t}(T)}\right] \end{equation} \end_inset \end_layout \begin_layout Standard The depletion capacitances temperature dependence is: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} CJ(T)={\mathrm{CJ}}\left[1+{\mathrm{MJ}}(4.0e^{-4}(T-{\mathrm{TNOM}})-\frac{VJ(T)}{{\mathrm{VJ}}}+1)\right] \end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} CJSW(T)={\mathrm{CJSW}}\left[1+{\mathrm{MJSW}}(4.0e^{-4}(T-{\mathrm{TNOM}})-\frac{PHP(T)}{{\mathrm{PHP}}}+1)\right] \end{equation} \end_inset \end_layout \begin_layout Standard The transit time temperature dependence is: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} TT(T)={\mathrm{TT}}(1+{\mathrm{TTT1}}(T-{\mathrm{TNOM}})+{\mathrm{TTT2}}(T-{\mathrm{TNOM}})^{2}) \end{equation} \end_inset \end_layout \begin_layout Standard The junction grading coefficient temperature dependence is: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} MJ(T)={\mathrm{MJ}}(1+{\mathrm{TM1}}(T-{\mathrm{TNOM}})+{\mathrm{TM2}}(T-{\mathrm{TNOM}})^{2}) \end{equation} \end_inset \end_layout \begin_layout Standard The series resistance temperature dependence is: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} RS(T)={\mathrm{RS}}(1+{\mathrm{TRS}}(T-{\mathrm{TNOM}})+{\mathrm{TRS2}}(T-{\mathrm{TNOM}})^{2}) \end{equation} \end_inset \end_layout \begin_layout Subsubsection* Noise model \end_layout \begin_layout Standard The diode has three noise contribution, one due to the presence of the parasitic resistance \family typewriter \series bold RS \family default \series default and the other two (shot and flicker) due to the pn junction. \end_layout \begin_layout Standard The thermal noise due to the parasitic resistance is: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \overline{i_{RS}^{2}}=\frac{4kT\Delta f}{RS} \end{equation} \end_inset \end_layout \begin_layout Standard The shot and flicker noise contributions with model parameters \family typewriter \series bold KF \family default \series default and \family typewriter \series bold AF \family default \series default are \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \overline{i_{d}^{2}}=2qI_{D}\Delta f+\frac{KF\cdot I_{D}^{AF}}{f}\Delta f \end{equation} \end_inset \end_layout \begin_layout Subsubsection* \begin_inset CommandInset label LatexCommand label name "subsec:Self-Heating-model" \end_inset Self Heating model \end_layout \begin_layout Standard Ngspice diode model has implemented a simple self heating approach. A current equivalent to the dissipated power is conducted to a RC parallel circuit. The connection node voltage is so a thermal equivalent to the junction overtemperature. This temperature follows in a electro-thermal feedback with appropriate change of the diode current and capacitance. \end_layout \begin_layout Standard Compared to the standard diode we have a third node \family typewriter \series bold tj \family default \series default and a flag \family typewriter \series bold thermal \family default \series default on element line. In the model description we have to set \family typewriter \series bold RTH0 \family default \series default and \family typewriter \series bold CTH0 \family default \series default model parameter. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form element usage: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout DXXXXXXX n+ n- tj mname thermal \end_layout \end_inset \end_layout \begin_layout Plain Layout Example model: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .model DPWR D (bv=16 is=1e-10 n=1.03 rth0=50 cth0=1u) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsubsection* \begin_inset CommandInset label LatexCommand label name "subsec:Separate sidewall diode" \end_inset Separate sidewall diode \end_layout \begin_layout Standard Models in semiconductor processes require higher accuracy for parasitic effects in integrated diodes. To achieve this bottom and sidewall parts of these diodes will be modeled separate. Defining the model parameter \family typewriter \series bold RSW \family default \series default will switch between both configurations as shown in the figure \begin_inset CommandInset ref LatexCommand ref reference "fig:Diode-model-structure" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . \end_layout \begin_layout Standard \begin_inset Float figure placement document alignment document wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/DIODE.png scale 65 \end_inset \begin_inset Graphics filename Images/DIODE_separate.png scale 65 \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:Diode-model-structure" \end_inset Diode model structure for different RSW definition: left standard, right separate diodes for bottom and sidewall (thermal model only shown once) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Diode models available via OpenVAF/OSDI \end_layout \begin_layout Standard With its integrated \begin_inset CommandInset href LatexCommand href name "OSDI interface" target "https://semimod.de/projects/" literal "false" \end_inset and the \begin_inset CommandInset href LatexCommand href name "OpenVAF" target "https://openvaf.semimod.de/" literal "false" \end_inset compiler (see chapter \begin_inset CommandInset ref LatexCommand ref reference "chap:Verilog-A-Compact-Device" nolink "false" \end_inset for details), ngspice makes available more Verilog-A compact diode models: \end_layout \begin_layout Subsubsection JUNCAP2 model \end_layout \begin_layout Standard Initially developed by Philips research. A widely used diode model in integrated circuit design. Works together with MOS models like PSP and as an alternative diode model for source/drain junctions of BSIM4 models. \end_layout \begin_layout Subsubsection DIODE_CMC \end_layout \begin_layout Standard The DIODE_CMC model includes following enhancement beyond JUNCAP2: \end_layout \begin_layout Enumerate Series resistor \end_layout \begin_layout Enumerate Diffusion cap with soft recovery \end_layout \begin_layout Enumerate Breakdown voltage temperature coefficient \end_layout \begin_layout Enumerate Noise \end_layout \begin_layout Enumerate Min-max parameters for warning purposes \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:BJTs" \end_inset BJT \end_layout \begin_layout Subsection \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Device models ! BJT \end_layout \end_inset Bipolar Junction Transistors (BJTs) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout QXXXXXXX nc nb ne mname \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Q23 10 24 13 QMOD IC=0.6, 5.0 \end_layout \begin_layout Plain Layout Q50A 11 26 4 20 MOD1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold nc \family default \series default , \family typewriter \series bold nb \family default \series default , and \family typewriter \series bold ne \family default \series default are the collector, base, and emitter nodes, respectively. \family typewriter \series bold ns \family default \series default is the (optional) substrate node. When unspecified, ground is used. \family typewriter \series bold tj \family default \series default is the (optional) junction temperature node, available in the VBIC model (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:VBIC-Model" nolink "false" \end_inset ). \family typewriter \series bold mname \family default \series default is the model name, \family typewriter \series bold area \family default \series default , \family typewriter \series bold areab \family default \series default , \family typewriter \series bold areac \family default \series default are the area factors (emitter, base and collector respectively), and \family typewriter \series bold off \family default \series default indicates an (optional) initial condition on the device for the dc analysis. If the area factor is omitted, a value of 1.0 is assumed. \end_layout \begin_layout Standard The (optional) initial condition specification using \family typewriter \series bold ic=vbe,vce \family default \series default is intended for use with the \family typewriter \series bold uic \family default \series default option on a \family typewriter .tran \family default control line, when a transient analysis is desired to start from other than the quiescent operating point. See the \family typewriter .ic \family default control line description for a better way to set transient initial conditions. The (optional) \family typewriter \series bold temp \family default \series default value is the temperature where this device is to operate, and overrides the temperature specification on the \family typewriter .option \family default control line. Using the \family typewriter \series bold dtemp \family default \series default option one can specify the instance's temperature relative to the circuit temperature. \end_layout \begin_layout Subsection BJT Models (NPN/PNP) \end_layout \begin_layout Standard Ngspice provides three different BJT device models, which are selected by the \family typewriter .model \family default card. \end_layout \begin_layout Standard \family typewriter .model QMOD1 PNP \end_layout \begin_layout Standard \family typewriter .model QMOD3 NPN level=4 \end_layout \begin_layout Standard These are the minimal versions, using default parameters supplied by ngspice. Further optional parameters listed in the table below may replace the ngspice default parameters. The \family typewriter \series bold LEVEL \family default \series default keyword specifies the model to be used: \end_layout \begin_layout Itemize \family typewriter \series bold LEVEL \family default \series default =1: This is the original SPICE BJT model, and it is the default model if the \family typewriter \series bold LEVEL \family default \series default keyword is not specified on the \family typewriter .model \family default line. By activating certain parameter a modified version of the original SPICE BJT that models both vertical and lateral devices, includes temperature corrections of collector, emitter and base resistors and allow modeling of quasi-saturation effects. \end_layout \begin_layout Itemize \family typewriter \series bold LEVEL \family default \series default =4: Advanced VBIC model (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:VBIC-Model" nolink "false" \end_inset and \begin_inset CommandInset href LatexCommand href target "http://www.designers-guide.org/VBIC/" literal "false" \end_inset for details) \end_layout \begin_layout Itemize \family typewriter \series bold LEVEL \family default \series default =8: HICUM/L2 model (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:HICUML2-Model" plural "false" caps "false" noprefix "false" nolink "false" \end_inset and \begin_inset CommandInset href LatexCommand href name "the official website" target "https://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.html" literal "false" \end_inset for details) \end_layout \begin_layout Standard With the (new in ngspice-39) OpenVAF/OSDI approach (see \begin_inset CommandInset ref LatexCommand ref reference "chap:Verilog-A-Compact-Device" nolink "false" \end_inset ), all modern bipolar models, written in Verilog-A, become available, like VBIC, Mextram and HICUM. \end_layout \begin_layout Subsection Gummel-Poon Models \end_layout \begin_layout Standard The bipolar junction transistor model in ngspice is an adaptation of the integral charge control model of Gummel and Poon. This modified Gummel-Poon model extends the original model to include several effects at high bias levels. The model automatically simplifies to the simpler Ebers-Moll model when certain parameters are not specified. The parameter names used in the modified Gummel-Poon model have been chosen to be more easily understood by the user, and to reflect better both physical and circuit design thinking. \end_layout \begin_layout Standard The dc model is defined by the parameters \family typewriter \series bold IS \family default \series default , \family typewriter \series bold BF \family default \series default , \family typewriter \series bold NF \family default \series default , \family typewriter \series bold ISE \family default \series default , \family typewriter \series bold IKF \family default \series default , and \family typewriter \series bold NE, \family default \series default which determine the forward current gain characteristics, \family typewriter \series bold IS \family default \series default , \family typewriter \series bold BR \family default \series default , \family typewriter \series bold NR \family default \series default , \family typewriter \series bold ISC \family default \series default , \family typewriter \series bold IKR \family default \series default , and \family typewriter \series bold NC \family default \series default , which determine the reverse current gain characteristics, and \family typewriter \series bold VAF \family default \series default and \family typewriter \series bold VAR \family default \series default , which determine the output conductance for forward and reverse regions. \end_layout \begin_layout Standard A more accurate model for transport current components is possible by specification of model parameter \family typewriter \series bold IBE \family default \series default and \family typewriter \series bold IBC \family default \series default instead of \family typewriter \series bold IS \family default \series default . \end_layout \begin_layout Standard Parameter \family typewriter \series bold NKF(NK) \family default \series default was introduced for more accurate high current beta rolloff modelling. \end_layout \begin_layout Standard The BJT model has among the standard temperature parameters an extension compatible with most foundry provided process design kits (see parameter table below \family typewriter \series bold TLEV \family default \series default ). \end_layout \begin_layout Standard The BJT model includes the substrate saturation current \family typewriter \series bold ISS \family default \series default . Three ohmic resistances \family typewriter \series bold RB \family default \series default , \family typewriter \series bold RC \family default \series default , and \family typewriter \series bold RE \family default \series default are included, where \family typewriter \series bold RB \family default \series default can be high current dependent. Base charge storage is modeled by forward and reverse transit times, \family typewriter \series bold TF \family default \series default and \family typewriter \series bold TR \family default \series default , where the forward transit time \family typewriter \series bold TF \family default \series default can be bias dependent if desired. Nonlinear depletion layer capacitances are defined with \family typewriter \series bold CJE \family default \series default , \family typewriter \series bold VJE \family default \series default , and \family typewriter \series bold NJE \family default \series default for the B-E junction, \family typewriter \series bold CJC \family default \series default , \family typewriter \series bold VJC \family default \series default , and \family typewriter \series bold NJC \family default \series default for the B-C junction and \family typewriter \series bold CJS \family default \series default , \family typewriter \series bold VJS \family default \series default , and \family typewriter \series bold MJS \family default \series default for the C-S (collector-substrate) junction. \end_layout \begin_layout Standard The BJT model support a substrate capacitance that is connected to the device's base or collector, to model lateral or vertical devices dependent on the parameter \family typewriter \series bold SUBS \family default \series default . The temperature dependence of the saturation currents, \family typewriter \series bold IS \family default \series default and \family typewriter \series bold ISS \family default \series default , is determined by the energy-gap, \family typewriter \series bold EG \family default \series default , and the saturation current temperature exponent, \family typewriter \series bold XTI \family default \series default . \end_layout \begin_layout Standard In the new model, additional base current temperature dependence is modeled by the beta temperature exponent \family typewriter \series bold XTB \family default \series default . The values specified are assumed to have been measured at the temperature \family typewriter \series bold TNOM \family default \series default , which can be specified on the \family typewriter .options \family default control line or overridden by a specification on the \family typewriter .model \family default line. \end_layout \begin_layout Standard The BJT parameters used in the modified Gummel-Poon model are listed below. The parameter names used in earlier versions of SPICE2 are still accepted. \end_layout \begin_layout Subsubsection* Gummel-Poon BJT Parameters (incl. model extensions) \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameters \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SUBS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Substrate connection: 1 for vertical geometry, -1 for lateral geometry \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Transport saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-16 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IBE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Base-Emitter saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-16 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IBC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Base-Collector saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-16 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout areab,areac \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ISS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Reverse saturation current, substrate-to-collector for vertical device or substrate-to-base for lateral \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ideal maximum forward beta. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Forward current emission coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VAF (VA) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Forward Early voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\infty$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 200 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IKF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Corner for forward beta current roll-off \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\infty$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.01 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none NKF(NK) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout High current Beta rolloff exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ISE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B-E leakage saturation current. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-13 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B-E leakage emission coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ideal maximum reverse beta \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Reverse current emission coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VAR (VB) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Reverse Early voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\infty$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 200 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IKR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Corner for reverse beta high current roll-off \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\infty$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.01 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ISC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B-C leakage saturation current (scale is `areab' for vertical devices and `areac' for lateral) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ 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Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNC2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for NC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNE1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for NE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNE2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for NE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNF1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for NF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNF2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for NF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNR1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for IKF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNR2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for IKF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TVAF1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for VAF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TVAF2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for VAF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TVAR1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for VAR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TVAR2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for VAR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CTC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for CJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CTE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for CJE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CTS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for CJS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TVJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for VJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TVJE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for VJE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TITF1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for ITF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TITF2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for ITF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TTF1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for TF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TTF2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for TF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TTR1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for TR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TTR2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for TR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TMJE1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for MJE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TMJE2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for MJE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TMJC1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1st order temperature coefficient for MJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TMJC2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2nd order temperature coefficient for MJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{°C^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Subsubsection* Quasi-Saturation Model extension \end_layout \begin_layout Standard By defining parameter \family typewriter \series bold RCO \family default \series default , \family typewriter \series bold VO \family default \series default , \family typewriter \series bold GAMMA \family default \series default and \family typewriter \series bold QCO \family default \series default an extension of the Gummel-Poon model will be switched on to model bipolar junction transistors that exhibit quasi-saturation effects. A description can be found in \begin_inset CommandInset citation LatexCommand cite key "key-24" literal "false" \end_inset . \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameters \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RCO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Epitaxial region resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.45 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1/area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Carrier mobility knee voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.16 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout GAMMA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Epitaxial region doping factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $-$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1e-11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout QCO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Epitaxial region charge factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.4E-11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Energy gap QS temp. depend. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.206 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CN \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Temperature exponent of RCI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.42 NPN 2.2 PNP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout D \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Temperature exponent of VO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout .87 NPN .52 PNP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The Collector current output characteristic shows a special moderate transition in the BJT saturation region, see figure \begin_inset CommandInset ref LatexCommand ref reference "fig:Quasi-Saturation output characteristic" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . Furthermore DC current gain and the unity gain frequency fT falls sharply. \end_layout \begin_layout Standard \begin_inset Float figure placement h alignment document wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/BJT-QS-Output.png scale 90 \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:Quasi-Saturation output characteristic" \end_inset Output characteristic with and w/o Quasi-Saturation \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:VBIC-Model" \end_inset VBIC \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Device models ! VBIC \end_layout \end_inset Model \end_layout \begin_layout Standard The VBIC model is an extended development of the Standard Gummel-Poon (SGP) model with the focus of integrated bipolar transistors in today’s modern semiconductor technologies. With the implemented modified Quasi-Saturation model from Kull and Nagel it is also possible to model the special output characteristic of discrete switching and RF transistors. It is a improved alternative to the SGP model for silicon, SiGe and III-V HBT devices. \end_layout \begin_layout Standard VBIC Capabilities compared to Standard Gummel-Poon Model: \end_layout \begin_layout Itemize Integrated substrate transistor for parasitic devices in integrated processes \end_layout \begin_layout Itemize Weak avalanche and base-emitter breakdown model \end_layout \begin_layout Itemize Improved Early effect modeling \end_layout \begin_layout Itemize Physical separation of Ic and Ib \end_layout \begin_layout Itemize Improved depletion capacitance model \end_layout \begin_layout Itemize Improved temperature modeling \end_layout \begin_layout Itemize Self-heating modeling \end_layout \begin_layout Subsubsection* VBIC self-heating model \end_layout \begin_layout Standard This model has implemented a simple 1-pole thermal network to cover self-heating effects. That means that the power dissipation is gathered in all branches of the device model and is conducted as an equivalent current Ith into one model node dt. This node has a resistor Rth and capacitor Cth parallel connection to ground. Because the resistor plays the role of the thermal resistance from junction to case the arising voltage at node dt is equivalent the BJT junctions temperature. The model realisizes that this temperature rise leads to deviations for internal resistors, currents and capacitors values, calculated by temperature update equations. This process is included into the ngspice iteration schema for all analyses and is controlled by the model parameter \family typewriter \series bold SELFT \family default \series default ( \family typewriter \series bold SELFT \series default =0 \family default : self heating calculation is off (default value), \family typewriter \series bold SELFT \series default =1 \family default : self-heating is on). In addition the model parameter \family typewriter \series bold RTH \family default \series default has to be given. \end_layout \begin_layout Standard The simple thermal network of the VBIC model is shown in Fig. \begin_inset CommandInset ref LatexCommand ref reference "fig:VBIC-thermal-network" nolink "false" \end_inset . \end_layout \begin_layout Standard \begin_inset Float figure placement h alignment document wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/vbic-thermal-network.png scale 80 \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:VBIC-thermal-network" \end_inset VBIC thermal network \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout How to instantiate the bipolar VBIC model (only minimal version) with self-heating: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout vc c 0 0 \end_layout \begin_layout Plain Layout vb b 0 1 \end_layout \begin_layout Plain Layout ve e 0 0 \end_layout \begin_layout Plain Layout vs s 0 0 \end_layout \begin_layout Plain Layout Q1 c b e s dt mod1 area=1 \end_layout \begin_layout Plain Layout .model mod1 npn Level=4 selft=1 rth=100 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Of course it is possible to connect an more accurate thermal network to the node dt. The following example is showing a simplified thermal network covering the thermal resistances and capacitances of junction-case and case-ambient transitions induced by a heat-sink. \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Q1 c b e s dt mod2 \end_layout \begin_layout Plain Layout .model mod2 npn Level=9 selft=1 rth=20 \end_layout \begin_layout Plain Layout X1 dt tamb junction-ambient \end_layout \begin_layout Plain Layout VTamb tamb 0 30 \end_layout \begin_layout Plain Layout .subckt junction-ambient jct amb \end_layout \begin_layout Plain Layout rjc jct 1 0.4 \end_layout \begin_layout Plain Layout ccs 1 0 5m \end_layout \begin_layout Plain Layout rcs 1 2 0.1 \end_layout \begin_layout Plain Layout csa 2 0 30m \end_layout \begin_layout Plain Layout rsa 2 amb 1.3 \end_layout \begin_layout Plain Layout .ends \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:HICUML2-Model" \end_inset HICUM \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Device models ! HICUM \end_layout \end_inset level 2 Model \end_layout \begin_layout Standard The physics-based HIgh-CUrrent Model (HICUM) Level2 (L2) has been a standard compact model for bipolar junction transistors and heterojunction bipolar transistors (HBTs) for many years. The model has been shown to be applicable to many process generations of SiGe HBTs and also to InP HBTs, including high-speed and high-voltage device designs. The implemented version in Ngspice is HICUML2/2.4 and can be activated by BJT model parameter level=8. \end_layout \begin_layout Standard HICUML2 captures most to all known physical effects relevant in HBTs, in example: \end_layout \begin_layout Itemize substrate transistor \end_layout \begin_layout Itemize avalanche effect \end_layout \begin_layout Itemize physics based transfer current model \end_layout \begin_layout Itemize self-heating \end_layout \begin_layout Itemize accurate modeling of the temperature dependence \end_layout \begin_layout Itemize excess phase between base and collector current \end_layout \begin_layout Standard Note that the noise correlation network is not implemented in Ngspice. More information regarding the model and its parameters can be found on the \begin_inset CommandInset href LatexCommand href name "website" target "https://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.html" literal "false" \end_inset . \end_layout \begin_layout Standard The equivalent circuit of the model is shown in fig. \begin_inset CommandInset ref LatexCommand ref reference "fig:hicum" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . The model is employed in many PDKs for state-of-the-art SiGe and InP HBTs and is actively developed at TU Dresden. \end_layout \begin_layout Standard \begin_inset Float figure placement document alignment document wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/hicum_manual.png lyxscale 50 display false width 15cm \end_inset \begin_inset Caption Standard \begin_layout Plain Layout The equivalent circuit of HICUM/L2 without the self-heating, NQS and noise correlation networks. \end_layout \end_inset \end_layout \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:hicum" \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The HICUM model exposes the following nodes to the user: \end_layout \begin_layout Standard C(ollector) B(ase) E(mitter) S(ubstrate) T(emperature) \end_layout \begin_layout Standard By connecting the T and S nodes of the model to other circuit elements, the thermal and substrate network can be modified by the user. Note that both self-heating and the avalanche effect may cause convergency issues if the operating region is too extreme. \end_layout \begin_layout Standard The HICUM/L2 model can be initiated like this example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout vc c 0 0 \end_layout \begin_layout Plain Layout vb b 0 1 \end_layout \begin_layout Plain Layout ve e 0 0 \end_layout \begin_layout Plain Layout vs s 0 0 \end_layout \begin_layout Plain Layout Q1 c b e s dt mod1 area=1 \end_layout \begin_layout Plain Layout .model mod1 npn Level=8 \end_layout \end_inset \end_layout \begin_layout Standard Self-heating is activated by model parameters \family typewriter \series bold FLSH \family default \series default , \family typewriter \series bold RTH \family default \series default and connecting T node of the device instance. \family typewriter \series bold FLSH \family default \series default = 1 will only consider main thermal contributions of IC and IB, \family typewriter \series bold FLSH \family default \series default = 2 include all power dissipations of the transistor. \end_layout \begin_layout Subsection BJT models available via OpenVAF/OSDI \end_layout \begin_layout Standard With its integrated \begin_inset CommandInset href LatexCommand href name "OSDI interface" target "https://semimod.de/projects/" literal "false" \end_inset and the \begin_inset CommandInset href LatexCommand href name "OpenVAF" target "https://openvaf.semimod.de/" literal "false" \end_inset compiler (see chapter \begin_inset CommandInset ref LatexCommand ref reference "chap:Verilog-A-Compact-Device" nolink "false" \end_inset for details), ngspice makes available more Verilog-A compact BJT models: \end_layout \begin_layout Subsubsection HICUM level 0 \end_layout \begin_layout Standard HICUM/L0 is being developed to reduce the simulation and design time especially for larger circuits. It addresses, compared to the SPICE Gummel-Poon model, modern BJT and HBT technologies by including more accurate formulations for important physical effects such as forward transit time, base-collector punch-through and collector impact ionization. \end_layout \begin_layout Subsubsection HICUM level 2 \end_layout \begin_layout Standard HICUM/L2 stands for HIgh CUrrent Model and targets the design of bipolar transistor circuits at high-frequencies and high-current densities using a wide range of Si, SiGe or III-V based process technologies. The compact model that contains accurate formulations of all known physical effects, enables geometry scaling and statistical modeling, and covers a wide temperature, operating and frequency range. \end_layout \begin_layout Subsubsection MEXTRAM 504 and 505 \end_layout \begin_layout Standard MEXTRAM is an advanced compact model for the description of bipolar transistors. It contains many features that the widely-used Gummel-Poon model lacks. Mextram can be used for advanced processes like double-poly or even SiGe transistors and for high-voltage power devices. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:JFETs" \end_inset JFETs \end_layout \begin_layout Subsection \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Device models ! JFET \end_layout \end_inset Junction Field-Effect Transistors (JFETs) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout JXXXXXXX nd ng ns mname \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout J1 7 2 3 JM1 OFF \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold nd \family default \series default , \family typewriter \series bold ng \family default \series default , and \family typewriter \series bold ns \family default \series default are the drain, gate, and source nodes, respectively. \family typewriter \series bold mname \family default \series default is the model name, \family typewriter \series bold area \family default \series default is the area factor, and \family typewriter \series bold off \family default \series default indicates an (optional) initial condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification, using \family typewriter \series bold ic=VDS,VGS \family default \series default is intended for use with the \family typewriter \series bold uic \family default \series default option on the \family typewriter .TRAN \family default control line, when a transient analysis is desired starting from other than the quiescent operating point. See the \family typewriter .ic \family default control line for a better way to set initial conditions. The (optional) \family typewriter temp \family default value is the temperature where this device is to operate, and overrides the temperature specification on the \family typewriter .option \family default control line. \end_layout \begin_layout Subsection JFET Models (NJF/PJF) \end_layout \begin_layout Subsection Basic model statement \end_layout \begin_layout Standard \family typewriter .model JM1 NJF level=1 \end_layout \begin_layout Standard \family typewriter .model JMOD2 PJF level=2 \end_layout \begin_layout Subsection JFET level 1 model with Parker Skellern modification \end_layout \begin_layout Standard The JFET \series bold level 1 \series default model is derived from the FET model of Shichman and Hodges. The dc characteristics are defined by the parameters \family typewriter \series bold VTO \family default \series default and \family typewriter \series bold BETA \family default \series default , which determine the variation of drain current with gate voltage, \family typewriter \series bold LAMBDA \family default \series default , which determines the output conductance, and IS, the saturation current of the two gate junctions. Two ohmic resistances, \family typewriter \series bold RD \family default \series default and \family typewriter \series bold RS \family default \series default , are included. \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} vgst=vgs-VTO \end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \beta_{p}=BETA\:(1+LAMBDA\:vds) \end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} bfac=\frac{1-B}{PB-VTO} \end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} I_{Drain}=\begin{cases} vds\cdot GMIN, & \mathrm{if}\;vgst\leq0\\ \beta_{p}\:vds\:(vds\:(bfac\:vds-B)\:vgst\:(2B+3bfac\:(vgst-vds)))+vds\cdot GMIN, & \mathrm{if}\;vgst\geq vds\\ \beta_{p}\:vgst^{2}\:(B+vgst\:bfac)+vds\cdot GMIN, & \mathrm{if}\;vgst \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Scaling factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VTO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Threshold voltage \begin_inset Formula $V_{T0}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Transconductance parameter ( \begin_inset Formula $\beta$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{A}{V^{"}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LAMBDA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Channel-length modulation parameter ( \begin_inset Formula $\lambda$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1/area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1/area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias G-S junction capacitance \begin_inset Formula $C_{gs}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias G-D junction capacitance \begin_inset Formula $C_{gd}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate junction potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate saturation current \begin_inset Formula $I_{S}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-14 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-14 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Doping tail parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NLEV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Noise equation selector \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout GDSNOI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Channel noise coefficient for nlev=3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coefficient for forward-bias depletion capacitance formula \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter measurement temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 27 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TCV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Threshold voltage temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{\text{°}C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.01 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VTOTC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Threshold voltage temperature coefficient (alternative model) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{\text{°}C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -2.5m \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BEX \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mobility temperature exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BETATCE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mobility temperature exponent (alternative model) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\%}{\text{°}C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XTI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate saturation current temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout EG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bandgap voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Additional to the standard thermal and flicker noise model an alternative thermal channel noise model is implemented and is selectable by setting \family typewriter \series bold NLEV \family default \series default parameter to 3. This leads to a correct channel thermal noise description in the linear region. \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} S_{noise}=\frac{2}{3}\:4kT\cdot BETA\cdot Vgst\:\frac{(1+\text{\alpha}+\alpha^{2})}{1+\alpha}GDSNOI \end{equation} \end_inset \end_layout \begin_layout Standard with \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} \alpha=\begin{cases} 1-\frac{vds}{vgs-VTO}, & \mathrm{if}\;vgs-VTO\geq vds\\ 0, & \mathrm{else} \end{cases} \end{equation} \end_inset \end_layout \begin_layout Standard JFET level 1 model has an alternative temperature model for main parameter \family typewriter \series bold VTO \family default \series default and \family typewriter \series bold BETA \family default \series default : \end_layout \begin_layout Itemize \family typewriter \series bold VTOTC \family default \series default is given: \begin_inset Formula \begin{equation} VTO(Temp)=VTO+VTOTC*(Temp-TNOM) \end{equation} \end_inset \end_layout \begin_layout Itemize \family typewriter \series bold VTOTC \family default \series default not given: \begin_inset Formula \begin{equation} VTO(Temp)=VTO-TCV*(Temp-TNOM) \end{equation} \end_inset \end_layout \begin_layout Itemize \family typewriter \series bold BETATCE \family default \series default is given: \begin_inset Formula \begin{equation} BETA(Temp)=BETA*1.01^{BETATCE*(Temp-TNOM)} \end{equation} \end_inset \end_layout \begin_layout Itemize \family typewriter \series bold BETATCE \family default \series default not given: \begin_inset Formula \begin{equation} BETA(Temp)=BETA*\left(\frac{Temp}{TNOM}\right)^{BEX} \end{equation} \end_inset \end_layout \begin_layout Subsection JFET level 2 Parker Skellern model \end_layout \begin_layout Standard The level 2 model is an improvement to level 1. Details are available in a \begin_inset CommandInset href LatexCommand href name "pdf" target "https://ngspice.sourceforge.io/external-documents/models/psfet.pdf" literal "false" \end_inset originating from Macquarie University. Some important items are \end_layout \begin_layout Itemize The description maintains strict continuity in its high-order derivatives, which is essential for prediction of distortion and intermodulation. \end_layout \begin_layout Itemize Frequency dependence of output conductance and transconductance is described as a function of bias. \end_layout \begin_layout Itemize Both drain-gate and source-gate potentials modulate the pinch-off potential, which is consistent with S-parameter and pulsed-bias measurements. \end_layout \begin_layout Itemize Self-heating varies with frequency. \end_layout \begin_layout Itemize Extreme operating regions - subthreshold, forward gate bias, controlled resistance, and breakdown regions - are included. \end_layout \begin_layout Itemize Parameters provide independent fitting to all operating regions. It is not necessary to compromise one region in favor of another. \end_layout \begin_layout Itemize Strict drain-source symmetry is maintained. The transition during drain-source potential reversal is smooth and continuous. \end_layout \begin_layout Standard The model equations are described in this \begin_inset CommandInset href LatexCommand href name "pdf document" target "https://ngspice.sourceforge.io/external-documents/models/psfet.pdf" literal "false" \end_inset and in \begin_inset CommandInset citation LatexCommand cite key "key-19" literal "true" \end_inset . \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ID \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Device IDText \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Text \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PF1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ACGAM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitance modulation \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Linear-region transconductance scale \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{-4}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias gate-source capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias gate-drain capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DELTA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Thermal reduction coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{W}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Forward bias capacitance parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout High-frequency VGS feedback parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFE1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFGAM modulation by VGD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFE2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFGAM modulation by VGS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFGAM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout High-frequency VGD feedback parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFG1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFGAM modulation by VSG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFG2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HFGAM modulation by VDG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IBD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-junction breakdown current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-junction saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $10^{-14}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LFGAM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Low-frequency feedback parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LFG1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LFGAM modulation by VSG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LFG2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LFGAM modulation by VDG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MVST \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Subthreshold modulation \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-junction ideality factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout P \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Linear-region power-law exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Q \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturated-region power-law exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TAUD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Relaxation time for thermal reduction \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $s$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TAUG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Relaxation time for gamma feedback \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $s$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VBD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-junction breakdown potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VBI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-junction potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VST \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Subthreshold potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VTO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Threshold voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Capacitance pinch-off reduction factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturation-knee potential factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1000 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Z \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Knee transition parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate inductance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $H$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source inductance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $H$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain inductance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $H$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CDSS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Fixed Drain-source capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AFAC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-width scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NFING \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number of gate fingers scale factor \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Nominal Temperature (Not implemented) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $K$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 300 K \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TEMP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $K$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 300 K \end_layout \end_inset \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:MESFETs" \end_inset MESFETs \end_layout \begin_layout Subsection \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Device models ! MESFET \end_layout \end_inset MESFET devices \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ZXXXXXXX ND NG NS MNAME \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Z1 7 2 3 ZM1 OFF \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection MESFET Models (NMF/PMF) \end_layout \begin_layout Standard \family typewriter .model ZM1 NMF level=1 \end_layout \begin_layout Standard \family typewriter .model MZMOD PMF level=4 \end_layout \begin_layout Standard These model statements will use the default parameters (level 1 listed below). \end_layout \begin_layout Subsection Model by Statz e.a. \end_layout \begin_layout Standard The MESFET model \series bold level 1 \series default is derived from the GaAs FET model of Statz et al. as described in \begin_inset CommandInset citation LatexCommand cite key "key-11" literal "true" \end_inset . The dc characteristics are defined by the parameters \family typewriter \series bold VTO \family default \series default , \family typewriter \series bold B \family default \series default , and \family typewriter \series bold BETA \family default \series default , which determine the variation of drain current with gate voltage, \family typewriter \series bold ALPHA \family default \series default , which determines saturation voltage, and \family typewriter \series bold LAMBDA \family default \series default , which determines the output conductance. The formula are given by: \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} I_{d}=\begin{cases} \frac{\beta(V_{gs}-V_{TO})^{2}}{1+B(V_{gs}-V_{TO})}\left[1-\left(1-\alpha\frac{V_{ds}}{3}\right)^{3}\right](1+\lambda V_{ds}) & \mathrm{for\;}0 \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VTO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Pinch-off voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Transconductance parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{A}{V^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Doping tail extending parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ALPHA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturation voltage parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LAMBDA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Channel-length modulation parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 100 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias G-S junction capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias G-D junction capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1pF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate junction potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coefficient for forward-bias depletion capacitance formula \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Device instance: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout z1 2 3 0 mesmod area=1.4 \end_layout \end_inset \end_layout \begin_layout Plain Layout Model: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .model mesmod nmf level=1 rd=46 rs=46 vt0=-1.3 \end_layout \begin_layout Plain Layout + lambda=0.03 alpha=3 beta=1.4e-3 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Model by Ytterdal e.a. \end_layout \begin_layout Standard \series bold level 2 \series default (and levels 3,4) Copyright 1993: T. Ytterdal, K. Lee, M. Shur and T. A. Fjeldly \end_layout \begin_layout Standard to be written \end_layout \begin_layout Standard M. Shur, T.A. Fjeldly, T. Ytterdal, K. Lee, "Unified GaAs MESFET Model for Circuit Simulation", Int. Journal of High Speed Electronics, vol. 3, no. 2, pp. 201-233, 1992 \end_layout \begin_layout Subsection hfet1 and hfet2 \end_layout \begin_layout Standard \series bold hfet1 level 5 \end_layout \begin_layout Standard Heterostructure Field Effect Transistor model as described in section 4.6 of the book \end_layout \begin_layout Standard K. Lee, M. Shur, T. A. Fjeldly and T. Ytterdal, Semiconductor Device Modeling for VLSI, 1993, Prentice Hall, New Jersey. \end_layout \begin_layout Standard Model parameters, equivalent circuit diagrams and device equations are also described in the \begin_inset CommandInset href LatexCommand href name "AIM-Spice reference manual" target "http://www.aimspice.com/downloads/aimspiceref.2020.100.pdf" literal "false" \end_inset , section Device Models A. \end_layout \begin_layout Standard \series bold hfet2 level6 \end_layout \begin_layout Standard The HFET level 2 model is a simplified version of the level 1 model. The model is optimized for speed and is suitable for simulation of digital circuits. To increase the speed, some of the features included in the level 1 model is not implemented for the level 2 model. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:MOSFETs" \end_inset MOSFETs \end_layout \begin_layout Standard Ngspice supports all the original MOSFET models present in SPICE3f5 and almost all the newer ones that have been published and made open-source. Both bulk and SOI (Silicon on Insulator) models are available. When compiled with the cider option, ngspice implements the four terminals numerical model that can be used to simulate a MOSFET (please refer to numerical modeling documentation for additional information and examples). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:MOSFET-devices" \end_inset MOSFET devices \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout MXXXXXXX nd ng ns nb mname \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout M1 24 2 0 20 TYPE1 \end_layout \begin_layout Plain Layout M31 2 17 6 10 MOSN L=5U W=2U \end_layout \begin_layout Plain Layout M1 2 9 3 0 MOSP L=10U W=5U AD=100P AS=100P PD=40U PS=40U \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Note the suffixes in the example: the suffix `u' specifies microns (1e-6 \begin_inset Formula $\mathrm{m}$ \end_inset ) and `p' sq-microns (1e-12 \begin_inset Formula $\mathrm{m^{2}}$ \end_inset ). \end_layout \begin_layout Standard The instance card for MOS devices starts with the letter ' \family typewriter \series bold M \family default \series default '. \family typewriter \series bold nd \family default \series default , \family typewriter \series bold ng \family default \series default , \family typewriter \series bold ns \family default \series default , and \family typewriter \series bold nb \family default \series default are the drain, gate, source, and bulk (substrate) nodes, respectively. \family typewriter \series bold mname \family default \series default is the model name and \family typewriter \series bold m \family default \series default is the multiplicity parameter, which simulates ` \family typewriter m \family default ' paralleled devices. All MOS models support the ` \family typewriter \series bold m \family default \series default ' multiplier parameter. Instance parameters \family typewriter \series bold l \family default \series default and \family typewriter \series bold w \family default \series default , channel length and width respectively, are expressed in meters. The drain and source diffusion areas are \family typewriter \series bold ad \family default \series default and \family typewriter \series bold as \family default \series default , in square meters ( \begin_inset Formula $\mathrm{m^{2}}$ \end_inset ). \end_layout \begin_layout Standard If any of \family typewriter \series bold l \family default \series default , \family typewriter \series bold w \family default \series default , \family typewriter \series bold ad \family default \series default , or \family typewriter \series bold as \family default \series default are not specified, default values are used. The use of defaults simplifies input file preparation, as well as the editing required if device geometries are to be changed. \family typewriter \series bold pd \family default \series default and \family typewriter \series bold ps \family default \series default are the perimeters of the drain and source junctions, in meters. \family typewriter \series bold nrd \family default \series default and \family typewriter \series bold nrs \family default \series default designate the equivalent number of squares of the drain and source diffusions; these values multiply the sheet resistance \family typewriter \series bold rsh \family default \series default specified on the \family typewriter .model \family default control line for an accurate representation of the parasitic series drain and source resistance of each transistor. \family typewriter \series bold pd \family default \series default and \family typewriter \series bold ps \family default \series default default to 0.0 while \family typewriter \series bold nrd \family default \series default and \family typewriter \series bold nrs \family default \series default to 1.0. \family typewriter \series bold off \family default \series default indicates an (optional) initial condition on the device for dc analysis. The (optional) initial condition specification using \family typewriter \series bold ic=vds,vgs,vbs \family default \series default is intended for use with the \family typewriter \series bold uic \family default \series default option on the \family typewriter .tran \family default control line, when a transient analysis is desired starting from other than the quiescent operating point. See the \family typewriter .ic \family default control line for a better and more convenient way to specify transient initial conditions. The (optional) \family typewriter \series bold temp \family default \series default value is the temperature at which this device is to operate, and overrides the temperature specification on the \family typewriter .option \family default control line. \end_layout \begin_layout Standard The temperature specification is ONLY valid for level 1, 2, 3, and 6 MOSFETs, not for level 4 or 5 (BSIM) devices. \end_layout \begin_layout Standard BSIM3 (v3.2 and v3.3.0), BSIM4 (v4.7 and v4.8) and BSIMSOI models are also supporting the instance parameter \family typewriter \series bold delvto \family default \series default and \family typewriter \series bold mulu0 \family default \series default for local mismatch and NBTI (negative bias temperature instability) modeling: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout delvto (delvt0) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Threshold voltage shift \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.07 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout mulu0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Low-field mobility multiplier (U0) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.9 \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection MOSFET models (NMOS/PMOS) \end_layout \begin_layout Standard MOSFET models are the central part of ngspice, probably because they are the most widely used devices in the electronics world. Ngspice provides all the MOSFETs implemented in the original Spice3f and adds several models developed by \begin_inset CommandInset href LatexCommand href name "UC Berkeley's Device Group" target "http://www-device.eecs.berkeley.edu/bsim/" literal "false" \end_inset and other independent groups. \end_layout \begin_layout Standard Each model is invoked with a \family typewriter .model \family default card. A minimal version is: \end_layout \begin_layout Standard \family typewriter .model MOSN NMOS level=8 version=3.3.0 \end_layout \begin_layout Standard The model name MOSN corresponds to the model name in the instance card (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:MOSFET-devices" nolink "false" \end_inset ). Parameter \family typewriter \series bold NMOS \family default \series default selects an n-channel device, \family typewriter \series bold PMOS \family default \series default would point to a p-channel transistor. The \family typewriter \series bold LEVEL \family default \series default and \family typewriter \series bold VERSION \family default \series default parameters select the specific model. Further model parameters are optional and replace ngspice default values. Due to the large number of parameters (more than 100 for modern models), model cards may be stored in extra files and loaded into the netlist by the .include ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.INCLUDE" nolink "false" \end_inset ) command. Model cards are specific for a an IC manufacturing process and are typically provided by the IC foundry. Some generic parameter sets, not linked to a specific process, are made available by the model developers, e.g. \begin_inset CommandInset href LatexCommand href name "UC Berkeley's Device Group" target "http://www-device.eecs.berkeley.edu/bsim/" literal "false" \end_inset for BSIM4 and BSIMSOI. \end_layout \begin_layout Standard Ngspice provides several MOSFET device models, which differ in the formulation of the I-V characteristic, and are of varying complexity. Models available are listed in table \begin_inset CommandInset ref LatexCommand ref reference "tab:MOSFET-model-summary" nolink "false" \end_inset . Current models for IC design are BSIM3 ( \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM3-model" nolink "false" \end_inset , down to channel length of 0.25 µm), BSIM4 ( \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM4-model" nolink "false" \end_inset , below 0.25 µm), BSIMSOI ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:BSIMSOI-models" nolink "false" \end_inset , silicon-on-insulator devices), HiSIM2 and HiSIM_HV ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:HiSIM-models-of" nolink "false" \end_inset , surface potential models for standard and high voltage/high power MOS devices). \end_layout \begin_layout Standard \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Device models ! MOSFET \end_layout \end_inset \begin_inset Float table placement document alignment document wide false sideways false status open \begin_layout Plain Layout \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold Level \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Version \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Developer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold References \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Notes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MOS1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Shichman-Hodges \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout This is the classical quadratic model. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MOS2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Grove-Frohman \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Described in [2] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MOS3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A semi-empirical model (see [1]) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Described in [3] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Described in [5] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MOS6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Described in [2] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MOS9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Alan Gillespie \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 8, 49 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout extensions by Alan Gillespie \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 8, 49 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout extensions by Serban Popescu \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 8, 49 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v32 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.2 - 3.2.4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Multi version code \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 8, 49 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.3.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Described in [13] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10, 58 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B4SOI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.3.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 14, 54 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4v5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.0 - 4.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Multi version code \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 14, 54 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4v6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.6.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 14, 54 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4v7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.7.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 14, 54 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.8.3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 55 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B3SOIFD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 56 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B3SOIDD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 57 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout B3SOIPD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Berkeley \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 60 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout STAG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout SOI3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Southampton \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 68 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HiSIM2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.8.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Hiroshima \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 73 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HiSIM_HV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.2.4/2.2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Hiroshima \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout High Voltage Version for LDMOS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VDMOS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Power MOS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ngspice team \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout weak inversion, quasi saturation, self heating \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout OSDI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout see \begin_inset CommandInset ref LatexCommand ref reference "sec:OSDI/OpenVAF" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout With its OSDI interface all MOS models written in Verilog-A and compiled with \begin_inset CommandInset href LatexCommand href name "OpenVAF" target "https://openvaf.semimod.de/" literal "false" \end_inset are available \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Examples: BSIMBULK, BSIM-CMG, BSIM-IMG, PSP, HiSIM (see \begin_inset CommandInset href LatexCommand href name "VA-Models" target "https://github.com/dwarning/VA-Models" literal "false" \end_inset ). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "tab:MOSFET-model-summary" \end_inset MOSFET model summary \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard With the (new in ngspice-39) OpenVAF/OSDI approach (see \begin_inset CommandInset ref LatexCommand ref reference "chap:Verilog-A-Compact-Device" nolink "false" \end_inset ), all modern MOS models, written in Verilog-A, become available, like BSIMBULK, BSIM-CMG and BSIM-IMG, PSP, HiSim etc.. \end_layout \begin_layout Subsubsection MOS Level 1 \end_layout \begin_layout Standard This model is also known as the `Shichman-Hodges' model. This is the first model written and the one often described in the introductory textbooks for electronics. This model is applicable only to long channel devices. The use of Meyer's model for the C-V part makes it non charge conserving. \end_layout \begin_layout Subsubsection MOS Level 2 \end_layout \begin_layout Standard This model tries to overcome the limitations of the Level 1 model addressing several short-channel effects, like velocity saturation. The implementation of this model is complicated and this leads to many convergence problems. C-V calculations can be done with the original Meyer model (non charge conserving). \end_layout \begin_layout Subsubsection MOS Level 3 \end_layout \begin_layout Standard This is a semi-empirical model derived from the Level 2 model. In the 80s this model has often been used for digital design and, over the years, has proved to be robust. A discontinuity in the model with respect to the \family typewriter \series bold KAPPA \family default \series default parameter has been detected (see [10]). The supplied fix has been implemented in Spice3f2 and later. Since this fix may affect parameter fitting, the option \family typewriter \series bold badmos3 \family default \series default may be set to use the old implementation (see the section on simulation variables and the \family typewriter .options \family default line). Ngspice level 3 implementation takes into account length and width mask adjustments ( \family typewriter \series bold XL \family default \series default and \family typewriter \series bold XW \family default \series default ) and device width narrowing due to diffusion ( \family typewriter \series bold WD \family default \series default ). \end_layout \begin_layout Subsubsection MOS Level 6 \end_layout \begin_layout Standard This model is described in \begin_inset CommandInset citation LatexCommand cite key "key-26" literal "true" \end_inset . The model can express the current characteristics of short-channel MOSFETs at least down to 0.25 \begin_inset Formula $\mu m$ \end_inset channel-length, GaAs FET, and resistance inserted MOSFETs. The model evaluation time is about 1/3 of the evaluation time of the SPICE3 mos level 3 model. The model also enables analytical treatments of circuits in short-channel region and makes up for a missing link between a complicated MOSFET current characteristics and circuit behaviors in the deep submicron region. \end_layout \begin_layout Subsubsection Notes on Level 1-6 models \end_layout \begin_layout Standard The dc characteristics of the level 1 through level 3 MOSFETs are defined by the model parameters \family typewriter \series bold VTO \family default \series default , \family typewriter \series bold KP \family default \series default , \family typewriter \series bold LAMBDA \family default \series default , \family typewriter \series bold PHI \family default \series default and \family typewriter \series bold GAMMA \family default \series default . These parameters are computed by ngspice if process parameters ( \family typewriter \series bold NSUB \family default \series default , \family typewriter \series bold TOX \family default \series default , ...) are given, but users specified values always override. \family typewriter \series bold VTO \family default \series default is positive (negative) for enhancement mode and negative (positive) for depletion mode N-channel (P-channel) devices. \end_layout \begin_layout Standard Charge storage is modeled by three constant capacitors, \family typewriter \series bold CGSO \family default \series default , \family typewriter \series bold CGDO \family default \series default and \family typewriter \series bold CGBO \family default \series default , which represent overlap capacitances, by the nonlinear thin-oxide capacitance that is distributed among the gate, source, drain, and bulk regions, and by the nonlinear depletion-layer capacitances for both substrate junctions divided into bottom and periphery, which vary as the \family typewriter \series bold MJ \family default \series default and \family typewriter \series bold MJSW \family default \series default power of junction voltage respectively, and are determined by the parameters \family typewriter \series bold CBD \family default \series default , \family typewriter \series bold CBS \family default \series default , \family typewriter \series bold CJ \family default \series default , \family typewriter \series bold CJSW \family default \series default , \family typewriter \series bold MJ \family default \series default , \family typewriter \series bold MJSW \family default \series default and \family typewriter \series bold PB \family default \series default . \end_layout \begin_layout Standard Charge storage effects are modeled by the piecewise linear voltages-dependent capacitance model proposed by Meyer. The thin-oxide charge-storage effects are treated slightly different for the level 1 model. These voltage-dependent capacitances are included only if \family typewriter \series bold TOX \family default \series default is specified in the input description and they are represented using Meyer's formulation. \end_layout \begin_layout Standard There is some overlap among the parameters describing the junctions, e.g. the reverse current can be input either as \family typewriter \series bold IS \family default \series default (in A) or as \family typewriter \series bold JS \family default \series default (in \begin_inset Formula $\nicefrac{A}{m^{2}}$ \end_inset ). Whereas the first is an absolute value the second is multiplied by \family typewriter \series bold ad \family default \series default and \family typewriter \series bold as \family default \series default to give the reverse current of the drain and source junctions respectively. \end_layout \begin_layout Standard This methodology has been chosen since there is no sense in relating always junction characteristics with \family typewriter \series bold ad \family default \series default and \family typewriter \series bold as \family default \series default entered on the device line; the areas can be defaulted. The same idea applies also to the zero-bias junction capacitances \family typewriter \series bold CBD \family default \series default and \family typewriter \series bold CBS \family default \series default (in F) on one hand, and \family typewriter \series bold CJ \family default \series default (in \begin_inset Formula $\nicefrac{F}{m^{2}}$ \end_inset ) on the other. \end_layout \begin_layout Standard The parasitic drain and source series resistance can be expressed as either \family typewriter \series bold RD \family default \series default and \family typewriter \series bold RS \family default \series default (in ohms) or \family typewriter \series bold RSH \family default \series default (in ohms/sq.), the latter being multiplied by the number of squares \family typewriter \series bold nrd \family default \series default and \family typewriter \series bold nrs \family default \series default input on the device line. \end_layout \begin_layout Subsubsection* \noindent MOS level 1, 2, 3 and 6 parameters \end_layout \begin_layout Standard \begin_inset space ~ \end_inset \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Example \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LEVEL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Model index \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VTO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias threshold voltage ( \begin_inset Formula $V_{T0})$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Transconductance parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{A}{V^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.0e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.1e-5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout GAMMA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bulk threshold parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\sqrt{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.37 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PHI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Surface potential (U) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.65 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LAMBDA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Channel length modulation (MOS1 and MOS2 only) ( \begin_inset Formula $\lambda)$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.02 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source ohmic resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\Omega$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CBD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias B-D junction capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 20fF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CBS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias B-S junction capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $F$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 20fF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout IS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bulk junction saturation current ( \begin_inset Formula $I_{S}$ \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $A$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-14 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bulk junction potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.8 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.87 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGSO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-source overlap capacitance per meter channel width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.0e-11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGDO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-drain overlap capacitance per meter channel width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.0e-11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGBO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-bulk overlap capacitance per meter channel width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.0e-11 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RSH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain and source diffusion sheet resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{\square}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias bulk junction bottom cap. per sq-meter of junction area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.0e-4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bulk junction bottom grading coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias bulk junction sidewall cap. per meter of junction perimeter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MJSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bulk junction sidewall grading coeff. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\begin{array}{cc} 0.50 & \mathrm{(level}1)\\ 0.33 & \mathrm{(level}2,3) \end{array}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout JS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Bulk junction saturation current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TOX \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Oxide thickness \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NSUB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Substrate doping \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $cm^{-3}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.0e15 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NSS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Surface state density \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $cm^{-2}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NFS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Fast surface state density \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $cm^{-2}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e10 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TPG \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type of gate material: +1 opp. to substrate, -1 same as substrate, 0 Al gate \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Metallurgical junction depth \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1M \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Lateral diffusion \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.8M \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout UO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Surface mobility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm^{2}}{V\cdot sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 600 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 700 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout UCRIT \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Critical field for mobility degradation (MOS2 only) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{V}{cm}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout UEXP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Critical field exponent in mobility degradation (MOS2 only) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout UTRA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Transverse field coeff. (mobility) (deleted for MOS2) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VMAX \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Maximum drift velocity of carriers \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{m}{s}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5.0e4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NEFF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Total channel-charge (fixed and mobile) coefficient (MOS2 only) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0e-26 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout AF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flicker noise exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NLEV \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Noise equation selector \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout GDSNOI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Channel noise coefficient for nlev=3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Coefficient for forward-bias depletion capacitance formula \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DELTA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Width effect on threshold voltage (MOS2 and MOS3) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout THETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mobility modulation (MOS3 only) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Static feedback (MOS3 only) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KAPPA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Saturation field factor (MOS3 only) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TNOM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parameter measurement temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 27 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 50 \end_layout \end_inset \end_inset \end_layout \begin_layout Subsubsection MOS Level 9 \end_layout \begin_layout Standard Documentation is not available.. \end_layout \begin_layout Subsection BSIM Models \end_layout \begin_layout Standard Ngspice implements many of the BSIM models developed by \begin_inset CommandInset href LatexCommand href name "Berkeley's BSIM group" target "http://bsim.berkeley.edu/" literal "false" \end_inset . BSIM stands for Berkeley Short-Channel IGFET Model and groups a class of models that is continuously updated. BSIM3 ( \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM3-model" nolink "false" \end_inset ) and BSIM4 ( \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM4-model" nolink "false" \end_inset ) are industry standards for CMOS processes down to 0.15 µm (BSIM3) and below (BSIM4), are very stable and are supported by model parameter sets from foundries all over the world. BSIM1 and BSIM2 are obsolete today. \end_layout \begin_layout Standard In general, all parameters of BSIM models are obtained from process characterization, in particular level 4 and level 5 (BSIM1 and BSIM2) parameters can be generated automatically. J. Pierret [4] describes a means of generating a `process' file, and the program \family typewriter ngproc2mod \family default provided with ngspice converts this file into a sequence of BSIM1 \family typewriter .model \family default lines suitable for inclusion in an ngspice input file. \end_layout \begin_layout Standard Parameters marked below with an \family typewriter * \family default in the \family typewriter l/w \family default column also have corresponding parameters with a length and width dependency. For example, \family typewriter \series bold VFB \family default \series default is the basic parameter with units of Volts, and \family typewriter \series bold LVFB \family default \series default and \family typewriter \series bold WVFB \family default \series default also exist and have units of Volt-meter. \end_layout \begin_layout Standard The formula \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} P=P_{0}+\frac{P_{L}}{L_{{\mathrm{effective}}}}+\frac{P_{W}}{W_{{\mathrm{effective}}}} \end{equation} \end_inset \end_layout \begin_layout Standard is used to evaluate the parameter for the actual device specified with \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} L_{{\mathrm{effective}}}=L_{{\mathrm{input}}}-DL \end{equation} \end_inset \end_layout \begin_layout Standard \begin_inset Formula \begin{equation} W_{{\mathrm{effective}}}=W_{{\mathrm{input}}}-DW \end{equation} \end_inset \end_layout \begin_layout Standard Note that unlike the other models in ngspice, the BSIM models are designed for use with a process characterization system that provides all the parameters, thus there are no defaults for the parameters, and leaving one out is considered an error. For an example set of parameters and the format of a process file, see the SPICE2 implementation notes [3]. For more information on BSIM2, see reference [5]. BSIM3 ( \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM3-model" nolink "false" \end_inset ) and BSIM4 ( \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM4-model" nolink "false" \end_inset ) represent state of the art for submicron and deep submicron IC design. \end_layout \begin_layout Subsubsection BSIM1 model (level 4) \end_layout \begin_layout Standard BSIM1 model (the first is a long series) is an empirical model. Developers placed less emphasis on device physics and based the model on parametrical polynomial equations to model the various physical effects. This approach pays in terms of circuit simulation behavior but the accuracy degrades in the submicron region. A known problem of this model is the negative output conductance and the convergence problems, both related to poor behavior of the polynomial equations. \end_layout \begin_layout Subsubsection* BSIM1 (level 4) parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Units \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold l/w \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VFB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Flat-band voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PHI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Surface inversion potential \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout K1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Body effect coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\sqrt{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout K2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain/source depletion charge-sharing coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ETA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias drain-induced barrier-lowering coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MUZ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias mobility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm^{2}}{V\cdot sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Shortening of channel \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\mu m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Narrowing of channel \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\mu m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout U0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias transverse-field mobility degradation coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout U1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias velocity saturation coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\mu}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X2MZ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of mobility to substrate bias at v=0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm^{2}}{V^{2}\cdot sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X2E \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of drain-induced barrier lowering effect to substrate bias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X3E \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of drain-induced barrier lowering effect to drain bias at \begin_inset Formula $V_{ds}=V_{dd}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X2U0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of transverse field mobility degradation effect to substrate bias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{V^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X2U1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of velocity saturation effect to substrate bias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\mu m}{V^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MUS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mobility at zero substrate bias and at \begin_inset Formula $V_{ds}=V_{dd}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm^{2}}{V^{2}sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X2MS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of mobility to substrate bias at \begin_inset Formula $V_{ds}=V_{dd}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm^{2}}{V^{2}sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X3MS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of mobility to drain bias at \begin_inset Formula $V_{ds}=V_{dd}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{cm^{2}}{V^{2}sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout X3U1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of velocity saturation effect on drain bias at Vds=Vdd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\mu m}{V^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TOX \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate oxide thickness \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\mu m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TEMP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Temperature where parameters were measured \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VDD \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Measurement bias range \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGDO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-drain overlap capacitance per meter channel width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGSO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-source overlap capacitance per meter channel width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CGBO \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-bulk overlap capacitance per meter channel length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout XPART \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate-oxide capacitance-charge model flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout N0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Zero-bias subthreshold slope coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout NB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of subthreshold slope to substrate bias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ND \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Sens. of subthreshold slope to drain bias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RSH \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain and source diffusion sheet resistance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{\Omega}{\square}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout JS \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source drain junction current density \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{A}{m^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Built in potential of source drain junction \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Grading coefficient of source drain junction \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PBSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Built in potential of source, drain junction sidewall \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $V$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout MJSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Grading coefficient of source drain junction sidewall \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source drain junction capacitance per unit area \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CJSW \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout source drain junction sidewall capacitance per unit length \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{F}{m}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout WDF \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source drain junction default width \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout DELL \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source drain junction length reduction \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $m$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Standard \family typewriter \series bold XPART \family default \series default =0 selects a 40/60 drain/source charge partition in saturation, while \family typewriter \series bold XPART \family default \series default =1 selects a 0/100 drain/source charge partition. \family typewriter \series bold nd \family default \series default , \family typewriter \series bold ng \family default \series default , and \family typewriter \series bold ns \family default \series default are the drain, gate, and source nodes, respectively. \family typewriter \series bold mname \family default \series default is the model name, \family typewriter \series bold area \family default \series default is the area factor, and \family typewriter \series bold off \family default \series default indicates an (optional) initial condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification, using \family typewriter \series bold ic=vds,vgs \family default \series default is intended for use with the \family typewriter \series bold uic \family default \series default option on the \family typewriter .tran \family default control line, when a transient analysis is desired starting from other than the quiescent operating point. See the \family typewriter .ic \family default control line for a better way to set initial conditions. \end_layout \begin_layout Subsubsection BSIM2 model (level 5) \end_layout \begin_layout Standard This model contains many improvements over BSIM1 and is suitable for analog simulation. Nevertheless, even BSIM2 breaks transistor operation into several distinct regions and this leads to discontinuities in the first derivative in C-V and I-V characteristics that can cause numerical problems during simulation. \end_layout \begin_layout Subsubsection \begin_inset CommandInset label LatexCommand label name "subsubsec:BSIM3-model" \end_inset BSIM3 model (levels 8, 49) \end_layout \begin_layout Standard BSIM3 solves the numerical problems of previous models with the introduction of smoothing functions. It adopts a single equation to describe device characteristics in the operating regions. This approach eliminates the discontinuities in the I-V and C-V characteristics. The original model, \begin_inset CommandInset href LatexCommand href name "BSIM3" target "http://bsim.berkeley.edu/models/bsim3/" literal "false" \end_inset evolved through three versions: BSIM3v1, BSIM3v2 and BSIM3v3. Both BSIM3v1 and BSIM3v2 had suffered from many mathematical problems and were replaced by BSIM3v3. The latter is the only surviving release and has itself a long revision history. \end_layout \begin_layout Standard The following table summarizes the story of this model and their available ngspice versions: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold Release \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Date \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Notes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Version flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v3.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10/30/1995 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v3.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 12/09/1996 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v3.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 06/16/1998 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Revisions available: BSIM3v3.2.2, BSIM3v3.2.3, and BSIM3v3.2.4 \end_layout \begin_layout Plain Layout Parallel processing with OpenMP is available for BSIM3v3.2.4. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.2, 3.2.2, 3.2.3, 3.2.4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM3v3.3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 07/29/2005 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Parallel processing with OpenMP is available for this model. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.3.0 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard BSIM3v2 and 3v3 models have been proven for accurate use in 0.18 \begin_inset Formula $\mu m$ \end_inset technologies. The model is publicly available as \begin_inset CommandInset href LatexCommand href name "source code" target "http://bsim.berkeley.edu/BSIM4/BSIM3/ftpv330.zip" literal "false" \end_inset form from University of California, Berkeley. \end_layout \begin_layout Standard A detailed description is given in the user's manual available from \begin_inset CommandInset href LatexCommand href name "here" target "http://ngspice.sourceforge.net/external-documents/models/bsim330_manual.pdf" literal "false" \end_inset . \end_layout \begin_layout Standard We recommend that you use only the most recent BSIM3 models (version 3.3.0), because it contains corrections to all known bugs. To achieve that, change the version parameter in your modelcard files to \end_layout \begin_layout Standard \family typewriter VERSION = 3.3.0 \family default . \end_layout \begin_layout Standard If no version number is given in the \family typewriter .model \family default card, this (newest) version is selected as the default. \end_layout \begin_layout Standard A basic model card using only the intrinsic default parameters may look like \end_layout \begin_layout LyX-Code .model n1 nmos level=49 version=3.3.0 \end_layout \begin_layout LyX-Code .model p1 pmos level=49 version=3.3.0 \end_layout \begin_layout Standard Unfortunately, due to historical reasons, these purely intrinsic parameters do not describe realistic devices. A better minimum model configuration, roughly describing 0.35µm transistors, is \end_layout \begin_layout LyX-Code .model n1 nmos level=49 version=3.3.0 tox=10n nch=1e17 nsub=5e16 \end_layout \begin_layout LyX-Code .model p1 pmos level=49 version=3.3.0 tox=10n nch=1e17 nsub=5e16 \end_layout \begin_layout Standard BSIM3v3.2.4 supports the extra model parameter \family typewriter \series bold LMLT \family default \series default on channel length scaling and is still used by many foundries today. \end_layout \begin_layout Standard The older BSIM3 models will not be supported, they are made available for reference only. \end_layout \begin_layout Subsubsection \begin_inset CommandInset label LatexCommand label name "subsubsec:BSIM4-model" \end_inset BSIM4 model (levels 14, 54) \end_layout \begin_layout Standard This is the newest class of the BSIM family and introduces noise modeling and extrinsic parasitics. BSIM4, as the extension of BSIM3 model, addresses the MOSFET physical effects into sub-100nm regime. It is a physics-based, accurate, scalable, robust and predictive MOSFET SPICE model for circuit simulation and CMOS technology development. It is developed by the BSIM Research Group in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley (see \begin_inset CommandInset href LatexCommand href name "BSIM4 home page" target "http://bsim.berkeley.edu/models/bsim4/" literal "false" \end_inset ). BSIM4 has a long revision history. The models offered by ngspice are summarized below. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold Release \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Date \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Notes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Version flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.5.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 07/29/2005 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ** \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.5.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.6.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 22/09/2009 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ** \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.6.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.7.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 04/08/2011 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ** \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout BSIM4.8.3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 19/05/2025 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ** \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4.8 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard **) Parallel processing using OpenMP support is available for this model. \end_layout \begin_layout Standard Details of any revision are to be found in the Berkeley user's manuals, a pdf download of the most recent edition is to be found \begin_inset CommandInset href LatexCommand href name "here" target "http://ngspice.sourceforge.net/external-documents/models/BSIM480_Manual.pdf" literal "false" \end_inset . \end_layout \begin_layout Standard We recommend that you use only the most recent BSIM4 model (version 4.8.3), because it contains corrections to all known bugs. To achieve that, change the version parameter in your modelcard files to \end_layout \begin_layout Standard \family typewriter VERSION = 4.8.3 \end_layout \begin_layout Standard If no version number is given in the \family typewriter .model \family default card, this (newest) version is selected as the default. The older models will typically not be supported, they are made available for reference only. All version parameter starting with 4.8 will use the code of the recent version. \end_layout \begin_layout Standard The basic model card, using only the intrinsic default parameters, already delivers reasonable device characteristics. \end_layout \begin_layout LyX-Code .model n1 nmos level=54 version=4.8.3 \end_layout \begin_layout LyX-Code .model p1 pmos level=54 version=4.8.3 \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:BSIMSOI-models" \end_inset BSIMSOI models (levels 10, 58, 55, 56, 57) \end_layout \begin_layout Standard BSIMSOI is a SPICE compact model for SOI (Silicon-On-Insulator) circuit design, created by \begin_inset CommandInset href LatexCommand href name "University of California at Berkeley" target "http://bsim.berkeley.edu/models/bsimsoi/" literal "false" \end_inset . This model is formulated on top of the BSIM3 framework. It shares the same basic equations with the bulk model so that the physical nature and smoothness of BSIM3v3 are retained. Four models are supported in ngspice, those based on BSIM3 and modeling fully depleted (FD, level 55), partially depleted (PD, level 57) and both (DD, level 56), as well as the modern BSIMSOI version 4 model (levels 10, 58). Detailed descriptions are beyond the scope of this manual, but see e.g. \begin_inset CommandInset href LatexCommand href name "BSIMSOIv4.4 User Manual" target "http://ngspice.sourceforge.net/external-documents/models/BSIMSOIv4.4_UsersManual.pdf" literal "false" \end_inset for a very extensive description of the recent model version. OpenMP support is available for levels 10, 58, version 4.4. \end_layout \begin_layout Subsection SOI3 model (level 60) \end_layout \begin_layout Standard see literature citation \begin_inset CommandInset citation LatexCommand cite key "key-18" literal "false" \end_inset for a description. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:HiSIM-models-of" \end_inset HiSIM models of the University of Hiroshima \end_layout \begin_layout Standard There are two model implementations available - see also \begin_inset CommandInset href LatexCommand href name "HiSIM Research Center" target "https://www.hisim.hiroshima-u.ac.jp/index.php?id=87" literal "false" \end_inset : \end_layout \begin_layout Enumerate HiSIM2 model: Surface-Potential-Based MOSFET Model for Circuit Simulation version 2.8.0 - level 68 (see \begin_inset CommandInset href LatexCommand href name "link to HiSIM2" target "http://home.hiroshima-u.ac.jp/usdl/HiSIM2/HiSIM_2.5.1_Release_20110407.zip" literal "false" \end_inset for source code and manual). \end_layout \begin_layout Enumerate HiSIM_HV model: Surface-Potential-Based HV/LD-MOSFET Model for Circuit Simulation version 1.2.4 and 2.2.0 - level 73 (see \begin_inset CommandInset href LatexCommand href name "link to HiSIM_HV" target "http://home.hiroshima-u.ac.jp/usdl/HiSIM_HV/C-Code/HiSIM_HV_1.2.2_Release_20110629.zip" literal "false" \end_inset for source code and manual). \end_layout \begin_layout Subsection MOS models available via OpenVAF/OSDI \end_layout \begin_layout Standard With its integrated \begin_inset CommandInset href LatexCommand href name "OSDI interface" target "https://semimod.de/projects/" literal "false" \end_inset and the \begin_inset CommandInset href LatexCommand href name "OpenVAF" target "https://openvaf.semimod.de/" literal "false" \end_inset compiler (see chapter \begin_inset CommandInset ref LatexCommand ref reference "chap:Verilog-A-Compact-Device" nolink "false" \end_inset for details), ngspice makes available several Verilog-A compact MOS models. To obtain the sources you may visit the github repository \begin_inset CommandInset href LatexCommand href name "VA-Models" target "https://github.com/dwarning/VA-Models" literal "false" \end_inset which assembles most of the publicly available Verilog-A compact models. To just name a few models: \end_layout \begin_layout Subsubsection PSP model \end_layout \begin_layout Standard The PSP model is a compact MOSFET model intended for digital, analog and RF-design, which is jointly developed by NXP Semiconductors Research (formerly part of Philips), different universities and CEA-Leti. \end_layout \begin_layout Standard PSP is a surface-potential based MOS Model, containing all relevant physical effects to model present-day and upcoming deep-submicron bulk CMOS technologies: \end_layout \begin_layout Itemize mobility reduction \end_layout \begin_layout Itemize velocity saturation drain induced barrier lowering DIBL \end_layout \begin_layout Itemize gate current \end_layout \begin_layout Itemize lateral doping gradient effects \end_layout \begin_layout Itemize STI stress \end_layout \begin_layout Standard The source/drain junction model, c.q. the JUNCAP2 model, is fully integrated in PSP. Detailes information and the most recent version of the model documentation are available on the the \begin_inset CommandInset href LatexCommand href name "CEA-Leti web site" target "https://www.cea.fr/cea-tech/leti/pspsupport/CurrentRelease" literal "false" \end_inset , see also the \begin_inset CommandInset href LatexCommand href name "PSP Summary" target "https://www.cea.fr/cea-tech/leti/pspsupport/Documents/psp103p8_summary.pdf" literal "false" \end_inset . \end_layout \begin_layout Subsubsection BSIM-BULK model \end_layout \begin_layout Standard \begin_inset CommandInset href LatexCommand href name "BSIM-BULK" target "http://bsim.berkeley.edu/models/bsimbulk/" literal "false" \end_inset is the successor to BSIM4, with high accuracy compared to measured data in all regions of operation. It features model symmetry valued for analog and RF applications. \end_layout \begin_layout Subsubsection BSIM-CMG model \end_layout \begin_layout Standard \begin_inset CommandInset href LatexCommand href name "BSIM-CMG" target "http://bsim.berkeley.edu/models/bsimcmg/" literal "false" \end_inset (Common Multi-Gate) is a compact model for the class of common multi-gate FETs, namely FinFETs, Nanowire and Gate-All-Around transistors. \end_layout \begin_layout Subsubsection EKV3 \end_layout \begin_layout Standard \begin_inset CommandInset href LatexCommand href name "EKV3" target "https://github.com/MatBucher/ekv3model" literal "false" \end_inset Due to CMOS scaling, ICs operate more and more in moderate and weak inversion. Evolution of CMOS device performance – from planar bulk to double-gate and FinFET. The model is a charge-based compact model – close to physics and design. Modularity allows high-frequency application with special attention to analog/RF IC design requirements. \end_layout \begin_layout Section Power \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Device models ! VDMOS \end_layout \end_inset MOSFET model (VDMOS) \end_layout \begin_layout Standard The VDMOS model is a relativly simple power MOS model with 3 terminals drain, gate and source. Its current equations are partly based on a modified MOS1 model. The gate-source capacitance is set to a constant value by model parameter \family typewriter \series bold CGS \family default \series default . The drain-source capacitance is evaluated from parameters \family typewriter \series bold CGDMAX \family default \series default , \family typewriter \series bold CGDMIN \family default \series default , and \family typewriter \series bold A \family default \series default . The drain-source capacitance is that of a parallel pn diode and calculated by \family typewriter \series bold CJO \family default \series default , \family typewriter \series bold FC \family default \series default , and \family typewriter \series bold M \family default \series default . Leakage and breakdown are modeled by the parallel pn diodes as well, using \family typewriter \series bold IS \family default \series default and other parameters. A subthreshold current model is available, using a single parameter \family typewriter \series bold KSUBTHRES \family default \series default . Quasi-saturation is modeled with parameters \family typewriter \series bold RQ \family default \series default and \family typewriter \series bold VQ \family default \series default . \family typewriter \series bold MTRIODE \family default \series default may be used here as well. The body diode can cover soft reverse recovery behavior by using a suitable parameter \family typewriter \series bold VP \family default \series default (e.g. 0.1) and transit time parameter \family typewriter \series bold TT \family default \series default > 0, see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Diode-Equations" plural "false" caps "false" noprefix "false" nolink "false" \end_inset \end_layout \begin_layout Standard The thermal network of the VDMOS model is shown in Fig. \begin_inset CommandInset ref LatexCommand ref reference "fig:VDMOS_thermal" nolink "false" \end_inset . \end_layout \begin_layout Standard \begin_inset Float figure placement h alignment document wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/VDMOS_thermal.png scale 80 \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "fig:VDMOS_thermal" \end_inset VDMOS model including thermal network \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This model does not have a level parameter. It is invoked by the VDMOS token preceding the parameters on the .model line. P-channel or n-channel are selected by the model parameter \series bold PCHAN \series default and \series bold NCHAN \series default . If no flag is given, n-channel is the default. Standard MOS instance parameters W and L are not acknowledged because they are no design parameters and are not provided by the device manufacturers. \end_layout \begin_layout Standard The following 'parameters' in the .model line are no model parameters, but serve information purposes for the user: \family typewriter mfg=..., Vds=..., Ron=..., \family default and \family typewriter Qg=... \family default They are ignored by ngspice. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout MXXXXXXX nd ng ns mname \end_layout \begin_layout Plain Layout .model mname VDMOS \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout M1 24 2 0 IXTH48P20P \end_layout \begin_layout Plain Layout .MODEL IXTH48P20P VDMOS Pchan Vds=200 VTO=-4 KP=10 Lambda=5m \end_layout \begin_layout Plain Layout + Mtriode=0.3 Ksubthres=120m Rs=10m Rd=20m Rds=200e6 \end_layout \begin_layout Plain Layout + Cgdmax=6000p Cgdmin=100p A=0.25 Cgs=5000p Cjo=9000p \end_layout \begin_layout Plain Layout + Is=2e-6 Rb=20m BV=200 IBV=250e-6 NBV=4 TT=260e-9 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsubsection* \noindent VDMOS instance parameters \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \series bold Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Parameter \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \series bold Units 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\begin_inset Text \begin_layout Plain Layout 1.5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TEXP1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain resistance rd1 temperature exponent \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRD1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain resistance linear temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{\text{°}C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRD2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Drain resistance quadratic temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{(\text{°}C)^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRG1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate resistance linear temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{\text{°}C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRG2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Gate resistance quadratic temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{(\text{°}C)^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRS1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source resistance linear temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{\text{°}C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRS2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Source resistance quadratic temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{(\text{°}C)^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRB1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Body resistance linear temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{\text{°}C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRB2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Body resistance quadratic temperature coefficient \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{(\text{°}C)^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TKSUBTHRES1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Linear temperature coefficient of ksubthres \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{\text{°}C}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TKSUBTHRES2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Quadratic temperature coefficient of ksubthres \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{1}{(\text{°}C)^{2}}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RTHJC \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Thermal resistance junction-case \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{K}{W}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0.4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout CTHJ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Thermal capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{J}{K}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 10e-6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5e-3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout RTHCA \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Thermal resistance case-ambient (w/o heatsink) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\nicefrac{K}{W}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1000 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \end_inset \end_layout \begin_layout Subsubsection* \noindent VDMOS electro-thermal model \end_layout \begin_layout Standard Power electronic devices behavior the effect of self-heating effect. That means that the dissipated power has an impact to the electrical behavior of the terminal currents. To minimize this effect and to protect the element from thermal destruction heat sinks are supplied to this kind of power devices. \end_layout \begin_layout Standard The ngspice VDMOS model has introduced an electro-thermal approach by stamping additional elements into the circuit matrix and by iteration the additional current control inside the spice solver. \end_layout \begin_layout Standard The transistor now has 5 terminals. Besides D, G, and S we have TJ and TCASE. The additional terminals must be activated by the device switch THERMAL. Heat is generated in the MOS channel and peripheral elements like resistors, its temperature is available and may be measured at node TJ, and is fed back internally into the device equations. Within the transistor package the heat is flowing from the channel to the metal surface of the case, at terminal TCASE. Here you may connect a heat sink, to offer a flow path for the heat away from the device. The internal heat resistance is \series bold RTHJC \series default (junction to case), a typical data sheet value. The model also includes the heat capacitance \series bold CTHJ \series default of the semiconductor die and package (typically not available in the data sheet, so to be estimated only). Internal model resistor \series bold RTHCA \series default (case to ambient) is connected to internal voltage source with a value of circuit temperature Tamb and act as an alternative for a missing external heat sink. \end_layout \begin_layout Standard The following example show the usage of ngspice electro-thermal model including a simple heat sink: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout MXXXXXXX nd ng ns tj tc mname thermal \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout M1 24 2 0 tj tc IXTH48P20P thermal \end_layout \begin_layout Plain Layout rcs tc 1 0.1 \end_layout \begin_layout Plain Layout csa 1 0 30m \end_layout \begin_layout Plain Layout rsa 1 amb 1.3 \end_layout \begin_layout Plain Layout VTamb tamb 0 25 \end_layout \begin_layout Plain Layout .MODEL IXTH48P20P VDMOS Pchan Vds=200 VTO=-4 KP=10 Lambda=5m \end_layout \begin_layout Plain Layout + Mtriode=0.3 Ksubthres=120m Rs=10m Rd=20m Rds=200e6 \end_layout \begin_layout Plain Layout + Cgdmax=6000p Cgdmin=100p A=0.25 Cgs=5000p Cjo=9000p \end_layout \begin_layout Plain Layout + Is=2e-6 Rb=20m BV=200 IBV=250e-6 NBV=4 TT=260e-9 \end_layout \begin_layout Plain Layout + Rthjc=0.4 Cthj=5e-3 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "cha:Behavioral-Modeling" \end_inset Mixed-Mode and Behavioral Modeling with XSPICE \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout XSPICE, see Code models \end_layout \end_inset \end_layout \begin_layout Standard Ngspice implements XSPICE extensions for behavioral and mixed-mode (analog and digital) modeling. In the XSPICE framework this is referred to as code level modeling. Behavioral modeling may benefit dramatically because XSPICE offers a means to add analog functionality programmed in C. Many examples (amplifiers, oscillators, filters ...) are presented in the following. Even more flexibility is available because you may define your own models and use them in addition and in combination with all the already existing ngspice functionality. Digital and mixed mode simulation is sped up significantly by simulating the digital part in an event driven manner, in that state equations use only a few allowed states and are evaluated only during switching, and not continuously in time and signal as in a pure analog simulator. \end_layout \begin_layout Standard This \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Code models \end_layout \end_inset chapter describes the predefined models available in ngspice, stemming from the original XSPICE simulator or being added to enhance the usability. The instructions for writing new code models are given in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Code-Models-and" nolink "false" \end_inset . \end_layout \begin_layout Standard To make use of the XSPICE extensions, you need to compile them in. Linux, CYGWIN, MINGW and other users may add the flag \family typewriter --enable-xspice \family default to their \family typewriter ./configure \family default command and then recompile. The pre-built ngspice for Windows distribution has XSPICE already enabled. For detailed compiling instructions see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Ngspice-Installation-under" nolink "false" \end_inset . \end_layout \begin_layout Section Code Model Element & .MODEL Cards \end_layout \begin_layout Subsection Syntax \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Code models ! netlist syntax \end_layout \end_inset \end_layout \begin_layout Standard Ngspice includes a library of predefined `Code Models' that can be placed within any circuit description in a manner similar to that used to place standard device models. Code model instance cards always begin with the letter `A', and always make use of a \family typewriter .MODEL \family default card to describe the code model desired. Section \begin_inset CommandInset ref LatexCommand ref reference "cha:Code-Models-and" nolink "false" \end_inset of this document goes into greater detail as to how a code model similar to the predefined models may be developed, but once any model is created and linked into the simulator it may be placed using one instance card and one \family typewriter .MODEL \family default card (note here we conform to the SPICE custom of referring to a single logical line of information as a `card'). As an example, the following uses a predefined `gain' code model taking as an input some value on node 1, multiplies it by a gain of 5.0, and outputs the new value to node 2. Note that, by convention, input ports are specified first on code models. Output ports follow the inputs. \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout a1 1 2 amp \end_layout \begin_layout Plain Layout .model amp gain(gain=5.0) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard In this example the numerical values picked up from single-ended (i.e. ground referenced) input node 1 and output to single-ended output node 2 will be voltages, since in the Interface Specification File for this code model (i.e., gain), the default port type is specified as a voltage (more on this later). However, if you didn't know this, the following modifications to the instance card could be used to insure it: \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout a1 %v(1) %v(2) amp \end_layout \begin_layout Plain Layout .model amp gain(gain=5.0) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The specification \family typewriter %v \family default preceding the input and output node numbers of the instance card indicate to the simulator that the inputs to the model should be single-ended voltage values. Other possibilities exist, as described later. \end_layout \begin_layout Standard Some of the other features of the instance and \family typewriter .MODEL \family default cards are worth noting. Of particular interest is the portion of the \family typewriter .MODEL \family default card that specifies \family typewriter gain=5.0 \family default . This portion of the card assigns a value to a parameter of the `gain' model. There are other parameters that can be assigned values for this model, and in general code models will have several. In addition to numeric values, code model parameters can take non-numeric values (such as TRUE and FALSE), and even vector values. All of these topics will be discussed at length in the following pages. In general, however, the instance and \family typewriter .MODEL \family default cards that define a code model will follow the abstract form described below. This form illustrates that the number of inputs and outputs and the number of parameters that can be specified is relatively open-ended and can be interpreted in a variety of ways (note that angle-brackets ` \family typewriter < \family default ' and ` \family typewriter > \family default ' enclose optional inputs): \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout AXXXXXXX <%v,%i,%vd,%id,%g,%gd,%h,%hd, or %d> \end_layout \begin_layout Plain Layout + <[> <~><%v,%i,%vd,%id,%g,%gd,%h,%hd, or %d> \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + <~>... > \end_layout \begin_layout Plain Layout + <%v,%i,%vd,%id,%g,%gd,%h,%hd,%d or %vnam> \end_layout \begin_layout Plain Layout + <[> <~><%v,%i,%vd,%id,%g,%gd,%h,%hd, \end_layout \begin_layout Plain Layout or %d> \end_layout \begin_layout Plain Layout + <~>...> \end_layout \begin_layout Plain Layout + MODELNAME \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .MODEL MODELNAME MODELTYPE \end_layout \begin_layout Plain Layout + <( PARAMNAME1= <[> VAL1 > PARAMNAME2..>)> \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Square brackets ([ ]) are used to enclose vector input nodes. In addition, these brackets are used to delineate vectors of parameters. \end_layout \begin_layout Standard The literal string `null', when included in a node list, is interpreted as no connection at that input to the model. `Null' is not allowed as the name of a model's input or output if the model only has one input or one output. Also, `null' should only be used to indicate a missing connection for a code model; use on other XSPICE component is not interpreted as a missing connection, but will be interpreted as an actual node name. \end_layout \begin_layout Standard The tilde, ` \family typewriter ~ \family default ', when prepended to a digital node name, specifies that the logical value of that node be inverted prior to being passed to the code model. This allows for simple inversion of input and output polarities of a digital model in order to handle logically equivalent cases and others that frequently arise in digital system design. The following example defines a NAND gate, one input of which is inverted: \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout a1 [~1 2] 3 nand1 \end_layout \begin_layout Plain Layout .model nand1 d_nand (rise_delay=0.1 fall_delay=0.2) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The optional symbols %v, %i, %vd, etc. specify the type of port the simulator is to expect for the subsequent port or port vector. The meaning of each symbol is given in Table \begin_inset CommandInset ref LatexCommand ref reference "cap:Port-Type-Modifiers" nolink "false" \end_inset . \end_layout \begin_layout Standard \begin_inset Float table placement document alignment document wide false sideways false status open \begin_layout Plain Layout \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none Port Type Modifiers \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Modifier \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Interpretation \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %v \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a single-ended voltage port - one node name or number is expected for each port. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %i \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a single-ended current port - one node name or number \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit is expected for each port. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %g \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a single-ended voltage-input, current-output (VCCS) port - one node name or number is expected for each port. This type of port is automatically an input/output. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %h \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a single-ended current-input, voltage-output (CCVS) port - one node name or number is expected for each port. This type of port is automatically an input/output. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %d \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a digital port - one node name or number is expected for each port. This type of port may be either an input or an output. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %vnam \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents the name of a voltage source, the current through which is taken as an input. This notation is provided primarily in order to allow models defined using SPICE2G6 syntax to operate properly in XSPICE. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %vd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a differential voltage port - two node names or numbers are expected for each port. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %id \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a differential current port - two node names or numbers are expected for each port. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %gd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a differential VCCS port - two node names or numbers are expected for each port. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout %hd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \bar no \noun off \color none represents a differential CCVS port - two node names or numbers \family default \series default \shape default \size default \emph default \bar default \noun default \color inherit are expected for each port. \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "cap:Port-Type-Modifiers" \end_inset Port Type Modifiers \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The symbols described in Table \begin_inset CommandInset ref LatexCommand ref reference "cap:Port-Type-Modifiers" nolink "false" \end_inset may be omitted if the default port type for the model is desired. Note that non-default port types for multi-input or multi-output (vector) ports must be specified by placing one of the symbols in front of EACH vector port. On the other hand, if all ports of a vector port are to be declared as having the same non-default type, then a symbol may be specified immediately prior to the opening bracket of the vector. The following examples should make this clear: \end_layout \begin_layout LyX-Code Example 1: - Specifies two differential voltage connections, one \end_layout \begin_layout LyX-Code to nodes 1 & 2, and one to nodes 3 & 4. \end_layout \begin_layout LyX-Code \begin_inset VSpace defskip \end_inset \end_layout \begin_layout LyX-Code %vd [1 2 3 4] \end_layout \begin_layout LyX-Code \begin_inset VSpace bigskip \end_inset \end_layout \begin_layout LyX-Code Example 2: - Specifies two single-ended connections to node 1 and \end_layout \begin_layout LyX-Code at node 2, and one differential connection to \end_layout \begin_layout LyX-Code nodes 3 & 4. \end_layout \begin_layout LyX-Code \begin_inset VSpace defskip \end_inset \end_layout \begin_layout LyX-Code %v [1 2 %vd 3 4] \end_layout \begin_layout LyX-Code \begin_inset VSpace bigskip \end_inset \end_layout \begin_layout LyX-Code Example 3: - Identical to the previous example...parenthesis \end_layout \begin_layout LyX-Code are added for additional clarity. \end_layout \begin_layout LyX-Code \begin_inset VSpace defskip \end_inset \end_layout \begin_layout LyX-Code %v [1 2 %vd(3 4)] \end_layout \begin_layout LyX-Code \begin_inset VSpace bigskip \end_inset \end_layout \begin_layout LyX-Code Example 4: - Specifies that the node numbers are to be treated in the \end_layout \begin_layout LyX-Code default fashion for the particular model. \end_layout \begin_layout LyX-Code If this model had `%v'' as a default for this \end_layout \begin_layout LyX-Code port, then this notation would represent four single-ended \end_layout \begin_layout LyX-Code voltage connections. \end_layout \begin_layout LyX-Code \begin_inset VSpace defskip \end_inset \end_layout \begin_layout LyX-Code [1 2 3 4] \end_layout \begin_layout LyX-Code \begin_inset VSpace bigskip \end_inset \end_layout \begin_layout Standard The parameter names listed on the \family typewriter .MODEL \family default card must be identical to those named in the code model itself. The parameters for each predefined code model are described in detail in Sections \begin_inset CommandInset ref LatexCommand ref reference "sec:XSPICE-Analog-Models" nolink "false" \end_inset (analog), \begin_inset CommandInset ref LatexCommand ref reference "sec:Hybrid-Models" plural "false" caps "false" noprefix "false" nolink "false" \end_inset (Hybrid, A/D) and \begin_inset CommandInset ref LatexCommand ref reference "sec:XSPICE-Digital-Models" nolink "false" \end_inset (digital). The steps required in order to specify parameters for user-defined models are described in Chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Code-Models-and" nolink "false" \end_inset . \end_layout \begin_layout Subsection Examples \end_layout \begin_layout Standard The following is a list of instance card and associated \family typewriter .MODEL \family default card examples showing use of predefined models within an XSPICE deck: \end_layout \begin_layout LyX-Code a1 1 2 amp \end_layout \begin_layout LyX-Code .model amp gain(in_offset=0.1 gain=5.0 out_offset=-0.01) \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset a2 %i[1 2] 3 sum1 \end_layout \begin_layout LyX-Code .model sum1 summer(in_offset=[0.1 -0.2] in_gain=[2.0 1.0] \end_layout \begin_layout LyX-Code + out_gain=5.0 out_offset=-0.01) \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset \end_layout \begin_layout LyX-Code a21 %i[1 %vd(2 5) 7 10] 3 sum2 \end_layout \begin_layout LyX-Code .model sum2 summer(out_gain=10.0) \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset a5 1 2 limit5 \end_layout \begin_layout LyX-Code .model limit5 limit(in_offset=0.1 gain=2.5 \end_layout \begin_layout LyX-Code + out_lower_limit=-5.0 out_upper_limit=5.0 limit_range=0.10 \end_layout \begin_layout LyX-Code + fraction=FALSE) \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset a7 2 %id(4 7) xfer_cntl1 \end_layout \begin_layout LyX-Code .model xfer_cntl1 pwl(x_array=[-2.0 -1.0 2.0 4.0 5.0] \end_layout \begin_layout LyX-Code + y_array=[-0.2 -0.2 0.1 2.0 10.0] \end_layout \begin_layout LyX-Code + input_domain=0.05 fraction=TRUE) \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset a8 3 %gd(6 7) switch3 \end_layout \begin_layout LyX-Code .model switch3 aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e6 \end_layout \begin_layout LyX-Code + r_on=10.0 log=TRUE) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Search-path-for" \end_inset Search path for file input \end_layout \begin_layout Standard Several code models ( \family typewriter filesource \family default \begin_inset CommandInset ref LatexCommand ref reference "subsec:Filesource" nolink "false" \end_inset , \family typewriter d_source \family default \begin_inset CommandInset ref LatexCommand ref reference "subsec:Digital-Source" nolink "false" \end_inset , \family typewriter d_state \family default \begin_inset CommandInset ref LatexCommand ref reference "subsec:State-Machine" nolink "false" \end_inset ) call additional files for supply of input data. A call to \family typewriter file="path/filename" \family default (or input_file=, state_file=) in the \family typewriter .model \family default card will start a search sequence for finding the file. \family typewriter path \family default may be an absolute path. If \family typewriter path \family default is omitted or is a relative path, \family typewriter filename \family default is looked for according to the following search list: \end_layout \begin_layout Labeling \labelwidthstring 00.00.0000 \family typewriter Infile_Path/ \family default (Infile_Path is the path of the input file \family sans *.sp \family default containing the netlist) \end_layout \begin_layout Labeling \labelwidthstring 00.00.0000 \family typewriter NGSPICE_INPUT_DIR/ \family default (where an additional path is set by the environmental variable) \end_layout \begin_layout Labeling \labelwidthstring 00.00.0000 \family typewriter \family default (where the search is relative to the current directory (OS dependent)) \end_layout \begin_layout Subsection Code model location and assessment \end_layout \begin_layout Standard To make use of the XSPICE extensions, you have to compile ngspice accordingly (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Ngspice-Installation-under" nolink "false" \end_inset ). ngspice then is prepared to load and use the code models. At the same time the code models are re-made. They are, however, not linked into ngspice at compile time, but reside in extra shared libraries or dlls, with names \family sans analog.cm \family default , \family sans digital.cm \family default , \family sans spice2poly.cm \family default , \family sans xtradev.cm \family default , \family sans xtraevt.cm \family default , and \family sans table.cm \family default . At run time, with XSPICE enabled, they are loaded dynamically into ngspice by the command \family typewriter codemodel \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Codemodel:-Load-an" nolink "false" \end_inset ). The sequence to load the codemodels is: Upon start-up ngspice locates, reads, and executes \family sans spinit \family default , the standard initialization file ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" nolink "false" \end_inset ). Within \family sans spinit \family default , you will find the commands to load the codemodels, typically with a path for the code models relative to the current working directory (the location of ngspice, in case of shared ngspice the location of the caller). \end_layout \begin_layout Standard If you don't want to make use of \family sans spinit \family default , you may run a script in ngspice, before loading any circuit, which contains the \family typewriter codemodel \family default commands. When using shared ngspice, one may issue the codemodel commands directly after initialization, with absolute path or path relative to the current working directory. \end_layout \begin_layout Standard In a standard ngspice installation in MS Windows, the codemodels are located in \family sans ../lib/ngspice \family default , e.g. in \family sans C: \backslash Spice64 \backslash lib \backslash ngspice \family default (see also \begin_inset CommandInset ref LatexCommand ref reference "subsec:make-ngspice-with-1" nolink "false" \end_inset ). \end_layout \begin_layout Standard In Linux, it depends on the OS invocation. In openSUSE you may find the codemodels in \family sans /usr/local/lib64/ngspice \family default , while ngspice resides in \family sans /usr/local/bin \family default . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:XSPICE-Analog-Models" \end_inset Analog Models \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Code models ! analog models \end_layout \end_inset \end_layout \begin_layout Standard The following analog models are supplied with XSPICE. The descriptions included consist of the model Interface Specification File and a description of the model's operation. This is followed by an example of a simulator-deck placement of the model, including the \family typewriter .MODEL \family default card and the specification of all available parameters. \end_layout \begin_layout Subsection Gain \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_gain \end_layout \begin_layout LyX-Code Spice_Model_Name: gain \end_layout \begin_layout LyX-Code Description: "A simple gain block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector.Bounds: - - \end_layout \begin_layout LyX-Code Null.Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain out_offset \end_layout \begin_layout LyX-Code Description: "input offset" "gain" "output offset" \end_layout \begin_layout LyX-Code Data_Type: real real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - - \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: noise_voltage noise_current \end_layout \begin_layout LyX-Code Description: "noise voltage" "noise current" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: noise_corner noise_exponent \end_layout \begin_layout LyX-Code Description: "1/f corner freq" "1/f exponent" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: This function is a simple gain block with optional offsets on the input and the output. The input offset is added to the input, the sum is then multiplied by the gain, and the result is produced by adding the output offset. This model will operate in DC, AC, NOISE and Transient analysis modes. The four parameters \family typewriter noise_xxx \family default , if selected, will add white and/or 1/f small signal noise sources to the input and output. \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout a1 1 2 amp \end_layout \begin_layout Plain Layout .model amp gain(in_offset=0.1 gain=5.0 \end_layout \begin_layout Plain Layout + out_offset=-0.01) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout a2 in1 out2 amp2 \end_layout \begin_layout Plain Layout .model amp2 gain(in_offset=0.1 gain=5.0 \end_layout \begin_layout Plain Layout + out_offset=-0.01 noise_voltage=2u noise_corner=1k noise_exponent=1.2) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Summer \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_summer \end_layout \begin_layout LyX-Code Spice_Model_Name: summer \end_layout \begin_layout LyX-Code Description: "A summer block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input vector" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset in_gain \end_layout \begin_layout LyX-Code Description: "input offset vector" "input gain vector" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: in in \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_gain out_offset \end_layout \begin_layout LyX-Code Description: "output gain" "output offset" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: This function is a summer block with 2-to-N input ports. Individual gains and offsets can be applied to each input and to the output. Each input is added to its respective offset and then multiplied by its gain. The results are then summed, multiplied by the output gain and added to the output offset. This model will operate in DC, AC, and Transient analysis modes. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example usage: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout a2 [1 2] 3 sum1 \end_layout \begin_layout Plain Layout .model sum1 summer(in_offset=[0.1 -0.2] in_gain=[2.0 1.0] \end_layout \begin_layout Plain Layout + out_gain=5.0 out_offset=-0.01) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout LyX-Code \end_layout \begin_layout Subsection Multiplier \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_mult \end_layout \begin_layout LyX-Code Spice_Model_Name: mult \end_layout \begin_layout LyX-Code Description: "multiplier block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input vector" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset in_gain \end_layout \begin_layout LyX-Code Description: "input offset vector" "input gain vector" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: in in \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_gain out_offset \end_layout \begin_layout LyX-Code Description: "output gain" "output offset" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: This function is a multiplier block with 2-to-N input ports. Individual gains and offsets can be applied to each input and to the output. Each input is added to its respective offset and then multiplied by its gain. The results are multiplied along with the output gain and are added to the output offset. This model will operate in DC, AC, and Transient analysis modes. However, in ac analysis it is important to remember that results are invalid unless only \emph on one \emph default input of the multiplier is connected to a node that i connected to an AC signal (this is exemplified by the use of a multiplier to perform a potentiometer function: one input is DC, the other carries the AC signal). \end_layout \begin_layout LyX-Code \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example SPICE Usage: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout a3 [1 2 3] 4 sigmult \end_layout \begin_layout Plain Layout .model sigmult mult(in_offset=[0.1 0.1 -0.1] \end_layout \begin_layout Plain Layout + in_gain=[10.0 10.0 10.0] out_gain=5.0 out_offset=0.05) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Divider \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_divide \end_layout \begin_layout LyX-Code Spice_Model_Name: divide \end_layout \begin_layout LyX-Code Description: "divider block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: num den out \end_layout \begin_layout LyX-Code Description: "numerator" "denominator" "output" \end_layout \begin_layout LyX-Code Direction: in in out \end_layout \begin_layout LyX-Code Default_Type: v v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: no no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: num_offset num_gain \end_layout \begin_layout LyX-Code Description: "numerator offset" "numerator gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: den_offset den_gain \end_layout \begin_layout LyX-Code Description: "denominator offset" "denominator gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: den_lower_limit \end_layout \begin_layout LyX-Code Description: "denominator lower limit" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-10 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: den_domain \end_layout \begin_layout LyX-Code Description: "denominator smoothing domain" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-10 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fraction \end_layout \begin_layout LyX-Code Description: "smoothing fraction/absolute value switch" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: false \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_gain out_offset \end_layout \begin_layout LyX-Code Description: "output gain" "output offset" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: This function is a two-quadrant divider. It takes two inputs; num (numerator) and den (denominator). Divide offsets its inputs, multiplies them by their respective gains, divides the results, multiplies the quotient by the output gain, and offsets the result. The denominator is limited to a value above zero via a user specified lower limit. This limit is approached through a quadratic smoothing function, the domain of which may be specified as a fraction of the lower limit value (default), or as an absolute value. This model will operate in DC, AC and Transient analysis modes. However, in ac analysis it is important to remember that results are invalid unless only \emph on one \emph default input of the divider is connected to a node that is connected to an ac signal (this is exemplified by the use of the divider to perform a potentiometer function: one input is dc, the other carries the ac signal). \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 1 2 4 divider \end_layout \begin_layout LyX-Code .model divider divide(num_offset=0.1 num_gain=2.5 den_offset=-0.1 \end_layout \begin_layout LyX-Code + den_gain=5.0 den_lower_limit=1e-5 den_domain=1e-6 \end_layout \begin_layout LyX-Code + fraction=FALSE out_gain=1.0 out_offset=0.0) \end_layout \begin_layout Subsection Limiter \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_limit \end_layout \begin_layout LyX-Code Spice_Model_Name: limit \end_layout \begin_layout LyX-Code Description: "limit block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain \end_layout \begin_layout LyX-Code Description: "input offset" "gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_lower_limit out_upper_limit \end_layout \begin_layout LyX-Code Description: "output lower limit" "output upper limit" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: limit_range \end_layout \begin_layout LyX-Code Description: "upper & lower smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fraction \end_layout \begin_layout LyX-Code Description: "smoothing fraction/absolute value switch" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: FALSE \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The Limiter is a single input, single output function similar to the Gain Block. However, the output of the Limiter function is restricted to the range specified by the output lower and upper limits. This model will operate in DC, AC and Transient analysis modes. Note that the limit range is the value \emph on below the upper limit and above the lower limit \emph default at which smoothing of the output begins. For this model, then, the limit range represents the delta \emph on with respect to the output level \emph default at which smoothing occurs. Thus, for an input gain of 2.0 and output limits of 1.0 and -1.0 volts, the output will begin to smooth out at \begin_inset Formula $\pm$ \end_inset 0.9 volts, which occurs when the input value is at \begin_inset Formula $\pm$ \end_inset 0.4. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a5 1 2 limit5 \end_layout \begin_layout LyX-Code .model limit5 limit(in_offset=0.1 gain=2.5 out_lower_limit=-5.0 \end_layout \begin_layout LyX-Code + out_upper_limit=5.0 limit_range=0.10 fraction=FALSE) \end_layout \begin_layout Subsection Controlled Limiter \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_climit \end_layout \begin_layout LyX-Code Spice_Model_Name: climit \end_layout \begin_layout LyX-Code Description: "controlled limiter block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in cntl_upper \end_layout \begin_layout LyX-Code Description: "input" "upper lim. control input" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: cntl_lower out \end_layout \begin_layout LyX-Code Description: "lower limit control input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain \end_layout \begin_layout LyX-Code Description: "input offset" "gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: upper_delta lower_delta \end_layout \begin_layout LyX-Code Description: "output upper delta" "output lower delta" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: limit_range fraction \end_layout \begin_layout LyX-Code Description: "upper & lower sm. range" "smoothing %/abs switch" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 1.0e-6 FALSE \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The Controlled Limiter is a single input, single output function similar to the Gain Block. However, the output of the Limiter function is restricted to the range specified by the output lower and upper limits. This model will operate in DC, AC, and Transient analysis modes. Note that the limit range is the value \emph on below the \begin_inset Formula $cntl\_upper$ \end_inset limit and above the \begin_inset Formula $cntl\_lower$ \end_inset limit \emph default at which smoothing of the output begins (minimum positive value of voltage must exist between the \emph on \begin_inset Formula $cntl\_upper$ \end_inset \emph default input and the \emph on \begin_inset Formula $cntl\_lower$ \end_inset \emph default input at all times). For this model, then, the limit range represents the delta \emph on with respect to the output level \emph default at which smoothing occurs. Thus, for an input gain of 2.0 and output limits of 1.0 and -1.0 volts, the output will begin to smooth out at \begin_inset Formula $\pm$ \end_inset 0.9 volts, which occurs when the input value is at \begin_inset Formula $\pm$ \end_inset 0.4. Note also that the Controlled Limiter code tests the input values of \begin_inset Formula $cntl\_upper$ \end_inset and \begin_inset Formula $cntl\_lower$ \end_inset to make sure that they are spaced far enough apart to guarantee the existence of a linear range between them. The range is calculated as the difference between ( \begin_inset Formula $cntl\_upper-upper\_delta-limit\_range$ \end_inset ) and ( \begin_inset Formula $cntl\_lower+lower\_delta+limit\_range$ \end_inset ) and must be greater than or equal to zero. Note that when the limit range is specified as a fractional value, the limit range used in the above is taken as the calculated fraction of the difference between \begin_inset Formula $cntl\_upper$ \end_inset and \begin_inset Formula $cntl\_lower$ \end_inset . Still, the potential exists for too great a limit range value to be specified for proper operation, in which case the model will return an error message. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code a6 3 6 8 4 varlimit \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model varlimit climit(in_offset=0.1 gain=2.5 upper_delta=0.0 \end_layout \begin_layout LyX-Code + lower_delta=0.0 limit_range=0.10 fraction=FALSE) \end_layout \begin_layout Subsection PWL Controlled Source \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_pwl \end_layout \begin_layout LyX-Code Spice_Model_Name: pwl \end_layout \begin_layout LyX-Code Description: "piecewise linear controlled source" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: x_array y_array \end_layout \begin_layout LyX-Code Description: "x-element array" "y-element array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] [2 -] \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_domain fraction \end_layout \begin_layout LyX-Code Description: "input sm. domain" "smoothing %/abs switch" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 0.01 TRUE \end_layout \begin_layout LyX-Code Limits: [1e-12 0.5] - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code Static_Var_Name: last_x_value \end_layout \begin_layout LyX-Code Data_Type: pointer \end_layout \begin_layout LyX-Code Description: "iteration holding variable for limiting" \end_layout \begin_layout Description Description: The Piece-Wise Linear Controlled Source is a single input, single output function similar to the Gain Block. However, the output of the PWL Source is not necessarily linear for all values of input. Instead, it follows an I/O relationship specified by you via the \family typewriter x_array \family default and \family typewriter y_array \family default coordinates. This is detailed below. \begin_inset Newline newline \end_inset The \family typewriter x_array \family default and \family typewriter y_array \family default values represent vectors of coordinate points on the x and y axes, respectively. The \family typewriter x_array \family default values are progressively increasing input coordinate points, and the associated \family typewriter y_array \family default values represent the outputs at those points. There may be as few as two ( \family typewriter x_array \family default [n], \family typewriter y_array \family default [n]) pairs specified, or as many as memory and simulation speed allow. This permits you to very finely approximate a non-linear function by capturing multiple input-output coordinate points. \begin_inset Newline newline \end_inset Two aspects of the PWL Controlled Source warrant special attention. These are the handling of endpoints and the smoothing of the described transfer function near coordinate points. \begin_inset Newline newline \end_inset In order to fully specify outputs for values of \family typewriter in \family default outside of the bounds of the PWL function (i.e., less than \family typewriter x_array \family default [0] or greater than \family typewriter x_array \family default [n], where n is the largest user-specified coordinate index), the PWL Controlled Source model extends the slope found between the lowest two coordinate pairs and the highest two coordinate pairs. This has the effect of making the transfer function completely linear for \family typewriter in \family default less than \family typewriter x_array \family default [0] and \family typewriter in \family default greater than \family typewriter x_array \family default [n]. It also has the potentially subtle effect of unrealistically causing an output to reach a very large or small value for large inputs. You should thus keep in mind that the PWL Source does not inherently provide a limiting capability. \begin_inset Newline newline \end_inset In order to diminish the potential for non-convergence of simulations when using the PWL block, a form of smoothing around the \family typewriter x_array \family default , \family typewriter y_array \family default coordinate points is necessary. This is due to the iterative nature of the simulator and its reliance on smooth first derivatives of transfer functions in order to arrive at a matrix solution. Consequently, the \family typewriter input_domain \family default and \family typewriter fraction \family default parameters are included to allow you some control over the amount and nature of the smoothing performed. \begin_inset Newline newline \end_inset \family typewriter Fraction \family default is a switch that is either TRUE or FALSE. When TRUE (the default setting), the simulator assumes that the specified input domain value is to be interpreted as a fractional figure. Otherwise, it is interpreted as an absolute value. Thus, if \family typewriter fraction \family default =TRUE and \family typewriter input_domain= \family default 0.10, The simulator assumes that the smoothing radius about each coordinate point is to be set equal to 10% of the length of either the \family typewriter x_array \family default segment above each coordinate point, or the \family typewriter x_array \family default segment below each coordinate point. The specific segment length chosen will be the smallest of these two for each coordinate point. \begin_inset Newline newline \end_inset On the other hand, if \family typewriter fraction \family default =FALSE and \family typewriter input_domain \family default =0.10, then the simulator will begin smoothing the transfer function at 0.10 volts (or amperes) below each \family typewriter x_array \family default coordinate and will continue the smoothing process for another 0.10 volts (or amperes) above each \family typewriter x_array \family default coordinate point. Since the overlap of smoothing domains is not allowed, checking is done by the model to ensure that the specified input domain value is not excessive. \begin_inset Newline newline \end_inset One subtle consequence of the use of the \family typewriter fraction \family default =TRUE feature of the PWL Controlled Source is that, in certain cases, you may inadvertently create extreme smoothing of functions by choosing inappropriate coordinate value points. This can be demonstrated by considering a function described by three coordinate pairs, such as (-1,-1), (1,1), and (2,1). In this case, with a 10% \family typewriter input_domain \family default value specified ( \family typewriter fraction \family default =TRUE, \family typewriter input_domain \family default =0.10), you would expect to see rounding occur between \family typewriter in \family default =0.9 and \family typewriter in \family default =1.1, and nowhere else. On the other hand, if you were to specify the same function using the coordinate pairs (-100,-100), (1,1) and (201,1), you would find that rounding occurs between \family typewriter in \family default =-19 and \family typewriter in \family default =21. Clearly in the latter case the smoothing might cause an excessive divergence from the intended linearity above and below \family typewriter in \family default =1. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a7 in out xfer_cntl1 \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code .model xfer_cntl1 pwl(x_array=[-2.0 -1.0 2.0 4.0 5.0] \end_layout \begin_layout LyX-Code + y_array=[-0.2 -0.2 0.1 2.0 10.0] \end_layout \begin_layout LyX-Code + input_domain=0.05 fraction=TRUE) \end_layout \begin_layout Subsection PWL Time Controlled Source with optional edge smoothing \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code C_Function_Name: cm_pwlts \end_layout \begin_layout LyX-Code Spice_Model_Name: pwlts \end_layout \begin_layout LyX-Code Description: "piecwise linear controlled source, time input" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Port_Name: out \end_layout \begin_layout LyX-Code Description: "output" \end_layout \begin_layout LyX-Code Direction: out \end_layout \begin_layout LyX-Code Default_Type: v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: x_array y_array \end_layout \begin_layout LyX-Code Description: "x-element array" "y-element array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] [2 -] \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: input_domain fraction \end_layout \begin_layout LyX-Code Description: "input sm. domain" "smoothing %/abs switch" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 0.01 TRUE \end_layout \begin_layout LyX-Code Limits: [1e-12 0.5] - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: limit \end_layout \begin_layout LyX-Code Description: "const or linearily extrapolated output" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: FALSE \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Static_Var_Name: last_x_value \end_layout \begin_layout LyX-Code Data_Type: pointer \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Description: "iteration holding variable for limiting" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Static_Var_Name: x y \end_layout \begin_layout LyX-Code Data_Type: pointer pointer \end_layout \begin_layout LyX-Code Description: "time array" "y-coefficient array" \end_layout \begin_layout Description Description: The Piece-Wise Linear Time Controlled Source is a time input, single output function. The output follows an time/output relationship specified by you via the \family typewriter x_array \family default and \family typewriter y_array \family default coordinates. This is detailed below. \begin_inset Newline newline \end_inset The \family typewriter x_array \family default and \family typewriter y_array \family default values represent vectors of coordinate points on the x and y axes, respectively. The \family typewriter x_array \family default values are progressively increasing positive input coordinate points (minimum is 0), and the associated \family typewriter y_array \family default values represent the outputs at those points. There may be as few as two ( \family typewriter x_array \family default [n], \family typewriter y_array \family default [n]) pairs specified, or as many as memory and simulation speed allow. This permits you to very finely approximate a non-linear time dependent waveform by capturing multiple input-output coordinate points. \begin_inset Newline newline \end_inset Two aspects of the PWLTS Controlled Source warrant special attention. These are the handling of endpoints and the smoothing of the described transfer function near coordinate points. \begin_inset Newline newline \end_inset In order to fully specify outputs for values of \family typewriter in \family default outside of the bounds of the PWLTS function (i.e., less than \family typewriter x_array \family default [0] (with \family typewriter x_array \family default [0] >= 0 always) or greater than \family typewriter x_array \family default [n], where n is the largest user-specified coordinate index), the PWLTS Time Controlled Source model extends the slope found between the lowest two coordinate pairs and the highest two coordinate pairs. This has the effect of making the transfer function completely linear for times less than \family typewriter x_array \family default [0] and times greater than \family typewriter x_array \family default [n]. It also has the potentially subtle effect of unrealistically causing an output to reach a very large or small value for large input times. \begin_inset Newline newline \end_inset In order to diminish the potential for non-convergence of simulations when using the PWL block, a form of smoothing around the \family typewriter x_array \family default , \family typewriter y_array \family default coordinate points is necessary. This is due to the iterative nature of the simulator and its reliance on smooth first derivatives of transfer functions in order to arrive at a matrix solution. Consequently, the \family typewriter input_domain \family default and \family typewriter fraction \family default parameters are included to allow you some control over the amount and nature of the smoothing performed. \begin_inset Newline newline \end_inset \family typewriter Fraction \family default is a switch that is either TRUE or FALSE. When TRUE (the default setting), the simulator assumes that the specified input domain value is to be interpreted as a fractional figure. Otherwise, it is interpreted as an absolute value. Thus, if \family typewriter fraction \family default =TRUE and \family typewriter input_domain= \family default 0.10, the simulator assumes that the smoothing radius about each coordinate point is to be set equal to 10% of the length of either the \family typewriter x_array \family default segment above each coordinate point, or the \family typewriter x_array \family default segment below each coordinate point. The specific segment length chosen will be the smallest of these two for each coordinate point. \begin_inset Newline newline \end_inset On the other hand, if \family typewriter fraction \family default =FALSE and \family typewriter input_domain \family default =0.10, then the simulator will begin smoothing the transfer function at 0.10 seconds below each \family typewriter x_array \family default coordinate and will continue the smoothing process for another 0.10 seconds above each \family typewriter x_array \family default coordinate point. Since the overlap of smoothing domains is not allowed, checking is done by the model to ensure that the specified input domain value is not excessive. \begin_inset Newline newline \end_inset One subtle consequence of the use of the \family typewriter fraction \family default =TRUE feature of the PWL Time Controlled Source is that, in certain cases, you may inadvertently create extreme smoothing of functions by choosing inappropriate coordinate value points. This can be demonstrated by considering a function described by three coordinate pairs, such as (0,-1), (2,1), and (3,1). In this case, with a 10% \family typewriter input_domain \family default value specified ( \family typewriter fraction \family default =TRUE, \family typewriter input_domain \family default =0.10), you would expect to see rounding occur between time=1.9 and time=2.1, and nowhere else. On the other hand, if you were to specify the same function using the coordinate pairs (0,-100), (101,1) and (301,1), you would find that rounding occurs between time=81 and time=121. Clearly in the latter case the smoothing might cause an excessive divergence from the intended linearity above and below time=101. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a8 out pwl_cntl1 \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code .model pwl_cntl1 pwlts(x_array=[0 1m 1.1m 2m 2.1m] \end_layout \begin_layout LyX-Code + y_array=[-0.2 -0.2 0.6 0.6 0.35] \end_layout \begin_layout LyX-Code + input_domain=0.2 fraction=TRUE \end_layout \begin_layout LyX-Code + limit=TRUE) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Filesource" \end_inset Filesource (PWL sourced from file) \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code C_Function_Name: cm_filesource \end_layout \begin_layout LyX-Code Spice_Model_Name: filesource \end_layout \begin_layout LyX-Code Description: "File Source" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Port_Name: out \end_layout \begin_layout LyX-Code Description: "output" \end_layout \begin_layout LyX-Code Direction: out \end_layout \begin_layout LyX-Code Default_Type: v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: timeoffset timescale \end_layout \begin_layout LyX-Code Description: "time offset" "timescale" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: timerelative amplstep \end_layout \begin_layout LyX-Code Description: "relative time" "step amplitude" \end_layout \begin_layout LyX-Code Data_Type: boolean boolean \end_layout \begin_layout LyX-Code Default_Value: FALSE FALSE \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: amploffset amplscale \end_layout \begin_layout LyX-Code Description: "ampl offset" "amplscale" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: file \end_layout \begin_layout LyX-Code Description: "file name" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: "filesource.txt" \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout Description Description: The File Source is similar to the Piece-Wise Linear (PWL) Source, except that the waveform data is read from a file instead of being taken from parameter vectors. The file format is line oriented ASCII. ` \family typewriter # \family default ' and ` \family typewriter ; \family default ' are comment characters; all characters from a comment character until the end of the line are ignored. Each line consists of two or more real values. The first value is the time; subsequent values correspond to the outputs. Values are separated by spaces. Time values are absolute and must be monotonically increasing, unless \family sans timerelative \family default is set to TRUE, in which case the values specify the interval between two samples and must be positive. Waveforms may be scaled and shifted in the time dimension by setting \family sans timescale \family default and \family sans timeoffset \family default . \begin_inset Newline newline \end_inset Amplitudes can also be scaled and shifted using \family sans amplscale \family default and \family sans amploffset \family default . Amplitudes are normally interpolated between two samples, unless \family sans amplstep \family default is set to TRUE. \begin_inset Newline newline \end_inset \end_layout \begin_layout Description Note: The file named by the parameter \family typewriter filename \family default in \family typewriter file= \family default " \family typewriter filename \family default " is sought after according to a search list described in \begin_inset CommandInset ref LatexCommand ref reference "subsec:Search-path-for" nolink "false" \end_inset . \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a8 %vd([1 0 2 0]) filesrc \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model filesrc filesource (file="sine.m" amploffset=[0 0] amplscale=[1 1] \end_layout \begin_layout LyX-Code + timeoffset=0 timescale=1 \end_layout \begin_layout LyX-Code + timerelative=false amplstep=false) \end_layout \begin_layout LyX-Code \begin_inset VSpace 1cm \end_inset \end_layout \begin_layout LyX-Code Example input file: \end_layout \begin_layout LyX-Code # name: sine.m \end_layout \begin_layout LyX-Code # two output ports \end_layout \begin_layout LyX-Code # column 1: time \end_layout \begin_layout LyX-Code # columns 2, 3: values \end_layout \begin_layout LyX-Code 0 0 1 \end_layout \begin_layout LyX-Code 3.90625e-09 0.02454122852291229 0.9996988186962042 \end_layout \begin_layout LyX-Code 7.8125e-09 0.04906767432741801 0.9987954562051724 \end_layout \begin_layout LyX-Code 1.171875e-08 0.07356456359966743 0.9972904566786902 \end_layout \begin_layout LyX-Code ... \end_layout \begin_layout LyX-Code \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:multi_input_pwl_block" \end_inset Multi_input_PWL_block \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code C_Function_Name: cm_multi_input_pwl \end_layout \begin_layout LyX-Code Spice_Model_Name: multi_input_pwl \end_layout \begin_layout LyX-Code Description: "multi_input_pwl block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input array" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: vd vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd,id] [vd,id] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: x y \end_layout \begin_layout LyX-Code Description: "x array" "y array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] [2 -] \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: model \end_layout \begin_layout LyX-Code Description: "model type" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: "and" \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: Multi-input gate voltage controlled voltage source that supports \series bold and \series default or \series bold or \series default gating. The x's and y's represent the piecewise linear variation of output (y) as a function of input (x). The type of gate is selectable by the parameter \family typewriter model \family default . In case the model is \series bold and \series default , the smallest input determines the output value (i.e. the \family typewriter and \family default function). In case the model is \series bold or \series default , the largest input determines the output value (i.e. the \family typewriter or \family default function). The inverse of these functions (i.e. \family typewriter nand \family default and \family typewriter nor \family default ) is constructed by complementing the y array. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code a82 [1 0 2 0 3 0] 7 0 pwlm \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model pwlm multi_input_pwl((x=[-2.0 -1.0 2.0 4.0 5.0] \end_layout \begin_layout LyX-Code + y=[-0.2 -0.2 0.1 2.0 10.0] \end_layout \begin_layout LyX-Code + model="and") \end_layout \begin_layout LyX-Code \end_layout \begin_layout Subsection Analog Switch \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_aswitch \end_layout \begin_layout LyX-Code Spice_Model_Name: aswitch \end_layout \begin_layout LyX-Code Description: "analog switch" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: cntl_in out \end_layout \begin_layout LyX-Code Description: "input" "resistive output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v gd \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [gd] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_off cntl_on \end_layout \begin_layout LyX-Code Description: "control `off' value" "control `on' value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: r_off log \end_layout \begin_layout LyX-Code Description: "off resistance" "log/linear switch" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 1.0e12 TRUE \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: r_on limit \end_layout \begin_layout LyX-Code Description: "on resistance" "set upper and lower \end_layout \begin_layout LyX-Code limits to resistance" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 1.0 false \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The Analog Switch is a resistor that varies either logarithmically or linearly between specified values of a controlling input voltage or current. Note that the input is not internally limited when parameter \family typewriter limit \family default is not given. Therefore, if the controlling signal exceeds the specified OFF state or ON state value, the resistance may become excessively large or excessively small (in the case of logarithmic dependence), or may become negative (in the case of linear dependence). For the experienced user, these excursions may prove valuable for modeling certain devices, but in most cases you are advised to add limiting of the controlling input if the possibility of excessive control value variation exists. Alternatively you may set the parameter \family typewriter limit \family default to TRUE. Then the resulting resistance is limited to r_on or r_off if the controlling voltage exceeds the given boundaries \family typewriter cntl_on \family default or \family typewriter cntl_off \family default . At these boundaries sharp edges in the R(control) characteristics will occur which may lead to convergence problems. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code a8 3 %gd(6 7) switch3 \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model switch3 aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e6 \end_layout \begin_layout LyX-Code + r_on=10.0 log=TRUE limit=TRUE) \end_layout \begin_layout Subsection Alternative Analog Switch \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_pswitch \end_layout \begin_layout LyX-Code Spice_Model_Name: pswitch \end_layout \begin_layout LyX-Code Description: "analog switch alternative" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: cntl_in out \end_layout \begin_layout LyX-Code Description: "input" "resistive output" \end_layout \begin_layout LyX-Code Direction: inout inout \end_layout \begin_layout LyX-Code Default_Type: gd gd \end_layout \begin_layout LyX-Code Allowed_Types: [g,gd] [gd] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_off cntl_on \end_layout \begin_layout LyX-Code Description: "control `off' value" "control `on' value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: r_off log \end_layout \begin_layout LyX-Code Description: "off resistance" "log/linear switch" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 1.0e12 TRUE \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: r_on r_cntl_in \end_layout \begin_layout LyX-Code Description: "on resistance" "input resistance for control terminal" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 1e12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The Alternative Analog Switch is a resistor that varies either logarithmically or linearly between specified values of a controlling input voltage or current. An input resistance \family typewriter r_cntl_in \family default may be specified. The output resistance is limited to \family typewriter r_on \family default or \family typewriter r_off \family default . At the control boundaries \family typewriter cntl_on \family default or \family typewriter cntl_off \family default the R(control) characteristics are slightly rounded. This behaviour is PSPICE-compatible and instances of this device are generated when parsing PSPICE netlists in compatability mode. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code a9 %g 13 %gd(16 17) switch4 \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model switch4 pswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e6 \end_layout \begin_layout LyX-Code + r_on=10.0 r_cntl_in=1e11 log=TRUE) \end_layout \begin_layout Subsection Zener Diode \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_zener \end_layout \begin_layout LyX-Code Spice_Model_Name: zener \end_layout \begin_layout LyX-Code Description: "zener diode" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: z \end_layout \begin_layout LyX-Code Description: "zener" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: gd \end_layout \begin_layout LyX-Code Allowed_Types: [gd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: v_breakdown i_breakdown \end_layout \begin_layout LyX-Code Description: "breakdown voltage" "breakdown current" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - 2.0e-2 \end_layout \begin_layout LyX-Code Limits: [1.0e-6 1.0e6] [1.0e-9 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: i_sat n_forward \end_layout \begin_layout LyX-Code Description: "saturation current" "forward emission coefficient" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0 \end_layout \begin_layout LyX-Code Limits: [1.0e-15 -] [0.1 10] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: limit_switch \end_layout \begin_layout LyX-Code Description: "switch for on-board limiting (convergence aid)" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: FALSE \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code Static_Var_Name: previous_voltage \end_layout \begin_layout LyX-Code Data_Type: pointer \end_layout \begin_layout LyX-Code Description: "iteration holding variable for limiting" \end_layout \begin_layout Description Description: The Zener Diode models the DC characteristics of most zeners. This model differs from the Diode/Rectifier by providing a user-defined dynamic resistance in the reverse breakdown region. The forward characteristic is defined by only a single point, since most data sheets for zener diodes do not give detailed characteristics in the forward region. \begin_inset Newline newline \end_inset The first three parameters define the DC characteristics of the zener in the breakdown region and are usually explicitly given on the data sheet. \begin_inset Newline newline \end_inset The saturation current refers to the relatively constant reverse current that is produced when the voltage across the zener is negative, but breakdown has not been reached. The reverse leakage current determines the slight increase in reverse current as the voltage across the zener becomes more negative. It is modeled as a resistance parallel to the zener with value v breakdown / i rev. \begin_inset Newline newline \end_inset Note that the limit switch parameter engages an internal limiting function for the zener. This can, in some cases, prevent the simulator from converging to an unrealistic solution if the voltage across or current into the device is excessive. If use of this feature fails to yield acceptable results, the convlimit option should be tried (add the following statement to the SPICE input deck: \family typewriter .options \family default convlimit) \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a9 3 4 vref10 \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model vref10 zener(v_breakdown=10.0 i_breakdown=0.02 \end_layout \begin_layout LyX-Code + r_breakdown=1.0 i_rev=1e-6 i_sat=1e-12) \end_layout \begin_layout Subsection Current Limiter \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_ilimit \end_layout \begin_layout LyX-Code Spice_Model_Name: ilimit \end_layout \begin_layout LyX-Code Description: "current limiter block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in pos_pwr \end_layout \begin_layout LyX-Code Description: "input" "positive power supply" \end_layout \begin_layout LyX-Code Direction: in inout \end_layout \begin_layout LyX-Code Default_Type: v g \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd] [g,gd] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: neg_pwr out \end_layout \begin_layout LyX-Code Description: "negative power supply" "output" \end_layout \begin_layout LyX-Code Direction: inout inout \end_layout \begin_layout LyX-Code Default_Type: g g \end_layout \begin_layout LyX-Code Allowed_Types: [g,gd] [g,gd] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain \end_layout \begin_layout LyX-Code Description: "input offset" "gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: r_out_source r_out_sink \end_layout \begin_layout LyX-Code Description: "sourcing resistance" "sinking resistance" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 1.0 \end_layout \begin_layout LyX-Code Limits: [1.0e-9 1.0e9] [1.0e-9 1.0e9] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: i_limit_source \end_layout \begin_layout LyX-Code Description: "current sourcing limit" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: i_limit_sink \end_layout \begin_layout LyX-Code Description: "current sinking limit" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: v_pwr_range i_source_range \end_layout \begin_layout LyX-Code Description: "upper & lower power "sourcing current \end_layout \begin_layout LyX-Code supply smoothing range" smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-6 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-15 -] [1.0e-15 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: i_sink_range \end_layout \begin_layout LyX-Code Description: "sinking current smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-15 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: r_out_domain \end_layout \begin_layout LyX-Code Description: "internal/external voltage delta smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-15 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The Current Limiter models the behavior of an operational amplifier or comparator device at a high level of abstraction. All of its pins act as inputs; three of the four also act as outputs. The model takes as input a voltage value from the \family typewriter in \family default connector. It then applies an offset and a gain, and derives from it an equivalent internal voltage ( \emph on veq \emph default ), which it limits to fall between \family typewriter pos_pwr \family default and \family typewriter neg_pwr \family default . If \emph on veq \emph default is greater than the output voltage seen on the \family typewriter out \family default connector, a sourcing current will flow from the output pin. Conversely, if the voltage is less than \emph on vout \emph default , a sinking current will flow into the output pin. \begin_inset Newline newline \end_inset Depending on the polarity of the current flow, either a sourcing or a sinking resistance value ( \family typewriter r_out_source \family default , \family typewriter r_out_sink \family default ) is applied to govern the \family typewriter vout/i_out \family default relationship. The chosen resistance will continue to control the output current until it reaches a maximum value specified by either \family typewriter i_limit_source \family default or \family typewriter i_limit_sink \family default . The latter mimics the current limiting behavior of many operational amplifier output stages. \begin_inset Newline newline \end_inset During all operation, the output current is reflected either in the \family typewriter pos_pwr \family default connector current or the \family typewriter neg_pwr \family default current, depending on the polarity of \family typewriter i_out \family default . Thus, realistic power consumption as seen in the supply rails is included in the model. \begin_inset Newline newline \end_inset The user-specified smoothing parameters relate to model operation as follows: \family typewriter v_pwr_range \family default controls the voltage below \family typewriter vpos_pwr \family default and above \family typewriter vneg_pwr \family default inputs beyond which \begin_inset Formula $veq=gain\:(vin+v_{offset})$ \end_inset is smoothed; \family typewriter i_source_range \family default specifies the current below \family typewriter i_limit_source \family default at which smoothing begins, as well as specifying the current increment above \family typewriter i_out \family default =0.0 at which \family typewriter i_pos_pwr \family default begins to transition to zero; \family typewriter i_sink_range \family default serves the same purpose with respect to \family typewriter i_limit_sink \family default and \family typewriter i_neg_pwr \family default that \family typewriter i_source_range \family default serves for \family typewriter i_limit_source \family default and \family typewriter i_pos_pwr \family default ; \family typewriter r_out_domain \family default specifies the incremental value above and below ( \family typewriter veq-vout \family default )=0.0 at which \family typewriter r_out \family default will be set to \family typewriter r_out_source \family default and \family typewriter r_out_sink \family default , respectively. For values of ( \family typewriter veq-vout \family default ) less than \family typewriter r_out_domain \family default and greater than \family typewriter -r_out_domain \family default , \family typewriter r_out \family default is interpolated smoothly between \family typewriter r_out_source \family default and \family typewriter r_out_sink \family default . \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a10 3 10 20 4 amp3 \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model amp3 ilimit(in_offset=0.0 gain=16.0 r_out_source=1.0 \end_layout \begin_layout LyX-Code + r_out_sink=1.0 i_limit_source=1e-3 \end_layout \begin_layout LyX-Code + i_limit_sink=10e-3 v_pwr_range=0.2 \end_layout \begin_layout LyX-Code + i_source_range=1e-6 i_sink_range=1e-6 \end_layout \begin_layout LyX-Code + r_out_domain=1e-6) \end_layout \begin_layout Subsection Hysteresis Block \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_hyst \end_layout \begin_layout LyX-Code Spice_Model_Name: hyst \end_layout \begin_layout LyX-Code Description: "hysteresis block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_low in_high \end_layout \begin_layout LyX-Code Description: "input low value" "input high value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: hyst out_lower_limit \end_layout \begin_layout LyX-Code Description: "hysteresis" "output lower limit" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.1 0.0 \end_layout \begin_layout LyX-Code Limits: [0.0 -] - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_upper_limit input_domain \end_layout \begin_layout LyX-Code Description: "output upper limit" "input smoothing domain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 0.01 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fraction \end_layout \begin_layout LyX-Code Description: "smoothing fraction/absolute value switch" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: TRUE \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The Hysteresis block is a simple buffer stage that provides hysteresis of the output with respect to the input. The \family typewriter in_low \family default and \family typewriter in_high \family default parameter values specify the center voltage or current inputs about which the hysteresis effect operates. The output values are limited to \family typewriter out_lower_limit \family default and \family typewriter out_upper_limit \family default . The value of \family typewriter hyst \family default is added to the \family typewriter in_low \family default and \family typewriter in_high \family default points in order to specify the points at which the slope of the hysteresis function would normally change abruptly as the input transitions from a low to a high value. Likewise, the value of \family typewriter hyst \family default is subtracted from the in high and in low values in order to specify the points at which the slope of the hysteresis function would normally change abruptly as the input transitions from a high to a low value. In fact, the slope of the hysteresis function is never allowed to change abruptly but is smoothly varied whenever the input domain smoothing parameter is set greater than zero. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a11 1 2 schmitt1 \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model schmitt1 hyst(in_low=0.7 in_high=2.4 hyst=0.5 \end_layout \begin_layout LyX-Code + out_lower_limit=0.5 out_upper_limit=3.0 \end_layout \begin_layout LyX-Code + input_domain=0.01 fraction=TRUE) \end_layout \begin_layout Subsection Differentiator \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_dt \end_layout \begin_layout LyX-Code Spice_Model_Name: d_dt \end_layout \begin_layout LyX-Code Description: "time-derivative block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: gain out_offset \end_layout \begin_layout LyX-Code Description: "gain" "output offset" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_lower_limit out_upper_limit \end_layout \begin_layout LyX-Code Description: "output lower limit" "output upper limit" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: limit_range \end_layout \begin_layout LyX-Code Description: "upper & lower limit smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The Differentiator block is a simple derivative stage that approximates the time derivative of an input signal by calculating the incremental slope of that signal since the previous time point. The block also includes gain and output offset parameters to allow for tailoring of the required signal, and output upper and lower limits to prevent convergence errors resulting from excessively large output values. The incremental value of output below the output upper limit and above the output lower limit at which smoothing begins is specified via the limit range parameter. In AC analysis, the value returned is equal to the radian frequency of analysis multiplied by the gain. \begin_inset Newline newline \end_inset Note that since truncation error checking is not included in the d_dt block, it is not recommended that the model be used to provide an integration function through the use of a feedback loop. Such an arrangement could produce erroneous results. Instead, you should make use of the "integrate" model, which does include truncation error checking for enhanced accuracy. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a12 7 12 slope_gen \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model slope_gen d_dt(out_offset=0.0 gain=1.0 \end_layout \begin_layout LyX-Code + out_lower_limit=1e-12 out_upper_limit=1e12 \end_layout \begin_layout LyX-Code + limit_range=1e-9) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Integrator" \end_inset Integrator \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_int \end_layout \begin_layout LyX-Code Spice_Model_Name: int \end_layout \begin_layout LyX-Code Description: "time-integration block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain \end_layout \begin_layout LyX-Code Description: "input offset" "gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_lower_limit out_upper_limit \end_layout \begin_layout LyX-Code Description: "output lower limit" "output upper limit" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: limit_range \end_layout \begin_layout LyX-Code Description: "upper & lower limit smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_ic \end_layout \begin_layout LyX-Code Description: "output initial condition" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The Integrator block is a simple integration stage that approximates the integral with respect to time of an input signal. The block also includes gain and input offset parameters to allow for tailoring of the required signal, and output upper and lower limits to prevent convergence errors resulting from excessively large output values. Note that these limits specify integrator behavior similar to that found in an operational amplifier-based integration stage, in that once a limit is reached, additional storage does not occur. Thus, the input of a negative value to an integrator that is currently driving at the out upper limit level will immediately cause a drop in the output, regardless of how long the integrator was previously summing positive inputs. The incremental value of output below the output upper limit and above the output lower limit at which smoothing begins is specified via the limit range parameter. In AC analysis, the value returned is equal to the gain divided by the radian frequency of analysis. \begin_inset Newline newline \end_inset Note that truncation error checking is included in the \family typewriter int \family default block. This should provide for a more accurate simulation of the time integration function, since the model will inherently request smaller time increments between simulation points if truncation errors would otherwise be excessive. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a13 7 12 time_count \end_layout \begin_layout LyX-Code .model time_count int(in_offset=0.0 gain=1.0 \end_layout \begin_layout LyX-Code + out_lower_limit=-1e12 out_upper_limit=1e12 \end_layout \begin_layout LyX-Code + limit_range=1e-9 out_ic=0.0) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:S-Domain-Transfer-Function" \end_inset S-Domain Transfer Function \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_s_xfer \end_layout \begin_layout LyX-Code Spice_Model_Name: s_xfer \end_layout \begin_layout LyX-Code Description: "s-domain transfer function" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain \end_layout \begin_layout LyX-Code Description: "input offset" "gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: num_coeff \end_layout \begin_layout LyX-Code Description: "numerator polynomial coefficients" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: den_coeff \end_layout \begin_layout LyX-Code Description: "denominator polynomial coefficients" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: int_ic \end_layout \begin_layout LyX-Code Description: "integrator stage initial conditions" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: den_coeff \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: denormalized_freq \end_layout \begin_layout LyX-Code Description: "denorm. corner freq.(radians) for 1 rad/s coeffs" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The s-domain transfer function is a single input, single output transfer function in the Laplace transform variable ` \family typewriter s \family default ' that allows for flexible modulation of the frequency domain characteristics of a signal. Ac and transient simulations are supported. The code model may be configured to produce an arbitrary s-domain transfer function with the following restrictions: \end_layout \begin_layout LyX-Code 1. The degree of the numerator polynomial cannot exceed that \end_layout \begin_layout LyX-Code of the denominator polynomial in the variable "s". \end_layout \begin_layout LyX-Code 2. The coefficients for a polynomial must be stated \end_layout \begin_layout LyX-Code explicitly. That is, if a coefficient is zero, it must be \end_layout \begin_layout LyX-Code included as an input to the num coeff or den coeff vector. \end_layout \begin_layout Standard The order of the coefficient parameters is from that associated with the highest-powered term decreasing to that of the lowest. Thus, for the coefficient parameters specified below, the equation in ` \family typewriter s \family default ' is shown: \end_layout \begin_layout LyX-Code .model filter s_xfer(gain=0.139713 \end_layout \begin_layout LyX-Code + num_coeff=[1.0 0.0 0.7464102] \end_layout \begin_layout LyX-Code + den_coeff=[1.0 0.998942 0.001170077] \end_layout \begin_layout LyX-Code + int_ic=[0 0]) \end_layout \begin_layout LyX-Code \end_layout \begin_layout Standard It specifies a transfer function of the form \end_layout \begin_layout Standard \align center \begin_inset Formula $N(s)=0.139713\cdot\frac{s^{2}+0.7464102}{s^{2}+0.998942s+0.00117077}$ \end_inset \end_layout \begin_layout Standard The s-domain transfer function includes \series bold gain \series default and \series bold in_offset \series default (input offset) parameters to allow for tailoring of the required signal. There are no limits on the internal signal values or on the output value of the s-domain transfer function, so you are cautioned to specify gain and coefficient values that will not cause the model to produce excessively large values. In AC analysis, the value returned is equal to the real and imaginary components of the total s-domain transfer function at each frequency of interest. \end_layout \begin_layout Standard The \series bold denormalized_freq \series default term allows you to specify coefficients for a normalized filter (i.e. one in which the frequency of interest is 1 rad/s). Once these coefficients are included, specifying the denormalized frequency value `shifts' the corner frequency to the actual one of interest. As an example, the following transfer function describes a Chebyshev low-pass filter with a corner (pass-band) frequency of 1 rad/s: \begin_inset Separator latexpar \end_inset \end_layout \begin_layout Standard \align center \begin_inset Formula $N(s)=0.139713\cdot\frac{1.0}{s^{2}+1.09773s+1.10251}$ \end_inset \end_layout \begin_layout Standard In order to define an s_xfer model for the above, but with the corner frequency equal to 1500 rad/s (239 Hz), the following instance and model lines would be needed: \end_layout \begin_layout LyX-Code a12 node1 node2 cheby1 \end_layout \begin_layout LyX-Code .model cheby1 s_xfer(num_coeff=[1] den_coeff=[1 1.09773 1.10251] \end_layout \begin_layout LyX-Code + int_ic=[0 0] denormalized_freq=1500) \end_layout \begin_layout Standard In the above, you add the normalized coefficients and scale the filter through the use of the denormalized freq parameter. Similar results could have been achieved by performing the denormalization prior to specification of the coefficients, and setting denormalized freq to the value 1.0 (or not specifying the frequency, as the default is 1.0 rad/s) Note in the above that frequencies are \emph on always specified as radians/second \emph default . \end_layout \begin_layout Standard Truncation error checking is included in the s-domain transfer block. This should provide for more accurate simulations, since the model will inherently request smaller time increments between simulation points if truncation errors would otherwise be excessive. \end_layout \begin_layout Standard The \series bold int_ic \series default parameter is an array that must be of size one less as the array of values specified for the \series bold den_coeff \series default parameter. Even if a 0 start value is required, you have to add the specific int_ic vector to the set of coefficients (see the examples above and below). \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a14 9 22 cheby_LP_3kHz \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code . \end_layout \begin_layout LyX-Code .model cheby_LP_3kHz s_xfer(in_offset=0.0 gain=1.0 int_ic=[0 0] \end_layout \begin_layout LyX-Code + num_coeff=[1.0] \end_layout \begin_layout LyX-Code + den_coeff=[1.0 1.42562 1.51620]) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:PWL-Transfer-Function" \end_inset PWL Transfer Function \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Spice_Model_Name: xfer \end_layout \begin_layout LyX-Code C_Function_Name: cm_xfer \end_layout \begin_layout LyX-Code Description: "AC transfer function block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: table \end_layout \begin_layout LyX-Code Description: "PWL table: frequency/magnitude/phase" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [3 -] \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: file \end_layout \begin_layout LyX-Code Description: "File in Touchstone format" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: r_i \end_layout \begin_layout LyX-Code Description: "table is in real/imaginary format" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: false \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: db \end_layout \begin_layout LyX-Code Description: "table is in magnitude(dB)/phase format" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: true \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: rad \end_layout \begin_layout LyX-Code Description: "phase in radians, not degrees" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: false \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: span offset \end_layout \begin_layout LyX-Code Description: "Length of table rows" "Offset within row" \end_layout \begin_layout LyX-Code Data_Type: int int \end_layout \begin_layout LyX-Code Default_Value: 3 1 \end_layout \begin_layout LyX-Code Limits: [ 3 - ] [ 1 - ] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code /* This is used internally to store the table in compact complex form. */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Static_Var_Name: table \end_layout \begin_layout LyX-Code Description: "Internal copy of data" \end_layout \begin_layout LyX-Code Data_Type: pointer \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code /* Only warn once about use in transient analysis. */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Static_Var_Name: warned \end_layout \begin_layout LyX-Code Description: "Warning indicator" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code \end_layout \begin_layout Standard This code model is useful only in AC analysis, where it applies a complex transfer function to its input. The current circuit frequency is input to a PWL function defined by a table and the output is produced by multiplying the input by the resulting complex number. The parameters supply the PWL table and determine its format. The \begin_inset Quotes eld \end_inset table \begin_inset Quotes erd \end_inset parameter supplies the data directly, while \begin_inset Quotes eld \end_inset file \begin_inset Quotes erd \end_inset defines a path (which must be all lower-case) to a file in Touchstone format containing the data. Exactly one of those parameters must be specified. \end_layout \begin_layout Standard The data is treated as consisting of rows, each of \begin_inset Quotes eld \end_inset span \begin_inset Quotes erd \end_inset real numbers. The first number is the frequency of a PWL corner and a pair of numbers at the \begin_inset Quotes eld \end_inset offset \begin_inset Quotes erd \end_inset position in the row supply the data. That allows a single Touchstone file to be shared by several instances of this code model, as such files for an n-port device will contain logical rows of 2*n^2+1 numbers: one frequency value and the components of an NxN complex matrix. The format of the data pairs is determined by the \begin_inset Quotes eld \end_inset db \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset rad \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset r_i \begin_inset Quotes erd \end_inset parameters. If any of these are set, they override the internal indicators in a Touchstone file which themselves override the parameter defaults. \end_layout \begin_layout Standard Examples of using this model are in the examples/sp directory: netlist file.sp shows direct use, while filter.sp uses the E-source wrapper ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:FREQ" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ). \end_layout \begin_layout Subsection Slew Rate Block \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_slew \end_layout \begin_layout LyX-Code Spice_Model_Name: slew \end_layout \begin_layout LyX-Code Description: "A simple slew rate follower block" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_slope \end_layout \begin_layout LyX-Code Description: "maximum rising slope value" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e9 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fall_slope \end_layout \begin_layout LyX-Code Description: "maximum falling slope value" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e9 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: range \end_layout \begin_layout LyX-Code Description: "smoothing range" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.1 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: This function is a simple slew rate block that limits the absolute slope of the output with respect to time to some maximum or value. The actual slew rate effects of over-driving an amplifier circuit can thus be accurately modeled by cascading the amplifier with this model. The units used to describe the maximum rising and falling slope values are expressed in volts or amperes per second. Thus a desired slew rate of 0.5 V/ \begin_inset Formula $\mu s$ \end_inset will be expressed as 0.5e+6, etc. \begin_inset Newline newline \end_inset The slew rate block will continue to raise or lower its output until the difference between the input and the output values is zero. Thereafter, it will resume following the input signal, unless the slope again exceeds its rise or fall slope limits. The range input specifies a smoothing region above or below the input value. Whenever the model is slewing and the output comes to within the input + or - the range value, the partial derivative of the output with respect to the input will begin to smoothly transition from 0.0 to 1.0. When the model is no longer slewing (output = input), dout/din will equal 1.0. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a15 1 2 slew1 \end_layout \begin_layout LyX-Code .model slew1 slew(rise_slope=0.5e6 fall_slope=0.5e6) \end_layout \begin_layout Subsection Inductive Coupling \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_lcouple \end_layout \begin_layout LyX-Code Spice_Model_Name: lcouple \end_layout \begin_layout LyX-Code Description: "inductive coupling (for use with 'core' model)" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: l mmf_out \end_layout \begin_layout LyX-Code Description: "inductor" "mmf output (in ampere-turns)" \end_layout \begin_layout LyX-Code Direction: inout inout \end_layout \begin_layout LyX-Code Default_Type: hd hd \end_layout \begin_layout LyX-Code Allowed_Types: [h,hd] [hd] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: num_turns \end_layout \begin_layout LyX-Code Description: "number of inductor turns" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: This function is a conceptual model that is used as a building block to create a wide variety of inductive and magnetic circuit models. This function is normally used in conjunction with the \family typewriter core \family default model, but can also be used with resistors, hysteresis blocks, etc. to build up systems that mock the behavior of linear and nonlinear components. \begin_inset Newline newline \end_inset The \family typewriter lcouple \family default takes as an input (on the ` \family typewriter l \family default ' port), a current. This current value is multiplied by the \family typewriter num_turns \family default value, \family typewriter N \family default , to produce an output value (a voltage value that appears on the \family typewriter mmf_out \family default port). The mmf_out acts similar to a magnetomotive force in a magnetic circuit; when the lcouple is connected to the \family typewriter core \family default model, or to some other resistive device, a current will flow. This current value (which is modulated by whatever the lcouple is connected to) is then used by the \family typewriter lcouple \family default to calculate a voltage `seen' at the \family typewriter l \family default port. The voltage is a function of the derivative with respect to time of the current value seen at \family typewriter mmf_out \family default . \begin_inset Newline newline \end_inset The most common use for \family typewriter lcouple \family default s will be as a building block in the construction of transformer models. To create a transformer with a single input and a single output, you would require two \family typewriter lcouple \family default models plus one \family typewriter core \family default model. The process of building up such a transformer is described under the description of the \family typewriter core \family default model, below. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code a150 (7 0) (9 10) lcouple1 \end_layout \begin_layout LyX-Code .model lcouple1 lcouple(num_turns=10.0) \end_layout \begin_layout Subsection Magnetic Core \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_core \end_layout \begin_layout LyX-Code Spice_Model_Name: core \end_layout \begin_layout LyX-Code Description: "magnetic core" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: mc \end_layout \begin_layout LyX-Code Description: "magnetic core" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: gd \end_layout \begin_layout LyX-Code Allowed_Types: [g,gd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: H_array B_array \end_layout \begin_layout LyX-Code Description: "magnetic field array" "flux density array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] [2 -] \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: area length \end_layout \begin_layout LyX-Code Description: "cross-sectional area" "core length" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: - - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_domain \end_layout \begin_layout LyX-Code Description: "input sm. domain" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.01 \end_layout \begin_layout LyX-Code Limits: [1e-12 0.5] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fraction \end_layout \begin_layout LyX-Code Description: "smoothing fraction/abs switch" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: TRUE \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: mode \end_layout \begin_layout LyX-Code Description: "mode switch (1 = pwl, 2 = hyst)" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 1 \end_layout \begin_layout LyX-Code Limits: [1 2] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_low in_high \end_layout \begin_layout LyX-Code Description: "input low value" "input high value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: hyst out_lower_limit \end_layout \begin_layout LyX-Code Description: "hysteresis" "output lower limit" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.1 0.0 \end_layout \begin_layout LyX-Code Limits: [0 -] - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_upper_limit \end_layout \begin_layout LyX-Code Description: "output upper limit" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: This function is a conceptual model that is used as a building block to create a wide variety of inductive and magnetic circuit models. This function is almost always expected to be used in conjunction with the \family typewriter lcouple \family default model to build up systems that mock the behavior of linear and nonlinear magnetic components. There are two fundamental modes of operation for the core model. These are the pwl mode (which is the default, and which is the most likely to be of use to you) and the hysteresis mode. These are detailed below. \end_layout \begin_layout Standard \align center PWL Mode (mode = 1) \end_layout \begin_layout Standard The core model in PWL mode takes as input a voltage that it treats as a magnetomotive force (mmf) value. This value is divided by the total effective length of the core to produce a value for the Magnetic Field Intensity, H. This value of H is then used to find the corresponding Flux Density, B, using the piecewise linear relationship described by you in the H array / B array coordinate pairs. B is then multiplied by the cross-sectional area of the core to find the Flux value, which is output as a current. The pertinent mathematical equations are listed below: \begin_inset Separator latexpar \end_inset \end_layout \begin_layout Standard \align center \begin_inset Formula \[ H=\frac{mmf}{L},{\textstyle \;where}\;L=Length \] \end_inset \end_layout \begin_layout Standard Here H, the Magnetic Field Intensity, is expressed in ampere-turns/meter. \begin_inset Separator latexpar \end_inset \end_layout \begin_layout Standard \align center \begin_inset Formula \[ B=f(H) \] \end_inset \end_layout \begin_layout Standard The B value is derived from a piecewise linear transfer function described to the model via the (H_array[],B_array[]) parameter coordinate pairs. This transfer function does not include hysteretic effects; for that, you would need to substitute a HYST model for the core. \begin_inset Separator latexpar \end_inset \end_layout \begin_layout Standard \align center \begin_inset Formula \[ \phi=BA,{\textstyle \;where}\;A=Area \] \end_inset \end_layout \begin_layout Standard The final current allowed to flow through the core is equal to \begin_inset Formula $\phi$ \end_inset . This value in turn is used by the "lcouple" code model to obtain a value for the voltage reflected back across its terminals to the driving electrical circuit. \end_layout \begin_layout Standard The following example code shows the use of two \family typewriter lcouple \family default models and one core model to produce a simple primary/secondary transformer. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a1 (2 0) (3 0) primary \end_layout \begin_layout LyX-Code .model primary lcouple (num_turns = 155) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a2 (3 4) iron_core \end_layout \begin_layout LyX-Code .model iron_core core (H_array = [-1000 -500 -375 -250 -188 -125 -63 0 \end_layout \begin_layout LyX-Code + 63 125 188 250 375 500 1000] \end_layout \begin_layout LyX-Code + B_array = [-3.13e-3 -2.63e-3 -2.33e-3 -1.93e-3 \end_layout \begin_layout LyX-Code + -1.5e-3 -6.25e-4 -2.5e-4 0 2.5e-4 \end_layout \begin_layout LyX-Code + 6.25e-4 1.5e-3 1.93e-3 2.33e-3 \end_layout \begin_layout LyX-Code + 2.63e-3 3.13e-3] \end_layout \begin_layout LyX-Code + area = 0.01 length = 0.01) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a3 (5 0) (4 0) secondary \end_layout \begin_layout LyX-Code .model secondary lcouple (num_turns = 310) \end_layout \begin_layout Standard \align center HYSTERESIS Mode (mode = 2) \end_layout \begin_layout Standard The core model in HYSTERESIS mode takes as input a voltage that it treats as a magnetomotive force (mmf) value. This value is used as input to the equivalent of a hysteresis code model block. The parameters defining the input low and high values, the output low and high values, and the amount of hysteresis are as in that model. The output from this mode, as in PWL mode, is a current value that is seen across the mc port. An example of the core model used in this fashion is shown below: \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a1 (2 0) (3 0) primary \end_layout \begin_layout LyX-Code .model primary lcouple (num_turns = 155) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a2 (3 4) iron_core \end_layout \begin_layout LyX-Code .model iron_core core (mode = 2 in_low=-7.0 in_high=7.0 \end_layout \begin_layout LyX-Code + out_lower_limit=-2.5e-4 out_upper_limit=2.5e-4 \end_layout \begin_layout LyX-Code + hyst = 2.3 ) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a3 (5 0) (4 0) secondary \end_layout \begin_layout LyX-Code .model secondary lcouple (num_turns = 310) \end_layout \begin_layout Standard \emph on One final note to be made about the two core model nodes is that certain parameters are available in one mode, but not in the other \emph default . In particular, the in_low, in_high, out_lower_limit, out_upper_limit, and hysteresis parameters are not available in PWL mode. Likewise, the H_array, B_array, area, and length values are unavailable in HYSTERESIS mode. The input domain and fraction parameters are common to both modes (though their behavior is somewhat different; for explanation of the input domain and fraction values for the HYSTERESIS mode, you should refer to the hysteresis code model discussion). \end_layout \begin_layout Subsection Controlled Sine Wave Oscillator \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_sine \end_layout \begin_layout LyX-Code Spice_Model_Name: sine \end_layout \begin_layout LyX-Code Description: "controlled sine wave oscillator" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: cntl_in out \end_layout \begin_layout LyX-Code Description: "control input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_array freq_array \end_layout \begin_layout LyX-Code Description: "control array" "frequency array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: [0.0 1.0] [1.0e3 2.0e3] \end_layout \begin_layout LyX-Code Limits: - [0 -] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] [2 -] \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_low out_high \end_layout \begin_layout LyX-Code Description: "output peak low value" "output peak high value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: -1.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: This function is a controlled sine wave oscillator with parametrizable values of low and high peak output. It takes an input voltage or current value. This value is used as the independent variable in the piecewise linear curve described by the coordinate points of the cntl array and freq array pairs. From the curve, a frequency value is determined, and the oscillator will output a sine wave at that frequency. From the above, it is easy to see that array sizes of 2 for both the cntl array and the freq array will yield a linear variation of the frequency with respect to the control input. Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description of the piecewise linear controlled source, which uses a similar method to derive an output value given a control input. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code asine 1 2 in_sine \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code .model in_sine sine(cntl_array = [-1 0 5 6] \end_layout \begin_layout LyX-Code + freq_array=[10 10 1000 1000] out_low = -5.0 \end_layout \begin_layout LyX-Code + out_high = 5.0) \end_layout \begin_layout Subsection Controlled Triangle Wave Oscillator \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_triangle \end_layout \begin_layout LyX-Code Spice_Model_Name: triangle \end_layout \begin_layout LyX-Code Description: "controlled triangle wave oscillator" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: cntl_in out \end_layout \begin_layout LyX-Code Description: "control input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_array freq_array \end_layout \begin_layout LyX-Code Description: "control array" "frequency array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: [0.0 1.0] [1.0e3 2.0e3] \end_layout \begin_layout LyX-Code Limits: - [0 -] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] cntl_array \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_low out_high \end_layout \begin_layout LyX-Code Description: "output peak low value" "output peak high value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: -1.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: duty_cycle \end_layout \begin_layout LyX-Code Description: "rise time duty cycle" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.5 \end_layout \begin_layout LyX-Code Limits: [1e-10 0.999999999] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: This function is a controlled triangle/ramp wave oscillator with parametrizable values of low and high peak output and rise time duty cycle. It takes an input voltage or current value. This value is used as the independent variable in the piecewise linear curve described by the coordinate points of the cntl_array and freq_array pairs. \begin_inset Newline newline \end_inset From the curve, a frequency value is determined, and the oscillator will output a triangle wave at that frequency. From the above, it is easy to see that array sizes of 2 for both the cntl_array and the freq_array will yield a linear variation of the frequency with respect to the control input. Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description of the piecewise linear controlled source, which uses a similar method to derive an output value given a control input. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code ain 1 2 ramp1 \end_layout \begin_layout LyX-Code .model ramp1 triangle(cntl_array = [-1 0 5 6] \end_layout \begin_layout LyX-Code + freq_array=[10 10 1000 1000] out_low = -5.0 \end_layout \begin_layout LyX-Code + out_high = 5.0 duty_cycle = 0.9) \end_layout \begin_layout Subsection Controlled Square Wave Oscillator \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_square \end_layout \begin_layout LyX-Code Spice_Model_Name: square \end_layout \begin_layout LyX-Code Description: "controlled square wave oscillator" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: cntl_in out \end_layout \begin_layout LyX-Code Description: "control input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_array freq_array \end_layout \begin_layout LyX-Code Description: "control array" "frequency array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: [0.0 1.0] [1.0e3 2.0e3] \end_layout \begin_layout LyX-Code Limits: - [0 -] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] [2 -] \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_low out_high \end_layout \begin_layout LyX-Code Description: "output peak low value" "output peak high value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: -1.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER.TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: duty_cycle rise_time \end_layout \begin_layout LyX-Code Description: "duty cycle" "output rise time" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.5 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1e-6 0.999999] - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fall_time \end_layout \begin_layout LyX-Code Description: "output fall time" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: This function is a controlled square wave oscillator with parametrizable values of low and high peak output, duty cycle, rise time, and fall time. It takes an input voltage or current value. This value is used as the independent variable in the piecewise linear curve described by the coordinate points of the cntl_array and freq_array pairs. From the curve, a frequency value is determined, and the oscillator will output a square wave at that frequency. \begin_inset Newline newline \end_inset From the above, it is easy to see that array sizes of 2 for both the cntl_array and the freq_array will yield a linear variation of the frequency with respect to the control input. Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description of the piecewise linear controlled source, which uses a similar method to derive an output value given a control input. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code ain 1 2 pulse1 \end_layout \begin_layout LyX-Code .model pulse1 square(cntl_array = [-1 0 5 6] \end_layout \begin_layout LyX-Code + freq_array=[10 10 1000 1000] out_low = 0.0 \end_layout \begin_layout LyX-Code + out_high = 4.5 duty_cycle = 0.2 \end_layout \begin_layout LyX-Code + rise_time = 1e-6 fall_time = 2e-6) \end_layout \begin_layout Subsection Controlled One-Shot \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_oneshot \end_layout \begin_layout LyX-Code Spice_Model_Name: oneshot \end_layout \begin_layout LyX-Code Description: "controlled one-shot" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: clk cntl_in \end_layout \begin_layout LyX-Code Description: "clock input" "control input" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: clear out \end_layout \begin_layout LyX-Code Description: "clear signal" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_trig retrig \end_layout \begin_layout LyX-Code Description: "clock trigger value" "retrigger switch" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 0.5 FALSE \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: pos_edge_trig \end_layout \begin_layout LyX-Code Description: "positive/negative edge trigger switch" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: TRUE \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no q \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_array pw_array \end_layout \begin_layout LyX-Code Description: "control array" "pulse width array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: [0.0 1.0] [1.0e-6 0.9999999] \end_layout \begin_layout LyX-Code Limits: - [0.00 -] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: - cntl_array \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_low out_high \end_layout \begin_layout LyX-Code Description: "output low value" "output high value" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fall_time rise_time \end_layout \begin_layout LyX-Code Description: "output fall time" "output rise time" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay \end_layout \begin_layout LyX-Code Description: "output delay from trigger" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: fall_delay \end_layout \begin_layout LyX-Code Description: "output delay from pw" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: This function is a controlled oneshot with parametrizable values of low and high peak output, input trigger value level, delay, and output rise and fall times. It takes an input voltage or current value. This value is used as the independent variable in the piecewise linear curve described by the coordinate points of the cntl_array and pw_array pairs. From the curve, a pulse width value is determined. The one-shot will output a pulse of that width, triggered by the clock signal (rising or falling edge), delayed by the delay value, and with specified rise and fall times. A positive slope on the clear input will immediately terminate the pulse, which resets with its fall time. \begin_inset Newline newline \end_inset From the above, it is easy to see that array sizes of 2 for both the cntl_array and the pw_array will yield a linear variation of the pulse width with respect to the control input. Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description of the piecewise linear controlled source, which uses a similar method to derive an output value given a control input. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code ain 1 2 3 4 pulse2 \end_layout \begin_layout LyX-Code .model pulse2 oneshot(cntl_array = [-1 0 10 11] \end_layout \begin_layout LyX-Code + pw_array=[1e-6 1e-6 1e-4 1e-4] \end_layout \begin_layout LyX-Code + clk_trig = 0.9 pos_edge_trig = FALSE \end_layout \begin_layout LyX-Code + out_low = 0.0 out_high = 4.5 \end_layout \begin_layout LyX-Code + rise_delay = 20.0e-9 fall_delay = 35.0e-9) \end_layout \begin_layout Subsection Capacitance Meter \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_cmeter \end_layout \begin_layout LyX-Code Spice_Model_Name: cmeter \end_layout \begin_layout LyX-Code Description: "capacitance meter" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: gain \end_layout \begin_layout LyX-Code Description: "gain" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The capacitance meter is a sensing device that is attached to a circuit node and produces as an output a scaled value equal to the total capacitance seen on its input multiplied by the gain parameter. This model is primarily intended as a building block for other models that must sense a capacitance value and alter their behavior based upon it. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code atest1 1 2 ctest \end_layout \begin_layout LyX-Code .model ctest cmeter(gain=1.0e12) \end_layout \begin_layout Subsection Inductance Meter \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_lmeter \end_layout \begin_layout LyX-Code Spice_Model_Name: lmeter \end_layout \begin_layout LyX-Code Description: "inductance meter" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: gain \end_layout \begin_layout LyX-Code Description: "gain" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The inductance meter is a sensing device that is attached to a circuit node and produces as an output a scaled value equal to the total inductance seen on its input multiplied by the gain parameter. This model is primarily intended as a building block for other models that must sense an inductance value and alter their behavior based upon it. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code atest2 1 2 ltest \end_layout \begin_layout LyX-Code .model ltest lmeter(gain=1.0e6) \end_layout \begin_layout Subsection Memristor \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_memristor \end_layout \begin_layout LyX-Code Spice_Model_Name: memristor \end_layout \begin_layout LyX-Code Description: "Memristor Interface" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: memris \end_layout \begin_layout LyX-Code Description: "memristor terminals" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: gd \end_layout \begin_layout LyX-Code Allowed_Types: [gd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rmin rmax \end_layout \begin_layout LyX-Code Description: "minimum resistance" "maximum resistance" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 10.0 10000.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rinit vt \end_layout \begin_layout LyX-Code Description: "initial resistance" "threshold" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 7000.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: alpha beta \end_layout \begin_layout LyX-Code Description: "model parameter 1" "model parameter 2" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout Description Description: The memristor is a two-terminal resistor with memory, whose resistance depends on the time integral of the voltage across its terminals. rmin and rmax provide the lower and upper limits of the resistance, rinit is its starting value (no voltage applied so far). The voltage has to be above a threshold vt to become effective in changing the resistance. alpha and beta are two model parameters. The memristor code model is derived from a SPICE subcircuit published in \begin_inset CommandInset citation LatexCommand cite key "key-23" literal "true" \end_inset . \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code amen 1 2 memr \end_layout \begin_layout LyX-Code .model memr memristor (rmin=1k rmax=10k rinit=7k \end_layout \begin_layout LyX-Code + alpha=0 beta=2e13 vt=1.6) \end_layout \begin_layout Subsection 2D table model \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_table2D \end_layout \begin_layout LyX-Code Spice_Model_Name: table2D \end_layout \begin_layout LyX-Code Description: "2D table model" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: inx iny out \end_layout \begin_layout LyX-Code Description: "inputx" "inputy" "output" \end_layout \begin_layout LyX-Code Direction: in in out \end_layout \begin_layout LyX-Code Default_Type: v v i \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: no no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: order verbose \end_layout \begin_layout LyX-Code Description: "order" "verbose" \end_layout \begin_layout LyX-Code Data_Type: int int \end_layout \begin_layout LyX-Code Default_Value: 3 0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: offset gain \end_layout \begin_layout LyX-Code Description: "offset" "gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: file \end_layout \begin_layout LyX-Code Description: "file name" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: "2D-table-model.txt" \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout Description Description: The 2D table model reads a matrix from file " \family typewriter file name \family default " (default 2D-table-model.txt) which has x columns and y rows. Each x,y pair, addressed by inx and iny, yields an output value \family typewriter out \family default . Linear interpolation is used for \family typewriter out \family default , eno (essentially non oscillating) interpolation for its derivatives. Parameters \family typewriter offset \family default (default 0) and \family typewriter gain \family default (default 1) modify the output table values according to \begin_inset Formula $offset+gain\;out$ \end_inset . Parameter \family typewriter order \family default (default 3) influences the calculation of the derivatives. Parameter \family typewriter verbose \family default (default 0) yields test outputs, if set to 1 or 2. The table format is shown below. Be careful to include the data point inx = 0, iny = 0 into your table, because ngspice uses these during \family typewriter .OP \family default computations. The x horizontal and y vertical address values have to increase monotonically. \end_layout \begin_layout LyX-Code Table Example: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code * table source \end_layout \begin_layout LyX-Code * number of columns (x) \end_layout \begin_layout LyX-Code 8 \end_layout \begin_layout LyX-Code * number of rows (y) \end_layout \begin_layout LyX-Code 9 \end_layout \begin_layout LyX-Code * x horizontal (column) address values (real numbers) \end_layout \begin_layout LyX-Code -1 0 1 2 3 4 5 6 \end_layout \begin_layout LyX-Code * y vertical (row) address values (real numbers) \end_layout \begin_layout LyX-Code -0.6 0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 \end_layout \begin_layout LyX-Code * table with output data (horizontally addressed by x, vertically by y) \end_layout \begin_layout LyX-Code 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 \end_layout \begin_layout LyX-Code 1 1 1 1 1 1 1 1 \end_layout \begin_layout LyX-Code 1 1.2 1.4 1.6 1.8 2 2.2 2.4 \end_layout \begin_layout LyX-Code 1 1.5 2 2.5 3 3.5 4 4.5 \end_layout \begin_layout LyX-Code 1 2 3 4 5 6 7 8 \end_layout \begin_layout LyX-Code 1 2.5 4 5.5 7 8.5 10 11.5 \end_layout \begin_layout LyX-Code 1 3 5 7 9 11 13 15 \end_layout \begin_layout LyX-Code 1 3.5 6 8.5 11 13.5 16 18.5 \end_layout \begin_layout LyX-Code 1 4 7 10 13 16 19 22 \end_layout \begin_layout Description \family roman Description: The usage example consists of two input voltages referenced to ground and a current source output with two floating nodes. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code atab inx iny %id(out1 out2) tabmod \end_layout \begin_layout LyX-Code .model tabmod table2d (offset=0.0 gain=1 order=3 file="table-simple.txt") \end_layout \begin_layout Subsection 3D table model \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_table3D \end_layout \begin_layout LyX-Code Spice_Model_Name: table3D \end_layout \begin_layout LyX-Code Description: "3D table model" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: inx iny inz \end_layout \begin_layout LyX-Code Description: "inputx" "inputy" "inputz" \end_layout \begin_layout LyX-Code Direction: in in in \end_layout \begin_layout LyX-Code Default_Type: v v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [v,vd,i,id,vnam] [v,vd,i,id,vnam] \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: no no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: out \end_layout \begin_layout LyX-Code Description: "output" \end_layout \begin_layout LyX-Code Direction: out \end_layout \begin_layout LyX-Code Default_Type: i \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: order verbose \end_layout \begin_layout LyX-Code Description: "order" "verbose" \end_layout \begin_layout LyX-Code Data_Type: int int \end_layout \begin_layout LyX-Code Default_Value: 3 0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: offset gain \end_layout \begin_layout LyX-Code Description: "offset" "gain" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: file \end_layout \begin_layout LyX-Code Description: "file name" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: "3D-table-model.txt" \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout Description Description: The 3D table model reads a matrix from file \family typewriter "file name" \family default (default 3D-table-model.txt) which has x columns, y rows per table and z tables. Each x,y,z triple, addressed by inx, iny, and inz, yields an output value \family typewriter out \family default . Linear interpolation is used for \family typewriter out \family default , eno (essentially non oscillating) interpolation for its derivatives. Parameters \family typewriter offset \family default (default 0) and \family typewriter gain \family default (default 1) modify the output table values according to \begin_inset Formula $offset+gain\;out$ \end_inset . Parameter \family typewriter order \family default (default 3) influences the calculation of the derivatives. Parameter \family typewriter verbose \family default (default 0) yields test outputs, if set to 1 or 2. The table format is shown below. Be careful to include the data point inx = 0, iny = 0, inz = 0 into your table, because ngspice needs these to for the \family typewriter .OP \family default calculation. The x horizontal, y vertical, and z table address values have to increase monotonically. \end_layout \begin_layout LyX-Code Table Example: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code * 3D table for nmos bsim 4, W=10um, L=0.13um \end_layout \begin_layout LyX-Code *x \end_layout \begin_layout LyX-Code 39 \end_layout \begin_layout LyX-Code *y \end_layout \begin_layout LyX-Code 39 \end_layout \begin_layout LyX-Code *z \end_layout \begin_layout LyX-Code 11 \end_layout \begin_layout LyX-Code *x (drain voltage) \end_layout \begin_layout LyX-Code -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 ... \end_layout \begin_layout LyX-Code *y (gate voltage) \end_layout \begin_layout LyX-Code -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 ... \end_layout \begin_layout LyX-Code *z (substrate voltage) \end_layout \begin_layout LyX-Code -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 \end_layout \begin_layout LyX-Code *table -1.8 \end_layout \begin_layout LyX-Code -4.50688E-10 -4.50613E-10 -4.50601E-10 -4.50599E-10 ... \end_layout \begin_layout LyX-Code -4.49622E-10 -4.49267E-10 -4.4921E-10 -4.49202E-10 ... \end_layout \begin_layout LyX-Code -4.50672E-10 -4.49099E-10 -4.48838E-10 -4.48795E-10 ... \end_layout \begin_layout LyX-Code -4.55575E-10 -4.4953E-10 -4.48435E-10 -4.48217E-10 ... \end_layout \begin_layout LyX-Code ... \end_layout \begin_layout LyX-Code *table -1.6 \end_layout \begin_layout LyX-Code -3.10015E-10 -3.09767E-10 -3.0973E-10 -3.09724E-10 ... \end_layout \begin_layout LyX-Code -3.09748E-10 -3.08524E-10 -3.08339E-10 -3.08312E-10 ... \end_layout \begin_layout LyX-Code ... \end_layout \begin_layout LyX-Code *table -1.4 \end_layout \begin_layout LyX-Code -2.04848E-10 -2.04008E-10 -2.03882E-10 ... \end_layout \begin_layout LyX-Code -2.07275E-10 -2.03117E-10 -2.02491E-10 ... \end_layout \begin_layout LyX-Code ... \end_layout \begin_layout Description \noindent \align left \family roman Description: The usage example simulates a NMOS transistor with independent drain, gate and bulk nodes, referenced to source. Parameter \emph on gain \emph default may be used to emulate transistor width, with respect to the table transistor. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code amos1 %vd(d s) %vd(g s) %vd(b s) %id(d s) mostable1 \end_layout \begin_layout LyX-Code .model mostable1 table3d (offset=0.0 gain=0.5 order=3 \end_layout \begin_layout LyX-Code + verbose=1 file="table-3D-bsim4n.txt") \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Simple-Diode-Model" \end_inset Simple Diode Model \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_sidiode \end_layout \begin_layout LyX-Code Spice_Model_Name: sidiode \end_layout \begin_layout LyX-Code Description: "simple diode" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: ds \end_layout \begin_layout LyX-Code Description: "diode port" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: gd \end_layout \begin_layout LyX-Code Allowed_Types: [gd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: ron roff \end_layout \begin_layout LyX-Code Description: "resistance on-state" "resistance off-state" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1 1 \begin_inset Foot status open \begin_layout Plain Layout If roff is not given, ron is the default \end_layout \end_inset \end_layout \begin_layout LyX-Code Limits: [1e-6 - ] [1e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: vfwd vrev \end_layout \begin_layout LyX-Code Description: "forward voltage" "reverse breakdown voltage" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0. 1e30 \end_layout \begin_layout LyX-Code Limits: [0. -] [0. -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: ilimit revilimit \end_layout \begin_layout LyX-Code Description: "limit of on-current" "limit of breakdown current" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1e30 1e30 \end_layout \begin_layout LyX-Code Limits: [1e-15 -] [1e-15 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: epsilon revepsilon \end_layout \begin_layout LyX-Code Description: "width quadrat. reg. 1" "width quadratic region 2" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0. 0. \end_layout \begin_layout LyX-Code Limits: [0. -] [0. -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rrev \end_layout \begin_layout LyX-Code Description: "resistance in breakdown" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout Standard This is a model for a simple diode. Three regions are modelled as linear I(V) curves: Reverse (breakdown) current with \family sans Rrev \family default starting at \family sans Vrev \family default into the negative direction, Off current with \family sans Roff \family default between \family sans Vrev \family default and \family sans Vfwd \family default and an On region with \family sans Ron \family default , staring at \family sans Vfwd \family default . The interface between the regions is described by a quadratic function, the width of the interface region is determined by \family sans Revepsilon \family default and \family sans Epsilon \family default . Current limits in the reverse breakdown ( \family sans Revilimit \family default ) and in the forward (on) state ( \family sans Ilimit \family default ) may be set. The interface is a tanh function. Thus the first derivative of the I(V) curve is continuous. All parameter values are entered as positive numbers. A diode capacitance is not modelled. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a1 a k ds1 \end_layout \begin_layout LyX-Code .model ds1 sidiode(Roff=1000 Ron=0.7 Rrev=0.2 Vfwd=1 \end_layout \begin_layout LyX-Code + Vrev=10 Revepsilon=0.2 Epsilon=0.2 Ilimit=7 Revilimit=7) \end_layout \begin_layout Subsection Analog delay \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_delay \end_layout \begin_layout LyX-Code Spice_Model_Name: delay \end_layout \begin_layout LyX-Code Description: "analog delay line" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out cntrl \end_layout \begin_layout LyX-Code Description: "input" "output" "control" \end_layout \begin_layout LyX-Code Direction: in out in \end_layout \begin_layout LyX-Code Default_Type: v v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,vnam] [v,vd] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: no no yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: delay buffer_size \end_layout \begin_layout LyX-Code Description: "time delay" "size of delay buffer" \end_layout \begin_layout LyX-Code Data_Type: real int \end_layout \begin_layout LyX-Code Default_Value: 0.0 1024 \end_layout \begin_layout LyX-Code Limits: - [1 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: has_delay_cnt \end_layout \begin_layout LyX-Code Description: "controlled delay" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: FALSE \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: delmin delmax \end_layout \begin_layout LyX-Code Description: "min delay" "max delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0 0 \end_layout \begin_layout LyX-Code Limits: [0 -] [0 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description \noindent \align left \family roman Description: During a transient simulation the input voltage at node \family typewriter in \family roman and its associated time value are stored in a ring buffer. \family default \family typewriter buffer_size \family roman allows to set the size of the buffer, the default is 1024 time steps. \family default There are two modes to read out the buffer contents with a delay and obtain the delayed values at port \family typewriter out \family default , determined by \family typewriter has_delay_cnt \family default . If \family typewriter has_delay_cnt \family default is \family typewriter TRUE \family default , then you may vary the delay time between \family typewriter delmin \family default and \family typewriter delmax \family default by a control voltage between 0 and 1 at the input terminal \series bold cntrl \series default . Parameter \family typewriter delay \family default is ignored. If \family typewriter has_delay_cnt \family default has been set to \family typewriter FALSE \family default , then the signal is delayed by the time value given by \family typewriter delay \family default . \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code adelay1 in out cntrl mydel1 \end_layout \begin_layout LyX-Code .model mydel1 delay(delay=2m buffer_size=2048) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code adelay2 in out cntrl mydel2 \end_layout \begin_layout LyX-Code .model mydel2 delay( \family typewriter has_delay_cnt \family default =TRUE delmin=5u delmax=8u) \end_layout \begin_layout Standard Due to the fact that time steps are not constant during a transient simulation, but optimized by the simulator, the delayed values are sometimes slightly deviating from the original, depending on the number of steps. So in a sinusoidal wave we will see a distortion < 0.3% for 1000 steps per sin cycle. \end_layout \begin_layout Subsection Potentiometer \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: potentiometer \end_layout \begin_layout LyX-Code C_Function_Name: cm_potentiometer \end_layout \begin_layout LyX-Code Description: "potentiometer" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: r0 wiper \end_layout \begin_layout LyX-Code Description: "pot connection 0" "wiper contact" \end_layout \begin_layout LyX-Code Direction: inout inout \end_layout \begin_layout LyX-Code Default_Type: g g \end_layout \begin_layout LyX-Code Allowed_Types: [g] [g] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: r1 \end_layout \begin_layout LyX-Code Description: "pot connection 1" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: g \end_layout \begin_layout LyX-Code Allowed_Types: [g] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: position \end_layout \begin_layout LyX-Code Description: "position of wiper connection (0.0 to 1.0)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.5 \end_layout \begin_layout LyX-Code Limits: [0.0 1.0] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: log r \end_layout \begin_layout LyX-Code Description: "log-linear switch" "total resistance" \end_layout \begin_layout LyX-Code Data_Type: boolean real \end_layout \begin_layout LyX-Code Default_Value: FALSE 1.0e5 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: log_multiplier \end_layout \begin_layout LyX-Code Description: "multiplier constant for log resistance" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description \noindent \align left Description: A resistance potentiometer with three connections: \family typewriter r0 \family default , \family typewriter wiper \family default , and \family typewriter r1 \family default . Parameter \family typewriter position \family default determines the lower and upper portions of the resistance. \shape italic Rlower \shape default is located between \family typewriter r0 \family default and \family typewriter wiper \family default , \shape italic Rupper \shape default between \family typewriter wiper \family default and \family typewriter r1 \family default . If \family typewriter log \family default is set to FALSE, \begin_inset Formula $Rlower=position*r$ \end_inset . If log is set to TRUE, then \begin_inset Formula $Rlower=r*10^{-position*log\_multiplier}$ \end_inset . For \shape italic Rupper \shape default we always have \begin_inset Formula $Rupper=r-Rlower$ \end_inset . \begin_inset Formula $position<=0$ \end_inset is resolved to \begin_inset Formula $position=1e-9$ \end_inset , \begin_inset Formula $position>=1$ \end_inset is resolved to \begin_inset Formula $position=0.999999999$ \end_inset . \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Apot r0 w r1 potmod \end_layout \begin_layout LyX-Code .model potmod potentiometer(position=0.45 r=1k log=FALSE log_multiplier=1) \end_layout \begin_layout Standard \begin_inset Separator plain \end_inset \end_layout \begin_layout Subsection Delayed state of a node \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_astate \end_layout \begin_layout LyX-Code Spice_Model_Name: astate \end_layout \begin_layout LyX-Code Description: "analog state delayed" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v v \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,vnam,i,id] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: astate_no \end_layout \begin_layout LyX-Code Description: "previous state to be returned" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 1 \end_layout \begin_layout LyX-Code Limits: [0 3] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code Static_Var_Name: locdata \end_layout \begin_layout LyX-Code Description: "local static data" \end_layout \begin_layout LyX-Code Data_Type: pointer \end_layout \begin_layout Description Description: This code model stores the last three states of the node connected to the input and returns the state of the node delayed by 0 ... 3 time steps, determined by the model parameter \family sans astate_no \family default . \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code astate1 in out newstate \end_layout \begin_layout LyX-Code .model newstate astate(astate_no=2) \end_layout \begin_layout Subsection OTA with small signal noise enabled \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_ota \end_layout \begin_layout LyX-Code Spice_Model_Name: ota \end_layout \begin_layout LyX-Code Description: "Operational Transconductance Amplifier with noise" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: inp out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: inout inout \end_layout \begin_layout LyX-Code Default_Type: gd g \end_layout \begin_layout LyX-Code Allowed_Types: [gd] [g] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: gm rout \end_layout \begin_layout LyX-Code Description: "transconductance" "output resistance" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-3 1.0e12 \end_layout \begin_layout LyX-Code Limits: [1e-15 -] [0 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rin \end_layout \begin_layout LyX-Code Description: "input resistance" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e12 \end_layout \begin_layout LyX-Code Limits: [0 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: en in_noise \end_layout \begin_layout LyX-Code Description: "input voltage noise "input current noise \end_layout \begin_layout LyX-Code density V/rtHz" density A/rtHz" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 0.0 \end_layout \begin_layout LyX-Code Limits: [0 -] [0 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: enk ink \end_layout \begin_layout LyX-Code Description: "voltage noise "current noise \end_layout \begin_layout LyX-Code 1/f corner Hz" 1/f corner Hz" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 0.0 \end_layout \begin_layout LyX-Code Limits: [0 -] [0 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: incm incmk \end_layout \begin_layout LyX-Code Description: "CM current noise "CM current noise \end_layout \begin_layout LyX-Code density A/rtHz" 1/f corner Hz" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 0.0 \end_layout \begin_layout LyX-Code Limits: [0 -] [0 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: noise_programmatic \end_layout \begin_layout LyX-Code Description: "enable programmatic noise sources" \end_layout \begin_layout LyX-Code Data_Type: boolean \end_layout \begin_layout LyX-Code Default_Value: TRUE \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: This code model is a simple operational transconductance amplifier with differential input and single output. It is made to demonstrate the small signal noise capability of code models. This feature has to be designed into the C code of the model, which is described in chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Small-signal-noise" \end_inset . If the flag \family typewriter noise_programmatic \family default is not set or set to \family typewriter TRUE \family default , the noise feature is enabled in its programmatic fashion, where parameters are defined and their influence on the generated noise is given in the code model file cfunc.mod (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Small-signal-noise" \end_inset ). Besides the usual OTA parameters \family typewriter gm \family default , \family typewriter rout \family default , and \family typewriter rin \family default , there are several noise parameters provided: \family typewriter en \family default is the input voltage noise, given in V/√Hz, in_noise is the input current noise, given in A/√Hz, \family typewriter enk \family default is the corner frequency of the 1/f voltage noise, \family typewriter ink \family default the current noise corner frequency, \family typewriter incm \family default is the common mode input current noise density (A/√Hz), \family typewriter incmk \family default the common mode input current 1/f noise corner frequency. This OTA code model serves as a reference implementation that exercises the programmatic noise interface. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code aota inn 0 out newota \end_layout \begin_layout LyX-Code .model newota ota (gm=1m rout=1e12 rin=1Meg en=31n enk=100 \end_layout \begin_layout LyX-Code + in_noise=20p ink=2k incm=0 incmk=2k noise_programmatic=TRUE) \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Hybrid-Models" \end_inset Hybrid Models \end_layout \begin_layout Standard The following hybrid \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Code models ! hybrid models \end_layout \end_inset models are supplied with XSPICE. The descriptions included below consist of the model Interface Specification File and a description of the model's operation. This is followed by an example of a simulator-deck placement of the model, including the \family typewriter .MODEL \family default card and the specification of all available parameters. \end_layout \begin_layout Standard A note should be made with respect to the use of hybrid models for other than simple digital-to-analog and analog-to-digital translations. The hybrid models represented in this section address that specific need, but in the development of user-defined nodes you may find a need to translate not only between digital and analog nodes, but also between real and digital, real and int, etc. In most cases such translations will not need to be as involved or as detailed as shown in the following. \end_layout \begin_layout Subsection Digital-to-Analog Node Bridge \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_dac_bridge \end_layout \begin_layout LyX-Code Spice_Model_Name: dac_bridge \end_layout \begin_layout LyX-Code Description: "digital-to-analog node bridge" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d v \end_layout \begin_layout LyX-Code Allowed_Types: [d] [v,vd,i,id] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_low \end_layout \begin_layout LyX-Code Description: "0-valued analog output" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_high \end_layout \begin_layout LyX-Code Description: "1-valued analog output" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_undef input_load \end_layout \begin_layout LyX-Code Description: "U-valued analog output" "input load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.5 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: t_rise t_fall \end_layout \begin_layout LyX-Code Description: "rise time 0->1" "fall time 1->0" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The \family typewriter dac_bridge \family default is the first of three node bridge devices designed to allow for the ready transfer of digital information to analog values and back again. The second device is the \family typewriter adc_bridge \family default (which takes an analog value and maps it to a digital one). The \family typewriter dac_bridge \family default offers two functions: if there is a single output connection and multiple inputs, it behaves as a multi-bit DAC. Otherwise the number of input and output nodes must be equal and it acts as an array of single-bit converters, each taking as input a digital value. This value by definition may take on only one of the values ` \family typewriter \series medium 0 \family default \series default ', `1' or `U'. The \family typewriter dac_bridge \family default then outputs the value \family typewriter out_low \family default , \family typewriter out_high \family default or \family typewriter out_undef \family default , or ramps linearly toward one of these `final' values from its current analog output level. The speed at which this ramping occurs depends on the values of \family typewriter t_rise \family default and \family typewriter t_fall \family default . These parameters are interpreted by the model so that the rise or fall slope generated is constant. Note that the \emph on \family typewriter \emph default dac_bridge \family default \emph on \emph default includes test code in its cfunc.mod file for determining the presence of the \family typewriter out_undef \family default parameter. If this parameter is not specified, and if \emph on \family typewriter \emph default out_high \family default \emph on \emph default and \emph on \family typewriter \emph default out_low \family default \emph on \emph default values are specified, then \family typewriter out_undef \family default is assigned the value of the arithmetic mean of \family typewriter out_high \family default \emph on \emph default and \emph on \family typewriter \emph default out_low \family default \series bold . \series default This simplifies coding of output buffers, where typically a logic family will include an \family typewriter out_low \family default and \family typewriter out_high \family default voltage, but not an \family typewriter out_undef \family default value. This model also posts an input load value (in farads) based on the parameter input load. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code abridge1 [7] [2] dac1 \end_layout \begin_layout LyX-Code .model dac1 dac_bridge(out_low = 0.7 out_high = 3.5 out_undef = 2.2 \end_layout \begin_layout LyX-Code + input_load = 5.0e-12 t_rise = 50e-9 \end_layout \begin_layout LyX-Code + t_fall = 20e-9) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Analog-to-Digital-Node-Bridge" \end_inset Analog-to-Digital Node Bridge \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: adc_bridge \end_layout \begin_layout LyX-Code C_Function_Name: cm_adc_bridge \end_layout \begin_layout LyX-Code Description: "analog-to-digital converter node bridge" \end_layout \begin_layout LyX-Code /* Input and output are vector ports. If port numbers are equal the \end_layout \begin_layout LyX-Code * device acts as a set of individual comparators (use %vd or %id for \end_layout \begin_layout LyX-Code * differential inputs. With a single input and multiple outputs, \end_layout \begin_layout LyX-Code * it is a single ADC with multi-bit output. \end_layout \begin_layout LyX-Code */ \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v d \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id,vnam] [d] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code /* If in_low > in_high the adc_bridge has hysteresis - a Schmitt trigger. */ \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_low \end_layout \begin_layout LyX-Code Description: "maximum 0-valued analog input" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.1 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_high \end_layout \begin_layout LyX-Code Description: "minimum 1-valued analog input" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.9 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1e-12 -] [1e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The \family typewriter adc_bridge \family default also offers two functions. With a single input and multiple outputs, it behaves as a conventional multi-bit ADC. Otherwise the number of input and output nodes must be equal and it operates as an array of independent comparators with digital outputs. Each input is taken from an analog node and may be a voltage or current, optionally differential. If the input value is less than or equal to in_low, then a digital output value of ` \family typewriter \series medium 0 \family default \series default ' is generated. If the input is greater than or equal to in_high, a digital output value of `1' is generated. If neither of these is true, then a digital `UNKNOWN' value is output. However, if in_low is set higher than in_high then it behaves as a Schmitt trigger, and the only outputs are 0 and 1. Note that, unlike the case of the \family typewriter dac_bridge \family default , no ramping time or delay is associated with the \family typewriter adc_bridge \family default . The continuous ramping of the input value provides for any associated delays in the digitized signal. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code abridge2 [1] [8] adc_buff \end_layout \begin_layout LyX-Code .model adc_buff adc_bridge(in_low = 0.3 in_high = 3.5) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Bidirectional-Analog/Digital-Node-Bridge" \end_inset Bidirectional Analog/Digital Node Bridge \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_bidi_bridge \end_layout \begin_layout LyX-Code Spice_Model_Name: bidi_bridge \end_layout \begin_layout LyX-Code Description: "bidirectional digital/analog node bridge" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: a d \end_layout \begin_layout LyX-Code Description: "analog" "digital in/out" \end_layout \begin_layout LyX-Code Direction: inout inout \end_layout \begin_layout LyX-Code Default_Type: g d \end_layout \begin_layout LyX-Code Allowed_Types: [g, gd] [d] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code /* The direction of the bridge ports may be controlled by digital inputs. \end_layout \begin_layout LyX-Code * with LOW selecting DAC behavior and HIGH selecting ADC. \end_layout \begin_layout LyX-Code * If null, or the value is UNKNOWN the bridge will be truly bi-directional. \end_layout \begin_layout LyX-Code */ \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: dir \end_layout \begin_layout LyX-Code Description: "direction" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code /* Alternatively, this parameter sets direction: 0-2 for DAC, ADC, ignore. \end_layout \begin_layout LyX-Code * Values 0/1 override the direction port. \end_layout \begin_layout LyX-Code */ \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: direction input_load \end_layout \begin_layout LyX-Code Description: "force direction" "capacitive input load (F)" \end_layout \begin_layout LyX-Code Data_Type: int real \end_layout \begin_layout LyX-Code Default_Value: 2 1.0e-12 \end_layout \begin_layout LyX-Code Limits: [0 2] - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code /* Digital 0utput strength is 0 (strong, default) or 1 (resistive). \end_layout \begin_layout LyX-Code * Smooth controls use of smoothing functions, default is 0 (no smoothing). \end_layout \begin_layout LyX-Code */ \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: strength smooth \end_layout \begin_layout LyX-Code Description: "output strength" "smoothing level" \end_layout \begin_layout LyX-Code Data_Type: int int \end_layout \begin_layout LyX-Code Default_Value: 0 0 \end_layout \begin_layout LyX-Code Limits: [0 2] [0 2] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code /* Analog thresholds, in_low may be greater than in-high, enabling hysteresis. \end_layout \begin_layout LyX-Code */ \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_low \end_layout \begin_layout LyX-Code Description: "maximum 0-valued analog input" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.1 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_high \end_layout \begin_layout LyX-Code Description: "minimum 1-valued analog input" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.9 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code /* Analog maximum and minimum output voltages. */ \end_layout \begin_layout LyX-Code Parameter_Name: out_low \end_layout \begin_layout LyX-Code Description: "minimum analog output voltage for 'ZERO' digital input" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: out_high \end_layout \begin_layout LyX-Code Description: "maximum analog output voltage for 'ONE' digital input" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 3.3 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code /* Analog maximum current. */ \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: drive_low drive_high \end_layout \begin_layout LyX-Code Description: "max current to ground" "max current from supply" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.02 0.02 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code /* Strong analog output cuts off smoothly at the voltage limits. \end_layout \begin_layout LyX-Code * Let vth = out_high - r_sth * drive_high. \end_layout \begin_layout LyX-Code * Then for input voltage v, with drive_high > v > vth, \end_layout \begin_layout LyX-Code * the maximum output current is (drive_high - v) / r_sth \end_layout \begin_layout LyX-Code */ \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: r_stl r_sth \end_layout \begin_layout LyX-Code Description: "low taper resistance" "high taper resistance" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 20 20 \end_layout \begin_layout LyX-Code Limits: [1e-6 -] [1e-6 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code /* Resistive analog drive. */ \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: r_low r_high \end_layout \begin_layout LyX-Code Description: "drive resistor to ground" "drive resistor to out_high" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 10000 10000 \end_layout \begin_layout LyX-Code Limits: [1e-6 -] [1e-6 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code /* Analog rise and fall times. */ \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: t_rise t_fall \end_layout \begin_layout LyX-Code Description: "rise time 0 -> 1" "fall time 1 -> 0" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1e-12 -] [1e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code /* Digital rise and fall delays. */ \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay 0 -> 1" "fall delay 1 -> 0" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1e-12 -] [1e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The \family typewriter bidi_bridge \family default is the third and most complex of three analog/digital node bridges. It is capable of effectively simultaneous output to both analog and digital ports, depending on the state of the other side. That requires the use of an analog transconductance port, which may cause convergence problems when there is high impedance on a connected analog node. Non-zero values for the \family typewriter smooth \family default parameter may be helpful if such problems occur. For digital nodes that are always strongly driven but also have digital inputs, the simpler \family typewriter dac_bridge \family default may be preferred. Otherwise, \family typewriter bidi_bridge \family default has some additional features that may make it preferable to the other bridges. The analog output characteristics change with the digital drive strength, with strong output behaving similarly to a very crude model of a CMOS output driver. The low input threshold may be higher than the high threshold, producing Schmitt Trigger behavior. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code abridge2 [1 2 3] [8 9 10] null bidi_buff \end_layout \begin_layout LyX-Code .model bidi_buff bidi_bridge(in_low = 2 in_high = 1.5) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Controlled-Digital-Oscillator" \end_inset Controlled Digital Oscillator \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_osc \end_layout \begin_layout LyX-Code Spice_Model_Name: d_osc \end_layout \begin_layout LyX-Code Description: "controlled digital oscillator" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: cntl_in out \end_layout \begin_layout LyX-Code Description: "control input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v d \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_array freq_array \end_layout \begin_layout LyX-Code Description: "control array" "frequency array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: [0.0 1.0] [1.0e6 2.0e6] \end_layout \begin_layout LyX-Code Limits: - [0 -] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] cntl_array \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: duty_cycle init_phase \end_layout \begin_layout LyX-Code Description: "duty cycle" "initial phase of output" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 0.5 0 \end_layout \begin_layout LyX-Code Limits: [1e-6 0.999999] [-180.0 +360.0] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1e-9 1e-9 \end_layout \begin_layout LyX-Code Limits: [0 -] [0 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Description Description: The digital oscillator is a hybrid model that accepts as input a voltage or current. This input is compared to the voltage-to-frequency transfer characteristic specified by the \family typewriter cntl_array/freq_array \family default coordinate pairs, and a frequency is obtained that represents a linear interpolation or extrapolation based on those pairs. A digital time-varying signal is then produced with this fundamental frequency. \begin_inset Newline newline \end_inset The output waveform, which is the equivalent of a digital clock signal, has rise and fall delays that can be specified independently. In addition, the duty cycle and the phase of the waveform are also variable and can be set by you. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a5 1 8 var_clock \end_layout \begin_layout LyX-Code .model var_clock d_osc(cntl_array = [-2 -1 1 2] \end_layout \begin_layout LyX-Code + freq_array = [1e3 1e3 10e3 10e3] \end_layout \begin_layout LyX-Code + duty_cycle = 0.4 init_phase = 180.0 \end_layout \begin_layout LyX-Code + rise_delay = 10e-9 fall_delay=8e-9) \end_layout \begin_layout Subsection Node bridge from digital to real with enable \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: d_to_real \end_layout \begin_layout LyX-Code C_Function_Name: ucm_d_to_real \end_layout \begin_layout LyX-Code Description: "Node bridge from digital to real with enable" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in enable out \end_layout \begin_layout LyX-Code Description: "input" "enable" "output" \end_layout \begin_layout LyX-Code Direction: in in out \end_layout \begin_layout LyX-Code Default_Type: d d real \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] [real] \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: no yes no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: zero one delay \end_layout \begin_layout LyX-Code Description: "value for 0" "value for 1" "delay" \end_layout \begin_layout LyX-Code Data_Type: real real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 1e-9 \end_layout \begin_layout LyX-Code Limits: - - [1e-15 -] \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes yes \end_layout \begin_layout Subsection A Z**-1 block working on real data \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: real_delay \end_layout \begin_layout LyX-Code C_Function_Name: ucm_real_delay \end_layout \begin_layout LyX-Code Description: "A Z ** -1 block working on real data" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in clk out \end_layout \begin_layout LyX-Code Description: "input" "clock" "output" \end_layout \begin_layout LyX-Code Direction: in in out \end_layout \begin_layout LyX-Code Default_Type: real d real \end_layout \begin_layout LyX-Code Allowed_Types: [real] [d] [real] \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: no no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: delay \end_layout \begin_layout LyX-Code Description: "delay from clk to out" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1e-9 \end_layout \begin_layout LyX-Code Limits: [1e-15 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Subsection A gain block for event-driven real data \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: real_gain \end_layout \begin_layout LyX-Code C_Function_Name: ucm_real_gain \end_layout \begin_layout LyX-Code Description: "A gain block for event-driven real data" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: real real \end_layout \begin_layout LyX-Code Allowed_Types: [real] [real] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: in_offset gain out_offset \end_layout \begin_layout LyX-Code Description: "input offset" "gain" "output offset" \end_layout \begin_layout LyX-Code Data_Type: real real real \end_layout \begin_layout LyX-Code Default_Value: 0.0 1.0 0.0 \end_layout \begin_layout LyX-Code Limits: - - - \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: delay ic \end_layout \begin_layout LyX-Code Description: "delay" "initial condition" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Subsection Node bridge from real to analog voltage \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: real_to_v \end_layout \begin_layout LyX-Code C_Function_Name: ucm_real_to_v \end_layout \begin_layout LyX-Code Description: "Node bridge from real to analog voltage" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: real v \end_layout \begin_layout LyX-Code Allowed_Types: [real] [v, vd, i, id] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: gain transition_time \end_layout \begin_layout LyX-Code Description: "gain" "output transition time" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0 1e-9 \end_layout \begin_layout LyX-Code Limits: - [1e-15 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Subsection Controlled PWM Oscillator \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: d_pwm \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_pwm \end_layout \begin_layout LyX-Code Description: "duty cycle controlled digital oscillator" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: cntl_in out \end_layout \begin_layout LyX-Code Description: "control input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: v d \end_layout \begin_layout LyX-Code Allowed_Types: [v,vd,i,id] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: cntl_array dc_array \end_layout \begin_layout LyX-Code Description: "control array" "duty cycle array" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: [-1 1] [0 1] \end_layout \begin_layout LyX-Code Limits: - [0 1] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] [2 -] \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: frequency init_phase \end_layout \begin_layout LyX-Code Description: "oscillator frequency" "initial phase of output" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1e6 0 \end_layout \begin_layout LyX-Code Limits: [1e-6 -] [-180.0 +360.0] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1e-9 1e-9 \end_layout \begin_layout LyX-Code Limits: [0 -] [0 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout Description Description: The digital pulse-width modulated oscillator is a hybrid model that accepts as control input a voltage or current. This input is compared to the voltage-to-duty cycle transfer characteristic specified by the \family typewriter cntl_array/dc_array \family default coordinate pairs, and a duty cycle is obtained that represents a linear interpolation or extrapolation based on those pairs. A digital duty cycle-varying signal is then produced. The duty cycle is limited between 0 and 1 (excluding the limits). \begin_inset Newline newline \end_inset The digital output waveform has rise and fall delays that can be specified independently. In addition, the oscillator frequency and the phase of the waveform are variable and user selectable. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a5 cin dout pwm_osc \end_layout \begin_layout LyX-Code .model pwm_osc d_pwm(cntl_array = [-2 -1.99 1.99 2] \end_layout \begin_layout LyX-Code + dc_array = [0.01 0.01 0.99 0.99] \end_layout \begin_layout LyX-Code + frequency = 1.2Meg init_phase = 90.0 \end_layout \begin_layout LyX-Code + rise_delay = 10e-9 fall_delay=8e-9) \end_layout \begin_layout Standard Currently there are some limits or bugs: a duty cycle < 1% or larger than 99% may generate false output (e.g. a 50% duty cycle signal). Sometimes spurious missing pulses occur. To obtain false results by extrapolation during evaluation of the cntl_array, it is recommended to force a flat output if input signals are above or below the outer limits of the cntl_array data (see the example shown above). \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:XSPICE-Digital-Models" \end_inset Digital Models \end_layout \begin_layout Standard The \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Code models ! digital models \end_layout \end_inset following digital models are supplied with XSPICE. The descriptions included below consist of a (sometimes abbreviated) model Interface Specification File and a description of the model's operation. This is followed by an example of a simulator-deck placement of the model, including the \family typewriter .MODEL \family default card and the specification of all available parameters. Note that these models have not been finalized at this time. \end_layout \begin_layout Standard Some information common to all digital models and/or digital nodes is included here. The following are general rules that should make working with digital nodes and models more straightforward: \end_layout \begin_layout Enumerate All digital nodes are initialized to ZERO at the start of a simulation (i.e., when INIT=TRUE). This means that a model need not post an explicit value to an output node upon initialization if its output would normally be a ZERO (although posting such would certainly cause no harm). \end_layout \begin_layout Enumerate Digital nodes may have one out of twelve possible node values. See \begin_inset CommandInset ref LatexCommand ref reference "subsec:Digital-Node-Type" nolink "false" \end_inset for details. \end_layout \begin_layout Enumerate Digital models typically have defined their rise and fall delays for their output signals. A capacitive input load value may be defined as well to determine a load-dependent delay, but is currently not used in any code model (see \begin_inset CommandInset ref LatexCommand ref reference "TOTAL_LOAD" nolink "false" \end_inset ). \end_layout \begin_layout Enumerate Several commands are available for outputting data, e.g. eprint, edisplay, and eprvcd. Digital inputs may be read from files. Please see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:(Digital)-Input/Output" nolink "false" \end_inset for more details. \end_layout \begin_layout Enumerate Hybrid models (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Hybrid-Models" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) provide an interface between the digital event driven world and the analog world of ngspice to enable true mixed mode simulation. \end_layout \begin_layout Standard There are some common parameters that are used by many of the digital models. To avoid repetition they are omitted from the individual Interface Description Files listed here and their availabilty is noted at the end of the file for each model. The common parameters are: \end_layout \begin_layout Description \family typewriter \begin_inset CommandInset label LatexCommand label name "inertial_delay" \end_inset inertial_delay \family default When this boolean parameter is set, output pulses that are shorter than the current delay time for the port are suppressed, and the output remains unchanged until the next state transition that completes its delay period. The default value is "false", giving transport delay behavior: all changes reach the output. An interpreter variable, \family typewriter digital_delay_type \family default , can be used to override the default. A value of 1 changes the default to "true"; 2 forces all relevant XSPICE elements to use transport delay; 3 forces inertial delay. \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset This parameter is used by PSpice-compatible U-devices ( \begin_inset CommandInset ref LatexCommand ref reference "chap:Digital-Device-Models" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ). In ngspice-40 these XSPICE digital devices: \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset d_and, d_buffer, d_inverter, d_nand, d_nor, d_or, d_tristate, d_xnor, d_xor \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset have the inertial_delay parameter. When the circuits in the examples/digital/digital_devices directory are run, subcircuits with PSpice U* device instances are translated to XSPICE primitives. Also, .model statements are generated containing inertial_delay=true. This causes the circuits to run with inertial delays (suppress glitches) rather than transport delays (propagate glitches). Most digital simulators model gates using inertial delays. \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset If you run the examples in ngspice-39 and ngspice-40 then compare waveforms produced by circuits behav-tristate-pulse.cir and behav-283.cir, you will see how glitches are suppressed by the inertial delay mechanism. To obtain transport delay behavior with ngspice-40, add the following line: \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset set digital_delay_type=2 \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset to the .spiceinit file in that directory. \end_layout \begin_layout Description \family typewriter family \family default This is a string-valued parameter that has no effect on the model itself, but labels the ports of instances of the model to guide the automatic bridging mechanism. See \begin_inset CommandInset ref LatexCommand ref reference "sec:Automatic insertion of bridging devices" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . \end_layout \begin_layout Description \family typewriter rise_delay \family default The delay time between a change in a model's internal state, as driven by its inputs, and a change in output to digital one. This is used when there is only one output, or they all have the same delays. \end_layout \begin_layout Description \family typewriter fall_delay \family default Like rise_delay, but for transitions to zero. \end_layout \begin_layout Description \family typewriter input_load \family default The capacitance of one or all digital inputs, in Farads. Code models may use the TOTAL_LOAD macro to find the capacitative load on their outputs. However, the outputs of models listed here do \emph on not \emph default respond to their loading. These models always drive outputs strongly with the specified delays. \end_layout \begin_layout Standard These common parameters appear in individual Interface Specification Files in these forms: \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rise_delay fall_delay \end_layout \begin_layout LyX-Code Description: "rise delay" "fall delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load \end_layout \begin_layout LyX-Code Description: "input load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: inertial_delay family \end_layout \begin_layout LyX-Code Description: "swallow short pulses" "Logic family for bridging" \end_layout \begin_layout LyX-Code Data_Type: boolean string \end_layout \begin_layout LyX-Code Default_Value: false - \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Subsection Buffer \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_buffer \end_layout \begin_layout LyX-Code Spice_Model_Name: d_buffer \end_layout \begin_layout LyX-Code Description: "digital one-bit-wide buffer" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout Standard Common parameters: inertial_delay, family, rise_delay, fall_delay, input_load. \end_layout \begin_layout Description Description: The buffer is a single-input, single-output digital buffer that produces as output a time-delayed copy of its input. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a6 1 8 buff1 \end_layout \begin_layout LyX-Code .model buff1 d_buffer(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Inverter \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_inverter \end_layout \begin_layout LyX-Code Spice_Model_Name: d_inverter \end_layout \begin_layout LyX-Code Description: "digital one-bit-wide inverter" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout Standard Common parameters: inertial_delay, family, rise_delay, fall_delay, input_load. \end_layout \begin_layout Description Description: The inverter is a single-input, single-output digital inverter that produces as output an inverted, time-delayed copy of its input. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a6 1 8 inv1 \end_layout \begin_layout LyX-Code .model inv1 d_inverter(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection And \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_and \end_layout \begin_layout LyX-Code Spice_Model_Name: d_and \end_layout \begin_layout LyX-Code Description: "digital `and' gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout Standard Common parameters: inertial_delay, family, rise_delay, fall_delay, input_load. \end_layout \begin_layout Description Description: The digital \family typewriter and \family default gate is an n-input, single-output \family typewriter and \family default gate that produces an active ` \family typewriter 1 \family default ' value if, and only if, all of its inputs are also ` \family typewriter 1 \family default ' values. If ANY of the inputs is a ` \family typewriter \series medium 0 \family default \series default ', the output will also be a ` \family typewriter 0 \family default '; if neither of these conditions holds, the output will be unknown. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a6 [1 2] 8 and1 \end_layout \begin_layout LyX-Code .model and1 d_and(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Nand \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_nand \end_layout \begin_layout LyX-Code Spice_Model_Name: d_nand \end_layout \begin_layout LyX-Code Description: "digital `nand' gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout Standard Common parameters: inertial_delay, family, rise_delay, fall_delay, input_load. \end_layout \begin_layout Description Description: The digital \family typewriter nand \family default gate is an n-input, single-output \family typewriter nand \family default gate that produces an active ` \family typewriter \series medium 0 \family default \series default ' value if and only if all of its inputs are ` \family typewriter \series medium 1 \family default \series default ' values. If ANY of the inputs is a ` \family typewriter \series medium 0 \family default \series default ', the output will be a ` \family typewriter \series medium 1 \family default \series default '; if neither of these conditions holds, the output will be unknown. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a6 [1 2 3] 8 nand1 \end_layout \begin_layout LyX-Code .model nand1 d_nand(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Or \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_or \end_layout \begin_layout LyX-Code Spice_Model_Name: d_or \end_layout \begin_layout LyX-Code Description: "digital `or' gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout Standard Common parameters: inertial_delay, family, rise_delay, fall_delay, input_load. \end_layout \begin_layout Description Description: The digital \family typewriter or \family default gate is an n-input, single-output \family typewriter or \family default gate that produces an active ` \family typewriter \series medium 1 \family default \series default ' value if at least one of its inputs is a ` \family typewriter \series medium 1 \family default \series default ' value. The gate produces a ` \family typewriter \series medium 0 \family default \series default ' value if all inputs are ` \family typewriter \series medium 0 \family default \series default '; if neither of these two conditions holds, the output is unknown. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a6 [1 2 3] 8 or1 \end_layout \begin_layout LyX-Code .model or1 d_or(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Nor \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_nor \end_layout \begin_layout LyX-Code Spice_Model_Name: d_nor \end_layout \begin_layout LyX-Code Description: "digital `nor' gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout Standard Common parameters: inertial_delay, family, rise_delay, fall_delay, input_load. \end_layout \begin_layout Description Description: The digital \family typewriter nor \family default gate is an n-input, single-output \family typewriter nor \family default gate that produces an active ` \family typewriter \series medium 0 \family default \series default ' value if at least one of its inputs is a ` \family typewriter \series medium 1 \family default \series default ' value. The gate produces a ` \family typewriter \series medium 0 \family default \series default ' value if all inputs are ` \family typewriter \series medium 0 \family default \series default '; if neither of these two conditions holds, the output is unknown. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code anor12 [1 2 3 4] 8 nor12 \end_layout \begin_layout LyX-Code .model nor12 d_nor(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Xor \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_xor \end_layout \begin_layout LyX-Code Spice_Model_Name: d_xor \end_layout \begin_layout LyX-Code Description: "digital exclusive-or gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout Standard Common parameters: inertial_delay, family, rise_delay, fall_delay, input_load. \end_layout \begin_layout Description Description: The digital \family typewriter xor \family default gate is an n-input, single-output \family typewriter xor \family default gate that produces an active ` \family typewriter \series medium 1 \family default \series default ' value if an odd number of its inputs are also ` \family typewriter \series medium 1 \family default \series default ' values. The delays associated with an output rise and those associated with an output fall may be specified independently. Note also that to maintain the technology-independence of the model, any UNKNOWN input, or any floating input causes the output to also go UNKNOWN. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a9 [1 2] 8 xor3 \end_layout \begin_layout LyX-Code .model xor3 d_xor(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Xnor \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_xnor \end_layout \begin_layout LyX-Code Spice_Model_Name: d_xnor \end_layout \begin_layout LyX-Code Description: "digital exclusive-nor gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [2 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout Standard Common parameters: inertial_delay, family, rise_delay, fall_delay, input_load. \end_layout \begin_layout Description Description: The digital \family typewriter xnor \family default gate is an n-input, single-output \family typewriter xnor \family default gate that produces an active ` \family typewriter \series medium 0 \family default \series default ' value if an odd number of its inputs are also ` \family typewriter \series medium 1 \family default \series default ' values. It produces a ` \family typewriter \series medium 1 \family default \series default ' output when an even number of ` \family typewriter \series medium 1 \family default \series default ' values occurs on its inputs. Note also that to maintain the technology-independence of the model, any UNKNOWN input, or any floating input causes the output to also go UNKNOWN. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a9 [1 2] 8 xnor3 \end_layout \begin_layout LyX-Code .model xnor3 d_xnor(rise_delay = 0.5e-9 fall_delay = 0.3e-9 \end_layout \begin_layout LyX-Code + input_load = 0.5e-12) \end_layout \begin_layout Subsection Tristate \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_tristate \end_layout \begin_layout LyX-Code Spice_Model_Name: d_tristate \end_layout \begin_layout LyX-Code Description: "digital tristate buffer" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in enable out \end_layout \begin_layout LyX-Code Description: "input" "enable" "output" \end_layout \begin_layout LyX-Code Direction: in in out \end_layout \begin_layout LyX-Code Default_Type: d d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] [d] \end_layout \begin_layout LyX-Code Vector: no no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - - \end_layout \begin_layout LyX-Code Null_Allowed: no no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: delay \end_layout \begin_layout LyX-Code Description: "delay" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: enable_load \end_layout \begin_layout LyX-Code Description: "enable load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Standard Common parameters: inertial_delay, family, input_load. \end_layout \begin_layout Description Description: The digital tristate is a simple tristate gate that can be configured to allow for open-collector behavior, as well as standard tristate behavior. The state seen on the input line is reflected in the output. The state seen on the enable line determines the strength of the output. Thus, a ONE forces the output to its state with a STRONG strength. A ZERO forces the output to go to a HI_IMPEDANCE strength. The delays associated with an output state or strength change cannot be specified independently, nor may they be specified independently for rise or fall conditions; other gate models may be used to provide such delays if needed. The model posts input and enable load values (in farads) based on the parameters input load and enable. Note also that to maintain the technology-independence of the model, any UNKNOWN input, or any floating input causes the output to also go UNKNOWN. Likewise, any UNKNOWN input on the enable line causes the output to go to an UNDETERMINED strength value. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a9 1 2 8 tri7 \end_layout \begin_layout LyX-Code .model tri7 d_tristate(delay = 0.5e-9 input_load = 0.5e-12 \end_layout \begin_layout LyX-Code + enable_load = 0.5e-12) \end_layout \begin_layout Subsection Pullup \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_pullup \end_layout \begin_layout LyX-Code Spice_Model_Name: d_pullup \end_layout \begin_layout LyX-Code Description: "digital pullup resistor" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out \end_layout \begin_layout LyX-Code Description: "output" \end_layout \begin_layout LyX-Code Direction: out \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: load \end_layout \begin_layout LyX-Code Description: "load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital pullup resistor is a device that emulates the behavior of an analog resistance value tied to a high voltage level. The pullup may be used in conjunction with tristate buffers to provide open-collector wired \family typewriter or \family default constructs, or any other logical constructs that rely on a resistive pullup common to many tristated output devices. The model posts an input load value (in farads) based on the parameter \family sans load \family default . \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a2 9 pullup1 \end_layout \begin_layout LyX-Code .model pullup1 d_pullup(load = 20.0e-12) \end_layout \begin_layout Subsection Pulldown \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_pulldown \end_layout \begin_layout LyX-Code Spice_Model_Name: d_pulldown \end_layout \begin_layout LyX-Code Description: "digital pulldown resistor" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out \end_layout \begin_layout LyX-Code Description: "output" \end_layout \begin_layout LyX-Code Direction: out \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: load \end_layout \begin_layout LyX-Code Description: "load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital pulldown resistor is a device that emulates the behavior of an analog resistance value tied to a low voltage level. The pulldown may be used in conjunction with tristate buffers to provide open-collector wired \family typewriter or \family default constructs, or any other logical constructs that rely on a resistive pulldown common to many tristated output devices. The model posts an input load value (in farads) based on the parameter \family typewriter load \family default . \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 9 pulldown1 \end_layout \begin_layout LyX-Code .model pulldown1 d_pulldown(load = 20.0e-12) \end_layout \begin_layout Subsection D Flip Flop \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_dff \end_layout \begin_layout LyX-Code Spice_Model_Name: d_dff \end_layout \begin_layout LyX-Code Description: "digital d-type flip flop" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: data clk \end_layout \begin_layout LyX-Code Description: "input data" "clock" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: set reset \end_layout \begin_layout LyX-Code Description: "asynch. set" "asynch. reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out Nout \end_layout \begin_layout LyX-Code Description: "data output" "inverted data output" \end_layout \begin_layout LyX-Code Direction: out out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_delay set_delay \end_layout \begin_layout LyX-Code Description: "delay from clk" "delay from set" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_delay ic \end_layout \begin_layout LyX-Code Description: "delay from reset" "output initial state" \end_layout \begin_layout LyX-Code Data_Type: real int \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 0 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [0 2] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: data_load clk_load \end_layout \begin_layout LyX-Code Description: "data load value (F)" "clk load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: set_load reset_load \end_layout \begin_layout LyX-Code Description: "set load value (F)" "reset load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector.Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Standard Common parameters: rise_delay, fall_delay. \end_layout \begin_layout Description Description: The digital d-type flip flop is a one-bit, edge-triggered storage element that will store data whenever the clk input line transitions from low to high (ZERO to ONE). In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_dff have separate load values and delays associated with them. Additionally, you may specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies. \begin_inset Newline newline \end_inset Note that any UNKNOWN input on the set or reset lines immediately results in an UNKNOWN output. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a7 1 2 3 4 5 6 flop1 \end_layout \begin_layout LyX-Code .model flop1 d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9 \end_layout \begin_layout LyX-Code + reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9 \end_layout \begin_layout LyX-Code + fall_delay = 3e-9) \end_layout \begin_layout Subsection JK Flip Flop \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_jkff \end_layout \begin_layout LyX-Code Spice_Model_Name: d_jkff \end_layout \begin_layout LyX-Code Description: "digital jk-type flip flop" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: j k \end_layout \begin_layout LyX-Code Description: "j input" "k input" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: clk \end_layout \begin_layout LyX-Code Description: "clock" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: set reset \end_layout \begin_layout LyX-Code Description: "asynchronous set" "asynchronous reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out Nout \end_layout \begin_layout LyX-Code Description: "data output" "inverted data output" \end_layout \begin_layout LyX-Code Direction: out out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_delay set_delay \end_layout \begin_layout LyX-Code Description: "delay from clk" "delay from set" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_delay ic \end_layout \begin_layout LyX-Code Description: "delay from reset" "output initial state" \end_layout \begin_layout LyX-Code Data_Type: real int \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 0 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [0 2] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: jk_load clk_load \end_layout \begin_layout LyX-Code Description: "j,k load values (F)" "clk load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: set_load reset_load \end_layout \begin_layout LyX-Code Description: "set load value (F)" "reset load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Standard Common parameters: rise_delay, fall_delay. \end_layout \begin_layout Description Description: The digital jk-type flip flop is a one-bit, edge-triggered storage element that will store data whenever the clk input line transitions from low to high (ZERO to ONE). In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_jkff have separate load values and delays associated with them. Additionally, you may specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies. \begin_inset Newline newline \end_inset Note that any UNKNOWN inputs other than j or k cause the output to go UNKNOWN automatically. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a8 1 2 3 4 5 6 7 flop2 \end_layout \begin_layout LyX-Code .model flop2 d_jkff(clk_delay = 13.0e-9 set_delay = 25.0e-9 \end_layout \begin_layout LyX-Code + reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9 \end_layout \begin_layout LyX-Code + fall_delay = 3e-9) \end_layout \begin_layout Subsection Toggle Flip Flop \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_tff \end_layout \begin_layout LyX-Code Spice_Model_Name: d_tff \end_layout \begin_layout LyX-Code Description: "digital toggle flip flop" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: t clk \end_layout \begin_layout LyX-Code Description: "toggle input" "clock" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: set reset \end_layout \begin_layout LyX-Code Description: "set" "reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out Nout \end_layout \begin_layout LyX-Code Description: "data output" "inverted data output" \end_layout \begin_layout LyX-Code Direction: out out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_delay set_delay \end_layout \begin_layout LyX-Code Description: "delay from clk" "delay from set" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_delay ic \end_layout \begin_layout LyX-Code Description: "delay from reset" "output initial state" \end_layout \begin_layout LyX-Code Data_Type: real int \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 0 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [0 2] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: t_load clk_load \end_layout \begin_layout LyX-Code Description: "toggle load value (F)" "clk load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: set_load reset_load \end_layout \begin_layout LyX-Code Description: "set load value (F)" "reset load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default.Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Standard Common parameters: rise_delay, fall_delay. \end_layout \begin_layout Description Description: The digital toggle-type flip flop is a one-bit, edge-triggered storage element that will toggle its current state whenever the clk input line transitions from low to high (ZERO to ONE). In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_tff have separate load values and delays associated with them. Additionally, you may specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies. \begin_inset Newline newline \end_inset Note that any UNKNOWN inputs other than t immediately cause the output to go UNKNOWN. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a8 2 12 4 5 6 3 flop3 \end_layout \begin_layout LyX-Code .model flop3 d_tff(clk_delay = 13.0e-9 set_delay = 25.0e-9 \end_layout \begin_layout LyX-Code + reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9 \end_layout \begin_layout LyX-Code + fall_delay = 3e-9 t_load = 0.2e-12) \end_layout \begin_layout Subsection Set-Reset Flip Flop \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_srff \end_layout \begin_layout LyX-Code Spice_Model_Name: d_srff \end_layout \begin_layout LyX-Code Description: "digital set-reset flip flop" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: s r \end_layout \begin_layout LyX-Code Description: "set input" "reset input" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: clk \end_layout \begin_layout LyX-Code Description: "clock" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: set reset \end_layout \begin_layout LyX-Code Description: "asynchronous set" "asynchronous reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out Nout \end_layout \begin_layout LyX-Code Description: "data output" "inverted data output" \end_layout \begin_layout LyX-Code Direction: out out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_delay set_delay \end_layout \begin_layout LyX-Code Description: "delay from clk" "delay from set" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_delay ic \end_layout \begin_layout LyX-Code Description: "delay from reset" "output initial state" \end_layout \begin_layout LyX-Code Data_Type: real int \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 0 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [0 2] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: sr_load clk_load \end_layout \begin_layout LyX-Code Description: "set/reset loads (F)" "clk load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: set_load reset_load \end_layout \begin_layout LyX-Code Description: "set load value (F)" "reset load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Standard Common parameters: rise_delay, fall_delay. \end_layout \begin_layout Description Description: The digital sr-type flip flop is a one-bit, edge-triggered storage element that will store data whenever the clk input line transitions from low to high (ZERO to ONE). The value stored (i.e., the \family typewriter out \family default value) will depend on the s and r input pin values, and will be: \end_layout \begin_layout LyX-Code out=ONE if s=ONE and r=ZERO; \end_layout \begin_layout LyX-Code out=ZERO if s=ZERO and r=ONE; \end_layout \begin_layout LyX-Code out=previous value if s=ZERO and r=ZERO; \end_layout \begin_layout LyX-Code out=UNKNOWN if s=ONE and r=ONE; \end_layout \begin_layout LyX-Code \end_layout \begin_layout Standard In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_srff have separate load values and delays associated with them. You may also specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies. \end_layout \begin_layout Standard Note that any UNKNOWN inputs other than s and r immediately cause the output to go UNKNOWN. \end_layout \begin_layout Standard Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a8 2 12 4 5 6 3 14 flop7 \end_layout \begin_layout LyX-Code .model flop7 d_srff(clk_delay = 13.0e-9 set_delay = 25.0e-9 \end_layout \begin_layout LyX-Code + reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9 \end_layout \begin_layout LyX-Code + fall_delay = 3e-9) \end_layout \begin_layout Subsection D Latch \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_dlatch \end_layout \begin_layout LyX-Code Spice_Model_Name: d_dlatch \end_layout \begin_layout LyX-Code Description: "digital d-type latch" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: data enable \end_layout \begin_layout LyX-Code Description: "input data" "enable input" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: set reset \end_layout \begin_layout LyX-Code Description: "set" "reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out Nout \end_layout \begin_layout LyX-Code Description: "data output" "inverter data output" \end_layout \begin_layout LyX-Code Direction: out out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: data_delay \end_layout \begin_layout LyX-Code Description: "delay from data" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: enable_delay set_delay \end_layout \begin_layout LyX-Code Description: "delay from enable" "delay from SET" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_delay ic \end_layout \begin_layout LyX-Code Description: "delay from RESET" "output initial state" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 0 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: data_load enable_load \end_layout \begin_layout LyX-Code Description: "data load (F)" "enable load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: set_load reset_load \end_layout \begin_layout LyX-Code Description: "set load value (F)" "reset load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Standard Common parameters: rise_delay, fall_delay. \end_layout \begin_layout Description Description: The digital d-type latch is a one-bit, level-sensitive storage element that will output the value on the data line whenever the enable input line is high (ONE). The value on the data line is stored (i.e., held on the out line) whenever the enable line is low (ZERO). \begin_inset Newline newline \end_inset In addition, asynchronous set and reset signals exist, and each of the four methods of changing the stored output of the d_dlatch (i.e., data changing with enable=ONE, enable changing to ONE from ZERO with a new value on data, raising set and raising reset) have separate delays associated with them. You may also specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies. \begin_inset Newline newline \end_inset Note that any UNKNOWN inputs other than on the data line when enable=ZERO immediately cause the output to go UNKNOWN. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 12 4 5 6 3 14 latch1 \end_layout \begin_layout LyX-Code .model latch1 d_dlatch(data_delay = 13.0e-9 enable_delay = 22.0e-9 \end_layout \begin_layout LyX-Code + set_delay = 25.0e-9 \end_layout \begin_layout LyX-Code + reset_delay = 27.0e-9 ic = 2 \end_layout \begin_layout LyX-Code + rise_delay = 10.0e-9 fall_delay = 3e-9) \end_layout \begin_layout Subsection Set-Reset Latch \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_srlatch \end_layout \begin_layout LyX-Code Spice_Model_Name: d_srlatch \end_layout \begin_layout LyX-Code Description: "digital sr-type latch" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: s r \end_layout \begin_layout LyX-Code Description: "set" "reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: enable \end_layout \begin_layout LyX-Code Description: "enable" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: set reset \end_layout \begin_layout LyX-Code Description: "set" "reset" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out Nout \end_layout \begin_layout LyX-Code Description: "data output" "inverted data output" \end_layout \begin_layout LyX-Code Direction: out out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: sr_delay \end_layout \begin_layout LyX-Code Description: "delay from s or r input change" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: enable_delay set_delay \end_layout \begin_layout LyX-Code Description: "delay from enable" "delay from SET" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_delay ic \end_layout \begin_layout LyX-Code Description: "delay from RESET" "output initial state" \end_layout \begin_layout LyX-Code Data_Type: real boolean \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 0 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: sr_load enable_load \end_layout \begin_layout LyX-Code Description: "s & r input loads (F)" "enable load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: set_load reset_load \end_layout \begin_layout LyX-Code Description: "set load value (F)" "reset load (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout Standard Common parameters: rise_delay, fall_delay. \end_layout \begin_layout Description Description: The digital sr-type latch is a one-bit, level-sensitive storage element that will output the value dictated by the state of the s and r pins whenever the enable input line is high (ONE). This value is stored (i.e., held on the out line) whenever the enable line is low (ZERO). The particular value chosen is as shown below: \end_layout \begin_layout LyX-Code s=ZERO, r=ZERO => out=current value (i.e., not change in output) \end_layout \begin_layout LyX-Code s=ZERO, r=ONE => out=ZERO \end_layout \begin_layout LyX-Code s=ONE, r=ZERO => out=ONE \end_layout \begin_layout LyX-Code s=ONE, r=ONE => out=UNKNOWN \end_layout \begin_layout Standard Asynchronous set and reset signals exist, and each of the four methods of changing the stored output of the d srlatch (i.e., s/r combination changing with enable=ONE, enable changing to ONE from ZERO with an output-changing combination of s and r, raising set and raising reset) have separate delays associated with them. You may also specify separate rise and fall delay values that are added to those specified for the input lines; these allow for more faithful reproduction of the output characteristics of different IC fabrication technologies. \end_layout \begin_layout Standard Note that any UNKNOWN inputs other than on the s and r lines when enable=ZERO immediately cause the output to go UNKNOWN. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 12 4 5 6 3 14 16 latch2 \end_layout \begin_layout LyX-Code .model latch2 d_srlatch(sr_delay = 13.0e-9 enable_delay = 22.0e-9 \end_layout \begin_layout LyX-Code + set_delay = 25.0e-9 \end_layout \begin_layout LyX-Code + reset_delay = 27.0e-9 ic = 2 \end_layout \begin_layout LyX-Code + rise_delay = 10.0e-9 fall_delay = 3e-9) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:State-Machine" \end_inset State Machine \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_state \end_layout \begin_layout LyX-Code Spice_Model_Name: d_state \end_layout \begin_layout LyX-Code Description: "digital state machine" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: in clk \end_layout \begin_layout LyX-Code Description: "input" "clock" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] - \end_layout \begin_layout LyX-Code Null_Allowed: yes no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: reset out \end_layout \begin_layout LyX-Code Description: "reset" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no yes \end_layout \begin_layout LyX-Code Vector_Bounds: - [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: yes no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_delay reset_delay \end_layout \begin_layout LyX-Code Description: "delay from CLK" "delay from RESET" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: Parameter_Name: state_file \end_layout \begin_layout LyX-Code Description: "state transition specification file name" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: "state.txt" \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_state \end_layout \begin_layout LyX-Code Description: "default state on RESET & at DC" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_load \end_layout \begin_layout LyX-Code Description: "clock loading capacitance (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_load \end_layout \begin_layout LyX-Code Description: "reset loading capacitance (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Standard Common parameters: input_load. \end_layout \begin_layout Description Description: The digital state machine provides for straightforward descriptions of clocked \series medium combinational \series default logic blocks with a variable number of inputs and outputs and with an unlimited number of possible states. The model can be configured to behave as virtually any type of counter or clocked \series medium combinational \series default logic block and can be used to replace very large digital circuit schematics with an identically functional but faster representation. \begin_inset Newline newline \end_inset The d state model is configured through the use of a state definition file (state.in) that resides in a directory of your choosing. The file defines all states to be understood by the model, plus input bit combinations that trigger changes in state. An example state.in file is shown below: \end_layout \begin_layout LyX-Code ----------- begin file ------------- \end_layout \begin_layout LyX-Code * This is an example state.in file. This file \end_layout \begin_layout LyX-Code * defines a simple 2-bit counter with one input. The \end_layout \begin_layout LyX-Code * value of this input determines whether the counter counts \end_layout \begin_layout LyX-Code * up (in = 1) or down (in = 0). \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code 0 0s 0s 0 -> 3 \end_layout \begin_layout LyX-Code 1 -> 1 \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code 1 0s 1z 0 -> 0 \end_layout \begin_layout LyX-Code 1 -> 2 \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code 2 1z 0s 0 -> 1 \end_layout \begin_layout LyX-Code 1 -> 3 \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code 3 1z 1z 0 -> 2 \end_layout \begin_layout LyX-Code 3 1z 1z 1 -> 0 \end_layout \begin_layout LyX-Code ------------------ end file --------------- \end_layout \begin_layout Standard Several attributes of the above file structure should be noted. First, \emph on all lines in the file must be one of four types \emph default . These are \end_layout \begin_layout Enumerate A comment, beginning with a ` \family typewriter * \family default ' in the first column. \end_layout \begin_layout Enumerate A header line, which is a complete description of the current state, the outputs corresponding to that state, an input value, and the state that the model will assume should that input be encountered. The first line of a state definition must \emph on always \emph default be a header line. \end_layout \begin_layout Enumerate A continuation line, which is a partial description of a state, consisting of an input value and the state that the model will assume should that input be encountered. Note that continuation lines may only be used after the initial header line definition for a state. \end_layout \begin_layout Enumerate A line containing nothing but white-spaces (space, form-feed, newline, carriage return, tab, vertical tab). \end_layout \begin_layout Standard A line that is not one of the above will cause a file-loading error. Note that in the example shown, whitespace (any combination of blanks, tabs, commas) is used to separate values, and that the character \family typewriter -> \family default is used to underline the state transition implied by the input preceding it. This particular character is not critical in of itself, and can be replaced with any other character or non-broken combination of characters that you prefer (e.g. \family typewriter ==> \family default , \family typewriter >> \family default , ' \family typewriter : \family default ', \family typewriter resolves_to \family default , etc.) \end_layout \begin_layout Standard The order of the output and input bits in the file is important; the first column is always interpreted to refer to the 'zeroth' bit of input and output. Thus, in the file above, the output from state 1 sets \family typewriter out \family default [0] to \family typewriter 0s \family default , and \family typewriter out \family default [1] to \family typewriter 1z \family default . \end_layout \begin_layout Standard The state numbers need not be in any particular order, but a state definition (which consists of the sum total of all lines that define the state, its outputs, and all methods by which a state can be exited) must be made on contiguous line numbers; a state definition cannot be broken into sub-blocks and distributed randomly throughout the file. On the other hand, the state definition can be broken up by as many comment lines as you desire. \end_layout \begin_layout Standard Header files may be used throughout the \family sans state.in \family default file, and continuation lines can be discarded completely if you so choose: continuation lines are primarily provided as a convenience. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 [2 3 4 5] 1 12 [22 23 24 25 26 27 28 29] state1 \end_layout \begin_layout LyX-Code .model state1 d_state(clk_delay = 13.0e-9 reset_delay = 27.0e-9 \end_layout \begin_layout LyX-Code + state_file = "newstate.txt" reset_state = 2) \end_layout \begin_layout Description Note: The file named by the parameter \family typewriter filename \family default in \family typewriter state_file= \family default " \family typewriter filename \family default " is sought after according to a search list described in \begin_inset CommandInset ref LatexCommand ref reference "subsec:Search-path-for" nolink "false" \end_inset . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Frequency-Divider" \end_inset Frequency Divider \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_fdiv \end_layout \begin_layout LyX-Code Spice_Model_Name: d_fdiv \end_layout \begin_layout LyX-Code Description: "digital frequency divider" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: freq_in freq_out \end_layout \begin_layout LyX-Code Description: "frequency input" "frequency output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: div_factor high_cycles \end_layout \begin_layout LyX-Code Description: "divide factor" "# of cycles for high out" \end_layout \begin_layout LyX-Code Data_Type: int int \end_layout \begin_layout LyX-Code Default_Value: 2 1 \end_layout \begin_layout LyX-Code Limits: [1 -] [1 div_factor-1] \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: i_count \end_layout \begin_layout LyX-Code Description: "divider initial count value" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: freq_in_load \end_layout \begin_layout LyX-Code Description: "freq_in load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Standard Common parameters: rise_delay, fall_delay. \end_layout \begin_layout Description Description: The digital frequency divider is a programmable step-down divider that accepts an arbitrary divisor (div_factor), a duty-cycle term (high_cycles), and an initial count value (i_count). The generated output is synchronized to the rising edges of the input signal. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 3 7 divider \end_layout \begin_layout LyX-Code .model divider d_fdiv(div_factor = 5 high_cycles = 3 \end_layout \begin_layout LyX-Code + i_count = 4 rise_delay = 23e-9 \end_layout \begin_layout LyX-Code + fall_delay = 9e-9) \end_layout \begin_layout Subsection RAM \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_ram \end_layout \begin_layout LyX-Code Spice_Model_Name: d_ram \end_layout \begin_layout LyX-Code Description: "digital random-access memory" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: data_in data_out \end_layout \begin_layout LyX-Code Description: "data input line(s)" "data output line(s)" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] data_in \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: address write_en \end_layout \begin_layout LyX-Code Description: "address input line(s)" "write enable line" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: select \end_layout \begin_layout LyX-Code Description: "chip select line(s)" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [1 16] \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: select_value \end_layout \begin_layout LyX-Code Description: "decimal active value for select line comparison" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 1 \end_layout \begin_layout LyX-Code Limits: [0 32767] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: ic \end_layout \begin_layout LyX-Code Description: "initial bit state @ dc" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 2 \end_layout \begin_layout LyX-Code Limits: [0 2] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: read_delay \end_layout \begin_layout LyX-Code Description: "read delay from address/select/write.en active" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 100.0e-9 \end_layout \begin_layout LyX-Code Limits: [1.0e-12 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: data_load address_load \end_layout \begin_layout LyX-Code Description: "data_in load value (F)" "addr. load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: no no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: select_load \end_layout \begin_layout LyX-Code Description: "select load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: enable_load \end_layout \begin_layout LyX-Code Description: "enable line load value (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital RAM is an M-wide, N-deep random access memory element with programmable select lines, tristated data out lines, and a single write/~read line. The width of the RAM words (M) is set through the use of the word width parameter. The depth of the RAM (N) is set by the number of address lines input to the device. The value of N is related to the number of address input lines (P) by the following equation: \begin_inset Formula \[ 2^{P}=N \] \end_inset There is no reset line into the device. However, an initial value for all bits may be specified by setting the ic parameter to either 0 or 1. In reading a word from the ram, the read delay value is invoked, and output will not appear until that delay has been satisfied. Separate rise and fall delays are not supported for this device. \begin_inset Newline newline \end_inset Note that UNKNOWN inputs on the address lines are not allowed during a write. In the event that an address line does indeed go unknown during a write, \emph on the entire contents of the ram will be set to unknown \emph default . This is in contrast to the data in lines being set to unknown during a write; in that case, only the selected word will be corrupted, and this is corrected once the data lines settle back to a known value. Note that protection is added to the write en line such that extended UNKNOWN values on that line are interpreted as ZERO values. This is the equivalent of a read operation and will not corrupt the contents of the RAM. A similar mechanism exists for the select lines. If they are unknown, then it is assumed that the chip is not selected. \begin_inset Newline newline \end_inset Detailed timing-checking routines are not provided in this model, other than for the enable delay and select delay restrictions on read operations. You are advised, therefore, to carefully check the timing into and out of the RAM for correct read and write cycle times, setup and hold times, etc. for the particular device they are attempting to model. \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a4 [3 4 5 6] [3 4 5 6] [12 13 14 15 16 17 18 19] 30 [22 23 24] ram2 \end_layout \begin_layout LyX-Code .model ram2 d_ram(select_value = 2 ic = 2 read_delay = 80e-9) \end_layout \begin_layout LyX-Code \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Digital-Source" \end_inset Digital Source \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_source \end_layout \begin_layout LyX-Code Spice_Model_Name: d_source \end_layout \begin_layout LyX-Code Description: "digital signal source" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port Name: out \end_layout \begin_layout LyX-Code Description: "output" \end_layout \begin_layout LyX-Code Direction: out \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_file \end_layout \begin_layout LyX-Code Description: "digital input vector filename" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: "source.txt" \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Standard Common parameters: input_load. \end_layout \begin_layout Description Description: The digital source provides for straightforward descriptions of digital signal vectors in a tabular format. The model reads input from the input file and, at the times specified in the file, generates the inputs along with the strengths listed. The format of the input file is as shown below. Note that comment lines are delineated through the use of a single ` \family typewriter * \family default ' character in the first column of a line. This is similar to the way the SPICE program handles comments. \end_layout \begin_layout LyX-Code * T c n n n . . . \end_layout \begin_layout LyX-Code * i l o o o . . . \end_layout \begin_layout LyX-Code * m o d d d . . . \end_layout \begin_layout LyX-Code * e c e e e . . . \end_layout \begin_layout LyX-Code * k a b c . . . \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code 0.0000 Uu Uu Us Uu . . . \end_layout \begin_layout LyX-Code 1.234e-9 0s 1s 1s 0z . . . \end_layout \begin_layout LyX-Code 1.376e-9 0s 0s 1s 0z . . . \end_layout \begin_layout LyX-Code 2.5e-7 1s 0s 1s 0z . . . \end_layout \begin_layout LyX-Code 2.5006e-7 1s 1s 1s 0z . . . \end_layout \begin_layout LyX-Code 5.0e-7 0s 1s 1s 0z . . . \end_layout \begin_layout Standard Note that in the example shown, whitespace (any combination of blanks, tabs, commas) is used to separate the time and state/strength tokens. The order of the input columns is important; the first column is always interpreted to mean `time'. The second through the N'th columns map to the \family typewriter out \family default [0] through \family typewriter out \family default [N-2] output nodes. A non-commented line that does not contain enough tokens to completely define all outputs for the digital source will cause an error. Also, time values must increase monotonically or an error will result in reading the source file. \end_layout \begin_layout Standard Errors will also occur if a line exists in \family sans source.txt \family default that is neither a comment nor vector line. The only exception to this is in the case of a line that is completely blank; this is treated as a comment (note that such lines often occur at the end of text within a file; ignoring these in particular prevents nuisance errors on the part of the simulator). \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code a3 [2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17] input_vector \end_layout \begin_layout LyX-Code .model input_vector d_source(input_file = "source_simple.text") \end_layout \begin_layout Description Note: The file named by the parameter \family typewriter filename \family default in \family typewriter input_file= \family default " \family typewriter filename \family default " is sought after according to a search list described in \begin_inset CommandInset ref LatexCommand ref reference "subsec:Search-path-for" nolink "false" \end_inset . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:LUT" \end_inset LUT \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_lut \end_layout \begin_layout LyX-Code Spice_Model_Name: d_lut \end_layout \begin_layout LyX-Code Description: "digital n-input look-up table gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: [1 -] - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: table_values \end_layout \begin_layout LyX-Code Description: "lookup table values" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout Standard Common parameters: rise_delay, fall_delay, input_load. \end_layout \begin_layout Description Description: \series medium The lookup table provides a way to map any arbitrary n-input, 1-output combinational logic block to XSPICE. The inputs are mapped to the output using a string of length 2^n. The string may contain values "0", "1" or "X", corresponding to an output of low, high, or unknown, respectively. The outputs are only mapped for inputs which are valid logic levels. Any unknown bit in the input vector will always produce an unknown output. The first character of the string \family typewriter table_values \family default corresponds to all inputs value zero, and the last (2^n) character corresponds to all inputs value one, with the first signal in the input vector being the least significant bit. For example, a 2-input lookup table representing the function \family typewriter (A * B) \family default (that is, \family typewriter A AND B \family default ), with input vector \family typewriter [A B] \family default can be constructed with a \family typewriter table_values \family default string of "0001"; function \family typewriter (~A * B) \family default with input vector \family typewriter [A B] \family default can be constructed with a \family typewriter table_values \family default string of "0010". \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code * LUT encoding 3-bit parity function \end_layout \begin_layout LyX-Code a4 [1 2 3] 5 lut_pty3_1 \end_layout \begin_layout LyX-Code .model lut_pty3_1 d_lut(table_values = "01101001" \end_layout \begin_layout LyX-Code + input_load 2.0e-12) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:GENLUT" \end_inset General LUT \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_genlut \end_layout \begin_layout LyX-Code Spice_Model_Name: d_genlut \end_layout \begin_layout LyX-Code Description: "digital n-input x m-output look-up table gate" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in out \end_layout \begin_layout LyX-Code Description: "input" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: no no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load input_delay \end_layout \begin_layout LyX-Code Description: "input load value (F)" "input delay" \end_layout \begin_layout LyX-Code Data_Type: real real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 0.0 \end_layout \begin_layout LyX-Code Limits: - - \end_layout \begin_layout LyX-Code Vector: yes yes \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: table_values \end_layout \begin_layout LyX-Code Description: "lookup table values" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout Standard Common parameters: rise_delay, fall_delay. \end_layout \begin_layout Description Description: \series medium The lookup table provides a way to map any arbitrary n-input, m-output combinational logic block to XSPICE. The inputs are mapped to the output using a string of length m * (2^n). The string may contain values "0", "1", "X", or "Z", corresponding to an output of low, high, unknown, or high-impedance, respectively. The outputs are only mapped for inputs which are valid logic levels. Any unknown bit in the input vector will always produce an unknown output. The character string is in groups of (2^n) characters, one group corresponding to each output pin, in order. The first character of a group in the string \family typewriter table_values \family default corresponds to all inputs value zero, and the last (2^n) character in the group corresponds to all inputs value one, with the first signal in the input vector being the least significant bit. For example, a 2-input lookup table representing the function \family typewriter (A * B) \family default (that is, \family typewriter A AND B \family default ), with input vector \family typewriter [A B] \family default can be constructed with a \family typewriter table_values \family default string of "0001"; function \family typewriter (~A * B) \family default with input vector \family typewriter [A B] \family default can be constructed with a "table_values" string of "0010". The delays associated with each output pin's rise and those associated with each output pin's fall may be specified independently. The model also posts independent input load values per input pin (in farads) based on the parameter \family typewriter input_load \family default . The parameter \family typewriter input_delay \family default provides a way to specify additional delay between each input pin and the output. This delay is added to the rise- or fall-time of the output. The output of this model does not respond to the total loading it sees on the output; it will always drive the output strongly with the specified delays. \series default \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code * LUT encoding 3-bit parity function \end_layout \begin_layout LyX-Code a4 [1 2 3] [5] lut_pty3_1 \end_layout \begin_layout LyX-Code .model lut_pty3_1 d_genlut(table_values = "01101001" \end_layout \begin_layout LyX-Code + input_load [2.0e-12]) \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code * LUT encoding a tristate inverter function (en in out) \end_layout \begin_layout LyX-Code a2 [1 2] [3] lut_triinv_1 \end_layout \begin_layout LyX-Code .model lut_triinv_1 d_genlut(table_values = "Z1Z0") \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code * LUT encoding a half-adder function (A B Carry Sum) \end_layout \begin_layout LyX-Code a8 [1 2] [3 4] lut_halfadd_1 \end_layout \begin_layout LyX-Code .model lut_halfadd_1 d_genlut(table_values = "00010110" \end_layout \begin_layout LyX-Code + rise_delay [ 1.5e-9 1.0e-9 ] fall_delay [ 1.5e-9 1.0e-9 ]) \end_layout \begin_layout Subsection D_process \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code C_Function_Name: cm_d_process \end_layout \begin_layout LyX-Code Spice_Model_Name: d_process \end_layout \begin_layout LyX-Code Description: "digital process" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in clk \end_layout \begin_layout LyX-Code Description: "input" "clock" \end_layout \begin_layout LyX-Code Direction: in in \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: yes no \end_layout \begin_layout LyX-Code Vector_Bounds: - - \end_layout \begin_layout LyX-Code Null_Allowed: yes no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: reset out \end_layout \begin_layout LyX-Code Description: "reset" "output" \end_layout \begin_layout LyX-Code Direction: in out \end_layout \begin_layout LyX-Code Default_Type: d d \end_layout \begin_layout LyX-Code Allowed_Types: [d] [d] \end_layout \begin_layout LyX-Code Vector: no yes \end_layout \begin_layout LyX-Code Vector_Bounds: - [1 -] \end_layout \begin_layout LyX-Code Null_Allowed: yes no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_delay \end_layout \begin_layout LyX-Code Description: "delay from CLK" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: process_file \end_layout \begin_layout LyX-Code Description: "file name of the executable process" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: "process" \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: process_params \end_layout \begin_layout LyX-Code Description: "parameters to be passed to an executable process" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: input_load \end_layout \begin_layout LyX-Code Description: "input loading capacitance (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: clk_load \end_layout \begin_layout LyX-Code Description: "clock loading capacitance (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: reset_load \end_layout \begin_layout LyX-Code Description: "reset loading capacitance (F)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-12 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Description Description: The digital d_process model runs an external program, specified by the process_file parameter, to read the input signals when the clock changes to ONE and then produces the output signals after the clk_delay. There can be zero (null) or more inputs, and one or more outputs. The maximum number of inputs or outputs is 255 bits wide. If a reset signal is specified and has the value ONE when the clock changes to ONE, the external program is notified of the reset by sending it a negative time value. The output signals are initialized to Uz. The strength (s, r, z, u) of an input signal is ignored. After time 0.0 initialization, outputs are driven with STRONG (s) strength. The input and output states are binary ONE or ZERO. If an input value is UNKNOWN (U) then a ONE or ZERO is chosen at random. \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset The external program is started by fork/exec or spawn, and connections are established using pipes. The external program is written in C, and first of all, in main() the argc, argv parameters can be read. These command line parameters are those specified in the process_params field of the d_process .model statement. A header is sent from ngspice to the external program which acknowledges that the number of inputs and outputs match. Thereafter, the external program executes a loop: while (read data from the input pipe and if it is OK) { compute output data for that input write the output data to the output pipe } In the meantime the cm_d_process code in ngspice is writing data to its output pipe at each clock change to ONE, then reading on its input pipe the response from the external program. \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset Please see examples/xspice/d_process for a simple example and study the source code in the .c files. The d_process model was developed by Uros Platise and he has provided a non-trivial example and detailed descriptions at: \begin_inset Newline newline \end_inset \begin_inset CommandInset href LatexCommand href name "https://www.isotel.eu/mixedsim/embedded/motorforce/index.html" target "https://www.isotel.eu/mixedsim/embedded/motorforce/index.html" literal "false" \end_inset . \end_layout \begin_layout LyX-Code Example SPICE Usage: \end_layout \begin_layout LyX-Code a1 [d1] clk1 reset1 [o1 o2 o3 o4] proc1 \end_layout \begin_layout LyX-Code .model proc1 d_process (process_file="prog1in4out" \end_layout \begin_layout LyX-Code + clk_delay = 2.5e-9) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:d_cosim" \end_inset d_cosim \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Spice_Model_Name: d_cosim \end_layout \begin_layout LyX-Code C_Function_Name: ucm_d_cosim \end_layout \begin_layout LyX-Code Description: "Bridge to an irreversible digital model" \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Port_Name: d_in \end_layout \begin_layout LyX-Code Description: "digital input" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [0 -] \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Port_Name: d_out \end_layout \begin_layout LyX-Code Description: "digital output" \end_layout \begin_layout LyX-Code Direction: out \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [0 -] \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Port_Name: d_inout \end_layout \begin_layout LyX-Code Description: "digital bidirectional port" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: d \end_layout \begin_layout LyX-Code Allowed_Types: [d] \end_layout \begin_layout LyX-Code Vector: yes \end_layout \begin_layout LyX-Code Vector_Bounds: [0 -] \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: delay \end_layout \begin_layout LyX-Code Description: "output delay time" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0e-9 \end_layout \begin_layout LyX-Code Limits: [1e-12 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: simulation \end_layout \begin_layout LyX-Code Description: "A shared library containing a digital model" \end_layout \begin_layout LyX-Code Data_Type: string \end_layout \begin_layout LyX-Code Default_Value: - \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code /* Instances maintain an internal input event queue that should be at least \end_layout \begin_layout LyX-Code * as large as the number of inputs. Performance with clocked logic may \end_layout \begin_layout LyX-Code * be improved by making it larger than (2 * F) / MTS, where F is \end_layout \begin_layout LyX-Code * the clock frequency and MTS is the maximum timestep for .tran. \end_layout \begin_layout LyX-Code */ \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: queue_size \end_layout \begin_layout LyX-Code Description: "input queue size" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 128 \end_layout \begin_layout LyX-Code Limits: [1 -] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Parameter_Name: irreversible \end_layout \begin_layout LyX-Code Description: "Parameter passed to library function cm_irreversible()" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 1 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Static_Var_Name: cosim_instance \end_layout \begin_layout LyX-Code Data_Type: pointer \end_layout \begin_layout LyX-Code Description: "Per-instance structure" \end_layout \begin_layout Standard The d_cosim code model is similar to d_process, as it also requires external software to define the behaviour of a code model instance. An important difference is that with d_cosim such software runs inside the ngspice process. This code model is intended as a container for other types of digital simulation and to provide a simplified programming interface for devices whose behaviour is defined purely by conventional software. In particular, it is intended to act as a container for sub-simulations that can not discard any time steps that fail in the main simulator; that is, they are irreversible. \end_layout \begin_layout Standard The actual behaviour of any d_cosim instance is defined by a shared library or Windows DLL that is set by the 'simulation' parameter and dynamically loaded. Input changes are relayed to a function in this library and any outputs reported by the library are relayed to the simulated circuit. The interface between this code model and the library that it hosts is defined in C-language header file cosim.h, included in the Ngspice source code and in directory share/ngspice/scripts/src/ngspice in a binary package. This interface is simpler than the XSPICE programming interface, but that has a cost: without special care only one d_cosim instance should exist in a circuit. For more information, see the description of cm_irreversible() in section \begin_inset CommandInset ref LatexCommand ref reference "cm_irreversible" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . \end_layout \begin_layout Standard Example SPICE usage: \end_layout \begin_layout LyX-Code adut [ Clk Comp Start] [Sample Valid ~d5 ~d4 ~d3 ~d2 ~d1 ~d0] null dut \end_layout \begin_layout LyX-Code .model dut d_cosim simulation="./adc.so" \end_layout \begin_layout Standard A method for creating a suitable library from HDL code is described in section \begin_inset CommandInset ref LatexCommand ref reference "sec:digital-devices-HDL" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . \end_layout \begin_layout Section Transmission lines models \end_layout \begin_layout Standard A set of XSPICE transmission lines models was added since the version 45. These models include microstrip lines and allow to simulate RF circuits with Ngspice. Here is an overview of this model group. All devices mentioned described in this section are available from Qucs-S schematic capture GUI. \end_layout \begin_layout Subsection Generic transmission line \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: tline \end_layout \begin_layout LyX-Code C_Function_Name: cm_tline \end_layout \begin_layout LyX-Code Description: "Generic transmission line" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: in \end_layout \begin_layout LyX-Code Description: "Terminals" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: hd \end_layout \begin_layout LyX-Code Allowed_Types: [hd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: out \end_layout \begin_layout LyX-Code Description: "Terminals" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: hd \end_layout \begin_layout LyX-Code Allowed_Types: [hd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: V1sens \end_layout \begin_layout LyX-Code Description: "Sensing terminals" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: V2sens \end_layout \begin_layout LyX-Code Description: "Sensing terminals" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: l \end_layout \begin_layout LyX-Code Description: "length" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: z \end_layout \begin_layout LyX-Code Description: "characteristic impedance" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 50.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: a \end_layout \begin_layout LyX-Code Description: "attenuation per length (dB)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code Static_Var_Name: sim_points_data \end_layout \begin_layout LyX-Code Description: "local static data" \end_layout \begin_layout LyX-Code Data_Type: pointer \end_layout \begin_layout Verbatim \end_layout \begin_layout Standard This model represents a generic transmission line described by characteristic impedance, length, and attenuation per length. The device contains models for both the frequency and time domains. The XSPICE device has four ports. The V1sens and V2sens terminals are the voltage sensing terminals. They should be connected in parallels to the line terminals. These terminals serve for the transient model. An example of netlist entry for this device is given below: \end_layout \begin_layout LyX-Code A1 %hd(in 0) %hd(out 0) %vd(in 0) %vd(out 0) TLIN1 \end_layout \begin_layout LyX-Code .MODEL TLIN1 TLINE(l=100e-3 z=50.0 a=0.0) \end_layout \begin_layout Standard This device represents a lossless transmission line with 50Ohm characteristic impedance and 100mm length. The sensing terminals are connected in parallel to the input and output terminals (nodes in and out). \end_layout \begin_layout Subsection Generic coupled lines \end_layout \begin_layout Verbatim \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: cpline \end_layout \begin_layout LyX-Code C_Function_Name: cm_cpline \end_layout \begin_layout LyX-Code Description: "Generic transmission line" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p1 \end_layout \begin_layout LyX-Code Description: "Terminals Line1" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: hd \end_layout \begin_layout LyX-Code Allowed_Types: [hd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p2 \end_layout \begin_layout LyX-Code Description: "Terminals Line1" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: hd \end_layout \begin_layout LyX-Code Allowed_Types: [hd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p3 \end_layout \begin_layout LyX-Code Description: "Terminals Line2" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: hd \end_layout \begin_layout LyX-Code Allowed_Types: [hd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p4 \end_layout \begin_layout LyX-Code Description: "Terminals Line2" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: hd \end_layout \begin_layout LyX-Code Allowed_Types: [hd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p1s \end_layout \begin_layout LyX-Code Description: "Sensing terminals line 1" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p2s \end_layout \begin_layout LyX-Code Description: "Sensing terminals line 1" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p3s \end_layout \begin_layout LyX-Code Description: "Sensing terminals line 1" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p4s \end_layout \begin_layout LyX-Code Description: "Sensing terminals line 1" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: l \end_layout \begin_layout LyX-Code Description: "length" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: ze \end_layout \begin_layout LyX-Code Description: "characteristic impedance of even mode" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 50.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: zo \end_layout \begin_layout LyX-Code Description: "characteristic impedance of odd mode" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 50.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: ae \end_layout \begin_layout LyX-Code Description: "attenuation per length (dB) even mode" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: ao \end_layout \begin_layout LyX-Code Description: "attenuation per length (dB) odd mode" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: ere \end_layout \begin_layout LyX-Code Description: "dielectric constant even mode" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: ero \end_layout \begin_layout LyX-Code Description: "dielectric constant odd mode" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code Static_Var_Name: sim_points_data \end_layout \begin_layout LyX-Code Description: "local static data" \end_layout \begin_layout LyX-Code Data_Type: pointer \end_layout \begin_layout Verbatim \end_layout \begin_layout Standard The device represents two generic coupled lines. It is described by characteristic impedance for even and odd propagation modes, line length, and attenuation. The device also provides both frequency and time domain models. The voltage sensing ports should be connected in parallel to the line terminals. For example p1s in parallel to p1. An example of SPICE entry for the coupled lines is shown below: \end_layout \begin_layout LyX-Code A1 %hd(p1 0) %hd(p2 0) %hd(p3 0) %hd(p4 0) \end_layout \begin_layout LyX-Code + %vd(p1 0) %vd(p2 0) %vd(p3 0) %vd(p4 0) CPLINE1 \end_layout \begin_layout LyX-Code .MODEL CPLINE1 CPLINE(ze=100 zo=50 l=100e-3 ere=1 \end_layout \begin_layout LyX-Code + ero=1 ao=0 ae=0) \end_layout \begin_layout Verbatim \end_layout \begin_layout Subsection Microstip line \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: mlin \end_layout \begin_layout LyX-Code C_Function_Name: cm_mlin \end_layout \begin_layout LyX-Code Description: "Microstrip line" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: port1 \end_layout \begin_layout LyX-Code Description: "Microstrip terminals" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: hd \end_layout \begin_layout LyX-Code Allowed_Types: [hd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: port2 \end_layout \begin_layout LyX-Code Description: "Microstrip terminals" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: hd \end_layout \begin_layout LyX-Code Allowed_Types: [hd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: V1sens \end_layout \begin_layout LyX-Code Description: "Sensing terminals" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: V2sens \end_layout \begin_layout LyX-Code Description: "Sensisng terminals" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: l \end_layout \begin_layout LyX-Code Description: "length (m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1e-2 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: w \end_layout \begin_layout LyX-Code Description: "width (m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1e-3 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: model \end_layout \begin_layout LyX-Code Description: "Model type" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: disp \end_layout \begin_layout LyX-Code Description: "Dispersion type" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: er \end_layout \begin_layout LyX-Code Description: "Substrate dielectric permittivity" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 9.8 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: h \end_layout \begin_layout LyX-Code Description: "Substrate thickness (m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1e-3 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: t \end_layout \begin_layout LyX-Code Description: "Metal strip thickness (m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 35e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: tand \end_layout \begin_layout LyX-Code Description: "Substrate dielectric loss" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 2e-4 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rho \end_layout \begin_layout LyX-Code Description: "Metal resistance (Ohm*m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.022e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: d \end_layout \begin_layout LyX-Code Description: "RMS Substrate roughness" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.15e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: tranmodel \end_layout \begin_layout LyX-Code Description: "TRAN model DC/FULL" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code Static_Var_Name: sim_points_data \end_layout \begin_layout LyX-Code Description: "local static data" \end_layout \begin_layout LyX-Code Data_Type: pointer \end_layout \begin_layout Verbatim \end_layout \begin_layout Standard This device represents the simple microstrip line. The connection scheme is the same as for generic transmission line. The er, h, t, tand, d, and rho parameters represent the substrate properties. This device includes both AC and transient model. The transient model is disabled by default and could be enabled by setting the tranmodel=1 property. Microstrip line allows to represent frequency dependency model and different dispersion model. It could be controlled by setting model and disp properties according the tables below. Set the appropriate code in the disp and model parameters. \end_layout \begin_layout Standard \begin_inset Float table placement document alignment document wide false sideways false status open \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout Microstrip model setting \end_layout \end_inset \begin_inset CommandInset label LatexCommand label name "tab:msline_model" \end_inset \end_layout \begin_layout Plain Layout \align center \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Model property value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Microstrip model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 (default) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Hammerstad \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Kirschning \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Wheeler \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Scheider \end_layout \end_inset \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Float table placement document alignment document wide false sideways false status open \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout Dispersion models \end_layout \end_inset \begin_inset CommandInset label LatexCommand label name "tab:dispersion" \end_inset \end_layout \begin_layout Plain Layout \align center \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Disp property value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Dispersion model \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 (default) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Kirschning \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Kobayashi \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Yamashita \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Hammerstad \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout getsinger \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 5 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Scheider \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Pramanick \end_layout \end_inset \end_inset \end_layout \end_inset \end_layout \begin_layout Standard An example of the microstrip device SPICE entry is shown below. The voltage sensing ports are connected in parallel to device ports (nodes in and out). \end_layout \begin_layout LyX-Code A1 %hd(in 0) %hd(out 0) %vd(in 0) %vd(out 0) MLIN1 \end_layout \begin_layout LyX-Code .MODEL MLIN1 MLIN(w=1e-3 l=50e-3 er=9.8 h=1e-3 t=35e-6 tand=1e-3 \end_layout \begin_layout LyX-Code + rho=0.022e-6 d=0.15e-6 model=0 disp=0 tranmodel=0) \end_layout \begin_layout Subsection Coupled microstrip \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: cpmlin \end_layout \begin_layout LyX-Code C_Function_Name: cm_cpmline \end_layout \begin_layout LyX-Code Description: "Generic transmission line" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p1 \end_layout \begin_layout LyX-Code Description: "Terminals Line1" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: hd \end_layout \begin_layout LyX-Code Allowed_Types: [hd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p2 \end_layout \begin_layout LyX-Code Description: "Terminals Line1" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: hd \end_layout \begin_layout LyX-Code Allowed_Types: [hd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p3 \end_layout \begin_layout LyX-Code Description: "Terminals Line2" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: hd \end_layout \begin_layout LyX-Code Allowed_Types: [hd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p4 \end_layout \begin_layout LyX-Code Description: "Terminals Line2" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: hd \end_layout \begin_layout LyX-Code Allowed_Types: [hd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p1s \end_layout \begin_layout LyX-Code Description: "Sensing terminals line 1" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p2s \end_layout \begin_layout LyX-Code Description: "Sensing terminals line 1" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p3s \end_layout \begin_layout LyX-Code Description: "Sensing terminals line 1" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p4s \end_layout \begin_layout LyX-Code Description: "Sensing terminals line 1" \end_layout \begin_layout LyX-Code Direction: in \end_layout \begin_layout LyX-Code Default_Type: vd \end_layout \begin_layout LyX-Code Allowed_Types: [vd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: l \end_layout \begin_layout LyX-Code Description: "length (m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1.0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: w \end_layout \begin_layout LyX-Code Description: "width (m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1e-3 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: s \end_layout \begin_layout LyX-Code Description: "gap (m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1e-3 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: model \end_layout \begin_layout LyX-Code Description: "Model type" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: disp \end_layout \begin_layout LyX-Code Description: "Dispersion type" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: er \end_layout \begin_layout LyX-Code Description: "Substrate dielectric permittivity" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 9.8 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: h \end_layout \begin_layout LyX-Code Description: "Substrate thickness (m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1e-3 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: t \end_layout \begin_layout LyX-Code Description: "Metal strip thickness (m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 35e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: tand \end_layout \begin_layout LyX-Code Description: "Substrate dielectric loss" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 2e-4 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rho \end_layout \begin_layout LyX-Code Description: "Metal resistance (Ohm*m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.022e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: d \end_layout \begin_layout LyX-Code Description: "RMS Substrate roughness" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.15e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: tranmodel \end_layout \begin_layout LyX-Code Description: "TRAN model DC/FULL" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code STATIC_VAR_TABLE: \end_layout \begin_layout LyX-Code Static_Var_Name: sim_points_data \end_layout \begin_layout LyX-Code Description: "local static data" \end_layout \begin_layout LyX-Code Data_Type: pointer \end_layout \begin_layout Verbatim \end_layout \begin_layout Standard This device provides a model for two coupled microstrip lines. The connection circuit is the same as for the generic coupled lines. The substrate parameters are defined in a similar way as for microstrip line. This device provide the models for both frequency and time domain. The time-domain model is disabled by default and may be enabled by setting tranmodel=1 parameter. The line model and dispersion model codes are the same as for microstrip line (see the tables \begin_inset CommandInset ref LatexCommand ref reference "tab:msline_model" plural "false" caps "false" noprefix "false" nolink "false" \end_inset and \begin_inset CommandInset ref LatexCommand ref reference "tab:dispersion" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ). Here is an example of SPICE entry for coupled microstrips: \end_layout \begin_layout LyX-Code A1 %hd(p1 0) %hd(p2 0) %hd(p3 0) %hd(p4 0) \end_layout \begin_layout LyX-Code + %vd(p1 0) %vd(p2 0) %vd(p3 0) %vd(p4 0) CPMLIN1 \end_layout \begin_layout LyX-Code .MODEL CPMLIN1 CPMLIN(w=1e-3 l=20e-3 s=0.3e-3 er=9.8 h=1e-3 \end_layout \begin_layout LyX-Code + t=35e-6 tand=1e-3 rho=0.022e-6 d=0.15e-6 model=0 disp=0) \end_layout \begin_layout Verbatim \end_layout \begin_layout Subsection Microstrip open end \end_layout \begin_layout Verbatim \end_layout \begin_layout LyX-Code NAME_TABLE: \end_layout \begin_layout LyX-Code Spice_Model_Name: msopen \end_layout \begin_layout LyX-Code C_Function_Name: cm_msopen \end_layout \begin_layout LyX-Code Description: "Microstrip open end" \end_layout \begin_layout LyX-Code PORT_TABLE: \end_layout \begin_layout LyX-Code Port_Name: p1 \end_layout \begin_layout LyX-Code Description: "terminals" \end_layout \begin_layout LyX-Code Direction: inout \end_layout \begin_layout LyX-Code Default_Type: gd \end_layout \begin_layout LyX-Code Allowed_Types: [gd] \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: no \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: w \end_layout \begin_layout LyX-Code Description: "width (m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1e-3 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: model \end_layout \begin_layout LyX-Code Description: "Model type" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: disp \end_layout \begin_layout LyX-Code Description: "Dispersion type" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: msopen_model \end_layout \begin_layout LyX-Code Description: "MSOpen model" \end_layout \begin_layout LyX-Code Data_Type: int \end_layout \begin_layout LyX-Code Default_Value: 0 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: er \end_layout \begin_layout LyX-Code Description: "Substrate dielectric permittivity" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 9.8 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: h \end_layout \begin_layout LyX-Code Description: "Substrate thickness (m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 1e-3 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: t \end_layout \begin_layout LyX-Code Description: "Metal strip thickness (m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 35e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: tand \end_layout \begin_layout LyX-Code Description: "Substrate dielectric loss" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 2e-4 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: rho \end_layout \begin_layout LyX-Code Description: "Metal resistance (Ohm*m)" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.022e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout LyX-Code PARAMETER_TABLE: \end_layout \begin_layout LyX-Code Parameter_Name: d \end_layout \begin_layout LyX-Code Description: "RMS Substrate roughness" \end_layout \begin_layout LyX-Code Data_Type: real \end_layout \begin_layout LyX-Code Default_Value: 0.15e-6 \end_layout \begin_layout LyX-Code Limits: - \end_layout \begin_layout LyX-Code Vector: no \end_layout \begin_layout LyX-Code Vector_Bounds: - \end_layout \begin_layout LyX-Code Null_Allowed: yes \end_layout \begin_layout Verbatim \end_layout \begin_layout Standard This device represents microstrip open end. It provides only an AC domain model. It acts as an open circuit for DC and transient. The substrate parameters, model, and dispersion are defined in a same way as for microstrip device. Here is an example of the SPICE netlist entry for this device. \end_layout \begin_layout LyX-Code A1 %gd(1 0) MODEL_MS \end_layout \begin_layout LyX-Code .MODEL MODEL_MS MSOPEN(w=117.6u model=0 disp=0 msopen_model=0 \end_layout \begin_layout LyX-Code + er=9.8 h=1m t=12.5u tand=0 rho=1E-10 d=0) \end_layout \begin_layout Section Predefined Node Types for event driven simulation \end_layout \begin_layout Standard The following predefined node types are included with the XSPICE simulator. These should provide you not only with valuable event-driven modeling capabilities, but also with examples to use for guidance in creating new UDN (user defined node) types. You may access these node data by the \family typewriter plot \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Plot:-Plot-values" nolink "false" \end_inset ) or \family typewriter eprint \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Eprint*:-Print-an" nolink "false" \end_inset ) commands. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Digital-Node-Type" \end_inset Digital Node Type \end_layout \begin_layout Standard The `digital' node type is directly built into the simulator. 12 digital node values are available. They are described by a two character string (the state/strength token). The first character (0, 1, or U) gives the state of the node (logic zero, logic one, or unknown logic state). The second character (s, r, z, u) gives the "strength" of the logic state (strong, resistive, hi-impedance, or undetermined). So these are the values we have: 0s, 1s, Us, 0r, 1r, Ur, 0z, 1z, Uz, 0u, 1u, Uu. \end_layout \begin_layout Subsection Real Node Type \end_layout \begin_layout Standard The `real' node type provides for event-driven simulation with double-precision floating point data. This type is useful for evaluating sampled-data filters and systems. The type implements all optional functions for User-Defined Nodes, including inversion and node resolution. For inversion, the sign of the value is reversed. For node resolution, the resultant value at a node is the sum of all values output to that node. The node is implemented as a user defined node in \family sans ngspice/src/xspice/icm/xtraevt/real \family default . \end_layout \begin_layout Subsection Int Node Type \end_layout \begin_layout Standard The `int' node type provides for event-driven simulation with integer data. This type is useful for evaluating round-off error effects in sampled-data systems. The type implements all optional functions for User-Defined Nodes, including inversion and node resolution. For inversion, the sign of the integer value is reversed. For node resolution, the resultant value at a node is the sum of all values output to that node. The node is implemented as a user defined node in \family sans ngspice/src/xspice/icm/xtraevt/int \family default . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:(Digital)-Input/Output" \end_inset (Digital) Input/Output \end_layout \begin_layout Standard The analog code models use the standard (analog) nodes provided by ngspice and thus are using all the commands for sourcing, storing, printing, and plotting data. \end_layout \begin_layout Standard I/O for event nodes (digital, real, int, and UDNs) is offered by the following tools: For output you may use the \family typewriter plot \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Plot:-Plot-values" nolink "false" \end_inset ) or \family typewriter eprint \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Eprint*:-Print-an" nolink "false" \end_inset ) commands, as well as \family typewriter edisplay \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Edisplay*" nolink "false" \end_inset ) and \family typewriter eprvcd \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Eprvcd*-1" nolink "false" \end_inset ). The latter writes all node data to a \begin_inset CommandInset href LatexCommand href name "VCD" target "http://en.wikipedia.org/wiki/Value_change_dump" literal "false" \end_inset file (a digital standard interface) that may be analyzed by viewers like \begin_inset CommandInset href LatexCommand href name "gtkwave" target "http://gtkwave.sourceforge.net/" literal "false" \end_inset . For input, you may create a test bench with existing code models (oscillator ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Controlled-Digital-Oscillator" nolink "false" \end_inset ), frequency divider ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Frequency-Divider" nolink "false" \end_inset ), state machine ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:State-Machine" nolink "false" \end_inset ) etc.). Reading data from a file is offered by d_source ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Digital-Source" nolink "false" \end_inset ). Some \begin_inset CommandInset href LatexCommand href name "comments and hints" target "https://sourceforge.net/p/ngspice/discussion/ngspice-tips/thread/3e193172/" literal "false" \end_inset have been provided by Sdaau. You may also use the analog input from file, (filesource \begin_inset CommandInset ref LatexCommand ref reference "subsec:Filesource" nolink "false" \end_inset ) and convert its analog input to the digital type by the \family typewriter adc_bridge \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Analog-to-Digital-Node-Bridge" nolink "false" \end_inset ). If you want reading data from a \begin_inset CommandInset href LatexCommand href name "VCD" target "http://en.wikipedia.org/wiki/Value_change_dump" literal "false" \end_inset file, please have a look at \begin_inset CommandInset href LatexCommand href name "ngspice tips and examples forum" target "https://sourceforge.net/p/ngspice/discussion/ngspice-tips/thread/635bb14a/" literal "false" \end_inset and apply a python script provided by Sdaau to translate the VCD data to d_source or filesource input. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Automatic insertion of bridging devices" \end_inset Automatic insertion of bridging devices \end_layout \begin_layout Standard Within ngspice, event nodes such as digital are quite different objects to analog nodes, but in real circuits analog and digital devices may interconnect. Ngspice requires bridging devices to interconnect its analog and digital domains. \end_layout \begin_layout Standard Bridges are inserted automatically whenever an analog and a digital node have the same name, so they are not required to be included in the netlist. To examine the inserted bridging devices, use the command \begin_inset Quotes eld \end_inset \family typewriter listing e \family default \begin_inset Quotes erd \end_inset . The extra devices appear at the end of the netlist. Automatic bridging may be disabled by setting the interpreter variable \family typewriter auto_bridge \family default to zero. \end_layout \begin_layout Standard The code models used for analog/digital bridges are described in section \begin_inset CommandInset ref LatexCommand ref reference "sec:Hybrid-Models" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . The default models are: \end_layout \begin_layout LyX-Code * Model for bridging digital node with inputs only. \end_layout \begin_layout LyX-Code .model auto_adc adc_bridge(in_low = 1.65 in_high = 1.65) \end_layout \begin_layout LyX-Code * Model for bridging digital node with outputs only. \end_layout \begin_layout LyX-Code .model auto_dac dac_bridge(out_low = 0 out_high = 3.3) \end_layout \begin_layout LyX-Code * Model for bridging digital node with either an inout connection or \end_layout \begin_layout LyX-Code * both inputs and outputs. \end_layout \begin_layout LyX-Code .model auto_bidi bidi_bridge(out_high=3.3 in_low=1.65 in_high=1.65) \end_layout \begin_layout Standard A 3.3 volt supply has been assumed. That may be overridden by setting a parameter, \family typewriter vcc \family default , to the supply voltage. When bridges are inserted in a subcircuit the local value of the parameter is used, so subcircuits may have differing supply voltages. An alternative name for the parameter may be set as the value of the interpreter variable \family typewriter auto_bridge_parm_d. \end_layout \begin_layout Standard If the defaults are unsatisfactory, they may be overridden by setting interpreter variables: \end_layout \begin_layout LyX-Code * Override the default DAC bridge for TTL levels \end_layout \begin_layout LyX-Code .control \end_layout \begin_layout LyX-Code pre_set auto_bridge_d_out = \end_layout \begin_layout LyX-Code + ( ".model auto_dac dac_bridge(out_low = 0.4 out_high = 3.6)" \end_layout \begin_layout LyX-Code + "auto_bridge%d [ %s ] [ %s ] auto_dac" ) \end_layout \begin_layout LyX-Code .endc \end_layout \begin_layout Standard The variable name is formed from a fixed part (auto_bridge_), the type of the event node (d is the internal name for "digital") and the bridging direction (in, out or inout). The first string is the model definition and the second is expanded into an instance of the bridging device. Note that the \family typewriter pre_set \family default command is used so that the variable is set before the circuit is parsed. \end_layout \begin_layout Standard Bridges may be defined by subcircuits as well as single devices: \end_layout \begin_layout LyX-Code pre_set auto_bridge_d_out = ( ".include test_sub.subcir" \end_layout \begin_layout LyX-Code + "xauto_buf%d %s %s auto_buf vcc=%g" \end_layout \begin_layout LyX-Code + 1 ) \end_layout \begin_layout Standard Here the constant "1" is required to specify that a separate instance of the subcircuit is needed for each bridged node. \end_layout \begin_layout Standard The included file might be: \end_layout \begin_layout LyX-Code * DAC with internal resistance. \end_layout \begin_layout LyX-Code .subckt auto_buf dig ana vcc=5 \end_layout \begin_layout LyX-Code .model auto_dac dac_bridge(out_low = 0 out_high = {vcc}) \end_layout \begin_layout LyX-Code auto_dac [ dig ] [ internal ] auto_dac \end_layout \begin_layout LyX-Code rint internal ana 100 \end_layout \begin_layout LyX-Code .ends \end_layout \begin_layout Standard An additional method for controlling automatic bridging is to set the parameter \emph on family \emph default on individual XSPICE devices or on subcircuits. When the parameter is found a specific interpreter variable is used to control bridges attached to the device, or as the default within the subcircuit. In this example all output bridges connected to or inside the subcircuit are specified. \end_layout \begin_layout LyX-Code Xmpx_gate in0 in1 in2 in3 sel1 sel0 out multiplexor \end_layout \begin_layout LyX-Code + family= \begin_inset Quotes erd \end_inset lsttl \begin_inset Quotes erd \end_inset \end_layout \begin_layout LyX-Code .control \end_layout \begin_layout LyX-Code pre_set auto_bridge_lsttl_d_out = \end_layout \begin_layout LyX-Code + ( ".model auto_dac dac_bridge(out_low = 0.2 out_high = 3.6)" \end_layout \begin_layout LyX-Code + "auto_bridge%d [ %s ] [ %s ] auto_dac" ) \end_layout \begin_layout LyX-Code .endc \end_layout \begin_layout Standard More details of controls on automatic bridging can found as a comment in the source file src/xspice/evt/evtcheck.c. Some examples of automatic bridging with various control options are included in the source directory examples/digital/auto_bridge. \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "chap:Verilog-A-Compact-Device" \end_inset Verilog-A \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Verilog-A device models \end_layout \end_inset Compact Device Models \end_layout \begin_layout Section Introduction \end_layout \begin_layout Standard New compact device models today are released as Verilog-A code, a analog subset of Verilog-AMS. Well-known examples are BSIMBULK, BSIMCMG, PSP, HiSIM or HICUM. The \begin_inset CommandInset href LatexCommand href name "Si2 CMC web page" target "https://si2.org/standard-models/" literal "false" \end_inset lists more than 20 device models which are publicly available. The models cover state-of-the-art MOS devices like SOI, FinFet, multi-gate and high voltage transistors, high speed SiGe bipolar transistors, HEMTs as well as complex diodes and resistors. ngspice makes all of these models available by its integrated \begin_inset CommandInset href LatexCommand href name "OSDI interface" target "https://semimod.de/projects/" literal "false" \end_inset and the \begin_inset CommandInset href LatexCommand href name "OpenVAF" target "https://openvaf.semimod.de/" literal "false" \end_inset compiler, which translates Verilog-A device models into dynamically loadable libraries. User-defined Verilog-A models may be compiled and loaded into ngspice as well. Currently Linux and MS Windows are supported, OSDI/OpenVAF for macOS is not yet available. We are thankful to \begin_inset CommandInset href LatexCommand href name "SemiMod GmbH" target "https://semimod.de" literal "false" \end_inset for these excellent contributions. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:OSDI/OpenVAF" \end_inset OSDI/OpenVAF \end_layout \begin_layout Standard OSDI is a simulator independent interface for device models. Since release 39 ngspice contains an integrated adapter to serve this interface and communicate with the compiled shared library device models. The shared library models are linked into ngspice dynamically at runtime with the \family typewriter osdi \family default or \family typewriter pre_osdi \family default (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Pre_ODSI:-load-a" nolink "false" \end_inset ) .control language commands. \end_layout \begin_layout Standard OpenVAF compiles Verilog-A compact device model files into shared libraries that conform to the OSDI interface. The model descriptions have to comply with the standard \begin_inset CommandInset href LatexCommand href name "Verilog-AMS LRM 2.x" target "https://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf" literal "false" \end_inset . Since ngspice-42, the small signal noise simulation ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.NOISE:-Noise-Analysis" nolink "false" \end_inset ) is implemented. Noise simulation , however, is only available with the Sparse 1.3 matrix solver, not with KLU (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:General-Options" nolink "false" \end_inset ). Other restrictions may apply. Please consult the \begin_inset CommandInset href LatexCommand href name "OpenVAF web pages" target "https://openvaf.semimod.de/" literal "false" \end_inset for further information. QA actions are not possible due to CMC refusing to provide data. \end_layout \begin_layout Section How to create and apply OpenVAF models \end_layout \begin_layout Subsection Preparing for simulation \end_layout \begin_layout Standard Using Verilog-A models for simulation in ngspice consists of five steps: Obtain or compile ngspice with OSDI interface, compile the VA-model with OpenVAF, prepare a suitable model parameter set, load the compiled model into ngspice ... and start the simulation. \end_layout \begin_layout Subsubsection Obtaining OpenVAF \end_layout \begin_layout Standard OpenVAF may be downloaded for MS Windows or Linux as a single executable each from \begin_inset CommandInset href LatexCommand href name "https://openvaf.semimod.de/download/" target "https://openvaf.semimod.de/download/" literal "false" \end_inset , and copied into a user defined directory. Compiling OpenVAF yourself is possible, however is not recommended due to its complicated procedure. \end_layout \begin_layout Subsubsection Verilog-A compact models \end_layout \begin_layout Standard Verilog-A compact device models are available from the \begin_inset CommandInset href LatexCommand href name "si2 CMC standard compact model page" target "https://si2.org/standard-models/" literal "false" \end_inset or directly from device modelling web sites, e.g. \begin_inset CommandInset href LatexCommand href name "BSIM from UC Berkeley" target "https://bsim.berkeley.edu/models/" literal "false" \end_inset , \begin_inset CommandInset href LatexCommand href name "HiSIM from Hiroshima University" target "https://www.hisim.hiroshima-u.ac.jp/index.php?id=87" literal "false" \end_inset , \begin_inset CommandInset href LatexCommand href name "PSP from CEA-Leti" target "https://www.cea.fr/cea-tech/leti/pspsupport/Pages/Welcome.aspx" literal "false" \end_inset , or \begin_inset CommandInset href LatexCommand href name "HICUM from TU Dresden" target "https://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.html" literal "false" \end_inset . Others are available. User provided or user defined models may be compiled as well. All models have to comply to the \begin_inset CommandInset href LatexCommand href name " LRM 2.x standard" target "https://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf" literal "false" \end_inset of Verilog-AMS. Not all publicly availables models do comply (e.g. PSP102, EKV2.6). \end_layout \begin_layout Standard There is a github repository \begin_inset CommandInset href LatexCommand href name "VA-Models" target "https://github.com/dwarning/VA-Models" literal "false" \end_inset with most of the public available Verilog-A compact models. The models are checked against the LRM 2.4.0 and prepared for ngspice simulation. A script for generation of the osdi files is provided and each model has more or less simple ngspice netlist files to show main capabilities. So this web site should be a good starting point for beginners. \end_layout \begin_layout Subsubsection Prepare ngspice \end_layout \begin_layout Standard Compile ngspice with the configure flag \family typewriter –enable-osdi \family default to add the OSDI interface to ngspice. The MSVC Windows version \family typewriter ngspice.exe \family default from the distribution already contains this interface. \end_layout \begin_layout Subsubsection \begin_inset CommandInset label LatexCommand label name "subsec:Compile-the-models" \end_inset Compile the models \end_layout \begin_layout Standard A very basic approach is to put the \family typewriter openvaf \family default executable and the Verilog-A model (e.g. \family typewriter bsimbulk.va \family default ) into a directory, then from a console window cd into that directory and call the command \family typewriter openvaf bsimbulk.va \family default . After a few seconds the compiled shared library \family typewriter bsimbulk.osdi \family default becomes available, ready to be loaded into ngspice. \end_layout \begin_layout Standard Where to place \family typewriter *.osdi \family default ? Basically in any directory of your choice, the \family typewriter osdi \family default or \family typewriter pre-osdi \family default commands ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Prepare-the-ngspice" nolink "false" \end_inset ) may be prepended by an absolute or relative path to that directory. For a permanent location a bulk model install to \family typewriter libs/ngspice \family default is recommended (to the folder where you also find the XSPICE code model libs \family typewriter *.cm \family default ). An easy way that ngspice can find the compiled and linked shared library files ( \family typewriter *.osdi \family default ) is to use the environment variable NGSPICE_OSDI_DIR, e.g. in Linux export NGSPICE_OSDI_DIR="$HOME/Verilog-A/VA-Models/osdilibs". \end_layout \begin_layout Standard \family typewriter openvaf --help \family default yields more options of the compiler. \end_layout \begin_layout Standard To simplify making suitable *.osdi models for the example netlists provided in ngspice/examples/osdi, the appropriate Verilog-A models and short scripts (for Linux and Windows) are available for download as \begin_inset CommandInset href LatexCommand href name "VAforOSDI.7z" target "https://sourceforge.net/projects/ngspice/files/ng-spice-rework/39/VAforOSDI.7z" literal "false" \end_inset from our release directory. The following steps are required to compile the shared library models: \end_layout \begin_layout Itemize Expand VAforOSDI.7z into a directory of your choice. \end_layout \begin_layout Itemize Download \begin_inset CommandInset href LatexCommand href name "OpenVAF" target "https://openvaf.semimod.de/download/" literal "false" \end_inset (Linux or Windows) from and place the executable here in this directory. \end_layout \begin_layout Itemize Run the script \family typewriter openvaf-compile-va.bat \family default for MS Windows or \family typewriter openvaf-compile-va.sh \family default for Linux \end_layout \begin_layout Itemize Copy the \family typewriter *.osdi \family default files from directory \family typewriter osdilibs \family default to the place where then code models ( \family typewriter *.cm \family default ) are located, typically in \family typewriter lib/ngspice \family default or similar. \end_layout \begin_layout Itemize Edit file ' \family typewriter spinit \family default ', typically found in \family typewriter share/ngspice/scripts \family default : Comment out the line ' \family typewriter unset osdi_enabled \family default ' \end_layout \begin_layout Subsubsection Prepare the model parameters \end_layout \begin_layout Standard According to chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Device-Models" nolink "false" \end_inset the model parameter set for each device model is organized in a \family typewriter .model \family default line. This is valid for OSDI models as well. However here the model type takes the role to distinguish models from each other, not the \family typewriter level \family default or \family typewriter version \family default parameters found in the intrinsic models. A \family typewriter TYPE \family default parameter determines, if NMOS ( \family typewriter TYPE=1 \family default ) or PMOS ( \family typewriter TYPE=-1 \family default ), NPN ( \family typewriter TYPE=1 \family default ) or PNP ( \family typewriter TYPE=-1 \family default ) are selected. \end_layout \begin_layout Standard Consider as an example the bsimbulk model. The \family typewriter modeltype \family default is set by the \end_layout \begin_layout LyX-Code module bsimbulk(d, g, s, b, t); \end_layout \begin_layout Standard line of the BSIMBULK.va Verilog-A model file. So one has to search for the module name in the *.va file to obtain the \family typewriter modeltype \family default for the .model line and the number of nodes (and their meanings) for the instance (or device) line while creating the netlist (see next chapter \begin_inset CommandInset ref LatexCommand ref reference "subsec:Prepare-the-ngspice" nolink "false" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .model mname modeltype(pname1=pval1 pname2=pval2 ... ) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .model BSIMBULK_osdi_N bsimbulk TYPE=1 GEOMOD=0 RGEOMOD=0 ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard So to prepare the .model line, select an appropriate model parameter set, comment out the \family typewriter version \family default and \family typewriter level \family default parameters, add the \family typewriter type \family default parameter, and change the \family typewriter modeltype \family default to the Verilog-A module name. \end_layout \begin_layout Subsubsection \begin_inset CommandInset label LatexCommand label name "subsec:Prepare-the-ngspice" \end_inset Prepare the ngspice netlist \end_layout \begin_layout Standard The compiled model, e.g. \family typewriter bsimbulk.osdi \family default , has to be loaded into ngspice. This may occur automatically during start-up of ngspice, if the installation has been prepared according to the bulk model install (compiled *.osdi models in lib/ngspice, osdi commands added to spinit). \end_layout \begin_layout Standard Local usage of a *.osdi which are residing in an arbitrary directory is possible from within a .control section ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Interactive-mode-with" nolink "false" \end_inset ) by the \family typewriter pre_osdi \family default command. A relative path (as in the example below) or an absolute path to that directory may be chosen. \end_layout \begin_layout LyX-Code pre_osdi ../osdi_libs/bsimbulk107.osdi \end_layout \begin_layout Standard The reference designator for the OSDI devices is the letter N. Instance lines starting with N are recognized as OSDI devices. The model name mname has to point to the .model line which contains the parameter set to be selected. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Instance line, general form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Ndevname node1 ... nodex mname pname1=pval1 pname2=pval2 ... \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Np1 z a vdd vdd BSIMBULK_osdi_P l=0.1u w=1u \end_layout \begin_layout Plain Layout + as=0.26235p ad=0.26235p ps=2.51u pd=2.51u \end_layout \begin_layout Plain Layout Nn1 z a vss vss BSIMBULK_osdi_N l=0.1u w=0.5u \end_layout \begin_layout Plain Layout + as=0.131175p ad=0.131175p ps=1.52u pd=1.52u \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard NMOS and PMOS devices are selected by their respective model names \family typewriter BSIMBULK_osdi_N \family default and \family typewriter BSIMBULK_osdi_P \family default . The number and role of the nodes has been defined in the VA code in its module statement ( \family typewriter module bsimbulk(d, g, s, b, t); \family default in the BSIMBULK example). Instance parameters (like l, w, as etc.) are allowed, as defined by the VA code. \end_layout \begin_layout Subsubsection Run the simulation \end_layout \begin_layout Standard The simulation may be run as usual. Batch mode is especially supported when the OSDI libraries are loaded via spinit during ngspice start-up. \end_layout \begin_layout Subsection OSDI/OpenVAF examples distributed with ngspice \end_layout \begin_layout Standard Several example input netlists are available in folder \family typewriter ngspice/examples/osdi \family default . All (except for \family typewriter bsimbulk-local \family default ) make use of the \family typewriter *.osdi \family default installation as a bulk model install in a folder pointed to by \family typewriter spinit \family default . \family typewriter bsimbulk-local \family default however requires a local copy of \family typewriter bsimbulk.osdi \family default into folder \family typewriter bsimbulk-local/osdi_libs \family default . \end_layout \begin_layout Standard Example folders \family typewriter bsimbulk \family default , \family typewriter bsimbulk-local \family default , \family typewriter bsimcmg \family default , \family typewriter mixed-models \family default , and \family typewriter psp103 \family default contain MOS devices with their dc characteristics, CMOS inverters, CMOS ring oscillators, or even the 7552_ann benchmark CMOS circuit with 15.000 transistors and may more passives. \family typewriter Hicuml0 \family default , or \family typewriter mextram \family default contain bipolar devices with output characteristics, Gummel-plot and some circuits. \family typewriter r2_cmc \family default is a special resistor model. \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "chap:Digital-Device-Models" \end_inset Digital Device Models \end_layout \begin_layout Section U devices (basic digital building blocks) \end_layout \begin_layout Standard If PS compatibility mode is set, ngspice supports .subckt statements which contain entirely U* instances of digital gates, flip-flops, latches, LOGICEXP and PINDLY behavioral primitives (see chapter \begin_inset CommandInset ref LatexCommand ref reference "subsec:List-of-devices" nolink "false" \end_inset for the list), and timing models. Typical rise/fall delays are estimated from the timing models and PINDLY statements. CONSTRAINT primitives and io models are ignored. Other U* instances (such as RAM, ROM, STIM and PLAs) in a .subckt are not supported, and such .subckt will not be converted to XSPICE digital primitives. \end_layout \begin_layout Standard These U devices are not meant to immediately describe digital circuits like the 74xx or 40xx series. However they are used in subcircuits to generate models for such circuits (see chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Support-for-standard" nolink "false" \end_inset ). Their syntax is mostly compatible to the Micro-Cap and PSPICE simulators. \end_layout \begin_layout Subsection General format \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout U [(*)] \end_layout \begin_layout Plain Layout + * \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout +[MNTYMXDLY=] \end_layout \begin_layout Plain Layout +[IO_LEVEL=] \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout U2 AND(2) $G_DPWR $G_DGND 4 5 6 \end_layout \begin_layout Plain Layout + M2 IOM2 IO_LEVEL=0 MNTYMXDLY=2 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .MODEL M2 UGATE () \end_layout \begin_layout Plain Layout .MODEL IOM2 UIO (INLD=0 OUTLD=0 DRVH=50 DRVL=50 \end_layout \begin_layout Plain Layout + ATOD1="ATOD1" DTOA1="DTOD1" ATOD2="ATOD2" DTOA2="DTOD2" \end_layout \begin_layout Plain Layout + ATOD3="ATOD3" DTOA3="DTOD3" ATOD4="ATOD4" DTOA4="DTOD4" \end_layout \begin_layout Plain Layout + TSWLH1=0 TSWLH2=0 TSWLH3=0 TSWLH4=0 \end_layout \begin_layout Plain Layout + TSWHL1=0 TSWHL2=0 TSWHL3=0 TSWHL4=0 DIGPOWER="DIGPOWER") \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:List-of-devices" \end_inset List of devices available in ngspice (basic types) \end_layout \begin_layout LyX-Code Standard gates: \end_layout \begin_layout LyX-Code BUF buffer \end_layout \begin_layout LyX-Code INV inverter \end_layout \begin_layout LyX-Code AND AND gate \end_layout \begin_layout LyX-Code NAND NAND gate \end_layout \begin_layout LyX-Code OR OR gate \end_layout \begin_layout LyX-Code NOR NOR gate \end_layout \begin_layout LyX-Code XOR exclusive OR gate \end_layout \begin_layout LyX-Code NXOR exclusive NOR gate \end_layout \begin_layout LyX-Code BUFA buffer array \end_layout \begin_layout LyX-Code INVA inverter array \end_layout \begin_layout LyX-Code ANDA AND gate array \end_layout \begin_layout LyX-Code NANDA NAND gate array \end_layout \begin_layout LyX-Code ORA OR gate array \end_layout \begin_layout LyX-Code NORA NOR gate array \end_layout \begin_layout LyX-Code XORA exclusive OR gate array \end_layout \begin_layout LyX-Code NXORA exclusive NOR gate array \end_layout \begin_layout LyX-Code AO AND-OR compound gate \end_layout \begin_layout LyX-Code OA OR-AND compound gate \end_layout \begin_layout LyX-Code AOI AND-NOR compound gate \end_layout \begin_layout LyX-Code OAI OR-NAND compound gate \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Tristate gates: \end_layout \begin_layout LyX-Code BUF3 buffer \end_layout \begin_layout LyX-Code INV3 inverter \end_layout \begin_layout LyX-Code AND3 AND gate \end_layout \begin_layout LyX-Code NAND3 NAND gate \end_layout \begin_layout LyX-Code OR3 OR gate \end_layout \begin_layout LyX-Code NOR3 NOR gate \end_layout \begin_layout LyX-Code XOR3 exclusive OR gate \end_layout \begin_layout LyX-Code NXOR3 exclusive NOR gate \end_layout \begin_layout LyX-Code BUF3A buffer array \end_layout \begin_layout LyX-Code INV3A inverter array \end_layout \begin_layout LyX-Code AND3A AND gate array \end_layout \begin_layout LyX-Code NAND3A NAND gate array \end_layout \begin_layout LyX-Code OR3A OR gate array \end_layout \begin_layout LyX-Code NOR3A NOR gate array \end_layout \begin_layout LyX-Code XOR3A exclusive OR gate array \end_layout \begin_layout LyX-Code NXOR3A exclusive NOR gate array \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Flip-flops and latches: \end_layout \begin_layout LyX-Code DFF D-type flip-flop, positive-edge triggered \end_layout \begin_layout LyX-Code JKFF J-K flip-flop, negative-edge triggered \end_layout \begin_layout LyX-Code DLTCH D-type latch \end_layout \begin_layout LyX-Code SRFF S-R flip-flop \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Delay lines: \end_layout \begin_layout LyX-Code DLYLINE Delay line \end_layout \begin_layout LyX-Code \end_layout \begin_layout LyX-Code Behavioral primitives: \end_layout \begin_layout LyX-Code LOGICEXP Combinational logic expressions \end_layout \begin_layout LyX-Code PINDLY Output buffers and tristate buffers with estimated delays \end_layout \begin_layout LyX-Code \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:URC-transmission-line" \end_inset URC transmission line versus U devices \end_layout \begin_layout Standard For the first time ngspice may have a naming conflict, in that the reference designator U is used for two different devices, the Uniformly distributet RC line and the U devices, our digital basic types or primitives. \end_layout \begin_layout Labeling \labelwidthstring 00.00.0000 \series bold U-devices \series default require the compatibility mode flag ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode" nolink "false" \end_inset ) set to \family typewriter PS \family default . In addition U devices are recognized only when they occur inside of a subcircuit. Finally the basic type (second token in the U instance line) has to fit to the list of basic types given in the table above. \end_layout \begin_layout Labeling \labelwidthstring 00.00.0000 \series bold URC \series default in any other case ngspice will assume an URC (uniformly distributed) transmission line. \end_layout \begin_layout LyX-Code \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Support-for-standard" \end_inset Support for standard digital devices \end_layout \begin_layout Standard The digital primitives (U devices) are the basic building blocks of the models for digital ICs used in ngspice. An example of a simple subcircuit model for a And Gate is listed below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: 74LV08A Quad 2-Input And Gate \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * ------------------------- 74LV08A ------ \end_layout \begin_layout Plain Layout * Quad 2-Input And Gate \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout * TI PDF File \end_layout \begin_layout Plain Layout * bss 2/21/03 \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .SUBCKT 74LV08A 1A 1B 1Y \end_layout \begin_layout Plain Layout + optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V \end_layout \begin_layout Plain Layout + params: MNTYMXDLY=0 IO_LEVEL=0 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout U1 and(2) DPWR_3V DGND_3V \end_layout \begin_layout Plain Layout + 1A 1B 1Y \end_layout \begin_layout Plain Layout + DLY_LV08 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .model DLY_LV08 ugate \end_layout \begin_layout Plain Layout + (tplhTY=7.5ns tplhMX=12.3ns tphlTY=7.5ns tphlMX=12.3ns) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .ENDS 74LV08A \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The circuit example \family typewriter ex4.cir \family default in \begin_inset CommandInset href LatexCommand href name "ngspice/examples/digital/digital_devices" target "https://sourceforge.net/p/ngspice/ngspice/ci/master/tree/examples/digital/digital_devices" literal "false" \end_inset , together with the stimulus file \family typewriter ex4.stim \family default presents a fully digital, event based full-adder simulation with 74xx series ICs. The internal plotting capability of ngspice is used. \family typewriter ex5.cir \family default with the stimulus file \family typewriter ex5.stim \family default demonstrates the conversion of a D-Type Flip-Flop. \family typewriter ex283.cir \family default is a 74283 4-bit full adder, with stimulus and involving \begin_inset CommandInset href LatexCommand href name "GTKWave" target "https://gtkwave.sourceforge.net/" literal "false" \end_inset for plotting. Also, there are several new examples illustrating LOGICEXP and PINDLY. \end_layout \begin_layout Standard A set of such models for the 74xx devices currently supported by ngspice is available from the \begin_inset CommandInset href LatexCommand href name "ngspice models" target "https://ngspice.sourceforge.io/modelparams.html" literal "false" \end_inset as \begin_inset CommandInset href LatexCommand href name "74xx-models.7z" target "https://ngspice.sourceforge.io/model-parameters/74xx-models.7z" literal "false" \end_inset , derived from the Micro-Cap library. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:digital-devices-HDL" \end_inset Digital devices defined by a Hardware Description Language \end_layout \begin_layout Standard Ngspice can make a digital device from a description in a Hardware Description Language, such as Verilog or VHDL. There are several ways that can be done, including running the HDL code in a separate process, or compiling directly to a partial netlist. The current Ngspice source code and binary packages also have support for three more direct methods: HDL files may be compiled by either \begin_inset CommandInset href LatexCommand href name "Verilator" target "https://www.veripool.org/verilator/" literal "false" \end_inset , \begin_inset CommandInset href LatexCommand href name "Icarus Verilog" target "https://steveicarus.github.io/iverilog/" literal "false" \end_inset or \begin_inset CommandInset href LatexCommand href name "GHDL" target "http://ghdl.free.fr/" literal "false" \end_inset and the output file may be loaded into an instance of the d_cosim XSPICE code model ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:d_cosim" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ). (Warning: using multiple d_cosim instances in a circuit requires careful planning.) \end_layout \begin_layout Standard The steps for using such a digital device are these: write HDL code whose top-level module defines the device behaviour; the HDL file is compiled into a form acceptable by d_cosim; and the netlist contains device and model lines to include the new device in a circuit. A circuit of this type can only be used for a single simulation before process exit, as previous HDL simulation state may not be cleared, even by \family typewriter remcirc \family default . \end_layout \begin_layout Standard Another method is to wrap the analog simulation in a dummy HDL module, implemented by Ngspice's shared library, and allow the HDL simulator to control the combined simulation. That method is used \begin_inset CommandInset href LatexCommand href name "here" target "https://github.com/themperek/spicebind" literal "false" \end_inset and, with additional testbench support, \begin_inset CommandInset href LatexCommand href name "here" target "https://vlsida.github.io/cocotbext-ams/" literal "false" \end_inset . \end_layout \begin_layout Subsection Using \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Verilog digital modules \end_layout \end_inset Verilator, Verilog, and code model d_cosim \end_layout \begin_layout Standard When using Verilator, version 4.210 or later is required. The compilation step is not straightforward, as \begin_inset Quotes eld \end_inset glue code \begin_inset Quotes erd \end_inset must be added to the C++ software created by Verilator's compiler so that it can be attached to a d_cosim instance. A script is provided to make this step easier: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ngspice vlnggen source.v \end_layout \end_inset \end_layout \begin_layout Standard Ngspice is used to run the script vlnggen, passing the Verilog source file, source.v, as input. The script analyses C++ code output from Verilator and creates additional code to describe the ports of the top-level module. Then all the generated code is compiled. The output will be a shared library/DLL called source.so/source.DLL that may be used in the netlist as: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ahdldevice [ inputs ... ] [ outputs ... ]dmod \end_layout \begin_layout Plain Layout .model dmod d_cosim simulation= \begin_inset Quotes erd \end_inset some/path/source \begin_inset Quotes erd \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Formally, a third list of nodes may be included in the device instance line. If present, they are matched against inout ports of the top-level Verilog module. But Verilator does not fully support inout ports. \end_layout \begin_layout Standard Additional arguments to vlnggen may be other HDL source files or options: everything is passed to Verilator. To pass options to Verilator, insert \begin_inset Quotes eld \end_inset -- \begin_inset Quotes erd \end_inset before them to mark the end of ngspice options. Verilator's \begin_inset Quotes eld \end_inset --timing \begin_inset Quotes erd \end_inset option must be passed this way if delays are used in the Verilog source, so to use time delays in the Verilog source the command may be: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ngspice vlnggen -- --timing pwm.v \end_layout \end_inset \end_layout \begin_layout Standard The output file is named from the first Verilog source file (*.v) that is listed, or is \begin_inset Quotes eld \end_inset verilated.so \begin_inset Quotes erd \end_inset / \begin_inset Quotes erd \end_inset verilated.DLL \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Standard For each port type the connected event nodes are assigned to bits of the Verilog ports from left to right, treating ports with multiple bits as big-endian: more significant bits are matched first. If the number of bits of each port type do not match, a warning is issued and extra input or output bits will be matched with any excess inout bits, in either direction. \end_layout \begin_layout Standard Example netlist and Verilog code can be found at examples/xspice/verilator, with instructions in README.txt. \end_layout \begin_layout Subsection Using Icarus Verilog, and code model d_cosim \end_layout \begin_layout Standard Icarus Verilog handles a larger subset of the full SystemVerilog specification than Verilator and compiles primarily into interpereted code. Ngspice includes components to run the interpreter, VVP, inside an instance of the d_cosim code model. To use this feature, Verilog code is compiled as usual for Icarus Verilog: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout iverilog -o adc adc.v \end_layout \end_inset \end_layout \begin_layout Standard The output file is in a form that can be executed directly on Unix-like systems or by VVP.EXE on Windows. It may also be included in a co-simulation with Ngspice by including netlist lines like: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout aivldevice [ inputs ... ] [ outputs ... ][ inouts ... ]dmod \end_layout \begin_layout Plain Layout .model dmod d_cosim simulation= \begin_inset Quotes erd \end_inset ivlng \begin_inset Quotes erd \end_inset sim_args=[ \begin_inset Quotes eld \end_inset adc \begin_inset Quotes erd \end_inset ] \end_layout \end_inset \end_layout \begin_layout Standard Here, ports of the top-level Verilog module are matched to ngspice nodes as for Verilator. Additional string values for the sim_args parameter will be passed to the Verilog simulation as though included in a command line. \end_layout \begin_layout Standard The timescale should always be set in Verilog source, even if no delays are used. The reason is that even without delays, VVP seems to schedule output to the next internal clock tick, and SPICE and Verilog times are bound as tight as possible. The precision should be small compared to the expected transient simulation step. \end_layout \begin_layout Standard While the user's setup for co-simulation with Icarus Verilog should be simple, the underlying mechanism is somewhat elaborate. In addition to the d_cosim code model that is included in ngspice's digital.cm dynamic library, three more dynamic libraries are loaded: ivlng.so/.DLL is specified by d_cosim's \begin_inset Quotes eld \end_inset simulation \begin_inset Quotes erd \end_inset parameter; it loads libvvp.so/.DLL, the dynamic library version of Icarus Verilog's simulation engine; and that in turn loads ivlng.vpi, a Verilog VPI module. Additionally, libvvp loads the compiled Verilog code, here the file \begin_inset Quotes eld \end_inset adc \begin_inset Quotes erd \end_inset . The files for ivlng.so/.DLL and ivlng.vpi are built and installed with ngspice. For libvvp to be available, Icarus Verilog must be configured with \begin_inset Quotes eld \end_inset –enable-libvvp \begin_inset Quotes erd \end_inset before building. \end_layout \begin_layout Standard NOTE: At the time of writing, libvvp is not included in standard binary builds, and Icarus Verilog may need to be built from source. Version 13 or later should be used. Suitable binary builds may be found at \begin_inset CommandInset href LatexCommand href target "https://github.com/gatk555/ngspice-builds/actions" literal "true" \end_inset (login required). \end_layout \begin_layout Standard In case of problems, relative or absolute paths to all components can be set as parameters. The lib_args parameter of d_cosim can be used to set: path to libvvp.so/.DLL; path to ivlng.vpi; and the path to a VVP log file. Note that null strings are ignored, so if libvvp is on the standard dynamic library search path (as it should be), it may be specified as \begin_inset Quotes eld \end_inset libvvp \begin_inset Quotes erd \end_inset , but must be set. \end_layout \begin_layout Standard Example netlists can be found at examples/xspice/icarus_verilog, with instructions in README.txt. The Verilog code is shared with the Verilator examples. \end_layout \begin_layout Subsection Using GHDL and code model d_cosim. \end_layout \begin_layout Standard The open source compiler GHDL translates VHDL source into binary programs or shared libraries. For use with d_cosim a shared library is generated, using the LLVM back end. (Other GHDL back-ends may work, but have not been tested). To use this method, both an LLVM-based build of GHDL and the C compiler, Clang, should be installed. GHDL Version 6, or later, is required. Suitable GHDL binaries can be found on \begin_inset CommandInset href LatexCommand href name "GHDL's development site." target "https://github.com/ghdl/ghdl/" literal "false" \end_inset (A Github login is required for downloading.) \end_layout \begin_layout Standard To prepare VHDL source for co-simulation, it must be processed by \begin_inset Quotes eld \end_inset \family typewriter ghdl -a \family default \begin_inset Quotes erd \end_inset (analysis) and combined with compiled source from ghdl_shim.c, a file included with ngspice. Then the code must be \begin_inset Quotes eld \end_inset elaborated \begin_inset Quotes erd \end_inset by \begin_inset Quotes eld \end_inset \family typewriter ghdl -e \family default \begin_inset Quotes erd \end_inset to produce a module that d_cosim can load. In addition, an auxiliary module must be built from included source, using \begin_inset Quotes eld \end_inset \family typewriter ghdl --vpi-compile \family default \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset \family typewriter ghdl --vpi-link \family default \begin_inset Quotes erd \end_inset . A script is provided to simplify these steps. If the top-level VHDL entity has the same name as the first source file: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ngspice ghnggen name.vhd ... \end_layout \end_inset \end_layout \begin_layout Standard When entity and file names differ: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ngspice -- ghnggen -top top_entity_name file_name.vhd ... \end_layout \end_inset \end_layout \begin_layout Standard The result will be a dynamic library (.so, .DLL or .dylib) named after the top-level. Apart from \begin_inset Quotes eld \end_inset -top \begin_inset Quotes erd \end_inset , anything else in the command will be passed to ghdl. In the netlist the VHDL code is accessed as an A-device, with ports mapped as for Verilog: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout adut [ inputs ... ] [ outputs ... ][ inouts ... ]ghdl_mod \end_layout \begin_layout Plain Layout .model ghdl_mod d_cosim \end_layout \begin_layout Plain Layout +simulation= \begin_inset Quotes erd \end_inset ./entity \begin_inset Quotes erd \end_inset sim_args=[ \begin_inset Quotes eld \end_inset ./entity \begin_inset Quotes erd \end_inset ] \end_layout \end_inset \end_layout \begin_layout Standard The sim_args values are passed to the simulation and may include \begin_inset Quotes eld \end_inset -gVariable=value \begin_inset Quotes erd \end_inset options to override top-level Generic parameters. A lib_args parameter may be used to set the explicit path to the auxiliary VP module, ghdlng.vpi. Otherwise it is expected to have been generated in the current directory. \end_layout \begin_layout Standard Example netlists can be found at examples/xspice/ghdl, with instructions in README.txt. \end_layout \begin_layout Subsection Using independent processes (e.g. C coded), pipes, and code model d_process \end_layout \begin_layout Standard Independent processes, e.g. made of C-coded executables, may be integrated into ngspice by using the code model d_process. A template for using this interface, with C-coded executables and ngspice netlists, is available at examples/xspice/d_process. The README will give you a detailed description of the procedure. A relatively complex example, a \begin_inset CommandInset href LatexCommand href name "motor control" target "https://www.isotel.eu/mixedsim/embedded/motorforce/index.html" literal "false" \end_inset , has been provided by Uros Platise at Isotel. His d_process code model has been enhanced to serve also MS Windows and is included in ngspice since version 42. \end_layout \begin_layout Subsection Using Yosys to map digital Verilog onto basic code model cells \end_layout \begin_layout Standard Another method to bring HDL code into a ngspice netlists for mixed-signal simulation is to use \begin_inset CommandInset href LatexCommand href name "Yosys" target "https://yosyshq.net/yosys/" literal "false" \end_inset to compile HDL and map the generated synthesizable cells directly to a ngspice sub-circuit definition using basic XSPICE elements (BUF, NOT, NAND, NOR, DLATCH, DFF). A demonstrator has been developed by Uros Platise at Isotel (see \begin_inset CommandInset href LatexCommand href name "description" target "https://www.isotel.eu/mixedsim/intro/prssine.html" literal "false" \end_inset and \begin_inset CommandInset href LatexCommand href name "code" target "https://github.com/Isotel/mixedsim/tree/master/examples/prssine" literal "false" \end_inset ). \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "chap:Analyses-and-Output" \end_inset Analyses and Output Control (batch mode) \end_layout \begin_layout Standard The command lines described in this chapter are used to specify analyses and outputs within the circuit description file. They start with a ` \family typewriter . \family default ' (dot commands). Specifying analyses and plots (or tables) in the input file with dot commands is used with batch runs. Batch mode is entered when either the \family typewriter \series bold -b \family default \series default option is given upon starting ngspice \end_layout \begin_layout Standard \family typewriter ngspice -b -r rawfile.raw circuitfile.cir \end_layout \begin_layout Standard or when the default input source is redirected from a file (see also Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Batch-mode" nolink "false" \end_inset ). \end_layout \begin_layout Standard \family typewriter ngspice < circuitfile.cir \end_layout \begin_layout Standard In batch mode, the analyses specified by the control lines in the input file (e.g. \family typewriter .ac \family default , \family typewriter .tran \family default , etc.) are immediately executed. If the \family typewriter \series bold -r \family default \series default rawfile option is given then all data generated is written to a ngspice rawfile. The rawfile may later be read by the interactive mode of ngspice using the \family sans load \family default command (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Load:-Load-rawfile" nolink "false" \end_inset ). In this case, the \family typewriter .save \family default line (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Batch-Output" nolink "false" \end_inset ) may be used to record the value of internal device variables (see Appendix, Chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Model-and-Device" nolink "false" \end_inset ). \end_layout \begin_layout Standard If a rawfile is not specified, then output plots (in `line-printer' form) and tables can be printed according to the \family typewriter .print \family default , \family typewriter .plot \family default , and \family typewriter .four \family default control lines, described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Batch-Output" nolink "false" \end_inset . \end_layout \begin_layout Standard If ngspice is started in interactive mode (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Interactive-mode" nolink "false" \end_inset ), like \end_layout \begin_layout Standard \family typewriter ngspice circuitfile.cir \end_layout \begin_layout Standard and no control section ( \family typewriter .control \family default ... \family typewriter .endc \family default , see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Interactive-mode-with" nolink "false" \end_inset ) is provided in the circuit file, the dot commands are not executed immediately, but are waiting for manually receiving the command \family sans run \family default . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Simulator-Variables" \end_inset Simulator Variables (.options) \end_layout \begin_layout Standard Various parameters of the simulations available in Ngspice can be altered to control the accuracy, speed, or default values for some devices. These parameters may be changed via the \family sans option \family default command (described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Option*:" nolink "false" \end_inset ) or via the \family typewriter .options \family default line: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .options opt1 opt2 ... (or opt=optval ...) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .options reltol=.005 trtol=8 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The options line allows the user to reset program control and user options for specific simulation purposes. Options specified to ngspice via the \family typewriter \series bold option \family default \series default command (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Option*:" nolink "false" \end_inset ) are also passed on as if specified on a \family typewriter .options \family default line. Any combination of the following options may be included, in any order. `x' (below) represents some positive number. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:General-Options" \end_inset General Options \end_layout \begin_layout Description SPARSE selects the Sparse 1.3 matrix solver, which is also the standard when no option is given. It is preferable for simulating behavioural device models. This option is required with noise ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.NOISE:-Noise-Analysis" nolink "false" \end_inset ) or CIDER ( \begin_inset CommandInset ref LatexCommand ref reference "cha:CIDER-User’s-Manual" nolink "false" \end_inset ) simulation. \end_layout \begin_layout Description KLU selects the KLU matrix solver, which is preferable (yielding faster simulation) when (large) circuits containing MOS devices are to be simulated. Small signal noise ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.NOISE:-Noise-Analysis" nolink "false" \end_inset ) or CIDER ( \begin_inset CommandInset ref LatexCommand ref reference "cha:CIDER-User’s-Manual" nolink "false" \end_inset ) simulations are not (yet) supported. \end_layout \begin_layout Description ACCT causes accounting and run time statistics to be printed. \end_layout \begin_layout Description NOACCT no printing of statistics, no printing of the Initial Transient Solution. \end_layout \begin_layout Description NOINIT suppresses only printing of the Initial Transient Solution, maybe combined with ACCT. \end_layout \begin_layout Description LIST causes the summary listing of the input data to be printed. \end_layout \begin_layout Description NOMOD suppresses the printout of the model parameters. \end_layout \begin_layout Description NOPAGE suppresses page ejects. \end_layout \begin_layout Description NODE causes the printing of the node table. \end_layout \begin_layout Description NOREFVALUE suppresses printing of reference values during simulation (the progress ticker in the Windows GUI and text output for others). \end_layout \begin_layout Description OPTS causes the option values to be printed. \end_layout \begin_layout Description SEED=val|random Sets the seed value of the random number generator. \series bold val \series default may be any integer number greater than 0. As an alternative, \series bold random \series default will set the seed value to the current Unix epoch time, which is the time in seconds since 1.1.1970 excluding leap seconds. \end_layout \begin_layout Description SEEDINFO will print the seed value when it has been set to a new integer number. \end_layout \begin_layout Description TEMP=x Resets the operating temperature of the circuit. The default value is 27 \begin_inset Formula $°C$ \end_inset (300K). TEMP can be overridden per device by a temperature specification on any temperature dependent instance. May also be generally overridden by a .TEMP card ( \begin_inset CommandInset ref LatexCommand ref reference "sec:.temp" nolink "false" \end_inset ). \end_layout \begin_layout Description TNOM=x resets the nominal temperature at which device parameters are measured. The default value is 27 \begin_inset Formula $°C$ \end_inset (300 deg K). TNOM can be overridden by a specification on any temperature dependent device model. \end_layout \begin_layout Description WARN=1|0 enables or turns of SOA (Safe Operating Area) voltage warning messages (default: 0). \end_layout \begin_layout Description MAXWARNS=x specifies the maximum number of SOA (Safe Operating Area) warning messages per model (default: 5). \end_layout \begin_layout Description SAVECURRENTS save currents through all terminals of the following devices: M, J, Q, D, R, C, L, B, F, G, W, S, I (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Circuit-elements-(device" nolink "false" \end_inset ). Recommended only for small circuits, because otherwise memory requirements explode and simulation speed suffers. See \begin_inset CommandInset ref LatexCommand ref reference "sec:Measuring-current-in" nolink "false" \end_inset for more details. This option is available only for op, dc, and tran simulation, not for ac. During transient simulation the value returned may be delayed by one time step. For M devices, MOS level 1 is supported fully, not all nodes are reported for the other MOS devices. As the option is installed upfront, before the simulation, it has no clue about the devices used in the circuit. It simply does do a best guess. This may lead to empty vectors of zero length after the simulation, impeding commands like \family typewriter wrdata \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Wrdata:-Write-data" nolink "false" \end_inset ). Running command \family typewriter remzerovec \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Remzerovec:-Remove-zero" nolink "false" \end_inset ) before \family typewriter wrdata \family default will remove all these zero length vectors. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:DC-Solution-Options" \end_inset OP and DC Solution Options \end_layout \begin_layout Standard The following options control properties pertaining to DC and OP (operating point) analyses and algorithms. Since transient analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Transient-Analysis-Options" nolink "false" \end_inset ) is based on OP, many of the options affect transient simulation as well. AC analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:AC-Solution-Options" nolink "false" \end_inset ) can be performed only when a stable operating point has been found. \end_layout \begin_layout Description ABSTOL=x resets the absolute current error tolerance of the program. The default value is 1 pA. \end_layout \begin_layout Description GMIN=x resets the value of GMIN, the minimum conductance allowed by the program. The default value is 1.0e-12. \end_layout \begin_layout Description GMINSTEPS=x [*] sets the number of Gmin steps to be attempted. If the value is set to zero, the standard gmin stepping algorithm is skipped. The standard behavior is that gmin stepping is tried before going to the source stepping algorithm. \end_layout \begin_layout Description ITL1=x resets the dc iteration limit. The default is 100. \end_layout \begin_layout Description ITL2=x resets the dc transfer curve iteration limit. The default is 50. \end_layout \begin_layout Description KEEPOPINFO Retain the operating point information when either an AC, Distortion, or Pole-Zero analysis is run. This is particularly useful if the circuit is large and you do not want to run a (redundant) \family typewriter .OP \family default analysis. \end_layout \begin_layout Description NOOPITER Go directly to gmin stepping, skipping the first iteration. \end_layout \begin_layout Description PIVREL=x resets the relative ratio between the largest column entry and an acceptable pivot value. The default value is 1.0e-3. In the numerical pivoting algorithm the allowed minimum pivot value is determined by \begin_inset Formula $\mathtt{EPSREL}=\mathtt{AMAX1}(\mathtt{PIVREL}\cdot\mathtt{MAXVAL},\:\mathtt{PIVTOL})$ \end_inset where MAXVAL is the maximum element in the column where a pivot is sought (partial pivoting). \end_layout \begin_layout Description PIVTOL=x resets the absolute minimum value for a matrix entry to be accepted as a pivot. The default value is 1.0e-13. \end_layout \begin_layout Description RELTOL=x resets the relative error tolerance of the program. The default value is 0.001 (0.1%). \end_layout \begin_layout Description RSHUNT=x introduces a resistor from each analog node to ground. The value of the resistor should be high enough to not interfere with circuit operations. The XSPICE option has to be enabled (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Advanced-Install" nolink "false" \end_inset ) . \end_layout \begin_layout Description VNTOL=x resets the absolute voltage error tolerance of the program. The default value is 1 \begin_inset Formula $\mu V$ \end_inset . \end_layout \begin_layout Subsubsection Matrix Conditioning info \end_layout \begin_layout Standard In SPICE-based simulators, specific problems arise with certain circuit topologies. One issue is the absence of a DC path to ground at some node. This may happen when two capacitors are connected in series with no other connection at the common node, or when code models are cascaded. The result is an ill-conditioned or nearly singular matrix that prevents the simulation from completing. Configuring with \family sans XSPICE \family default introduces the \family typewriter rshunt \family default option to help eliminate this problem. The option inserts resistors to ground at all the analog nodes in the circuit. In general, the value of \family typewriter rshunt \family default is set to some high resistance (e.g. \begin_inset Formula $1000\:\mathsf{M}\Omega$ \end_inset or greater) so that the operation of the circuit is essentially unaffected but the matrix problems are corrected. If a `no DC path to ground' or a `matrix is nearly singular' error message is encountered, add the following \family typewriter .option \family default card to the circuit deck: \end_layout \begin_layout LyX-Code .option rshunt = 1.0e12 \end_layout \begin_layout Standard Usually a value of \begin_inset Formula $1\mathsf{\:T}\Omega$ \end_inset is sufficient to correct the problem. In bad cases one can try lowering the value to \begin_inset Formula $10\mathsf{\:G}\Omega$ \end_inset or even \begin_inset Formula $1\:\mathsf{G}\Omega$ \end_inset . \end_layout \begin_layout Standard A different matrix conditioning problem occurs if an inductor is placed in parallel to a voltage source. The AC simulation will fail, because it is preceded by an OP analysis. Option \family typewriter NOOPAC \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:AC-Solution-Options" nolink "false" \end_inset ) will help if the circuit is linear. However, if the circuit is non-linear the OP analysis is essential. In such a case, adding a small resistor (e.g. \begin_inset Formula $0.1\mathsf{m}\Omega$ \end_inset ) in series to the inductor will help to obtain convergence. \end_layout \begin_layout LyX-Code .option rseries = 1.0e-4 \end_layout \begin_layout Standard adds a series resistor to each inductor in the circuit. Be careful when using behavioral inductors (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Inductors,-dependent-on" nolink "false" \end_inset ), as the result may become unpredictable. \end_layout \begin_layout LyX-Code .option cshunt = 1.3e-13 \end_layout \begin_layout Standard adds a capacitor from each voltage node in the circuit to ground. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:AC-Solution-Options" \end_inset AC Solution Options \end_layout \begin_layout Description NOOPAC Do not run an operating point (OP) analysis prior to an AC analysis. This option requires that the circuit is linear, \emph on i.e. \emph default consists only of R, L, and C devices, independent V, I sources and linear dependent E, G, H, and F sources (without poly statement, non-behavioral). If a non-linear device is detected, the OP analysis is executed automatically. This option is of interest \emph on e.g. \emph default in nested LC circuits where no series resistance for L devices is present. During the OP analysis an ill-formed matrix may be encountered, causing the simulator to abort with an error message. It is also useful if you have very large linear arrays (10000 nodes and more), where simulation speedup by a factor of 10 may be achieved. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Transient-Analysis-Options" \end_inset Transient Analysis Options \end_layout \begin_layout Description AUTOSTOP stops a transient analysis after successfully calculating all functions ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.MEAS" nolink "false" \end_inset ) specified with the dot command \family typewriter .meas \family default . Autostop is not available with the \family typewriter meas \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Meas*:-Mesurements-on" nolink "false" \end_inset ) command used in control mode. \end_layout \begin_layout Description CHGTOL=x resets the charge tolerance of the program. The default value is 1.0e-14. \end_layout \begin_layout Description CONVSTEP=x relative step limit applied to code models. \end_layout \begin_layout Description CONVABSSTEP=x absolute step limit applied to code models. \end_layout \begin_layout Description INTERP interpolates output data onto fixed time steps on a \family typewriter TSTEP \family default grid ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.TRAN:-Transient-Analysis" nolink "false" \end_inset ). Uses linear interpolation between previous and next time values. Simulation itself is not influenced by this option. This option can be used in all simulation modes (batch, control or interactive, \begin_inset CommandInset ref LatexCommand ref reference "sec:Starting-options" nolink "false" \end_inset ). It may drastically reduce memory requirements in control mode, and file size in batch mode, but care is needed not to undersample the output data. See also the command \family typewriter linearize \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Linearize*:-Interpolate-to" nolink "false" \end_inset ) that achieves a similar result by post-processing the data in control mode. The \family sans Ngspice/examples/xspice/delta-sigma/delta-sigma-1.cir \family default example demonstrates how INTERP reduces memory requirements and speeds up plotting. \end_layout \begin_layout Description ITL3=x resets the lower transient analysis iteration limit. The default value is 4. (Note: not implemented in Spice3). \end_layout \begin_layout Description ITL4=x resets the transient analysis time-point iteration limit. The default is 10. \end_layout \begin_layout Description ITL5=x resets the transient analysis total iteration limit. The default is 5000. Set \family sans ITL5 \family default =0 to omit this test. (Note: not implemented in Spice3). \end_layout \begin_layout Description ITL6=x [*] synonym for \family sans SRCSTEPS \family default . \end_layout \begin_layout Description MAXEVTITER=x sets the maximum number of event iterations per analysis point. \end_layout \begin_layout Description MAXOPALTER=x specifies the maximum number of analog/event alternations that the simulator will use to solve a hybrid circuit. \end_layout \begin_layout Description MAXORD=x [*] specifies the maximum order for the numerical integration method used by SPICE. Possible values for the Gear method are from 2 (the default) to 6. Using the value 1 with the trapezoidal method specifies backward Euler integration. \end_layout \begin_layout Description METHOD=name sets the numerical integration method used by SPICE. Possible names are `Gear' or `trapezoidal' (or just `trap'). The default is trapezoidal. \end_layout \begin_layout Description NOOPALTER=TRUE|FALSE if set to false, alternations between analog and event calls to XSPICE models are enabled during initial DC operating analysis. \end_layout \begin_layout Description RAMPTIME=x During source stepping, this option sets the rate of change of independent supplies. It also affects code model inductors and capacitors that have initial conditions specified. \end_layout \begin_layout Description SRCSTEPS=x [*] a non-zero value causes SPICE to use a source-stepping method to find the DC operating point. The value specifies the number of steps. \end_layout \begin_layout Description \begin_inset CommandInset label LatexCommand label name "des:TRTOL" \end_inset TRTOL=x resets the transient error tolerance. The default value is 7. This parameter is an estimate of the factor by which SPICE overestimates the actual truncation error. If XSPICE is configured and 'A' devices are included, the value is internally set to 1 for higher precision. This slows down transient analysis by a factor of two. \end_layout \begin_layout Description XMU=x sets the damping factor for trapezoidal integration. The default value is \family typewriter XMU \family default =0.5. A value \family typewriter < \family default 0.5 may be chosen. Even a small reduction, e.g. to 0.495, may already suppress trap ringing. The reduction has to be set carefully in order not to excessively damp circuits that are prone to ringing or oscillation, which might lead the user to believe that the circuit is stable. \end_layout \begin_layout Subsection ELEMENT Specific options \end_layout \begin_layout Description diode_cj0=x Add optional diode junction capacitance, if none is defined in the .model statement. Example call: \family typewriter .options diode_cj0=20p \family default . \end_layout \begin_layout Description diode_rser=x Add optional diode series resistance, if none is defined in the .model statement. Example call: \family typewriter .options diode_rser=20m \family default . \end_layout \begin_layout Description BADMOS3 Use the older version of the MOS3 model with the `kappa' discontinuity. \end_layout \begin_layout Description DEFAD=x resets the value for MOS drain diffusion area; the default is 0. \end_layout \begin_layout Description DEFAS=x resets the value for MOS source diffusion area; the default is 0. \end_layout \begin_layout Description DEFL=x resets the value for MOS channel length; the default is 100 \begin_inset Formula $\mu m$ \end_inset . \end_layout \begin_layout Description DEFW=x resets the value for MOS channel width; the default is 100 \begin_inset Formula $\mu m$ \end_inset . \end_layout \begin_layout Description SCALE=x set the element scaling factor for geometric element parameters whose default unit is meters. As an example: \family typewriter scale=1u \family default and a MOSFET instance parameter \family typewriter W=10 \family default will result in a width of 10 \begin_inset Formula $\mu m$ \end_inset for this device. An area parameter \family typewriter AD=20 \family default will result in \begin_inset Formula $\mathsf{20e-12\:m^{2}}$ \end_inset . Following instance parameters are scaled: \end_layout \begin_layout Itemize Resistors and Capacitors: W, L \end_layout \begin_layout Itemize Diodes: W, L, Area \end_layout \begin_layout Itemize JFET, MESFET: W, L, Area \end_layout \begin_layout Itemize MOSFET: W, L, AS, AD, PS, PD, SA, SB, SC, SD \end_layout \begin_layout Subsection Transmission Lines Specific Options \end_layout \begin_layout Description TRYTOCOMPACT Applicable only to the LTRA model (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Lossy-Transmission-Line" nolink "false" \end_inset ). When specified, the simulator tries to condense an LTRA transmission line's past history of input voltages and currents. \end_layout \begin_layout Subsection Precedence of option and .options commands \end_layout \begin_layout Standard There are various ways to set the above mentioned options in Ngspice. If no \family typewriter option \family default or \family typewriter .options \family default lines are set by the user, internal default values are given for each of the simulator variables. \end_layout \begin_layout Standard You may set options in the init files \family sans spinit \family default or \family sans .spiceinit \family default via the \family typewriter option \family default command (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Option*:" nolink "false" \end_inset ). The values given there will supersede the default values. If you set options via the \family typewriter .options \family default line in your input file, their values will supersede the default and init file data. Finally, if you set options inside a \family typewriter .control \family default ... \family typewriter .endc \family default section, these values will again supersede any simulator variables given so far. \end_layout \begin_layout Section Initial Conditions \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.NODESET" \end_inset .NODESET: Specify Initial Node Voltage Guesses \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .nodeset v(nodnum)=val v(nodnum)=val ... \end_layout \begin_layout Plain Layout .nodeset all=val \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .nodeset v(12)=4.5 v(4)=2.23 \end_layout \begin_layout Plain Layout .nodeset all=1.5 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .nodeset \family default line helps the program find the DC or initial transient solution by making a preliminary pass with the specified nodes held to the given voltages. The restrictions are then released and the iteration continues to the true solution. The \family typewriter .nodeset \family default line may be necessary for convergence on bistable or astable circuits. \family typewriter .nodeset all=val \family default sets all starting node voltages (except for the ground node) to the same value. In general, the \family typewriter .nodeset \family default line should not be necessary. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.IC:-Set-Initial" \end_inset .IC: Set Initial Conditions \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .ic v(nodnum)=val v(nodnum)=val ... \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .ic v(11)=5 v(4)=-5 v(2)=2.2 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .ic \family default line is for setting transient initial conditions. It has two different interpretations, depending on whether the \family typewriter \series bold uic \family default \series default parameter is specified on the \family typewriter .tran \family default control line, or not. One should not confuse this line with the \family typewriter .nodeset \family default line. The \family typewriter .nodeset \family default line is only to help DC convergence, and does not affect the final bias solution (except for multi-stable circuits). The two indicated interpretations of this line are as follows: \end_layout \begin_layout Enumerate When the \family typewriter \series bold uic \family default \series default parameter is specified on the \family typewriter .tran \family default line, the node voltages specified on the \family typewriter .ic \family default control line are used to compute the capacitor, diode, BJT, JFET, and MOSFET initial conditions. This is equivalent to specifying the \family typewriter \series bold ic=... \family default \series default parameter on each device line, but is much more convenient. The \family typewriter \series bold ic=... \family default \series default parameter can still be specified and takes precedence over the \family typewriter .ic \family default values. Since no dc bias (initial transient) solution is computed before the transient analysis, one should take care to specify all dc source voltages on the \family typewriter .ic \family default control line if they are to be used to compute device initial conditions. \end_layout \begin_layout Enumerate When the \family typewriter \series bold uic \family default \series default parameter is not specified on the \family typewriter .tran \family default control line, the DC bias (initial transient) solution is computed before the transient analysis. In this case, the node voltages specified on the \family typewriter .ic \family default control lines are forced to the desired initial values during the bias solution. During transient analysis, the constraint on these node voltages is removed. This is the preferred method since it allows Ngspice to compute a consistent dc solution. \end_layout \begin_layout Standard The \family typewriter wrnodev \family default command \begin_inset CommandInset ref LatexCommand ref reference "subsec:Wrnodev:-Write-node" plural "false" caps "false" noprefix "false" nolink "false" \end_inset saves node voltages in \family typewriter .ic \family default format so that they may re-input by \family typewriter .include \family default . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Analyses" \end_inset Analyses \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.AC:-Small-Signal-AC" \end_inset .AC: Small-Signal AC Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .ac dec nd fstart fstop \end_layout \begin_layout Plain Layout .ac oct no fstart fstop \end_layout \begin_layout Plain Layout .ac lin np fstart fstop \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .ac dec 10 1 10K \end_layout \begin_layout Plain Layout .ac dec 10 1K 100MEG \end_layout \begin_layout Plain Layout .ac lin 100 1 100HZ \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold dec \family default \series default stands for decade variation, and \family typewriter \series bold nd \family default \series default is the number of points per decade. \family typewriter \series bold oct \family default \series default stands for octave variation, and \family typewriter \series bold no \family default \series default is the number of points per octave. \family typewriter \series bold lin \family default \series default stands for linear variation, and \family typewriter \series bold np \family default \series default is the number of points. \family typewriter \series bold fstart \family default \series default is the starting frequency, and \family typewriter \series bold fstop \family default \series default is the final frequency. If this line is included in the input file, Ngspice performs an AC analysis of the circuit over the specified frequency range. Note that in order for this analysis to be meaningful, at least one independent source must have been specified with an ac value. Typically it does not make much sense to specify more than one ac source. If you do, the result will be a superposition of all sources and difficult to interpret. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Basic RC circuit \end_layout \begin_layout Plain Layout r 1 2 1.0 \end_layout \begin_layout Plain Layout c 2 0 1.0 \end_layout \begin_layout Plain Layout vin 1 0 dc 0 ac 1 $ <--- the ac source \end_layout \begin_layout Plain Layout .options noacct \end_layout \begin_layout Plain Layout .ac dec 10 .01 10 \end_layout \begin_layout Plain Layout .plot ac vdb(2) xlog \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard In this AC (or 'small signal') analysis, all non-linear devices are linearized around their actual DC operating point. All L and C devices get their imaginary value that depends on the actual frequency step. Each output vector will be calculated relative to the input voltage (current) given by the AC value ( \begin_inset Formula $V_{in}$ \end_inset equals 1 in the example above). The resulting node voltages (and branch currents) are complex vectors. Therefore one has to be careful using the \family typewriter plot \family default command, specifically, one may use the variants of vxx(node) described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.PRINT-Lines" nolink "false" \end_inset like \family typewriter vdb(2) \family default (see also the above example). \end_layout \begin_layout Standard If one wants to simulate ac on a \series bold large linear array \series default , the option \family typewriter noopac \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:AC-Solution-Options" nolink "false" \end_inset ) may be useful. Linear circuits are containing only linear device instances starting with letters r, l, c, i, v, e, g, f, h, k. The instances e, g, f, h have to be the simple ones, as of chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Linear-Dependent-Sources" nolink "false" \end_inset , not the polynomial nor the behavioral variants. If the option \family typewriter noopac \family default is set, ngspice tests for the absence of any other devices. If successful, the often lengthy op calculation is skipped, ac is started immediately. Considerable simulation time savings may result. \end_layout \begin_layout Standard Output parameters like \family typewriter @m1[cgs] \family default or \family typewriter @r1[i] \family default (see \begin_inset CommandInset ref LatexCommand ref reference "cha:Model-and-Device" nolink "false" \end_inset ) are not supported during AC simulation. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.DC:-DC-Transfer" \end_inset .DC: DC Transfer Function \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .dc srcnam vstart vstop vincr [src2 start2 stop2 incr2] \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .dc VIN 0.25 5.0 0.25 \end_layout \begin_layout Plain Layout .dc VDS 0 10 .5 VGS 0 5 1 \end_layout \begin_layout Plain Layout .dc VCE 0 10 .25 IB 0 10u 1u \end_layout \begin_layout Plain Layout .dc RLoad 1k 2k 100 \end_layout \begin_layout Plain Layout .dc TEMP -15 75 5 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .dc \family default line defines the dc transfer curve source and sweep limits (with capacitors open and inductors shorted). \family typewriter \series bold srcnam \family default \series default is the name of an independent voltage or current source, a resistor, or the circuit temperature. \family typewriter \series bold vstart \family default \series default , \family typewriter \series bold vstop \family default \series default , and \family typewriter \series bold vincr \family default \series default are the starting, final, and incrementing values, respectively. The first example causes the value of the voltage source \begin_inset Formula $V_{IN}$ \end_inset to be swept from 0.25 Volts to 5.0 Volts with steps of 0.25 Volt. A second source ( \family typewriter \series bold src2 \family default \series default ) may optionally be specified with its own associated sweep parameters. In such a case the first source is swept over its own range for each value of the second source. This option is useful for obtaining semiconductor device output characteristics. See the example on transistor characterization ( \begin_inset CommandInset ref LatexCommand ref reference "sec:MOSFET-Characterization" nolink "false" \end_inset ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.DISTO:-Distortion-Analysis" \end_inset .DISTO: Distortion Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .disto dec nd fstart fstop \end_layout \begin_layout Plain Layout .disto oct no fstart fstop \end_layout \begin_layout Plain Layout .disto lin np fstart fstop \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .disto dec 10 1kHz 100MEG \end_layout \begin_layout Plain Layout .disto dec 10 1kHz 100MEG 0.9 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .disto \family default line does a small-signal distortion analysis of the circuit. A multi-dimensional Volterra series analysis is done using multi-dimensional Taylor series to represent the nonlinearities at the operating point. Terms of up to third order are used in the series expansions. \end_layout \begin_layout Standard If the optional parameter \family typewriter \series bold f2overf1 \family default \series default is not specified, \family typewriter .disto \family default does a harmonic analysis - i.e., it analyses distortion in the circuit using only a single input frequency \begin_inset Formula $F_{1}$ \end_inset , which is swept as specified by arguments of the \family typewriter .disto \family default command exactly as in the \family typewriter .ac \family default command. Inputs at this frequency may be present at more than one input source, and their magnitudes and phases are specified by the arguments of the \family typewriter \series bold distof1 \family default \series default keyword in the input file lines for the input sources (see the description for independent sources). (The arguments of the \family typewriter \series bold distof2 \family default \series default keyword are not relevant in this case). \end_layout \begin_layout Standard The analysis produces information about the AC values of all node voltages and branch currents at the harmonic frequencies \begin_inset Formula $2F_{1}$ \end_inset and , vs. the input frequency \begin_inset Formula $F_{1}$ \end_inset as it is swept. (A value of 1 (as a complex distortion output) signifies \begin_inset Formula $\cos(2\pi(2F_{1})t)$ \end_inset at \begin_inset Formula $2F_{1}$ \end_inset and \begin_inset Formula $\cos(2\pi(3F_{1})t)$ \end_inset at \begin_inset Formula $3F_{1}$ \end_inset , using the convention that 1 at the input fundamental frequency is equivalent to \begin_inset Formula $\cos(2\pi F_{1}t)$ \end_inset .) The distortion component desired ( \begin_inset Formula $2F_{1}$ \end_inset or \begin_inset Formula $3F_{1}$ \end_inset ) can be selected using interactive or control commands in ngspice, and then printed or plotted. (Normally, one is interested primarily in the magnitude of the harmonic components, so the magnitude of the AC distortion value is looked at). It should be noted that these are the AC values of the actual harmonic components, and are not equal to HD2 and HD3. To obtain HD2 and HD3, one must divide by the corresponding AC values at \begin_inset Formula $F_{1}$ \end_inset , obtained from an \family typewriter .ac \family default line. This division can be done again using interactive or control commands. \end_layout \begin_layout Standard If the optional \family typewriter \series bold f2overf1 \family default \series default parameter is specified, it should be a real number between (and not equal to) 0.0 and 1.0; in this case, \family typewriter .disto \family default does a spectral analysis. It considers the circuit with sinusoidal inputs at two different frequencies \begin_inset Formula $F_{1}$ \end_inset and \begin_inset Formula $F_{2}$ \end_inset . \begin_inset Formula $F_{1}$ \end_inset is swept according to the \family typewriter .disto \family default control line options exactly as in the \family typewriter .ac \family default control line. \begin_inset Formula $F_{2}$ \end_inset is kept fixed at a single frequency as \begin_inset Formula $F_{1}$ \end_inset sweeps - the value at which it is kept fixed is equal to \family typewriter f2overf1 \family default times \family typewriter fstart \family default . Each independent source in the circuit may potentially have two (superimposed) sinusoidal inputs for distortion, at the frequencies \begin_inset Formula $F_{1}$ \end_inset and \begin_inset Formula $F_{2}$ \end_inset . The magnitude and phase of the \begin_inset Formula $F_{1}$ \end_inset component are specified by the arguments of the \family typewriter \series bold distof1 \family default \series default keyword in the source's input line (see the description of independent sources); the magnitude and phase of the \begin_inset Formula $F_{2}$ \end_inset component are specified by the arguments of the \family typewriter \series bold distof2 \family default \series default keyword. The analysis produces plots of all node voltages/branch currents at the intermodulation product frequencies \begin_inset Formula $F_{1}+F_{2}$ \end_inset , \begin_inset Formula $F_{1}-F_{2}$ \end_inset , and \begin_inset Formula $(2F_{1})-F_{2}$ \end_inset , vs the swept frequency \begin_inset Formula $F_{1}$ \end_inset . The IM product of interest may be selected using the \family sans setplot \family default command, and displayed with the \family typewriter print \family default and \family typewriter plot \family default commands. It is to be noted as in the harmonic analysis case, the results are the actual AC voltages and currents at the intermodulation frequencies, and need to be normalized with respect to \family typewriter .ac \family default values to obtain the IM parameters. \end_layout \begin_layout Standard If the \family typewriter \series bold distof1 \family default \series default or \family typewriter \series bold distof2 \family default \series default keywords are missing from the description of an independent source, then that source is assumed to have no input at the corresponding frequency. The default values of the magnitude and phase are 1.0 and 0.0 respectively. The phase should be specified in degrees. \end_layout \begin_layout Standard It should be carefully noted that the number \family typewriter \series bold f2overf1 \family default \series default should ideally be an irrational number, and that since this is not possible in practice, efforts should be made to keep the denominator in its fractional representation as large as possible, certainly above 3, for accurate results (i.e., if \family typewriter \series bold f2overf1 \family default \series default is represented as a fraction \begin_inset Formula $\nicefrac{A}{B}$ \end_inset , where \begin_inset Formula $A$ \end_inset and \begin_inset Formula $B$ \end_inset are integers with no common factors, \begin_inset Formula $B$ \end_inset should be as large as possible; note that \begin_inset Formula $A49/100$ \end_inset \begin_inset Formula $F_{1}=F_{2}$ \end_inset . In this case, there are two very closely spaced frequency components at \begin_inset Formula $F_{2}$ \end_inset and \begin_inset Formula $F_{1}-F_{2}$ \end_inset . One of the advantages of the Volterra series technique is that it computes distortions at mix frequencies expressed symbolically (i.e. \begin_inset Formula $nF_{1}+mF_{2}$ \end_inset ), therefore one is able to obtain the strengths of distortion components accurately even if the separation between them is very small, as opposed to transient analysis for example. The disadvantage is of course that if two of the mix frequencies coincide, the results are not merged together and presented (though this could presumably be done as a postprocessing step). Currently, the interested user should keep track of the mix frequencies himself or herself and add the distortions at coinciding mix frequencies together should it be necessary. \end_layout \begin_layout Standard Only a subset of the ngspice nonlinear device models supports distortion analysis. These are \end_layout \begin_layout Itemize Diodes (DIO), \end_layout \begin_layout Itemize BJT, \end_layout \begin_layout Itemize JFET (level 1), \end_layout \begin_layout Itemize MOSFETs (levels 1, 2, 3, 9, and BSIM1), \end_layout \begin_layout Itemize MESFET (level 1). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.NOISE:-Noise-Analysis" \end_inset .NOISE: Noise Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .noise v(output <,ref>) src ( dec | lin | oct ) pts fstart fstop \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .noise v(5) VIN dec 10 1kHz 100MEG \end_layout \begin_layout Plain Layout .noise v(5,3) V1 oct 8 1.0 1.0e6 1 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .noise \family default line does a noise analysis of the circuit. \family typewriter \series bold output \family default \series default is the node at which the total output noise is desired; if \family typewriter \series bold ref \family default \series default is specified, then the noise voltage \family typewriter \series bold v(output) - v(ref) \family default \series default is calculated. By default, \family typewriter \series bold ref \family default \series default is assumed to be ground. \family typewriter \series bold src \family default \series default is the name of an independent source to which input noise is referred. \family typewriter \series bold pts \family default \series default , \family typewriter \series bold fstart \family default \series default and \family typewriter \series bold fstop \family default \series default are \family typewriter .ac \family default type parameters that specify the frequency range over which plots are desired. \family typewriter \series bold pts_per_summary \family default \series default is an optional integer; if specified, the noise contributions of each noise generator is produced every \family typewriter \series bold pts_per_summary \family default \series default frequency points. The \family typewriter .noise \family default control line produces two plots, which can selected by \family typewriter setplot \family default command: \end_layout \begin_layout Itemize one for the Voltage or Current Noise Spectral Density (in \begin_inset Formula $\nicefrac{V}{\sqrt{Hz}}$ \end_inset or \begin_inset Formula $\nicefrac{A}{\sqrt{Hz}}$ \end_inset respective the input is a voltage or current source) curves (e.g. after \family typewriter setplot noise1 \family default ). There are two vectors over frequency: \end_layout \begin_deeper \begin_layout Itemize \family typewriter \series bold onoise_spectrum \family default \series default : This is the output noise voltage or current divided by \begin_inset Formula $\sqrt{Hz}$ \end_inset . \end_layout \begin_layout Itemize \family typewriter \series bold inoise_spectrum \family default \series default : This the equivalent input noise = output noise divided by the gain of the circuit. \end_layout \end_deeper \begin_layout Itemize one for the Total Integrated Noise (in \begin_inset Formula $V$ \end_inset or \begin_inset Formula $A$ \end_inset ) over the specified frequency range (e.g. after \family typewriter setplot noise \family default 2). There are two vectors which are in reality scalars: \end_layout \begin_deeper \begin_layout Itemize \family typewriter \series bold onoise_total \family default \series default : This is the output noise voltage over the specified frequency range \end_layout \begin_layout Itemize \family typewriter \series bold inoise_total \family default \series default : This the equivalent input noise over the specified frequency range = output noise divided by the gain of the circuit. \end_layout \end_deeper \begin_layout Standard The units of all result vectors can be changed by using control variable \family typewriter \series bold sqrnoise: \end_layout \begin_layout Itemize \family typewriter \series bold set sqrnoise: \family default \series default will deliver results in squared form, means the unit is \begin_inset Formula $\nicefrac{V^{2}}{Hz}$ \end_inset or \begin_inset Formula $\nicefrac{A^{2}}{Hz}$ \end_inset . This value refers more to the convenient Power Spectral Density. \end_layout \begin_layout Standard Default setting of ngspice is \family typewriter \series bold unset sqrnoise, \family default \series default which delivers Voltage or Current Noise Spectral Density. This is more practical from designers point of view. \end_layout \begin_layout Standard The KLU matrix solver ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:General-Options" nolink "false" \end_inset ) is not compatible with noise simulation. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.OP:-Operating-Point" \end_inset .OP: Operating Point Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .op \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Compute the DC operating point of the circuit with inductors shorted and capacitors opened. \end_layout \begin_layout Standard A DC solution can be difficult to find for some circuits, including those with floating nodes or active devices that are non-conducting. After an attempt at an initial DC solution (may be suppressed by \family typewriter .option noopiter \family default ), ngspice uses the following convergence aids, in order, to try to obtain a DC solution: \end_layout \begin_layout Enumerate gmin stepping (gminsteps option). Inserts small conductances across active devices. \end_layout \begin_deeper \begin_layout Itemize gminsteps = 0: No gmin \end_layout \begin_layout Itemize gminsteps = 1: Two gmin stepping processes in series (default) \end_layout \begin_layout Itemize gminsteps = 2: Original SPICE 3 gmin \end_layout \end_deeper \begin_layout Enumerate source stepping (srcsteps option) \end_layout \begin_deeper \begin_layout Itemize srcsteps = 0: No source stepping \end_layout \begin_layout Itemize srcsteps = 1: Gillespie source stepping (default) \end_layout \begin_layout Itemize srcsteps = 2: Original SPICE 3 source stepping \end_layout \end_deeper \begin_layout Enumerate transient operating point (optional) \end_layout \begin_layout Standard DC analysis is complete as soon as one successful step is found, according to some convergence criteria.. \end_layout \begin_layout Standard The default behaviour during gmin stepping is the following: Switch \family typewriter gmin \family default to a start value (1e-3), followed by a first trial of gmin stepping, using the true device gmin, then try dynamic gmin stepping with diagonal parallel gmin elements. If variable dyngmin is set, only dynamic gmin stepping is used. \end_layout \begin_layout Standard Source stepping sets all supply voltages and currents to zero, then ramps them up dynamically to 100%. \end_layout \begin_layout Standard The transient op calculation uses a transient simulation, with default parameters set by ngspice (initial iteration, gmin and source stepping enabled, optran step size \family typewriter 10n \family default , total optran time \family typewriter 10u \family default ). The results of this transient simulation then are used as the operating point for starting any other simulation (tran, ac, noise, pz etc.). No other data of this transient op are stored anywhere. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout optran !noopiter gminsteps srcsteps tstep tstop supramp \end_layout \end_inset \end_layout \begin_layout Plain Layout Example 1: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout optran 0 0 0 100n 10u 0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Example 1 changes the defaults to: no inital op iteration, no gmin stepping, no source stepping, i.e. directly move to transient op with transient step and stop times given. Flag \family typewriter supramp \family default ins currently not used. The optran command may be put into one of the initialization files \family typewriter .spiceinit \family default or \family typewriter spinit \family default . or into the \family typewriter .control \family default section. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example 2: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout optran 1 1 1 100n 10u 0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Example 2 shows an \family typewriter optran \family default command which restores the initial conditions. \end_layout \begin_layout Standard Note: an operating point analysis is automatically performed prior to a transient analysis (if the parameter uic is not selected) to determine the transient initial conditions, and prior to an AC small-signal, Noise, and Pole-Zero analysis to determine the linearized, small-signal models for nonlinear devices. These data are not stored, except for setting the \family typewriter KEEPOPINFO \family default variable \begin_inset CommandInset ref LatexCommand ref reference "subsec:DC-Solution-Options" nolink "false" \end_inset , that prompts creating an OP plot in addition to the TRAN, AC, Noise, or PZ plots. \end_layout \begin_layout LyX-Code \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.PZ:-Pole-Zero-Analysis" \end_inset .PZ: Pole-Zero Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .pz node1 node2 node3 node4 cur pol \end_layout \begin_layout Plain Layout .pz node1 node2 node3 node4 cur zer \end_layout \begin_layout Plain Layout .pz node1 node2 node3 node4 cur pz \end_layout \begin_layout Plain Layout .pz node1 node2 node3 node4 vol pol \end_layout \begin_layout Plain Layout .pz node1 node2 NODE3 node4 vol zer \end_layout \begin_layout Plain Layout .pz node1 node2 node3 node4 vol pz \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .pz 1 0 3 0 cur pol \end_layout \begin_layout Plain Layout .pz 2 3 5 0 vol zer \end_layout \begin_layout Plain Layout .pz 4 1 4 1 cur pz \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold cur \family default \series default stands for a transfer function of the type (output voltage)/(input current) while \family typewriter \series bold vol \family default \series default stands for a transfer function of the type (output voltage)/(input voltage). \family typewriter \series bold pol \family default \series default stands for pole analysis only, \family typewriter \series bold zer \family default \series default for zero analysis only and \family typewriter \series bold pz \family default \series default for both. This feature is provided mainly because if there is a non-convergence in finding poles or zeros, then, at least the other can be found. Finally, \family typewriter \series bold node1 \family default \series default and \family typewriter \series bold node2 \family default \series default are the two input nodes and \family typewriter \series bold node3 \family default \series default and \family typewriter \series bold node4 \family default \series default are the two output nodes. Thus, there is complete freedom regarding the output and input ports and the type of transfer function. \end_layout \begin_layout Standard In interactive mode, the command syntax is the same except that the first field is \family sans pz \family default instead of \family typewriter .pz \family default . To print the results, one should use the command \family sans print all \family default . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.SENS" \end_inset .SENS: DC or Small-Signal AC Sensitivity Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .SENS OUTVAR [< filter ...>] [DC] \end_layout \begin_layout Plain Layout .SENS OUTVAR [< filter ...>] AC DEC ND FSTART FSTOP \end_layout \begin_layout Plain Layout .SENS OUTVAR [< filter ...>] AC OCT NO FSTART FSTOP \end_layout \begin_layout Plain Layout .SENS OUTVAR [< filter ...>] AC LIN NP FSTART FSTOP \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .SENS V(1,OUT) \end_layout \begin_layout Plain Layout .SENS V(OUT) AC DEC 10 100 100k \end_layout \begin_layout Plain Layout .SENS I(VTEST) rbias m*_* q*:* \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The sensitivity of OUTVAR to device and model parameters is calculated when the SENS analysis is specified. OUTVAR is a circuit variable (node voltage or voltage-source branch current). The first form calculates sensitivity of the DC operating-point value of OUTVAR. The second form calculates sensitivity of the AC values of OUTVAR. The sweep parameters listed for AC sensitivity are the same as in an AC analysis (see \family typewriter .AC \family default above). The output values are in dimensions of change in output per unit change of input (as opposed to percent change in output or per percent change of input). \end_layout \begin_layout Standard By default, all modifiable, real-valued parameters are varied and an output vector is created for each. For primary device parameters, that may be written directly after the node list, the vector name is the device name. (Examples are resistance and inductance.) Otherwise vector names have the form \shape italic device_parameter \shape default for device parameters, and \shape italic model:parameter \shape default for model parameters. \end_layout \begin_layout Standard Optional filter strings allow selection of the parameters to be varied and recorded by matching potential vector names. The filter strings may include '*' to match any substring or '?' that will match any single character (a byte, not a complete multibyte character). So, in the example above, a specific resistor, all device parameters for MOSFETS and all model parameters for BJTs are selected. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.SP-S-Parameter" \end_inset .SP S-Parameter Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .sp dec nd fstart fstop \end_layout \begin_layout Plain Layout .sp oct no fstart fstop \end_layout \begin_layout Plain Layout .sp lin np fstart fstop \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .sp dec 10 1 10K \end_layout \begin_layout Plain Layout .sp dec 10 1K 100MEG 1 \end_layout \begin_layout Plain Layout .sp lin 100 1 100HZ \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard To prepare the independent voltage source VSRC please see \begin_inset CommandInset ref LatexCommand ref reference "subsec:RF-Port" nolink "false" \end_inset . \end_layout \begin_layout Standard SP Simulation Syntax is identical to .AC ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.AC:-Small-Signal-AC" nolink "false" \end_inset ) except that you have one more optional parameter donoise (0|1). SP does always linear S-Matrix simulation and, as outputs, it gives \end_layout \begin_layout Description S Matrix (size nport x nport where nport is the count of RF ports) which is the Scattering Parameters. It may be used to export Touchstone files (to be implemented yet)... \end_layout \begin_layout Description Y Matrix (size nport x nport where nport is the count of RF ports) which is the Admittance Matrix \end_layout \begin_layout Description Z Matrix (size nport x nport where nport is the count of RF ports) which is the Impedance Matrix \end_layout \begin_layout Standard All S|Y|Z output are S_i_j where i and j are integer identifiers of the ports. They refer to the \family sans portnum \family default identifier of corresponding RF port of the VSRC ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:RF-Port" nolink "false" \end_inset ). \end_layout \begin_layout Standard If donoise = 0 SP simulation ends here. \end_layout \begin_layout Standard If donoise = 1, SP simulation performs also SP Noise. In this case: you have one more output which is the Noise Current Correlation Matrix: Cy_i_j Cy_i_j = which is the correlation between equivalent input noise current at port i and equivalent input noise current at port j. * stands for conjugate \end_layout \begin_layout Standard When donoise = 1 and you have a two port networks, 4 more outputs are provided: \end_layout \begin_layout Description Rn input noise resistance (unnormalized) \end_layout \begin_layout Description NF (dB): noise figure of the 2-ports network \end_layout \begin_layout Description NFmin (dB): minimum noise figure \end_layout \begin_layout Description SOpt: optimum input reflection coefficient for noise \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.TF:-Transfer-Function" \end_inset .TF: Transfer Function Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .tf outvar insrc \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .tf v(5, 3) VIN \end_layout \begin_layout Plain Layout .tf i(VLOAD) VIN \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .tf \family default line defines the small-signal output and input for the dc small-signal analysis. \family typewriter \series bold outvar \family default \series default is the small signal output variable and \family typewriter \series bold insrc \family default \series default is the small-signal input source. If this line is included, ngspice computes the dc small-signal value of the transfer function (output/input), input resistance, and output resistance. For the first example, ngspice would compute the ratio of V(5, 3) to VIN, the small-signal input resistance at VIN, and the small signal output resistance measured across nodes 5 and 3. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.TRAN:-Transient-Analysis" \end_inset .TRAN: Transient Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .tran tstep tstop > \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .tran 1ns 100ns \end_layout \begin_layout Plain Layout .tran 1ns 1000ns 500ns \end_layout \begin_layout Plain Layout .tran 10ns 1us \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold tstep \family default \series default is the printing or plotting increment for line-printer output. For use with the post-processor, \family typewriter \series bold tstep \family default \series default is the suggested computing increment. \family typewriter \series bold tstop \family default \series default is the final time, and \family typewriter \series bold tstart \family default \series default is the initial time. If \family typewriter \series bold tstart \family default \series default is omitted, it is assumed to be zero. The transient analysis always begins at time zero. In the interval [zero, \family typewriter \series bold tstart \family default \series default ), the circuit is analyzed (to reach a steady state), but no outputs are stored. In the interval [ \family typewriter \series bold tstart \family default \series default , \family typewriter \series bold tstop \family default \series default ], the circuit is analyzed and outputs are stored. \family typewriter \series bold tmax \family default \series default is the maximum stepsize that ngspice uses; for default, the program chooses either \family typewriter \series bold tstep \family default \series default or ( \family typewriter \series bold tstop \family default \series default - \family typewriter \series bold tstart \family default \series default )/50.0, whichever is smaller. \family typewriter \series bold tmax \family default \series default is useful when one wishes to guarantee a computing interval that is smaller than the printer increment, \family typewriter \series bold tstep \family default \series default . \end_layout \begin_layout Standard An initial transient operating point at time zero is calculated according to the following procedure: all independent voltages and currents are applied with their time zero values, all capacitances are opened, inductances are shorted, the non linear device equations are solved iteratively. \end_layout \begin_layout Standard \family typewriter \series bold uic \family default \series default (use initial conditions) is an optional keyword that indicates that the user does not want ngspice to solve for the quiescent operating point before beginning the transient analysis. If this keyword is specified, ngspice uses the values specified using IC=... on the various elements as the initial transient condition and proceeds with the analysis. If the \family typewriter .ic \family default control line has been specified (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:.IC:-Set-Initial" nolink "false" \end_inset ), then the node voltages on the \family typewriter .ic \family default line are used to compute the initial conditions for the devices. IC=... will take precedence over the values given in the \family typewriter .ic \family default control line. If neither IC=... nor the \family typewriter .ic \family default control line is given for a specific node, node voltage zero is assumed. \end_layout \begin_layout Standard Look at the description on the \family typewriter .ic \family default control line ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.IC:-Set-Initial" nolink "false" \end_inset ) for its interpretation when \family typewriter \series bold uic \family default \series default is not specified. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Transient-noise-analysis" \end_inset Transient noise analysis (at low frequency) \end_layout \begin_layout Standard In contrast to the analysis types described above, the transient noise simulation (noise current or voltage versus time) is not implemented as a dot command, but is integrated with the independent voltage source \family typewriter vsrc \family default ( \family typewriter isrc \family default not yet available) (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Transient-noise-source" nolink "false" \end_inset ) and used in combination with the \family typewriter .tran \family default transient analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.TRAN:-Transient-Analysis" nolink "false" \end_inset ). \end_layout \begin_layout Standard Transient noise analysis deals with noise currents or voltages added to your circuits as a time dependent signal of randomly generated voltage excursion on top of a fixed dc voltage. The sequence of voltage values has random amplitude, but equidistant time intervals, selectable by the user (parameter \family typewriter NT \family default ). The resulting voltage waveform is differentiable and thus does not require any modifications of the matrix solving algorithms. \end_layout \begin_layout Standard White noise is generated by the ngspice random number generator, applying the Box-Muller transform. Values are generated on the fly, each time when a breakpoint is hit. \end_layout \begin_layout Standard The 1/f noise is generated with an algorithm provided by N. J. Kasdin (` \shape italic Discrete simulation of colored noise and stochastic processes and \begin_inset Formula $1/f^{a}$ \end_inset power law noise generation \shape default ', Proceedings of the IEEE, Volume 83, Issue 5, May 1995 Page(s):802–827). The noise sequence (one for each voltage/current source with 1/f selected) is generated upon start up of the simulator and stored for later use. The number of points is determined by the total simulation time divided by \family typewriter NT \family default , rounded up the the nearest power of 2. Each time a breakpoint ( \begin_inset Formula $n\star NT$ \end_inset , relevant to the noise signal) is hit, the next value is retrieved from the sequence. \end_layout \begin_layout Standard If you want a random, but reproducible sequence, you may select a seed value for the random number generator by adding \end_layout \begin_layout Standard \family typewriter setseed nn \end_layout \begin_layout Standard to the \family sans spinit \family default or \family sans .spiceinit \family default file, \family typewriter nn \family default being a positive integer number. \end_layout \begin_layout Standard The transient noise analysis will allow the simulation of the three most important noise sources. Thermal noise is described by the Gaussian white noise. Flicker noise (pink noise or 1 over f noise) with an exponent between 0 and 2 is provided as well. Shot noise is dependent on the current flowing through a device and may be simulated by applying a non-linear source as demonstrated in the following example: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * Shot noise test with B source, diode \end_layout \begin_layout Plain Layout * voltage on device (diode, forward) \end_layout \begin_layout Plain Layout Vdev out 0 DC 0 PULSE(0.4 0.45 10u) \end_layout \begin_layout Plain Layout * diode, forward direction, to be modeled with noise \end_layout \begin_layout Plain Layout D1 mess 0 DMOD \end_layout \begin_layout Plain Layout .model DMOD D IS=1e-14 N=1 \end_layout \begin_layout Plain Layout X1 0 mess out ishot \end_layout \begin_layout Plain Layout * device between 1 and 2 \end_layout \begin_layout Plain Layout * new output terminals of device including noise: 1 and 3 \end_layout \begin_layout Plain Layout .subckt ishot 1 2 3 \end_layout \begin_layout Plain Layout * white noise source with rms 1V \end_layout \begin_layout Plain Layout * 20000 sample points \end_layout \begin_layout Plain Layout VNG 0 11 DC 0 TRNOISE(1 1n 0 0) \end_layout \begin_layout Plain Layout *measure the current i(v1) \end_layout \begin_layout Plain Layout V1 2 3 DC 0 \end_layout \begin_layout Plain Layout * calculate the shot noise \end_layout \begin_layout Plain Layout * sqrt(2*current*q*bandwidth) \end_layout \begin_layout Plain Layout BI 1 3 I=sqrt(2*abs(i(v1))*1.6e-19*1e7)*v(11) \end_layout \begin_layout Plain Layout .ends ishot \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .tran 1n 20u \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot (-1)*i(vdev) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The selection of the delta time step ( \family typewriter NT \family default ) is worth discussing. Gaussian white noise has unlimited bandwidth and thus unlimited energy content. This is unrealistic. The bandwidth of real noise is limited, but it is still called `White' if it is the same level throughout the frequency range of interest, e.g. the bandwidth of your system. Thus you may select \family typewriter NT \family default to be a factor of 10 smaller than the frequency limit of your circuit. A thorough analysis is still needed to clarify the appropriate factor. The transient method is probably most suited to circuits including switches, which are not amenable to the small signal \family typewriter .NOISE \family default analysis (Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.NOISE:-Noise-Analysis" nolink "false" \end_inset ). \end_layout \begin_layout Standard There is a price you have to pay for transient noise analysis: the number of required time steps, and thus the simulation time, increases. \end_layout \begin_layout Standard In addition to white and 1/f noise the independent voltage and current sources offer a random telegraph signal ( \family typewriter RTS \family default ) noise source, also known as burst noise or popcorn noise, again for transient analysis. For each voltage (current) source offering \family typewriter RTS \family default noise an individual noise amplitude is required for input, as well as a mean capture time and a mean emission time. The amplitude resembles the influence of a single trap on the current or voltage. The capture and emission times emulate the filling and emptying of the trap, typically following a Poisson process. They are generated from an random exponential distribution with respective mean values given by the user. To simulate an ensemble of traps, you may combine several current or voltage sources with different parameters. \end_layout \begin_layout Standard All three sources (white, 1/f, and \family typewriter RTS \family default ) may be combined in a single command line. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout RTS noise example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * white noise, 1/f noise, RTS noise \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * voltage source \end_layout \begin_layout Plain Layout VRTS2 13 12 DC 0 trnoise(0 0 0 0 5m 18u 30u) \end_layout \begin_layout Plain Layout VRTS3 11 0 DC 0 trnoise(0 0 0 0 10m 20u 40u) \end_layout \begin_layout Plain Layout VALL 12 11 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout VW1of 21 0 DC trnoise(1m 1u 1.0 0.1m) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * current source \end_layout \begin_layout Plain Layout IRTS2 10 0 DC 0 trnoise(0 0 0 0 5m 18u 30u) \end_layout \begin_layout Plain Layout IRTS3 10 0 DC 0 trnoise(0 0 0 0 10m 20u 40u) \end_layout \begin_layout Plain Layout IALL 10 0 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u) \end_layout \begin_layout Plain Layout R10 10 0 1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout IW1of 9 0 DC trnoise(1m 1u 1.0 0.1m) \end_layout \begin_layout Plain Layout Rall 9 0 1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * sample points \end_layout \begin_layout Plain Layout .tran 1u 500u \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot v(13) v(21) \end_layout \begin_layout Plain Layout plot v(10) v(9) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .end \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Some details on \family typewriter RTS \family default noise modeling are available in a recent article \begin_inset CommandInset citation LatexCommand cite key "key-20" literal "true" \end_inset , available \begin_inset CommandInset href LatexCommand href name "here" target "http://www.see.ed.ac.uk/~tbt/iscas09.pdf" literal "false" \end_inset . \end_layout \begin_layout Standard \emph on This transient noise feature is still experimental. \emph default \end_layout \begin_layout Standard The following questions (among others) are to be solved: \end_layout \begin_layout Itemize clarify the theoretical background \end_layout \begin_layout Itemize noise limit of plain ngspice (numerical solver, fft etc.) \end_layout \begin_layout Itemize time step ( \family typewriter NT \family default ) selection \end_layout \begin_layout Itemize calibration of noise spectral density \end_layout \begin_layout Itemize how to generate noise from a transistor model \end_layout \begin_layout Itemize application benefits and limits \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.PSS:-Periodic_Steady_State-Analysis" \end_inset .PSS: Periodic Steady State Analysis \end_layout \begin_layout Standard \emph on Experimental code, not yet made publicly available. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .pss gfreq tstab oscnob psspoints harms sciter steadycoeff \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .pss 150 200e-3 2 1024 11 50 5e-3 uic \end_layout \begin_layout Plain Layout .pss 624e6 1u v_plus 1024 10 150 5e-3 uic \end_layout \begin_layout Plain Layout .pss 624e6 500n bout 1024 10 100 5e-3 uic \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter \series bold gfreq \family default \series default is guessed frequency of fundamental suggested by user. When performing transient analysis the PSS algorithm tries to infer a new rough guess \family typewriter \series bold rgfreq \family default \series default on the fundamental. If \family typewriter \series bold gfreq \family default \series default is out of \begin_inset Formula $\pm$ \end_inset 10% with respect to \family typewriter \series bold rgfreq \family default \series default then \family typewriter \series bold gfreq \family default \series default is discarded. \end_layout \begin_layout Standard \family typewriter \series bold tstab \family default \series default is stabilization time before the shooting begin to search for the PSS. It has to be noticed that this parameter heavily influence the possibility to reach the PSS. Thus is a good practice to ensure a circuit to have a right \family typewriter \series bold tstab \family default \series default , e.g. performing a separate TRAN analysis before to run PSS analysis. \end_layout \begin_layout Standard \family typewriter \series bold oscnob \family default \series default is the node or branch where the oscillation dynamic is expected. PSS analysis will give a brief report of harmonic content at this node or branch. \end_layout \begin_layout Standard \family typewriter \series bold psspoints \family default \series default is number of step in evaluating predicted period after convergence is reached. It is useful only in Time Domain plots. However this number should be higher than 2 times the requested \family typewriter \series bold harms \family default \series default . Otherwise the PSS analysis will properly adjust it. \end_layout \begin_layout Standard \family typewriter \series bold harms \family default \series default number of harmonics to be calculated as requested by the user. \end_layout \begin_layout Standard \family typewriter \series bold sciter \family default \series default number of allowed shooting cycle iterations. Default is 50. \end_layout \begin_layout Standard \family typewriter \series bold steady_coeff \family default \series default is the weighting coefficient for calculating the Global Convergence Error (GCE), which is the reference value in order to infer is convergence is reached. The lower \family typewriter \series bold steady_coeff \family default \series default is set, the higher the accuracy of predicted frequency can be reached but at longer analysis time and \family typewriter \series bold sciter \family default \series default number. Default is 1e-3. \end_layout \begin_layout Standard \family typewriter \series bold uic \family default \series default (use initial conditions) is an optional keyword that indicates that the user does not want ngspice to solve for the quiescent operating point before beginning the transient analysis. If this keyword is specified, ngspice uses the values specified using IC=... on the various elements as the initial transient condition and proceeds with the analysis. If the \family typewriter .ic \family default control line has been specified, then the node voltages on the \family typewriter .ic \family default line are used to compute the initial conditions for the devices. Look at the description on the \family typewriter .ic \family default control line for its interpretation when \family typewriter \series bold uic \family default \series default is not specified. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "subsec:.MEAS" \end_inset Measurements after AC, DC and Transient Analysis \end_layout \begin_layout Subsection .meas(ure) \end_layout \begin_layout Standard The \series bold .meas \series default or \series bold .measure \series default statement (and its equivalent \series bold meas \series default command, see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Meas*:-Mesurements-on" nolink "false" \end_inset ) are used to analyze the output data of a tran, ac, or dc simulation. The command is executed immediately after the simulation has finished. \end_layout \begin_layout Subsection batch versus interactive mode \end_layout \begin_layout Standard \family typewriter .meas \family default analysis may not be used in batch mode ( \family typewriter \series bold -b \family default \series default command line option), if an output file (rawfile) is given at the same time ( \family typewriter \series bold -r \series default rawfile \family default command line option). In this batch mode ngspice will write its simulation output data directly to the output file. The data is not kept in memory, thus is no longer available for further analysis. This is done to allow a very large output stream with only a relatively small memory usage. For \family typewriter .meas \family default to be active you need to run the batch mode with a \family typewriter .plot \family default or \family typewriter .print \family default command. A better alternative may be to start ngspice in interactive mode. \end_layout \begin_layout Standard If you need batch like operation, you may add a \family typewriter .control ... .endc \family default section to the input file: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout *input file \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout .tran 1ns 1000ns \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout ********************************* \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout write outputfile data \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout ********************************* \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard and start ngspice in interactive mode, e.g. by running the command \end_layout \begin_layout Standard \family typewriter ngspice inputfile \family default . \end_layout \begin_layout Standard \family typewriter .meas \family default then prints its user-defined data analysis to the standard output. The analysis includes propagation, delay, rise time, fall time, peak-to-peak voltage, minimum or maximum voltage, the integral or derivative over a specified period and several other user defined values. \end_layout \begin_layout Subsection General remarks \end_layout \begin_layout Standard The measure type \family typewriter {DC|AC|TRAN|SP} \family default depends on the data that is to be evaluated, either originating from a dc analysis, an ac analysis, or a transient simulation. The type \family typewriter SP \family default to analyze a spectrum from the \family typewriter spec \family default or \family typewriter fft \family default commands is only available when executed in a \family typewriter meas \family default command, see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Meas*:-Mesurements-on" nolink "false" \end_inset . \end_layout \begin_layout Standard \series bold result \series default will be a vector containing the result of the measurement. \family typewriter trig_variable \family default , \family typewriter targ_variable \family default , and \family typewriter out_variable \family default are vectors stemming from the simulation, e.g. a voltage vector v(out). \end_layout \begin_layout Standard \family typewriter VAL \family default \series bold = \family typewriter \series default val \family default expects a real number val. It may be as well a parameter delimited by \family typewriter '' or {} \family default expanding to a real number. \end_layout \begin_layout Standard \family typewriter TD \family default \series bold = \family typewriter \series default td \family default and \family typewriter AT \family default \series bold = \family typewriter \series default time \family default expect a time value if measure type is \family typewriter tran \family default . For \family typewriter ac \family default and \family typewriter sp, AT \family default will be a frequency value, \family typewriter TD \family default is ignored. For \family typewriter dc \family default analysis, \family typewriter AT \family default is a voltage (or current), \family typewriter TD \family default is ignored as well. \end_layout \begin_layout Standard \family typewriter CROSS \family default \series bold =# \series default requires an integer number #. \family typewriter CROSS \family default \series bold = \family typewriter \series default LAST \family default is possible as well. The same is expected by \family typewriter RISE \family default and \family typewriter FALL \family default . \end_layout \begin_layout Standard Frequency and time values may start at 0 and extend to positive real numbers. Voltage (or current) inputs for the independent (scale) axis in a dc analysis may start or end at arbitrary real valued numbers. \end_layout \begin_layout Standard Please note that not all of the \family typewriter .measure \family default commands have been implemented. \end_layout \begin_layout Subsection Input \end_layout \begin_layout Standard In the following lines you will get some explanation on the \family typewriter .measure \family default commands. A simple simulation file with two sines of different frequencies may serve as an example. The transient simulation delivers time as the independent variable and two voltages as output (dependent variables). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Input file: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout File: simple-meas-tran.sp \end_layout \begin_layout Plain Layout * Simple .measure examples \end_layout \begin_layout Plain Layout * transient simulation of two sine \end_layout \begin_layout Plain Layout * signals with different frequencies \end_layout \begin_layout Plain Layout vac1 1 0 DC 0 sin(0 1 1k 0 0) \end_layout \begin_layout Plain Layout vac2 2 0 DC 0 sin(0 1.2 0.9k 0 0) \end_layout \begin_layout Plain Layout .tran 10u 5m \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .measure tran ... $ for the different inputs see below! \end_layout \begin_layout Plain Layout * \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot v(1) v(2) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard After displaying the general syntax of the \family typewriter .measure \family default statement, some examples are posted, referring to the input file given above. \end_layout \begin_layout Subsection Trig Targ \end_layout \begin_layout Standard \family typewriter .measure \family default according to general form 1 measures the difference in dc voltage, frequency or time between two points selected from one or two output vectors. The current examples all are using transient simulation. Measurements for \family typewriter tran \family default analysis start after a delay time td. If you run other examples with \family typewriter ac \family default simulation or \family typewriter sp \family default ectrum analysis, time may be replaced by frequency, after a \family typewriter dc \family default simulation the independent variable may become a voltage or current. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form 1: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result TRIG trig_variable VAL=val \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + TARG targ_variable \end_layout \begin_layout Plain Layout + VAL=val \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement example (for use in the input file given above): \end_layout \begin_layout Standard \family typewriter .measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=2 \end_layout \begin_layout Standard measures the time difference between v(1) reaching 0.5 V for the first time on its first rising slope (TRIG) versus reaching 0.5 V again on its second rising slope (TARG), i.e. it measures the signal period. \end_layout \begin_layout Standard Output: \end_layout \begin_layout Standard \family typewriter tdiff = 1.000000e-003 targ= 1.083343e-003 trig= 8.334295e-005 \end_layout \begin_layout Standard Measure statement example: \end_layout \begin_layout Standard \family typewriter .measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=3 \end_layout \begin_layout Standard measures the time difference between v(1) reaching 0.5 V for the first time on its rising slope versus reaching 0.5 V on its rising slope for the third time (i.e. two periods). \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 FALL=1 \end_layout \begin_layout Standard measures the time difference between v(1) reaching 0.5V for the first time on its rising slope versus reaching 0.5 V on its first falling slope. \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran tdiff TRIG v(1) VAL=0 FALL=3 TARG v(2) VAL=0 FALL=3 \end_layout \begin_layout Standard measures the time difference between v(1) reaching 0V its third falling slope versus v(2) reaching 0 V on its third falling slope. \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran tdiff TRIG v(1) VAL=-0.6 CROSS=1 TARG v(2) VAL=-0.8 CROSS=1 \end_layout \begin_layout Standard measures the time difference between v(1) crossing -0.6 V for the first time (any slope) versus v(2) crossing -0.8 V for the first time (any slope). \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran tdiff TRIG AT=1m TARG v(2) VAL=-0.8 CROSS=3 \end_layout \begin_layout Standard measures the time difference between the time point 1ms versus the time when v(2) crosses -0.8 V for the third time (any slope). \end_layout \begin_layout Subsection Find ... When \end_layout \begin_layout Standard The \family typewriter FIND \family default and \family typewriter WHEN \family default functions allow measuring any dependent or independent time, frequency, or dc parameter, when two signals cross each other or a signal crosses a given value. Measurements start after a delay \family typewriter TD \family default and may be restricted to a range between \family typewriter FROM \family default and \family typewriter TO \family default . \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form 2: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result WHEN out_variable=val \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran teval WHEN v(2)=0.7 CROSS=LAST \end_layout \begin_layout Standard measures the time point when v(2) crosses 0.7 V for the last time (any slope). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form 3: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result \end_layout \begin_layout Plain Layout + WHEN out_variable=out_variable2 \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran teval WHEN v(2)=v(1) RISE=LAST \end_layout \begin_layout Standard measures the time point when v(2) and v(1) are equal, v(2) rising for the last time. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form 4: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result FIND out_variable \end_layout \begin_layout Plain Layout + WHEN out_variable2=val \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran yeval FIND v(2) WHEN v(1)=-0.4 FALL=LAST \end_layout \begin_layout Standard returns the dependent (y) variable drawn from v(2) at the time point when v(1) equals a value of -0.4, v(1) falling for the last time. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form 5: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result FIND out_variable \end_layout \begin_layout Plain Layout + WHEN out_variable2=out_variable3 \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran yeval FIND v(2) WHEN v(1)=v(3) FALL=2 \end_layout \begin_layout Standard returns the dependent (y) variable drawn from v(2) at the time point when v(1) crosses v(3), v(1) falling for the second time. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form 6: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result FIND out_variable AT=val \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran yeval FIND v(2) AT=2m \end_layout \begin_layout Standard returns the dependent (y) variable drawn from v(2) at the time point 2 ms (given by \family typewriter AT \family default =time). \end_layout \begin_layout Subsection \family typewriter \series medium AVG|MIN|MAX|PP|RMS|MIN_AT|MAX_AT \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form 7: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result \end_layout \begin_layout Plain Layout + {AVG|MIN|MAX|PP|RMS|MIN_AT|MAX_AT} \end_layout \begin_layout Plain Layout + out_variable \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statements: \end_layout \begin_layout Standard \family typewriter .measure tran ymax MAX v(2) from=2m to=3m \end_layout \begin_layout Standard returns the maximum value of v(2) inside the time interval between 2 ms and 3 ms. \end_layout \begin_layout Standard \family typewriter .measure tran tymax MAX_AT v(2) from=2m to=3m \end_layout \begin_layout Standard returns the time point of the maximum value of v(2) inside the time interval between 2 ms and 3 ms. \end_layout \begin_layout Standard \family typewriter .measure tran ypp PP v(1) from=2m to=4m \end_layout \begin_layout Standard returns the peak to peak value of v(1) inside the time interval between 2 ms and 4 ms. \end_layout \begin_layout Standard \family typewriter .measure tran yrms RMS v(1) from=2m to=4m \end_layout \begin_layout Standard returns the root mean square value of v(1) inside the time interval between 2 ms and 4 ms. \end_layout \begin_layout Standard \family typewriter .measure tran yavg AVG v(1) from=2m to=4m \end_layout \begin_layout Standard returns the average value of v(1) inside the time interval between 2 ms and 4 ms. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Integ" \end_inset Integ \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form 8: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result INTEG out_variable \end_layout \begin_layout Plain Layout + \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .measure tran yint INTEG v(2) from=2m to=3m \end_layout \begin_layout Standard returns the area under v(2) inside the time interval between 2 ms and 3 ms. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:param" \end_inset param \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form 9: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result param='expression' \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Measure statement: \end_layout \begin_layout Standard \family typewriter .param fval=5 \end_layout \begin_layout Standard \family typewriter .measure tran yadd param='fval + 7' \end_layout \begin_layout Standard will evaluate the given expression fval + 7 and return the value 12. \end_layout \begin_layout Standard \shape italic 'Expression' \shape default is evaluated according to the rules given in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Syntax-of-expressions" nolink "false" \end_inset during start up of ngspice. It may contain parameters defined with the \family typewriter .param \family default statement. It may also contain parameters resulting from preceding \family typewriter .meas \family default statements. \end_layout \begin_layout Standard \family typewriter .param vout_diff=50u \end_layout \begin_layout Standard \family typewriter ... \end_layout \begin_layout Standard \family typewriter .measure tran tdiff TRIG AT=1m TARG v(2) VAL=-0.8 CROSS=3 \end_layout \begin_layout Standard \family typewriter .meas tran bw_chk param='(tdiff < vout_diff) ? 1 : 0' \end_layout \begin_layout Standard will evaluate the given ternary function and return the value 1 in \family typewriter bw_chk \family default , if \family typewriter tdiff \family default measured is smaller than parameter \family typewriter vout_diff \family default . \end_layout \begin_layout Standard The expression may not contain vectors like v(10), e.g. anything resulting directly from a simulation. This may be handled with the following \family typewriter .meas \family default command option. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:par('expression'-)" \end_inset par( \series medium \shape italic 'expression' \series default \shape default \family typewriter ) \end_layout \begin_layout Standard The \family typewriter par( \family default \shape italic 'expression' \family typewriter \shape default ) \family default option ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:par('expression'):-Algebraic-expressions" nolink "false" \end_inset ) allows the use of algebraic expressions on the \family typewriter .measure \family default lines. Every \family sans out_variable \family default may be replaced by \family typewriter par \family default ( \shape italic 'expression' \shape default ) using the general forms 1\SpecialChar ldots 9 described above. Internally \family typewriter par \family default ( \shape italic 'expression' \shape default ) is substituted by a vector according to the rules of the B source (Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" nolink "false" \end_inset ). A typical example of the general form is shown below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form 10: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|TRAN|AC|SP} result \end_layout \begin_layout Plain Layout + FIND par('expression') AT=val \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The measure statement \end_layout \begin_layout Standard \family typewriter .measure tran vtest find par('(v(2)*v(1)') AT=2.3m \end_layout \begin_layout Standard returns the product of the two voltages at time point 2.3 ms. \end_layout \begin_layout Standard Note that a B-source, and therefore the \family typewriter par('...') \family default feature, operates on values of type complex in AC analysis mode. \end_layout \begin_layout Standard Both \family typewriter param \family default and \family typewriter par \family default are not available for the \family typewriter meas \family default command ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Meas*:-Mesurements-on" nolink "false" \end_inset ) inside of a .control section, where \family typewriter meas \family default with \family typewriter par \family default or \family typewriter param \family default may be replaced by \family typewriter let \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Let:-Assign-a" nolink "false" \end_inset ). \end_layout \begin_layout Subsection Deriv \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result DERIV out_variable \end_layout \begin_layout Plain Layout + AT=val \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result DERIV out_variable \end_layout \begin_layout Plain Layout + WHEN out_variable2=val \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .MEASURE {DC|AC|TRAN|SP} result DERIV out_variable \end_layout \begin_layout Plain Layout + WHEN out_variable2=out_variable3 \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout + \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection More examples \end_layout \begin_layout Standard Some other examples, also showing the use of parameters, are given below. Corresponding demonstration input files are distributed with ngspice in folder /examples/measure. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Other examples: \end_layout \begin_layout LyX-Code \begin_inset listings lstparams "breaklines=true" inline false status open \begin_layout Plain Layout .meas tran inv_delay2 trig v(in) val='vp/2' td=1n fall=1 \end_layout \begin_layout Plain Layout + targ v(out) val='vp/2' rise=1 \end_layout \begin_layout Plain Layout .meas tran test_data1 trig AT = 1n targ v(out) \end_layout \begin_layout Plain Layout + val='vp/2' rise=3 \end_layout \begin_layout Plain Layout .meas tran out_slew trig v(out) val='0.2*vp' rise=2 \end_layout \begin_layout Plain Layout + targ v(out) val='0.8*vp' rise=2 \end_layout \begin_layout Plain Layout .meas tran delay_chk param='(inv_delay < 100ps) ? 1 : 0' \end_layout \begin_layout Plain Layout .meas tran skew when v(out)=0.6 \end_layout \begin_layout Plain Layout .meas tran skew2 when v(out)=skew_meas \end_layout \begin_layout Plain Layout .meas tran skew3 when v(out)=skew_meas fall=2 \end_layout \begin_layout Plain Layout .meas tran skew4 when v(out)=skew_meas fall=LAST \end_layout \begin_layout Plain Layout .meas tran skew5 FIND v(out) AT=2n \end_layout \begin_layout Plain Layout .meas tran v0_min min i(v0) \end_layout \begin_layout Plain Layout + from='dfall' to='dfall+period' \end_layout \begin_layout Plain Layout .meas tran v0_avg avg i(v0) \end_layout \begin_layout Plain Layout + from='dfall' to='dfall+period' \end_layout \begin_layout Plain Layout .meas tran v0_integ integ i(v0) \end_layout \begin_layout Plain Layout + from='dfall' to='dfall+period' \end_layout \begin_layout Plain Layout .meas tran v0_rms rms i(v0) \end_layout \begin_layout Plain Layout + from='dfall' to='dfall+period' \end_layout \begin_layout Plain Layout .meas dc is_at FIND i(vs) AT=1 \end_layout \begin_layout Plain Layout .meas dc is_max max i(vs) from=0 to=3.5 \end_layout \begin_layout Plain Layout .meas dc vds_at when i(vs)=0.01 \end_layout \begin_layout Plain Layout .meas ac vout_at FIND v(out) AT=1MEG \end_layout \begin_layout Plain Layout .meas ac vout_atd FIND vdb(out) AT=1MEG \end_layout \begin_layout Plain Layout .meas ac vout_max max v(out) from=1k to=10MEG \end_layout \begin_layout Plain Layout .meas ac freq_at when v(out)=0.1 \end_layout \begin_layout Plain Layout .meas ac vout_diff trig v(out) val=0.1 rise=1 targ v(out) \end_layout \begin_layout Plain Layout + val=0.1 fall=1 \end_layout \begin_layout Plain Layout .meas ac fixed_diff trig AT = 10k targ v(out) \end_layout \begin_layout Plain Layout + val=0.1 rise=1 \end_layout \begin_layout Plain Layout .meas ac vout_avg avg v(out) from=10k to=1MEG \end_layout \begin_layout Plain Layout .meas ac vout_integ integ v(out) from=20k to=500k \end_layout \begin_layout Plain Layout .meas ac freq_at2 when v(out)=0.1 fall=LAST \end_layout \begin_layout Plain Layout .meas ac bw_chk param='(vout_diff < 100k) ? 1 : 0' \end_layout \begin_layout Plain Layout .meas ac vout_rms rms v(out) from=10 to=1G \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:SOA-Warnings" \end_inset Safe Operating Area (SOA) warning messages \end_layout \begin_layout Standard By setting \family typewriter .option warn=1, \family default the Safe Operation Area check algorithm is enabled. In this case for \family typewriter .op \family default , \family typewriter .dc \family default and \family typewriter .tran \family default analysis warning messages are issued if the branch voltages of devices (Resistors, Capacitors, Diodes, BJTs and MOSFETs), or the currents and dissipated power (Diodes, and BJTs), or the resulting temperature (Diodes) exceed limits that are specified by model parameters. All these parameters are positive with default value of infinity. For the bipolar VBIC model ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:VBIC-(levels-4" nolink "false" \end_inset ) \family typewriter .option warn=2 \family default will add additional operating point info \end_layout \begin_layout Standard The check is executed after Newton-Raphson iteration is finished i.e. in transient analysis in each time step. The user can specify an additional \family typewriter .option \family default \family typewriter maxwarns \family default (default: 5) to limit the count of messages. \end_layout \begin_layout Standard The output goes on default to stdout or alternatively to a file specified by command line option \family typewriter --soa-log=filename \family default . \end_layout \begin_layout Standard To achive SOA checking, add some or all of these parameters with suitable limit values to the .model line of the respective device. \end_layout \begin_layout Subsection Resistor and Capacitor SOA model parameters \end_layout \begin_layout Enumerate \family typewriter Bv_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vr| or |Vc| exceed \family typewriter Bv_max \family default , SOA warning is issued. \end_layout \begin_layout Subsection Diode SOA model parameters \end_layout \begin_layout Enumerate \family typewriter Bv_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vj| exceeds \family typewriter Bv_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Fv_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vf| exceeds \family typewriter Fv_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Id_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Id| exceeds \family typewriter Id_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Pd_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If power exceeds \family typewriter Pd_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Te_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If temperature exceeds \family typewriter Te_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter rth0 \family default : \begin_inset space \hspace{} \length 1.4cm \end_inset Thermal resistance between junction and ambient. \end_layout \begin_layout Enumerate \family typewriter tnom \family default : \begin_inset space \hspace{} \length 1.4cm \end_inset Nominal temperature where all parameters have been measured at. \end_layout \begin_layout Standard Three SOA modes are available. All modes check for \family typewriter Bv_max \family default , \family typewriter Vf_max \family default , and \family typewriter Id_max \family default . \end_layout \begin_layout Standard If self-heating ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Self-Heating-model" nolink "false" \end_inset ) is switched on, and \family typewriter Te_max \family default , \family typewriter tnom \family default and \family typewriter rth0 \family default are given, then a derating for the maximam allowed power dissipation is calculated, and power and current temperature are checked against their max. allowed values. \end_layout \begin_layout Standard \begin_inset Formula $pd_{max}=pd_{maxmod}-(temp_{curr}-tnom)/rth0$ \end_inset \end_layout \begin_layout Standard If self-heating is switched off, and \family typewriter rth0 \family default and \family typewriter tnom \family default are given, then a static max. power derating is calculated, taking the device temperature (set by its default value 27 °C, or the global \family typewriter .temp \family default value, or the device specific instance parameter \family typewriter temp \family default ) into account. The reference temperature is \family typewriter tnom \family default . \end_layout \begin_layout Standard \begin_inset Formula $pd_{max}=pd_{maxmod}-(temp-tnom)/rth0$ \end_inset \end_layout \begin_layout Standard If \family typewriter rth0 \family default or \family typewriter tnom \family default are not given, no derating is calculated, the power disspation is simply checked against \family typewriter Pd_max. \end_layout \begin_layout Subsection BJT SOA model parameters \end_layout \begin_layout Subsubsection Gummel-Poon (levels 1 and 2) \end_layout \begin_layout Standard Bipolar device models level 1 and 2 are supported with all the SOA parameters named below. \end_layout \begin_layout Enumerate \family typewriter Vbe_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vbe| exceeds \family typewriter Vbe_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vbc_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vbc| exceeds \family typewriter Vbc_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vce_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vce| exceeds \family typewriter Vce_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vcs_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vcs| exceeds \family typewriter Vcs_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Ic_max \family default : \begin_inset space \hspace{} \length 1.2cm \end_inset If |Ic| exceeds \family typewriter Ic_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Ib_max \family default : \begin_inset space \hspace{} \length 1.2cm \end_inset If |Ib| exceeds \family typewriter Ib_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Pd_max \family default : \begin_inset space \hspace{} \length 1.2cm \end_inset If power exceeds \family typewriter Pd_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Te_max \family default : \begin_inset space \hspace{} \length 1.2cm \end_inset If temperature exceeds \family typewriter Te_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter rth0 \family default : \begin_inset space \hspace{} \length 1.6cm \end_inset Thermal resistance between junction and ambient. \end_layout \begin_layout Enumerate \family typewriter tnom \family default : \begin_inset space \hspace{} \length 1.6cm \end_inset Nominal temperature where all parameters have been measured at. \end_layout \begin_layout Standard Two SOA modes are available (self-heating is not yet modeled in bipolar level 1 and 2). All modes check for \family typewriter Vbe_max \family default , \family typewriter Vbc_max \family default , \family typewriter Vce_max \family default , \family typewriter Vcs_max \family default , \family typewriter Ic_max \family default and \family typewriter Ib_max \family default . \end_layout \begin_layout Standard If \family typewriter rth0 \family default and \family typewriter tnom \family default are given, then a static max. power derating is calculated, taking the device temperature (set by its default value 27 °C, or the global \family typewriter .temp \family default value, or the device specific instance parameter \family typewriter temp \family default ) into account. The reference temperature is \family typewriter tnom \family default . \end_layout \begin_layout Standard \begin_inset Formula $pd_{max}=pd{}_{maxmod}-(temp-tnom)/rth0$ \end_inset \end_layout \begin_layout Standard If \family typewriter rth0 \family default or \family typewriter tnom \family default are not given, no derating is calculated, the power disspation is simply checked against \family typewriter Pd_max. \end_layout \begin_layout Standard \family typewriter Te_max \family default is not (yet) used. \end_layout \begin_layout Subsubsection HICUM (level 8) \end_layout \begin_layout Standard HICUM2 currently aknowledges the following voltage parameters: \end_layout \begin_layout Enumerate \family typewriter Vbe_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vbe| exceeds \family typewriter Vbe_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vbc_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vbc| exceeds \family typewriter Vbc_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vce_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vce| exceeds \family typewriter Vce_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vcs_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vcs| exceeds \family typewriter Vcs_max \family default , SOA warning is issued. \end_layout \begin_layout Subsubsection \begin_inset CommandInset label LatexCommand label name "subsec:VBIC-(levels-4" \end_inset VBIC (levels 4 and 9) \end_layout \begin_layout Standard VBIC aknowledges the following parameters: \end_layout \begin_layout Enumerate \family typewriter Vbe_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vbe| exceeds \family typewriter Vbe_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vbc_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vbc| exceeds \family typewriter Vbc_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vce_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vce| exceeds \family typewriter Vce_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vcs_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vcs| exceeds \family typewriter Vcs_max \family default , SOA warning is issued. \end_layout \begin_layout Standard As an alternative to the above listed parameters \family typewriter bvbe \family default , \family typewriter bvbc \family default , \family typewriter bvce \family default , and \family typewriter bvsub \family default may be used. \end_layout \begin_layout Standard If \family typewriter .option warn=2 \family default is set, the following parameters (defaults are set to 0.2 V) may be used to determine the current operation point of the device. \end_layout \begin_layout Enumerate \family typewriter vbefwd \family default \begin_inset space \hspace{} \length 1cm \end_inset B-E forward voltage. \end_layout \begin_layout Enumerate \family typewriter vbcfwd \family default \begin_inset space \hspace{} \length 1cm \end_inset B-C forward voltage. \end_layout \begin_layout Standard The following criteria are used: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout op \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout conditions \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout off \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter Vbe <= vbefwd \family default and \family typewriter Vbc <= vbcfwd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout saturation \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter Vbe > vbefwd \family default and \family typewriter Vbc > vbcfwd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout forward \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter Vbe > vbefwd \family default and \family typewriter Vbc <= vbcfwd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout reverse \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter Vbe <= vbefwd \family default and \family typewriter Vbc > vbcfwd \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Substrate leakage due to forward conduction of the collector-substrate diode may be detected using: \end_layout \begin_layout Enumerate \family typewriter vsubfwd \family default \begin_inset space \hspace{} \length 1cm \end_inset Substrate junction forward voltage. \end_layout \begin_layout Subsection MOS SOA model parameters \end_layout \begin_layout Enumerate \family typewriter Vgs_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vgs| exceeds \family typewriter Vgs_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vgd_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vgd| exceeds \family typewriter Vgd_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vgb_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vgb| exceeds \family typewriter Vgb_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vds_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vds| exceeds \family typewriter Vds_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vbs_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vbs| exceeds \family typewriter Vbs_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vbd_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vbd| exceeds \family typewriter Vbd_max \family default , SOA warning is issued. \end_layout \begin_layout Subsection VDMOS SOA model parameters \end_layout \begin_layout Enumerate \family typewriter Vgs_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vgs| exceeds \family typewriter Vgs_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vgd_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vgd| exceeds \family typewriter Vgd_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vds_max \family default : \begin_inset space \hspace{} \length 1cm \end_inset If |Vds| exceeds \family typewriter Vds_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vgsr_max \family default : \begin_inset space \hspace{} \length 0.8cm \end_inset If |Vgsr| exceeds \family typewriter Vgsr_max \family default , SOA warning is issued. \end_layout \begin_layout Enumerate \family typewriter Vgdr_max \family default : \begin_inset space \hspace{} \length 0.8cm \end_inset If |Vgdr| exceeds \family typewriter Vgdr_max \family default , SOA warning is issued. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Batch-Output" \end_inset Batch Output \end_layout \begin_layout Standard The following commands \family typewriter .print \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.PRINT-Lines" nolink "false" \end_inset ), \family typewriter .plot \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.PLOT-Lines" nolink "false" \end_inset ) and \family typewriter .four \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.FOUR:-Fourier-Analysis" nolink "false" \end_inset ) are valid only if ngspice is started in batch mode (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Batch-mode" nolink "false" \end_inset ), whereas \family typewriter .save \family default and the equivalent \family typewriter .probe \family default are aknowledged in all operating modes. \end_layout \begin_layout Standard If you start ngspice in batch mode using the -b command line option, the outputs of \family typewriter .print \family default , \family typewriter .plot \family default , and \family typewriter .four \family default are printed to the console output. You may use the output redirection of your shell to direct this printout into a file (not available with MS Windows GUI). As an alternative, you may extend the ngspice command by specifying an output file: \end_layout \begin_layout Standard \family typewriter ngspice -b -o output.log input.cir \end_layout \begin_layout Standard If you however add the command line option \family typewriter -r \family default to create a rawfile, \family typewriter .print \family default and \family typewriter .plot \family default are ignored. If you want to involve the graphics plot output of ngspice, use the control mode ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Interactive-mode-with" nolink "false" \end_inset ) instead of the \family typewriter -b \family default batch mode option. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.SAVE-Lines" \end_inset .SAVE: Name vector(s) to be saved in raw file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .save vector vector vector ... \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .save i(vin) node1 v(node2) \end_layout \begin_layout Plain Layout .save @m1[id] vsource#branch \end_layout \begin_layout Plain Layout .save all @m2[vdsat] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The vectors listed on the \family typewriter .SAVE \family default line are recorded in the rawfile for use later with ngspice. The standard vector names are accepted. Node voltages may be saved by giving the \emph on nodename \emph default or \family typewriter v( \family default \emph on nodename \family typewriter \emph default ) \family default . Currents through an independent voltage source are given by \family typewriter i( \family default \emph on sourcename \family typewriter \emph default ) \family default or \emph on sourcename \family typewriter \emph default # \family default \emph on branch \emph default . Internal device data are accepted as \family typewriter @ \family default \emph on dev \family typewriter \emph default [ \family default \emph on param \family typewriter \emph default ] \family default . \end_layout \begin_layout Standard If no \family typewriter .SAVE \family default line is given, then the default set of vectors is saved (node voltages and voltage source branch currents). If \family typewriter .SAVE \family default lines are given, only those vectors specified are saved. For more discussion on internal device data, e.g. \family typewriter @m1[id] \family default , see Appendix, Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Accessing-internal-device" nolink "false" \end_inset . If you want to save internal data in addition to the default vector set, add the parameter \series bold all \series default to the additional vectors to be saved. If the command \family typewriter .save vm(out) \family default is given, and you store the data in a rawfile, only the original data \family typewriter v( \family default \emph on out \family typewriter \emph default ) \family default are stored. The request for storing the magnitude is ignored, because this may be added later during rawfile data evaluation with ngspice. See also the section on the interactive command interpreter (Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" nolink "false" \end_inset ) for information on how to use the rawfile. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.PRINT-Lines" \end_inset .PRINT Lines \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .print prtype ov1 \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .print tran v(4) i(vin) \end_layout \begin_layout Plain Layout .print dc v(2) i(vsrc) v(23, 17) \end_layout \begin_layout Plain Layout .print ac vm(4, 2) vr(7) vp(8, 3) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .print \family default line defines the contents of a tabular listing of one to eight output variables. \family typewriter prtype \family default is the type of the analysis ( \family typewriter DC \family default , \family typewriter AC \family default , \family typewriter TRAN \family default , \family typewriter NOISE \family default , or \family typewriter DISTO \family default ) for which the specified outputs are desired. The form for voltage or current output variables is the same as given in the previous section for the \family typewriter print \family default command; Spice2 restricts the output variable to the following forms (though this restriction is not enforced by ngspice): \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \family typewriter V(N1<,N2>) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \noindent specifies the voltage difference between nodes N1 and N2. If N2 (and the preceding comma) is omitted, ground (0) is assumed. See the \family typewriter print \family default command in the previous section for more details. For compatibility with SPICE2, the following five additional values can be accessed for the ac analysis by replacing the `V' in V(N1,N2) with: \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout VR \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Real part \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VI \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Imaginary part \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Magnitude \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VP \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Phase \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout VDB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $20\textrm{log}10(magnitude)$ \end_inset \end_layout \end_inset \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter I(VXXXXXXX) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout specifies the current flowing in the independent voltage source named VXXXXXXX. Positive current flows from the positive node, through the source, to the negative node. (Not yet implemented: For the ac analysis, the corresponding replacements for the letter \family typewriter I \family default may be made in the same way as described for voltage outputs.) \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Output variables for the noise and distortion analyses have a different general form from that of the other analyses. There is no limit on the number of \family typewriter .print \family default lines for each type of analysis. The \family typewriter par \series bold ( \family default \series default \shape italic 'expression' \family typewriter \series bold \shape default ) \family default \series default option ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:par('expression'):-Algebraic-expressions" nolink "false" \end_inset ) allows the use of algebraic expressions in the \family typewriter .print \family default lines. \series bold .width \series default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.width" nolink "false" \end_inset ) selects the maximum number of characters per line. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.PLOT-Lines" \end_inset .PLOT Lines \end_layout \begin_layout Standard \family typewriter .plot \family default creates a printer plot output. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .plot pltype ov1 <(plo1, phi1)> ... ov8> \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .plot dc v(4) v(5) v(1) \end_layout \begin_layout Plain Layout .plot tran v(17, 5) (2, 5) i(vin) v(17) (1, 9) \end_layout \begin_layout Plain Layout .plot ac vm(5) vm(31, 24) vdb(5) vp(5) \end_layout \begin_layout Plain Layout .plot disto hd2 hd3(R) sim2 \end_layout \begin_layout Plain Layout .plot tran v(5, 3) v(4) (0, 5) v(7) (0, 10) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .plot \family default line defines the contents of one plot of from one to eight output variables. \family typewriter pltype \family default is the type of analysis ( \family typewriter DC \family default , \family typewriter AC \family default , \family typewriter TRAN \family default , \family typewriter NOISE \family default , or \family typewriter DISTO \family default ) for which the specified outputs are desired. The syntax for the \family typewriter ov \shape italic i \family default \shape default is identical to that for the \family typewriter .print \family default line and for the \family typewriter plot \family default command in the interactive mode. \end_layout \begin_layout Standard The overlap of two or more traces on any plot is indicated by the letter `X'. When more than one output variable appears on the same plot, the first variable specified is printed as well as plotted. If a printout of all variables is desired, then a companion \family typewriter .print \family default line should be included. There is no limit on the number of \family typewriter .plot \family default lines specified for each type of analysis. The \family typewriter par( \family default \shape italic 'expression' \family typewriter \shape default ) \family default option ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:par('expression'):-Algebraic-expressions" nolink "false" \end_inset ) allows the use of algebraic expressions in the \family typewriter .plot \family default lines. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.FOUR:-Fourier-Analysis" \end_inset .FOUR: Fourier Analysis of Transient Analysis Output \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .four freq ov1 \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .four 100K v(5) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter .four \family default (or Fourier) line controls whether ngspice performs a Fourier analysis as a part of the transient analysis. \family typewriter freq \family default is the fundamental frequency, and \family typewriter ov1 \family default is the desired vector to be analyzed. The analysis is the same as is done by the \family typewriter fourier \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Fourier:-Perform-a" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) command. The \family typewriter par( \family default \shape italic 'expression' \family typewriter \shape default ) \family default option ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:par('expression'):-Algebraic-expressions" nolink "false" \end_inset ) allows the use of algebraic expressions in the \family typewriter .four \family default lines. \end_layout \begin_layout Standard As \family typewriter .four \family default is available only when ngspice is executed in batch mode ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Batch-mode" nolink "false" \end_inset ), and no rawfile selected, you may consider the \family typewriter spec \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Spec:-Create-a-1" nolink "false" \end_inset ), \family typewriter fourier \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Fourier:-Perform-a" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) or \family typewriter fft \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:fft:-fast-Fourier" nolink "false" \end_inset ) commands, when using ngspice in .control mode (with a .control section, \begin_inset CommandInset ref LatexCommand ref reference "subsec:Interactive-mode-with" nolink "false" \end_inset ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.PROBE:-Name-vector(s)" \end_inset .PROBE: Save device node currents, device power dissipation, or differential voltages between arbitrary nodes \end_layout \begin_layout Standard Command \family typewriter .probe \family default enables current measurement at user specified device nodes, as well as (differential) voltage measurements between device nodes. \end_layout \begin_layout Subsubsection \begin_inset CommandInset label LatexCommand label name "subsec:Current-measurement" \end_inset Current measurement \end_layout \begin_layout Standard Current measurement at a device node is achieved by automatically placing a Zero volt voltage source (VSRC, \begin_inset CommandInset ref LatexCommand ref reference "sec:Independent-Sources-for" nolink "false" \end_inset ) between the selected (or all) device node and the net attached to that node. The positive pole of the VSRC is pointing out towards the net, the negative pole towards the device. The resulting output vectors are using the \family sans xx#branch \family default notation (see examples below). Only top level devices are accessible, so device inside of subcircuits are not considered. \end_layout \begin_layout Standard Besides standard devices you may also measure currents at X instance lines (subcircuit calls). If the subcircuit definition (.subckt line) uses named nodes, these are used instead of node numbers (see device u1 in the example below). \end_layout \begin_layout Standard Be careful when \family typewriter .probe alli \family default is given, because the many output vectors generated automatically may require a large amount of memory to store all the current measurement vectors. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form for current measurements on all devices: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .probe alli \end_layout \end_inset \end_layout \begin_layout Plain Layout General form for current measurements on a 2- and multi-terminal device: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .probe I(device) \end_layout \end_inset \end_layout \begin_layout Plain Layout General form for current measurements on a multi-terminal device (one command per terminal): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .probe I(device,node) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * measure current at every node of each device in the circuit \end_layout \begin_layout Plain Layout .probe \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * measure current at node 1 of a two-terminal device \end_layout \begin_layout Plain Layout .probe I(R1) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * measure current at all nodes of a subcircuit invocation \end_layout \begin_layout Plain Layout .probe I(XU1) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * measure current at node no. 2 of a subcircuit invocation \end_layout \begin_layout Plain Layout .probe I(XU1,2) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * measure current at node 3 of a multi-terminal device M4 \end_layout \begin_layout Plain Layout .probe I(MQ4,3) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Resulting output vectors: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout r1#branch \end_layout \begin_layout Plain Layout xu1:trig#branch \end_layout \begin_layout Plain Layout mq4:s#branch \end_layout \end_inset \end_layout \begin_layout Plain Layout Resulting output vectors for \family typewriter .probe alli \family default (excerpt only, example file 555-timer-2.cir): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout ra#branch : current, real, 14579 long \end_layout \begin_layout Plain Layout rb#branch : current, real, 14579 long \end_layout \begin_layout Plain Layout rl#branch : current, real, 14579 long \end_layout \begin_layout Plain Layout time : time, real, 14579 long [default scale] \end_layout \begin_layout Plain Layout xu1:cont#branch : current, real, 14579 long \end_layout \begin_layout Plain Layout xu1:disc#branch : current, real, 14579 long \end_layout \begin_layout Plain Layout xu1:gnd#branch : current, real, 14579 long \end_layout \begin_layout Plain Layout xu1:out#branch : current, real, 14579 long \end_layout \begin_layout Plain Layout xu1:reset#branch : current, real, 14579 long \end_layout \begin_layout Plain Layout xu1:thres#branch : current, real, 14579 long \end_layout \begin_layout Plain Layout xu1:trig#branch : current, real, 14579 long \end_layout \begin_layout Plain Layout xu1:vcc#branch : current, real, 14579 long \end_layout \begin_layout Plain Layout xu2:1#branch : current, real, 14579 long \end_layout \begin_layout Plain Layout xu2:19#branch : current, real, 14579 long \end_layout \begin_layout Plain Layout ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Compared to the approach using command \family typewriter .options savecurrents \family default the resulting vectors from a \family typewriter .probe \family default command are available for every simulation type including AC simulation. A slight disadvantage may be that new nodes are added to the instance matrix, increasing simulation time (typically a little bit only). \end_layout \begin_layout Subsubsection (Differential) voltage measurement \end_layout \begin_layout Standard Differential voltage measurements are achieved by placing a voltage controlled voltage source (VCVS, E device) with its two inputs connected to the nodes specified by the user and gain 1. The output is then saved in a vector with a leading vd_ in its name. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form for (differential) voltage measurements: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .probe v(node1) \end_layout \begin_layout Plain Layout .probe vd(device:node1:node2) \end_layout \begin_layout Plain Layout .probe vd(device1:node1, device2:node2) \end_layout \end_inset \end_layout \begin_layout Plain Layout device, device1, and device2 are device names (first token in an instance line). node1, node2 are either numbers (according to the node sequence in the instance line, e.g. 1, 2, 3, ...), or are node names of known devices (d, g, s, b for MOS of JFET, c, b, e for bipolar. \end_layout \begin_layout Plain Layout \begin_inset VSpace defskip \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * voltage at node named nR1 \end_layout \begin_layout Plain Layout .probe v(nR1) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * voltage across a two-terminal device named R1 \end_layout \begin_layout Plain Layout .probe vd(R1) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * voltage at instance node 1 of device m4 \end_layout \begin_layout Plain Layout .probe vd(m4:1:0) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * voltage between nodes 1 and 3 of device m4 \end_layout \begin_layout Plain Layout .probe vd(m4:1:3) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * voltage between node 1 of device m4 and node 3 of device m5 \end_layout \begin_layout Plain Layout .probe vd(m4:1, m5:3) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * m4, m5 are MOS devices, so the following is equivalent: \end_layout \begin_layout Plain Layout .probe vd(m4:d, m5:s) \end_layout \end_inset \end_layout \begin_layout Plain Layout Resulting output vectors: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout nR1 \end_layout \begin_layout Plain Layout vd_R1 \end_layout \begin_layout Plain Layout vd_m4:d:0 \end_layout \begin_layout Plain Layout vd_m4:d:s \end_layout \begin_layout Plain Layout vd_m3:d_m5:s \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsubsection Measurement of power dissipation in a device \end_layout \begin_layout Standard A power consumption measurement of a device with n nodes consists of two steps: all n device node currents \family typewriter i1, i2, ... , in \family default are measured (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Current-measurement" nolink "false" \end_inset ). Then all node voltages \family typewriter v1 ... vn \family default are measured. A common virtual star point \family typewriter vref \family default is calculated as the mean of all \family typewriter n \family default node voltages. Power is the sum of the products of each node current times its node voltage minus \family typewriter vref \family default . \end_layout \begin_layout Standard \family typewriter P = i1*(v1-vref) + i2*(v2-vref) +...+ in*(vn-vref) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form for power measurements: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .probe p(device) \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * power dissipation of a subcircuit device \end_layout \begin_layout Plain Layout .probe p(XU1) \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * power dissipation in a MOS transistor \end_layout \begin_layout Plain Layout .probe p(MQ1) \end_layout \end_inset \end_layout \begin_layout Plain Layout Resulting output vectors: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout xu1:power \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout mq1:power \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard All new items are added to the list of vectors named by \family typewriter .SAVE \family default (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:.SAVE-Lines" nolink "false" \end_inset ). If .save is not given, only the newly generated \family typewriter .PROBE \family default vectors are saved. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:par('expression'):-Algebraic-expressions" \end_inset par( \series medium \shape italic 'expression' \series default \shape default ): Algebraic expressions for output \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout par('expression') \end_layout \begin_layout Plain Layout output=par('expression') $ not in .measure ac \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .four 1001 sq1=par('v(1)*v(1)') \end_layout \begin_layout Plain Layout .measure tran vtest find par('(v(2)*v(1))') AT=2.3m \end_layout \begin_layout Plain Layout .print tran output=par('v(1)/v(2)') v(1) v(2) \end_layout \begin_layout Plain Layout .plot dc v(1) diff=par('(v(4)-v(2))/0.01') out222 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard With the output lines \family typewriter .four, .plot, .print, .save \family default and in \family typewriter .measure \family default evaluation, it is possible to add algebraic expressions for output, in addition to vectors. All of these output lines accept \family typewriter par \series bold ( \family default \series default \shape italic 'expression' \family typewriter \series bold \shape default ) \family default \series default , where expression is any expression valid for a B source (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:B-source-(ASRC)" nolink "false" \end_inset ). Thus \family sans expression \family default may contain predefined functions, numerical values, constants, simulator output like v(n1) or i(vdb), parameters predefined by a \family typewriter .param \family default statement, and the variables \family typewriter hertz \family default , \family typewriter temper \family default , and \family typewriter time \family default . Note that a B-source, and therefore the \family typewriter par('...') \family default feature, operates on values of type complex in AC analysis mode. \end_layout \begin_layout Standard Internally the expression is replaced by a generated voltage node that is the output of a B source, one node, and the B source implementing \family typewriter par \family default \series bold ( \series default '...' \series bold ) \series default . Several \family typewriter par \family default ('...') are allowed in each line, up to 99 per input file. The internal nodes are named \family sans pa_00 \family default to \family sans pa_99 \family default . An error will occur if the input file contains any of these reserved node names. \end_layout \begin_layout Standard In \family typewriter .four, .plot, .print, .save, \family default but not in \family typewriter .measure, \family default an alternative syntax \begin_inset Newline newline \end_inset \family sans output \family typewriter \series bold = \series default par( \family default \shape italic 'expression' \family typewriter \series bold \shape default ) \family default \series default is possible. \family typewriter par( \family default \shape italic 'expression' \family typewriter \series bold \shape default ) \family default \series default may be used as described above. \family sans output \family default is the name of the new node to replace the expression. So \family sans output \family default has to be unique and a valid node name. \end_layout \begin_layout Standard The syntax of \family sans output \family typewriter \series bold = \series default par( \family default \shape italic expression \family typewriter \series bold \shape default ) \family default \series default is strict: no spaces are allowed between \family typewriter par \family default and \family typewriter (' \family default or between \family typewriter ( \family default and \family typewriter '. \family default Also, \family typewriter (' \family default and \family typewriter ') \family default both are required. There is not much error checking on your input, so if there is a typo, for example, an error may pop up at an unexpected place. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.width" \end_inset .width \end_layout \begin_layout Standard Set the width of a print-out or plot with the following card: \end_layout \begin_layout Standard \family typewriter .with out = 256 \end_layout \begin_layout Standard Parameter \series bold out \series default yields the maximum number of characters plotted in a row, if printing in columns or an ASCII-plot is selected. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:.SNDPARAM-.SNDPRINT-Write" \end_inset .SNDPARAM .SNDPRINT Write sound files *.wav from analogue signals \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .SNDPARAM FILENAME [ SAMPLERATE [FORMAT [V_OFF [V_MULT] [OVERSAMPLING] ] ] ] \end_layout \begin_layout Plain Layout .SNDPRINT PRTYPE OV1 [ OV2 ... OV8 ] \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .sndparam test-io.wav 48000 wav24 1.0 0.0 1.0 \end_layout \begin_layout Plain Layout .sndprint tran v(1) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard For details please see chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Sound-files-(*.wav)" \end_inset . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Measuring-current-in" \end_inset Measuring current through device terminals \end_layout \begin_layout Subsection Using the .probe command \end_layout \begin_layout Standard Device currents (discrete devices or subcircuits) may be measured by the .probe command ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.PROBE:-Name-vector(s)" nolink "false" \end_inset ). Voltage sources for measurements are placed in series to the devices nodes specified by the user. For details please see ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.PROBE:-Name-vector(s)" nolink "false" \end_inset ). \end_layout \begin_layout Subsection Adding a voltage source in series \end_layout \begin_layout Standard The ngspice matrix solver determines node voltages and currents through independent voltage sources. So to measure the currents through a resistor, you may add a voltage source in series with dc voltage 0. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Current measurement with series voltage source \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout *measure current through R1 \end_layout \begin_layout Plain Layout V1 1 0 1 \end_layout \begin_layout Plain Layout R1 1 0 5 \end_layout \begin_layout Plain Layout R2 1 0 10 \end_layout \begin_layout Plain Layout * will become \end_layout \begin_layout Plain Layout V1 1 0 1 \end_layout \begin_layout Plain Layout R1 1 11 5 \end_layout \begin_layout Plain Layout Vmeas 11 0 dc 0 \end_layout \begin_layout Plain Layout R2 1 0 10 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard and the current is available as \end_layout \begin_layout LyX-Code vmeas#branch \end_layout \begin_layout Standard after simulation. \end_layout \begin_layout Subsection Using option 'savecurrents' \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Current measurement by reading internal current data \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout *measure current through R1 and R2 \end_layout \begin_layout Plain Layout V1 1 0 1 \end_layout \begin_layout Plain Layout R1 1 0 5 \end_layout \begin_layout Plain Layout R2 1 0 10 \end_layout \begin_layout Plain Layout .options savecurrents \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The option \series bold savecurrents \series default will add \family typewriter .save \family default lines ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.SAVE-Lines" nolink "false" \end_inset ) like \end_layout \begin_layout Standard \family typewriter .save @r1[i] \end_layout \begin_layout Standard \family typewriter .save @r2[i] \end_layout \begin_layout Standard to your input file information read during circuit parsing. These newly created vectors contain the terminal currents of the devices R1 and R2. \end_layout \begin_layout Standard You will find information of the nomenclature in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Model-and-Device" nolink "false" \end_inset , also how to plot these vectors. The following devices are supported: M, J, Q, D, R, C, L, B, F, G, W, S, I (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Circuit-elements-(device" nolink "false" \end_inset ). For MOSFETdevices only a subset of MOS1 to MOS9 current parameters are included per default (but see options below). Devices in subcircuits are supported as well. The advantage of the data obtained by \family typewriter .options savecurrents \family default is that no extra nodes are required, because the data are retrieved from internal nodes already existing. \end_layout \begin_layout Standard This option however cannot be used in AC simulations, because complex data are not supported. Vectors thus created will be empty after an AC simulation. So for AC you might use one of the two methods (.probe or series voltage source) as previously described. \end_layout \begin_layout Standard Be careful when choosing \family typewriter savecurrents \family default in larger circuits, because 1 to 4 additional output vectors are created per device and this may consume lots of memory. \end_layout \begin_layout Standard Also note that the data thus retrieved may be delayed by on time step after a transient simulation. \end_layout \begin_layout Standard For MOS1, BSIM3 and BSIM4 three special options are available, listing all currents as described in chapters 31.6.1, 31.6.8 and 31.6.9 of the ngspice manual: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Current measurement for MOS transistors with BSIM3 or BSIM4 models: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout *measure all currents of MOS1, BSIM3 and BSIM4 transistors \end_layout \begin_layout Plain Layout .options savecurrents_mos1 \end_layout \begin_layout Plain Layout .options savecurrents_bsim3 \end_layout \begin_layout Plain Layout .options savecurrents_bsim4 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "chap:Starting-ngspice" \end_inset Starting ngspice \end_layout \begin_layout Section Introduction \end_layout \begin_layout Standard Ngspice consists of the simulator and a front-end for data analysis and plotting. Input to the simulator is a netlist file, including commands for circuit analysis and output control. Interactive ngspice can plot data from a simulation on a PC or a workstation display. \end_layout \begin_layout Standard The usual way to run ngspice is by a console command, passing options and at least one netlist file as a parameter. Multiple netlists are concatenated and treated as one, except when the first file is a pure script with parameters \begin_inset CommandInset ref LatexCommand eqref reference "sec:SCRIPTS" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . \end_layout \begin_layout Standard Ngspice on Linux (and OSs like MacOS, Cygwin, BSD, Solaris ...) uses the X Window System for plotting (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:LINUX" nolink "false" \end_inset ) if the environment variable \family typewriter DISPLAY \family default is available. (An X11 server must first be installed on MacOS.) Otherwise, a console mode (non-graphical) interface is used. If you are using X on a workstation, the \family typewriter DISPLAY \family default variable should already be set; if you want to display graphics on a system different from the one you are running ngspice or ngutmeg on, \family typewriter DISPLAY \family default should be of the form \family sans machine:0.0 \family default . See the appropriate documentation on the X Window System for more details. \end_layout \begin_layout Standard The MS Windows GUI version of ngspice has a native graphics interface (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:MS-Windows" nolink "false" \end_inset ). \end_layout \begin_layout Section Where to obtain ngspice \end_layout \begin_layout Standard The actual distribution of ngspice may be downloaded from the \begin_inset CommandInset href LatexCommand href name "ngspice download web page" target "http://sourceforge.net/projects/ngspice/files/" literal "false" \end_inset . The installation for Linux or MS Windows is described in the file \series bold INSTALL \series default to be found in the top level directory. You may also have a look at Chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Compilation-notes" nolink "false" \end_inset of this manual for compiling instructions. \end_layout \begin_layout Standard If you want to check out the source code that is actually under development, you may have a look at the ngspice source code repository, which is stored using the Git Source Code Management (SCM) tool. The Git repository may be browsed on the \begin_inset CommandInset href LatexCommand href name "Git web page" target "http://sourceforge.net/scm/?type=git&group_id=38962" literal "false" \end_inset , also useful for downloading individual files. You may however download (or clone) the complete repository including all source code trees from the console window (Linux, CYGWIN or MSYS/MINGW) by issuing the command (in a single line) \end_layout \begin_layout Standard \family typewriter git clone git://git.code.sf.net/p/ngspice/ngspice \end_layout \begin_layout Standard You need to have Git installed, which is available for all three OSs. The whole source tree is then available in \family sans /ngspice \family default . Compilation and local installation is again described in \series bold INSTALL \series default (or Chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Compilation-notes" nolink "false" \end_inset ). If you later want to update your files and download the recent changes from SourceForge into your local repository, cd into the ngspice directory and just type \end_layout \begin_layout Standard \family typewriter git pull \end_layout \begin_layout Standard git pull will not overwrite modified files in your working directory. To drop your local changes first, you can run \end_layout \begin_layout Standard \family typewriter git reset --hard \end_layout \begin_layout Standard To learn more about git, which can be both powerful and difficult to master, please consult \begin_inset CommandInset href LatexCommand href target "http://git-scm.com/" literal "false" \end_inset , especially: \begin_inset CommandInset href LatexCommand href target "http://git-scm.com/documentation" literal "false" \end_inset , which has pointers to documentation and tutorials. \end_layout \begin_layout Section Command line options for starting ngspice \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Command Synopsis: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ngspice [ -o logfile] [ -r rawfile] [ -b ] [ -i ] [ input files ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Where data file is the standard ngspice rawfile. \end_layout \begin_layout Standard Options are shown below. \end_layout \begin_layout Standard \noindent \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Option \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Long option \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Meaning \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter -n \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter --no-spiceinit \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Don't try to source the file upon start-up. Normally ngspice seeks to find it according to the search folder sequence described in \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" nolink "false" \end_inset . \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter -t TERM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter --terminal=TERM \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The program is being run on a terminal with mfb name term (obsolete). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter -b \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter --batch \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \noindent Run in batch mode. Ngspice reads the default input source (e.g. keyboard) or reads the given input file and performs the analyses specified; output is either Spice2-like line-printer plots ("ascii plots") or a ngspice rawfile. See the following section for details. Note that if the input source is not a terminal (e.g. using the IO redirection notation of "<") ngspice defaults to batch mode (-i overrides). This option is valid for ngspice only. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter -s \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter --server \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Run in server mode. This is like batch mode, except that a temporary rawfile is used and then written to the standard output, preceded by a line with a single "@", after the simulation is done. This mode is used by the ngspice daemon. This option is valid for ngspice only. \end_layout \begin_layout Plain Layout Example for using pipes from the console window: \end_layout \begin_layout Plain Layout \family typewriter cat adder.cir|ngspice -s|more \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter -i \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter --interactive \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Run in interactive mode. This is useful if the standard input is not a terminal but interactive mode is desired. Command completion is not available unless the standard input is a terminal, however. This option is valid for ngspice only. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter -r FILE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter --rawfile=FILE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Use rawfile as the default file into which the results of the simulation are saved. This option is valid for ngspice only. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter -p \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter --pipe \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Allow a program (e.g., xcircuit) to act as a GUI frontend for ngspice through a pipe. Thus ngspice will assume that the input pipe is a tty and allow running in interactive mode. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter -o FILE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter --output=FILE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout All logs generated during a batch run (-b) will be saved in outfile. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter -h \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter --help \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A short help statement of the command line syntax. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter -v \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter --version \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Prints a version information. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter –version-small \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Output small version information \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter -f \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter –version-full \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Output full version information \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter -a \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter --autorun \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Start simulation immediately, as if a control section \end_layout \begin_layout Plain Layout \family typewriter .control \end_layout \begin_layout Plain Layout \family typewriter run \end_layout \begin_layout Plain Layout \family typewriter .endc \end_layout \begin_layout Plain Layout had been added to the input file. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter --soa-log=FILE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout output from Safe Operating Area (SOA) check \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter -D \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter --define \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Set a variable ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Variables" nolink "false" \end_inset ), to be used in a .control section. \end_layout \begin_layout Plain Layout \family typewriter -D var1 \family default will set a boolean variable named var1, \end_layout \begin_layout Plain Layout \family typewriter -D var2=7 \family default will set a variable with its value. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Further arguments to ngspice are taken to be ngspice input files, which are read and saved (if running in batch mode then they are run immediately). Ngspice accepts Spice3 (and also most Spice2) input files, and outputs ASCII plots, Fourier analyses, and node printouts as specified in \family typewriter .plot \family default , \family typewriter .four \family default , and \family typewriter .print \family default cards. If an out parameter is given on a \family typewriter .width \family default card ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.width" nolink "false" \end_inset ), the effect is the same as \family sans set width = .... \family default Since ngspice ASCII plots do not use multiple ranges, however, if vectors together on a \family typewriter .plot \family default card have different ranges they do not provide as much information as they do in a scalable graphics plot. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Starting-options" \end_inset Starting options \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Batch-mode" \end_inset Batch mode \end_layout \begin_layout Standard Let's take as an example the Four-Bit binary adder MOS circuit shown in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:MOS-Four-Bit" nolink "false" \end_inset , stored in a file \family sans adder-mos.cir \family default . You may start the simulation immediately by calling \end_layout \begin_layout Standard \family typewriter ngspice -b -r adder.raw -o adder.log adder-mos.cir \end_layout \begin_layout Standard ngspice will start, simulate according to the \family typewriter .tran \family default command and store the output data in a rawfile adder.raw. Comments, warnings and info messages go to log file adder.log. Commands for batch mode operation are described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "chap:Analyses-and-Output" nolink "false" \end_inset . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Interactive-mode" \end_inset Interactive mode \end_layout \begin_layout Standard If you call \end_layout \begin_layout Standard \family typewriter ngspice \end_layout \begin_layout Standard ngspice will start, load \family sans spinit \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" nolink "false" \end_inset ) and \family sans .spiceinit \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" nolink "false" \end_inset , if available), and then waits for your manual input. Any of the commands described in \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" nolink "false" \end_inset may be chosen, but many of them are useful only after a circuit has been loaded by \end_layout \begin_layout Standard \family typewriter ngspice 1 -> source adder-mos.cir \end_layout \begin_layout Standard others require the simulation to be done already (e.g. plot): \end_layout \begin_layout Standard \family typewriter ngspice 2 ->run \begin_inset Newline newline \end_inset ngspice 3 ->plot allv \end_layout \begin_layout Standard If you call ngspice from the command line with a circuit file as parameter: \end_layout \begin_layout Standard \family typewriter ngspice adder-mos.cir \end_layout \begin_layout Standard ngspice will start, load the circuit file, parse the circuit (same circuit file as above, containing only dot commands (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "chap:Analyses-and-Output" nolink "false" \end_inset ) for analysis and output control). ngspice then just waits for your input. You may start the simulation by issuing the \family typewriter run \family default command. Following completion of the simulation you may analyze the data by any of the commands given in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" nolink "false" \end_inset . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Interactive-mode-with" \end_inset Control mode (Interactive mode with control file or control section) \end_layout \begin_layout Standard If you add the following control section to your input file \family sans adder-mos.cir \family default , you may call \end_layout \begin_layout Standard \family typewriter ngspice adder-mos.cir \end_layout \begin_layout Standard from the command line and see ngspice starting, simulating and then plotting immediately. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Control section: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout save vcc#branch \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot vcc#branch \end_layout \begin_layout Plain Layout rusage all \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Any suitable command listed in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" nolink "false" \end_inset may be added to the control section, as well as control structures described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Control-Structures" nolink "false" \end_inset . Batch-like behavior may be obtained by changing the control section to \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Control section with batch-like behavior: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout save vcc#branch \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout write adder.raw vcc#branch \end_layout \begin_layout Plain Layout quit \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If you put this control section into a file, say \family sans adder-start.sp \family default , you may just add the line \end_layout \begin_layout Standard \family typewriter .include adder-start.sp \end_layout \begin_layout Standard to your input file \family sans adder-mos.cir \family default to obtain the batch-like behavior. In the following example the line \family typewriter .tran ... \family default from the input file is overridden by the \series bold tran \series default command given in the control section. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Control section overriding the \family typewriter .tran \family default command: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout save vcc#branch \end_layout \begin_layout Plain Layout tran 1n 500n \end_layout \begin_layout Plain Layout plot vcc#branch \end_layout \begin_layout Plain Layout rusage time \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The commands within the \family typewriter .control \family default section are executed in the order they are listed and only \series bold after \series default the circuit has been read in and parsed. If you want to have a command being executed \series bold before \series default circuit parsing, you may use the prefix pre_ ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Pre_-execute-commands" nolink "false" \end_inset ) to the command. \end_layout \begin_layout Standard A warning is due however: If your circuit file contains such a control section ( \family typewriter .control \family default ... \family typewriter .endc \family default ), you should \emph on not \emph default start ngspice in batch mode (with -b as parameter). The outcome may be unpredictable! \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Standard-configuration-file" \end_inset Standard configuration file spinit \end_layout \begin_layout Standard At startup ngspice reads its configuration file \family sans spinit \family default . \family sans spinit \family default may be found in a path relative to the location of the ngspice executable \begin_inset Newline newline \end_inset \family sans .. \backslash share \backslash ngspice \backslash scripts \family default . The path may be overridden by setting the environmental variable SPICE_SCRIPTS to a path where \family sans spinit \family default is located. Ngspice for Windows will additionally search for \family sans spinit \family default in the directory where \family sans ngspice.exe \family default resides. If \family sans spinit \family default is not found a warning message is issued, but ngspice continues. \end_layout \begin_layout Standard \family sans spinit \family default contains a script, made of commands from Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" nolink "false" \end_inset , that is run upon start up of ngspice. Aliases (name equivalences) can be set. The asterisk ` \family typewriter * \family default ' comments out a line. If used by ngspice, \family sans spinit \family default will then load the XSPICE code models from a path relative to the current directory where the ngspice executable resides, as well as OpenVAF compiled compact devices models. You may also define absolute paths. \end_layout \begin_layout Standard If the standard path for the libraries (see standard \family sans spinit \family default above or \family typewriter /usr/local/lib/spice \family default under CYGWIN and Linux) is not adequate, you can add the \family sans ./configure \family default options \family typewriter --prefix=/usr --libdir=/usr/lib64 \family default to set the codemodel search path to \family typewriter /usr/lib64/spice \family default . Besides the standard \family typewriter lib \family default only \family typewriter lib64 \family default is acknowledged. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Standard \family sans spinit \family default contents: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * Standard ngspice init file \end_layout \begin_layout Plain Layout alias exit quit \end_layout \begin_layout Plain Layout alias acct rusage all \end_layout \begin_layout Plain Layout ** set the number of threads in openmp \end_layout \begin_layout Plain Layout ** (to the number of physical cores) \end_layout \begin_layout Plain Layout ** default (if compiled with --enable-openmp) is: 2 \end_layout \begin_layout Plain Layout set num_threads=8 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout if $?sharedmode \end_layout \begin_layout Plain Layout unset interactive \end_layout \begin_layout Plain Layout unset moremode \end_layout \begin_layout Plain Layout else \end_layout \begin_layout Plain Layout set interactive \end_layout \begin_layout Plain Layout set x11lineararcs \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * comment out if central osdi management is set up \end_layout \begin_layout Plain Layout * unset osdi_enabled \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * Load the codemodels \end_layout \begin_layout Plain Layout if $?xspice_enabled \end_layout \begin_layout Plain Layout codemodel ../lib/spice/spice2poly.cm \end_layout \begin_layout Plain Layout codemodel ../lib/spice/analog.cm \end_layout \begin_layout Plain Layout codemodel ../lib/spice/digital.cm \end_layout \begin_layout Plain Layout codemodel ../lib/spice/xtradev.cm \end_layout \begin_layout Plain Layout codemodel ../lib/spice/xtraevt.cm \end_layout \begin_layout Plain Layout codemodel ../lib/spice/table.cm \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout * Load the OpenVAF/OSDI models \end_layout \begin_layout Plain Layout if $?osdi_enabled \end_layout \begin_layout Plain Layout osdi ../lib/ngspice/BSIMBULK107.osdi \end_layout \begin_layout Plain Layout osdi ../lib/ngspice/BSIMCMG.osdi \end_layout \begin_layout Plain Layout osdi ../lib/ngspice/psp103_nqs.osdi \end_layout \begin_layout Plain Layout osdi ../lib/ngspice/vbic_4T_et_cf.osdi \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Special care has to be taken when using the ngspice shared library. If you use \family sans ngspice.dll \family default under Windows OS, the standard is to use relative paths for the code models as shown above. However, the path is relative to the calling program, not to the dll. This is fine when \family sans ngspice.dll \family default and the calling program reside in the same directory. If \family sans ngspice.dll \family default is placed in a different directory, please check Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Ngspice-Compilation-under" nolink "false" \end_inset . \end_layout \begin_layout Standard The Linux shared library ... t.b.d. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:User-defined-configuration" \end_inset User defined configuration file .spiceinit \end_layout \begin_layout Standard In addition to \family sans spinit \family default you may define a (personal) configuration file \family sans .spiceinit \family default and put it into any of the following locations. The typical search sequence for \family sans .spiceinit \family default is: \end_layout \begin_layout Enumerate directory from where the netlist will be loaded \end_layout \begin_layout Enumerate user provided directory (in env. variable SPICE_USERINIT_DIR) \end_layout \begin_layout Enumerate current directory \end_layout \begin_layout Enumerate HOME (Linux) \end_layout \begin_layout Enumerate USERPROFILE (Windows). \end_layout \begin_layout Standard HOME (Linux, Cygwin, macOS) may point to \family sans /home/ \family default , or \family sans /root \family default if you are acting as admin. USERPROFILE (MS Windows) is typically \family sans C: \backslash Users \backslash \family default . To find out what directory HOME or USERPROFILE are pointing to, enter the commands \family typewriter set \family default or \family typewriter export \family default into a console window and search for the token. \end_layout \begin_layout Standard In case of ngspice as a shared library item 1. of the list above may read \end_layout \begin_layout Enumerate in the directory Infile_Path received from the caller (to be sent before initialization) \end_layout \begin_layout Standard \family sans .spiceinit \family default will be read in and executed after \family sans spinit \family default , but before any other input file is read. It may contain further scripts, \family typewriter set \family default variables, or issue commands from Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" nolink "false" \end_inset to override commands given in \family sans spinit \family default . For example \family typewriter set filetype=ascii \family default will yield ASCII output in the output data file (rawfile), instead of the compact binary format that is used by default. \family typewriter set ngdebug \family default will yield a lot of additional debug output. Any other contents of the script, e.g. plotting preferences, may be included here also. If the command line option \family typewriter -n \family default is used upon ngspice start up, this file will be ignored. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout \family sans .spiceinit \family default for simulating IC designs with MOS transistor data from PDKs may contain: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * .spiceinit for use with Skywater PDK and ngspice KLU \end_layout \begin_layout Plain Layout set ngbehavior=hsa ; set compatibility for reading \end_layout \begin_layout Plain Layout ; PDK libs \end_layout \begin_layout Plain Layout set no_auto_braces ; omit some time consuming checks \end_layout \begin_layout Plain Layout ; during lib loading \end_layout \begin_layout Plain Layout set ng_nomodcheck ; don't check the model parameters \end_layout \begin_layout Plain Layout option noinit ; don't print operating point data \end_layout \begin_layout Plain Layout option klu ; select KLU as matrix solver \end_layout \begin_layout Plain Layout optran 0 0 0 100p 2n 0 ; don't use dc operating point, \end_layout \begin_layout Plain Layout ; but only transient op \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard set \family typewriter num_threads=8 \family default should be set to the number of physical cores of the computer in use (here for example 8 cores), \family typewriter set ngbehavior=hsa \family default will ensure HSPICE compatibility with some important and essential tweaks for the PDK, \family typewriter set skywaterpdk \family default suppresses time consuming checks during lib loading, assuming 4 nodes for a MOS device and adequately labled parameters. \family typewriter set ng_nomodcheck \family default will suppress some unwanted warnings, \family typewriter option noinit \family default will suppress the (often lengthy) printing of the operating point results. \family typewriter option klu \family default often will yield simulation speed up by a factor of 2 or more. \family typewriter optran ... \family default will skip usual operating point iterations, which for very large circuits consume much time, and replace them by a time integrated operating point estimation. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout \family sans .spiceinit \family default for simulating circuits containing PSPICE-compatible behavioural models may contain: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * User defined ngspice init file \end_layout \begin_layout Plain Layout set filetype=ascii \end_layout \begin_layout Plain Layout *set ngdebug \end_layout \begin_layout Plain Layout *set outputpath=C: \backslash Spice64 \backslash out \end_layout \begin_layout Plain Layout set ngbehavior = ltpsa \end_layout \begin_layout Plain Layout option sparse \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter set ngbehavior = ltpsa \family default will provide PSPICE compatibility. \family typewriter option sparse \family default (maybe omitted) selects the venerable Sparse 1.3 matrix solver, which sometimes is much faster than klu. \end_layout \begin_layout Standard Some editors on MS Windows refuse to save files with leading dot in their names. An alternative name to \family sans .spiceinit \family default is therefore \family sans spice.rc \family default . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Environmental-variables" \end_inset Environmental variables \end_layout \begin_layout Subsection Ngspice specific variables \end_layout \begin_layout Description \family typewriter SPICE_LIB_DIR \family default default: \family sans /usr/local/share/ngspice \family default (Linux, CYGWIN), \family sans C: \backslash Spice \backslash share \backslash ngspice \family default (Windows) \end_layout \begin_layout Description \family typewriter SPICE_EXEC_DIR \family default default: \family sans /usr/local/bin \family default (Linux, CYGWIN), \family sans C: \backslash Spice \backslash bin \family default (Windows) \end_layout \begin_layout Description \family typewriter SPICE_BUGADDR \family default default: \family sans https://ngspice.sourceforge.io/bugrep.html \family default \begin_inset Newline newline \end_inset Where to send bug reports on ngspice. \end_layout \begin_layout Description \family typewriter SPICE_EDITOR \family default default: vi (Linux, CYGWIN), \family sans notepad.exe \family default (MINGW, Visual Studio) \begin_inset Newline newline \end_inset Set the editor called in the \series bold edit \series default command. Always overrides the EDITOR env. variable. \end_layout \begin_layout Description \family typewriter SPICE_ASCIIRAWFILE \family default default: 0 \begin_inset Newline newline \end_inset Format of the rawfile. 0 for binary, and 1 for ascii. \end_layout \begin_layout Description \family typewriter SPICE_NEWS \family default default: \family sans $SPICE_LIB_DIR/news \family default \begin_inset Newline newline \end_inset A file that is copied verbatim to stdout when ngspice starts in interactive mode. \end_layout \begin_layout Description \family typewriter SPICE_HELP_DIR \family default default: \family sans $SPICE_LIB_DIR/helpdir \family default \begin_inset Newline newline \end_inset Help directory, not used in Windows mode \end_layout \begin_layout Description \family typewriter SPICE_HOST \family default default: empty string \begin_inset Newline newline \end_inset Used in the \series bold rspice \series default command (probably obsolete, to be documented) \end_layout \begin_layout Description \family typewriter SPICE_SCRIPTS \family default default: \family sans $SPICE_LIB_DIR/scripts \family default \begin_inset Newline newline \end_inset In this directory the \family sans spinit \family default file will be searched. \end_layout \begin_layout Description \family typewriter SPICE_PATH \family default default: \family sans $SPICE_EXEC_DIR/ngspice \family default \begin_inset Newline newline \end_inset Used in the \series bold aspice \series default command (probably obsolete, to be documented) \end_layout \begin_layout Description \family typewriter NGSPICE_MEAS_PRECISION \family default default: 5 \begin_inset Newline newline \end_inset Sets the number of digits if output values are printed by the \series bold meas(ure) \series default command. \end_layout \begin_layout Description \family typewriter SPICE_NO_DATASEG_CHECK \family default default: undefined \begin_inset Newline newline \end_inset If defined, will suppress memory resource info (probably obsolete, not used on Windows or where the \family sans /proc \family default information system is available.) \end_layout \begin_layout Description \family typewriter NGSPICE_INPUT_DIR \family default default: undefined \begin_inset Newline newline \end_inset If defined, using a valid directory name, will add the given directory to the search path when looking for input files ( \family sans *.cir \family default , \family sans *.inc \family default , \family sans *.lib \family default ). \end_layout \begin_layout Description \family typewriter NGSPICE_OSDI_DIR \family default default: undefined \begin_inset Newline newline \end_inset If defined, using a valid directory name, will add the given directory to the search path when looking for VA-Models shared library files ( \family sans *. \family default osdi). \end_layout \begin_layout Description \family typewriter SPICE_USERINIT_DIR \family default default: undefined \begin_inset Newline newline \end_inset If defined, using a valid directory name, this is the first place to search for the user-defined initialization file .spiceinit (or spice.rc). The search sequence then following is: current directory, HOME directory, USERPROFILE directory \end_layout \begin_layout Subsection Common environment variables \end_layout \begin_layout Standard \family typewriter \series bold TERM LINES COLS DISPLAY HOME PATH EDITOR SHELL POSIXLY_CORRECT \family default \end_layout \begin_layout Section Memory usage \end_layout \begin_layout Standard Ngspice started with batch option (-b) and rawfile output (-r rawfile) will store all simulation data immediately into the rawfile without keeping them in memory. Thus very large circuits may be simulated, the memory requested upon ngspice start up will depend on the circuit size, but will not increase during simulation. \end_layout \begin_layout Standard If you start ngspice in interactive mode or interactively with control section, all data will be kept in memory, to be available for later evaluation. A large circuit may outgrow even Gigabytes of memory. The same may happen after a very long simulation run with many vectors and many time steps to be stored. Issuing the \family typewriter save \family default command will help to reduce memory requirements by saving only the data defined by the command. You may also choose option INTERP ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Transient-Analysis-Options" nolink "false" \end_inset ) to reduce memory usage. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Simulation-time" \end_inset Simulation time \end_layout \begin_layout Standard Simulating large circuits may take an considerable amount of CPU time. If this is of importance, you should compile ngspice with the flags for optimum speed, set during configuring ngspice compilation. Under Linux, MINGW, CYGWIN, and macOS there are bash scripts for compiling in the main directory of the ngspice distribution, see chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Compilation-notes" nolink "false" \end_inset . The -O2 optimization flag for compiling and linking is used. \end_layout \begin_layout Standard Under MS Visual Studio, you will have to select the \series bold releaseOMP \series default or release versions, which includes optimization for speed. \end_layout \begin_layout Standard Several simulation periods contribute to CPU time usage. There is the setup period, especially time consuming when externally contributed PDKs have to be resolved, or large circuits are loaded. Due to its data structure the KLU matrix solver ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:General-Options" nolink "false" \end_inset ) may be advantageous here. A lengthy (transient) simulation comprises of two activities: solving the matrix and solving the non-linear device equations. Again, KLU is often faster than Sparse while solving the matrix. Device evaluation, especially for MOS transistors, is sped up by parallel processing with OpenMP ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Ngspice-on-multi-core" nolink "false" \end_inset ). Finally data evaluation may take some additional time. \end_layout \begin_layout Standard Setting \family typewriter no_auto_braces \family default in spinit or .spiceinit will speed up the loading of large PDKs by avoiding to check for unquoted parameters, so assumes that all parameters are quoted correctly by { } or ' '. \end_layout \begin_layout Standard In its standard configuration ngspice limits the maximum time step for transient simulation to \family typewriter tstep \family default of the tran command ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.TRAN:-Transient-Analysis" \end_inset ). Sometimes a significant speedup of the simulation is achievable by setting the variable \family typewriter nostepsizelimit \family default . Now the simulator selects a time step as large as the truncation error correction allows, limited only by giving a \family typewriter tmax \family default in the tran command. Sometimes convergence issue arise, or wave forms are distorted, when selecting this option. \end_layout \begin_layout Standard The new voltage-based truncation error correction ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Transient-simulation-time" \end_inset ) has the potential to further optimize the simulation speed. \end_layout \begin_layout Standard XSPICE (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Behavioral-Modeling" nolink "false" \end_inset and \begin_inset CommandInset ref LatexCommand ref reference "par:XSPICE-Software-User's" nolink "false" \end_inset ) is enabled as part of your compilation configuration. Then the value of \series bold trtol \series default (see \begin_inset CommandInset ref LatexCommand ref reference "des:TRTOL" nolink "false" \end_inset ) is set internally to 1 (instead of default 7) for higher precision if XSPICE code model 'A' devices included in the circuit. This may double or even triple the CPU time needed for any transient simulation, because the amount of time steps and thus iteration steps is more than doubled. \end_layout \begin_layout Standard You may enforce higher speed during XSPICE usage by setting the variable xtrtol in your \family sans .spiceinit \family default initialization file or in the \family typewriter .control \family default section in front of the tran command (via \family typewriter set xtrtol=2 \family default using the set command \begin_inset CommandInset ref LatexCommand ref reference "subsec:Set:-Set-the" nolink "false" \end_inset ) and override the above trtol reduction. Beware however of precision or convergence issues if you use XSPICE 'A' devices, especially if xtrtol is set to values larger than 2. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Ngspice-on-multi-core" \end_inset Ngspice on multi-core processors using OpenMP \end_layout \begin_layout Subsection Introduction \end_layout \begin_layout Standard Today's computers typically come with CPUs having more than one core. It will thus be useful to enhance ngspice to make use of such multi-core processors. \end_layout \begin_layout Standard Using circuits containing mostly transistors and e.g. the BSIM3 model, around 2/3 of the CPU time is spent in evaluating the model equations (e.g. in the BSIM3Load() function). The same happens with other advanced transistor models. Thus, such functions should be parallelized, if possible. Solving the matrix takes about 10% to 50% of the CPU time, so parallel processing in the matrix solver is sometimes of secondary interest only! Furthermore, such paralellization is difficult to achieve with our Sparse and KLU matrix solvers. \end_layout \begin_layout Standard Another alternative is using CUSPICE, that is ngspice (developpment based on ngspice-27) designed for running massively parallel on NVIDIA GPUs. \begin_inset CommandInset href LatexCommand href name "CUDA" target "https://developer.nvidia.com/cuda-toolkit" literal "false" \end_inset enhancements to C code are applied. For LINUX, please see the \begin_inset CommandInset href LatexCommand href name "user guide" target "http://ngspice.sourceforge.net/cuspice/CUSPICE_User_Guide.pdf" literal "false" \end_inset . For MS Windows, an executable is available at the \begin_inset CommandInset href LatexCommand href name "ngspice download pages" target "http://ngspice.sourceforge.net/download.html#exp1" literal "false" \end_inset . \end_layout \begin_layout Subsection Internals \end_layout \begin_layout Standard A publication [1] has described a way to exactly do that using OpenMP, which is available on many platforms and is easy to use, especially if you want to perform parallel processing of a for-loop. \end_layout \begin_layout Standard To explain the implemented approach BSIM3 version 3.3.0 model was chosen, located in the BSIM3 directory, as the first example. The BSIM3load() function in b3ld.c contains two nested for-loops using linked lists (models and instances, e.g. individual transistors). Unfortunately OpenMP requires a loop with an integer index. So in file B3set.c an array is defined, filled with pointers to all instances of BSIM3 and stored in model->BSIM3InstanceArray. \end_layout \begin_layout Standard BSIM3load() is now a wrapper function, calling the for-loop, which runs through functions BSIM3LoadOMP(), once per instance. Inside BSIM3LoadOMP() the model equations are calculated. \end_layout \begin_layout Standard Typically it is necessary to use synchronization constructs such as mutexes when multiple threads write to a common memory location. To avoid the performance degradation of such synchronization, temporary per-thread memory locations are used within the for loop of the BSIM3LoadOMP() function as defined in \family sans bsim3def.h \family default . After all threads complete the for-loop, the update to the matrix is done in an extra function BSIM3LoadRhsMat() in the main thread. \end_layout \begin_layout Standard Then the thread programming needed is only a single line!! \end_layout \begin_layout Standard \family typewriter #pragma omp parallel for \end_layout \begin_layout Standard introducing the for-loop over the device instances. \end_layout \begin_layout Standard This of course is made possible only thanks to the OpenMP guys and the clever trick on no synchronization introduced by the above cited authors. \end_layout \begin_layout Standard The time-measuring function \family typewriter getrusage() \family default used with Linux or Cygwin to determine the CPU time usage (with the \family typewriter rusage \family default option enabled) counts tics from every core, adds them up, and thus reports a CPU time value enlarged by a factor of 8 if 8 threads have been chosen. So now ngspice is forced to use \family typewriter ftime \family default for time measuring if OpenMP is selected. \end_layout \begin_layout Subsection Some results \end_layout \begin_layout Standard Some results on an inverter chain with 627 CMOS inverters, BSIM4.7, 45 nm, running for 200ns, compiled with Visual Studio Community 2019 on Windows 10 (full optimization) or gcc 7.4, SUSE Linux Leap 15.1, -O2, on a i9 9900K machine with 8 real cores (16 logical processors using hyperthreading) and 32 GB of memory are shown in table \begin_inset CommandInset ref LatexCommand ref reference "tab:OpenMP-performance" nolink "false" \end_inset . \end_layout \begin_layout Standard \begin_inset Float table placement document alignment document wide false sideways false status open \begin_layout Plain Layout \align center \begin_inset Caption Standard \begin_layout Plain Layout \begin_inset CommandInset label LatexCommand label name "tab:OpenMP-performance" \end_inset OpenMP performance \end_layout \end_inset \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \family typewriter Threads \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter CPU time [s] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter CPU time [s] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter Windows \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter Linux \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 65.4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 69.3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 46.7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 47.4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 37.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 36.9 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 33.6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 33.6 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 8 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 32.4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 32.4 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 12 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 35.7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 31.7 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 16 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 38.2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter 34.3 \end_layout \end_inset \end_inset \end_layout \end_inset \end_layout \begin_layout Standard So we see a ngspice speed up of more than a factor of two! Even on an Windows 7 notebook with a dual core i7 processor, more than 1.5x improvement using two threads was attained. This is consistent with the fact that roughly half of the CPU time is used for evaluating the device model, half of the time for solving the matrix. Only the device evaluation is parallelized by OpenMP. The time for doing this becomes negligible with 8 or more threads. Allowing more than 8 threads (using the 8 physical cores) does not yield much improvement, even leads to a slight increase of simulation time, because the code is not optimized for hyperthreading. \end_layout \begin_layout Subsection Usage \end_layout \begin_layout Standard To state it clearly: OpenMP is installed inside the model equations of a particular model. It is available in \series bold BSIM3 versions 3.3.0 \series default and \series bold 3.2.4 \series default , but not in any other BSIM3 model, in \series bold BSIM4 versions 4.5, 4.6.5, 4.7 \series default or \series bold 4.8 \series default , but not in any other BSIM4 model, and in \series bold B4SOI, version 4.4 \series default , not in any other SOI model and in models added by the OSDI interface. Older parameter files of version 4.6.x (x any number up to 5) are accepted, you have to check for compatibility. \end_layout \begin_layout Standard OpenMP is enabled as a default during ngspice compilation with gcc on all operating systems. \end_layout \begin_layout Standard Under \series bold MS Windows \series default with \series bold Visual Studio \series default the preprocessor flag \family typewriter USE_OMP \family default , and the \family sans /openmp \family default flag in Visual Studio are enabled when selecting the ReleaseOMP configuration. \end_layout \begin_layout Standard The number of threads has to be set manually by placing \end_layout \begin_layout Standard \family typewriter set num_threads=4 \end_layout \begin_layout Standard into \family sans spinit \family default or \family sans .spiceinit \family default or in the control section of the SPICE input file. If OpenMP is enabled, but num_threads not set, a default value \family typewriter num_threads=2 \family default is set internally. \end_layout \begin_layout Standard If you simulate a circuit, please keep in mind to select BSIM3 (levels 8, 49) version 3.2.4 or 3.3.0 ( \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM3-model" nolink "false" \end_inset ), by placing this version number into your parameter files, BSIM4 (levels 14, 54) version 4.5, 4.6.5, 4.7 or 4.8 ( \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM4-model" nolink "false" \end_inset ), or B4SOI (levels 10, 58) version 4.4 ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:BSIMSOI-models" nolink "false" \end_inset ). All other transistor models run as usual (without multithreading support). \end_layout \begin_layout Standard If you run \family sans ./configure \family default with \family typewriter --disable-openmp \family default (or without \family typewriter USE_OMP \family default preprocessor flag under MS Windows), you will get only the standard, not paralleled BSIM3 and BSIM4 models, as has been available from Berkeley. If OpenMP is selected and the number of threads set to 1, there will be only a very slight CPU time disadvantage (typ. 3%) compared to the old, non OpenMP build. \end_layout \begin_layout Subsection Literature \end_layout \begin_layout Standard [1] R.K. Perng, T.-H. Weng, and K.-C. Li: "On Performance Enhancement of Circuit Simulation Using Multithreaded Techniques", IEEE International Conference on Computational Science and Engineering, 2009, pp. 158-165 \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Compatibility" \end_inset Compatibility \end_layout \begin_layout Standard ngspice is a direct derivative of spice3f5 from UC Berkeley and thus inherits all of the commands available in its predecessor. Thanks to the open source policy of UCB (original spice3 from 1994 is still available \begin_inset CommandInset href LatexCommand href name "here" target "http://embedded.eecs.berkeley.edu/pubs/downloads/spice/index.htm" literal "false" \end_inset ), several commercial variants have sprung off, either being more dedicated to IC design or more concentrating on simulating discrete and board level electronics. None of the commercial and almost none of the freely downloadable SPICE providers publishes the source code. All of them have proceeded with the development, by adding functionality, or by adding a more dedicated user interface. Some have kept the original SPICE syntax for their netlist description, others have quickly changed some if not many of the commands, functions and procedures. Thus it is difficult, if not impossible, to offer a simulator that acknowledges all of these netlist dialects. ngspice includes some features that enhance compatibility that are included automatically. This selection may be controlled to some extend by setting the compatibility mode. Others may be invoked by the user by small additions to the netlist input file. Some of them are listed in this chapter, some will be integrated into ngspice at a later stage, others will be added if they are reported by users. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Compatibility-mode" \end_inset Compatibility mode \end_layout \begin_layout Standard The variable ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset ) ngbehavior sets the compatibility mode. Per default no compatibility mode is selected. The compatibility status will be displayed in the output window. \end_layout \begin_layout LyX-Code \family typewriter set ngbehavior=ltpsa \family default \end_layout \begin_layout Standard in \family sans spinit \family default or \family sans .spiceinit \family default is a typical command, setting PSPICE and LTSPICE compatibility for the whole netlist. Flag ' \family typewriter a \family default ' may be combined with any of the flags listed below. By contrast \end_layout \begin_layout LyX-Code \family typewriter set ngbehavior=ps \family default \end_layout \begin_layout Standard (without \family typewriter \family default ' \family typewriter a \family default ') will set PSPICE compatibility only for libraries which are added by a .include command. So you may keep your Spice3 compatible netlist, but including PSPICE device models. The available compatibility flags are: \end_layout \begin_layout Standard \begin_inset Float table placement H alignment document wide false sideways false status open \begin_layout Plain Layout \noindent \align center \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Flag \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ref. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Short description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout a \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout complete netlist transformed \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ps \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode-1" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout PSPICE compatibility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout hs \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode-1-4" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout HSPICE compatibility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout spe \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode-1-3" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Spectre compatibility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout lt \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode-1-1" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout LTSPICE compatibility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout s3 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Spice3 compatibility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ll \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout all (currently not used) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ki \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode-1-2" nolink "false" \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout KiCad compatibility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout eg \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout EAGLE compatibility \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout mc \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout for ' \family typewriter make check \family default ' \end_layout \end_inset \end_inset \end_layout \begin_layout Plain Layout \begin_inset Caption Standard \begin_layout Plain Layout Compatibility flags \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter 's3' \family default will disable some of the advanced ngspice features. \family typewriter 'eg' \family default will enable EAGLE compatible voltage vector output. \family typewriter 'mc' \family default is required when the command \family typewriter 'make check' \family default is to be executed. Then all flags are reset, in addition the compatibility status output is suppressed. Flags \family typewriter 'ps' \family default and \family typewriter 'hs' \family default are mutually exclusive. \end_layout \begin_layout Standard The command \family typewriter 'unset ngbehavior' \family default will remove the variable \family typewriter ngbehavior \family default , thus resetting the compatibility mode to the default (no compat mode is set). \end_layout \begin_layout Subsection Missing functions \end_layout \begin_layout Standard You may add one or more function definitions to your input file, as listed below. \end_layout \begin_layout LyX-Code .func LIMIT(x,a,b) {min(max(x, a), b)} \end_layout \begin_layout LyX-Code .func PWR(x,a) {abs(x) ** a} \end_layout \begin_layout LyX-Code .func PWRS(x,a) {sgn(x) * PWR(x,a)} \end_layout \begin_layout LyX-Code .func stp(x) {u(x)} \end_layout \begin_layout Subsection Devices \end_layout \begin_layout Subsubsection E Source with LAPLACE \end_layout \begin_layout Standard see \begin_inset CommandInset ref LatexCommand ref reference "subsec:LAPLACE" nolink "false" \end_inset . \end_layout \begin_layout Subsubsection VSwitch \end_layout \begin_layout Standard The VSwitch \end_layout \begin_layout LyX-Code S1 2 3 11 0 SW \end_layout \begin_layout LyX-Code .MODEL SW VSWITCH(VON=5V VOFF=0V RON=0.1 ROFF=100K) \end_layout \begin_layout Standard may become \end_layout \begin_layout LyX-Code a1 %v(11) %gd(2 3) sw \end_layout \begin_layout LyX-Code .MODEL SW aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e5 \end_layout \begin_layout LyX-Code + r_on=0.1 log=TRUE) \end_layout \begin_layout Standard The XSPICE option has to be enabled. \end_layout \begin_layout Subsection Controls and commands \end_layout \begin_layout Subsubsection .lib \end_layout \begin_layout Standard The ngspice .lib command (see \begin_inset CommandInset ref LatexCommand ref reference "sec:.LIB" nolink "false" \end_inset ) requires two parameters, a file name followed by a library name. If no library name is given, the line \end_layout \begin_layout LyX-Code .lib filename \end_layout \begin_layout Standard should be replaced by \end_layout \begin_layout LyX-Code .inc filename \end_layout \begin_layout Standard Alternatively, the compatibility mode ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode" nolink "false" \end_inset ) may be set to \family typewriter 'ps' \family default . \end_layout \begin_layout Subsubsection \begin_inset CommandInset label LatexCommand label name "subsec:.incpslt" \end_inset .incpslt \end_layout \begin_layout Standard A special command to include model files is needed if the compatibility mode is set to \family typewriter 'hs' \family default , for reading data from a PDK ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode-1-4" nolink "false" \end_inset ), but you want to co-simulate this (integrated) circuit together with for example a power device which has a model that requires the compatibility mode \family typewriter 'pslt' \family default . The command \end_layout \begin_layout LyX-Code .incpslt filename \end_layout \begin_layout Standard treats the included netlist from file \family typewriter filename \family default , e.g. a subcircuit device model, as if its compatibility mode had been set to \family typewriter 'pslt' \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode-1-1-1" nolink "false" \end_inset ), but otherwise the netlist (including library handling) is treated according to compatibility mode given at top level, typically \family typewriter 'hs' \family default or none. \end_layout \begin_layout Subsubsection .step \end_layout \begin_layout Standard Repeated analysis in ngspice is offered by a short script inside of a \family typewriter .control \family default section (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Parameter-sweep" nolink "false" \end_inset ) added to the input file. A simple application (multiple dc sweeps) is shown below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Input file with parameter sweep \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout parameter sweep \end_layout \begin_layout Plain Layout * resistive divider, R1 swept from start_r to stop_r \end_layout \begin_layout Plain Layout * replaces .STEP R1 1k 10k 1k \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout R1 1 2 1k \end_layout \begin_layout Plain Layout R2 2 0 1k \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout VDD 1 0 DC 1 \end_layout \begin_layout Plain Layout .dc VDD 0 1 .1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout let start_r = 1k \end_layout \begin_layout Plain Layout let stop_r = 10k \end_layout \begin_layout Plain Layout let delta_r = 1k \end_layout \begin_layout Plain Layout let r_act = start_r \end_layout \begin_layout Plain Layout * loop \end_layout \begin_layout Plain Layout while r_act le stop_r \end_layout \begin_layout Plain Layout alter r1 r_act \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout write dc-sweep.out v(2) \end_layout \begin_layout Plain Layout set appendwrite \end_layout \begin_layout Plain Layout let r_act = r_act + delta_r \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout plot dc1.v(2) dc2.v(2) dc3.v(2) dc4.v(2) dc5.v(2) \end_layout \begin_layout Plain Layout + dc6.v(2) dc7.v(2) dc8.v(2) dc9.v(2) dc10.v(2) \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Compatibility-mode-1" \end_inset PSPICE Compatibility mode \end_layout \begin_layout Standard If the variable ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset ) \family typewriter ngbehavior \family default is set to \family typewriter 'ps' \family default or \family typewriter 'psa' \family default with the commands \end_layout \begin_layout LyX-Code \family typewriter set ngbehavior=ps \end_layout \begin_layout Standard or \end_layout \begin_layout LyX-Code \family typewriter set ngbehavior=psa \end_layout \begin_layout Standard in \family sans spinit \family default or \family sans .spiceinit, ngspice \family default will translate all files that have been read into ngspice netlist by the .include command ( \family sans ps \family default ) or the complete netlist ( \family sans psa \family default ) from PSPICE syntax to ngspice. This feature allows reading of PSPICE (or TINA) compatible device libraries ( \family sans ps \family default ) that are often supplied by the semiconductor device manufacturers. Or you may choose to use complete PSPICE simulation decks ( \family sans psa \family default ). Some ngspice input files may fail, however. For example \family sans ngspice \backslash examples \backslash memristor \backslash memristor.sp \family default will not do, because it uses the parameter \family sans vt \family default , and \family sans vt \family default is a reserved word in PSPICE. \end_layout \begin_layout Standard PSPICE to ngspice translation details: \end_layout \begin_layout Itemize .model replacement in ako (a kind of) model descriptions \end_layout \begin_layout Itemize replace the E source TABLE function by a B source pwl \end_layout \begin_layout Itemize add predefined params TEMP, VT, GMIN to beginning of deck \end_layout \begin_layout Itemize add predefined params TEMP, VT to beginning of each .subckt call \end_layout \begin_layout Itemize add .functions limit, pwr, pwrs, stp, if, int \end_layout \begin_layout Itemize replace \begin_inset Newline newline \end_inset \family typewriter S1 D S DG GND SWN \begin_inset Newline newline \end_inset .MODEL SWN VSWITCH(VON=0.55 VOFF=0.49 \begin_inset Newline newline \end_inset + RON={1/(2*M*(W/LE)*(KPN/2)*10)} ROFF=1G) \begin_inset Newline newline \end_inset \family default by \begin_inset Newline newline \end_inset \family typewriter as1 %vd(DG GND) % gd(D S) aswn \begin_inset Newline newline \end_inset .model aswn aswitch(cntl_off=0.49 cntl_on=0.55 \begin_inset Newline newline \end_inset + r_off=1G r_on={1/(2*M*(W/LE)*(KPN/2)*10)} log=TRUE) \end_layout \begin_layout Itemize replace & by && \end_layout \begin_layout Itemize replace | by || \end_layout \begin_layout Itemize replace \family typewriter T_ABS \family default by \family typewriter temp \family default and \family typewriter T_REL_GLOBAL \family default by \family typewriter dtemp \end_layout \begin_layout Itemize get the area factor for diodes and bipolar devices \begin_inset Newline newline \end_inset \family typewriter d1 n1 n2 dmod 7 \family default –> \family typewriter d1 n1 n2 dmod area=7 \begin_inset Newline newline \end_inset q2 n1 n2 n3 [n4] bjtmod 1.35 \family default –> \family typewriter q2 n1 n2 n3 n4 bjtmod area=1.35 \begin_inset Newline newline \end_inset q3 1 2 3 4 bjtmod 1.45 \family default –> \family typewriter q2 1 2 3 4 bjtmod area=1.45 \end_layout \begin_layout Itemize Check for double '{{ }}', replace the inner '{', '}' by '(', ')' \end_layout \begin_layout Itemize Limit for exp function (linear growth when exponent is larger than 14). \end_layout \begin_layout Standard In ps or psa mode, ngspice will treat all .lib entries like .include. There is no hierarchically library handling. So for reading HSPICE compatible libraries, you definitely have to unset the ps mode, e.g. by not adding \family typewriter set ngbehavior=ps \family default or disabling it by \end_layout \begin_layout LyX-Code \family typewriter unset ngbehavior=ps \end_layout \begin_layout Standard New analogue and digital device models from some semiconductor vendors contain the token GND inside of their subcircuits. In the past ngspice has declared GND as global and replaced it by 0. Now, if PS is selected, GND is not declared as global, and is not replaced inside of a subcircuit. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Compatibility-mode-1-1" \end_inset LTSPICE Compatibility mode \end_layout \begin_layout Standard If the variable ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset ) \family typewriter ngbehavior \family default is set to \family typewriter 'lt' \family default or \family typewriter 'lta' \family default with the commands \end_layout \begin_layout LyX-Code \family typewriter set ngbehavior=lt \family default \end_layout \begin_layout Standard or \end_layout \begin_layout LyX-Code \family typewriter set ngbehavior=lta \end_layout \begin_layout Standard in \family sans spinit \family default or \family sans .spiceinit, ngspice \family default will translate all files that have been read into ngspice netlist by the .include command ( \family sans lt \family default ) or the complete netlist ( \family sans lta \family default ) from LTSPICE syntax to ngspice. This feature allows reading of LTSPICE compatible device libraries or complete netlists. \end_layout \begin_layout Standard Currently we offer only a subset of the documented or undocumented functions (uplim, dnlim, uplim_tanh, dnlim_tanh). More user input is definitely required here! \end_layout \begin_layout Standard This compatibility mode also adds a simple diode using the sidiode code model ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Simple-Diode-Model" nolink "false" \end_inset ). The diode model \end_layout \begin_layout LyX-Code d1 a k ds1 \end_layout \begin_layout LyX-Code .model ds1 d(Roff=1000 Ron=0.7 Rrev=0.2 Vfwd=1 \end_layout \begin_layout LyX-Code + Vrev=10 Revepsilon=0.2 Epsilon=0.2 Ilimit=7 Revilimit=15) \end_layout \begin_layout Standard is translated automatically to the equivalent code model diode \end_layout \begin_layout LyX-Code ad1 a k ads1 \end_layout \begin_layout LyX-Code .model ads1 sidiode(Roff=1000 Ron=0.7 Rrev=0.2 Vfwd=1 \end_layout \begin_layout LyX-Code + Vrev=10 Revepsilon=0.2 Epsilon=0.2 Ilimit=7 Revilimit=15) \end_layout \begin_layout Standard \series bold RKM code compatibility: \end_layout \begin_layout Itemize In LT compatibility mode ngspice will follow the \begin_inset CommandInset href LatexCommand href name "RKM code" target "https://en.wikipedia.org/wiki/RKM_code" literal "false" \end_inset notation. In addition to the standard notation, resistor (R) and capacitor (C) values may also be entered according to the following listings (the internally translated value is given after the ;): \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout RKM code for resistors \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout R1 1 0 4K7 ; 4.7k \end_layout \begin_layout Plain Layout R2 1 0 4R7 ; 4.7 \end_layout \begin_layout Plain Layout R3 1 0 R47 ; 0.47 \end_layout \begin_layout Plain Layout R4 1 0 470R ; 470 \end_layout \begin_layout Plain Layout R5 1 0 47K ; 47k \end_layout \begin_layout Plain Layout R6 1 0 47K3 ; 47.3k \end_layout \begin_layout Plain Layout R7 1 0 470K ; 470k \end_layout \begin_layout Plain Layout R8 1 0 4Meg7 tc1=1e-6 tc2=1e-9 dtemp=6 \end_layout \begin_layout Plain Layout * ; 4.7Meg <-- Not defined in the RKM notation \end_layout \begin_layout Plain Layout R9 1 0 4L7 ; 4.7m \end_layout \begin_layout Plain Layout R10 1 0 470L ; 470m \end_layout \begin_layout Plain Layout R11 1 0 4M7 ; 4.7m <-- This deviates fom the RKM notation \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout RKM code for capacitors \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout C1 1 0 4p7 ; 4.7p \end_layout \begin_layout Plain Layout C2 1 0 4n7 ; 4.7n \end_layout \begin_layout Plain Layout C3 1 0 4u7 ; 4.7u \end_layout \begin_layout Plain Layout C4 1 0 4m7 ; 4.7m \end_layout \begin_layout Plain Layout C5 1 0 4F7 ; 4.7f <-- This deviates fom the RKM notation \end_layout \begin_layout Plain Layout C6 1 0 47p3 ; 4.73p \end_layout \begin_layout Plain Layout C7 1 0 470p ; 470p \end_layout \begin_layout Plain Layout C8 1 0 4u76 tc1=1e-6 tc2=1e-9 dtemp=6 \end_layout \begin_layout Plain Layout * ; 4.76u \end_layout \begin_layout Plain Layout C9 1 0 4m7 ; 4.7m \end_layout \begin_layout Plain Layout C10 1 0 470nF ; 470n \end_layout \begin_layout Plain Layout C11 1 0 47fF ; 47f <-- This deviates fom the RKM notation \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard There are some exceptions to the RKM code notation: \end_layout \begin_layout Itemize all letters may be entered upper or lower case, and will internally be transformed to lower case. \end_layout \begin_layout Itemize m, M always denote milli (1e-3). \end_layout \begin_layout Itemize f, F denote femto (1e-15), fF will be again femto \end_layout \begin_layout Itemize meg, Meg denotes mega (1e6) \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Compatibility-mode-1-1-1" \end_inset LTSPICE/PSPICE Compatibility mode \end_layout \begin_layout Standard If the variable ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset ) \family typewriter ngbehavior \family default is set to \family typewriter 'ltps' \family default or \family typewriter 'ltpsa' \family default with the commands \end_layout \begin_layout LyX-Code \family typewriter set ngbehavior=ltps \family default \end_layout \begin_layout Standard or \end_layout \begin_layout LyX-Code \family typewriter set ngbehavior=ltpsa \end_layout \begin_layout Standard in \family sans spinit \family default or \family sans .spiceinit, ngspice \family default will translate all files that have been read into ngspice netlist by the .include command ( \family sans ltps \family default ) or the complete netlist ( \family sans ltpsa \family default ) \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode-1-1" nolink "false" \end_inset , \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode-1" nolink "false" \end_inset from LTSPICE and PSPICE syntax to ngspice. This feature allows reading of LTSPICE and PSPICE compatible device libraries or complete netlists. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Compatibility-mode-1-2" \end_inset KiCad Compatibility mode \end_layout \begin_layout Standard KiCad will generate vector names containing '/'. If the variable ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset ) \family typewriter ngbehavior \family default is set to \family typewriter ki \family default with the command \end_layout \begin_layout LyX-Code \family typewriter set ngbehavior=ki \end_layout \begin_layout Standard is set in \family typewriter .spiceinit \family default (or plot line flag \family typewriter kicad \family default is given \begin_inset CommandInset ref LatexCommand ref reference "subsec:Plot:-Plot-values" nolink "false" \end_inset ), ngspice will place " around this vector name. The mathematical operation 'division' in the plot command will then work only if spaces are placed around the division operator /. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Compatibility-mode-1-3" \end_inset Spectre Compatibility mode \end_layout \begin_layout Standard If the variable ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset ) \family typewriter ngbehavior \family default is set to \family typewriter spe \family default with the command \end_layout \begin_layout LyX-Code \family typewriter set ngbehavior=spe \end_layout \begin_layout Standard is set in \family typewriter .spiceinit \family default Spectre compatibility mode is enabled. True compatibility today is still far away. The only action available for now is the use of the MOS device instance parameter \family typewriter nf \family default . If \family typewriter nf \family default is given and larger than 1 and Spectre (or HSPICE) compatibility is enabled, \family typewriter nf \family default is used as a divisor to the transistor width \family typewriter W \family default given on the instance line. The resulting \family typewriter W/nf \family default is now used to select the suitable device model in the binning process. This procedure is of interest for a multi-gate transistor, which has a total width of \family typewriter W \family default , but each finger is model according to the model given for \family typewriter W/nf \family default . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Compatibility-mode-1-4" \end_inset HSPICE Compatibility mode \end_layout \begin_layout Standard If the variable ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset ) \family typewriter ngbehavior \family default is set to \family typewriter hs \family default with the command \end_layout \begin_layout LyX-Code \family typewriter set ngbehavior=hs \end_layout \begin_layout Standard given in \family typewriter .spiceinit \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" \end_inset ), HSPICE compatibility mode is enabled. This mode allows to read libraries with the \family typewriter .lib \family default command in a recursive fashion, as is required by HSPICE compatible process development kits (PDKs). In addition the \family typewriter nf \family default flag is enabled, as described in \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode-1-3" nolink "false" \end_inset . \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Transient-simulation-time" \end_inset Transient simulation time steps with voltage-based truncation error correction \end_layout \begin_layout Standard Traditionally Spice3f5 and ngspice use a charge-based truncation error correction, while calculating the next time step in a transient simulation. As this is a central procedure determining the simulation speed and convergence behavior, ngspice now also offers an alternative voltage-based method. It requires ngspice compiled with the \family typewriter –enable-predictor \family default flag (which is the default) and may be selected by setting \family typewriter option newtrunc \family default in \family typewriter .spiceinit \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example .spiceinit settings: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout option newtrunc \end_layout \begin_layout Plain Layout option ltetrtol=900 ; optimum: 400-500 for gear, 800 for trap \end_layout \begin_layout Plain Layout option ltereltol=1e-3 ; default is 1e-3 \end_layout \begin_layout Plain Layout option lteabstol=1e-6 ; default is 1e-6 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The options \family typewriter ltetrtol \family default , \family typewriter ltereltol \family default , and \family typewriter lteabstol \family default have their usable meanings, comparable to their standard counterparts (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:DC-Solution-Options" \end_inset ), but may differ in the values selected. \end_layout \begin_layout Standard This new feature is currently largely unexplored, will need theoretical and practical backings, but may offer further optimization of the transient simulation. \end_layout \begin_layout Section Server mode option -s \end_layout \begin_layout Standard A program may write the SPICE input to the console. This output is redirected to ngspice via ` \family typewriter | \family default '. ngspice called with the -s option writes its output to the console, which again is redirected to a receiving program by ` \family typewriter | \family default '. In the following simple example \series bold cat \series default reads the input file and prints it content to the console, which is redirected to ngspice by a first pipe, ngspice transfers its output (similar to a raw file, see below) to \series bold less \series default via another pipe. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example command line: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout cat input.cir|ngspice -s|less \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Under MS Windows you will need to compile ngspice as a console application (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:ngspice-mingw-or" nolink "false" \end_inset ) for this server mode usage. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example input file: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout test -s \end_layout \begin_layout Plain Layout v1 1 0 1 \end_layout \begin_layout Plain Layout r1 1 0 2k \end_layout \begin_layout Plain Layout .options filetype=ascii \end_layout \begin_layout Plain Layout .save i(v1) \end_layout \begin_layout Plain Layout .dc v1 -1 1 0.5 \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If you start ngspice console with \end_layout \begin_layout LyX-Code ngspice -s \end_layout \begin_layout Standard you may type in the above circuit line by line (not to forget the first line, which is a title and will be ignored). If you close your input with \family typewriter ctrl Z \family default , and \family typewriter return \family default , you will get the following output (this is valid for MINGW only) on the console, like a raw file: \end_layout \begin_layout LyX-Code Circuit: test -s \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 \begin_inset Newline newline \end_inset \begin_inset Newline newline \end_inset Title: test -s \end_layout \begin_layout LyX-Code Date: Sun Jan 15 18:57:13 2012 \end_layout \begin_layout LyX-Code Plotname: DC transfer characteristic \end_layout \begin_layout LyX-Code Flags: real \end_layout \begin_layout LyX-Code No. Variables: 2 \end_layout \begin_layout LyX-Code No. Points: 0 \end_layout \begin_layout LyX-Code Variables: \end_layout \begin_layout LyX-Code No. of Data Columns : 2 \end_layout \begin_layout LyX-Code 0 v(v-sweep) voltage \end_layout \begin_layout LyX-Code 1 i(v1) current \end_layout \begin_layout LyX-Code Values: \end_layout \begin_layout LyX-Code 0 -1.000000000000000e+000 \end_layout \begin_layout LyX-Code 5.000000000000000e-004 \end_layout \begin_layout LyX-Code 1 -5.000000000000000e-001 \end_layout \begin_layout LyX-Code 2.500000000000000e-004 \end_layout \begin_layout LyX-Code 2 0.000000000000000e+000 \end_layout \begin_layout LyX-Code 0.000000000000000e+000 \end_layout \begin_layout LyX-Code 3 5.000000000000000e-001 \end_layout \begin_layout LyX-Code -2.500000000000000e-004 \end_layout \begin_layout LyX-Code 4 1.000000000000000e+000 \end_layout \begin_layout LyX-Code -5.000000000000000e-004 \end_layout \begin_layout LyX-Code @@@ 122 5 \end_layout \begin_layout Standard The number \family typewriter 5 \family default of the last line \family typewriter @@@ 122 5 \family default shows the number of data points, which is missing in the above line \family typewriter No. Points: 0 \family default because at the time of writing to the console it has not yet been available. \end_layout \begin_layout Standard \family typewriter ctrl Z \family default is not usable here in Linux, a patch to install \family typewriter ctrl D \family default instead is being evaluated. \end_layout \begin_layout Section Pipe mode option -p \end_layout \begin_layout Standard A program may write a set of ngspice commands (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" nolink "false" \end_inset ) to the console. This output is redirected to ngspice via ` \family typewriter | \family default '. ngspice called with the -p option immediately executes the commands and then exits. In the following simple example \series bold cat \series default reads the input file and prints it content to the console, which is redirected to ngspice by a pipe, ngspice executes the commands. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example command line: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout cat pipe-circuit.cir | ngspice -p \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Under MS Windows you will need to compile ngspice as a console application (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:ngspice-mingw-or" nolink "false" \end_inset ) for this pipe mode usage. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example input file: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout *pipe-circuit.cir \end_layout \begin_layout Plain Layout source circuit.cir \end_layout \begin_layout Plain Layout tran 10u 2m \end_layout \begin_layout Plain Layout write pcir.raw all \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example circuit file: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * Circuit.cir \end_layout \begin_layout Plain Layout V1 n0 0 SIN(0 10 1kHz) \end_layout \begin_layout Plain Layout C1 n1 n0 3.3nF \end_layout \begin_layout Plain Layout R1 0 n1 1k \end_layout \begin_layout Plain Layout .end \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The raw file pcir.raw will contain the final simulation results. \end_layout \begin_layout Section Ngspice control via input, output fifos \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example bash script: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout #!/usr/bin/env bash \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout NGSPICE_COMMAND="ngspice" \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout rm input.fifo \end_layout \begin_layout Plain Layout rm output.fifo \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout mkfifo input.fifo \end_layout \begin_layout Plain Layout mkfifo output.fifo \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout $NGSPICE_COMMAND -p -i output.fifo & \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout exec 3>input.fifo \end_layout \begin_layout Plain Layout echo "I can write to input.fifo" \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout echo "Start processing..." \end_layout \begin_layout Plain Layout echo "" \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout echo "source circuit.cir" >&3 \end_layout \begin_layout Plain Layout echo "unset askquit" >&3 \end_layout \begin_layout Plain Layout echo "set nobreak" >&3 \end_layout \begin_layout Plain Layout echo "tran 0.01ms 0.1ms">&3 \end_layout \begin_layout Plain Layout echo "print n0" >&3 \end_layout \begin_layout Plain Layout echo "quit" >&3 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout echo "Try to open output.fifo ..." \end_layout \begin_layout Plain Layout exec 4&- \end_layout \begin_layout Plain Layout exec 4>&- \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout echo "End processing" \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The bash script listed above (tested under Linux and Cygwin) \end_layout \begin_layout Standard - launches ngspice in pipe mode (-p) in another thread. \end_layout \begin_layout Standard - writes some commands to the ngspice input \end_layout \begin_layout Standard - runs ngspice with the tran command \end_layout \begin_layout Standard - reads the output and prints it onto the console. \end_layout \begin_layout Standard The input file with a small circuit is: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout \family sans Circuit.cir \family default : \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * Circuit.cir \end_layout \begin_layout Plain Layout V1 n0 0 SIN(0 10 1kHz) \end_layout \begin_layout Plain Layout C1 n1 n0 3.3nF \end_layout \begin_layout Plain Layout R1 0 n1 1k \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section Tests \end_layout \begin_layout Standard The ngspice distribution is accompanied by a suite of test input and output files, located in the directory \family sans ngspice/tests \family default . Originally this suite was meant to see if ngspice with all models was made and installed properly. It is started by \end_layout \begin_layout Standard \family typewriter $ make check \end_layout \begin_layout Standard from within your compilation and development shell. A sequence of simulations is thus started, its outputs compared to given output files by comparisons string by string. This feature is momentarily used to check for some basic procedures and the XSPICE extension ( \begin_inset CommandInset ref LatexCommand ref reference "cha:Behavioral-Modeling" nolink "false" \end_inset ) as a regression test. Several other input files located in directory \family sans ngspice/tests \family default may serve as light-weight examples for invoking devices and simple circuits. \end_layout \begin_layout Standard Today's very complex device models (BSIM3 ( \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM3-model" nolink "false" \end_inset ), BSIM4 (see \begin_inset CommandInset ref LatexCommand ref reference "subsubsec:BSIM4-model" nolink "false" \end_inset ), HiSIM (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:HiSIM-models-of" nolink "false" \end_inset ) and others) require a different strategy for verification. Under development for ngspice is the CMC Regression test by Colin McAndrew, which accompanies every new model. These tests cover a large range of different DC, AC and noise simulations with different geometry ranges and operating conditions and are more meaningful the transient simulations with their step size dependencies. A major advantage is the scalability of the diff comparisons, which check for equality within a given tolerance. A set of Perl modules cares for input, output and comparisons of the models. Currently BSIM3, BSIM4, BSIMSOI4, HICUM2, HiSIM, and HiSIM_HV models implement the QA test. You may invoke it by running the command given above or by \end_layout \begin_layout Standard \family typewriter $ make -i check 2>&1 | tee results \end_layout \begin_layout Standard \family typewriter -i \family default will cause \family typewriter make \family default to ignore any errors, and \family typewriter tee \family default will provide console output as well as printing to file 'results'. Be aware that under MS Windows you will need the console binary (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:ngspice-mingw-or" nolink "false" \end_inset ) to run the CMC tests, and you have to have Perl installed! \end_layout \begin_layout Standard As these tests may consume a considerable amount of CPU time, there is a configure option \family typewriter \series bold --enable-shortcheck \family default \series default \begin_inset CommandInset ref LatexCommand ref reference "subsec:Options-Specific-to" nolink "false" \end_inset available, providing a strongly reduced runtime, because besides some regression tests only BSIM3 and BSM4 devices are checked. \end_layout \begin_layout Standard Other tests have been developed, there are also some benchmark circuit compilations available. Please have a look at our \begin_inset CommandInset href LatexCommand href name "Tests and Quality Assurance" target "http://ngspice.sourceforge.net/applic.html#test" literal "false" \end_inset web page. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Debugging-a-circuit" \end_inset Tools for debugging a circuit netlist \end_layout \begin_layout Standard This a chapter only in its initial state. Not all circuits will simulate immediately and easily. The netlist may contain a bug. The netlist may be o.k., but then ngspice may not find an operating point. If the operating point has been found, the transient simulation will just yield the famous error message 'transient time step too small'. Unfortumately there are many reasons for failure, on the other hand there is a lot of literature available to traet non-convergence. \end_layout \begin_layout Standard So for now there will be listed here only a few 'tools' offered by ngspice to aid debugging. \end_layout \begin_layout Subsection options and initial conditions \end_layout \begin_layout Standard If ngspice has trouble finding the operating point, setting some initial conditions by adding \family typewriter .nodeset \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.NODESET" nolink "false" \end_inset ) or \family typewriter .ic \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.IC:-Set-Initial" nolink "false" \end_inset ) for critical nodes may help. The variation of some op option parameters may help as well (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:DC-Solution-Options" nolink "false" \end_inset ). If there are nodes without dc connection to ground (e.g. two capacitors in series connection), finding the operating point will fail. Here the option RSHUNT may be of help by adding are (typically large) resistor from each node to ground. Convergence may be improved by the RSERIES option that add a (typically small) resistor in series to each inductor. \end_layout \begin_layout Standard Transient simulations are governed by another set of options (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Transient-Analysis-Options" nolink "false" \end_inset ). Careful variation of the parameters, as described in the literature, may enable convergence in incritical situations (not guaranteed, however). \end_layout \begin_layout Subsection set debug \end_layout \begin_layout Standard If set in .spiceinit (or spice.rc), the command \family typewriter set debug \family default will yield an analysis of each command which is run from .spiceinit and .control. \end_layout \begin_layout Subsection set ngdebug \end_layout \begin_layout Standard The command \family typewriter set ngdebug \family default , if set in .spiceinit (spice.rc) provides some additional warning messages. If ngspice has write access to the current directory, 3 or 4 files are saved to that directory, showing the netlist at specific stages during parsing. Each file contain two parts, the netlist without comment lines, followed by the same netlist including all comment lines. \family typewriter debug-out.txt \family default is available after pre-processing the netlist. \family typewriter debug-out2.txt \family default shows the netlist after parameter and subcircuit expansion. \family typewriter debug-out3.txt \family default lists the final netlist. debug-out-mc.txt is issued, when the netlist is reloaded after a \family typewriter reset \family default or \family typewriter mc_source \family default command. \end_layout \begin_layout Standard During a transient simulation a vector 'speedcheck' is generated in the current tran plot. The independent variable is the scale vector 'time', the dependent variable is the wall clock time with a resolution of about 100 ms. So you may monitor the simulation progress of a (lengthy) transient simulation and detect critical (simulated) times where the simulation may be slowed down. \end_layout \begin_layout Standard Another vector 'deltacheck' is generated in the current tran plot. The independent variable is again the scale vector 'time', the dependent variable is the time delta between the accepted time points. This is another way to monitor the simulation progress of a transient simulation and allows to detect critical circuit conditions (e.g. when small deltas are clustered at a specific time step). \end_layout \begin_layout Standard When ngspice is used as a shared library ( \begin_inset CommandInset ref LatexCommand ref reference "chap:ngspice-as-shared" nolink "false" \end_inset ), the complete netlist sent to ngspice by the calling process is returned to the caller by the callback function \family typewriter printfcn \family default . Also return each command received by the caller. \end_layout \begin_layout Subsection miscellaneous \end_layout \begin_layout Standard Debugging the equations of a \series bold B source \series default are described in chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Debugging-a-behavioral" nolink "false" \end_inset . \end_layout \begin_layout Standard Compiling ngspice with the ./configure flag \family typewriter --enable-ftedebug \family default or (for MS Visual Studio: adding a preprocessor flag \family typewriter FTEDEBUG \family default ) will enable some additional warning messages. \end_layout \begin_layout Standard Compiling ngspice with the ./configure flag \family typewriter --enable-stepdebug \family default or (for MS Visual Studio: adding a preprocessor flag \family typewriter STEPDEBUG \family default ) yields a very powerful tool for analysing the steps of a transient simulation. The amount of messages printed however is overwhelming and may be interpreted by an insider only. \end_layout \begin_layout Section Reporting bugs and errors \end_layout \begin_layout Standard Ngspice is a complex piece of software. The source code contains over 1500 files. Various models and simulation procedures are provided, some of them not used and tested intensively. Therefore errors may be found, some still evolving from the original spice3f5 code, others introduced during the ongoing code enhancements. \end_layout \begin_layout Standard If you happen to experience an error during the usage of ngspice, please send a report to the development team. Ngspice is hosted on SourceForge, the preferred place to post a bug report is the \begin_inset CommandInset href LatexCommand href name "ngspice bug tracker" target "http://sourceforge.net/tracker/?group_id=38962&atid=423915" literal "false" \end_inset . We would prefer to have your bug tested against the actual source code available at Git, but of course a report using the most recent ngspice release is welcome! Please provide the following information with your report: \end_layout \begin_layout Standard Ngspice version \end_layout \begin_layout Standard Operating system \end_layout \begin_layout Standard Small input file to reproduce the bug \end_layout \begin_layout Standard Actual output versus the expected output \end_layout \begin_layout Chapter \begin_inset CommandInset label LatexCommand label name "chap:Interactive-Interpreter" \end_inset Interactive Interpreter \end_layout \begin_layout Section Introduction \end_layout \begin_layout Standard The simulation flow in ngspice (input, simulation, output) may be controlled by dot commands (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "chap:Analyses-and-Output" nolink "false" \end_inset and \begin_inset CommandInset ref LatexCommand ref reference "subsec:Batch-mode" nolink "false" \end_inset ) in batch mode. There is, however, a much more powerful control scheme available in ngspice, traditionally coined `Interactive Interpreter', but being much more than just that. In fact there are several ways to use this feature, truly interactively by typing commands to the input, but also running command sequences as scripts or as part of your input deck in a quasi batch mode. \end_layout \begin_layout Standard You may type in expressions, functions ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Expressions,-Functions,-and" nolink "false" \end_inset ) or commands ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" nolink "false" \end_inset ) into the input console to elaborate on data already achieved from the interactive simulation session. \end_layout \begin_layout Standard Sequences of commands, functions and control structures ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Control-Structures" nolink "false" \end_inset ) may be assembled as a script ( \begin_inset CommandInset ref LatexCommand ref reference "sec:SCRIPTS" nolink "false" \end_inset ) into a file, and then activated by just typing the file name into the console input of an interactive ngspice session. \end_layout \begin_layout Standard \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Netlists ! .control sections \end_layout \end_inset Finally, and most useful, is to add a script to the input file, in addition the the netlist and dot commands. This is achieved by enclosing the script into \family typewriter .control ... .endc \family default (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Interactive-mode-with" nolink "false" \end_inset , and \begin_inset CommandInset ref LatexCommand ref reference "subsec:Parameter-sweep" nolink "false" \end_inset for an example). This feature enables a wealth of control options. You may set internal ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset ) and other variables, start a simulation, evaluate the simulation output, start a new simulation based on these data, and finally make use of many options for outputting the data (graphically or into output files). \end_layout \begin_layout Standard Historical note: The final releases of Berkeley Spice introduced a command shell and scripting possibilities. The former releases were not interactive. The choice for the scripting language was an early version of `csh', the C-shell, which was \emph on en vogue \emph default back then as an improvement over the ubiquitous Bourne Shell. Berkeley Spice incorporated a modified csh source code that, instead of invoking the unix `exec' system call, executed internal SPICE C subroutines. Apart from bug fixes, this is still how ngspice works. \end_layout \begin_layout Standard One important difference from C-shell is that ngspice does not support multiple commands on one line, separated by ';'. In ngspice, semi-colons introduce a comment. \end_layout \begin_layout Standard The csh-like scripting language is active in \family typewriter .control \family default sections. It works on `strings', and does string substitution of `environment' variables. You see the csh at work in ngspice with \family typewriter set foo = "bar"; set baz = "bar$foo" \family default , and in \family typewriter if \family default , \family typewriter repeat \family default , \family typewriter for \family default , ... constructs. However, ngspice processes mainly numerical data, and support for this was not available in the c-sh implementation. Therefore, Berkeley implemented an additional type of variables, with different syntax, to access double and complex double vectors (possibly of length 1). This new variable type is modified with \family typewriter let \family default , and can be used without special syntax in places where a numerical expression is expected: \family typewriter let bar = 4 * 5; let zoo = bar * 4 \family default works. Unfortunately, occasionally one has to cross the boundary between the numeric and the string domain. For this purpose the \family typewriter $& \family default construct is available – it queries a variable in the numerical \family typewriter let \family default domain, and expands it to a c-sh string denoting the value. This lets you do do something like \family typewriter set another = "this is $&bar" \family default . It is important to remember that \family typewriter set \family default can only operate on (c-sh) strings, and that \family typewriter let \family default operates only on numeric data contained in vectors. Convert from numeric to string with \family typewriter $& \family default , and from string to numeric with \family typewriter $ \family default . \end_layout \begin_layout Section \begin_inset Index idx range none pageformat default status open \begin_layout Plain Layout Parsers for expressions ! control language parser \end_layout \end_inset \begin_inset CommandInset label LatexCommand label name "sec:Expressions,-Functions,-and" \end_inset Expressions, Functions, and Constants \end_layout \begin_layout Standard Ngspice stores data in the form of vectors: time, voltage, etc. Each vector has a type, and vectors can be operated on and combined algebraically in ways consistent with their types. Vectors are normally created as the output of a simulation, or when a data file (output raw file) is read in again (ngspice using the the \family sans load \family default command \begin_inset CommandInset ref LatexCommand ref reference "subsec:Load:-Load-rawfile" nolink "false" \end_inset . They can also be created with the \family sans let \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Let:-Assign-a" nolink "false" \end_inset ) and \family sans \shape italic \emph on compose \family default \shape default \emph default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compose:-Compose-a" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) commands. Arithmetic and logical operations on vectors with multiple elements are done in parallel, with the shorter vector padded as needed by duplicating the last entry. \end_layout \begin_layout Standard An expression is an algebraic formula involving vectors and scalars (a scalar is a numeric constant or a vector of length 1) and the following arithmetic operations: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout + - * / ^ % , \end_layout \end_inset \end_layout \begin_layout Standard % is the modulo operator, and the comma operator has two meanings: if it is present in the argument list of a user definable function, it serves to separate the arguments. Otherwise, the term \family typewriter x , y \family default is synonymous with \family typewriter x + j(y) \family default . Also available are the logical operations & (and), | (or), ! (not), and the relational operations <, >, >=, <=, =, and <> (not equal). If used in an algebraic expression they work as they would in C, with any non-zero number considered logically true, and producing values of 0 or 1. The relational operators have the following synonyms: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Operator \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Synonym \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout gt \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout > \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout lt \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout < \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ge \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout >= \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout le \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout <= \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ne \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout <> \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout and \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout & \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout or \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout | \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ! \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout eq \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout = \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The operators are useful when < and > might be confused with the internal IO redirection (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Command-Interpretation" nolink "false" \end_inset , which is almost always happening). It is however safe to use < and > with the \family typewriter \series bold define \family default \series default command ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Define:-Define-a" nolink "false" \end_inset ). \end_layout \begin_layout Standard \noindent The C-style conditional operator evaluates one of two expressions chosen by the logical value of a condition: \begin_inset Quotes eld \end_inset \shape italic cond ? expr1 : expr2 \shape default \begin_inset Quotes erd \end_inset . The \emph on cond \emph default term must be a scalar. \end_layout \begin_layout Standard Utility functions for vectors are listed in the following table: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Function \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout v(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout This pseudo-function effectively quotes its argument, and gives access to vectors whose names are numbers, typically saved node values from a simulation. With two arguments, \emph on v(a, b) \emph default behaves as \emph on v(a) - v(b) \emph default . \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout i(source) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout This pseudo-function gives access to the current through a voltage source, if the matching \emph on source#branch \emph default vector was saved. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout length(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The number of entries in the vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout unitvec(number) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The result is a vector of length number, all elements having a value 1. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout vector(number) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The result is a vector of length number, with elements 0, 1, ... number - 1. If number is a vector then just the first element is taken, and if it isn't an integer then the floor of the magnitude is used. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout cvector(number) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Return a vector of length number, containing complex elements, with the real part values increasing from 0 to number-1, the imaginary values are set to 0. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout timer(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns CPU-time minus the value of the first vector element. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout clock(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns wall-time minus the value of the first vector element. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The following mathematical functions are available: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Function \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout mag(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Magnitude of vector (same as abs(vector)). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ph(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Phase of complex vector, in radians. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout cph(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Phase of complex vector, in radians. Continuous values, no discontinuity at ± \begin_inset Formula $\pi$ \end_inset . \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout unwrap(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Phase of vector with real phase vector in degrees as input and output. Continuous values, no discontinuity at ±180. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout j(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout i (sqrt(-1)) times vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout real(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The real component of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout imag(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The imaginary part of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout conj(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The complex conjugate of a vector \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout db(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 20 log10(mag(vector)). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout log10(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The logarithm (base 10) of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout log(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The natural logarithm (base e) of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ln(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The natural logarithm (base e) of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout exp(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout e to the vector power. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout abs(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The absolute value of vector (same as mag). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sqrt(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The square root of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sin(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The sine of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout cos(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The cosine of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout tan(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The tangent of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout atan(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The inverse tangent of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sinh(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The hyperbolic sine of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout cosh(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The hyperbolic cosine of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout tanh(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The hyperbolic tangent of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout atanh(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The inverse hyperbolic tangent of vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout floor(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Largest integer that is less than or equal to vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ceil(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Smallest integer that is greater than or equal to vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout norm(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The vector normalized to 1 (i.e, the largest magnitude of any component is 1). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout mean(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The result is a scalar (a length 1 vector) that is the mean of the elements of vector (elements values added, divided by number of elements). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout avg(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The average of a vector. \begin_inset Newline newline \end_inset Returns a vector where each element is the mean of the preceding elements of the input vector (including the actual element). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout stddev(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The result is a scalar (a length 1 vector) that is the standard deviation of the elements of vector . \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout group_delay(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Calculates the group delay \begin_inset Formula $-dphase[rad]/dω[rad/s]$ \end_inset . Input is the complex vector of a system transfer function versus frequency, resembling damping and phase per frequency value. Output is a vector of group delay values (real values of delay times) versus frequency. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Function \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout integ(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Integrates over the given vector (versus the real component of the scale vector), using the trapeziodal method. The result is another vector, showing the integral up to the current scale value. See also \begin_inset CommandInset ref LatexCommand ref reference "subsec:Integ" nolink "false" \end_inset for measuring the integral sum for a section of a vector, and \begin_inset CommandInset ref LatexCommand ref reference "subsec:Integrator" nolink "false" \end_inset for integration on the fly during a transient simulation. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout deriv(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Calculates the derivative of the given vector. This uses numeric differentiation by interpolating a polynomial. The degree of the polynomal may be set by the variable \family sans dpolydegree \family default (default is 2). The procedure may not produce satisfactory results (particularly with iterated differentiation). The implementation only calculates the derivative with respect to the real component of that vector's scale. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout vecd(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Compute the differential of a vector. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout vecmin(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns the value of the vector element with minimum value. Same as minimum. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout minimum(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns the value of the vector element with minimum value. Same as vecmin. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout vecmax(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns the value of the vector element with maximum value. Same as maximum. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout maximum(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns the value of the vector element with maximum value. Same as vecmax. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout fft(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout fast fourier transform ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:fft:-fast-Fourier" nolink "false" \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ifft(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout inverse fast fourier transform ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:fft:-fast-Fourier" nolink "false" \end_inset ) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sortorder(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns a vector with the positions of the elements in a real vector after they have been sorted into increasing order using a stable method (qsort). \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout m3avg(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \nospellcheck off \bar no \strikeout off \xout off \uuline off \uwave off \noun off \color none Returns a vector. Used for filtering of trap ringing after tran simulation. Moving average across three time steps with D(tn) = (C(tn-1)/2 + C(tn) + C(tn+1)/2)/2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \nospellcheck off \bar no \strikeout off \xout off \uuline off \uwave off \noun off \color none mtimeavg(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family roman \series medium \shape up \size normal \emph off \nospellcheck off \bar no \strikeout off \xout off \uuline off \uwave off \noun off \color none Returns a vector after moving window filtering with function. A window of fixed time width is given by 'set mtimeavgwindow=400u'. The boundaries for averaging are +/- mtimeavgwindow/2. Length and scale of the result vector resembles the original vector. Large vector and large window take their time. OpenMP is used if available. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Several functions offering statistical procedures are listed in the following table: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Function \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout rnd(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A vector with each component a random integer between 0 and the absolute value of the input vector's corresponding integer element value. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sgauss(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns a vector of random numbers drawn from a Gaussian distribution (real value, mean = 0 , standard deviation = 1). The length of the vector returned is determined by the input vector. The contents of the input vector will not be used. A call to sgauss(0) will return a single value of a random number as a vector of length 1. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sunif(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns a vector of random real numbers uniformly distributed in the interval [-1 .. 1[. The length of the vector returned is determined by the input vector. The contents of the input vector will not be used. A call to sunif(0) will return a single value of a random number as a vector of length 1. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout poisson(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns a vector with its elements being integers drawn from a Poisson distribution. The elements of the input vector (real numbers) are the expected numbers \begin_inset Formula $λ$ \end_inset . Complex vectors are allowed, real and imaginary values are treated separately. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout exponential(vector) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Returns a vector with its elements (real numbers) drawn from an exponential distribution. The elements of the input vector are the respective mean values (real numbers). Complex vectors are allowed, real and imaginary values are treated separately. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard An input vector may be either the name of a vector already defined or a floating-point number (a scalar). A scalar will result in an output vector of length 1. A number may be written in any format acceptable to ngspice, such as 14.6Meg or -1.231e-4. Note that you can either use scientific notation or one of the abbreviations like MEG or G, but not both. As with ngspice, a number may have trailing alphabetic characters. \end_layout \begin_layout Standard The notation \family sans expr [num] \family default denotes the num'th element of expr. For multi-dimensional vectors, a vector of one less dimension is returned. Also for multi-dimensional vectors, the notation \family sans expr[m][n] \family default will return the nth element of the mth subvector. To get a subrange of a vector, use the form \family sans expr[lower, upper] \family default . To reference vectors in a plot that is not the current plot (see the \family sans setplot \family default command, below), the notation \family sans plotname.vecname \family default can be used. Either a plotname or a vector name may be the wildcard \family sans all \family default . If the plotname is \family sans all \family default , matching vectors from all plots are specified, and if the vector name is all, all vectors in the specified plots are referenced. Note that you may not use binary operations on expressions involving wildcards - it is not obvious what \family sans all + all \family default should denote, for instance. Some (contrived) examples of expressions are shown below. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Expressions examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout cos(TIME) + db(v(3)) \end_layout \begin_layout Plain Layout sin(cos(log([1 2 3 4 5 6 7 8 9 10]))) \end_layout \begin_layout Plain Layout TIME * rnd(v(9)) - 15 * cos(vin#branch) ^ [7.9e5 8] \end_layout \begin_layout Plain Layout not ((ac3.FREQ[32] & tran1.TIME[10]) gt 3) \end_layout \begin_layout Plain Layout (sunif(0) ge 0) ? 1.0 : 2.0 \end_layout \begin_layout Plain Layout mag(fft(v(18))) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Vector names in ngspice may look like \family sans @dname[param] \family default , where dname is either the name of a device instance or of a device model. The vector contains the value of the parameter of the device or model. See Appendix, Chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Model-and-Device" nolink "false" \end_inset for details of which parameters are available. The returned value is a vector of length 1. Please note that finding the value of device and device model parameters can also be done with the show command (e.g. \family typewriter show v1 : dc \family default ). \end_layout \begin_layout Standard There are a number of pre-defined constants in ngspice, which you may use by their name. They are stored in plot ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Plots" nolink "false" \end_inset ) \family typewriter const \family default and are listed in the table below: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Description \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Value \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout pi \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\pi$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 3.14159... \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout e \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $e$ \end_inset (the base of natural logarithms) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 2.71828... \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout c \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $c$ \end_inset (the speed of light) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 299,792,458 \begin_inset Formula $\nicefrac{m}{sec}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout i \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout i (the square root of -1) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \begin_inset Formula $\sqrt{-1}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout kelvin \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout (absolute zero in centigrade) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout -273.15 \begin_inset Formula $°C$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout echarge \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout q (the charge of an electron) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.60219e-19 C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout boltz \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout k (Boltzmann's constant) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1.38062e-23 \begin_inset Formula $\nicefrac{J}{K}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout planck \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout h (Planck's constant) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 6.62607e-34 J s \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout yes \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout boolean \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout no \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout boolean \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout TRUE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout boolean \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 1 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout FALSE \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout boolean \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout 0 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard These constants are all given in MKS units. If you define another variable with a name that conflicts with one of these then it takes precedence. \end_layout \begin_layout Standard Additional constants may be generated during circuit setup (see \family typewriter .csparam \family default , \begin_inset CommandInset ref LatexCommand ref reference "sec:.csparam" nolink "false" \end_inset ). \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Plots" \end_inset Plots \end_layout \begin_layout Standard The output vectors of any analysis are stored in plots, a traditional SPICE notion. A plot is a group of vectors. A first \family typewriter tran \family default command will generate several vectors within a plot tran1. A subsequent \family typewriter tran \family default command will store their vectors in tran2. Then a \family typewriter linearize \family default command will linearize all vectors from tran2 and store them in tran3, which then becomes the current plot. A \family typewriter fft \family default will generate a plot spec1, again now the current plot. The \family typewriter display \family default command always will show all vectors in the current plot. \family typewriter Echo $plots \family default followed by Return lists all plots generated so far \family typewriter \series bold . \series default Setplot \family default followed by Return will show all plots and ask for a (new) plot to become current. A simple Return will end the command. \family typewriter Setplot name \family default will change the current plot to 'name' (e.g. \family typewriter setplot tran2 \family default will make tran2 the current plot). A sequence \family typewriter \series bold name.vector \family default \series default may be used to access the vector from a foreign plot. \end_layout \begin_layout Standard You may generate plots by yourself: \family typewriter setplot new \family default will generate a new plot named unknown1, \family typewriter set curplottitle= \begin_inset Quotes erd \end_inset a new plot \begin_inset Quotes erd \end_inset \family default will set a title, set \family typewriter curplotname=myplot \family default will set its name as a short description, set \family typewriter curplotdate= \begin_inset Quotes erd \end_inset Sat Aug 28 10:49:42 2010 \begin_inset Quotes erd \end_inset \family default will set its date. Note that strings with spaces have to be given with double quotes. \end_layout \begin_layout Standard Of course the notion 'plot' will be used by this manual also in its more common meaning, denoting a graphics plot or being a \family typewriter plot \family default command. Be careful to get the correct meaning. \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Command-Interpretation" \end_inset Command Interpretation \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:On-the-console" \end_inset On the console \end_layout \begin_layout Standard On the ngspice console window (or into the Windows GUI) you may directly type in any command from \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" nolink "false" \end_inset . Within a command sequence, Input/output redirection is available (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Output-redirection" nolink "false" \end_inset for an example) - the symbols \family typewriter > \family default , \family typewriter >> \family default , \family typewriter >& \family default , \family typewriter >>& \family default , and \family typewriter < \family default have the same effects as in the C-shell. This I/O-redirection is internal to ngspice commands, and should not be mixed up with the `external' I/O-redirection offered by the usual shells (Linux, MSYS etc.), see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Shell:-Call-the" nolink "false" \end_inset . \end_layout \begin_layout Subsection Scripts \end_layout \begin_layout Standard If a word is typed as a command, and there is no built-in command with that name, the directories in the \family typewriter sourcepath \family default list are searched in order for a file with the name given by the word. If it is found, it is read in as a input file (as if it were sourced). Such a file will often be a pure script containing only interpreter commands. Such files can be written to externd the command set. Full details of scripting are in \begin_inset CommandInset ref LatexCommand eqref reference "sec:SCRIPTS" plural "false" caps "false" noprefix "false" nolink "false" \end_inset . \end_layout \begin_layout Standard There are various command scripts installed in \family typewriter /usr/local/lib/spice/scripts \family default (or whatever the path is on your machine), and the default \family typewriter sourcepath \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset ) includes this directory, so you can use these command files (almost) like built-in commands. \end_layout \begin_layout Subsection Add-on to circuit file \end_layout \begin_layout Standard Probably the most common way to invoke the commands described in the following Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" nolink "false" \end_inset is to add a \family typewriter .control \family default ... \family typewriter .endc \family default section to the circuit input file (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Interactive-mode-with" nolink "false" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout pre_set strict_errorhandling \end_layout \begin_layout Plain Layout unset ngdebug \end_layout \begin_layout Plain Layout *save outputs and specials \end_layout \begin_layout Plain Layout save x1.x1.x1.7 V(9) V(10) V(11) V(12) V(13) \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout display \end_layout \begin_layout Plain Layout * plot the inputs, use offset to plot on top of each other \end_layout \begin_layout Plain Layout plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28 \end_layout \begin_layout Plain Layout * plot the outputs, use offset to plot on top of each other \end_layout \begin_layout Plain Layout plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16 \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Section \begin_inset CommandInset label LatexCommand label name "sec:Commands" \end_inset Commands \end_layout \begin_layout Standard Commands marked with a * are only available in standard ngspice, not in shared ngspice. Those marked with ** are available in shared ngspice only. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Ac*:-Perform-an" \end_inset Ac: Perform an AC, small-signal frequency response analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ac ( DEC | OCT | LIN ) N Fstart Fstop \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Do an small signal ac analysis (see also Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.AC:-Small-Signal-AC" nolink "false" \end_inset ) over the specified frequency range. \end_layout \begin_layout Standard \family typewriter \series bold DEC \family default \series default decade variation, and \family typewriter \series bold N \family default \series default is the number of points per decade. \end_layout \begin_layout Standard \family typewriter \series bold OCT \family default \series default stands for octave variation, and \family typewriter \series bold N \family default \series default is the number of points per octave. \end_layout \begin_layout Standard \family typewriter \series bold LIN \family default \series default stands for linear variation, and \family typewriter \series bold N \family default \series default is the number of points. \end_layout \begin_layout Standard \family typewriter \series bold fstart \family default \series default is the starting frequency, and \family typewriter \series bold fstop \family default \series default is the final frequency. \end_layout \begin_layout Standard Note that in order for this analysis to be meaningful, at least one independent source must have been specified with an ac value. \end_layout \begin_layout Standard In this ac analysis all non-linear devices are linearized around their actual dc operating point. Each Ls and Cs gets its imaginary value based on the actual frequency step. Each output vector will be calculated relative to the input voltage (current) given by the ac value (Iin equals to 1 in the example below). The resulting node voltages (and branch currents) are complex vectors. Therefore you have to be careful using the plot command. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * AC test \end_layout \begin_layout Plain Layout Iin 1 0 AC 1 \end_layout \begin_layout Plain Layout R1 1 2 100 \end_layout \begin_layout Plain Layout L1 2 0 1 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout AC LIN 101 10 10K \end_layout \begin_layout Plain Layout plot v(2) $ real part ! \end_layout \begin_layout Plain Layout plot mag(v(2)) $ magnitude \end_layout \begin_layout Plain Layout plot db(v(2)) $ same as vdb(2) \end_layout \begin_layout Plain Layout plot imag(v(2)) $ imaginary part of v(2) \end_layout \begin_layout Plain Layout plot real(v(2)) $ same as plot v(2) \end_layout \begin_layout Plain Layout plot phase(v(2)) $ phase in rad \end_layout \begin_layout Plain Layout plot cph(v(2)) $ phase in rad, continuous beyond pi \end_layout \begin_layout Plain Layout plot 180/PI*phase(v(2)) $ phase in degrees \end_layout \begin_layout Plain Layout set units = degrees \end_layout \begin_layout Plain Layout plot phase(v(2)) $ phase in degrees \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard In addition to the plot examples given above you may use the variants of vxx(node) described in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.PRINT-Lines" nolink "false" \end_inset like \family typewriter vdb(2) \family default . If you apply this notion to another plot \family typewriter ac3 \family default , the term \family typewriter vdb(ac3.2) \family default is o.k., however \family typewriter ac3.vdb(2) \family default is not. \end_layout \begin_layout Standard An option to suppress OP analysis before AC may be set for linear circuits ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:AC-Solution-Options" nolink "false" \end_inset ). \end_layout \begin_layout Standard Output parameters like \family typewriter @m1[cgs] \family default or \family typewriter @r1[i] \family default (see \begin_inset CommandInset ref LatexCommand ref reference "cha:Model-and-Device" nolink "false" \end_inset ) are not supported during AC simulation. \end_layout \begin_layout Subsection Alias: Create an alias for a command \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout alias [word] [text ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Causes word to be aliased to text. \family typewriter History \family default substitutions may be used, as in C-shell aliases. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Alter*:-Change-a" \end_inset Alter: Change a device or model parameter \end_layout \begin_layout Standard Alter changes the value for a device or a specified parameter of a device or model. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout alter dev = \end_layout \begin_layout Plain Layout alter dev param = \end_layout \begin_layout Plain Layout alter @dev[param] = \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard < \shape italic expression \shape default > must be real (complex isn't handled right now, integer is fine though, but no strings. For booleans, use 0/1). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Old style (pre 3f4): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout alter device value \end_layout \begin_layout Plain Layout alter device parameter value [ parameter value ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Using the old style, its first form is used by simple devices that have one principal value (resistors, capacitors, etc.) where the second form is for more complex devices (bjt's, etc.). Model parameters can be changed with the second form if the name contains a ` \family typewriter # \family default '. For specifying a list of parameters as values, start it with ` \family typewriter [ \family default ', followed by the values in the list, and end with ` \family typewriter ] \family default '. Be sure to place a space between each of the values and before and after the ` \family typewriter [ \family default ' and ` \family typewriter ] \family default '. \end_layout \begin_layout Standard Some examples are given below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Examples (Spice3f4 style): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout alter vd = 0.1 \end_layout \begin_layout Plain Layout alter vg dc = 0.6 \end_layout \begin_layout Plain Layout alter @m1[w]= 15e-06 \end_layout \begin_layout Plain Layout alter @vg[sin] [ -1 1.5 2MEG ] \end_layout \begin_layout Plain Layout alter @Vi[pwl] = [ 0 1.2 100p 0 ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold alter \series default may have vectors ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Vectors" nolink "false" \end_inset ) or variables ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Variables" nolink "false" \end_inset ) as parameters. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Examples (vector or variable in parameter list): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout let newfreq = 10k \end_layout \begin_layout Plain Layout alter @vg[sin] [ -1 1.5 $&newfreq ] $ vector \end_layout \begin_layout Plain Layout set newperiod = 150u \end_layout \begin_layout Plain Layout alter @Vi[pwl] = [ 0 1.2 $newperiod 0 ] $ variable \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard You may change a parameter of a device residing in a subcircuit, e.g. of MOS transistor msub1 in subcircuit xm1 (see also Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Accessing-internal-device" nolink "false" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Examples (parameter of device in subcircuit): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout alter m.xm1.msub1 w = 20u \end_layout \begin_layout Plain Layout alter @m.xm1.msub1[w] = 20u \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Altermod*:-Change-a" \end_inset Altermod: Change model parameter(s) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout altermod mod param = \end_layout \begin_layout Plain Layout altermod @mod[param] = \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout altermod nc1 tox = 10e-9 \end_layout \begin_layout Plain Layout altermod @nc1[tox] = 10e-9 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold Altermod \series default operates on models and is used to change model parameters. The above example will change the parameter \family typewriter tox \family default in all devices using the model \family typewriter nc1 \family default , which is defined as \end_layout \begin_layout LyX-Code *** BSIM3v3 model \end_layout \begin_layout LyX-Code .MODEL nc1 nmos LEVEL=8 version = 3.2.2 \end_layout \begin_layout LyX-Code + acm = 2 mobmod = 1 capmod = 1 noimod = 1 \end_layout \begin_layout LyX-Code + rs = 2.84E+03 rd = 2.84E+03 rsh = 45 \end_layout \begin_layout LyX-Code + tox = 20E-9 xj = 0.25E-6 nch = 1.7E+17 \end_layout \begin_layout LyX-Code + ... \end_layout \begin_layout Standard If you invoke the model by the MOS device \end_layout \begin_layout Standard \family typewriter M1 d g s b nc1 w=10u l=1u \end_layout \begin_layout Standard you might also insert the device name M1 for \family typewriter mod \family default as in \end_layout \begin_layout Standard \family typewriter altermod M1 tox = 10e-9 \end_layout \begin_layout Standard The model parameter \family typewriter tox \family default will be modified, however not only for device M1, but for all devices using the associated MOS model nc1! \end_layout \begin_layout Standard If you want to run corner simulations within a single simulation flow, the following option of altermod may be of help. The existing models are defined during circuit setup at start up of ngspice. Model parameter sets have been included by \family typewriter .model \family default statements ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Device-Models" nolink "false" \end_inset ) in your input file or included by the \family typewriter .include \family default command. The parameter set with name \family typewriter nc1 \family default may be overrun by the altermod command specifying a model file. All parameter values fitting to the existing model \family typewriter nc1 \family default will be modified. As usual the 'reset' command (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Reset*:-Reset-an" nolink "false" \end_inset ) restores the original values. The model file (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Device-Models" nolink "false" \end_inset ) has to use the standard specifications for an input file, the \family typewriter .model \family default section is the relevant part. However the first line in the model file will be ignored by the input parser, so it should contain only some title information. The \family typewriter .model \family default statement should appear then in the second or any later line. More than one \family typewriter .model \family default section may reside in the file. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout altermod mod1 [mod2 .. mod15] file = \end_layout \begin_layout Plain Layout altermod mod1 [mod2 .. mod15] file \end_layout \end_inset \end_layout \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout altermod nc1 file = BSIM3_nmos.mod \end_layout \begin_layout Plain Layout altermod nc1 pc1 file BSIM4_mos.mod \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Be careful that the new model file corresponds to the existing model selected by token \family sans nc1 \family default . In the example given above, the models \family sans nc1 \family default (or \family sans nc1 \family default and \family sans pc1 \family default ) have to be already included in the netlist before calling \family typewriter altermod \family default . If they are not found in the active circuit, ngspice will terminate with an error message. The file BSIM3_nmos.mod has to include a .model line starting with \family sans .MODEL nc1 nmos \family default .... There is no checking however of the version and level parameters! So you have to be responsible for offering model data of the same model name ( \family sans nc1 \family default ) and level (e.g. level 8 for BSIM3). Thus no new model is selectable by \family typewriter altermod \family default , but the parameters of the existing model(s) (here \family sans nc1 \family default and \family sans pc1 \family default ) may be changed (partially, completely, temporarily). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Alterparam*:-Change-value" \end_inset Alterparam: Change value of a global parameter \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout alterparam paramname=pvalue \end_layout \begin_layout Plain Layout alterparam subname paramname=pvalue \end_layout \end_inset \end_layout \begin_layout Plain Layout Example (global, top level parameter): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .param npar = 5 \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout alterparam npar = 7 $ change npar from 5 to 7 \end_layout \begin_layout Plain Layout reset \end_layout \end_inset \end_layout \begin_layout Plain Layout Example (parameter in a subcircuit): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .subckt sname \end_layout \begin_layout Plain Layout .param subpar = 13 \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout .ends \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout alterparam sname subpar = 11 $ change subpar from 13 to 11 \end_layout \begin_layout Plain Layout reset \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold Alterparam \series default operates on global parameters or on parameters in a subcircuit defined by the \family typewriter .param ... \family default statement. A subsequent call to \family typewriter reset \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Reset*:-Reset-an" nolink "false" \end_inset ) is required for the parameter value change to become effective. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Asciiplot:-Plot-values" \end_inset Asciiplot: Plot values using old-style character plots \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout asciiplot plotargs \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Produce a line printer plot of the vectors. The plot is sent to the standard output, or you can put it into a file with \family sans asciiplot args ... > file \family default . The set options width, height, and nobreak determine the width and height of the plot, and whether there are page breaks, respectively. The 'more' mode is the standard mode if printing to the screen, that is after a number of lines given by height, and after a page break printing stops with request for answering the prompt by , 'c' or 'q'. If everything shall be printed without stopping, put the command \family typewriter set nomoremode \family default into \family sans .spiceinit \family default \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" nolink "false" \end_inset (or \family sans spinit \family default \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" nolink "false" \end_inset ). Note that you will have problems if you try to \family typewriter asciiplot \family default something with an X-scale that isn't monotonic (i.e, something like sin(TIME) ), because \family typewriter asciiplot \family default uses a simple-minded linear interpolation. The \family typewriter asciiplot \family default command doesn't deal with log scales or the delta keywords. \end_layout \begin_layout Subsection Aspice*: Asynchronous ngspice run \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout aspice input-file [output-file] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Start an ngspice run, and when it is finished load the resulting data. The raw data is kept in a temporary file. If output-file is specified then the diagnostic output is directed into that file, otherwise it is thrown away. \end_layout \begin_layout Subsection Bg_ctrl**: suspend running controls until bg_run has finished \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout bg_ctrl \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Create a suspended thread to start any control commands only when \family typewriter bg_run \family default has finished. This may be achieved also by issuing \family typewriter set controlswait \family default in the beginning of a .control section. \end_layout \begin_layout Subsection Bg_halt**: halt a run \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout bg_halt \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Halt a run which has been started by \family typewriter bg_run \family default . There may be conditions where this command cannot be executed immediately. \end_layout \begin_layout Subsection Bg_run**: Run analysis from the input file in the background thread \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout bg_run \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Run the simulation as specified in the input file in the second (background) thread of shared ngspice. If there were any of the control lines \family typewriter .ac \family default , \family typewriter .op \family default , \family typewriter .tran \family default , or \family typewriter .dc \family default , they are executed. The output is available in plots and their vectors, and/or in the API via callback function \series bold SendData \series default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:typedef-int-(SendData)(pvecvalue" nolink "false" \end_inset ). \end_layout \begin_layout Subsection Bug: Output URL for ngspice bug tracker \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout bug \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Get URL to file a bug report. Please go the the URL provided by this command when you have a bug report to file. Include a short summary of the problem, the version number and name of the operating system that you are running, the version of ngspice that you are running, and any relevant ngspice input and output files. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Cd:-Change-directory" \end_inset Cd: Change directory \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout cd [directory] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Change the current working directory to directory, or to the user's home directory (Linux: HOME, MS Windows: USERPROFILE), if none is given. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Cdump:-Dump-the" \end_inset Cdump: Dump the control flow to the screen \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout cdump \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Dumps the control sequence to the screen (all statements inside the \family typewriter .control \family default ... \family typewriter .endc \family default structure before the line with cdump). Indentations show the structure of the sequence. The example below is printed if you add \series bold cdump \series default to \family sans /examples/Monte_Carlo/MonteCarlo.sp \family default . \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example (abbreviated): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout let mc_runs=5 \end_layout \begin_layout Plain Layout let run=0 \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout define agauss(nom, avar, sig) (nom + avar/sig * sgauss(0)) \end_layout \begin_layout Plain Layout define limit(nom, avar) (nom + ((sgauss(0) >=0) ? avar : -avar)) \end_layout \begin_layout Plain Layout dowhile run < mc_runs \end_layout \begin_layout Plain Layout alter c1=unif(1e-09, 0.1) \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout ac oct 100 250k 10meg \end_layout \begin_layout Plain Layout meas ac bw trig vdb(out) val=-10 rise=1 targ vdb(out) \end_layout \begin_layout Plain Layout + val=-10 fall=1 \end_layout \begin_layout Plain Layout set run="$&run" \end_layout \begin_layout Plain Layout ... \end_layout \begin_layout Plain Layout let run=run + 1 \end_layout \begin_layout Plain Layout end \end_layout \begin_layout Plain Layout plot db({$scratch}.allv) \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout print {$scratch}.bwh \end_layout \begin_layout Plain Layout cdump \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Circbyline*:-Enter-a" \end_inset Circbyline: Enter a circuit line by line \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout circbyline line \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Enter a circuit line by line. \series bold line \series default is any circuit line, as found in the \family sans *.cir \family default ngspice input files. The first line is a title line. The entry will be finished by entering \family typewriter .end \family default . Circuit parsing is then started automatically. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout circbyline test circuit \end_layout \begin_layout Plain Layout circbyline v1 1 0 1 \end_layout \begin_layout Plain Layout circbyline r1 1 0 1 \end_layout \begin_layout Plain Layout circbyline .dc v1 0.5 1.5 0.1 \end_layout \begin_layout Plain Layout circbyline .end \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot i(v1) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Codemodel:-Load-an" \end_inset Codemodel: Load an XSPICE code model library \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout codemodel [library file] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Load a XSPICE code model shared library file (e.g. \family sans analog.cm \family default ...). Only available if ngspice is compiled with the XSPICE option ( \family typewriter --enable-xspice \family default ) or with the Windows executable distributed since ngspice21. This command has to be called from \family sans spinit \family default (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" nolink "false" \end_inset ) (or \family sans .spiceinit \family default for personal code models, \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" nolink "false" \end_inset ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Compose:-Compose-a" \end_inset Compose: Compose a vector \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form 1 - List of values: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout compose name values value1 [ value2 ... ] \end_layout \end_inset \end_layout \begin_layout Plain Layout General forms 2 - Linearly spaced values: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout compose name start=val stop=val step=val \end_layout \begin_layout Plain Layout compose name center=val span=val step=val \end_layout \begin_layout Plain Layout compose name lin=val center=val span=val \end_layout \begin_layout Plain Layout compose name lin=val \end_layout \end_inset \end_layout \begin_layout Plain Layout General forms 3 - Logarithmically spaced values: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout compose name (log=val | dec=val | oct=val) start=val stop=val \end_layout \begin_layout Plain Layout compose name (log=val | dec=val | oct=val) center=val span=val \end_layout \end_inset \end_layout \begin_layout Plain Layout General form 4 - Gaussian distributed values: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout compose name gauss=val \end_layout \end_inset \end_layout \begin_layout Plain Layout General forms 5 - Uniformly distributed values: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout compose name unif=val \end_layout \begin_layout Plain Layout compose name unif=val start=val stop=val \end_layout \end_inset \end_layout \begin_layout Plain Layout General form 6 - XSPICE node history: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout compose event-node-name xspice \end_layout \end_inset \end_layout \begin_layout Plain Layout General form 7 - Make vector(s) from device parameters: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout compose parameter-name device \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The general form 1 takes the values and creates a new vector, where the \emph on values \emph default may be arbitrary expressions. If negative numbers or expressions starting with '-' are to be entered, put them into brackets, e.g. (-2.364) or (-5*PI). \end_layout \begin_layout Standard The forms 2 - 5 create a new vector according the following possible parameters: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \family typewriter start \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Value of \emph on name \emph default [0] (default: 0) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter stop \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Last value of \emph on name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter step \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Difference between successive elements of the linearly spaced vector (default: 1) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter lin \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number of points, linearly spaced \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter log \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number of points, logarithmically spaced \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter dec \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number of points per decade, logarithmically spaced \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout oct \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number of points per octave, logarithmically spaced \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter center \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Where to center the range of points \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter span \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Size of the range of points (default for uniform distribution: 1) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter gauss \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number of points, Gaussian distributed \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter mean \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Mean value of the Gaussian (default 0) or uniform distribution (default 0.5) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout sd \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Standard deviation for the Gaussian distribution (default 1) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter unif \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Number of points, uniformly distributed \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Form 6 creates a vector from the saved history of an XSPICE event node with similar results to plotting or printing an event node. \end_layout \begin_layout Subsection Cutout: Cut out a section of all vectors in a tran plot \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout let cut-tstart = time1 \end_layout \begin_layout Plain Layout let cut-tstop = time2 \end_layout \begin_layout Plain Layout cutout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Cut out part of each vector of the current tran plot, from times cut-tstart to cut-tstop and copy these into a new tran plot. A new scale vector 'time' will be generated as well. Vectors that are shorter than the new scale vector will not be copied. If \family typewriter cut-start \family default or \family typewriter cut-stop \family default are not given, the starting or end times of the current plot are used. \end_layout \begin_layout Standard So the simple command \family typewriter cutout \family default may be used to get rid of 0-length vectors in a new tran plot that may occur if for example something like generating \family typewriter m1[id] \family default is not served in an AC simulation. \end_layout \begin_layout Subsection Dc: Perform a DC-sweep analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout dc Source Vstart Vstop Vincr [ Source2 Vstart2 Vstop2 Vincr2 ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Do a dc transfer curve analysis. See the previous Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.DC:-DC-Transfer" nolink "false" \end_inset for more details. Several options may be set ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:DC-Solution-Options" nolink "false" \end_inset ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Define:-Define-a" \end_inset Define: Define a function \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout define function(arg1, arg2, ...) expression \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Define the function with the name function and arguments arg1, arg2, ... to be \emph on expression \emph default , which may involve the arguments. When the function is later used, the arguments it is given are substituted for the formal parameters when it was parsed. If expression is not present, any existing definition for function is printed, and if there are no arguments then expressions for all currently active definitions are printed. Note that you may have different functions defined with the same name but different arities. Some useful definitions are \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout define max(x,y) (x > y) * x + (x <= y) * y \end_layout \begin_layout Plain Layout define min(x,y) (x < y) * x + (x >= y) * y \end_layout \begin_layout Plain Layout define limit(nom, avar) (nom + ((sgauss(0) >= 0) ? avar : -avar)) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard When defining the function, the tokens used (here \family typewriter x \family default , \family typewriter y \family default , \family typewriter nom \family default , or \family typewriter avar \family default ) should not have been defined elsewhere, e.g. as vectors. Otherwise strange errors may result. \end_layout \begin_layout Subsection Deftype: Define a new type for a vector or plot \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout deftype [v | p] typename abbrev \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard defines types for vectors and plots. abbrev will be used to parse things like abbrev(name) and to label axes with M, instead of numbers. Also, the command `deftype p plottype pattern ...' will assign plottype as the name for any plot with one of the patterns in its Name: field. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout deftype v capacitance F \end_layout \begin_layout Plain Layout settype capacitance moscap \end_layout \begin_layout Plain Layout plot moscap vs v(cc) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Delete*:-Remove-a" \end_inset Delete: Remove a trace or breakpoint \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout delete [ debug-number ... ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Delete the specified saved nodes and parameters, breakpoints and traces. The debug numbers are those shown by the status command (unless you do \family sans status > file \family default , in which case the debug numbers are not printed). \end_layout \begin_layout Subsection Destroy: Delete an output data set \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout destroy [plotnames | all] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Release the memory holding the output data (the given plot or all plots) for the specified runs. The initial plot, "const", can not be destroyed. \end_layout \begin_layout Subsection Devhelp: information on available devices \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout devhelp [-csv] [-type] [-flags] [device_name [parameter]] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Devhelp command shows the user information about the devices available in the simulator. If called without arguments, it simply displays the list of available devices in the simulator. The name of the device is the name used inside the simulator to access that device. If the user specifies a device name, then all the parameters of that device (model and instance parameters) will be printed. Parameter description includes the internal ID of the parameter ( \family typewriter id# \family default ), the name used in the model card or on the instance line ( \emph on Name \emph default ), the direction ( \emph on Dir \emph default ) and the description of the parameter ( \emph on Description \emph default ). All the fields are self-explanatory, except the ` \emph on direction \emph default '. Direction can be \family typewriter in \family default , \family typewriter out \family default or \family typewriter inout \family default and corresponds to a ` \emph on write-only \emph default ', ` \emph on read-only \emph default ' or a ` \emph on read/write \emph default ' parameter. Read-only parameters can be read but not set, write only can be set but not read and \emph on read/write \emph default can be both set and read by the user. \end_layout \begin_layout Standard The \family typewriter -type \family default option prints the type of each parameter, for example \family typewriter real \family default , \family typewriter integer \family default , \family typewriter string \family default . Values ending with \family typewriter vec \family default indicate vectors. \end_layout \begin_layout Standard The \family typewriter -csv \family default option prints the fields, separated by a commas, for direct import into a spreadsheet. This option is used to generate the simulator documentation. \end_layout \begin_layout Standard The \family typewriter -flags \family default option prints the internal Spice flags for each parameter. A specific string is appended to the result for each flag: \end_layout \begin_layout Description X the parameter is not used in sensitivity analysis. \end_layout \begin_layout Description Q the parameter must be non-zero for sensitivity analysis of the subsequent parameter. \end_layout \begin_layout Description Z the previous parameter must be non-zero for sensitivity analysis. \end_layout \begin_layout Description QO Like Q, but or-ed with the previous Q value. \end_layout \begin_layout Description A the parameter is significant for time-varying (non-DC) analyses. \end_layout \begin_layout Description P the parameter is a principal of the device. Used for naming output variables in sensitivity. \end_layout \begin_layout Description AA the parameter is significant for AC analyses only. \end_layout \begin_layout Description N the parameter is significant for noise analyses only. \end_layout \begin_layout Description U the parameter is not shown in the default \family typewriter show \family default command output. \end_layout \begin_layout Description R redundant parameter name (e.g. \family typewriter vto \family default vs. \family typewriter vt0 \family default ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout devhelp \end_layout \begin_layout Plain Layout devhelp resistor \end_layout \begin_layout Plain Layout devhelp capacitor ic \end_layout \begin_layout Plain Layout devhelp -flags -type bjt \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Diff:-Compare-vectors" \end_inset Diff: Compare vectors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout diff plot1 plot2 [vec ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Compare all the vectors in the specified plots, or only the named vectors if any are given. If there are different vectors in the two plots, or any values in the vectors differ significantly, the difference is reported. The variables \family sans diff_abstol \family default , \family sans diff_reltol \family default , and \family sans diff_vntol \family default are used to determine a significant difference. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Display:-List-known" \end_inset Display: List known vectors and types \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout display [varname ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Prints a summary of currently defined vectors, or of the names specified. The vectors are sorted by name unless the variable \family sans nosort \family default is set. The information given is the name of the vector, the length, the type of the vector, and whether it is real or complex data. Additionally, one vector is labeled [scale]. When a command such as \family typewriter plot \family default is given without a \family sans vs \family default argument, this scale is used for the X-axis. It is always the first vector in a rawfile, or the first vector defined in a new plot. If you undefine the scale (i.e, \family sans let TIME = [] \family default ), one of the remaining vectors becomes the new scale (which one is unpredictable). You may set the scale to another vector of the plot with the command \family typewriter \series bold \family sans \series default setscale \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Setscale:-Set-the" nolink "false" \end_inset ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Echo:-Print-text" \end_inset Echo: Print text \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout echo [-n] [text | $variable | $&vector] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Echos all text, variables and vectors to the screen or the redirected output location. If -n included as the first argument, a newline will not be printed. Otherwise one will be appended to the output. \end_layout \begin_layout Subsection Edit*: Edit the current circuit \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout edit [ file-name ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Print the current ngspice input file into a file, call up the editor on that file and allow the user to modify it, and then read it back in, replacing the original file. If a file-name is given, then edit that file and load it, making the circuit the current one. The editor may be defined in \series bold \family sans \series default .spiceinit \family default or \family sans spinit \family default by a command line like \family typewriter \end_layout \begin_layout Standard \family typewriter set editor=emacs \end_layout \begin_layout Standard Using MS Windows, to allow the \series bold edit \series default command calling an editor, you will have to add the editor's path to the PATH variable of the command prompt windows (see \begin_inset CommandInset href LatexCommand href name "here" target "http://en.wikipedia.org/wiki/Environment_variable#Examples_of_DOS_environment_variables" literal "false" \end_inset ). \series bold edit \series default then calls \family sans cmd.exe \family default with e.g. \family sans notepad++ \family default and \family typewriter file-name \family default as parameter, if you have set \end_layout \begin_layout Standard \family typewriter set editor=notepad++.exe \end_layout \begin_layout Standard in \family sans .spiceinit \family default or \family sans spinit \family default . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Edisplay*" \end_inset Edisplay: Print a list of all the event nodes \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout edisplay \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Print the node names, node types, and number of events per node of all event driven nodes generated or used by XSPICE 'A' devices. See \family typewriter eprint \family default , \family typewriter eprvcd \family default , and \begin_inset CommandInset ref LatexCommand ref reference "subsec:Running-example-C3" nolink "false" \end_inset for an example. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Eprint*:-Print-an" \end_inset Eprint: Print an event driven node \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout eprint node [node] \end_layout \begin_layout Plain Layout eprint node [node] > nodeout.txt $ output redirected \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Print an event driven node generated or used by an XSPICE 'A' device. These nodes are vectors not organized in plots. See \family typewriter edisplay \family default , \family typewriter eprvcd \family default , and Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Running-example-C3" nolink "false" \end_inset for an example. Output redirection into a file is available. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Eprvcd*-1" \end_inset Eprvcd: Dump nodes in VCD format \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout eprvcd [-t unit][-a] node1 node2 .. noden [ > filename ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Dump the data of the specified event driven nodes and others to a \family sans .vcd \family default file (see also \begin_inset CommandInset ref LatexCommand ref reference "subsec:VCD" nolink "false" \end_inset ). Such files may be viewed with an vcd viewer, for example \begin_inset CommandInset href LatexCommand href name "gtkwave" target "http://gtkwave.sourceforge.net/" literal "false" \end_inset . Values for analog nodes and expressions (as for \family typewriter plot \family default ) may be included, but expressions may not contain spaces. Option \begin_inset Quotes eld \end_inset -t \begin_inset Quotes erd \end_inset sets the VCD file's time unit; values are rounded to a negative power of 10. If not used the unit is chosen to fit the simulation's maximum timestep. Analog values are examined only when a recorded XSPICE event value changes, unless option \begin_inset Quotes eld \end_inset -a \begin_inset Quotes erd \end_inset is used to dump them at each timestep. Also see \family typewriter edisplay \family default , \family typewriter eprint \family default . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Esave:-Save-as" \end_inset Esave: Save a set of event node outputs \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout esave all | none | node ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Save a set of event node outputs, discarding the rest (if keyword \family sans all \family default is not given). May be used to dramatically reduce memory (RAM) requirements when only a few useful nodes' events are saved. \end_layout \begin_layout Standard For backward compatibility, if there are no esave commands given, all outputs are saved. If you want to \family typewriter eprint \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Eprint*:-Print-an" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) or \family typewriter eprvcd \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Eprvcd*-1" plural "false" caps "false" noprefix "false" nolink "false" \end_inset ) a node, you have to save it explicitly, except for \family sans all \family default given or no save command at all. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Don't save anything: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout esave none \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Useful if you do not need to examine the event data separately from the normal plot. \end_layout \begin_layout Subsection Fclose: close an open file handle \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout fclose handle \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This command closes an open file identified by the integer 'handle'. It ignores values less than 3 and any file that was not opened by fopen or read by fread. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:fft:-fast-Fourier" \end_inset FFT: fast Fourier transform of vectors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout fft vector1 [vector2] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This analysis provides a fast Fourier transform of the input vector(s) in forward direction. \family typewriter fft \family default is much faster than \family typewriter spec \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Spec:-Create-a" nolink "false" \end_inset ) (about a factor of 50 to 100 for larger vectors). \end_layout \begin_layout Standard The \family typewriter fft \family default command will create a new plot consisting of the Fourier transforms of the vectors given on the command line. Each vector given should be a transient analysis result, i.e. it should have \family typewriter time \family default as a scale. You will have gotten these vectors by the \family typewriter tran Tstep Tstop Tstart \family default command. \end_layout \begin_layout Standard The vector should have a linear equidistant time scale. Therefore linearization using the \family typewriter linearize \family default command is recommended before running \family typewriter fft \family default . Be careful selecting a \family typewriter Tstep \family default value small enough for good interpolation, e.g. much smaller than any signal period to be resolved by \family typewriter fft \family default (see \family typewriter linearize \family default command). The Fast Fourier Transform will be computed using a optional window function as given with the specwindow variable. A new plot named \family sans specN \family default will be generated with a new vector (having the same name as the input vector, see command above) containing the transformed data. \end_layout \begin_layout Standard Ngspice has two FFT implementations: \end_layout \begin_layout Enumerate Standard code is based on the FFT function provided by John Green `FFTs for RISC 2.0`, downloaded 2012, now to be found \begin_inset CommandInset href LatexCommand href name "here" target "http://hyperarchive.lcs.mit.edu/HyperArchive/Archive/dev/src/ffts-for-risc-2-c.hqx" literal "false" \end_inset . These are a power-of-two routines for fft and ifft. If the input size doesn't fit this requirement the remaining data will be zero padded up to the next 2 \begin_inset Formula $N$ \end_inset field size. You have to take care of the correlated change in the scale vector. \end_layout \begin_layout Enumerate If available on the operating system (see Chapter \begin_inset CommandInset ref LatexCommand ref reference "cha:Compilation-notes" nolink "false" \end_inset ) ngspice can be linked to the famous FFTW-3 package, found \begin_inset CommandInset href LatexCommand href name "here" target "http://www.fftw.org/" literal "false" \end_inset . This high performance package has advantages in speed and accuracy compared to most of the freely available FFT libraries. It makes arbitrary size transforms for even and odd data. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout How to compute the \family typewriter fft \family default from a transient simulation output: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ngspice 8 -> setplot tran1 \end_layout \begin_layout Plain Layout ngspice 9 -> linearize V(2) \end_layout \begin_layout Plain Layout ngspice 9 -> set specwindow=blackman \end_layout \begin_layout Plain Layout ngspice 10 -> fft V(2) \end_layout \begin_layout Plain Layout ngspice 11 -> plot mag(V(2)) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter Linearize \family default will create a new vector V(2) in a new plot \family typewriter tran2 \family default . The command \family typewriter fft V(2) \family default will create a new plot \family typewriter spec1 \family default with vector V(2) holding the resulting data. \end_layout \begin_layout Standard The variables listed in the following table control operation of the \family typewriter fft \family default command. Each can be set with the set command before calling \family typewriter \series bold \series default fft \family default . \end_layout \begin_layout Subparagraph specwindow \family typewriter \series medium : \end_layout \begin_layout Standard This variable is set to one of the following strings, which will determine the type of windowing used for the Fourier transform in the \family typewriter spec \family default and \family typewriter fft \family default command. If not set, the default is \family typewriter hanning \family default . \end_layout \begin_layout Standard All window functions have a rms value of 1. That means: No amplitude correction for the result is needed after applying the functions to the time domain input signal. \end_layout \begin_layout Description none No windowing \end_layout \begin_layout Description rectangular Rectangular window \end_layout \begin_layout Description bartlet Bartlett (also triangle) window \end_layout \begin_layout Description hanning Hanning (also hann or cosine) window \end_layout \begin_layout Description blackman Blackman window \end_layout \begin_layout Description blackmanharris Blackman-Harris window \end_layout \begin_layout Description hamming Hamming window \end_layout \begin_layout Description gaussian Gaussian window \end_layout \begin_layout Description flattop Flat top window \end_layout \begin_layout Standard \begin_inset Float figure placement H alignment document wide false sideways false status open \begin_layout Plain Layout \begin_inset Graphics filename Images/fft_windows.png width 70line% \end_inset \begin_inset Caption Standard \begin_layout Plain Layout Spec and FFT window functions (Gaussian order = 4) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subparagraph specwindoworder: \end_layout \begin_layout Standard This can be set to an integer in the range 2-8. This sets the order when the Gaussian window is used in the \family typewriter spec \family default and \family typewriter fft \family default commands. If not set, order 2 is used. \end_layout \begin_layout Subsection Fopen: open a text file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout fopen handle file_name [mode] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The named file is opened and a numeric handle is returned in variable 'handle', or -1 on error. This is a simple wrapper around the standard C-library function with the same name, so the meaning of string 'mode' is as defined by your OS documentation. By default the file is opened for reading only. If interpreter variable "silent_fileio" is set, no message is printed on error. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Fourier:-Perform-a" \end_inset Fourier: Perform a Fourier transform \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout fourier fundamental_frequency [expression ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold Fourier \series default is used to analyze the output vector(s) of a preceding transient analysis (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Tran*:-Perform-a" nolink "false" \end_inset ). It does a Fourier analysis of each of the given values, finding the DC level and the first 9 multiples of the fundamental frequency (or the first ( \series bold nfreqs \series default - 1) multiples, if that variable is set (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset )). The Fourier analysis is performed over the interval \family typewriter \family default , where \family typewriter TSTOP \family default is the final time specified for the transient analysis, \family typewriter period \family default is one period of the fundamental frequency and numPeriod is the value of the \series bold nperiods \series default variable, or 1. For maximum accuracy, \family typewriter TMAX \family default (see the \family typewriter .tran \family default line) should be set to \family typewriter period \family default *numperiod/100.0 (or less for very high-Q circuits). \end_layout \begin_layout Standard The printed output is like that of the \family typewriter .four \family default ngspice line (Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.FOUR:-Fourier-Analysis" nolink "false" \end_inset ). The expressions may be any valid expression (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Expressions,-Functions,-and" nolink "false" \end_inset ), e.g. v(2). The evaluated expression values are interpolated onto a fixed-space grid with the number of points given by the \series bold fourgridsize \series default variable, or 200 if it is not set. The interpolation is of degree \series bold polydegree \series default if that variable is set, or 1 otherwise. If \series bold polydegree \series default is 0, then no interpolation is done. This is likely to give erroneous results if the time scale is not monotonic. \end_layout \begin_layout Standard The \series bold fourier \series default command not only issues a printout, but also generates vectors, one per expression. The size of the vector is 3 x nfreqs (per default 3 x 10). The name of the new vector is fouriermn, where m is set by the mth call to the fourier command, n is the nth expression given in the actual fourier command. fouriermn[0] is the vector of the 10 (nfreqs) frequency values, fouriermn[1] contains the 10 (nfreqs) magnitude values, fouriermn[2] the 10 (nfreqs) phase values of the result. Vector generation may be suppressed by setting the \series bold fournosave \series default variable. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * do the transient analysis \end_layout \begin_layout Plain Layout tran 1n 1m \end_layout \begin_layout Plain Layout * do the fourier analysis \end_layout \begin_layout Plain Layout fourier 3.34e6 v(2) v(3) $ first call \end_layout \begin_layout Plain Layout fourier 100e6 v(2) v(3) $ second call \end_layout \begin_layout Plain Layout * get individual values \end_layout \begin_layout Plain Layout let newt1 = fourier11[0][1] \end_layout \begin_layout Plain Layout let newt2 = fourier11[1][1] \end_layout \begin_layout Plain Layout let newt3 = fourier11[2][1] \end_layout \begin_layout Plain Layout let newt4 = fourier12[0][4] \end_layout \begin_layout Plain Layout let newt5 = fourier12[1][4] \end_layout \begin_layout Plain Layout let newt6 = fourier12[2][4] \end_layout \begin_layout Plain Layout * plot magnitude of second expression (v(3)) \end_layout \begin_layout Plain Layout * from first call versus frequency \end_layout \begin_layout Plain Layout plot fourier12[1] vs fourier12[0] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter plot \family default command from the example plots the vector of the magnitude values, obtained by the first call to fourier and evaluating the first expression in this call, against the vector of the frequency values. \end_layout \begin_layout Subsection Fread: read into a variable from a text file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout fread result handle [length] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This command sets the string variable 'result' by reading one line from the open file specified by the integer 'handle'. Terminating characters are stripped and the length returned in variable 'length', if given. The handle will usually have been set by the fopen command, but any valid file descriptor may be used. \end_layout \begin_layout Standard The length will be -1 if attempting to read at end-of-file or -2 on error. If interpreter variable "silent_fileio" is set, no message is printed on error. \end_layout \begin_layout Subsection Getcwd: Print the current working directory \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout getcwd \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Print the current working directory. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Gnuplot:-Graphics-output" \end_inset Gnuplot: Graphics output via gnuplot \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout gnuplot file plotargs \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Like plot, but using \family sans gnuplot \family default for graphics output and further data manipulation. ngspice creates a file called \family sans file.plt \family default containing the \family sans gnuplot \family default command sequence, a file called \family sans file.data \family default containing the data to be plotted. On Linux, \family sans gnuplot \family default may be called directly or via called via \family typewriter xterm \family default , and offers a Gnuplot console to manipulate the data. On Windows, a plot window is opened and the command console window is available with a mouse click. Of course you have to have \family sans gnuplot \family default installed on your system. Please see chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Gnuplot" nolink "false" \end_inset for more details. \end_layout \begin_layout Subsection Hardcopy: Save a plot to a file for printing \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout hardcopy file plotargs \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Just like plot, except that it creates a file called \family typewriter file \family default containing the plot. Various output formats are available, depending on the variable \family typewriter hcopydevtype \family default . It may be set to \family typewriter postscript \family default or \family typewriter svg \family default . See also Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Printing-options" nolink "false" \end_inset for more details (color etc.). \end_layout \begin_layout Subsection Help: Print summaries of Ngspice commands \end_layout \begin_layout Standard Prints help. This help information, however, is spice3f5-like, stemming from 1991 and thus is outdated. If commands are given, descriptions of those commands are printed. Otherwise help for only a few major commands is printed. On Windows, this \series bold help \series default command only provides a link to documentation. Spice3f5 compatible help may be found in the \begin_inset CommandInset href LatexCommand href name "Spice 3 User manual" target "https://web.archive.org/web/20180221111839/http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/" literal "false" \end_inset . For ngspice, please use this manual. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:History:-Review-previous-commands" \end_inset History: Review previous commands \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout history [-r] [number] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Print out the history of the last (first if \series bold -r \series default is specified) \family typewriter number \family default commands typed at the keyboard. \end_layout \begin_layout Standard A history substitution enables you to reuse a portion of a previous command as you type the current command. History substitutions save typing. This feature is disabled by default, as it may interfere with use of '!' in expressions. To enable, set variable \family typewriter histsubst. \family default A history substitution normally starts with a \family typewriter '!' \family default . A history substitution has three parts: an event that specifies a previous command, a selector that selects one or more words of the event, and some modifiers that modify the selected words. The selector and modifiers are optional. A history substitution has the form \family typewriter ![event][:]selector[:modifier] \family sans \SpecialChar ldots \family typewriter ] \family default The event is required unless it is followed by a selector that does not start with a digit. The \family typewriter ':' \family default can be omitted before the selector if this selector does not begin with a digit. History substitutions are interpreted before anything else \family typewriter — \family default even before quotations and command substitutions. The only way to quote the \family typewriter '!' \family default of a history substitution is to escape it with a preceding backslash. A \family typewriter '!' \family default need not be escaped if it is followed by whitespace, \family typewriter '=' \family default , or \family typewriter '(' \family default . \end_layout \begin_layout Standard Ngspice saves each command that you type in a history list, provided that the command contains at least one word. The commands in the history list are called events. The events are numbered, with the first command that you issue when you start Ngspice being number one. The \family typewriter history \family default variable specifies how many events are retained in the history list. \end_layout \begin_layout Standard These are the forms of an event in a history substitution: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \family typewriter !! \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The preceding event. Typing \family typewriter '!!' \family default is an easy way to reissue the previous command. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter !n \family default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Event number \emph on n. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter !-n \family default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The \emph on n \emph default \begin_inset script superscript \begin_layout Plain Layout th \end_layout \end_inset previous event. For example, \family typewriter !-1 \family default refers to the immediately preceding event and is equivalent to \family typewriter !!. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter !str \family default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The unique previous event whose name starts with \emph on str. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter !?str[?] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The unique previous event containing the string \emph on str \emph default . The closing \family typewriter '?' \family default can be omitted if it is followed by a newline. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard You can modify the words of an event by attaching one or more modifiers. Each modifier must be preceded by a colon. The following modifiers assume that the first selected word is a file name: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \family typewriter :r \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Removes the trailing \family typewriter .str \family default extension from the first selected word. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter :h \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Removes a trailing path name component from the first selected word. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter :t \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Removes all leading path name components from the first selected word. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter :e \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Remove all but the trailing suffix. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter :p \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Print the new command but do not execute it. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter s/ \family default \emph on old \emph default / \emph on new \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Substitute \emph on new \emph default for the first occurrence of \emph on old \emph default in the event line. Any delimiter may be used in place of ` \family typewriter / \family default '. The delimiter may be quoted in \emph on old \emph default and \emph on new \emph default with a single backslash. If ` \family typewriter & \family default ' appears in \family typewriter new \family default , it is replaced by \family typewriter old \family default . A single backslash will quote the ` \family typewriter & \family default '. The final delimiter is optional if it is the last character on the input line. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter & \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Repeat the previous substitution. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter g a \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Cause changes to be applied over the entire event line. Used in conjunction with ` \family typewriter s \family default ', as in \family typewriter gs \family default / \emph on old \emph default / \emph on new \emph default /, or with ` \family typewriter & \family default '. \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter G \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Apply the following ` \family typewriter s \family default ' modifier once to each word in the event. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard For example, if the command \family sans ls /usr/elsa/toys.txt \family default has just been executed, then the command \family sans echo !!^:r !!^:h !!^:t !!^:t:r \family default produces the output \family sans /usr/elsa/toys /usr/elsa toys.txt toys . \family default The ' \family typewriter ^ \family default ' command is explained in the table below. \end_layout \begin_layout Standard You can select a subset of the words of an event by attaching a selector to the event. A history substitution without a selector includes all of the words of the event. These are the possible selectors for selecting words of the event: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \family sans :0 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The command name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans [:]^ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The first argument \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans [:]$ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The last argument \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans :n \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The \emph on n \emph default \begin_inset script superscript \begin_layout Plain Layout th \end_layout \end_inset argument ( \emph on n \emph default \begin_inset Formula $\geq$ \end_inset 1) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans :n1-n2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Words \emph on n \emph default 1 through \emph on n \emph default 2 \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans [:]* \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Words 1 through $ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans :x* \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Words \emph on x \emph default through $ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans :x- \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Words \emph on x \emph default through ($ - 1) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans [:]-x \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Words 0 through \emph on x \emph default \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans [:]% \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout The word matched by the last \family sans ?str? \family default search used \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The colon preceding a selector can be omitted if the selector does not start with a digit. \end_layout \begin_layout Standard The following additional special conventions provide abbreviations for commonly used forms of history substitution: \end_layout \begin_layout Itemize An event specification can be omitted from a history substitution if it is followed by a selector that does not start with a digit. In this case the event is taken to be the event used in the most recent history reference on the same line if there is one, or the preceding event otherwise. For example, the command \family sans echo !?qucs?^ !$ \family default echoes the first and last arguments of the most recent command containing the string \family sans qucs \family default . \end_layout \begin_layout Itemize If the first non-blank character of an input line is \family sans '^' \family default , the \family sans '^' \family default is taken as an abbreviation for \family sans !:s^ \family default . This form provides a convenient way to correct a simple spelling error in the previous line. For example, if by mistake you typed the command \family sans cat /etc/lasswd \family default you could re-execute the command with \family sans lasswd \family default changed to \family sans passwd \family default by typing \family sans ^l^p . \end_layout \begin_layout Itemize You can enclose a history substitution in braces to prevent it from absorbing the following characters. In this case the entire substitution except for the starting \family sans '!' \family default must be within the braces. For example, suppose that you previously issued the command \family sans cp accounts ../money . \family default Then the command \family sans !cps \family default looks for a previous command starting with \family sans cps \family default while the command \family sans !{cp}s \family default turns into a command \family sans cp accounts ../moneys . \end_layout \begin_layout Standard Some characters are handled specially as follows: \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \family sans ~ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Expands to the home directory \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans * \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Matches any string of characters in a filename \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans ? \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Matches any single character in a filename \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans [] \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Matches any of the characters enclosed in a filename \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Used within \family sans [] \family default to specify a range of characters. For example, \family sans [b-k] \family default matches on any character between and including \family sans ‘b’ \family default through to \family sans ‘k’ \family default . \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family sans ^ \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout If the \family sans ^ \family default is included within \family sans [] \family default as the first character, then it negates the following characters matching on anything but those. For example, \family sans [^agm] \family default would match on anything other than \family sans ‘a’ \family default , \family sans ‘g’ \family default and \family sans ‘m’ \family default . \family sans [^a-zA-Z] \family default would match on anything other than an alphabetic character. \end_layout \end_inset \end_inset \end_layout \begin_layout Standard The wildcard characters \family sans * \family default , \family sans ? \family default , \family sans [ \family default , and \family sans ] \family default can be used, but only if you \family sans unset noglob \family default first. This makes them rather useless for typing algebraic expressions, so you should \family sans set noglob \family default again after you are done with wildcard expansion. \end_layout \begin_layout Standard When the environment variable \family sans HOME \family default exists (on Unix, Linux, or CYGWIN), \family typewriter history \family default permanently stores previous command lines in the file \family typewriter $HOME/._ngspice_history \family default . When this variable does not exist (typically on Windows when the readline library is not officially installed), the history file is called \family typewriter .history \family default and put in the current working directory. \end_layout \begin_layout Standard The \family typewriter history \family default command is part of the readline or editline package. The readline program provides a command line editor that is configurable through the file \family typewriter .inputrc \family default . The path to this configuration file is either found in the shell variable \family sans INPUTRC, \family default or it is (on Unix/Linux/CYGWIN) the file \family sans ~/.inputrc \family default in the user's home directory. On Windows systems, the configuration file is \family sans /Users//.inputrc \family default , unless the readline library was officially installed. In that case the filename is taken from the Windows registry and points to a location that the user specified during installation. See \family sans \begin_inset CommandInset href LatexCommand href target "https://web.archive.org/web/20190527085247/https://tiswww.case.edu/php/chet/readline/rltop.html" literal "false" \end_inset \family default for detailed documentation. Some useful commands are below. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout \family typewriter Left/Right arrow \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Move one character to the left or right \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter Home/End \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Move to beginning or end of line \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter Up/Down arrow \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Cycle through the history buffer \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter C-_- \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Undo last editing command \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter C-r \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Incremental search backward \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter TAB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout completion of a file name \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter C-ak \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Erase the command line (kill) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter C-y \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Retrieve last kill (yank) \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \family typewriter C-u \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Erase from cursor to start of line \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection Inventory: Print circuit inventory \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout inventory \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This commands accepts no argument and simply prints the number of instances of a particular device in a loaded netlist. \end_layout \begin_layout Subsection Iplot*: Incremental plot \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout iplot [-d delay] [-w width] [-o] [ node ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Incrementally plot the values of the nodes while ngspice runs. The \family typewriter iplot \family default command can be used with the \family typewriter where \family default command to find trouble spots in a transient simulation. The \begin_inset Quotes eld \end_inset -d \begin_inset Quotes erd \end_inset options sets the delay (in simulation steps) between the start of the simulation and the appearance of the window. It can be used to suppress flicker when new values cause rapid resizing at the start of the simulation. The \begin_inset Quotes eld \end_inset -w \begin_inset Quotes erd \end_inset option sets a fixed width for the window in simulation units (time, frequency etc). When the output does not fit, only the latest output values are shown. \end_layout \begin_layout Standard Node expressions are not supported, except that a fixed offset may be applied to event nodes (usually digital) to separate traces vertically. \end_layout \begin_layout Standard The \begin_inset Quotes eld \end_inset -o \begin_inset Quotes erd \end_inset option gives automatic separation, similar to the \begin_inset Quotes eld \end_inset digitop \begin_inset Quotes erd \end_inset keyword for \begin_inset Quotes eld \end_inset plot \begin_inset Quotes erd \end_inset . Explicit and automatic offsets may be combined: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout iplot -o controlx4 d_d+4.5 d_u \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter @name[param] \family default notation ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Accessing-internal-device" nolink "false" \end_inset ) does not work yet. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Let:-Assign-a" \end_inset Let: Assign a value to a vector \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout let name = expr \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Creates a new vector called name with the value specified by \emph on expr \emph default , an expression as described above. Individual elements of a vector may be modified by appending a subscript to name (ex. name[0]). If there are no arguments, \family typewriter let \family default is the same as \family typewriter display \family default . \end_layout \begin_layout Standard The command \series bold let \series default usually creates a vector in the current plot. Use \series bold setplot \series default \begin_inset CommandInset ref LatexCommand eqref reference "subsec:Setplot:-Switch-the" nolink "false" \end_inset to create a new plot or switch plots. \end_layout \begin_layout Standard There is no straightforward way to initialize a new vector. In general, one might want to have \family typewriter let \family default initialize a slice (i.e. name[4:4,21:23] = [ 1 2 3 ]) of a multi-dimensional matrix of arbitrary type (i.e. real, complex ..), where all values and indexes are arbitrary expressions. This will fail. The procedure is to first allocate a real vector of the appropriate size with either \family typewriter vector \family default (), or \family typewriter unitvec \family default (). The second step is to optionally change the type of the new vector (to complex) with the \family typewriter j \family default () function. The third step \family typewriter reshape \family default s the dimensions, and the final step (re)initializes the contents, like so: \end_layout \begin_layout Quote \family typewriter let a = j(vector(10)) \end_layout \begin_layout Quote \family typewriter reshape a [2][5] \end_layout \begin_layout Quote \family typewriter let a[0][0] = (pi,pi) \end_layout \begin_layout Standard Initialization of real vectors can be done quite efficiently with \family typewriter compose: \end_layout \begin_layout Standard \begin_inset Separator plain \end_inset \end_layout \begin_layout Quote \family typewriter compose a values (pi, pi) (1,1) (2,sqrt(7)) (boltz,e) \end_layout \begin_layout Quote \family typewriter reshape a [2][2] \end_layout \begin_layout Standard \noindent See also \series bold unlet \series default \begin_inset CommandInset ref LatexCommand eqref reference "subsec:Unlet:-Delete-the" nolink "false" \end_inset , \series bold compose \series default \begin_inset CommandInset ref LatexCommand eqref reference "subsec:Compose:-Compose-a" nolink "false" \end_inset . \end_layout \begin_layout Standard \noindent If the vector to be changed does not exist, \series bold let \series default overwrites any existing vector with that name in the \series bold const \series default plot. To prevent that, set the variable sanelet: \family typewriter \begin_inset Quotes eld \end_inset set sanelet \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Linearize*:-Interpolate-to" \end_inset Linearize: Interpolate to a linear scale \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout linearize ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Create a new plot with all of the vectors in the current plot, or only those mentioned as arguments to the command, all data linearized onto an equidistant time scale. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout How to compute the \family typewriter fft \family default from a transient simulation output: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout setplot tran1 \end_layout \begin_layout Plain Layout linearize V(2) \end_layout \begin_layout Plain Layout set specwindow=blackman \end_layout \begin_layout Plain Layout fft V(2) \end_layout \begin_layout Plain Layout plot mag(V(2))tstep \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Alternative linearize options \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout linearize np=1001 V(2) \end_layout \begin_layout Plain Layout linearize np=auto2n V(2) V(3) V(5) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Command \family typewriter linearize \family default is needed for example if you want to do an FFT analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:fft:-fast-Fourier" nolink "false" \end_inset ). \end_layout \begin_layout Standard \family typewriter Linearize \family default will redo the vectors \series bold vec \series default or renew all vectors of the current plot (e.g. tran3) if no arguments are given and store them into a new plot (e.g. tran4). The new vectors are interpolated onto a linear time scale, which is determined by the values of \family typewriter tstep \family default , \family typewriter tstart \family default , and \family typewriter tstop \family default in the currently active transient analysis, if the number of points \family typewriter np \family default is not given. The currently loaded input file must include a transient analysis (a \family typewriter tran \family default command may be run interactively before the last \family typewriter reset \family default , alternately), and the current plot must be from this transient analysis. \end_layout \begin_layout Standard Without \family typewriter np \family default given, the length of the new vector is \family typewriter floor((tstop - tstart) / tstep + 1.5) \family default . Please note that the parameter \family typewriter tstep \family default of your transient analysis (see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.TRAN:-Transient-Analysis" nolink "false" \end_inset ) has to be small enough to get adequate resolution, otherwise the command \family typewriter linearize \family default will do sub-sampling of your signal. If no circuit is loaded and the data have been acquired by the \family typewriter load \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Load:-Load-rawfile" nolink "false" \end_inset ) command, \family typewriter Linearize \family default will take time data from transient analysis scale vector. \end_layout \begin_layout Standard With optional \family typewriter np=xx \family default , \family typewriter xx \family default may be a positive integer number, like \family typewriter np=512 \family default . The linearization then spans from point 0 to point \family typewriter xx \family default , covering \family typewriter xx-1 \family default periods. When \family typewriter np=auto2n \family default is given, the number of points is set automatically to \family typewriter 2^n \family default , with \family typewriter n = (int)round(log2((tstop - tstart) / tstep)) \family default . \end_layout \begin_layout Standard The \family typewriter linearize \family default command may be used to create a linearized cutout of the original vector by defining the vectors \family typewriter lin-tstart \family default , \family typewriter lin-tstop \family default , and \family typewriter lin-tstep \family default before issuing the \family typewriter linearize \family default command. At least \family typewriter lin-tstart \family default or \family typewriter lin-tstop \family default has to be defined. This may be used to plot just a portion of a vector, or to prepare a better fft by skipping the start-up phase of a ring oscillator. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Excerpt from the ring oscillator example soi/ring51_40.sp: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * original time scale by .tran command is from 0 to 16ns \end_layout \begin_layout Plain Layout save out25 out50 \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout plot out25 out50 \end_layout \begin_layout Plain Layout let lin-tstart = 4n $ skip the start-up phase \end_layout \begin_layout Plain Layout let lin-tstop = 14n $ end earlier(just for demonstration) \end_layout \begin_layout Plain Layout let lin-tstep = 5p \end_layout \begin_layout Plain Layout linearize out25 out50 \end_layout \begin_layout Plain Layout plot out25 out50 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter linearize \family default command should explicitly name the vectors of interest. Otherwise warning messages pop up that the vectors lin-tstart etc cannot be linearized. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Listing*:-Print-a" \end_inset Listing: Print a listing of the current circuit \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout listing [logical] [physical] [deck] [expand] [runnable] [param] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If the \series bold logical \series default argument is given, the listing is with all continuation lines collapsed into one line, and if the \series bold physical \series default argument is given the lines are printed out as they were found in the file. The default is logical. A \series bold deck \series default listing is just like the physical listing, except without the line numbers it recreates the input file verbatim (except that it does not preserve case). If the word \series bold expand \series default is present, the circuit is printed with all subcircuits expanded. Argument \series bold runnable \series default will list the circuit netlist expanded, but without additional line numbers, ready to be sourced again and run in ngspice. The option \series bold param \series default allows printing all parameters and their actual values. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout source d: \backslash myngspice \backslash inputs \backslash decade_counter.cir \end_layout \begin_layout Plain Layout listing r > $inputdir/decade_counter_runnable.cir \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard All options (except for \series bold param \series default ) may be invoked by just entering their first letter. The example sources a ngspice netlist, the \family typewriter listing r \family default command will save the expanded netlist (all parameters evaluated, subcircuits flattened, .control sections removed) into a file within the same directory. \end_layout \begin_layout Standard If you are using CIDER ( \begin_inset CommandInset ref LatexCommand ref reference "cha:CIDER-User’s-Manual" nolink "false" \end_inset ), \family typewriter listing r \family default will not create a runnable netlist, because some data lines which have been created internally are missing. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Load:-Load-rawfile" \end_inset Load: Load rawfile data \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout load [filename] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Loads either binary or ascii format rawfile data from the files named. The default file name is rawspice.raw, or the argument to the -r flag if there was one. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Mc_source*:-Reload-the" \end_inset Mc_source: Reload the circuit netlist from an internal storage \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout mc_source \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Upon reading a netlist, after its preprocessing is finished, the modified netlist is stored internally. This command will reload this netlist and create a new circuit inside ngspice. This command is used in conjunction with the alterparam command. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Meas*:-Mesurements-on" \end_inset Meas: Measurements on simulation data \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form (example): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout MEAS {DC|AC|TRAN|SP} result TRIG trig_variable VAL=val \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout TARG targ_variable VAL=val \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Most of the input forms found in \begin_inset CommandInset ref LatexCommand ref reference "subsec:.MEAS" nolink "false" \end_inset may be used here with the command \family typewriter meas \family default instead of \family typewriter .meas(ure) \family default . Using meas inside the \family typewriter .control \family default ... \family typewriter .endc \family default section offers additional features compared to the \family typewriter .meas \family default use. \family typewriter meas \family default will print the results as usual, but in addition will store its measurement result (typically the token \family typewriter \series bold result \family default \series default given in the command line) in a vector. This vector may be used in following command lines of the script as an input value of another command. For details of the command see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.MEAS" nolink "false" \end_inset . The measurement type \family typewriter SP \family default is only available here, because a \family typewriter fft \family default command will prepare the data for \family typewriter SP \family default measurement. Option \family typewriter autostop \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Transient-Analysis-Options" nolink "false" \end_inset ) is not available. \end_layout \begin_layout Standard Unfortunately \family typewriter par( \family default \shape italic 'expression' \series bold \shape default ) \series default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:par('expression'-)" nolink "false" \end_inset , \begin_inset CommandInset ref LatexCommand ref reference "subsec:par('expression'):-Algebraic-expressions" nolink "false" \end_inset ) and \family typewriter param \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:param" nolink "false" \end_inset ) will not work here, i.e. inside the \family typewriter .control \family default section. You may use an expression by the \series bold let \series default command ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Let:-Assign-a" nolink "false" \end_inset ) instead, giving \family typewriter let vec_new = \family default \shape italic expression \shape default . \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Replacement for \family typewriter par \family default ( \shape italic 'expression' \shape default ) in \family typewriter meas \family default inside the \family typewriter .control \family default section \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout let vdiff = v(n1)-v(n0) \end_layout \begin_layout Plain Layout meas tran vtest find vdiff at=0.04e-3 \end_layout \begin_layout Plain Layout *the following will not do here: \end_layout \begin_layout Plain Layout *meas tran vtest find par('v(n1)-v(n0)') at=0.04e-3 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Mdump: Dump the matrix values to a file (or to console) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout mdump \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If \family typewriter \family default is given, the output will be stored in file \family typewriter \family default , otherwise dumped to your console. \end_layout \begin_layout Subsection Mrdump: Dump the matrix right hand side values to a file (or to console) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout mrdump \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If \family typewriter \family default is given, the output will be appended to file \family typewriter \family default , otherwise dumped to your console. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example usage after ngspice has started: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * Dump matrix and RHS values after 10 and 20 steps \end_layout \begin_layout Plain Layout * of a transient simulation \end_layout \begin_layout Plain Layout source rc.cir \end_layout \begin_layout Plain Layout step 10 \end_layout \begin_layout Plain Layout mdump m1.txt \end_layout \begin_layout Plain Layout mrdump mr1.txt \end_layout \begin_layout Plain Layout step 10 \end_layout \begin_layout Plain Layout mdump m2.txt \end_layout \begin_layout Plain Layout mrdump mr2.txt \end_layout \begin_layout Plain Layout * just to continue to the end \end_layout \begin_layout Plain Layout step 10000 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard You may create a loop using the control structures (Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Control-Structures" nolink "false" \end_inset ). \end_layout \begin_layout Subsection Noise: Noise analysis \end_layout \begin_layout Standard See the \family typewriter .NOISE \family default analysis ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.NOISE:-Noise-Analysis" nolink "false" \end_inset ) for details. \end_layout \begin_layout Standard The \family typewriter \series bold noise \family default \series default command will generate two plots (typically named noise1 and noise2) with Noise Spectral Density Curves and Integrated Noise data. To write these data into output file(s), you may use the following command sequence: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Command sequence for writing noise data to file(s): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout tran 1e-6 1e-3 \end_layout \begin_layout Plain Layout write test_tran.raw \end_layout \begin_layout Plain Layout noise V(out) vinp dec 333 1 1e8 16 \end_layout \begin_layout Plain Layout print inoise_total onoise_total \end_layout \begin_layout Plain Layout *first option to get all of the output (two files) \end_layout \begin_layout Plain Layout setplot noise1 \end_layout \begin_layout Plain Layout write test_noise1.raw all \end_layout \begin_layout Plain Layout setplot noise2 \end_layout \begin_layout Plain Layout write test_noise2.raw all \end_layout \begin_layout Plain Layout * second option (all in one raw-file) \end_layout \begin_layout Plain Layout write testall.raw noise1.all noise2.all \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Op: Perform an operating point analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout op \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Do an operating point analysis. See Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.OP:-Operating-Point" nolink "false" \end_inset for more details. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Option*:" \end_inset Option: Set a ngspice option \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout option [option=val] [option=val] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Set any of the simulator variables as listed in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Simulator-Variables" nolink "false" \end_inset . See this chapter also for more information on the available options. The \family typewriter \series bold option \family default \series default command without any argument lists the current options set in the simulator. It shows the current options, while new values are set to be used in the next analysis run. That means that changed options will not be visible immediately, but only after the next analysis run. Multiple options may be set in a single line. \end_layout \begin_layout Standard The following example demonstrates a control section, which may be added to your circuit file to test the influence of variable trtol on the number of iterations and on the simulation time. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Command sequence for testing option trtol: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout set noinit \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout option trtol=1 \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout echo trtol=1 \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout rusage traniter trantime \end_layout \begin_layout Plain Layout reset \end_layout \begin_layout Plain Layout option trtol=3 \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout echo trtol=3 \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout rusage traniter trantime \end_layout \begin_layout Plain Layout reset \end_layout \begin_layout Plain Layout option trtol=5 \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout echo trtol=5 \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout rusage traniter trantime \end_layout \begin_layout Plain Layout reset \end_layout \begin_layout Plain Layout option trtol=7 \end_layout \begin_layout Plain Layout echo \end_layout \begin_layout Plain Layout echo trtol=7 \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout rusage traniter trantime \end_layout \begin_layout Plain Layout plot tran1.v(out25) tran1.v(out50) v(out25) v(out50) \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Plot:-Plot-values" \end_inset Plot*: Plot vectors on the display \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout plot expr1 [vs scale_expr1] [expr2 [vs scale_expr2]] ... \end_layout \begin_layout Plain Layout [ylimit ylo yhi] [xlimit xlo xhi] [xindices xilo xihi] \end_layout \begin_layout Plain Layout [xcompress comp] [xdelta xdel] [ydelta ydel] \end_layout \begin_layout Plain Layout [xlog] [ylog] [loglog] [nogrid] \end_layout \begin_layout Plain Layout [linplot] [combplot] [pointplot] [nointerp] [retraceplot] \end_layout \begin_layout Plain Layout [polar] [smith] [smithgrid] \end_layout \begin_layout Plain Layout [xlabel word] [ylabel word] [title word] \end_layout \begin_layout Plain Layout [samep] [linear] [kicad] [plainplot] [digitop] \end_layout \begin_layout Plain Layout [all] [allv] [alli] [ally] [alle] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Plot the given vectors or expressions on the screen (if you are on a graphics terminal). XSPICE node names may appear in expressions, unless a vector with the same name exists. \end_layout \begin_layout Standard The \family typewriter xlimit \family default and \family typewriter ylimit \family default arguments determine the high and low x- and y-limits of the axes, respectively. The \family typewriter xindices \family default arguments determine what range of points are to be plotted - everything between the \family typewriter xilo \family default 'th point and the \family typewriter xihi \family default 'th point is plotted. The \family typewriter xcompress \family default argument specifies that only one out of every comp points should be plotted. If an \family typewriter xdelta \family default or a \family typewriter ydelta \family default parameter is present, it specifies the spacing between grid lines on the X- and Y-axis. These parameter names may be abbreviated to \family typewriter xl \family default , \family typewriter yl \family default , \family typewriter xind \family default , \family typewriter xcomp \family default , \family typewriter xdel \family default , and \family typewriter ydel \family default respectively. \end_layout \begin_layout Standard The scal_expr argument(s) are expressions to use as the scale on the x-axis instead of the default scale for the plot. If \family typewriter xlog \family default or \family typewriter ylog \family default are present, then the X or Y scale, respectively, are logarithmic ( \family typewriter loglog \family default is the same as specifying both). The \family typewriter xlabel \family default and \family typewriter ylabel \family default arguments cause the specified labels to be used for the X and Y axes, respectively. \end_layout \begin_layout Standard If \family typewriter samep \family default is given, the values of the other parameters from the previous \family typewriter plot \family default , \family typewriter hardcopy \family default , or \family typewriter asciiplot \family default command are used even if they are redefined on the command line. \end_layout \begin_layout Standard The \family typewriter title \family default argument is used in the headline of the plot window and replaces the default text, which is `actual plot: first line of input file'. \end_layout \begin_layout Standard The \family typewriter linear \family default keyword is used to override a default logscale plot (as in the output for an AC analysis). \end_layout \begin_layout Standard The keywords \family typewriter linplot \family default , \family typewriter combplot \family default and \family typewriter pointplot \family default select different plot styles. The keyword \family typewriter nointerp \family default turns off interpolation of the vector data, \family typewriter nogrid \family default suppresses the drawing of gridlines. \family typewriter retraceplot \family default may be required if the scale vector (the x axis) has values which do not grow monothonically (e.g. plotting a circle or the hyseresis loop of a memristor). Without this keyword retracing values (x values moving forth and back) are suppressed. \end_layout \begin_layout Standard Finally, the keyword \family typewriter polar \family default generates a polar plot. To produce a Smith plot, use the keyword \family typewriter smith \family default . Note that the data is transformed, so for Smith plots you will see the data a + jb transformed to \begin_inset Formula \begin{equation} a=(a^{2}+b^{2}-1)/((a+1)^{2}+b^{2}) \end{equation} \begin{equation} b=(2*b)/((a+1)^{2}+b^{2}) \end{equation} \end_inset To produce a polar plot with a Smith grid but without performing the Smith transform, use the keyword \family typewriter smithgrid \family default . \end_layout \begin_layout Standard Keyword \family typewriter retraceplot \family default may be useful if the x-axis values are non-monotonic. Whereas \family typewriter time \family default is always growing monotonically, during plotting \family typewriter ynew vs xnew \family default xnew may partially increase, then decrease again. If this occurs, plotting is suppressed as per default. \family typewriter retraceplot \family default will enable plotting all data. \end_layout \begin_layout Standard If you specify \family typewriter plot all \family default , all vectors (including the scale vector) are plotted versus the scale vector (see commands display ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Display:-List-known" nolink "false" \end_inset ) or \family typewriter setscale \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Setscale:-Set-the" nolink "false" \end_inset ) on viewing the vectors of the current plot). The command \family typewriter plot ally \family default will not plot the scale vector, but all other 'real' y values. The command \family typewriter plot alli \family default selects all current vectors, the command \family typewriter plot allv \family default all voltage vectors. \end_layout \begin_layout Standard If the vector name to be plotted contains \family typewriter - , / \family default or other tokens that may be taken for operators of an expression, and plotting fails, try enclosing the name in double quotes, e.g. \family typewriter plot \begin_inset Quotes eld \end_inset /vout \begin_inset Quotes erd \end_inset \family default . \end_layout \begin_layout Standard Plotting of complex vectors, as may occur after an ac simulation, requires special considerations. Please see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:Ac*:-Perform-an" nolink "false" \end_inset for details. \end_layout \begin_layout Standard Keyword \family typewriter kicad \family default will enable plotting vectors with leading character / (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Compatibility-mode-1-2" nolink "false" \end_inset ) by placing double quotes around the token, keyword \family typewriter plainplot \family default will allow this by suppressing the evaluation of any expression containing such characters. vc1 vs vc2 is not supported with using \family typewriter plainplot \family default . The same effect may be generated by setting the variable \family typewriter plainplot \family default . \end_layout \begin_layout Standard \family typewriter digitop \family default will assemble all digital (event) nodes into a single graph, arranged on top of each other. \end_layout \begin_layout Standard Plot all analog nodes \family typewriter [all] \family default , all voltage nodes only \family typewriter [allv] \family default , all current nodes, \family typewriter [alli] \family default , all nodes except for the scale \family typewriter [ally] \family default , all event nodes \family typewriter [alle] \family default . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Pre_-execute-commands" \end_inset Pre_: execute commands prior to parsing the circuit \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout pre_ \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard All commands in a \family typewriter .control \family default ... \family typewriter .endc \family default section are executed \emph on after \emph default the circuit has been parsed. If you need command execution \emph on before \emph default circuit parsing, you may add these commands to the general \family sans spinit \family default or local \family sans .spiceinit \family default files. Another possibility is adding a leading pre_ to a command within the \family typewriter .control \family default section of an ordinary input file, which forces the command to be executed \emph on before \emph default circuit parsing. Basically \family typewriter \family default may be any command listed in Chapt. \begin_inset CommandInset ref LatexCommand ref reference "sec:Commands" nolink "false" \end_inset , however only a few commands are indeed useful here. Some examples are given below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout pre_unset ngdebug \end_layout \begin_layout Plain Layout pre_set strict_errorhandling \end_layout \begin_layout Plain Layout pre_codemodel mymod.cm \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter pre_ \family default is available only in the \emph on .control mode \emph default (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:Interactive-mode-with" nolink "false" \end_inset ), \emph on not \emph default in \emph on interactive mode \emph default , where the user may determine when a circuit is to be parsed, using the \family typewriter source \family default command ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Source:-Read-a" nolink "false" \end_inset ) . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Pre_ODSI:-load-a" \end_inset Pre_OSDI: load a *.osdi compact device model shared library \end_layout \begin_layout Standard Compact device models, written in Verilog-A HDL and compiled with OpenVAF (see \begin_inset CommandInset ref LatexCommand ref reference "sec:OSDI/OpenVAF" nolink "false" \end_inset ) are loaded dynamically at runtime. Several models may be loaded for a single simulation run. Please add these commands at the beginning of the .control section. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout pre_osdi osdi_libs/bsimbulk107.osdi osdi_libs/psp103.osdi \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Print:-Print-values" \end_inset Print: Print values \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout print [col] [line] expr ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Prints the vector(s) described by the expression(s). XSPICE node names may appear in expressions, unless a vector with the same name exists. \end_layout \begin_layout Standard If the \family typewriter col \family default argument is present, print the vectors named side by side. If \family typewriter line \family default is given, the vectors are printed horizontally. \family typewriter col \family default is the default, unless all the vectors named have a length of one, in which case \family typewriter line \family default is the default. The options \family typewriter width \family default (default 80) and \family typewriter height \family default (default 24) are effective for this command (see \family typewriter asciiplot \family default \begin_inset CommandInset ref LatexCommand ref reference "subsec:Asciiplot:-Plot-values" nolink "false" \end_inset ). The 'more' mode is the standard mode if printing to the screen, that is after a number of lines given by height, and after a page break printing stops with request for answering the prompt by (print next page), 'c' (print rest) or 'q' (quit printing). If everything shall be printed with stopping after each page (only useful in interactive mode, because need manual continuation), use the command \family typewriter set moremode \family default before printing or put it into \family sans .spiceinit \family default \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" nolink "false" \end_inset (or \family sans spinit \family default \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" nolink "false" \end_inset ). If the expression is \family typewriter all \family default , all of the vectors available are printed. Thus \family typewriter print col all > filename \family default prints everything into the file \family typewriter filename \family default in SPICE2 format. The scale vector (time, frequency) is always in the first column unless the variable \family typewriter noprintscale \family default is true. You may use the vectors \family typewriter alli, allv, ally \family default with the \family typewriter print \family default command, but then the scale vector will not be printed. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout print all \end_layout \begin_layout Plain Layout set width=300 \end_layout \begin_layout Plain Layout print v(1) > outfile.out \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Psd: power spectral density of vectors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout psd ave vector1 [vector2] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Calculate the single sided power spectral density of signals (vectors) resulting from a transient analysis. Windowing is available as described in the fft command ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:fft:-fast-Fourier" nolink "false" \end_inset ). The FFT data are squared, summarized, weighted and printed as total noise power up to Nyquist frequency, and as noise voltage or current. \end_layout \begin_layout Standard \family typewriter ave \family default is the number of points used for averaging and smoothing in a postprocess, useful for noisy data. A new plot vector is created that holds the averaged results of the FFT, weighted by the frequency bin. The result can be plotted and has the units V^2/Hz or A^2/Hz, depending on the the input vector. \end_layout \begin_layout Subsection Pyplot: plotting with Python's matplotlib \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout pyplot file plot_args \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard See chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:pyplot" \end_inset for details. \end_layout \begin_layout Subsection Quit: Leave Ngspice \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout quit \end_layout \begin_layout Plain Layout quit [exitcode] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Quit ngspice. Ngspice will ask for an acknowledgment if parameters have not been saved. If \family typewriter unset askquit \family default is specified, ngspice will terminate immediately. \end_layout \begin_layout Standard The optional parameter \family typewriter exitcode \family default is an integer that sets the exit code for ngspice. This is useful to return a success/fail value to the operating system. \end_layout \begin_layout Subsection Rehash: Reset internal hash tables \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout rehash \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Recalculate the internal hash tables used when looking up UNIX commands, and make all UNIX commands in the user's PATH available for command completion. This is useless unless you have set unixcom first (see above). \end_layout \begin_layout Subsection Remcirc: Remove the current circuit \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout remcirc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This command removes the current circuit from the list of circuits sourced into ngspice. To select a specific circuit, use \family typewriter setcirc \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Setcirc*:-Change-the" nolink "false" \end_inset ). To load another circuit, refer to \series bold source \series default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Source:-Read-a" nolink "false" \end_inset ). The new active circuit will be the circuit on top of the list of the remaining circuits. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Remzerovec:-Remove-zero" \end_inset Remzerovec: Remove zero length vectors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout remzerovec \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This command removes vectors of length zero from the current plot. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Reset*:-Reset-an" \end_inset Reset: Reset an analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout reset \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Throw out any intermediate data in the circuit (e.g, after a breakpoint or after one or more analyses have been done), and re-parse the input file. The circuit can then be re-run from it's initial state, overriding the effect of any \family typewriter set \family default or \family typewriter alter \family default commands. These two need to be repeated after the \family typewriter reset \family default command. \end_layout \begin_layout Standard \family typewriter Reset \family default may be required in simulation loops preceding any \family typewriter run \family default (or \family typewriter tran \family default ...) command. \end_layout \begin_layout Standard \family typewriter Reset \family default is required after an \family typewriter alterparam \family default command ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Alterparam*:-Change-value" nolink "false" \end_inset ) for making the parameter change effective. \end_layout \begin_layout Subsection Reshape: Alter the dimensionality or dimensions of a vector \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout reshape vector vector ... \end_layout \begin_layout Plain Layout or \end_layout \begin_layout Plain Layout reshape vector vector ... [ dimension, dimension, ... ] \end_layout \begin_layout Plain Layout or \end_layout \begin_layout Plain Layout reshape vector vector ... [ dimension ][ dimension ] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This command changes the dimensions of a vector or a set of vectors. The final dimension may be left off and it will be filled in automatically. If no dimensions are specified, then the dimensions of the first vector are copied to the other vectors. An error message of the form 'dimensions of x were inconsistent' can be ignored. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * generate vector with all (here 30) elements \end_layout \begin_layout Plain Layout let newvec=vector(30) \end_layout \begin_layout Plain Layout * reshape vector to format 3 x 10 \end_layout \begin_layout Plain Layout reshape newvec [3][10] \end_layout \begin_layout Plain Layout * access elements of the reshaped vector \end_layout \begin_layout Plain Layout print newvec[0][9] \end_layout \begin_layout Plain Layout print newvec[1][5] \end_layout \begin_layout Plain Layout let newt = newvec[2][4] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Command \family typewriter reshape \family default expects positive interger numbers to define the dimensions. Vectors ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Vectors" nolink "false" \end_inset ) or variables ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Variables" nolink "false" \end_inset ) are suitable, when transformed into numbers. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example (using vectors and variables): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout let ntasks=12 ; vector \end_layout \begin_layout Plain Layout set nparams=3 ; variable \end_layout \begin_layout Plain Layout let p=vector(36) ; new vector \end_layout \begin_layout Plain Layout reshape p[$&ntasks][$nparams] ; create format 12 x 3 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Resume*:-Continue-a" \end_inset Resume: Continue a simulation after a stop \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout resume \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Resume a simulation after a stop or interruption (control-C). \end_layout \begin_layout Subsection Run: Run analysis from the input file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout run [rawfile] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Run the simulation as specified in the input file. If there were any of the control lines \family typewriter .ac \family default , \family typewriter .op \family default , \family typewriter .tran \family default , or \family typewriter .dc \family default , they are executed. The output is put in \family typewriter rawfile \family default if it was given, in addition to being available interactively. \end_layout \begin_layout Subsection Rusage: Resource usage \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout rusage [resource ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Print resource usage statistics. If any resources are given, just print the usage of that resource. Most resources require that a circuit be loaded. Currently valid resources are \end_layout \begin_layout Description time Total Analysis Time \end_layout \begin_layout Description cputime The amount of time elapsed since the last \family typewriter rusage cputime \family default call. \end_layout \begin_layout Description totalcputime Total elapsed time used so far. \end_layout \begin_layout Description decklineno Number of lines in deck \end_layout \begin_layout Description netloadtime Nelist loading time \end_layout \begin_layout Description netparsetime Netlist parsing time \end_layout \begin_layout Description faults Number of page faults and context switches (BSD only). \end_layout \begin_layout Description space Data space used (output is depending on the operating system). \end_layout \begin_layout Description temp Operating temperature. \end_layout \begin_layout Description tnom Temperature at which device parameters were measured. \end_layout \begin_layout Description equations Number of circuit equations \end_layout \begin_layout Description totiter Total iterations \end_layout \begin_layout Description accept Accepted time-points \end_layout \begin_layout Description rejected Rejected time-points \end_layout \begin_layout Description loadtime Time spent loading the circuit matrix and RHS. \end_layout \begin_layout Description reordertime Matrix reordering time \end_layout \begin_layout Description lutime L-U decomposition time \end_layout \begin_layout Description solvetime Matrix solve time \end_layout \begin_layout Description trantime Transient analysis time \end_layout \begin_layout Description tranpoints Transient time-points \end_layout \begin_layout Description traniter Transient iterations \end_layout \begin_layout Description trancuriters Transient iterations for the last time point \end_layout \begin_layout Description tranlutime Transient L-U decomposition time \end_layout \begin_layout Description transolvetime Transient matrix solve time \end_layout \begin_layout Description everything All of the above. \end_layout \begin_layout Description all All of the above. \end_layout \begin_layout Standard If rusage is given without any parameter, a sequence of outputs is printed using the following rusage parameters: time, totalcputime, space. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Save*:-Save-a" \end_inset Save: Save a set of outputs \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout save [all | outvec ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Save a set of outputs, discarding the rest (if keyword \family sans all \family default is not given). May be used to dramatically reduce memory (RAM) requirements if only a few useful node voltages or branch currents are saved. \end_layout \begin_layout Standard Node voltages may be saved by giving the nodename or v(nodename). Currents through an independent voltage source are given by i(sourcename) or \emph on sourcename \family typewriter # \family default branch \emph default . Internal device data ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Accessing-internal-device" nolink "false" \end_inset ) are accepted as @dev[param]. The syntax is identical to the \family typewriter .save \family default command ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:.SAVE-Lines" nolink "false" \end_inset ). \end_layout \begin_layout Standard Note: In the \family typewriter .control .... .endc \family default section \family typewriter save \family default \emph on must \emph default occur before the \family typewriter run \family default or \family typewriter tran \family default command to become effective. \end_layout \begin_layout Standard If a node has been mentioned in a \family typewriter save \family default command, it appears in the working plot after a run has completed, or in the rawfile written by the write ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Write:-Write-data" nolink "false" \end_inset ) command. For backward compatibility, if there are no save commands given, all outputs are saved. If you want to \family typewriter trace \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Trace*:-Trace-nodes" nolink "false" \end_inset ) or \family typewriter plot \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Plot:-Plot-values" nolink "false" \end_inset ) a node, you have to save it explicitly, except for \family sans all \family default given or no save command at all. \end_layout \begin_layout Standard When the keyword \family sans all \family default appears in the save command, all node voltages, voltage source currents and inductor currents are saved in addition to any other vectors listed. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Save voltage and current: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout save vd_node vs#branch v(vs_node) i(vs2) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter Save \family default allows storing and later access of internal device parameters. e.g. in a command like \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Save internal parameters: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout save all @mn1[gm] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard saves all standard analysis output data plus \family sans gm \family default of transistor mn1 to internal memory (see also \begin_inset CommandInset ref LatexCommand ref reference "sec:Accessing-internal-device" nolink "false" \end_inset ). \end_layout \begin_layout Standard \family typewriter save \family default may store data from nodes or devices residing inside of a subcircuit: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Save voltage on node 3 (top level), node 8 (from inside subcircuit x2) and current through vmeas (from subcircuit x1): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout save 3 x1.x2.x1.x2.8 v.x1.x1.x1.vmeas#branch \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Save internal parameters within subcircuit: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout save @m.xmos3.mn1[gm] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Use commands \family typewriter listing expand ( \family default \begin_inset CommandInset ref LatexCommand ref reference "subsec:Listing*:-Print-a" nolink "false" \end_inset \family typewriter , \family default before the simulation) or \family typewriter display \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Display:-List-known" nolink "false" \end_inset , after simulation) to obtain a list of all nodes and currents available. Please see Chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Model-and-Device" nolink "false" \end_inset for an explanation of the syntax for internal parameters. \end_layout \begin_layout Standard Entering several save lines in a single \family typewriter .control \family default section will accumulate the nodes and parameters to be saved. If you want to exclude a node, you have to get its number by calling \family typewriter status \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Status*:-Display-breakpoint" nolink "false" \end_inset ) and then calling \family typewriter delete number \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Delete*:-Remove-a" nolink "false" \end_inset ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Don't save anything: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout save none \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Useful if shared ngspice library is used and data are immediately transferred to the caller via the shared ngspice interface. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Don't save subcircuit internal nodes: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout save nosub \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Don't save node vectors that are defined inside of a subcircuit. This may for example save a lot of memory if you are not interested in the internals of a subcircuit device model. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Don't save internal device nodes: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout save nointernals \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Don't save internal device nodes issued by OpenVAF/OSDI Verilog-A models like PSP.. \end_layout \begin_layout Subsection Sens: Run a sensitivity analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout sens output_variable [filter ...] \end_layout \begin_layout Plain Layout sens out_var [filter ...] ac (DEC|OCT|LIN) N Fstart Fstop \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Perform a Sensitivity analysis \family typewriter : output_variable \family default is either a node voltage (ex. \family typewriter v(1) \family default or \family typewriter v(A,out) \family default ) or a current through a voltage source (e.g. \family typewriter i(vtest) \family default ). The first form calculates DC sensitivities, the second form AC sensitivities. The output values are in dimensions of change in output per unit change of input (as opposed to percent change in output or per percent change of input). See \begin_inset CommandInset ref LatexCommand ref reference "subsec:.SENS" plural "false" caps "false" noprefix "false" nolink "false" \end_inset for further details. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Set:-Set-the" \end_inset Set: Set the value of a variable \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout set [word] \end_layout \begin_layout Plain Layout set [word = value] ... \end_layout \begin_layout Plain Layout set [word = ( list of values )] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Set the value of word to \family sans value \family default , if it is present. You can set any word to be any value: numeric, string or list. If no value is given then the value is the Boolean `true'. If you enter a string, you have to enclose it in double quotes. Set saves the lower case version of a \family typewriter word \family default string but the setcs variant of the command preserves case. If a variable is set to a list of values that are enclosed in parentheses (which must be separated from their values by white space), the value of the variable is the list. \end_layout \begin_layout Standard The value of word may be inserted into a command by writing \family typewriter $word, \family default or \family typewriter $word[index] \family default for an individual list element. The index may itself be a substitution: \family typewriter $word[$index] \family default . \end_layout \begin_layout Standard The variables used by ngspice are listed in section \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset . \end_layout \begin_layout Standard If a variable has the same name as a simulator option, setting it will also attempt to set the option. \end_layout \begin_layout Standard \family typewriter Set \family default entered without any parameter will list all variables set, and their values, if applicable. \end_layout \begin_layout Standard Be advised that \family typewriter set \family default sets the lower case variant of \family typewriter word \family default . An exceptions to this rule is the variable \family typewriter sourcepath \family default . \end_layout \begin_layout Standard \family typewriter Set \family default automatically tries to distinguish between values given as numbers, strings or lists. If a string starts with a numerical value, like 2N5401_C and is not enclosed in double quotes, it is interpreted as a real number 2n, i.e. 2e-9. The rest of the string is discarded. \end_layout \begin_layout Standard A variable may be set to a value read from a file by I/O redirection. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout set invar < infile.txt \end_layout \begin_layout Plain Layout echo $invar \end_layout \begin_layout Plain Layout echo $invar[2] \end_layout \begin_layout Plain Layout echo $invar[5] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard With the input text file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout infile.txt: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * testing set input from file \end_layout \begin_layout Plain Layout 3 \end_layout \begin_layout Plain Layout NeXt \end_layout \begin_layout Plain Layout 4 \end_layout \begin_layout Plain Layout 5 and 7 \end_layout \begin_layout Plain Layout \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard you will get the output from \family typewriter echo \end_layout \begin_layout LyX-Code \family typewriter 3 NeXt 4 \family default 5 and 7 \end_layout \begin_layout LyX-Code \family typewriter NeXt \end_layout \begin_layout LyX-Code \family typewriter and \end_layout \begin_layout Standard Lines starting with '*' are comment lines and will be ignored. Lines with multiple tokens are stored as list vectors, lines with a single token as string. \end_layout \begin_layout Standard Another option to set a variable from outside is the I/O redirection by backquotes or backticks (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Using-shell-variables" nolink "false" \end_inset ), if you run ngspice as a console application. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Setcs:-Set-the" \end_inset Setcs: Set the value of a variable, case preserved \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout setcs [word] \end_layout \begin_layout Plain Layout setcs [word = value] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Set the value of word to \family sans value \family default , if it is present. You can set any word to be any value, numeric or string. If no value is given then the value is the Boolean `true'. If you enter a string, you have to enclose it in double quotes. \family typewriter Setcs \family default keeps the case of a \family typewriter word \family default string. \end_layout \begin_layout Standard The value of word may be inserted into a command by writing \family typewriter $word \family default . If a variable is set to a list of values that are enclosed in parentheses (which must be separated from their values by white space), the value of the variable is the list. \end_layout \begin_layout Standard The variables used by ngspice are listed in section \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset . \end_layout \begin_layout Standard \family typewriter Setcs \family default entered without any parameter will list all variables set, and their values, if applicable. \end_layout \begin_layout Standard \family typewriter Setcs \family default automatically tries to distinguish between values given as numbers, strings or lists. If a string starts with a numerical value, like 2N5401_C and is not enclosed in double quotes, it is interpreted as a real number 2n, i.e. 2e-9. The rest of the string is discarded. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Setcirc*:-Change-the" \end_inset Setcirc: Change the current circuit \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout setcirc [circuit number] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The current circuit is the one that is used for the simulation commands below. When a circuit is loaded with the source command (see below, \begin_inset CommandInset ref LatexCommand ref reference "subsec:Source:-Read-a" nolink "false" \end_inset ) it becomes the current circuit. \end_layout \begin_layout Standard \family typewriter \series bold Setcirc \family default \series default followed by 'return' without any parameters lists all circuits loaded. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Setplot:-Switch-the" \end_inset Setplot: Switch the current set of vectors \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout setplot \end_layout \begin_layout Plain Layout setplot [plotname] \end_layout \begin_layout Plain Layout setplot previous \end_layout \begin_layout Plain Layout setplot next \end_layout \begin_layout Plain Layout setplot new \end_layout \begin_layout Plain Layout setplot new script_vars \begin_inset Quotes eld \end_inset Working variables for scripts \begin_inset Quotes erd \end_inset \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Set the current plot to the plot with the given name, or if no name is given, prompt the user with a list of all plots generated so far. (Note that the plots are named as they are loaded, with names like \family typewriter tran1 \family default or \family typewriter op2 \family default . These names are shown by the \family sans setplot \family default and \family sans display \family default commands and are used by \family typewriter diff \family default , \begin_inset CommandInset ref LatexCommand ref reference "subsec:Diff:-Compare-vectors" plural "false" caps "false" noprefix "false" nolink "false" \end_inset .) If the ` \family typewriter New \family default ' item is selected, a new plot is generated that has no vectors defined and up to three extra arguments are accepted: a name for the plot and two descriptive strings. \end_layout \begin_layout Standard Note that here the word \family sans plot \family default refers to a group of vectors that are the result of one ngspice run. When more than one file is loaded in, or more than one plot is present in one file, ngspice keeps them separate and only shows you the vectors in the current plot with the \family sans display \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Display:-List-known" nolink "false" \end_inset ) command. \family sans setplot previous \family default will show the previous plot in the plot list, if available, \family sans setplot next \family default the next plot. If not available, a warning is issued and the current plot stays active. Setplot will also allow selecting the digital event nodes that have been created during the simulation that made the analog plot. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Setscale:-Set-the" \end_inset Setscale: Set the scale vector for the current plot \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout setscale [vector1] [vector2] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The scale vector provides the values for the x-axis in a 2D plot. If no argument is given, the current scale vector is printed. With one argument, defines the default scale vector for the current plot. With two arguments, sets the specific scale vector of vector1 to be vector2. If vector2 is \begin_inset Quotes eld \end_inset none \begin_inset Quotes erd \end_inset the scale vector for vector1 reverts to the plot's default. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Setseed:-Set-the" \end_inset Setseed: Set the seed value for the random number generator \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout setseed [number] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard When this command is given, the seed value for the random number generator is set to \family typewriter number \family default . \family typewriter Number \family default has to be an integer greater than 0. The random numbers retrieved after this command are a sequence of pseudo random numbers with a huge period. Setting the seed value will provide a reproducible sequence of random numbers, i.e. the same seed results in the same sequence. See also the options SEED and SEEDINFO in chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:General-Options" nolink "false" \end_inset and chapt. \begin_inset CommandInset ref LatexCommand ref reference "cha:Statistical-circuit-analysis" nolink "false" \end_inset on statistical circuit analysis.. \end_layout \begin_layout Subsection Settype: Set the type of a vector \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout settype type vector ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Change the type of the named vectors to \family typewriter type \family default . Type names can be found in the following table. \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Unit \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Type \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Unit \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout notype \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout pole \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout time \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout s \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout zero \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout frequency \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Hz \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout s-param \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout - \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout voltage \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout temp-sweep \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Celsius \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout current \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout res-sweep \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ohms \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout voltage-density \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V/ \begin_inset Formula $\sqrt{Hz}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout impedance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Ohms \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout current-density \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A/ \begin_inset Formula $\sqrt{Hz}$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout admittance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout S \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout voltage^2-density \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout V²/ \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout power \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout W \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout current^2-density \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout A²/ \begin_inset Formula $Hz$ \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout phase \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Degree \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout temperature \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Celsius \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout decibel \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout dB \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout charge \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout C \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout capacitance \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout F \end_layout \end_inset \end_inset \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Shell:-Call-the" \end_inset Shell: Call the command interpreter \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout shell [ command ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Call the operating system's command interpreter; execute the specified command or call for interactive use. The status returned by the command is stored in variable \family typewriter shellstatus. \end_layout \begin_layout Subsection Shift: Alter a list variable \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout shift [varname] [number] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If \family typewriter varname \family default is the name of a list variable, it is shifted to the left by \family sans number \family default elements (i.e, the number leftmost elements are removed). The default \family typewriter varname \family default is \family typewriter argv \family default , and the default number is 1. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Show*:-List-device" \end_inset Show: List device state \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout show devices [ : parameters ] , ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter show \family default command prints out tables summarizing the operating condition of selected devices. If \family typewriter devices \family default is missing, a default set of devices are listed, if \family typewriter devices \family default is a single letter, devices of that type are listed. A device's full name may be specified to list only that device. Finally, devices may be selected by model by using the form \family sans #modelname \family default . \end_layout \begin_layout Standard Because the output format is tabular, long strings, including device names, may be truncated. The command \begin_inset Quotes eld \end_inset \family typewriter set altshow \family default \begin_inset Quotes erd \end_inset selects an alternative output format without truncations. \end_layout \begin_layout Standard If no parameters are specified, the values for a standard set of parameters are listed. If the list of parameters contains a ` \family sans + \family default ', the default set of parameters is listed along with any other specified parameters. \end_layout \begin_layout Standard For both devices and parameters, the word \family typewriter all \family default has the obvious meaning. \end_layout \begin_layout Standard Note: there must be spaces around the ` \family typewriter : \family default ' that divides the device list from the parameter list. \end_layout \begin_layout Subsection Showmod: List model parameter values \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout showmod models [ : parameters ] , ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family typewriter showmod \family default command operates like the \family typewriter show \family default command (above) but prints out model parameter values. The applicable forms for \family sans models \family default are a single letter specifying the device type letter (e.g. \family sans m \family default , or \family sans c \family default ), a device name (e.g. \family sans m.xbuf22.m4b \family default ), or \family sans #modelname \family default (e.g. \family sans #p1 \family default ). \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Typical usage (e.g. for BSIM4 model): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout showmod #cmosn #cmosp : lkvth0 vth0 \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Note: there must be spaces around the ` \family typewriter : \family default ' that divides the device list from the parameter list. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Obtain the default model parameters (e.g. for a BJT device): \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout netlist for default bipolar transistor \end_layout \begin_layout Plain Layout Q1 cc bb ee defbip \end_layout \begin_layout Plain Layout .model defbip npn \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout op \end_layout \begin_layout Plain Layout showmod q1 \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family typewriter op \family default is required to set the data (otherwise all reported values are 0). The combination of the default parameters and the parameters given in the .model line (This is what the simulator finally uses.) are obtainable by \family typewriter showmod \family default only after a simulation command (e.g. \family typewriter op \family default ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Snload*:-List-model-1" \end_inset Sndparam: Prepare sound file *.wav output \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout SNDPARAM FILENAME [ SAMPLERATE [FORMAT [V_OFF [V_MULT] [OVERSAMPLING] ] ] ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold sndparam \series default sends output file format data to the simulator. See chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Sound-files-(*.wav)" \end_inset for details. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Snload*:-List-model-2" \end_inset Sndprint: Save a *.wav sound file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout SNDPRINT OV1 [ OV2 ... OV8 ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold sndprint \series default saves nodes voltage into a *.wav file, with format info provided by \series bold sndparam \series default . See chapter \begin_inset CommandInset ref LatexCommand ref reference "sec:Sound-files-(*.wav)" \end_inset for details. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Snload*:-List-model" \end_inset Snload: Load the snapshot file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout snload circuit-file file \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \series bold snload \series default reads the snapshot file generated by \family typewriter snsave \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Snsave*:-List-model" nolink "false" \end_inset ). \family sans circuit-file \family default is the original circuit input file. After reading, the simulation may be continued by \family typewriter resume \family default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Resume*:-Continue-a" nolink "false" \end_inset ). \end_layout \begin_layout Standard An input script for loading circuit and intermediate data, resuming simulation and plotting is shown below: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Typical usage: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * SCRIPT: ADDER - 4 BIT BINARY \end_layout \begin_layout Plain Layout * script to reload circuit and continue the simulation \end_layout \begin_layout Plain Layout * begin with editing the file location \end_layout \begin_layout Plain Layout * to be started with 'ngspice adder_snload.script' \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout * cd to where all files are located \end_layout \begin_layout Plain Layout cd D: \backslash Spice_general \backslash ngspice \backslash examples \backslash snapshot \end_layout \begin_layout Plain Layout * load circuit and snpashot file \end_layout \begin_layout Plain Layout snload adder_mos_circ.cir adder500.snap \end_layout \begin_layout Plain Layout * continue simulation \end_layout \begin_layout Plain Layout resume \end_layout \begin_layout Plain Layout * plot some node voltages \end_layout \begin_layout Plain Layout plot v(10) v(11) v(12) \end_layout \begin_layout Plain Layout .endc \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Due to a bug we currently need the term 'script' in the title line (first line) of the script. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Snsave*:-List-model" \end_inset Snsave: Save a snapshot file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout snsave file \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard If you run a transient simulation and interrupt it by e.g. a \series bold stop \series default breakpoint ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Stop*:-Set-a" nolink "false" \end_inset ), you may resume simulation immediately ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Resume*:-Continue-a" nolink "false" \end_inset ) or store the intermediate status in a snapshot file by \family typewriter snsave \family default for resuming simulation later (using snload ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Snload*:-List-model" nolink "false" \end_inset )), even with a new instance of ngspice. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Typical usage: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout Example input file for snsave \end_layout \begin_layout Plain Layout * load a circuit (including transistor models and .tran command) \end_layout \begin_layout Plain Layout * starts transient simulation until stop point \end_layout \begin_layout Plain Layout * store intermediate data to file \end_layout \begin_layout Plain Layout * begin with editing the file location \end_layout \begin_layout Plain Layout * to be run with 'ngspice adder_mos.cir' \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .include adder_mos_circ.cir \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout *cd to where all files are located \end_layout \begin_layout Plain Layout cd D: \backslash Spice_general \backslash ngspice \backslash examples \backslash snapshot \end_layout \begin_layout Plain Layout unset askquit \end_layout \begin_layout Plain Layout set noinit \end_layout \begin_layout Plain Layout *interrupt condition for the simulation \end_layout \begin_layout Plain Layout stop when time > 500n \end_layout \begin_layout Plain Layout * simulate \end_layout \begin_layout Plain Layout run \end_layout \begin_layout Plain Layout * store snapshot to file \end_layout \begin_layout Plain Layout snsave adder500.snap \end_layout \begin_layout Plain Layout quit \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .END \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard \family sans adder_mos_circ.cir \family default is a circuit input file, including the netlist, \family typewriter .model \family default and \family typewriter .tran \family default statements. \end_layout \begin_layout Standard Unfortunately \family typewriter snsave \family default / \family typewriter snload \family default will not work if you have XSPICE devices (or V/I sources with polynomial statements) in your input deck. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Source:-Read-a" \end_inset Source: Read a ngspice input file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout source infile \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard For ngspice: read the ngspice input file \series bold infile \series default , containing a circuit netlist. Ngspice control commands may be included in the file, and must be enclosed between the lines \family typewriter .control \family default and \family typewriter .endc \family default . These commands are executed immediately after the circuit is loaded, so a control line of \family typewriter ac ... \family default works the same as the corresponding \family typewriter .ac \family default card. The first line in any input file is considered a title line and not parsed but kept as the name of the circuit. Thus, a ngspice command script in \series bold infile \series default must begin with a blank line and then with a \family typewriter .control \family default line. Also, any line starting with the string ` \family typewriter *# \family default ' is considered as a control line ( \family typewriter .control \family default and \family typewriter .endc \family default is placed around this line automatically.). The exception to these rules are the files \family sans spinit \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:Standard-configuration-file" nolink "false" \end_inset ) and \family sans .spiceinit \family default ( \begin_inset CommandInset ref LatexCommand ref reference "sec:User-defined-configuration" nolink "false" \end_inset ). \end_layout \begin_layout Standard For ngutmeg: reads commands from the file \series bold infile \series default . Lines beginning with the character ` \family typewriter * \family default ' are considered comments and are ignored. \end_layout \begin_layout Standard The following search path is executed to find \series bold infile \series default : current directory (OS dependent), \family sans /share/ngspice/scripts \family default , env. variable \family typewriter NGSPICE_INPUT_DIR \family default (if defined), see \begin_inset CommandInset ref LatexCommand ref reference "sec:Environmental-variables" nolink "false" \end_inset . This sequence may be overridden by setting the internal \family typewriter sourcepath \family default variable (see \begin_inset CommandInset ref LatexCommand ref reference "sec:Variables" nolink "false" \end_inset ) before calling \family typewriter source infile \family default . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Spec:-Create-a-1" \end_inset Sp: S-Parameter Analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout sp dec nd fstart fstop \end_layout \begin_layout Plain Layout sp oct no fstart fstop \end_layout \begin_layout Plain Layout sp lin np fstart fstop \end_layout \end_inset \end_layout \begin_layout Plain Layout Examples: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout sp dec 10 1 10K \end_layout \begin_layout Plain Layout sp dec 10 1K 100MEG 1 \end_layout \begin_layout Plain Layout sp lin 100 1 100HZ \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard For details please see chapter \begin_inset CommandInset ref LatexCommand ref reference "subsec:.SP-S-Parameter" nolink "false" \end_inset . the ports required are available as an option to the independent voltage source VSRC (see \begin_inset CommandInset ref LatexCommand ref reference "subsec:RF-Port" nolink "false" \end_inset ). \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Spec:-Create-a" \end_inset Spec: Create a frequency domain plot \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout spec start_freq stop_freq step_freq vector [vector ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Calculates a new complex vector containing the Fourier transform of the input vector (typically the linearized result of a transient analysis). The default behavior is to use a Hanning window, but this can be changed by setting the variables \family typewriter specwindow \family default and \family typewriter specwindoworder \family default appropriately. \end_layout \begin_layout Standard Typical usage: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ngspice 13 -> linearize \end_layout \begin_layout Plain Layout ngspice 14 -> set specwindow = "blackman" \end_layout \begin_layout Plain Layout ngspice 15 -> spec 10 1000000 1000 v(out) \end_layout \begin_layout Plain Layout ngspice 16 -> plot mag(v(out)) \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Possible values for specwindow are \family typewriter none \family default , \family typewriter hanning \family default , \family typewriter cosine \family default , \family typewriter rectangular \family default , \family typewriter hamming \family default , \family typewriter triangle \family default , \family typewriter bartlet \family default , \family typewriter blackman \family default and \family typewriter gaussian \family default . In the case of a Gaussian window \family typewriter specwindoworder \family default is a number specifying its order. For a list of window functions see \begin_inset CommandInset ref LatexCommand ref reference "subsec:fft:-fast-Fourier" nolink "false" \end_inset . \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Status*:-Display-breakpoint" \end_inset Status: Display breakpoint information \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout status \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Display all of the saved nodes and parameters, traces and breakpoints currently in effect. \end_layout \begin_layout Subsection Step: Run a fixed number of time-points \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout step [ number ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Iterate number times, or once, and then stop. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Stop*:-Set-a" \end_inset Stop: Set a breakpoint \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout stop [ after n] [ when value cond value ] ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Set a breakpoint. The argument after \family typewriter \series bold n \family default \series default means stop after iteration number `n', and the argument \family typewriter \series bold when value cond value \family default \series default means stop when the first value is in the given relation with the second value, the possible relations being \end_layout \begin_layout Standard \begin_inset Tabular \begin_inset Text \begin_layout Plain Layout Symbol \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Alias \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout Meaning \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout = \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout eq \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout equal to \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout <> \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ne \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout not equal \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout > \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout gt \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout greater than \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout < \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout lt \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout less than \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout >= \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout ge \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout greater than or equal to \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout <= \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout le \end_layout \end_inset \begin_inset Text \begin_layout Plain Layout less than or equal to \end_layout \end_inset \end_inset \end_layout \begin_layout Standard Symbol or alias may be used alternatively. All stop commands have to be given in the control flow before the \family typewriter run \family default command. The values above may be node names in the running circuit, or real values. If more than one condition is given, e.g. \end_layout \begin_layout Standard \family typewriter stop after 4 when v(1) > 4 when v(2) < 2 \family default , \end_layout \begin_layout Standard the conjunction of the conditions is implied. If the condition is met, the simulation and control flow are interrupted, and ngspice waits for user input. \end_layout \begin_layout Standard In a transient simulation the ` \family typewriter = \family default ' or \family typewriter eq \family default will only work with vector \family typewriter time \family default in commands like \end_layout \begin_layout Standard \family typewriter stop when time = 200n \family default . \end_layout \begin_layout Standard Internally, a breakpoint will be set at the time requested. Multiple breakpoints may be set. If the first stop condition is met, the simulation is interrupted, the commands following \family typewriter run \family default or \family typewriter tran \family default (e.g. \family typewriter alter \family default or \family typewriter altermod \family default ) are executed, then the simulation may continue at the first \family typewriter resume \family default command. The next breakpoint requires another \family typewriter resume \family default to continue automatically. Otherwise the simulation stops and ngspice waits for user input. \end_layout \begin_layout Standard If you try to \family typewriter stop \family default at \end_layout \begin_layout Standard \family typewriter stop when V(1) eq 1 \family default \end_layout \begin_layout Standard (or similar) during a transient simulation, you probably will miss this point, because it is not very likely that at any time step the vector v(1) will have the exact value of 1. Then ngspice simply will not stop. \end_layout \begin_layout Subsection Strcmp: Compare two strings \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout strcmp _flag $string1 "string2" \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The command compares two strings, either given by a variable (string1) or as a string in quotes (`string2'). _flag is set as an output variable to '0', if both strings are equal. A value greater than zero indicates that the first character that does not match has a greater value in str1 than in str2; and a value less than zero indicates the opposite (like the C strcmp function). \end_layout \begin_layout Subsection Strslice: Extract a substring \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout strslice result input offset length \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This command sets variable 'result' to be a portion of string 'input' starting at the given offset and with the requested length. Offset and length should be integers. If offset is negative, it is counted from the end of the input string. \end_layout \begin_layout Subsection Strstr: Find a substring \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout strstr result \begin_inset Quotes eld \end_inset $haystack \begin_inset Quotes erd \end_inset needle \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The command searches string variable 'haystack' for a copy of string 'needle'. If successful, variable 'result' is set to the offset of the first match. Otherwise, the result is -1. As a special case, if 'needle' is the empty string, the result is the length of $haystack. \end_layout \begin_layout Subsection Sysinfo: Print system information \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout sysinfo \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The command prints system information useful for sending bug report to developers. Information consists of \end_layout \begin_layout Itemize Name of the operating system, \end_layout \begin_layout Itemize CPU type, \end_layout \begin_layout Itemize Number of physical processors, \end_layout \begin_layout Itemize Number of logical processors, \end_layout \begin_layout Itemize Total amount of DRAM available, \end_layout \begin_layout Itemize DRAM currently available. \end_layout \begin_layout Standard The example below shows the use of this command. \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ngspice 1 -> sysinfo \end_layout \begin_layout Plain Layout OS: CYGWIN_NT-5.1 1.5.25(0.156/4/2) 2008-06-12 19:34 \end_layout \begin_layout Plain Layout CPU: Intel(R) Pentium(R) 4 CPU 3.40GHz \end_layout \begin_layout Plain Layout Logical processors: 2 \end_layout \begin_layout Plain Layout Total DRAM available = 1535.480469 MB. \end_layout \begin_layout Plain Layout DRAM currently available = 984.683594 MB. \end_layout \begin_layout Plain Layout ngspice 2 -> \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This command has been tested under Windows OS and Linux. It may not be available in your operating system environment. \end_layout \begin_layout Subsection Tf: Run a Transfer Function analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout tf output_node input_source \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard The \family sans tf \family default command performs a transfer function analysis, returning: \end_layout \begin_layout Itemize the transfer function (output/input), \end_layout \begin_layout Itemize output resistance, \end_layout \begin_layout Itemize and input resistance \end_layout \begin_layout Standard between the given output node and the given input source. The analysis assumes a small-signal DC (slowly varying) input. The following example file \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Example input file: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout * Tf test circuit \end_layout \begin_layout Plain Layout vs 1 0 dc 5 \end_layout \begin_layout Plain Layout r1 1 2 100 \end_layout \begin_layout Plain Layout r2 2 3 50 \end_layout \begin_layout Plain Layout r3 3 0 150 \end_layout \begin_layout Plain Layout r4 2 0 200 \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .control \end_layout \begin_layout Plain Layout tf v(3,5) vs \end_layout \begin_layout Plain Layout print all \end_layout \begin_layout Plain Layout .endc \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout .end \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard will yield the following output: \end_layout \begin_layout Standard \family typewriter transfer_function = 3.750000e-001 \end_layout \begin_layout Standard \family typewriter output_impedance_at_v(3,5) = 6.662500e+001 \end_layout \begin_layout Standard \family typewriter vs#input_impedance = 2.000000e+002 \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Trace*:-Trace-nodes" \end_inset Trace: Trace nodes \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout trace [ node ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard For every step of an analysis, the value of the node is printed. Several traces may be active at once. Tracing is not applicable for all analyses. To remove a trace, use the \series bold delete \series default ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Delete*:-Remove-a" nolink "false" \end_inset ) command. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Tran*:-Perform-a" \end_inset Tran: Perform a transient analysis \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout tran Tstep Tstop [ Tstart [ Tmax ] ] [ UIC ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Perform a transient analysis. See Chapt. \begin_inset CommandInset ref LatexCommand ref reference "subsec:.TRAN:-Transient-Analysis" nolink "false" \end_inset of this manual for more details. \end_layout \begin_layout Standard An interactive transient analysis may be interrupted by issuing a \series bold ctrl-c \series default (control-C) command. The analysis then can be resumed by the \series bold resume \series default command ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Resume*:-Continue-a" nolink "false" \end_inset ). Several options may be set to control the simulation ( \begin_inset CommandInset ref LatexCommand ref reference "subsec:Transient-Analysis-Options" nolink "false" \end_inset ). \end_layout \begin_layout Subsection Transpose: Swap the elements in a multi-dimensional data set \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout transpose vector vector ... \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard This command transposes a multidimensional vector. No analysis in ngspice produces multidimensional vectors, although the DC transfer curve may be run with two varying sources. You must use the \family sans reshape \family default command to reform the one-dimensional vectors into two dimensional vectors. In addition, the default scale is incorrect for plotting. You must plot versus the vector corresponding to the second source, but you must also refer only to the first segment of this second source vector. For example (circuit to produce the transfer characteristic of a MOS transistor): \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout How to produce the transfer characteristic of a MOS transistor: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ngspice > dc vgg 0 5 1 vdd 0 5 1 \end_layout \begin_layout Plain Layout ngspice > plot i(vdd) \end_layout \begin_layout Plain Layout ngspice > reshape all [6,6] \end_layout \begin_layout Plain Layout ngspice > transpose i(vdd) v(drain) \end_layout \begin_layout Plain Layout ngspice > plot i(vdd) vs v(drain)[0] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Subsection Unalias: Retract an alias \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout unalias [word ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Removes any aliases present for the words. \end_layout \begin_layout Subsection Undefine: Retract a definition \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout undefine [function ...] \end_layout \begin_layout Plain Layout undefine * \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Definitions for the named user-defined functions are deleted. If * is given, all user-defined functions are deleted. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Unlet:-Delete-the" \end_inset Unlet: Delete the specified vector(s) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout unlet [vector ...] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Delete the specified vector(s). See also \series bold let \series default \begin_inset CommandInset ref LatexCommand eqref reference "subsec:Let:-Assign-a" nolink "false" \end_inset . \end_layout \begin_layout Subsection Unset: Clear a variable \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout unset [word ...] \end_layout \begin_layout Plain Layout unset * \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Clear the value of the specified variable(s) (word). If * is specified, all variables are cleared. \end_layout \begin_layout Subsection Version: Print the version of ngspice \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout version [-s | -f | ] \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard Print out the version of ngspice that is running, if invoked without argument or with \series bold -s \series default or \series bold -f \series default . If the argument is a \series bold \series default (any string different from \series bold -s \series default or \series bold -f \series default is considered a \series bold \series default ), the command checks to make sure that the arguments match the current version of ngspice. (This is mainly used as a \family typewriter Command: \family default line in rawfiles.) \end_layout \begin_layout Standard Options description: \end_layout \begin_layout Itemize No option: The output of the command is the message you can see when running ngspice from the command line, no more no less. \end_layout \begin_layout Itemize \series bold -s \series default (hort): A shorter version of the message you see when calling ngspice from the command line. \end_layout \begin_layout Itemize \series bold -f \series default (ull): You may want to use this option if you want to know what extensions are included into the simulator and what compilation switches are active. A list of compilation options and included extensions is appended to the normal (not short) message. May be useful when sending bug reports. \end_layout \begin_layout Standard The following example shows what the command returns in some situations: \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout Use of the version command: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout ngspice 10 -> version \end_layout \begin_layout Plain Layout ****** \end_layout \begin_layout Plain Layout ** ngspice-39 : Circuit level simulation program \end_layout \begin_layout Plain Layout ** The U. C. Berkeley CAD Group \end_layout \begin_layout Plain Layout ** Copyright 1985-1994, Regents of the University \end_layout \begin_layout Plain Layout of California. \end_layout \begin_layout Plain Layout ** Copyright 2001-2023, The ngspice team. \end_layout \begin_layout Plain Layout ** Please get your ngspice manual from \end_layout \begin_layout Plain Layout https://ngspice.sourceforge.io/docs.html \end_layout \begin_layout Plain Layout ** Please file your bug-reports at \end_layout \begin_layout Plain Layout https://ngspice.sourceforge.io/bugrep.html \end_layout \begin_layout Plain Layout ** Creation Date: Mar 7 2023 17:25:48 \end_layout \begin_layout Plain Layout ****** \end_layout \begin_layout Plain Layout ngspice 2 -> \end_layout \begin_layout Plain Layout ngspice 11 -> version 14 \end_layout \begin_layout Plain Layout Note: rawfile is version 14 (current version is 39) \end_layout \begin_layout Plain Layout ngspice 12 -> version 39 \end_layout \begin_layout Plain Layout ngspice 13 -> \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Quote Note for developers: The option listing returned when \family sans version \family default is called with the \family typewriter \series bold -f \family default \series default flag is built at compile time using \family typewriter #ifdef \family default blocks. When new compile switches are added, if you want them to appear on the list, you have to modify the code in \family typewriter misccoms.c \family default . \end_layout \begin_layout Subsection Where: Identify troublesome node or device \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout where \end_layout \end_inset \end_layout \end_inset \end_layout \begin_layout Standard When performing a transient or operating point analysis, the name of the last node or device to cause non-convergence is saved. The \family typewriter where \family default command prints out this information so that you can examine the circuit and either correct the problem or generate a bug report. You may do this either in the middle of a run or after the simulator has given up on the analysis. For transient simulation, the \family sans iplot \family default command can be used to monitor the progress of the analysis. When the analysis slows down severely or hangs, interrupt the simulator (with control-C) and issue the \family typewriter where \family default command. Note that only one node or device is printed; there may be problems with more than one node. \end_layout \begin_layout Subsection \begin_inset CommandInset label LatexCommand label name "subsec:Wrdata:-Write-data" \end_inset Wrdata: Write data to a file (simple table) \end_layout \begin_layout Standard \begin_inset Box Frameless position "t" hor_pos "c" has_inner_box 1 inner_pos "t" use_parbox 0 use_makebox 0 width "100col%" special "none" height "1in" height_special "totalheight" thickness "0.4pt" separation "3pt" shadowsize "4pt" framecolor "black" backgroundcolor "none" status open \begin_layout Plain Layout General Form: \end_layout \begin_layout LyX-Code \begin_inset listings inline false status open \begin_layout Plain Layout \end_layout \begin_layout Plain Layout \end_layout \begin_layout Plain Layout