pax_global_header00006660000000000000000000000064144647771260014534gustar00rootroot0000000000000052 comment=5268ea80e32a6f09f911114e12a20a8176055163 ROCT-Thunk-Interface-rocm-5.7.0/000077500000000000000000000000001446477712600162375ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/.gitignore000066400000000000000000000002061446477712600202250ustar00rootroot00000000000000.* # # git files that we don't want to ignore even it they are dot-files # !.gitignore !.mailmap patches-* build/ outgoing/ Makefile ROCT-Thunk-Interface-rocm-5.7.0/CMakeLists.txt000066400000000000000000000461771446477712600210160ustar00rootroot00000000000000################################################################################ ## ## Copyright (c) 2016 Advanced Micro Devices, Inc. All rights reserved. ## ## MIT LICENSE: ## Permission is hereby granted, free of charge, to any person obtaining a copy of ## this software and associated documentation files (the "Software"), to deal in ## the Software without restriction, including without limitation the rights to ## use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ## of the Software, and to permit persons to whom the Software is furnished to do ## so, subject to the following conditions: ## ## The above copyright notice and this permission notice shall be included in all ## copies or substantial portions of the Software. ## ## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ## SOFTWARE. ## ################################################################################ cmake_minimum_required ( VERSION 3.6.3 ) set ( HSAKMT "hsakmt" ) set ( HSAKMT_PACKAGE "hsakmt-roct" ) set ( HSAKMT_COMPONENT "lib${HSAKMT}" ) set ( HSAKMT_TARGET "${HSAKMT}" ) project ( ${HSAKMT_TARGET} VERSION 1.9.0) # Build thunk as static by default if ( NOT DEFINED BUILD_SHARED_LIBS ) set ( BUILD_SHARED_LIBS "off" ) endif() set ( BUILD_SHARED_LIBS ${BUILD_SHARED_LIBS} CACHE BOOL "Build shared library (.so) or not.") # Optionally, build HSAKMT with ccache. set(ROCM_CCACHE_BUILD OFF CACHE BOOL "Set to ON for a ccache enabled build") if (ROCM_CCACHE_BUILD) find_program(CCACHE_PROGRAM ccache) if (CCACHE_PROGRAM) set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE ${CCACHE_PROGRAM}) else() message(WARNING "Unable to find ccache. Falling back to real compiler") endif() # if (CCACHE_PROGRAM) endif() # if (ROCM_CCACHE_BUILD) list( APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake_modules" ) ## Include common cmake modules include ( utils ) include ( GNUInstallDirs ) ## Setup the package version. get_version ( "1.0.0" ) set ( BUILD_VERSION_MAJOR ${VERSION_MAJOR} ) set ( BUILD_VERSION_MINOR ${VERSION_MINOR} ) set ( BUILD_VERSION_PATCH ${VERSION_PATCH} ) set ( LIB_VERSION_MAJOR 1) set ( LIB_VERSION_MINOR 0) if (${ROCM_PATCH_VERSION}) set ( LIB_VERSION_PATCH ${ROCM_PATCH_VERSION} ) else () set ( LIB_VERSION_PATCH 6) endif () set ( LIB_VERSION_STRING "${LIB_VERSION_MAJOR}.${LIB_VERSION_MINOR}.${LIB_VERSION_PATCH}" ) if ( DEFINED VERSION_BUILD AND NOT ${VERSION_BUILD} STREQUAL "" ) message ( "VERSION BUILD DEFINED ${VERSION_BUILD}" ) set ( BUILD_VERSION_PATCH "${BUILD_VERSION_PATCH}-${VERSION_BUILD}" ) endif () set ( BUILD_VERSION_STRING "${BUILD_VERSION_MAJOR}.${BUILD_VERSION_MINOR}.${BUILD_VERSION_PATCH}" ) ## Compiler flags set (HSAKMT_C_FLAGS -fPIC -W -Wall -Wextra -Wno-unused-parameter -Wformat-security -Wswitch-default -Wundef -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wredundant-decls -Wunreachable-code -std=gnu99 -fvisibility=hidden) if ( CMAKE_COMPILER_IS_GNUCC ) set ( HSAKMT_C_FLAGS "${HSAKMT_C_FLAGS}" -Wlogical-op) endif () if ( ${HSAKMT_WERROR} ) set ( HSAKMT_C_FLAGS "${HSAKMT_C_FLAGS}" -Werror ) endif () if ( "${CMAKE_BUILD_TYPE}" STREQUAL Release ) set ( HSAKMT_C_FLAGS "${HSAKMT_C_FLAGS}" -O2 ) else () set ( HSAKMT_C_FLAGS "${HSAKMT_C_FLAGS}" -g ) endif () set ( HSAKMT_LINKER_SCRIPT "${CMAKE_CURRENT_SOURCE_DIR}/src/libhsakmt.ver" ) ## Linker Flags ## Add --enable-new-dtags to generate DT_RUNPATH set (HSAKMT_LINK_FLAGS "${HSAKMT_LINK_FLAGS} -Wl,--enable-new-dtags -Wl,--version-script=${HSAKMT_LINKER_SCRIPT} -Wl,-soname=${HSAKMT_COMPONENT}.so.${LIB_VERSION_MAJOR} -Wl,-z,nodelete") ## Address Sanitize Flag if ( ${ADDRESS_SANITIZER} ) set ( HSAKMT_C_FLAGS "${HSAKMT_C_FLAGS}" -fsanitize=address ) set ( HSAKMT_LINK_FLAGS "${HSAKMT_LINK_FLAGS} -fsanitize=address" ) if ( BUILD_SHARED_LIBS ) set ( HSAKMT_LINK_FLAGS "${HSAKMT_LINK_FLAGS} -shared-libsan" ) else () set ( HSAKMT_LINK_FLAGS "${HSAKMT_LINK_FLAGS} -static-libsan" ) endif () else () if ( CMAKE_COMPILER_IS_GNUCC ) set ( HSAKMT_LINK_FLAGS "${HSAKMT_LINK_FLAGS} -Wl,-no-undefined" ) else () set ( HSAKMT_LINK_FLAGS "${HSAKMT_LINK_FLAGS} -Wl,-undefined,error" ) endif () endif () ## Source files set ( HSAKMT_SRC "src/debug.c" "src/events.c" "src/fmm.c" "src/globals.c" "src/libhsakmt.c" "src/memory.c" "src/openclose.c" "src/perfctr.c" "src/pmc_table.c" "src/queues.c" "src/time.c" "src/topology.c" "src/rbtree.c" "src/spm.c" "src/version.c" "src/svm.c") ## Declare the library target name add_library ( ${HSAKMT_TARGET} "") ## Add sources target_sources ( ${HSAKMT_TARGET} PRIVATE ${HSAKMT_SRC} ) ## Add headers. The public headers need to point at their location in both build and install ## directory layouts. This declaration allows publishing library use data to downstream clients. target_include_directories( ${HSAKMT_TARGET} PUBLIC $ $ PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src ) set_property(TARGET ${HSAKMT_TARGET} PROPERTY LINK_FLAGS ${HSAKMT_LINK_FLAGS}) ## Set the VERSION and SOVERSION values set_property ( TARGET ${HSAKMT_TARGET} PROPERTY VERSION "${LIB_VERSION_STRING}" ) set_property ( TARGET ${HSAKMT_TARGET} PROPERTY SOVERSION "${LIB_VERSION_MAJOR}" ) find_package(PkgConfig) # get OS-info for OS-specific build dependencies get_os_info() find_package(PkgConfig) # Check for libraries required for building find_library(LIBC NAMES c REQUIRED) find_library(NUMA NAMES numa REQUIRED) message(STATUS "LIBC:" ${LIBC}) message(STATUS "NUMA:" ${NUMA}) ## If environment variable DRM_DIR is set, the script ## will pick up the corresponding libraries from that path. list (PREPEND CMAKE_PREFIX_PATH "${DRM_DIR}") # The module name passed to pkg_check_modules() is determined by the # name of file *.pc pkg_check_modules(DRM REQUIRED libdrm) pkg_check_modules(DRM_AMDGPU REQUIRED libdrm_amdgpu) include_directories(${DRM_AMDGPU_INCLUDE_DIRS}) include_directories(${DRM_INCLUDE_DIRS}) target_link_libraries ( ${HSAKMT_TARGET} PRIVATE ${DRM_LDFLAGS} ${DRM_AMDGPU_LDFLAGS} pthread rt c numa ) target_compile_options(${HSAKMT_TARGET} PRIVATE ${DRM_CFLAGS} ${HSAKMT_C_FLAGS}) ## Define default paths and packages. if( CMAKE_INSTALL_PREFIX_INITIALIZED_TO_DEFAULT ) set ( CMAKE_INSTALL_PREFIX "/opt/rocm" ) endif() set ( CMAKE_INSTALL_PREFIX ${CMAKE_INSTALL_PREFIX} CACHE STRING "Default installation directory." FORCE ) set ( CPACK_PACKAGING_INSTALL_PREFIX "${CMAKE_INSTALL_PREFIX}" CACHE STRING "Default packaging prefix." ) set ( CPACK_GENERATOR "DEB;RPM" CACHE STRING "Default packaging generators." ) ## set components if ( ENABLE_ASAN_PACKAGING ) # ASAN Package requires only asan component with libraries and license file set ( CPACK_COMPONENTS_ALL asan ) else() set ( CPACK_COMPONENTS_ALL devel ) endif() # Installs binaries and exports the library usage data to ${HSAKMT_TARGET}Targets install ( TARGETS ${HSAKMT_TARGET} EXPORT ${HSAKMT_TARGET}Targets ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT asan LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT asan ) install ( TARGETS ${HSAKMT_TARGET} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT devel LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT devel ) #install ( FILES ${CMAKE_CURRENT_SOURCE_DIR}/LICENSE.md DESTINATION ${CMAKE_INSTALL_DOCDIR} COMPONENT devel ) # Install public headers install ( DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/include/ DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${HSAKMT_TARGET} COMPONENT devel PATTERN "linux" EXCLUDE ) # Option to build header path migration helpers. if( NOT ENABLE_ASAN_PACKAGING ) option(INCLUDE_PATH_COMPATIBILITY "Generate backward compatible headers and include paths. Use of these headers will warn when included." ON) endif() if(INCLUDE_PATH_COMPATIBILITY) # To enable/disable #error in wrapper header files if(NOT DEFINED ROCM_HEADER_WRAPPER_WERROR) if(DEFINED ENV{ROCM_HEADER_WRAPPER_WERROR}) set(ROCM_HEADER_WRAPPER_WERROR "$ENV{ROCM_HEADER_WRAPPER_WERROR}" CACHE STRING "Header wrapper warnings as errors.") else() set(ROCM_HEADER_WRAPPER_WERROR "OFF" CACHE STRING "Header wrapper warnings as errors.") endif() endif() if(ROCM_HEADER_WRAPPER_WERROR) set(deprecated_error 1) else() set(deprecated_error 0) endif() include(hsakmt-backward-compat.cmake) endif() # Record our usage data for clients find_package calls. install ( EXPORT ${HSAKMT_TARGET}Targets FILE ${HSAKMT_TARGET}Targets.cmake NAMESPACE ${HSAKMT_TARGET}:: DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/${HSAKMT_TARGET} COMPONENT devel) # Adds the target alias hsakmt::hsakmt to the local cmake cache. # This isn't necessary today. It's harmless preparation for some # hypothetical future in which the we might be included by add_subdirectory() # in some other project's cmake file. It allows uniform use of find_package # and target_link_library() without regard to whether a target is external or # a subdirectory of the current build. add_library( ${HSAKMT_TARGET}::${HSAKMT_TARGET} ALIAS ${HSAKMT_TARGET} ) # Create cmake configuration files include(CMakePackageConfigHelpers) configure_package_config_file(${HSAKMT_TARGET}-config.cmake.in ${HSAKMT_TARGET}-config.cmake INSTALL_DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/${HSAKMT_TARGET} ) write_basic_package_version_file(${HSAKMT_TARGET}-config-version.cmake VERSION ${BUILD_VERSION_STRING} COMPATIBILITY AnyNewerVersion) install(FILES ${CMAKE_CURRENT_BINARY_DIR}/${HSAKMT_TARGET}-config.cmake ${CMAKE_CURRENT_BINARY_DIR}/${HSAKMT_TARGET}-config-version.cmake DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/${HSAKMT_TARGET} COMPONENT devel) # Optionally record the package's find module in the user's package cache. if ( NOT DEFINED EXPORT_TO_USER_PACKAGE_REGISTRY ) set ( EXPORT_TO_USER_PACKAGE_REGISTRY "off" ) endif() set ( EXPORT_TO_USER_PACKAGE_REGISTRY ${EXPORT_TO_USER_PACKAGE_REGISTRY} CACHE BOOL "Add cmake package config location to the user's cmake package registry.") if(${EXPORT_TO_USER_PACKAGE_REGISTRY}) # Enable writing to the registry set(CMAKE_EXPORT_PACKAGE_REGISTRY ON) # Generate a target file for the build export(TARGETS ${HSAKMT_TARGET} NAMESPACE ${HSAKMT_TARGET}:: FILE ${HSAKMT_TARGET}Targets.cmake) # Record the package in the user's cache. export(PACKAGE ${HSAKMT_TARGET}) endif() # CPACK_PACKAGING_INSTALL_PREFIX is needed in libhsakmt.pc.in # TODO: Add support for relocatable packages. configure_file ( libhsakmt.pc.in libhsakmt.pc @ONLY ) install ( FILES ${CMAKE_CURRENT_BINARY_DIR}/libhsakmt.pc DESTINATION ${CMAKE_INSTALL_DATADIR}/pkgconfig COMPONENT devel) ########################### # Packaging directives ########################### # Use component packaging set(CPACK_COMPONENTS_GROUPING IGNORE) set(CPACK_DEB_COMPONENT_INSTALL ON) set(CPACK_RPM_COMPONENT_INSTALL ON) set(CPACK_PACKAGE_VENDOR "Advanced Micro Devices, Inc.") set(CPACK_PACKAGE_VERSION_MAJOR ${VERSION_MAJOR}) set(CPACK_PACKAGE_VERSION_MINOR ${VERSION_MINOR}) set(CPACK_PACKAGE_VERSION_PATCH ${VERSION_PATCH}) set(CPACK_PACKAGE_CONTACT "AMD GFX mailing list ") set(CPACK_RESOURCE_FILE_LICENSE "${CMAKE_CURRENT_SOURCE_DIR}/LICENSE.md") set(CPACK_COMPONENT_DESCRIPTION "HSAKMT development package.\n This package includes the user-mode API interfaces\nused to interact with the ROCk driver.\n This package contains the headers, pkgonfig and\n cmake files for the ROCT package.") set ( ENABLE_LDCONFIG ON CACHE BOOL "Set library links and caches using ldconfig.") # Install License file install ( FILES ${CPACK_RESOURCE_FILE_LICENSE} DESTINATION ${CMAKE_INSTALL_DOCDIR} COMPONENT devel) if ( ENABLE_ASAN_PACKAGING ) install ( FILES ${CPACK_RESOURCE_FILE_LICENSE} DESTINATION ${CMAKE_INSTALL_DOCDIR}-asan COMPONENT asan) endif() # Make proper version for appending # Default Value is 99999, setting it first set(ROCM_VERSION_FOR_PACKAGE "99999") if(DEFINED ENV{ROCM_LIBPATCH_VERSION}) set(ROCM_VERSION_FOR_PACKAGE $ENV{ROCM_LIBPATCH_VERSION}) endif() # Prepare final version for the CPACK use set(PACKAGE_VERSION_STR "${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}.${ROCM_VERSION_FOR_PACKAGE}") set(CPACK_PACKAGE_VERSION "${PACKAGE_VERSION_STR}") # Debian package specific variables set(CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface") set(CPACK_DEBIAN_PACKAGE_NAME "hsakmt-roct-dev") if (DEFINED ENV{CPACK_DEBIAN_PACKAGE_RELEASE}) set(CPACK_DEBIAN_PACKAGE_RELEASE $ENV{CPACK_DEBIAN_PACKAGE_RELEASE}) else() set(CPACK_DEBIAN_PACKAGE_RELEASE "local") endif() ## Process the Debian install/remove scripts to update the CPACK variables configure_file ( ${CMAKE_CURRENT_SOURCE_DIR}/DEBIAN/postinst.in DEBIAN/postinst @ONLY ) configure_file ( ${CMAKE_CURRENT_SOURCE_DIR}/DEBIAN/prerm.in DEBIAN/prerm @ONLY ) set(CPACK_DEBIAN_PACKAGE_CONTROL_EXTRA "DEBIAN/postinst;DEBIAN/prerm") # Needed since some packages still say they need hsakmt-roct set(CPACK_DEBIAN_PACKAGE_REPLACES "hsakmt-roct") set(CPACK_DEBIAN_PACKAGE_PROVIDES "hsakmt-roct") set(CPACK_RPM_PACKAGE_OBSOLETES "hsakmt-roct") set(CPACK_RPM_PACKAGE_PROVIDES "hsakmt-roct") # Debian devel component specific flags set(CPACK_DEBIAN_DEVEL_PACKAGE_NAME "hsakmt-roct-dev") set(CPACK_DEBIAN_DEVEL_PACKAGE_REPLACES "hsakmt-roct") set(CPACK_DEBIAN_DEVEL_PACKAGE_PROVIDES "hsakmt-roct") set(CPACK_RPM_DEVEL_PACKAGE_PROVIDES "hsakmt-roct") # Debian package specific variable for ASAN set(CPACK_DEBIAN_ASAN_PACKAGE_NAME "hsakmt-roct-asan" ) ## Process the Rpm install/remove scripts to update the CPACK variables configure_file ( "${CMAKE_CURRENT_SOURCE_DIR}/RPM/post.in" RPM/post @ONLY ) configure_file ( "${CMAKE_CURRENT_SOURCE_DIR}/RPM/postun.in" RPM/postun @ONLY ) ## RPM package specific variables set ( CPACK_RPM_PRE_INSTALL_SCRIPT_FILE "${CMAKE_CURRENT_BINARY_DIR}/RPM/post" ) set ( CPACK_RPM_POST_UNINSTALL_SCRIPT_FILE "${CMAKE_CURRENT_BINARY_DIR}/RPM/postun" ) if(DEFINED CPACK_PACKAGING_INSTALL_PREFIX) set(CPACK_RPM_EXCLUDE_FROM_AUTO_FILELIST_ADDITION "${CPACK_PACKAGING_INSTALL_PREFIX} ${CPACK_PACKAGING_INSTALL_PREFIX}/${CMAKE_INSTALL_BINDIR}") endif() set(CPACK_RPM_PACKAGE_NAME "hsakmt-roct-devel") set(CPACK_RPM_PACKAGE_LICENSE "MIT") # RPM package specific variable for ASAN set(CPACK_RPM_ASAN_PACKAGE_NAME "hsakmt-roct-asan" ) # RPM package devel specific variable set(CPACK_RPM_DEVEL_PACKAGE_NAME "hsakmt-roct-devel") # Since we changed the package name to match RPM specs, take care of older builds that had -dev installed # Also cover the fact that this now replaces the old binary package hsakmt-roct set(CPACK_RPM_PACKAGE_OBSOLETES "hsakmt-roct-dev hsakmt-roct") set(CPACK_RPM_DEVEL_PACKAGE_OBSOLETES "hsakmt-roct-dev hsakmt-roct") if(DEFINED ENV{CPACK_RPM_PACKAGE_RELEASE}) set(CPACK_RPM_PACKAGE_RELEASE $ENV{CPACK_RPM_PACKAGE_RELEASE}) else() set(CPACK_RPM_PACKAGE_RELEASE "local") endif() ## Specify a RPM SPEC template # This template was generated by using "CPACK_RPM_GENERATE_USER_BINARY_SPECFILE_TEMPLATE" # but I've modified it to support CPACK_RPM_PACKAGE_RECOMMENDS for EL8+ and SLE set ( CPACK_RPM_USER_BINARY_SPECFILE "${CMAKE_CURRENT_SOURCE_DIR}/RPM/${CPACK_RPM_PACKAGE_NAME}.spec.in" ) # 'dist' breaks manual builds on debian systems due to empty Provides execute_process( COMMAND rpm --eval %{?dist} RESULT_VARIABLE PROC_RESULT OUTPUT_VARIABLE EVAL_RESULT OUTPUT_STRIP_TRAILING_WHITESPACE ) message("RESULT_VARIABLE ${PROC_RESULT} OUTPUT_VARIABLE: ${EVAL_RESULT}") if ( PROC_RESULT EQUAL "0" AND NOT EVAL_RESULT STREQUAL "" ) string ( APPEND CPACK_RPM_PACKAGE_RELEASE "%{?dist}" ) endif() # Setting devel package dependendent version set(CPACK_DEBIAN_PACKAGE_DEPENDS "libdrm-amdgpu-dev | libdrm-dev, rocm-core") set(CPACK_DEBIAN_PACKAGE_RECOMMENDS "libdrm-amdgpu-dev") set(CPACK_DEBIAN_PACKAGE_REPLACES "hsakmt-roct") set(CPACK_DEBIAN_DEVEL_PACKAGE_DEPENDS "libdrm-amdgpu-dev | libdrm-dev, rocm-core") set(CPACK_DEBIAN_DEVEL_PACKAGE_RECOMMENDS "libdrm-amdgpu-dev") set(CPACK_DEBIAN_DEVEL_PACKAGE_REPLACES "hsakmt-roct") # Debian package specific variable for ASAN set(CPACK_DEBIAN_ASAN_PACKAGE_DEPENDS "libdrm-amdgpu-dev | libdrm-dev, rocm-core-asan") set(CPACK_DEBIAN_ASAN_PACKAGE_RECOMMENDS "libdrm-amdgpu-dev") set(CPACK_RPM_PACKAGE_REQUIRES "rocm-core") set(CPACK_RPM_DEVEL_PACKAGE_REQUIRES "rocm-core") # RPM package specific variable for ASAN set(CPACK_RPM_ASAN_PACKAGE_REQUIRES "rocm-core-asan") # NOTE: CentOS/RHEL <8 and SUSE <10 do not have support for rpm recommends, # so HSAKMT_REQUIRES_LIBDRM should be defined when building EL7 to avoid # producing binaries which do not install on CentOS7 or RHEL7 if(HSAKMT_REQUIRES_LIBDRM) string ( APPEND CPACK_RPM_PACKAGE_REQUIRES ", libdrm-amdgpu-devel" ) string ( APPEND CPACK_RPM_DEVEL_PACKAGE_REQUIRES ", libdrm-amdgpu-devel" ) string ( APPEND CPACK_RPM_ASAN_PACKAGE_REQUIRES ", libdrm-amdgpu-devel" ) else() string ( APPEND CPACK_RPM_PACKAGE_REQUIRES ", (libdrm-amdgpu-devel or libdrm-devel)" ) string ( APPEND CPACK_RPM_DEVEL_PACKAGE_REQUIRES ", (libdrm-amdgpu-devel or libdrm-devel)" ) string ( APPEND CPACK_RPM_ASAN_PACKAGE_REQUIRES ", (libdrm-amdgpu-devel or libdrm-devel)" ) set(CPACK_RPM_PACKAGE_RECOMMENDS "libdrm-amdgpu-devel" ) set(CPACK_RPM_DEVEL_PACKAGE_RECOMMENDS "libdrm-amdgpu-devel" ) set(CPACK_RPM_ASAN_PACKAGE_RECOMMENDS "libdrm-amdgpu-devel" ) endif() # Set the names now using CPACK utility set(CPACK_DEBIAN_FILE_NAME "DEB-DEFAULT") set(CPACK_RPM_FILE_NAME "RPM-DEFAULT") # Remove dependency on rocm-core if -DROCM_DEP_ROCMCORE=ON not given to cmake if(NOT ROCM_DEP_ROCMCORE) string(REGEX REPLACE ",? ?rocm-core" "" CPACK_RPM_PACKAGE_REQUIRES ${CPACK_RPM_PACKAGE_REQUIRES}) string(REGEX REPLACE ",? ?rocm-core" "" CPACK_DEBIAN_PACKAGE_DEPENDS ${CPACK_DEBIAN_PACKAGE_DEPENDS}) string(REGEX REPLACE ",? ?rocm-core" "" CPACK_RPM_DEVEL_PACKAGE_REQUIRES ${CPACK_RPM_DEVEL_PACKAGE_REQUIRES}) string(REGEX REPLACE ",? ?rocm-core" "" CPACK_DEBIAN_DEVEL_PACKAGE_DEPENDS ${CPACK_DEBIAN_DEVEL_PACKAGE_DEPENDS}) string(REGEX REPLACE ",? ?rocm-core-asan" "" CPACK_RPM_ASAN_PACKAGE_REQUIRES ${CPACK_RPM_ASAN_PACKAGE_REQUIRES}) string(REGEX REPLACE ",? ?rocm-core-asan" "" CPACK_DEBIAN_ASAN_PACKAGE_DEPENDS ${CPACK_DEBIAN_ASAN_PACKAGE_DEPENDS}) endif() include(CPack) cpack_add_component(asan DISPLAY_NAME "ASAN" DESCRIPTION "ASAN libraries for the LIBHSAKMT") ROCT-Thunk-Interface-rocm-5.7.0/DEBIAN/000077500000000000000000000000001446477712600171615ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/DEBIAN/control000066400000000000000000000002741446477712600205670ustar00rootroot00000000000000Package: hsakmt-rocm-dev Architecture: $arch Maintainer: Advanced Micro Devices Inc. Depends:libpci3, libnuma1 Priority: optional Version: $version Description: Thunk library for AMD KFD ROCT-Thunk-Interface-rocm-5.7.0/DEBIAN/postinst.in000077500000000000000000000007131446477712600214000ustar00rootroot00000000000000#!/bin/bash set -e # left-hand term originates from ENABLE_LDCONFIG = ON/OFF at package build do_ldconfig() { if [ "@ENABLE_LDCONFIG@" == "ON" ]; then echo @CPACK_PACKAGING_INSTALL_PREFIX@/@CMAKE_INSTALL_LIBDIR@ > /@CMAKE_INSTALL_SYSCONFDIR@/ld.so.conf.d/x86_64-libhsakmt.conf ldconfig fi } case "$1" in ( configure ) do_ldconfig ;; ( abort-upgrade | abort-remove | abort-deconfigure ) echo "$1" ;; ( * ) exit 0 ;; esac ROCT-Thunk-Interface-rocm-5.7.0/DEBIAN/prerm.in000077500000000000000000000005371446477712600206460ustar00rootroot00000000000000#!/bin/bash set -e # left-hand term originates from ENABLE_LDCONFIG = ON/OFF at package build rm_ldconfig() { if [ "@ENABLE_LDCONFIG@" == "ON" ]; then rm -f /@CMAKE_INSTALL_SYSCONFDIR@/ld.so.conf.d/x86_64-libhsakmt.conf && ldconfig fi } case "$1" in ( remove | upgrade ) rm_ldconfig ;; ( purge ) ;; ( * ) exit 0 ;; esac ROCT-Thunk-Interface-rocm-5.7.0/DEBIAN/x86_64-libhsakmt.conf000066400000000000000000000000161446477712600227370ustar00rootroot00000000000000/opt/rocm/lib ROCT-Thunk-Interface-rocm-5.7.0/LICENSE.md000066400000000000000000000047461446477712600176560ustar00rootroot00000000000000ROCT-Thunk Interface LICENSE Copyright (c) 2016 Advanced Micro Devices, Inc. All rights reserved. MIT LICENSE: Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. This product contains software provided by Nginx, Inc. and its contributors. Copyright (C) 2002-2018 Igor Sysoev Copyright (C) 2011-2018 Nginx, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ROCT-Thunk-Interface-rocm-5.7.0/README.md000066400000000000000000000056251446477712600175260ustar00rootroot00000000000000### ROCt Library This repository includes the user-mode API interfaces used to interact with the ROCk driver. Starting at 1.7 release, ROCt uses drm render device. This requires the user to belong to video group. Add the user account to video group with "sudo usermod -a -G video _username_" command if the user if not part of video group yet. NOTE: Users of Ubuntu 20.04 will need to add the user to the new "render" group, as Ubuntu has changed the owner:group of /dev/kfd to render:render as of that release #### ROCk Driver The ROCt library is not a standalone product and requires that you have the correct ROCk driver installed, or are using a compatible upstream kernel. Please refer to https://docs.amd.com/ under "Getting Started Guide" for a list of supported Operating Systems and kernel versions, as well as supported hardware. #### Building the Thunk A simple cmake-based system is available for building thunk. To build the thunk from the the ROCT-Thunk-Interface directory, execute: ```bash mkdir -p build cd build cmake .. make ``` If the hsakmt-roct and hsakmt-roct-dev packages are desired: ```bash mkdir -p build cd build cmake .. make package ``` If you choose not to build and install packages, manual installation of the binaries and header files can be done via: ```bash make install ``` NOTE: For older versions of the thunk where hsakmt-dev.txt is present, "make package-dev" and "make install-dev" are required to generate/install the developer packages. Currently, these are created via the "make package" and "make install" commands #### Disclaimer The information contained herein is for informational purposes only, and is subject to change without notice. While every precaution has been taken in the preparation of this document, it may contain technical inaccuracies, omissions and typographical errors, and AMD is under no obligation to update or otherwise correct this information. Advanced Micro Devices, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this document, and assumes no liability of any kind, including the implied warranties of noninfringement, merchantability or fitness for particular purposes, with respect to the operation or use of AMD hardware, software or other products described herein. No license, including implied or arising by estoppel, to any intellectual property rights is granted by this document. Terms and limitations applicable to the purchase or use of AMD's products are as set forth in a signed agreement between the parties or in AMD's Standard Terms and Conditions of Sale. AMD, the AMD Arrow logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright (c) 2014-2023 Advanced Micro Devices, Inc. All rights reserved. ROCT-Thunk-Interface-rocm-5.7.0/RPM/000077500000000000000000000000001446477712600166755ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/RPM/hsakmt-roct-devel.spec.in000066400000000000000000000043131446477712600235100ustar00rootroot00000000000000# Restore old style debuginfo creation for rpm >= 4.14. %undefine _debugsource_packages %undefine _debuginfo_subpackages # -*- rpm-spec -*- BuildRoot: %_topdir/@CPACK_PACKAGE_FILE_NAME@@CPACK_RPM_PACKAGE_COMPONENT_PART_PATH@ Summary: @CPACK_RPM_PACKAGE_SUMMARY@ Name: @CPACK_RPM_PACKAGE_NAME@ Version: @CPACK_RPM_PACKAGE_VERSION@ Release: @CPACK_RPM_PACKAGE_RELEASE@ License: @CPACK_RPM_PACKAGE_LICENSE@ Group: @CPACK_RPM_PACKAGE_GROUP@ Vendor: @CPACK_RPM_PACKAGE_VENDOR@ @TMP_RPM_URL@ @TMP_RPM_REQUIRES@ @TMP_RPM_REQUIRES_PRE@ @TMP_RPM_REQUIRES_POST@ @TMP_RPM_REQUIRES_PREUN@ @TMP_RPM_REQUIRES_POSTUN@ @TMP_RPM_PROVIDES@ @TMP_RPM_OBSOLETES@ @TMP_RPM_CONFLICTS@ @TMP_RPM_SUGGESTS@ @TMP_RPM_AUTOPROV@ @TMP_RPM_AUTOREQ@ @TMP_RPM_AUTOREQPROV@ @TMP_RPM_BUILDARCH@ @TMP_RPM_PREFIXES@ @TMP_RPM_EPOCH@ # Modifications to allow recommends to be used (not implemented in cpack): %if "@CPACK_RPM_PACKAGE_RECOMMENDS@" != "" Recommends: @CPACK_RPM_PACKAGE_RECOMMENDS@ %endif # End of modifications @TMP_RPM_DEBUGINFO@ %define _rpmdir %_topdir/RPMS %define _srcrpmdir %_topdir/SRPMS @FILE_NAME_DEFINE@ %define _unpackaged_files_terminate_build 0 @TMP_RPM_SPEC_INSTALL_POST@ @CPACK_RPM_SPEC_MORE_DEFINE@ @CPACK_RPM_COMPRESSION_TYPE_TMP@ %description @CPACK_RPM_PACKAGE_DESCRIPTION@ # This is a shortcutted spec file generated by CMake RPM generator # we skip _install step because CPack does that for us. # We do only save CPack installed tree in _prepr # and then restore it in build. %prep mv $RPM_BUILD_ROOT %_topdir/tmpBBroot %install if [ -e $RPM_BUILD_ROOT ]; then rm -rf $RPM_BUILD_ROOT fi mv %_topdir/tmpBBroot $RPM_BUILD_ROOT @TMP_RPM_DEBUGINFO_INSTALL@ %clean %post @RPM_SYMLINK_POSTINSTALL@ @CPACK_RPM_SPEC_POSTINSTALL@ %posttrans @CPACK_RPM_SPEC_POSTTRANS@ %postun @CPACK_RPM_SPEC_POSTUNINSTALL@ %pre @CPACK_RPM_SPEC_PREINSTALL@ %pretrans @CPACK_RPM_SPEC_PRETRANS@ %preun @CPACK_RPM_SPEC_PREUNINSTALL@ %files %defattr(@TMP_DEFAULT_FILE_PERMISSIONS@,@TMP_DEFAULT_USER@,@TMP_DEFAULT_GROUP@,@TMP_DEFAULT_DIR_PERMISSIONS@) @CPACK_RPM_INSTALL_FILES@ @CPACK_RPM_ABSOLUTE_INSTALL_FILES@ @CPACK_RPM_USER_INSTALL_FILES@ %changelog @CPACK_RPM_SPEC_CHANGELOG@ @TMP_OTHER_COMPONENTS@ ROCT-Thunk-Interface-rocm-5.7.0/RPM/libhsakmt.spec000066400000000000000000000013241446477712600215270ustar00rootroot00000000000000%define name hsakmt-rocm-dev %define version %{getenv:PACKAGE_VER} %define packageroot %{getenv:PACKAGE_DIR} Name: %{name} Version: %{version} Release: 1 Summary: Thunk libraries for AMD KFD Group: System Environment/Libraries License: Advanced Micro Devices Inc. %if 0%{?centos} == 6 Requires: numactl %else Requires: numactl-libs %endif %description This package includes the libhsakmt (Thunk) libraries for AMD KFD %prep %setup -T -D -c -n %{name} %install cp -R %packageroot $RPM_BUILD_ROOT find $RPM_BUILD_ROOT \! -type d | sed "s|$RPM_BUILD_ROOT||"> thunk.list %post ldconfig %postun ldconfig %clean rm -rf $RPM_BUILD_ROOT %files -f thunk.list %defattr(-,root,root,-) ROCT-Thunk-Interface-rocm-5.7.0/RPM/post.in000066400000000000000000000004071446477712600202130ustar00rootroot00000000000000# left-hand term originates from ENABLE_LDCONFIG = ON/OFF at package build if [ "@ENABLE_LDCONFIG@" == "ON" ]; then echo -e "@CPACK_PACKAGING_INSTALL_PREFIX@/@CMAKE_INSTALL_LIBDIR@" > /@CMAKE_INSTALL_SYSCONFDIR@/ld.so.conf.d/x86_64-libhsakmt.conf ldconfig fi ROCT-Thunk-Interface-rocm-5.7.0/RPM/postun.in000066400000000000000000000004531446477712600205570ustar00rootroot00000000000000# second term originates from ENABLE_LDCONFIG = ON/OFF at package build if [ $1 -le 1 ] && [ "@ENABLE_LDCONFIG@" == "ON" ]; then # perform the below actions for rpm remove($1=0) or upgrade($1=1) operations rm -f /@CMAKE_INSTALL_SYSCONFDIR@/ld.so.conf.d/x86_64-libhsakmt.conf ldconfig fi ROCT-Thunk-Interface-rocm-5.7.0/cmake_modules/000077500000000000000000000000001446477712600210475ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/cmake_modules/utils.cmake000066400000000000000000000124371446477712600232200ustar00rootroot00000000000000################################################################################ ## ## The University of Illinois/NCSA ## Open Source License (NCSA) ## ## Copyright (c) 2014-2017, Advanced Micro Devices, Inc. All rights reserved. ## ## Developed by: ## ## AMD Research and AMD HSA Software Development ## ## Advanced Micro Devices, Inc. ## ## www.amd.com ## ## Permission is hereby granted, free of charge, to any person obtaining a copy ## of this software and associated documentation files (the "Software"), to ## deal with the Software without restriction, including without limitation ## the rights to use, copy, modify, merge, publish, distribute, sublicense, ## and#or sell copies of the Software, and to permit persons to whom the ## Software is furnished to do so, subject to the following conditions: ## ## - Redistributions of source code must retain the above copyright notice, ## this list of conditions and the following disclaimers. ## - Redistributions in binary form must reproduce the above copyright ## notice, this list of conditions and the following disclaimers in ## the documentation and#or other materials provided with the distribution. ## - Neither the names of Advanced Micro Devices, Inc, ## nor the names of its contributors may be used to endorse or promote ## products derived from this Software without specific prior written ## permission. ## ## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ## THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ## OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ## ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ## DEALINGS WITH THE SOFTWARE. ## ################################################################################ ## Parses the VERSION_STRING variable and places ## the first, second and third number values in ## the major, minor and patch variables. function( parse_version VERSION_STRING ) string ( FIND ${VERSION_STRING} "-" STRING_INDEX ) if ( ${STRING_INDEX} GREATER -1 ) math ( EXPR STRING_INDEX "${STRING_INDEX} + 1" ) string ( SUBSTRING ${VERSION_STRING} ${STRING_INDEX} -1 VERSION_BUILD ) endif () string ( REGEX MATCHALL "[0123456789]+" VERSIONS ${VERSION_STRING} ) list ( LENGTH VERSIONS VERSION_COUNT ) if ( ${VERSION_COUNT} GREATER 0) list ( GET VERSIONS 0 MAJOR ) set ( VERSION_MAJOR ${MAJOR} PARENT_SCOPE ) set ( TEMP_VERSION_STRING "${MAJOR}" ) endif () if ( ${VERSION_COUNT} GREATER 1 ) list ( GET VERSIONS 1 MINOR ) set ( VERSION_MINOR ${MINOR} PARENT_SCOPE ) set ( TEMP_VERSION_STRING "${TEMP_VERSION_STRING}.${MINOR}" ) endif () if ( ${VERSION_COUNT} GREATER 2 ) list ( GET VERSIONS 2 PATCH ) set ( VERSION_PATCH ${PATCH} PARENT_SCOPE ) set ( TEMP_VERSION_STRING "${TEMP_VERSION_STRING}.${PATCH}" ) endif () if ( DEFINED VERSION_BUILD ) set ( VERSION_BUILD "${VERSION_BUILD}" PARENT_SCOPE ) endif () set ( VERSION_STRING "${TEMP_VERSION_STRING}" PARENT_SCOPE ) endfunction () ## Gets the current version of the repository ## using versioning tags and git describe. ## Passes back a packaging version string ## and a library version string. function ( get_version DEFAULT_VERSION_STRING ) parse_version ( ${DEFAULT_VERSION_STRING} ) find_program ( GIT NAMES git ) if ( GIT ) execute_process ( COMMAND git describe --tags --dirty --long WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} OUTPUT_VARIABLE GIT_TAG_STRING OUTPUT_STRIP_TRAILING_WHITESPACE RESULT_VARIABLE RESULT ) if ( ${RESULT} EQUAL 0 ) parse_version ( ${GIT_TAG_STRING} ) endif () endif () set( VERSION_STRING "${VERSION_STRING}" PARENT_SCOPE ) set( VERSION_MAJOR "${VERSION_MAJOR}" PARENT_SCOPE ) set( VERSION_MINOR "${VERSION_MINOR}" PARENT_SCOPE ) set( VERSION_PATCH "${VERSION_PATCH}" PARENT_SCOPE ) set( VERSION_BUILD "${VERSION_BUILD}" PARENT_SCOPE ) endfunction() #get the OS version function(get_os_info) if( EXISTS "/etc/os-release") file(STRINGS "/etc/os-release" DISTRO_ID REGEX "^ID=") file(STRINGS "/etc/os-release" DISTRO_RELEASE REGEX "^VERSION_ID=") string(REPLACE "ID=" "" DISTRO_ID "${DISTRO_ID}") string(REPLACE "VERSION_ID=" "" DISTRO_RELEASE "${DISTRO_RELEASE}") message(STATUS "Detected distribution: ${DISTRO_ID}:${DISTRO_RELEASE}") elseif(EXISTS "/etc/centos-release" ) # Example: CentOS release 6.10 (Final) file(STRINGS "/etc/centos-release" DISTRO_FULL_STR REGEX "release") string(REGEX MATCH "^[a-zA-Z]+" DISTRO_ID "${DISTRO_FULL_STR}") string(TOLOWER "${DISTRO_ID}" DISTRO_ID) string(REGEX MATCH "[0-9]+" DISTRO_RELEASE "${DISTRO_FULL_STR}") message(STATUS "Detected distribution: ${DISTRO_ID}:${DISTRO_RELEASE}") else() message(STATUS "Not able to detect OS") endif() set(DISTRO_ID "${DISTRO_ID}" PARENT_SCOPE ) set(DISTRO_RELEASE "${DISTRO_RELEASE}" PARENT_SCOPE ) endfunction() ROCT-Thunk-Interface-rocm-5.7.0/hsakmt-backward-compat.cmake000066400000000000000000000111251446477712600235650ustar00rootroot00000000000000# Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell # copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN # THE SOFTWARE. set(HSAKMT_WRAPPER_DIR ${CMAKE_CURRENT_BINARY_DIR}/wrapper_dir) set(HSAKMT_WRAPPER_INC_DIR ${HSAKMT_WRAPPER_DIR}/include) #Function to generate header template file function(create_header_template) file(WRITE ${HSAKMT_WRAPPER_DIR}/header.hpp.in "/* Copyright (c) 2022 Advanced Micro Devices, Inc. All rights reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the \"Software\"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef @include_guard@ #define @include_guard@ #ifndef ROCM_HEADER_WRAPPER_WERROR #define ROCM_HEADER_WRAPPER_WERROR @deprecated_error@ #endif #if ROCM_HEADER_WRAPPER_WERROR /* ROCM_HEADER_WRAPPER_WERROR 1 */ #error \"@file_name@ has moved to @CMAKE_INSTALL_PREFIX@/@CMAKE_INSTALL_INCLUDEDIR@/hsakmt and package include paths have changed.\\nInclude as \\\"hsakmt/@file_name@\\\" when using cmake packages.\" #else /* ROCM_HEADER_WRAPPER_WERROR 0 */ #if defined(__GNUC__) #warning \"@file_name@ has moved to @CMAKE_INSTALL_PREFIX@/@CMAKE_INSTALL_INCLUDEDIR@/hsakmt and package include paths have changed.\\nInclude as \\\"hsakmt/@file_name@\\\" when using cmake packages.\" #else #pragma message(\"@file_name@ has moved to @CMAKE_INSTALL_PREFIX@/@CMAKE_INSTALL_INCLUDEDIR@/hsakmt and package include paths have changed.\\nInclude as \\\"hsakmt/@file_name@\\\" when using cmake packages.\") #endif #endif /* ROCM_HEADER_WRAPPER_WERROR */ @include_statements@ #endif") endfunction() #use header template file and generate wrapper header files function(generate_wrapper_header) file(MAKE_DIRECTORY ${HSAKMT_WRAPPER_INC_DIR}) #find all header files from include folder file(GLOB include_files ${CMAKE_CURRENT_SOURCE_DIR}/include/*.h) #generate wrapper header files foreach(header_file ${include_files}) # set include guard get_filename_component(INC_GUARD_NAME ${header_file} NAME_WE) string(TOUPPER ${INC_GUARD_NAME} INC_GUARD_NAME) set(include_guard "${include_guard}HSAKMT_WRAPPER_INCLUDE_${INC_GUARD_NAME}_H") # set include statements get_filename_component(file_name ${header_file} NAME) set(include_statements "${include_statements}#include \"hsakmt/${file_name}\"\n") configure_file(${HSAKMT_WRAPPER_DIR}/header.hpp.in ${HSAKMT_WRAPPER_INC_DIR}/${file_name}) unset(include_guard) unset(include_statements) endforeach() endfunction() #Creater a template for header file create_header_template() #Use template header file and generater wrapper header files generate_wrapper_header() install(DIRECTORY ${HSAKMT_WRAPPER_INC_DIR} DESTINATION . COMPONENT devel PATTERN "linux" EXCLUDE) ROCT-Thunk-Interface-rocm-5.7.0/hsakmt-config.cmake.in000066400000000000000000000010731446477712600224010ustar00rootroot00000000000000@PACKAGE_INIT@ include( CMakeFindDependencyMacro ) # Locate dependent packages here. Finding them propagates usage requirements, # if any, to our clients and ensures that their target names are in scope for # the build. hsakmt has no cmake project dependencies so there is nothing to # find. If we switch to use find_package with external (to ROCm) library # dependencies (ie libnuma) then those packages should be located here using # find_dependencies as shown below. #find_dependency(Bar, 2.0) include( "${CMAKE_CURRENT_LIST_DIR}/@HSAKMT_TARGET@Targets.cmake" ) ROCT-Thunk-Interface-rocm-5.7.0/include/000077500000000000000000000000001446477712600176625ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/include/hsakmt.h000066400000000000000000000633121446477712600213270ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef _HSAKMT_H_ #define _HSAKMT_H_ #include "hsakmttypes.h" #ifdef __cplusplus extern "C" { #endif /** "Opens" the HSA kernel driver for user-kernel mode communication. On Windows, this function gets a handle to the KFD's AMDKFDIO device object that is responsible for user-kernel communication, this handle is used internally by the thunk library to send device I/O control to the HSA kernel driver. No other thunk library function may be called unless the user-kernel communication channel is opened first. On Linux this call opens the "/dev/kfd" device file to establish a communication path to the kernel. */ HSAKMT_STATUS HSAKMTAPI hsaKmtOpenKFD( void ); /** "Closes" the user-kernel communication path. On Windows, the handle obtained by the hsaKmtOpenKFD() function is closed; no other communication with the kernel driver is possible after the successful execution of the saKmdCloseKFD() function. Depending on the failure reason, the user-kernel communication path may or may not be still active. On Linux the function closes the "dev/kfd" device file. No further communication to the kernel driver is allowed until hsaKmtOpenKFD() function is called again. */ HSAKMT_STATUS HSAKMTAPI hsaKmtCloseKFD( void ); /** Returns the user-kernel interface version supported by KFD. Higher major numbers usually add new features to KFD and may break user-kernel compatibility; higher minor numbers define additional functionality associated within a major number. The calling software should validate that it meets the minimum interface version as described in the API specification. */ HSAKMT_STATUS HSAKMTAPI hsaKmtGetVersion( HsaVersionInfo* VersionInfo //OUT ); /** The function takes a "snapshot" of the topology information within the KFD to avoid any changes during the enumeration process. */ HSAKMT_STATUS HSAKMTAPI hsaKmtAcquireSystemProperties( HsaSystemProperties* SystemProperties //OUT ); /** Releases the topology "snapshot" taken by hsaKmtAcquireSystemProperties() */ HSAKMT_STATUS HSAKMTAPI hsaKmtReleaseSystemProperties( void ) ; /** Retrieves the discoverable sub-properties for a given HSA node. The parameters returned allow the application or runtime to size the management structures necessary to store the information. */ HSAKMT_STATUS HSAKMTAPI hsaKmtGetNodeProperties( HSAuint32 NodeId, //IN HsaNodeProperties* NodeProperties //OUT ); /** Retrieves the memory properties of a specific HSA node. the memory pointer passed as MemoryProperties is sized as NumBanks * sizeof(HsaMemoryProperties). NumBanks is retrieved with the hsaKmtGetNodeProperties() call. Some of the data returned is optional. Not all implementations may return all parameters in the hsaMemoryProperties. */ HSAKMT_STATUS HSAKMTAPI hsaKmtGetNodeMemoryProperties( HSAuint32 NodeId, //IN HSAuint32 NumBanks, //IN HsaMemoryProperties* MemoryProperties //OUT ); /** Retrieves the cache properties of a specific HSA node and processor ID. ProcessorID refers to either a CPU core or a SIMD unit as enumerated earlier via the hsaKmtGetNodeProperties() call. The memory pointer passed as CacheProperties is sized as NumCaches * sizeof(HsaCacheProperties). NumCaches is retrieved with the hsaKmtGetNodeProperties() call. The data returned is optional. Not all implementations may return all parameters in the CacheProperties. */ HSAKMT_STATUS HSAKMTAPI hsaKmtGetNodeCacheProperties( HSAuint32 NodeId, //IN HSAuint32 ProcessorId, //IN HSAuint32 NumCaches, //IN HsaCacheProperties* CacheProperties //OUT ); /** Retrieves the HSA IO affinity properties of a specific HSA node. the memory pointer passed as Properties is sized as NumIoLinks * sizeof(HsaIoLinkProperties). NumIoLinks is retrieved with the hsaKmtGetNodeProperties() call. The data returned is optional. Not all implementations may return all parameters in the IoLinkProperties. */ HSAKMT_STATUS HSAKMTAPI hsaKmtGetNodeIoLinkProperties( HSAuint32 NodeId, //IN HSAuint32 NumIoLinks, //IN HsaIoLinkProperties* IoLinkProperties //OUT ); /** Creates an operating system event associated with a HSA event ID */ HSAKMT_STATUS HSAKMTAPI hsaKmtCreateEvent( HsaEventDescriptor* EventDesc, //IN bool ManualReset, //IN bool IsSignaled, //IN HsaEvent** Event //OUT ); /** Destroys an operating system event associated with a HSA event ID */ HSAKMT_STATUS HSAKMTAPI hsaKmtDestroyEvent( HsaEvent* Event //IN ); /** Sets the specified event object to the signaled state */ HSAKMT_STATUS HSAKMTAPI hsaKmtSetEvent( HsaEvent* Event //IN ); /** Sets the specified event object to the non-signaled state */ HSAKMT_STATUS HSAKMTAPI hsaKmtResetEvent( HsaEvent* Event //IN ); /** Queries the state of the specified event object */ HSAKMT_STATUS HSAKMTAPI hsaKmtQueryEventState( HsaEvent* Event //IN ); /** Checks the current state of the event object. If the object's state is nonsignaled, the calling thread enters the wait state. The function returns when one of the following occurs: - The specified event object is in the signaled state. - The time-out interval elapses. */ HSAKMT_STATUS HSAKMTAPI hsaKmtWaitOnEvent( HsaEvent* Event, //IN HSAuint32 Milliseconds //IN ); /** Checks the current state of the event object. If the object's state is nonsignaled, the calling thread enters the wait state. event_age can help avoiding race conditions. The function returns when one of the following occurs: - The specified event object is in the signaled state. - The time-out interval elapses. - Tracking event age */ HSAKMT_STATUS HSAKMTAPI hsaKmtWaitOnEvent_Ext( HsaEvent* Event, //IN HSAuint32 Milliseconds, //IN uint64_t *event_age //IN/OUT ); /** Checks the current state of multiple event objects. The function returns when one of the following occurs: - Either any one or all of the specified objects are in the signaled state - if "WaitOnAll" is "true" the function returns when the state of all objects in array is signaled - if "WaitOnAll" is "false" the function returns when the state of any one of the objects is set to signaled - The time-out interval elapses. */ HSAKMT_STATUS HSAKMTAPI hsaKmtWaitOnMultipleEvents( HsaEvent* Events[], //IN HSAuint32 NumEvents, //IN bool WaitOnAll, //IN HSAuint32 Milliseconds //IN ); /** Checks the current state of multiple event objects. event_age can help avoiding race conditions. The function returns when one of the following occurs: - Either any one or all of the specified objects are in the signaled state - if "WaitOnAll" is "true" the function returns when the state of all objects in array is signaled - if "WaitOnAll" is "false" the function returns when the state of any one of the objects is set to signaled - The time-out interval elapses. - Tracking event age */ HSAKMT_STATUS HSAKMTAPI hsaKmtWaitOnMultipleEvents_Ext( HsaEvent* Events[], //IN HSAuint32 NumEvents, //IN bool WaitOnAll, //IN HSAuint32 Milliseconds, //IN uint64_t *event_age //IN/OUT ); /** new TEMPORARY function definition - to be used only on "Triniti + Southern Islands" platform If used on other platforms the function will return HSAKMT_STATUS_ERROR */ HSAKMT_STATUS HSAKMTAPI hsaKmtReportQueue( HSA_QUEUEID QueueId, //IN HsaQueueReport* QueueReport //OUT ); /** Creates a GPU queue with user-mode access rights */ HSAKMT_STATUS HSAKMTAPI hsaKmtCreateQueue( HSAuint32 NodeId, //IN HSA_QUEUE_TYPE Type, //IN HSAuint32 QueuePercentage, //IN HSA_QUEUE_PRIORITY Priority, //IN void* QueueAddress, //IN HSAuint64 QueueSizeInBytes, //IN HsaEvent* Event, //IN HsaQueueResource* QueueResource //OUT ); /** Updates a queue */ HSAKMT_STATUS HSAKMTAPI hsaKmtUpdateQueue( HSA_QUEUEID QueueId, //IN HSAuint32 QueuePercentage,//IN HSA_QUEUE_PRIORITY Priority, //IN void* QueueAddress, //IN HSAuint64 QueueSize, //IN HsaEvent* Event //IN ); /** Destroys a queue */ HSAKMT_STATUS HSAKMTAPI hsaKmtDestroyQueue( HSA_QUEUEID QueueId //IN ); /** Set cu mask for a queue */ HSAKMT_STATUS HSAKMTAPI hsaKmtSetQueueCUMask( HSA_QUEUEID QueueId, //IN HSAuint32 CUMaskCount, //IN HSAuint32* QueueCUMask //IN ); HSAKMT_STATUS HSAKMTAPI hsaKmtGetQueueInfo( HSA_QUEUEID QueueId, //IN HsaQueueInfo *QueueInfo //IN ); /** Allows an HSA process to set/change the default and alternate memory coherency, before starting to dispatch. */ HSAKMT_STATUS HSAKMTAPI hsaKmtSetMemoryPolicy( HSAuint32 Node, //IN HSAuint32 DefaultPolicy, //IN HSAuint32 AlternatePolicy, //IN void* MemoryAddressAlternate, //IN (page-aligned) HSAuint64 MemorySizeInBytes //IN (page-aligned) ); /** Allocates a memory buffer that may be accessed by the GPU */ HSAKMT_STATUS HSAKMTAPI hsaKmtAllocMemory( HSAuint32 PreferredNode, //IN HSAuint64 SizeInBytes, //IN (multiple of page size) HsaMemFlags MemFlags, //IN void** MemoryAddress //IN/OUT (page-aligned) ); /** Frees a memory buffer */ HSAKMT_STATUS HSAKMTAPI hsaKmtFreeMemory( void* MemoryAddress, //IN (page-aligned) HSAuint64 SizeInBytes //IN ); /** Inquires memory available for allocation as a memory buffer */ HSAKMT_STATUS HSAKMTAPI hsaKmtAvailableMemory( HSAuint32 Node, HSAuint64 *AvailableBytes ); /** Registers with KFD a memory buffer that may be accessed by the GPU */ HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterMemory( void* MemoryAddress, //IN (cache-aligned) HSAuint64 MemorySizeInBytes //IN (cache-aligned) ); /** Registers with KFD a memory buffer that may be accessed by specific GPUs */ HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterMemoryToNodes( void *MemoryAddress, // IN (cache-aligned) HSAuint64 MemorySizeInBytes, // IN (cache-aligned) HSAuint64 NumberOfNodes, // IN HSAuint32* NodeArray // IN ); /** Registers with KFD a memory buffer with memory attributes */ HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterMemoryWithFlags( void *MemoryAddress, // IN (cache-aligned) HSAuint64 MemorySizeInBytes, // IN (cache-aligned) HsaMemFlags MemFlags // IN ); /** Registers with KFD a graphics buffer and returns graphics metadata */ HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterGraphicsHandleToNodes( HSAuint64 GraphicsResourceHandle, //IN HsaGraphicsResourceInfo *GraphicsResourceInfo, //OUT HSAuint64 NumberOfNodes, //IN HSAuint32* NodeArray //IN ); /** * Export a dmabuf handle and offset for a given memory address * * Validates that @MemoryAddress belongs to a valid allocation and that the * @MemorySizeInBytes doesn't exceed the end of that allocation. Returns a * dmabuf fd of the allocation and the offset of MemoryAddress within that * allocation. The memory will remain allocated even after the allocation is * freed by hsaKmtFreeMemory for as long as a dmabuf fd remains open or any * importer of that fd maintains an active reference to the memory. */ HSAKMT_STATUS HSAKMTAPI hsaKmtExportDMABufHandle( void *MemoryAddress, //IN HSAuint64 MemorySizeInBytes, //IN int *DMABufFd, //OUT HSAuint64 *Offset //OUT ); /** Export a memory buffer for sharing with other processes NOTE: for the current revision of the thunk spec, SizeInBytes must match whole allocation. */ HSAKMT_STATUS HSAKMTAPI hsaKmtShareMemory( void *MemoryAddress, // IN HSAuint64 SizeInBytes, // IN HsaSharedMemoryHandle *SharedMemoryHandle // OUT ); /** Register shared memory handle */ HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterSharedHandle( const HsaSharedMemoryHandle *SharedMemoryHandle, // IN void **MemoryAddress, // OUT HSAuint64 *SizeInBytes // OUT ); /** Register shared memory handle to specific nodes only */ HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterSharedHandleToNodes( const HsaSharedMemoryHandle *SharedMemoryHandle, // IN void **MemoryAddress, // OUT HSAuint64 *SizeInBytes, // OUT HSAuint64 NumberOfNodes, // OUT HSAuint32* NodeArray // OUT ); /** Copy data from the GPU address space of the process identified by Pid. Size Copied will return actual amount of data copied. If return is not SUCCESS, partial copies could have happened. */ HSAKMT_STATUS HSAKMTAPI hsaKmtProcessVMRead( HSAuint32 Pid, // IN HsaMemoryRange *LocalMemoryArray, // IN HSAuint64 LocalMemoryArrayCount, // IN HsaMemoryRange *RemoteMemoryArray, // IN HSAuint64 RemoteMemoryArrayCount, // IN HSAuint64 *SizeCopied // OUT ); /** Write data to the GPU address space of the process identified by Pid. See also hsaKmtProcessVMRead. */ HSAKMT_STATUS HSAKMTAPI hsaKmtProcessVMWrite( HSAuint32 Pid, // IN HsaMemoryRange *LocalMemoryArray, // IN HSAuint64 LocalMemoryArrayCount, // IN HsaMemoryRange *RemoteMemoryArray, // IN HSAuint64 RemoteMemoryArrayCount, // IN HSAuint64 *SizeCopied // OUT ); /** Unregisters with KFD a memory buffer */ HSAKMT_STATUS HSAKMTAPI hsaKmtDeregisterMemory( void* MemoryAddress //IN ); /** Ensures that the memory is resident and can be accessed by GPU */ HSAKMT_STATUS HSAKMTAPI hsaKmtMapMemoryToGPU( void* MemoryAddress, //IN (page-aligned) HSAuint64 MemorySizeInBytes, //IN (page-aligned) HSAuint64* AlternateVAGPU //OUT (page-aligned) ); /** Ensures that the memory is resident and can be accessed by GPUs */ HSAKMT_STATUS HSAKMTAPI hsaKmtMapMemoryToGPUNodes( void* MemoryAddress, //IN (page-aligned) HSAuint64 MemorySizeInBytes, //IN (page-aligned) HSAuint64* AlternateVAGPU, //OUT (page-aligned) HsaMemMapFlags MemMapFlags, //IN HSAuint64 NumberOfNodes, //IN HSAuint32* NodeArray //IN ); /** Releases the residency of the memory */ HSAKMT_STATUS HSAKMTAPI hsaKmtUnmapMemoryToGPU( void* MemoryAddress //IN (page-aligned) ); /** Notifies the kernel driver that a process wants to use GPU debugging facilities */ HSAKMT_STATUS HSAKMTAPI hsaKmtMapGraphicHandle( HSAuint32 NodeId, //IN HSAuint64 GraphicDeviceHandle, //IN HSAuint64 GraphicResourceHandle, //IN HSAuint64 GraphicResourceOffset, //IN HSAuint64 GraphicResourceSize, //IN HSAuint64* FlatMemoryAddress //OUT ); /** Stub for Unmap Graphic Handle */ HSAKMT_STATUS HSAKMTAPI hsaKmtUnmapGraphicHandle( HSAuint32 NodeId, //IN HSAuint64 FlatMemoryAddress, //IN HSAuint64 SizeInBytes //IN ); /** * Get an AMDGPU device handle for a GPU node */ HSAKMT_STATUS HSAKMTAPI hsaKmtGetAMDGPUDeviceHandle( HSAuint32 NodeId, //IN HsaAMDGPUDeviceHandle *DeviceHandle //OUT ); /** Allocate GWS resource for a queue */ HSAKMT_STATUS HSAKMTAPI hsaKmtAllocQueueGWS( HSA_QUEUEID QueueId, //IN HSAuint32 nGWS, //IN HSAuint32 *firstGWS //OUT ); /** Notifies the kernel driver that a process wants to use GPU debugging facilities */ HSAKMT_STATUS HSAKMTAPI hsaKmtDbgRegister( HSAuint32 NodeId //IN ); /** Detaches the debugger process from the HW debug established by hsaKmtDbgRegister() API */ HSAKMT_STATUS HSAKMTAPI hsaKmtDbgUnregister( HSAuint32 NodeId //IN ); /** Controls a wavefront */ HSAKMT_STATUS HSAKMTAPI hsaKmtDbgWavefrontControl( HSAuint32 NodeId, //IN HSA_DBG_WAVEOP Operand, //IN HSA_DBG_WAVEMODE Mode, //IN HSAuint32 TrapId, //IN HsaDbgWaveMessage* DbgWaveMsgRing //IN ); /** Sets watch points on memory address ranges to generate exception events when the watched addresses are accessed */ HSAKMT_STATUS HSAKMTAPI hsaKmtDbgAddressWatch( HSAuint32 NodeId, //IN HSAuint32 NumWatchPoints, //IN HSA_DBG_WATCH_MODE WatchMode[], //IN void* WatchAddress[], //IN HSAuint64 WatchMask[], //IN, optional HsaEvent* WatchEvent[] //IN, optional ); HSAKMT_STATUS HSAKMTAPI hsaKmtRuntimeEnable( void* rDebug, // IN bool setupTtmp ); HSAKMT_STATUS HSAKMTAPI hsaKmtRuntimeDisable(void); HSAKMT_STATUS HSAKMTAPI hsaKmtGetRuntimeCapabilities( HSAuint32 *caps_mask // OUT ); /** Enable debug trap. */ HSAKMT_STATUS HSAKMTAPI hsaKmtDbgEnable( void **runtime_info, //Out HSAuint32 *data_size //Out ); /** Disable debug trap. */ HSAKMT_STATUS HSAKMTAPI hsaKmtDbgDisable(void); /** Get device snapshot. */ HSAKMT_STATUS HSAKMTAPI hsaKmtDbgGetDeviceData( void **data, //Out HSAuint32 *n_entries, //Out HSAuint32 *entry_size //Out ); /** Get queues snapshot. */ HSAKMT_STATUS HSAKMTAPI hsaKmtDbgGetQueueData( void **data, //Out HSAuint32 *n_entries, //Out HSAuint32 *entry_size, //Out bool suspend_queues //In ); /** Gets GPU and CPU clock counters for particular Node */ HSAKMT_STATUS HSAKMTAPI hsaKmtGetClockCounters( HSAuint32 NodeId, //IN HsaClockCounters* Counters //OUT ); /** Retrieves information on the available HSA counters */ HSAKMT_STATUS HSAKMTAPI hsaKmtPmcGetCounterProperties( HSAuint32 NodeId, //IN HsaCounterProperties** CounterProperties //OUT ); /** Registers a set of (HW) counters to be used for tracing/profiling */ HSAKMT_STATUS HSAKMTAPI hsaKmtPmcRegisterTrace( HSAuint32 NodeId, //IN HSAuint32 NumberOfCounters, //IN HsaCounter* Counters, //IN HsaPmcTraceRoot* TraceRoot //OUT ); /** Unregisters a set of (HW) counters used for tracing/profiling */ HSAKMT_STATUS HSAKMTAPI hsaKmtPmcUnregisterTrace( HSAuint32 NodeId, //IN HSATraceId TraceId //IN ); /** Allows a user mode process to get exclusive access to the defined set of (HW) counters used for tracing/profiling */ HSAKMT_STATUS HSAKMTAPI hsaKmtPmcAcquireTraceAccess( HSAuint32 NodeId, //IN HSATraceId TraceId //IN ); /** Allows a user mode process to release exclusive access to the defined set of (HW) counters used for tracing/profiling */ HSAKMT_STATUS HSAKMTAPI hsaKmtPmcReleaseTraceAccess( HSAuint32 NodeId, //IN HSATraceId TraceId //IN ); /** Starts tracing operation on a previously established set of performance counters */ HSAKMT_STATUS HSAKMTAPI hsaKmtPmcStartTrace( HSATraceId TraceId, //IN void* TraceBuffer, //IN (page aligned) HSAuint64 TraceBufferSizeBytes //IN (page aligned) ); /** Forces an update of all the counters that a previously started trace operation has registered */ HSAKMT_STATUS HSAKMTAPI hsaKmtPmcQueryTrace( HSATraceId TraceId //IN ); /** Stops tracing operation on a previously established set of performance counters */ HSAKMT_STATUS HSAKMTAPI hsaKmtPmcStopTrace( HSATraceId TraceId //IN ); /** Sets trap handler and trap buffer to be used for all queues associated with the specified NodeId within this process context */ HSAKMT_STATUS HSAKMTAPI hsaKmtSetTrapHandler( HSAuint32 NodeId, //IN void* TrapHandlerBaseAddress, //IN HSAuint64 TrapHandlerSizeInBytes, //IN void* TrapBufferBaseAddress, //IN HSAuint64 TrapBufferSizeInBytes //IN ); /** Gets image tile configuration. */ HSAKMT_STATUS HSAKMTAPI hsaKmtGetTileConfig( HSAuint32 NodeId, // IN HsaGpuTileConfig* config // IN & OUT ); /** Returns information about pointers */ HSAKMT_STATUS HSAKMTAPI hsaKmtQueryPointerInfo( const void * Pointer, //IN HsaPointerInfo * PointerInfo //OUT ); /** Associates user data with a memory allocation */ HSAKMT_STATUS HSAKMTAPI hsaKmtSetMemoryUserData( const void * Pointer, //IN void * UserData //IN ); /** Acquire request exclusive use of SPM */ HSAKMT_STATUS HSAKMTAPI hsaKmtSPMAcquire( HSAuint32 PreferredNode //IN ); /** Release exclusive use of SPM */ HSAKMT_STATUS HSAKMTAPI hsaKmtSPMRelease( HSAuint32 PreferredNode //IN ); /** Set up the destination user mode buffer for stream performance counter data. */ HSAKMT_STATUS HSAKMTAPI hsaKmtSPMSetDestBuffer( HSAuint32 PreferredNode, //IN HSAuint32 SizeInBytes, //IN HSAuint32 * timeout, //IN/OUT HSAuint32 * SizeCopied, //OUT void *DestMemoryAddress, //IN bool *isSPMDataLoss //OUT ); /* Helper functions for calling KFD SVM ioctl */ HSAKMT_STATUS HSAKMTAPI hsaKmtSVMSetAttr( void *start_addr, // IN: Start of the virtual address range (page-aligned) HSAuint64 size, // IN: size (page-aligned) unsigned int nattr, // IN: number of attributes HSA_SVM_ATTRIBUTE *attrs // IN: array of attributes ); HSAKMT_STATUS HSAKMTAPI hsaKmtSVMGetAttr( void *start_addr, // IN: Start of the virtual address range (page-aligned) HSAuint64 size, // IN: size (page aligned) unsigned int nattr, // IN: number of attributes HSA_SVM_ATTRIBUTE *attrs // IN/OUT: array of attributes ); HSAKMT_STATUS HSAKMTAPI hsaKmtSetXNACKMode( HSAint32 enable // IN: enable/disable XNACK node. ); HSAKMT_STATUS HSAKMTAPI hsaKmtGetXNACKMode( HSAint32 * enable // OUT: returns XNACK value. ); /** Open anonymous file handle to enable events and read SMI events. To enable events, write 64bit events mask to fd, event enums as bit index. for example, event mask (HSA_SMI_EVENT_MASK_FROM_INDEX(HSA_SMI_EVENT_INDEX_MAX) - 1) to enable all events Read event from fd is not blocking, use poll with timeout value to check if event is available. Event is dropped if kernel event fifo is full. */ HSAKMT_STATUS HSAKMTAPI hsaKmtOpenSMI( HSAuint32 NodeId, // IN: GPU node_id to receive the SMI event from int *fd // OUT: anonymous file handle ); /** If this is GPU Mapped memory, remap the first page at this address to be normal system memory This is used in ASAN mode to remap the first page of device memory to share host ASAN logic. This function is only supported when libhsakmt is compiled in ASAN mode. */ HSAKMT_STATUS HSAKMTAPI hsaKmtReplaceAsanHeaderPage( void *addr // IN: Start of othe virtual address page ); /** If this is GPU Mapped memory, remap the first page back to the original GPU memory This is used in ASAN mode to remap the first page back to its original mapping. This function is only supported when libhsakmt is compiled in ASAN mode. */ HSAKMT_STATUS HSAKMTAPI hsaKmtReturnAsanHeaderPage( void *addr // IN: Start of othe virtual address page ); #ifdef __cplusplus } //extern "C" #endif #endif //_HSAKMT_H_ ROCT-Thunk-Interface-rocm-5.7.0/include/hsakmttypes.h000066400000000000000000002004421446477712600224110ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef _HSAKMTTYPES_H_ #define _HSAKMTTYPES_H_ //the definitions and THUNK API are version specific - define the version numbers here #define HSAKMT_VERSION_MAJOR 0 #define HSAKMT_VERSION_MINOR 99 #ifdef __cplusplus extern "C" { #endif #if defined(_WIN64) || defined(_WINDOWS) || defined(_WIN32) #if defined(_WIN32) #define HSAKMTAPI __stdcall #else #define HSAKMTAPI #endif typedef unsigned char HSAuint8; typedef char HSAint8; typedef unsigned short HSAuint16; typedef signed short HSAint16; typedef unsigned __int32 HSAuint32; typedef signed __int32 HSAint32; typedef signed __int64 HSAint64; typedef unsigned __int64 HSAuint64; #elif defined(__linux__) #include #include #define HSAKMTAPI typedef uint8_t HSAuint8; typedef int8_t HSAint8; typedef uint16_t HSAuint16; typedef int16_t HSAint16; typedef uint32_t HSAuint32; typedef int32_t HSAint32; typedef int64_t HSAint64; typedef uint64_t HSAuint64; #endif typedef void* HSA_HANDLE; typedef HSAuint64 HSA_QUEUEID; // An HSA_QUEUEID that is never a valid queue ID. #define INVALID_QUEUEID 0xFFFFFFFFFFFFFFFFULL // A PID that is never a valid process ID. #define INVALID_PID 0xFFFFFFFF // // A HSA_NODEID that is never a valid node ID. #define INVALID_NODEID 0xFFFFFFFF // This is included in order to force the alignments to be 4 bytes so that // it avoids extra padding added by the compiler when a 64-bit binary is generated. #pragma pack(push, hsakmttypes_h, 4) // // HSA STATUS codes returned by the KFD Interfaces // typedef enum _HSAKMT_STATUS { HSAKMT_STATUS_SUCCESS = 0, // Operation successful HSAKMT_STATUS_ERROR = 1, // General error return if not otherwise specified HSAKMT_STATUS_DRIVER_MISMATCH = 2, // User mode component is not compatible with kernel HSA driver HSAKMT_STATUS_INVALID_PARAMETER = 3, // KFD identifies input parameters invalid HSAKMT_STATUS_INVALID_HANDLE = 4, // KFD identifies handle parameter invalid HSAKMT_STATUS_INVALID_NODE_UNIT = 5, // KFD identifies node or unit parameter invalid HSAKMT_STATUS_NO_MEMORY = 6, // No memory available (when allocating queues or memory) HSAKMT_STATUS_BUFFER_TOO_SMALL = 7, // A buffer needed to handle a request is too small HSAKMT_STATUS_NOT_IMPLEMENTED = 10, // KFD function is not implemented for this set of paramters HSAKMT_STATUS_NOT_SUPPORTED = 11, // KFD function is not supported on this node HSAKMT_STATUS_UNAVAILABLE = 12, // KFD function is not available currently on this node (but // may be at a later time) HSAKMT_STATUS_OUT_OF_RESOURCES = 13, // KFD function request exceeds the resources currently available. HSAKMT_STATUS_KERNEL_IO_CHANNEL_NOT_OPENED = 20, // KFD driver path not opened HSAKMT_STATUS_KERNEL_COMMUNICATION_ERROR = 21, // user-kernel mode communication failure HSAKMT_STATUS_KERNEL_ALREADY_OPENED = 22, // KFD driver path already opened HSAKMT_STATUS_HSAMMU_UNAVAILABLE = 23, // ATS/PRI 1.1 (Address Translation Services) not available // (IOMMU driver not installed or not-available) HSAKMT_STATUS_WAIT_FAILURE = 30, // The wait operation failed HSAKMT_STATUS_WAIT_TIMEOUT = 31, // The wait operation timed out HSAKMT_STATUS_MEMORY_ALREADY_REGISTERED = 35, // Memory buffer already registered HSAKMT_STATUS_MEMORY_NOT_REGISTERED = 36, // Memory buffer not registered HSAKMT_STATUS_MEMORY_ALIGNMENT = 37, // Memory parameter not aligned } HSAKMT_STATUS; // // HSA KFD interface version information. Calling software has to validate that it meets // the minimum interface version as described in the API specification. // All future structures will be extended in a backward compatible fashion. // typedef struct _HsaVersionInfo { HSAuint32 KernelInterfaceMajorVersion; // supported kernel interface major version HSAuint32 KernelInterfaceMinorVersion; // supported kernel interface minor version } HsaVersionInfo; // // HSA Topology Discovery Infrastructure structure definitions. // The infrastructure implementation is based on design specified in the Kernel HSA Driver ADD // The discoverable data is retrieved from ACPI structures in the platform infrastructure, as defined // in the "Heterogeneous System Architecture Detail Topology" specification. // // The following structure is returned on a call to hsaKmtAcquireSystemProperties() as output. // When the call is made within a process context, a "snapshot" of the topology information // is taken within the KFD to avoid any changes during the enumeration process. // The Snapshot is released when hsaKmtReleaseSystemProperties() is called // or when the process exits or is terminated. // typedef struct _HsaSystemProperties { HSAuint32 NumNodes; // the number of "H-NUMA" memory nodes. // each node represents a discoverable node of the system // All other enumeration is done on a per-node basis HSAuint32 PlatformOem; // identifies HSA platform, reflects the OEMID in the CRAT HSAuint32 PlatformId; // HSA platform ID, reflects OEM TableID in the CRAT HSAuint32 PlatformRev; // HSA platform revision, reflects Platform Table Revision ID } HsaSystemProperties; typedef union { HSAuint32 Value; struct { unsigned int uCode : 10; // ucode packet processor version unsigned int Major : 6; // GFXIP Major engine version unsigned int Minor : 8; // GFXIP Minor engine version unsigned int Stepping : 8; // GFXIP Stepping info }ui32; } HSA_ENGINE_ID; typedef union { HSAuint32 Value; struct { unsigned int uCodeSDMA: 10; // ucode version SDMA engine unsigned int uCodeRes : 10; // ucode version (reserved) unsigned int Reserved : 12; // Reserved, must be 0 }; } HSA_ENGINE_VERSION; typedef union { HSAuint32 Value; struct { unsigned int HotPluggable : 1; // the node may be removed by some system action // (event will be sent) unsigned int HSAMMUPresent : 1; // This node has an ATS/PRI 1.1 compatible // translation agent in the system (e.g. IOMMUv2) unsigned int SharedWithGraphics : 1; // this HSA nodes' GPU function is also used for OS primary // graphics render (= UI) unsigned int QueueSizePowerOfTwo : 1; // This node GPU requires the queue size to be a power of 2 value unsigned int QueueSize32bit : 1; // This node GPU requires the queue size to be less than 4GB unsigned int QueueIdleEvent : 1; // This node GPU supports notification on Queue Idle unsigned int VALimit : 1; // This node GPU has limited VA range for platform // (typical 40bit). Affects shared VM use for 64bit apps unsigned int WatchPointsSupported: 1; // Indicates if Watchpoints are available on the node. unsigned int WatchPointsTotalBits: 4; // Watchpoints available. To determine the number use 2^value unsigned int DoorbellType : 2; // 0: This node has pre-1.0 doorbell characteristic // 1: This node has 1.0 doorbell characteristic // 2,3: reserved for future use unsigned int AQLQueueDoubleMap : 1; // The unit needs a VA “double map” unsigned int DebugTrapSupported : 1; // Indicates if Debug Trap is supported on the node. unsigned int WaveLaunchTrapOverrideSupported: 1; // Indicates if Wave Launch Trap Override is supported on the node. unsigned int WaveLaunchModeSupported: 1; // Indicates if Wave Launch Mode is supported on the node. unsigned int PreciseMemoryOperationsSupported: 1; // Indicates if Precise Memory Operations are supported on the node. unsigned int DEPRECATED_SRAM_EDCSupport: 1; // Old buggy user mode depends on this being 0 unsigned int Mem_EDCSupport: 1; // Indicates if GFX internal DRAM/HBM EDC/ECC functionality is active unsigned int RASEventNotify: 1; // Indicates if GFX extended RASFeatures and RAS EventNotify status is available unsigned int ASICRevision: 4; // Indicates the ASIC revision of the chip on this node. unsigned int SRAM_EDCSupport: 1; // Indicates if GFX internal SRAM EDC/ECC functionality is active unsigned int SVMAPISupported : 1; // Whether or not the SVM API is supported unsigned int CoherentHostAccess: 1; // Whether or not device memory can be coherently accessed by the host CPU unsigned int DebugSupportedFirmware : 1; unsigned int Reserved : 2; } ui32; } HSA_CAPABILITY; // Debug Properties and values // HSA runtime may expose a subset of the capabilities outlined to the applicati typedef union { HSAuint64 Value; struct { HSAuint64 WatchAddrMaskLoBit: 4; // Only bits // WatchAddrMaskLoBit..WatchAddrMaskHiBit // of the HSAuint64 WatchAddrMaskHiBit: 6; // watch address mask are used. // 0 is the least significant bit. HSAuint64 DispatchInfoAlwaysValid: 1; // 0 if control of TTMP setup is // controlled on a per process // basis and is not always enabled // 1 if TTMP setup is always // enabled HSAuint64 AddressWatchpointShareKind: 1; // whether the address watchpoint // is per process or shared with // all proccesses // 0 if shared or unsuppoted // (unsupported indicated by // address_watchpoint_count == 0) // All current devices have shared watchpoints // 1 if unshared HSAuint64 Reserved: 52; // }; } HSA_DEBUG_PROPERTIES; // // HSA node properties. This structure is an output parameter of hsaKmtGetNodeProperties() // The application or runtime can use the information herein to size the topology management structures // Unless there is some very weird setup, there is at most one "GPU" device (with a certain number // of throughput compute units (= SIMDs) associated with a H-NUMA node. // #define HSA_PUBLIC_NAME_SIZE 64 // Marketing name string size typedef struct _HsaNodeProperties { HSAuint32 NumCPUCores; // # of latency (= CPU) cores present on this HSA node. // This value is 0 for a HSA node with no such cores, // e.g a "discrete HSA GPU" HSAuint32 NumFComputeCores; // # of HSA throughtput (= GPU) FCompute cores ("SIMD") present in a node. // This value is 0 if no FCompute cores are present (e.g. pure "CPU node"). HSAuint32 NumMemoryBanks; // # of discoverable memory bank affinity properties on this "H-NUMA" node. HSAuint32 NumCaches; // # of discoverable cache affinity properties on this "H-NUMA" node. HSAuint32 NumIOLinks; // # of discoverable IO link affinity properties of this node // connecting to other nodes. HSAuint32 CComputeIdLo; // low value of the logical processor ID of the latency (= CPU) // cores available on this node HSAuint32 FComputeIdLo; // low value of the logical processor ID of the throughput (= GPU) // units available on this node HSA_CAPABILITY Capability; // see above HSAuint32 MaxWavesPerSIMD; // This identifies the max. number of launched waves per SIMD. // If NumFComputeCores is 0, this value is ignored. HSAuint32 LDSSizeInKB; // Size of Local Data Store in Kilobytes per SIMD Wavefront HSAuint32 GDSSizeInKB; // Size of Global Data Store in Kilobytes shared across SIMD Wavefronts HSAuint32 WaveFrontSize; // Number of SIMD cores per wavefront executed, typically 64, // may be 32 or a different value for some HSA based architectures HSAuint32 NumShaderBanks; // Number of Shader Banks or Shader Engines, typical values are 1 or 2 HSAuint32 NumArrays; // Number of SIMD arrays per engine HSAuint32 NumCUPerArray; // Number of Compute Units (CU) per SIMD array HSAuint32 NumSIMDPerCU; // Number of SIMD representing a Compute Unit (CU) HSAuint32 MaxSlotsScratchCU; // Number of temp. memory ("scratch") wave slots available to access, // may be 0 if HW has no restrictions HSA_ENGINE_ID EngineId; // Identifier (rev) of the GPU uEngine or Firmware, may be 0 HSAuint16 VendorId; // GPU vendor id; 0 on latency (= CPU)-only nodes HSAuint16 DeviceId; // GPU device id; 0 on latency (= CPU)-only nodes HSAuint32 LocationId; // GPU BDF (Bus/Device/function number) - identifies the device // location in the overall system HSAuint64 LocalMemSize; // Local memory size HSAuint32 MaxEngineClockMhzFCompute; // maximum engine clocks for CPU and HSAuint32 MaxEngineClockMhzCCompute; // GPU function, including any boost caopabilities, HSAint32 DrmRenderMinor; // DRM render device minor device number HSAuint16 MarketingName[HSA_PUBLIC_NAME_SIZE]; // Public name of the "device" on the node (board or APU name). // Unicode string HSAuint8 AMDName[HSA_PUBLIC_NAME_SIZE]; //CAL Name of the "device", ASCII HSA_ENGINE_VERSION uCodeEngineVersions; HSA_DEBUG_PROPERTIES DebugProperties; // Debug properties of this node. HSAuint64 HiveID; // XGMI Hive the GPU node belongs to in the system. It is an opaque and static // number hash created by the PSP HSAuint32 NumSdmaEngines; // number of PCIe optimized SDMA engines HSAuint32 NumSdmaXgmiEngines;// number of XGMI optimized SDMA engines HSAuint8 NumSdmaQueuesPerEngine;// number of SDMA queue per one engine HSAuint8 NumCpQueues; // number of Compute queues HSAuint8 NumGws; // number of GWS barriers HSAuint8 Reserved2; HSAuint32 Domain; // PCI domain of the GPU HSAuint64 UniqueID; // Globally unique immutable id HSAuint32 VGPRSizePerCU; // VGPR size in bytes per CU HSAuint32 SGPRSizePerCU; // SGPR size in bytes per CU HSAuint32 NumXcc; // Number of XCC HSAuint32 KFDGpuID; // GPU Hash ID generated by KFD HSAuint32 FamilyID; // GPU family id } HsaNodeProperties; typedef enum _HSA_HEAPTYPE { HSA_HEAPTYPE_SYSTEM = 0, HSA_HEAPTYPE_FRAME_BUFFER_PUBLIC = 1, // CPU "visible" part of GPU device local memory (for discrete GPU) HSA_HEAPTYPE_FRAME_BUFFER_PRIVATE = 2, // CPU "invisible" part of GPU device local memory (for discrete GPU) // All HSA accessible memory is per definition "CPU visible" // "Private memory" is relevant for graphics interop only. HSA_HEAPTYPE_GPU_GDS = 3, // GPU internal memory (GDS) HSA_HEAPTYPE_GPU_LDS = 4, // GPU internal memory (LDS) HSA_HEAPTYPE_GPU_SCRATCH = 5, // GPU special memory (scratch) HSA_HEAPTYPE_DEVICE_SVM = 6, // sys-memory mapped by device page tables HSA_HEAPTYPE_MMIO_REMAP = 7, // remapped mmio, such as hdp flush registers HSA_HEAPTYPE_NUMHEAPTYPES, HSA_HEAPTYPE_SIZE = 0xFFFFFFFF } HSA_HEAPTYPE; typedef union { HSAuint32 MemoryProperty; struct { unsigned int HotPluggable : 1; // the memory may be removed by some system action, // memory should be used for temporary data unsigned int NonVolatile : 1; // memory content is preserved across a power-off cycle. unsigned int Reserved :30; } ui32; } HSA_MEMORYPROPERTY; // // Discoverable HSA Memory properties. // The structure is the output parameter of the hsaKmtGetNodeMemoryProperties() function // typedef struct _HsaMemoryProperties { HSA_HEAPTYPE HeapType; // system or frame buffer, union { HSAuint64 SizeInBytes; // physical memory size of the memory range in bytes struct { HSAuint32 SizeInBytesLow; // physical memory size of the memory range in bytes (lower 32bit) HSAuint32 SizeInBytesHigh; // physical memory size of the memory range in bytes (higher 32bit) } ui32; }; HSA_MEMORYPROPERTY Flags; // See definitions above HSAuint32 Width; // memory width - the number of parallel bits of the memory interface HSAuint32 MemoryClockMax; // memory clock for the memory, this allows computing the available bandwidth // to the memory when needed HSAuint64 VirtualBaseAddress; // if set to value != 0, indicates the virtual base address of the memory // in process virtual space } HsaMemoryProperties; // // Discoverable Cache Properties. (optional). // The structure is the output parameter of the hsaKmtGetNodeMemoryProperties() function // Any of the parameters may be 0 (= not defined) // #define HSA_CPU_SIBLINGS 256 #define HSA_PROCESSORID_ALL 0xFFFFFFFF typedef union { HSAuint32 Value; struct { unsigned int Data : 1; unsigned int Instruction : 1; unsigned int CPU : 1; unsigned int HSACU : 1; unsigned int Reserved :28; } ui32; } HsaCacheType; typedef struct _HaCacheProperties { HSAuint32 ProcessorIdLow; // Identifies the processor number HSAuint32 CacheLevel; // Integer representing level: 1, 2, 3, 4, etc HSAuint32 CacheSize; // Size of the cache HSAuint32 CacheLineSize; // Cache line size in bytes HSAuint32 CacheLinesPerTag; // Cache lines per Cache Tag HSAuint32 CacheAssociativity; // Cache Associativity HSAuint32 CacheLatency; // Cache latency in ns HsaCacheType CacheType; HSAuint32 SiblingMap[HSA_CPU_SIBLINGS]; } HsaCacheProperties; // // Discoverable CPU Compute Properties. (optional). // The structure is the output parameter of the hsaKmtGetCComputeProperties() function // Any of the parameters may be 0 (= not defined) // typedef struct _HsaCComputeProperties { HSAuint32 SiblingMap[HSA_CPU_SIBLINGS]; } HsaCComputeProperties; // // Discoverable IoLink Properties (optional). // The structure is the output parameter of the hsaKmtGetIoLinkProperties() function. // Any of the parameters may be 0 (= not defined) // typedef enum _HSA_IOLINKTYPE { HSA_IOLINKTYPE_UNDEFINED = 0, HSA_IOLINKTYPE_HYPERTRANSPORT = 1, HSA_IOLINKTYPE_PCIEXPRESS = 2, HSA_IOLINKTYPE_AMBA = 3, HSA_IOLINKTYPE_MIPI = 4, HSA_IOLINK_TYPE_QPI_1_1 = 5, HSA_IOLINK_TYPE_RESERVED1 = 6, HSA_IOLINK_TYPE_RESERVED2 = 7, HSA_IOLINK_TYPE_RAPID_IO = 8, HSA_IOLINK_TYPE_INFINIBAND = 9, HSA_IOLINK_TYPE_RESERVED3 = 10, HSA_IOLINK_TYPE_XGMI = 11, HSA_IOLINK_TYPE_XGOP = 12, HSA_IOLINK_TYPE_GZ = 13, HSA_IOLINK_TYPE_ETHERNET_RDMA = 14, HSA_IOLINK_TYPE_RDMA_OTHER = 15, HSA_IOLINK_TYPE_OTHER = 16, HSA_IOLINKTYPE_NUMIOLINKTYPES, HSA_IOLINKTYPE_SIZE = 0xFFFFFFFF } HSA_IOLINKTYPE; typedef union { HSAuint32 LinkProperty; struct { unsigned int Override : 1; // bus link properties are determined by this structure // not by the HSA_IOLINKTYPE. The other flags are valid // only if this bit is set to one unsigned int NonCoherent : 1; // The link doesn't support coherent transactions // memory accesses across must not be set to "host cacheable"! unsigned int NoAtomics32bit : 1; // The link doesn't support 32bit-wide atomic transactions unsigned int NoAtomics64bit : 1; // The link doesn't support 64bit-wide atomic transactions unsigned int NoPeerToPeerDMA : 1; // The link doesn't allow device P2P access unsigned int Reserved :27; } ui32; } HSA_LINKPROPERTY; typedef struct _HsaIoLinkProperties { HSA_IOLINKTYPE IoLinkType; // see above HSAuint32 VersionMajor; // Bus interface version (optional) HSAuint32 VersionMinor; // Bus interface version (optional) HSAuint32 NodeFrom; // HSAuint32 NodeTo; // HSAuint32 Weight; // weight factor (derived from CDIT) HSAuint32 MinimumLatency; // minimum cost of time to transfer (rounded to ns) HSAuint32 MaximumLatency; // maximum cost of time to transfer (rounded to ns) HSAuint32 MinimumBandwidth; // minimum interface Bandwidth in MB/s HSAuint32 MaximumBandwidth; // maximum interface Bandwidth in MB/s HSAuint32 RecTransferSize; // recommended transfer size to reach maximum bandwidth in Bytes HSA_LINKPROPERTY Flags; // override flags (may be active for specific platforms) } HsaIoLinkProperties; // // Memory allocation definitions for the KFD HSA interface // typedef struct _HsaMemFlags { union { struct { unsigned int NonPaged : 1; // default = 0: pageable memory unsigned int CachePolicy : 2; // see HSA_CACHING_TYPE unsigned int ReadOnly : 1; // default = 0: Read/Write memory unsigned int PageSize : 2; // see HSA_PAGE_SIZE unsigned int HostAccess : 1; // default = 0: GPU access only unsigned int NoSubstitute: 1; // default = 0: if specific memory is not available on node (e.g. on // discrete GPU local), allocation may fall back to system memory node 0 // memory (= always available). Otherwise no allocation is possible. unsigned int GDSMemory : 1; // default = 0: If set, the allocation will occur in GDS heap. // HostAccess must be 0, all other flags (except NoSubstitute) should // be 0 when setting this entry to 1. GDS allocation may fail due to // limited resources. Application code is required to work without // any allocated GDS memory using regular memory. // Allocation fails on any node without GPU function. unsigned int Scratch : 1; // default = 0: If set, the allocation will occur in GPU "scratch area". // HostAccess must be 0, all other flags (except NoSubstitute) should be 0 // when setting this entry to 1. Scratch allocation may fail due to limited // resources. Application code is required to work without any allocation. // Allocation fails on any node without GPU function. unsigned int AtomicAccessFull: 1; // default = 0: If set, the memory will be allocated and mapped to allow // atomic ops processing. On AMD APU, this will use the ATC path on system // memory, irrespective of the NonPaged flag setting (= if NonPaged is set, // the memory is pagelocked but mapped through IOMMUv2 instead of GPUVM). // All atomic ops must be supported on this memory. unsigned int AtomicAccessPartial: 1; // default = 0: See above for AtomicAccessFull description, however // focused on AMD discrete GPU that support PCIe atomics; the memory // allocation is mapped to allow for PCIe atomics to operate on system // memory, irrespective of NonPaged set or the presence of an ATC path // in the system. The atomic operations supported are limited to SWAP, // CompareAndSwap (CAS) and FetchAdd (this PCIe op allows both atomic // increment and decrement via 2-complement arithmetic), which are the // only atomic ops directly supported in PCI Express. // On AMD APU, setting this flag will allocate the same type of memory // as AtomicAccessFull, but it will be considered compatible with // discrete GPU atomic operations access. unsigned int ExecuteAccess: 1; // default = 0: Identifies if memory is primarily used for data or accessed // for executable code (e.g. queue memory) by the host CPU or the device. // Influences the page attribute setting within the allocation unsigned int CoarseGrain : 1; // default = 0: The memory can be accessed assuming cache // coherency maintained by link infrastructure and HSA agents. // 1: memory consistency needs to be enforced at // synchronization points at dispatch or other software // enforced synchronization boundaries. unsigned int AQLQueueMemory: 1; // default = 0; If 1: The caller indicates that the memory will be used as AQL queue memory. // The KFD will ensure that the memory returned is allocated in the optimal memory location // and optimal alignment requirements unsigned int FixedAddress : 1; // Allocate memory at specified virtual address. Fail if address is not free. unsigned int NoNUMABind: 1; // Don't bind system memory to a specific NUMA node unsigned int Uncached: 1; // Caching flag for fine-grained memory on A+A HW platform unsigned int NoAddress: 1; // only do vram allocation, return a handle, not allocate virtual address. unsigned int OnlyAddress: 1; // only do virtal address allocation without vram allocation. unsigned int Reserved: 12; } ui32; HSAuint32 Value; }; } HsaMemFlags; typedef struct _HsaMemMapFlags { union { struct { unsigned int Reserved1 : 1; // unsigned int CachePolicy : 2; // see HSA_CACHING_TYPE unsigned int ReadOnly : 1; // memory is not modified while mapped // allows migration scale-out unsigned int PageSize : 2; // see HSA_PAGE_SIZE, hint to use // this page size if possible and // smaller than default unsigned int HostAccess : 1; // default = 0: GPU access only unsigned int Migrate : 1; // Hint: Allows migration to local mem // of mapped GPU(s), instead of mapping // physical location unsigned int Probe : 1; // default = 0: Indicates that a range // will be mapped by the process soon, // but does not initiate a map operation // may trigger eviction of nonessential // data from the memory, reduces latency // “cleanup hint” only, may be ignored unsigned int Reserved : 23; } ui32; HSAuint32 Value; }; } HsaMemMapFlags; typedef struct _HsaGraphicsResourceInfo { void *MemoryAddress; // For use in hsaKmtMapMemoryToGPU(Nodes) HSAuint64 SizeInBytes; // Buffer size const void *Metadata; // Pointer to metadata owned by Thunk HSAuint32 MetadataSizeInBytes; // Size of metadata HSAuint32 NodeId; // GPU exported the buffer } HsaGraphicsResourceInfo; typedef enum _HSA_CACHING_TYPE { HSA_CACHING_CACHED = 0, HSA_CACHING_NONCACHED = 1, HSA_CACHING_WRITECOMBINED = 2, HSA_CACHING_RESERVED = 3, HSA_CACHING_NUM_CACHING, HSA_CACHING_SIZE = 0xFFFFFFFF } HSA_CACHING_TYPE; typedef enum _HSA_PAGE_SIZE { HSA_PAGE_SIZE_4KB = 0, HSA_PAGE_SIZE_64KB = 1, //64KB pages, not generally available in systems HSA_PAGE_SIZE_2MB = 2, HSA_PAGE_SIZE_1GB = 3, //1GB pages, not generally available in systems } HSA_PAGE_SIZE; typedef enum _HSA_DEVICE { HSA_DEVICE_CPU = 0, HSA_DEVICE_GPU = 1, MAX_HSA_DEVICE = 2 } HSA_DEVICE; typedef enum _HSA_QUEUE_PRIORITY { HSA_QUEUE_PRIORITY_MINIMUM = -3, HSA_QUEUE_PRIORITY_LOW = -2, HSA_QUEUE_PRIORITY_BELOW_NORMAL = -1, HSA_QUEUE_PRIORITY_NORMAL = 0, HSA_QUEUE_PRIORITY_ABOVE_NORMAL = 1, HSA_QUEUE_PRIORITY_HIGH = 2, HSA_QUEUE_PRIORITY_MAXIMUM = 3, HSA_QUEUE_PRIORITY_NUM_PRIORITY, HSA_QUEUE_PRIORITY_SIZE = 0xFFFFFFFF } HSA_QUEUE_PRIORITY; typedef enum _HSA_QUEUE_TYPE { HSA_QUEUE_COMPUTE = 1, // AMD PM4 compatible Compute Queue HSA_QUEUE_SDMA = 2, // PCIe optimized SDMA Queue, used for data transport and format conversion (e.g. (de-)tiling, etc). HSA_QUEUE_MULTIMEDIA_DECODE = 3, // reserved, for HSA multimedia decode queue HSA_QUEUE_MULTIMEDIA_ENCODE = 4, // reserved, for HSA multimedia encode queue HSA_QUEUE_SDMA_XGMI = 5, // XGMI optimized SDMA Queue // the following values indicate a queue type permitted to reference OS graphics // resources through the interoperation API. See [5] "HSA Graphics Interoperation // specification" for more details on use of such resources. HSA_QUEUE_COMPUTE_OS = 11, // AMD PM4 compatible Compute Queue HSA_QUEUE_SDMA_OS = 12, // SDMA Queue, used for data transport and format conversion (e.g. (de-)tiling, etc). HSA_QUEUE_MULTIMEDIA_DECODE_OS = 13, // reserved, for HSA multimedia decode queue HSA_QUEUE_MULTIMEDIA_ENCODE_OS = 14, // reserved, for HSA multimedia encode queue HSA_QUEUE_COMPUTE_AQL = 21, // HSA AQL packet compatible Compute Queue HSA_QUEUE_DMA_AQL = 22, // HSA AQL packet compatible DMA Queue HSA_QUEUE_DMA_AQL_XGMI = 23, // HSA AQL packet compatible XGMI optimized DMA Queue // more types in the future HSA_QUEUE_TYPE_SIZE = 0xFFFFFFFF //aligns to 32bit enum } HSA_QUEUE_TYPE; /** The user context save area is page aligned. The HsaUserContextSaveAreaHeader header starts at offset 0. Space for a user space copy of the control stack comes next and is immediately followed by the user space wave save state. The start of the user space wave save state is page aligned. The debugger reserved area comes next and is 64 byte aligned. The user context save area is valid for the duration that the associated queue exists. When a context save occurs, the HsaUserContextSaveAreaHeader header will be updated with information about the context save. The context save area is not modified by any other operation, including a context resume. */ typedef struct { HSAuint32 ControlStackOffset; // Byte offset from start of user context // save area to the last saved top (lowest // address) of control stack data. Must be // 4 byte aligned. HSAuint32 ControlStackSize; // Byte size of the last saved control stack // data. Must be 4 byte aligned. HSAuint32 WaveStateOffset; // Byte offset from start of user context save // area to the last saved base (lowest address) // of wave state data. Must be 4 byte aligned. HSAuint32 WaveStateSize; // Byte size of the last saved wave state data. // Must be 4 byte aligned. HSAuint32 DebugOffset; // Byte offset from start of the user context // save area to the memory reserved for the // debugger. Must be 64 byte aligned. HSAuint32 DebugSize; // Byte size of the memory reserved for the // debugger. Must be 64 byte aligned. volatile HSAint64 *ErrorReason; // Address of the HSA signal payload for // reporting the error reason bitmask. // Must be 4 byte aligned. HSAuint32 ErrorEventId; // Event ID used for exception signalling. // Must be 4 byte aligned. HSAuint32 Reserved1; } HsaUserContextSaveAreaHeader; typedef struct { HSAuint32 QueueDetailError; // HW specific queue error state HSAuint32 QueueTypeExtended; // HW specific queue type info. // 0 = no information HSAuint32 NumCUAssigned; // size of *CUMaskInfo bit array, Multiple // of 32, 0 = no information HSAuint32* CUMaskInfo; // runtime/system CU assignment for realtime // queue & reserved CU priority. Ptr to // bit-array, each bit represents one CU. // NULL = no information HSAuint32* UserContextSaveArea; // reference to user space context save area HSAuint64 SaveAreaSizeInBytes; // Must be 4-Byte aligned HSAuint32* ControlStackTop; // ptr to the TOS HSAuint64 ControlStackUsedInBytes; // Must be 4-Byte aligned HsaUserContextSaveAreaHeader *SaveAreaHeader; HSAuint64 Reserved2; // runtime/system CU assignment } HsaQueueInfo; typedef struct _HsaQueueResource { HSA_QUEUEID QueueId; /** queue ID */ /** Doorbell address to notify HW of a new dispatch */ union { HSAuint32* Queue_DoorBell; HSAuint64* Queue_DoorBell_aql; HSAuint64 QueueDoorBell; }; /** virtual address to notify HW of queue write ptr value */ union { HSAuint32* Queue_write_ptr; HSAuint64* Queue_write_ptr_aql; HSAuint64 QueueWptrValue; }; /** virtual address updated by HW to indicate current read location */ union { HSAuint32* Queue_read_ptr; HSAuint64* Queue_read_ptr_aql; HSAuint64 QueueRptrValue; }; volatile HSAint64* ErrorReason; /** exception bits signal payload */ } HsaQueueResource; //TEMPORARY structure definition - to be used only on "Triniti + Southern Islands" platform typedef struct _HsaQueueReport { HSAuint32 VMID; //Required on SI to dispatch IB in primary ring void* QueueAddress; //virtual address of UM mapped compute ring HSAuint64 QueueSize; //size of the UM mapped compute ring } HsaQueueReport; typedef enum _HSA_DBG_WAVEOP { HSA_DBG_WAVEOP_HALT = 1, //Halts a wavefront HSA_DBG_WAVEOP_RESUME = 2, //Resumes a wavefront HSA_DBG_WAVEOP_KILL = 3, //Kills a wavefront HSA_DBG_WAVEOP_DEBUG = 4, //Causes wavefront to enter debug mode HSA_DBG_WAVEOP_TRAP = 5, //Causes wavefront to take a trap HSA_DBG_NUM_WAVEOP = 5, HSA_DBG_MAX_WAVEOP = 0xFFFFFFFF } HSA_DBG_WAVEOP; typedef enum _HSA_DBG_WAVEMODE { HSA_DBG_WAVEMODE_SINGLE = 0, //send command to a single wave //Broadcast to all wavefronts of all processes is not supported for HSA user mode HSA_DBG_WAVEMODE_BROADCAST_PROCESS = 2, //send to waves within current process HSA_DBG_WAVEMODE_BROADCAST_PROCESS_CU = 3, //send to waves within current process on CU HSA_DBG_NUM_WAVEMODE = 3, HSA_DBG_MAX_WAVEMODE = 0xFFFFFFFF } HSA_DBG_WAVEMODE; typedef enum _HSA_DBG_WAVEMSG_TYPE { HSA_DBG_WAVEMSG_AUTO = 0, HSA_DBG_WAVEMSG_USER = 1, HSA_DBG_WAVEMSG_ERROR = 2, HSA_DBG_NUM_WAVEMSG, HSA_DBG_MAX_WAVEMSG = 0xFFFFFFFF } HSA_DBG_WAVEMSG_TYPE; typedef enum _HSA_DBG_WATCH_MODE { HSA_DBG_WATCH_READ = 0, //Read operations only HSA_DBG_WATCH_NONREAD = 1, //Write or Atomic operations only HSA_DBG_WATCH_ATOMIC = 2, //Atomic Operations only HSA_DBG_WATCH_ALL = 3, //Read, Write or Atomic operations HSA_DBG_WATCH_NUM } HSA_DBG_WATCH_MODE; typedef enum _HSA_DBG_TRAP_OVERRIDE { HSA_DBG_TRAP_OVERRIDE_OR = 0, // Bitwise OR exception mask with HSA_DBG_TRAP_MASK HSA_DBG_TRAP_OVERRIDE_REPLACE = 1, // Replace exception mask with HSA_DBG_TRAP_MASK HSA_DBG_TRAP_OVERRIDE_NUM } HSA_DBG_TRAP_OVERRIDE; typedef enum _HSA_DBG_TRAP_MASK { HSA_DBG_TRAP_MASK_FP_INVALID = 1, // Floating point invalid operation HSA_DBG_TRAP_MASK_FP_INPUT_DENOMAL = 2, // Floating point input denormal HSA_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO = 4, // Floating point divide by zero HSA_DBG_TRAP_MASK_FP_OVERFLOW = 8, // Floating point overflow HSA_DBG_TRAP_MASK_FP_UNDERFLOW = 16, // Floating point underflow HSA_DBG_TRAP_MASK_FP_INEXACT = 32, // Floating point inexact HSA_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO = 64, // Integer divide by zero HSA_DBG_TRAP_MASK_DBG_ADDRESS_WATCH = 128, // Debug address watch HSA_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION = 256 // Memory violation } HSA_DBG_TRAP_MASK; typedef enum _HSA_DBG_TRAP_EXCEPTION_CODE { HSA_DBG_EC_NONE = 0, /* per queue */ HSA_DBG_EC_QUEUE_WAVE_ABORT = 1, HSA_DBG_EC_QUEUE_WAVE_TRAP = 2, HSA_DBG_EC_QUEUE_WAVE_MATH_ERROR = 3, HSA_DBG_EC_QUEUE_WAVE_ILLEGAL_INSTRUCTION = 4, HSA_DBG_EC_QUEUE_WAVE_MEMORY_VIOLATION = 5, HSA_DBG_EC_QUEUE_WAVE_APERTURE_VIOLATION = 6, HSA_DBG_EC_QUEUE_PACKET_DISPATCH_DIM_INVALID = 16, HSA_DBG_EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID = 17, HSA_DBG_EC_QUEUE_PACKET_DISPATCH_CODE_INVALID = 18, HSA_DBG_EC_QUEUE_PACKET_RESERVED = 19, HSA_DBG_EC_QUEUE_PACKET_UNSUPPORTED = 20, HSA_DBG_EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID = 21, HSA_DBG_EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID = 22, HSA_DBG_EC_QUEUE_PACKET_VENDOR_UNSUPPORTED = 23, HSA_DBG_EC_QUEUE_PREEMPTION_ERROR = 30, HSA_DBG_EC_QUEUE_NEW = 31, /* per device */ HSA_DBG_EC_DEVICE_QUEUE_DELETE = 32, HSA_DBG_EC_DEVICE_MEMORY_VIOLATION = 33, HSA_DBG_EC_DEVICE_RAS_ERROR = 34, HSA_DBG_EC_DEVICE_FATAL_HALT = 35, HSA_DBG_EC_DEVICE_NEW = 36, /* per process */ HSA_DBG_EC_PROCESS_RUNTIME = 48, HSA_DBG_EC_PROCESS_DEVICE_REMOVE = 49, HSA_DBG_EC_MAX } HSA_DBG_TRAP_EXCEPTION_CODE; /* Mask generated by ecode defined in enum above. */ #define HSA_EC_MASK(ecode) (1ULL << (ecode - 1)) typedef enum _HSA_DBG_WAVE_LAUNCH_MODE { HSA_DBG_WAVE_LAUNCH_MODE_NORMAL = 0, // Wavefront launched normally. HSA_DBG_WAVE_LAUNCH_MODE_HALT = 1, // Wavefront launched in halted mode. HSA_DBG_WAVE_LAUNCH_MODE_KILL = 2, // Wavefront is launched but immediately // terminated before executing any instructions. HSA_DBG_WAVE_LAUNCH_MODE_SINGLE_STEP = 3, // Wavefront is launched in single step (debug) // mode. If debug trap is enabled by // hsaKmtDbgEnableDebugTrap() then causes a // trap after executing each instruction, // otherwise behaves the same as // HSA_DBG_WAVE_LAUNCH_MODE_NORMAL. HSA_DBG_WAVE_LAUNCH_MODE_DISABLE = 4, // Disable launching any new waves. HSA_DBG_WAVE_LAUNCH_MODE_NUM } HSA_DBG_WAVE_LAUNCH_MODE; /** * There are no flags currently defined. */ typedef enum HSA_DBG_NODE_CONTROL { HSA_DBG_NODE_CONTROL_FLAG_MAX = 0x01 } HSA_DBG_NODE_CONTROL; #define HSA_RUNTIME_ENABLE_CAPS_SUPPORTS_CORE_DUMP_MASK 0x80000000 //This structure is hardware specific and may change in the future typedef struct _HsaDbgWaveMsgAMDGen2 { HSAuint32 Value; HSAuint32 Reserved2; } HsaDbgWaveMsgAMDGen2; typedef union _HsaDbgWaveMessageAMD { HsaDbgWaveMsgAMDGen2 WaveMsgInfoGen2; //for future HsaDbgWaveMsgAMDGen3; } HsaDbgWaveMessageAMD; typedef struct _HsaDbgWaveMessage { void* MemoryVA; // ptr to associated host-accessible data HsaDbgWaveMessageAMD DbgWaveMsg; } HsaDbgWaveMessage; // // HSA sync primitive, Event and HW Exception notification API definitions // The API functions allow the runtime to define a so-called sync-primitive, a SW object // combining a user-mode provided "syncvar" and a scheduler event that can be signaled // through a defined GPU interrupt. A syncvar is a process virtual memory location of // a certain size that can be accessed by CPU and GPU shader code within the process to set // and query the content within that memory. The definition of the content is determined by // the HSA runtime and potentially GPU shader code interfacing with the HSA runtime. // The syncvar values may be commonly written through an PM4 WRITE_DATA packet in the // user mode instruction stream. // The OS scheduler event is typically associated and signaled by an interrupt issued by // the GPU, but other HSA system interrupt conditions from other HW (e.g. IOMMUv2) may be // surfaced by the KFD by this mechanism, too. // // these are the new definitions for events typedef enum _HSA_EVENTTYPE { HSA_EVENTTYPE_SIGNAL = 0, //user-mode generated GPU signal HSA_EVENTTYPE_NODECHANGE = 1, //HSA node change (attach/detach) HSA_EVENTTYPE_DEVICESTATECHANGE = 2, //HSA device state change( start/stop ) HSA_EVENTTYPE_HW_EXCEPTION = 3, //GPU shader exception event HSA_EVENTTYPE_SYSTEM_EVENT = 4, //GPU SYSCALL with parameter info HSA_EVENTTYPE_DEBUG_EVENT = 5, //GPU signal for debugging HSA_EVENTTYPE_PROFILE_EVENT = 6, //GPU signal for profiling HSA_EVENTTYPE_QUEUE_EVENT = 7, //GPU signal queue idle state (EOP pm4) HSA_EVENTTYPE_MEMORY = 8, //GPU signal for signaling memory access faults and memory subsystem issues //... HSA_EVENTTYPE_MAXID, HSA_EVENTTYPE_TYPE_SIZE = 0xFFFFFFFF } HSA_EVENTTYPE; // // Definitions for types of pending debug events // typedef enum _HSA_DEBUG_EVENT_TYPE { HSA_DEBUG_EVENT_TYPE_NONE = 0, HSA_DEBUG_EVENT_TYPE_TRAP = 1, HSA_DEBUG_EVENT_TYPE_VMFAULT = 2, HSA_DEBUG_EVENT_TYPE_TRAP_VMFAULT = 3 } HSA_DEBUG_EVENT_TYPE; typedef HSAuint32 HSA_EVENTID; // // Subdefinitions for various event types: Syncvar // typedef struct _HsaSyncVar { union { void* UserData; //pointer to user mode data HSAuint64 UserDataPtrValue; //64bit compatibility of value } SyncVar; HSAuint64 SyncVarSize; } HsaSyncVar; // // Subdefinitions for various event types: NodeChange // typedef enum _HSA_EVENTTYPE_NODECHANGE_FLAGS { HSA_EVENTTYPE_NODECHANGE_ADD = 0, HSA_EVENTTYPE_NODECHANGE_REMOVE = 1, HSA_EVENTTYPE_NODECHANGE_SIZE = 0xFFFFFFFF } HSA_EVENTTYPE_NODECHANGE_FLAGS; typedef struct _HsaNodeChange { HSA_EVENTTYPE_NODECHANGE_FLAGS Flags; // HSA node added/removed on the platform } HsaNodeChange; // // Sub-definitions for various event types: DeviceStateChange // typedef enum _HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS { HSA_EVENTTYPE_DEVICESTATUSCHANGE_START = 0, //device started (and available) HSA_EVENTTYPE_DEVICESTATUSCHANGE_STOP = 1, //device stopped (i.e. unavailable) HSA_EVENTTYPE_DEVICESTATUSCHANGE_SIZE = 0xFFFFFFFF } HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS; typedef struct _HsaDeviceStateChange { HSAuint32 NodeId; // F-NUMA node that contains the device HSA_DEVICE Device; // device type: GPU or CPU HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS Flags; // event flags } HsaDeviceStateChange; // // Sub-definitions for various event types: Memory exception // typedef enum _HSA_EVENTID_MEMORYFLAGS { HSA_EVENTID_MEMORY_RECOVERABLE = 0, //access fault, recoverable after page adjustment HSA_EVENTID_MEMORY_FATAL_PROCESS = 1, //memory access requires process context destruction, unrecoverable HSA_EVENTID_MEMORY_FATAL_VM = 2, //memory access requires all GPU VA context destruction, unrecoverable } HSA_EVENTID_MEMORYFLAGS; typedef struct _HsaAccessAttributeFailure { unsigned int NotPresent : 1; // Page not present or supervisor privilege unsigned int ReadOnly : 1; // Write access to a read-only page unsigned int NoExecute : 1; // Execute access to a page marked NX unsigned int GpuAccess : 1; // Host access only unsigned int ECC : 1; // RAS ECC failure (notification of DRAM ECC - non-recoverable - error, if supported by HW) unsigned int Imprecise : 1; // Can't determine the exact fault address unsigned int ErrorType : 3; // Indicates RAS errors or other errors causing the access to GPU to fail // 0 = no RAS error, 1 = ECC_SRAM, 2 = Link_SYNFLOOD (poison), 3 = GPU hang (not attributable to a specific cause), other values reserved unsigned int Reserved : 23; // must be 0 } HsaAccessAttributeFailure; // data associated with HSA_EVENTID_MEMORY typedef struct _HsaMemoryAccessFault { HSAuint32 NodeId; // H-NUMA node that contains the device where the memory access occurred HSAuint64 VirtualAddress; // virtual address this occurred on HsaAccessAttributeFailure Failure; // failure attribute HSA_EVENTID_MEMORYFLAGS Flags; // event flags } HsaMemoryAccessFault; typedef struct _HsaEventData { HSA_EVENTTYPE EventType; //event type union { // return data associated with HSA_EVENTTYPE_SIGNAL and other events HsaSyncVar SyncVar; // data associated with HSA_EVENTTYPE_NODE_CHANGE HsaNodeChange NodeChangeState; // data associated with HSA_EVENTTYPE_DEVICE_STATE_CHANGE HsaDeviceStateChange DeviceState; // data associated with HSA_EVENTTYPE_MEMORY HsaMemoryAccessFault MemoryAccessFault; } EventData; // the following data entries are internal to the KFD & thunk itself. HSAuint64 HWData1; // internal thunk store for Event data (OsEventHandle) HSAuint64 HWData2; // internal thunk store for Event data (HWAddress) HSAuint32 HWData3; // internal thunk store for Event data (HWData) } HsaEventData; typedef struct _HsaEventDescriptor { HSA_EVENTTYPE EventType; // event type to allocate HSAuint32 NodeId; // H-NUMA node containing GPU device that is event source HsaSyncVar SyncVar; // pointer to user mode syncvar data, syncvar->UserDataPtrValue may be NULL } HsaEventDescriptor; typedef struct _HsaEvent { HSA_EVENTID EventId; HsaEventData EventData; } HsaEvent; typedef enum _HsaEventTimeout { HSA_EVENTTIMEOUT_IMMEDIATE = 0, HSA_EVENTTIMEOUT_INFINITE = 0xFFFFFFFF } HsaEventTimeOut; typedef struct _HsaClockCounters { HSAuint64 GPUClockCounter; HSAuint64 CPUClockCounter; HSAuint64 SystemClockCounter; HSAuint64 SystemClockFrequencyHz; } HsaClockCounters; #ifndef DEFINE_GUID typedef struct _HSA_UUID { HSAuint32 Data1; HSAuint16 Data2; HSAuint16 Data3; HSAuint8 Data4[8]; } HSA_UUID; #define HSA_DEFINE_UUID(name, dw, w1, w2, b1, b2, b3, b4, b5, b6, b7, b8) \ static const HSA_UUID name = {dw, w1, w2, {b1, b2, b3, b4, b5, b6, b7, b8}} #else #define HSA_UUID GUID #define HSA_DEFINE_UUID DEFINE_GUID #endif // HSA_UUID that identifies the GPU ColorBuffer (CB) block // {9ba429c6-af2d-4b38-b349-157271beac6a} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_CB, 0x9ba429c6, 0xaf2d, 0x4b38, 0xb3, 0x49, 0x15, 0x72, 0x71, 0xbe, 0xac, 0x6a); // HSA_UUID that identifies the GPU (CPF) block // {2b0ad2b5-1c43-4f46-a7bc-e119411ea6c9} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_CPF, 0x2b0ad2b5, 0x1c43, 0x4f46, 0xa7, 0xbc, 0xe1, 0x19, 0x41, 0x1e, 0xa6, 0xc9); // HSA_UUID that identifies the GPU (CPG) block // {590ec94d-20f0-448f-8dff-316c679de7ff HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_CPG, 0x590ec94d, 0x20f0, 0x448f, 0x8d, 0xff, 0x31, 0x6c, 0x67, 0x9d, 0xe7, 0xff); // HSA_UUID that identifies the GPU (DB) block // {3d1a47fc-0013-4ed4-8306-822ca0b7a6c2 HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_DB, 0x3d1a47fc, 0x0013, 0x4ed4, 0x83, 0x06, 0x82, 0x2c, 0xa0, 0xb7, 0xa6, 0xc2); // HSA_UUID that identifies the GPU (GDS) block // {f59276ec-2526-4bf8-8ec0-118f77700dc9 HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_GDS, 0xf59276ec, 0x2526, 0x4bf8, 0x8e, 0xc0, 0x11, 0x8f, 0x77, 0x70, 0x0d, 0xc9); // HSA_UUID that identifies the GPU (GRBM) block // {8f00933c-c33d-4801-97b7-7007f78573ad HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_GRBM, 0x8f00933c, 0xc33d, 0x4801, 0x97, 0xb7, 0x70, 0x07, 0xf7, 0x85, 0x73, 0xad); // HSA_UUID that identifies the GPU (GRBMSE) block // {34ebd8d7-7c8b-4d15-88fa-0e4e4af59ac1 HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_GRBMSE, 0x34ebd8d7, 0x7c8b, 0x4d15, 0x88, 0xfa, 0x0e, 0x4e, 0x4a, 0xf5, 0x9a, 0xc1); // HSA_UUID that identifies the GPU (IA) block // {34276944-4264-4fcd-9d6e-ae264582ec51 HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_IA, 0x34276944, 0x4264, 0x4fcd, 0x9d, 0x6e, 0xae, 0x26, 0x45, 0x82, 0xec, 0x51); // HSA_UUID that identifies the GPU Memory Controller (MC) block // {13900B57-4956-4D98-81D0-68521937F59C HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_MC, 0x13900b57, 0x4956, 0x4d98, 0x81, 0xd0, 0x68, 0x52, 0x19, 0x37, 0xf5, 0x9c); // HSA_UUID that identifies the GPU (PASC) block // {b0e7fb5d-0efc-4744-b516-5d23dc1fd56c HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_PASC, 0xb0e7fb5d, 0x0efc, 0x4744, 0xb5, 0x16, 0x5d, 0x23, 0xdc, 0x1f, 0xd5, 0x6c); // HSA_UUID that identifies the GPU (PASU) block // {9a152b6a-1fad-45f2-a5bf-f163826bd0cd HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_PASU, 0x9a152b6a, 0x1fad, 0x45f2, 0xa5, 0xbf, 0xf1, 0x63, 0x82, 0x6b, 0xd0, 0xcd); // HSA_UUID that identifies the GPU (SPI) block // {eda81044-d62c-47eb-af89-4f6fbf3b38e0 HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_SPI, 0xeda81044, 0xd62c, 0x47eb, 0xaf, 0x89, 0x4f, 0x6f, 0xbf, 0x3b, 0x38, 0xe0); // HSA_UUID that identifies the GPU (SRBM) block // {9f8040e0-6830-4019-acc8-463c9e445b89 HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_SRBM, 0x9f8040e0, 0x6830, 0x4019, 0xac, 0xc8, 0x46, 0x3c, 0x9e, 0x44, 0x5b, 0x89); // GUID that identifies the GPU Shader Sequencer (SQ) block // {B5C396B6-D310-47E4-86FC-5CC3043AF508} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_SQ, 0xb5c396b6, 0xd310, 0x47e4, 0x86, 0xfc, 0x5c, 0xc3, 0x4, 0x3a, 0xf5, 0x8); // HSA_UUID that identifies the GPU (SX) block // {bdb8d737-43cc-4162-be52-51cfb847beaf} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_SX, 0xbdb8d737, 0x43cc, 0x4162, 0xbe, 0x52, 0x51, 0xcf, 0xb8, 0x47, 0xbe, 0xaf); // HSA_UUID that identifies the GPU (TA) block // {c01ee43d-ad92-44b1-8ab9-be5e696ceea7} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_TA, 0xc01ee43d, 0xad92, 0x44b1, 0x8a, 0xb9, 0xbe, 0x5e, 0x69, 0x6c, 0xee, 0xa7); // HSA_UUID that identifies the GPU TextureCache (TCA) block // {333e393f-e147-4f49-a6d1-60914c7086b0} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_TCA, 0x333e393f, 0xe147, 0x4f49, 0xa6, 0xd1,0x60, 0x91, 0x4c, 0x70, 0x86, 0xb0); // HSA_UUID that identifies the GPU TextureCache (TCC) block // {848ce855-d805-4566-a8ab-73e884cc6bff} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_TCC, 0x848ce855, 0xd805, 0x4566, 0xa8, 0xab, 0x73, 0xe8, 0x84, 0xcc, 0x6b, 0xff); // HSA_UUID that identifies the GPU (TCP) block // {e10a013b-17d4-4bf5-b089-429591059b60} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_TCP, 0xe10a013b, 0x17d4, 0x4bf5, 0xb0, 0x89, 0x42, 0x95, 0x91, 0x05, 0x9b, 0x60); // HSA_UUID that identifies the GPU (TCS) block // {4126245c-4d96-4d1a-8aed-a939d4cc8ec9} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_TCS, 0x4126245c, 0x4d96, 0x4d1a, 0x8a, 0xed, 0xa9, 0x39, 0xd4, 0xcc, 0x8e, 0xc9); // HSA_UUID that identifies the GPU (TD) block // {7d7c0fe4-fe41-4fea-92c9-4544d7706dc6} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_TD, 0x7d7c0fe4, 0xfe41, 0x4fea, 0x92, 0xc9, 0x45, 0x44, 0xd7, 0x70, 0x6d, 0xc6); // HSA_UUID that identifies the GPU (VGT) block // {0b6a8cb7-7a01-409f-a22c-3014854f1359} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_VGT, 0x0b6a8cb7, 0x7a01, 0x409f, 0xa2, 0x2c, 0x30, 0x14, 0x85, 0x4f, 0x13, 0x59); // HSA_UUID that identifies the GPU (WD) block // {0e176789-46ed-4b02-972a-916d2fac244a} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_WD, 0x0e176789, 0x46ed, 0x4b02, 0x97, 0x2a, 0x91, 0x6d, 0x2f, 0xac, 0x24, 0x4a); // GUID that identifies the IMOMMUv2 HW device // {80969879-B0F6-4BE6-97F6-6A6300F5101D} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_IOMMUV2, 0x80969879, 0xb0f6, 0x4be6, 0x97, 0xf6, 0x6a, 0x63, 0x0, 0xf5, 0x10, 0x1d); // GUID that identifies the KFD // {EA9B5AE1-6C3F-44B3-8954-DAF07565A90A} HSA_DEFINE_UUID(HSA_PROFILEBLOCK_AMD_KERNEL_DRIVER, 0xea9b5ae1, 0x6c3f, 0x44b3, 0x89, 0x54, 0xda, 0xf0, 0x75, 0x65, 0xa9, 0xa); typedef enum _HSA_PROFILE_TYPE { HSA_PROFILE_TYPE_PRIVILEGED_IMMEDIATE = 0, //immediate access counter (KFD access only) HSA_PROFILE_TYPE_PRIVILEGED_STREAMING = 1, //streaming counter, HW continuously //writes to memory on updates (KFD access only) HSA_PROFILE_TYPE_NONPRIV_IMMEDIATE = 2, //user-queue accessible counter HSA_PROFILE_TYPE_NONPRIV_STREAMING = 3, //user-queue accessible counter //... HSA_PROFILE_TYPE_NUM, HSA_PROFILE_TYPE_SIZE = 0xFFFFFFFF // In order to align to 32-bit value } HSA_PROFILE_TYPE; typedef struct _HsaCounterFlags { union { struct { unsigned int Global : 1; // counter is global // (not tied to VMID/WAVE/CU, ...) unsigned int Resettable : 1; // counter can be reset by SW // (always to 0?) unsigned int ReadOnly : 1; // counter is read-only // (but may be reset, if indicated) unsigned int Stream : 1; // counter has streaming capability // (after trigger, updates buffer) unsigned int Reserved : 28; } ui32; HSAuint32 Value; }; } HsaCounterFlags; typedef struct _HsaCounter { HSA_PROFILE_TYPE Type; // specifies the counter type HSAuint64 CounterId; // indicates counter register offset HSAuint32 CounterSizeInBits; // indicates relevant counter bits HSAuint64 CounterMask; // bitmask for counter value (if applicable) HsaCounterFlags Flags; // Property flags (see above) HSAuint32 BlockIndex; // identifies block the counter belongs to, // value may be 0 to NumBlocks } HsaCounter; typedef struct _HsaCounterBlockProperties { HSA_UUID BlockId; // specifies the block location HSAuint32 NumCounters; // How many counters are available? // (sizes Counters[] array below) HSAuint32 NumConcurrent; // How many counter slots are available // in block? HsaCounter Counters[1]; // Start of counter array // (NumCounters elements total) } HsaCounterBlockProperties; typedef struct _HsaCounterProperties { HSAuint32 NumBlocks; // How many profilable block are available? // (sizes Blocks[] array below) HSAuint32 NumConcurrent; // How many blocks slots can be queried // concurrently by HW? HsaCounterBlockProperties Blocks[1]; // Start of block array // (NumBlocks elements total) } HsaCounterProperties; typedef HSAuint64 HSATraceId; typedef struct _HsaPmcTraceRoot { HSAuint64 TraceBufferMinSizeBytes;// (page aligned) HSAuint32 NumberOfPasses; HSATraceId TraceId; } HsaPmcTraceRoot; typedef struct _HsaGpuTileConfig { HSAuint32 *TileConfig; HSAuint32 *MacroTileConfig; HSAuint32 NumTileConfigs; HSAuint32 NumMacroTileConfigs; HSAuint32 GbAddrConfig; HSAuint32 NumBanks; HSAuint32 NumRanks; /* 9 dwords on 64-bit system */ HSAuint32 Reserved[7]; /* Round up to 16 dwords for future extension */ } HsaGpuTileConfig; typedef enum _HSA_POINTER_TYPE { HSA_POINTER_UNKNOWN = 0, HSA_POINTER_ALLOCATED = 1, // Allocated with hsaKmtAllocMemory (except scratch) HSA_POINTER_REGISTERED_USER = 2, // Registered user pointer HSA_POINTER_REGISTERED_GRAPHICS = 3, // Registered graphics buffer HSA_POINTER_REGISTERED_SHARED = 4, // Registered shared buffer (IPC) // (hsaKmtRegisterGraphicsToNodes) HSA_POINTER_RESERVED_ADDR = 5 // address-only reservation VA } HSA_POINTER_TYPE; typedef struct _HsaPointerInfo { HSA_POINTER_TYPE Type; // Pointer type HSAuint32 Node; // Node where the memory is located HsaMemFlags MemFlags; // HsaMemFlags used to alloc memory void *CPUAddress; // Start address for CPU access HSAuint64 GPUAddress; // Start address for GPU access HSAuint64 SizeInBytes; // Size in bytes HSAuint32 NRegisteredNodes; // Number of nodes the memory is registered to HSAuint32 NMappedNodes; // Number of nodes the memory is mapped to const HSAuint32 *RegisteredNodes; // Array of registered nodes const HSAuint32 *MappedNodes; // Array of mapped nodes void *UserData; // User data associated with the memory } HsaPointerInfo; typedef HSAuint32 HsaSharedMemoryHandle[8]; typedef struct _HsaMemoryRange { void *MemoryAddress; // Pointer to GPU memory HSAuint64 SizeInBytes; // Size of above memory } HsaMemoryRange; typedef enum _HSA_SVM_FLAGS { HSA_SVM_FLAG_HOST_ACCESS = 0x00000001, // Guarantee host access to memory HSA_SVM_FLAG_COHERENT = 0x00000002, // Fine grained coherency between all devices with access HSA_SVM_FLAG_HIVE_LOCAL = 0x00000004, // Use any GPU in same hive as preferred device HSA_SVM_FLAG_GPU_RO = 0x00000008, // GPUs only read, allows replication HSA_SVM_FLAG_GPU_EXEC = 0x00000010, // Allow execution on GPU HSA_SVM_FLAG_GPU_READ_MOSTLY = 0x00000020, // GPUs mostly read, may allow similar optimizations as RO, but writes fault HSA_SVM_FLAG_GPU_ALWAYS_MAPPED = 0x00000040, // Keep GPU memory mapping always valid as if XNACK is disable } HSA_SVM_FLAGS; typedef enum _HSA_SVM_ATTR_TYPE { HSA_SVM_ATTR_PREFERRED_LOC, // gpuid of the preferred location, 0 for // system memory, INVALID_NODEID for // "don't care" HSA_SVM_ATTR_PREFETCH_LOC, // gpuid of the prefetch location, 0 for // system memory. Setting this triggers an // immediate prefetch (migration) HSA_SVM_ATTR_ACCESS, HSA_SVM_ATTR_ACCESS_IN_PLACE, HSA_SVM_ATTR_NO_ACCESS, // specify memory access for the gpuid given // by the attribute value HSA_SVM_ATTR_SET_FLAGS, // bitmask of flags to set (see HSA_SVM_FLAGS) HSA_SVM_ATTR_CLR_FLAGS, // bitmask of flags to clear HSA_SVM_ATTR_GRANULARITY // migration granularity (log2 num pages) } HSA_SVM_ATTR_TYPE; typedef struct _HSA_SVM_ATTRIBUTE { HSAuint32 type; // attribute type (see enum HSA_SVM_ATTR_TYPE) HSAuint32 value; // attribute value } HSA_SVM_ATTRIBUTE; typedef enum _HSA_SMI_EVENT { HSA_SMI_EVENT_NONE = 0, /* not used */ HSA_SMI_EVENT_VMFAULT = 1, /* event start counting at 1 */ HSA_SMI_EVENT_THERMAL_THROTTLE = 2, HSA_SMI_EVENT_GPU_PRE_RESET = 3, HSA_SMI_EVENT_GPU_POST_RESET = 4, HSA_SMI_EVENT_MIGRATE_START = 5, HSA_SMI_EVENT_MIGRATE_END = 6, HSA_SMI_EVENT_PAGE_FAULT_START = 7, HSA_SMI_EVENT_PAGE_FAULT_END = 8, HSA_SMI_EVENT_QUEUE_EVICTION = 9, HSA_SMI_EVENT_QUEUE_RESTORE = 10, HSA_SMI_EVENT_UNMAP_FROM_GPU = 11, HSA_SMI_EVENT_INDEX_MAX = 12, /* * max event number, as a flag bit to get events from all processes, * this requires super user permission, otherwise will not be able to * receive event from any process. Without this flag to receive events * from same process. */ HSA_SMI_EVENT_ALL_PROCESS = 64 } HSA_EVENT_TYPE; typedef enum _HSA_MIGRATE_TRIGGERS { HSA_MIGRATE_TRIGGER_PREFETCH, HSA_MIGRATE_TRIGGER_PAGEFAULT_GPU, HSA_MIGRATE_TRIGGER_PAGEFAULT_CPU, HSA_MIGRATE_TRIGGER_TTM_EVICTION } HSA_MIGRATE_TRIGGERS; typedef enum _HSA_QUEUE_EVICTION_TRIGGERS { HSA_QUEUE_EVICTION_TRIGGER_SVM, HSA_QUEUE_EVICTION_TRIGGER_USERPTR, HSA_QUEUE_EVICTION_TRIGGER_TTM, HSA_QUEUE_EVICTION_TRIGGER_SUSPEND, HSA_QUEUE_EVICTION_CRIU_CHECKPOINT, HSA_QUEUE_EVICTION_CRIU_RESTORE } HSA_QUEUE_EVICTION_TRIGGERS; typedef enum _HSA_SVM_UNMAP_TRIGGERS { HSA_SVM_UNMAP_TRIGGER_MMU_NOTIFY, HSA_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE, HSA_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU } HSA_SVM_UNMAP_TRIGGERS; #define HSA_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1)) #define HSA_SMI_EVENT_MSG_SIZE 96 typedef void *HsaAMDGPUDeviceHandle; #pragma pack(pop, hsakmttypes_h) #ifdef __cplusplus } //extern "C" #endif #endif //_HSAKMTTYPES_H_ ROCT-Thunk-Interface-rocm-5.7.0/include/linux/000077500000000000000000000000001446477712600210215ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/include/linux/kfd_ioctl.h000066400000000000000000001617041446477712600231410ustar00rootroot00000000000000/* * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef KFD_IOCTL_H_INCLUDED #define KFD_IOCTL_H_INCLUDED #include #include /* * - 1.1 - initial version * - 1.3 - Add SMI events support * - 1.4 - Indicate new SRAM EDC bit in device properties * - 1.5 - Add SVM API * - 1.6 - Query clear flags in SVM get_attr API * - 1.7 - Checkpoint Restore (CRIU) API * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs * - 1.9 - Add available_memory ioctl * - 1.10 - Add SMI profiler event log * - 1.11 - Add unified memory for ctx save/restore area * - 1.12 - Add DMA buf export ioctl * - 1.13 - Add debugger API * - 1.14 - Update kfd_event_data */ #define KFD_IOCTL_MAJOR_VERSION 1 #define KFD_IOCTL_MINOR_VERSION 14 /* * Debug revision change log * * 0.1 - Initial revision * 0.2 - Fix to include querying pending event that is both trap and vmfault * 1.0 - Removed function to set debug data (renumbering functions broke ABI) * 1.1 - Allow attaching to processes that have not opened /dev/kfd yet * 1.2 - Allow flag option to clear queue status on queue suspend * 1.3 - Fix race condition between clear on suspend and trap event handling * 1.4 - Fix bad kfifo free * 1.5 - Fix ABA issue between queue snapshot and suspend * 2.0 - Return number of queues suspended/resumed and mask invalid/error * array slots * 2.1 - Add Set Address Watch, and Clear Address Watch support. * 3.0 - Overhaul set wave launch override API * 3.1 - Add support for GFX10 * 3.2 - Add support for GFX10.3 * 3.3 - Add precise memory operations enable * 4.0 - Remove gpu_id from api * 5.0 - Report exception codes to the debugger * 6.0 - Pass event file descriptor from userspace. * 6.1 - Add KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO. * 6.2 - Add KFD_IOC_DBG_TRAP_DEVICE_SNAPSHOT. * 7.0 - Redefine exception codes * 7.1 - Add KFD_IOC_DBG_TRAP_RUNTIME_ENABLE * 7.2 - Add KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT * 8.0 - Expand runtime information given to the debugger * 8.1 - Allow the debugger to set the exception mask * 9.0 - Handle multiple exceptions from single trap signal * 10.0 - Query debug event returns both queue_id and gpu_id * 10.1 - Add additional debug capability information * 10.2 - Reserved * 10.3 - Pass context_save_restore_area size to user-space */ #define KFD_IOCTL_DBG_MAJOR_VERSION 10 #define KFD_IOCTL_DBG_MINOR_VERSION 3 struct kfd_ioctl_get_version_args { __u32 major_version; /* from KFD */ __u32 minor_version; /* from KFD */ }; /* For kfd_ioctl_create_queue_args.queue_type. */ #define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0 #define KFD_IOC_QUEUE_TYPE_SDMA 0x1 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2 #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3 #define KFD_MAX_QUEUE_PERCENTAGE 100 #define KFD_MAX_QUEUE_PRIORITY 15 struct kfd_ioctl_create_queue_args { __u64 ring_base_address; /* to KFD */ __u64 write_pointer_address; /* from KFD */ __u64 read_pointer_address; /* from KFD */ __u64 doorbell_offset; /* from KFD */ __u32 ring_size; /* to KFD */ __u32 gpu_id; /* to KFD */ __u32 queue_type; /* to KFD */ __u32 queue_percentage; /* to KFD */ __u32 queue_priority; /* to KFD */ __u32 queue_id; /* from KFD */ __u64 eop_buffer_address; /* to KFD */ __u64 eop_buffer_size; /* to KFD */ __u64 ctx_save_restore_address; /* to KFD */ __u32 ctx_save_restore_size; /* to KFD */ __u32 ctl_stack_size; /* to KFD */ }; struct kfd_ioctl_destroy_queue_args { __u32 queue_id; /* to KFD */ __u32 pad; }; struct kfd_ioctl_update_queue_args { __u64 ring_base_address; /* to KFD */ __u32 queue_id; /* to KFD */ __u32 ring_size; /* to KFD */ __u32 queue_percentage; /* to KFD */ __u32 queue_priority; /* to KFD */ }; struct kfd_ioctl_set_cu_mask_args { __u32 queue_id; /* to KFD */ __u32 num_cu_mask; /* to KFD */ __u64 cu_mask_ptr; /* to KFD */ }; struct kfd_ioctl_get_queue_wave_state_args { __u64 ctl_stack_address; /* to KFD */ __u32 ctl_stack_used_size; /* from KFD */ __u32 save_area_used_size; /* from KFD */ __u32 queue_id; /* to KFD */ __u32 pad; }; struct kfd_queue_snapshot_entry { __u64 exception_status; __u64 ring_base_address; __u64 write_pointer_address; __u64 read_pointer_address; __u64 ctx_save_restore_address; __u32 queue_id; __u32 gpu_id; __u32 ring_size; __u32 queue_type; __u32 ctx_save_restore_area_size; __u32 reserved; }; struct kfd_dbg_device_info_entry { __u64 exception_status; __u64 lds_base; __u64 lds_limit; __u64 scratch_base; __u64 scratch_limit; __u64 gpuvm_base; __u64 gpuvm_limit; __u32 gpu_id; __u32 location_id; __u32 vendor_id; __u32 device_id; __u32 revision_id; __u32 subsystem_vendor_id; __u32 subsystem_device_id; __u32 fw_version; __u32 gfx_target_version; __u32 simd_count; __u32 max_waves_per_simd; __u32 array_count; __u32 simd_arrays_per_engine; __u32 num_xcc; __u32 capability; __u32 debug_prop; }; /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ #define KFD_IOC_CACHE_POLICY_COHERENT 0 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 struct kfd_ioctl_set_memory_policy_args { __u64 alternate_aperture_base; /* to KFD */ __u64 alternate_aperture_size; /* to KFD */ __u32 gpu_id; /* to KFD */ __u32 default_policy; /* to KFD */ __u32 alternate_policy; /* to KFD */ __u32 pad; }; /* * All counters are monotonic. They are used for profiling of compute jobs. * The profiling is done by userspace. * * In case of GPU reset, the counter should not be affected. */ struct kfd_ioctl_get_clock_counters_args { __u64 gpu_clock_counter; /* from KFD */ __u64 cpu_clock_counter; /* from KFD */ __u64 system_clock_counter; /* from KFD */ __u64 system_clock_freq; /* from KFD */ __u32 gpu_id; /* to KFD */ __u32 pad; }; struct kfd_process_device_apertures { __u64 lds_base; /* from KFD */ __u64 lds_limit; /* from KFD */ __u64 scratch_base; /* from KFD */ __u64 scratch_limit; /* from KFD */ __u64 gpuvm_base; /* from KFD */ __u64 gpuvm_limit; /* from KFD */ __u32 gpu_id; /* from KFD */ __u32 pad; }; /* * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an * unlimited number of GPUs. */ #define NUM_OF_SUPPORTED_GPUS 7 struct kfd_ioctl_get_process_apertures_args { struct kfd_process_device_apertures process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */ /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */ __u32 num_of_nodes; __u32 pad; }; struct kfd_ioctl_get_process_apertures_new_args { /* User allocated. Pointer to struct kfd_process_device_apertures * filled in by Kernel */ __u64 kfd_process_device_apertures_ptr; /* to KFD - indicates amount of memory present in * kfd_process_device_apertures_ptr * from KFD - Number of entries filled by KFD. */ __u32 num_of_nodes; __u32 pad; }; #define MAX_ALLOWED_NUM_POINTS 100 #define MAX_ALLOWED_AW_BUFF_SIZE 4096 #define MAX_ALLOWED_WAC_BUFF_SIZE 128 struct kfd_ioctl_dbg_register_args { __u32 gpu_id; /* to KFD */ __u32 pad; }; struct kfd_ioctl_dbg_unregister_args { __u32 gpu_id; /* to KFD */ __u32 pad; }; struct kfd_ioctl_dbg_address_watch_args { __u64 content_ptr; /* a pointer to the actual content */ __u32 gpu_id; /* to KFD */ __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ }; struct kfd_ioctl_dbg_wave_control_args { __u64 content_ptr; /* a pointer to the actual content */ __u32 gpu_id; /* to KFD */ __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ }; #define KFD_DBG_EV_FLAG_CLEAR_STATUS 1 /* queue states for suspend/resume */ #define KFD_DBG_QUEUE_ERROR_BIT 30 #define KFD_DBG_QUEUE_INVALID_BIT 31 #define KFD_DBG_QUEUE_ERROR_MASK (1 << KFD_DBG_QUEUE_ERROR_BIT) #define KFD_DBG_QUEUE_INVALID_MASK (1 << KFD_DBG_QUEUE_INVALID_BIT) #define KFD_INVALID_GPUID 0xffffffff #define KFD_INVALID_QUEUEID 0xffffffff #define KFD_INVALID_FD 0xffffffff enum kfd_dbg_trap_override_mode { KFD_DBG_TRAP_OVERRIDE_OR = 0, KFD_DBG_TRAP_OVERRIDE_REPLACE = 1 }; enum kfd_dbg_trap_mask { KFD_DBG_TRAP_MASK_FP_INVALID = 1, KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL = 2, KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO = 4, KFD_DBG_TRAP_MASK_FP_OVERFLOW = 8, KFD_DBG_TRAP_MASK_FP_UNDERFLOW = 16, KFD_DBG_TRAP_MASK_FP_INEXACT = 32, KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO = 64, KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH = 128, KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION = 256, KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START = (1 << 30), KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END = (1 << 31) }; /* Wave launch modes */ enum kfd_dbg_trap_wave_launch_mode { KFD_DBG_TRAP_WAVE_LAUNCH_MODE_NORMAL = 0, KFD_DBG_TRAP_WAVE_LAUNCH_MODE_HALT = 1, KFD_DBG_TRAP_WAVE_LAUNCH_MODE_DEBUG = 3 }; /* Address watch modes */ enum kfd_dbg_trap_address_watch_mode { KFD_DBG_TRAP_ADDRESS_WATCH_MODE_READ = 0, KFD_DBG_TRAP_ADDRESS_WATCH_MODE_NONREAD = 1, KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ATOMIC = 2, KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL = 3 }; /* Additional wave settings */ enum kfd_dbg_trap_flags { KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP = 1, }; enum kfd_dbg_trap_exception_code { EC_NONE = 0, /* per queue */ EC_QUEUE_WAVE_ABORT = 1, EC_QUEUE_WAVE_TRAP = 2, EC_QUEUE_WAVE_MATH_ERROR = 3, EC_QUEUE_WAVE_ILLEGAL_INSTRUCTION = 4, EC_QUEUE_WAVE_MEMORY_VIOLATION = 5, EC_QUEUE_WAVE_APERTURE_VIOLATION = 6, EC_QUEUE_PACKET_DISPATCH_DIM_INVALID = 16, EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID = 17, EC_QUEUE_PACKET_DISPATCH_CODE_INVALID = 18, EC_QUEUE_PACKET_RESERVED = 19, EC_QUEUE_PACKET_UNSUPPORTED = 20, EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID = 21, EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID = 22, EC_QUEUE_PACKET_VENDOR_UNSUPPORTED = 23, EC_QUEUE_PREEMPTION_ERROR = 30, EC_QUEUE_NEW = 31, /* per device */ EC_DEVICE_QUEUE_DELETE = 32, EC_DEVICE_MEMORY_VIOLATION = 33, EC_DEVICE_RAS_ERROR = 34, EC_DEVICE_FATAL_HALT = 35, EC_DEVICE_NEW = 36, /* per process */ EC_PROCESS_RUNTIME = 48, EC_PROCESS_DEVICE_REMOVE = 49, EC_MAX }; /* Mask generated by ecode defined in enum above. */ #define KFD_EC_MASK(ecode) (1ULL << (ecode - 1)) /* Masks for exception code type checks below. */ #define KFD_EC_MASK_QUEUE (KFD_EC_MASK(EC_QUEUE_WAVE_ABORT) | \ KFD_EC_MASK(EC_QUEUE_WAVE_TRAP) | \ KFD_EC_MASK(EC_QUEUE_WAVE_MATH_ERROR) | \ KFD_EC_MASK(EC_QUEUE_WAVE_ILLEGAL_INSTRUCTION) | \ KFD_EC_MASK(EC_QUEUE_WAVE_MEMORY_VIOLATION) | \ KFD_EC_MASK(EC_QUEUE_WAVE_APERTURE_VIOLATION) | \ KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_DIM_INVALID) | \ KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID) | \ KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_CODE_INVALID) | \ KFD_EC_MASK(EC_QUEUE_PACKET_UNSUPPORTED) | \ KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID) | \ KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID) | \ KFD_EC_MASK(EC_QUEUE_PACKET_VENDOR_UNSUPPORTED) | \ KFD_EC_MASK(EC_QUEUE_PREEMPTION_ERROR) | \ KFD_EC_MASK(EC_QUEUE_NEW)) #define KFD_EC_MASK_DEVICE (KFD_EC_MASK(EC_DEVICE_QUEUE_DELETE) | \ KFD_EC_MASK(EC_DEVICE_RAS_ERROR) | \ KFD_EC_MASK(EC_DEVICE_FATAL_HALT) | \ KFD_EC_MASK(EC_DEVICE_MEMORY_VIOLATION) | \ KFD_EC_MASK(EC_DEVICE_NEW)) #define KFD_EC_MASK_PROCESS (KFD_EC_MASK(EC_PROCESS_RUNTIME) | \ KFD_EC_MASK(EC_PROCESS_DEVICE_REMOVE)) /* Checks for exception code types for KFD search. */ #define KFD_DBG_EC_TYPE_IS_QUEUE(ecode) \ (!!(KFD_EC_MASK(ecode) & KFD_EC_MASK_QUEUE)) #define KFD_DBG_EC_TYPE_IS_DEVICE(ecode) \ (!!(KFD_EC_MASK(ecode) & KFD_EC_MASK_DEVICE)) #define KFD_DBG_EC_TYPE_IS_PROCESS(ecode) \ (!!(KFD_EC_MASK(ecode) & KFD_EC_MASK_PROCESS)) enum kfd_dbg_runtime_state { DEBUG_RUNTIME_STATE_DISABLED = 0, DEBUG_RUNTIME_STATE_ENABLED = 1, DEBUG_RUNTIME_STATE_ENABLED_BUSY = 2, DEBUG_RUNTIME_STATE_ENABLED_ERROR = 3 }; struct kfd_runtime_info { __u64 r_debug; __u32 runtime_state; __u32 ttmp_setup; }; /* Enable modes for runtime enable */ #define KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK 1 #define KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK 2 #define KFD_RUNTIME_ENABLE_CAPS_SUPPORTS_CORE_DUMP_MASK 0x80000000 /** * kfd_ioctl_runtime_enable_args - Arguments for runtime enable * * Coordinates debug exception signalling and debug device enablement with runtime. * * @r_debug - pointer to user struct for sharing information between ROCr and the debuggger * @mode_mask - mask to set mode * KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK - enable runtime for debugging, otherwise disable * KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK - enable trap temporary setup (ignore on disable) * * Return - 0 on SUCCESS. * - EBUSY if runtime enable call already pending. * - EEXIST if user queues already active prior to call. * If process is debug enabled, runtime enable will enable debug devices and * wait for debugger process to send runtime exception EC_PROCESS_RUNTIME * to unblock - see kfd_ioctl_dbg_trap_args. * */ struct kfd_ioctl_runtime_enable_args { __u64 r_debug; __u32 mode_mask; __u32 capabilities_mask; }; /* Context save area header information */ struct kfd_context_save_area_header { struct { __u32 control_stack_offset; __u32 control_stack_size; __u32 wave_state_offset; __u32 wave_state_size; } wave_state; __u32 debug_offset; __u32 debug_size; __u64 err_payload_addr; __u32 err_event_id; __u32 reserved1; }; /* * Debug operations * * For specifics on usage and return values, see documentation per operation * below. Otherwise, generic error returns apply: * - ESRCH if the process to debug does not exist. * * - EINVAL (with KFD_IOC_DBG_TRAP_ENABLE exempt) if operation * KFD_IOC_DBG_TRAP_ENABLE has not succeeded prior. * Also returns this error if GPU hardware scheduling is not supported. * * - EPERM (with KFD_IOC_DBG_TRAP_DISABLE exempt) if target process is not * PTRACE_ATTACHED. KFD_IOC_DBG_TRAP_DISABLE is exempt to allow * clean up of debug mode as long as process is debug enabled. * * - EACCES if any DBG_HW_OP (debug hardware operation) is requested when * AMDKFD_IOC_RUNTIME_ENABLE has not succeeded prior. * * - ENODEV if any GPU does not support debugging on a DBG_HW_OP call. * * - Other errors may be returned when a DBG_HW_OP occurs while the GPU * is in a fatal state. * */ enum kfd_dbg_trap_operations { KFD_IOC_DBG_TRAP_ENABLE = 0, KFD_IOC_DBG_TRAP_DISABLE = 1, KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT = 2, KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED = 3, KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE = 4, /* DBG_HW_OP */ KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE = 5, /* DBG_HW_OP */ KFD_IOC_DBG_TRAP_SUSPEND_QUEUES = 6, /* DBG_HW_OP */ KFD_IOC_DBG_TRAP_RESUME_QUEUES = 7, /* DBG_HW_OP */ KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH = 8, /* DBG_HW_OP */ KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH = 9, /* DBG_HW_OP */ KFD_IOC_DBG_TRAP_SET_FLAGS = 10, KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT = 11, KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO = 12, KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT = 13, KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT = 14 }; /** * kfd_ioctl_dbg_trap_enable_args * * Arguments for KFD_IOC_DBG_TRAP_ENABLE. * * Enables debug session for target process. Call @op KFD_IOC_DBG_TRAP_DISABLE in * kfd_ioctl_dbg_trap_args to disable debug session. * * @exception_mask (IN) - exceptions to raise to the debugger * @rinfo_ptr (IN) - pointer to runtime info buffer (see kfd_runtime_info) * @rinfo_size (IN/OUT) - size of runtime info buffer in bytes * @dbg_fd (IN) - fd the KFD will nofify the debugger with of raised * exceptions set in exception_mask. * * Generic errors apply (see kfd_dbg_trap_operations). * Return - 0 on SUCCESS. * Copies KFD saved kfd_runtime_info to @rinfo_ptr on enable. * Size of kfd_runtime saved by the KFD returned to @rinfo_size. * - EBADF if KFD cannot get a reference to dbg_fd. * - EFAULT if KFD cannot copy runtime info to rinfo_ptr. * - EINVAL if target process is already debug enabled. * */ struct kfd_ioctl_dbg_trap_enable_args { __u64 exception_mask; __u64 rinfo_ptr; __u32 rinfo_size; __u32 dbg_fd; }; /** * kfd_ioctl_dbg_trap_send_runtime_event_args * * * Arguments for KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT. * Raises exceptions to runtime. * * @exception_mask (IN) - exceptions to raise to runtime * @gpu_id (IN) - target device id * @queue_id (IN) - target queue id * * Generic errors apply (see kfd_dbg_trap_operations). * Return - 0 on SUCCESS. * - ENODEV if gpu_id not found. * If exception_mask contains EC_PROCESS_RUNTIME, unblocks pending * AMDKFD_IOC_RUNTIME_ENABLE call - see kfd_ioctl_runtime_enable_args. * All other exceptions are raised to runtime through err_payload_addr. * See kfd_context_save_area_header. */ struct kfd_ioctl_dbg_trap_send_runtime_event_args { __u64 exception_mask; __u32 gpu_id; __u32 queue_id; }; /** * kfd_ioctl_dbg_trap_set_exceptions_enabled_args * * Arguments for KFD_IOC_SET_EXCEPTIONS_ENABLED * Set new exceptions to be raised to the debugger. * * @exception_mask (IN) - new exceptions to raise the debugger * * Generic errors apply (see kfd_dbg_trap_operations). * Return - 0 on SUCCESS. */ struct kfd_ioctl_dbg_trap_set_exceptions_enabled_args { __u64 exception_mask; }; /** * kfd_ioctl_dbg_trap_set_wave_launch_override_args * * Arguments for KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE * Enable HW exceptions to raise trap. * * @override_mode (IN) - see kfd_dbg_trap_override_mode * @enable_mask (IN/OUT) - reference kfd_dbg_trap_mask. * IN is the override modes requested to be enabled. * OUT is referenced in Return below. * @support_request_mask (IN/OUT) - reference kfd_dbg_trap_mask. * IN is the override modes requested for support check. * OUT is referenced in Return below. * * Generic errors apply (see kfd_dbg_trap_operations). * Return - 0 on SUCCESS. * Previous enablement is returned in @enable_mask. * Actual override support is returned in @support_request_mask. * - EINVAL if override mode is not supported. * - EACCES if trap support requested is not actually supported. * i.e. enable_mask (IN) is not a subset of support_request_mask (OUT). * Otherwise it is considered a generic error (see kfd_dbg_trap_operations). */ struct kfd_ioctl_dbg_trap_set_wave_launch_override_args { __u32 override_mode; __u32 enable_mask; __u32 support_request_mask; __u32 pad; }; /** * kfd_ioctl_dbg_trap_set_wave_launch_mode_args * * Arguments for KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE * Set wave launch mode. * * @mode (IN) - see kfd_dbg_trap_wave_launch_mode * * Generic errors apply (see kfd_dbg_trap_operations). * Return - 0 on SUCCESS. */ struct kfd_ioctl_dbg_trap_set_wave_launch_mode_args { __u32 launch_mode; __u32 pad; }; /** * kfd_ioctl_dbg_trap_suspend_queues_ags * * Arguments for KFD_IOC_DBG_TRAP_SUSPEND_QUEUES * Suspend queues. * * @exception_mask (IN) - raised exceptions to clear * @queue_array_ptr (IN) - pointer to array of queue ids (u32 per queue id) * to suspend * @num_queues (IN) - number of queues to suspend in @queue_array_ptr * @grace_period (IN) - wave time allowance before preemption * per 1K GPU clock cycle unit * * Generic errors apply (see kfd_dbg_trap_operations). * Destruction of a suspended queue is blocked until the queue is * resumed. This allows the debugger to access queue information and * the its context save area without running into a race condition on * queue destruction. * Automatically copies per queue context save area header information * into the save area base * (see kfd_queue_snapshot_entry and kfd_context_save_area_header). * * Return - Number of queues suspended on SUCCESS. * . KFD_DBG_QUEUE_ERROR_MASK and KFD_DBG_QUEUE_INVALID_MASK masked * for each queue id in @queue_array_ptr array reports unsuccessful * suspend reason. * KFD_DBG_QUEUE_ERROR_MASK = HW failure. * KFD_DBG_QUEUE_INVALID_MASK = queue does not exist, is new or * is being destroyed. */ struct kfd_ioctl_dbg_trap_suspend_queues_args { __u64 exception_mask; __u64 queue_array_ptr; __u32 num_queues; __u32 grace_period; }; /** * kfd_ioctl_dbg_trap_resume_queues_args * * Arguments for KFD_IOC_DBG_TRAP_RESUME_QUEUES * Resume queues. * * @queue_array_ptr (IN) - pointer to array of queue ids (u32 per queue id) * to resume * @num_queues (IN) - number of queues to resume in @queue_array_ptr * * Generic errors apply (see kfd_dbg_trap_operations). * Return - Number of queues resumed on SUCCESS. * KFD_DBG_QUEUE_ERROR_MASK and KFD_DBG_QUEUE_INVALID_MASK mask * for each queue id in @queue_array_ptr array reports unsuccessful * resume reason. * KFD_DBG_QUEUE_ERROR_MASK = HW failure. * KFD_DBG_QUEUE_INVALID_MASK = queue does not exist. */ struct kfd_ioctl_dbg_trap_resume_queues_args { __u64 queue_array_ptr; __u32 num_queues; __u32 pad; }; /** * kfd_ioctl_dbg_trap_set_node_address_watch_args * * Arguments for KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH * Sets address watch for device. * * @address (IN) - watch address to set * @mode (IN) - see kfd_dbg_trap_address_watch_mode * @mask (IN) - watch address mask * @gpu_id (IN) - target gpu to set watch point * @id (OUT) - watch id allocated * * Generic errors apply (see kfd_dbg_trap_operations). * Return - 0 on SUCCESS. * Allocated watch ID returned to @id. * - ENODEV if gpu_id not found. * - ENOMEM if watch IDs can be allocated */ struct kfd_ioctl_dbg_trap_set_node_address_watch_args { __u64 address; __u32 mode; __u32 mask; __u32 gpu_id; __u32 id; }; /** * kfd_ioctl_dbg_trap_clear_node_address_watch_args * * Arguments for KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH * Clear address watch for device. * * @gpu_id (IN) - target device to clear watch point * @id (IN) - allocated watch id to clear * * Generic errors apply (see kfd_dbg_trap_operations). * Return - 0 on SUCCESS. * - ENODEV if gpu_id not found. * - EINVAL if watch ID has not been allocated. */ struct kfd_ioctl_dbg_trap_clear_node_address_watch_args { __u32 gpu_id; __u32 id; }; /** * kfd_ioctl_dbg_trap_set_flags_args * * Arguments for KFD_IOC_DBG_TRAP_SET_FLAGS * Sets flags for wave behaviour. * * @flags (IN/OUT) - IN = flags to enable, OUT = flags previously enabled * * Generic errors apply (see kfd_dbg_trap_operations). * Return - 0 on SUCCESS. * - EACCESS if any debug device does not allow flag options. */ struct kfd_ioctl_dbg_trap_set_flags_args { __u32 flags; __u32 pad; }; /** * kfd_ioctl_dbg_trap_query_debug_event_args * * Arguments for KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT * * Find one or more raised exceptions. This function can return multiple * exceptions from a single queue or a single device with one call. To find * all raised exceptions, this function must be called repeatedly until it * returns -EAGAIN. Returned exceptions can optionally be cleared by * setting the corresponding bit in the @exception_mask input parameter. * However, clearing an exception prevents retrieving further information * about it with KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO. * * @exception_mask (IN/OUT) - exception to clear (IN) and raised (OUT) * @gpu_id (OUT) - gpu id of exceptions raised * @queue_id (OUT) - queue id of exceptions raised * * Generic errors apply (see kfd_dbg_trap_operations). * Return - 0 on raised exception found * Raised exceptions found are returned in @exception mask * with reported source id returned in @gpu_id or @queue_id. * - EAGAIN if no raised exception has been found */ struct kfd_ioctl_dbg_trap_query_debug_event_args { __u64 exception_mask; __u32 gpu_id; __u32 queue_id; }; /** * kfd_ioctl_dbg_trap_query_exception_info_args * * Arguments KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO * Get additional info on raised exception. * * @info_ptr (IN) - pointer to exception info buffer to copy to * @info_size (IN/OUT) - exception info buffer size (bytes) * @source_id (IN) - target gpu or queue id * @exception_code (IN) - target exception * @clear_exception (IN) - clear raised @exception_code exception * (0 = false, 1 = true) * * Generic errors apply (see kfd_dbg_trap_operations). * Return - 0 on SUCCESS. * If @exception_code is EC_DEVICE_MEMORY_VIOLATION, copy @info_size(OUT) * bytes of memory exception data to @info_ptr. * If @exception_code is EC_PROCESS_RUNTIME, copy saved * kfd_runtime_info to @info_ptr. * Actual required @info_ptr size (bytes) is returned in @info_size. */ struct kfd_ioctl_dbg_trap_query_exception_info_args { __u64 info_ptr; __u32 info_size; __u32 source_id; __u32 exception_code; __u32 clear_exception; }; /** * kfd_ioctl_dbg_trap_get_queue_snapshot_args * * Arguments KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT * Get queue information. * * @exception_mask (IN) - exceptions raised to clear * @snapshot_buf_ptr (IN) - queue snapshot entry buffer (see kfd_queue_snapshot_entry) * @num_queues (IN/OUT) - number of queue snapshot entries * The debugger specifies the size of the array allocated in @num_queues. * KFD returns the number of queues that actually existed. If this is * larger than the size specified by the debugger, KFD will not overflow * the array allocated by the debugger. * * @entry_size (IN/OUT) - size per entry in bytes * The debugger specifies sizeof(struct kfd_queue_snapshot_entry) in * @entry_size. KFD returns the number of bytes actually populated per * entry. The debugger should use the KFD_IOCTL_MINOR_VERSION to determine, * which fields in struct kfd_queue_snapshot_entry are valid. This allows * growing the ABI in a backwards compatible manner. * Note that entry_size(IN) should still be used to stride the snapshot buffer in the * event that it's larger than actual kfd_queue_snapshot_entry. * * Generic errors apply (see kfd_dbg_trap_operations). * Return - 0 on SUCCESS. * Copies @num_queues(IN) queue snapshot entries of size @entry_size(IN) * into @snapshot_buf_ptr if @num_queues(IN) > 0. * Otherwise return @num_queues(OUT) queue snapshot entries that exist. */ struct kfd_ioctl_dbg_trap_queue_snapshot_args { __u64 exception_mask; __u64 snapshot_buf_ptr; __u32 num_queues; __u32 entry_size; }; /** * kfd_ioctl_dbg_trap_get_device_snapshot_args * * Arguments for KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT * Get device information. * * @exception_mask (IN) - exceptions raised to clear * @snapshot_buf_ptr (IN) - pointer to snapshot buffer (see kfd_dbg_device_info_entry) * @num_devices (IN/OUT) - number of debug devices to snapshot * The debugger specifies the size of the array allocated in @num_devices. * KFD returns the number of devices that actually existed. If this is * larger than the size specified by the debugger, KFD will not overflow * the array allocated by the debugger. * * @entry_size (IN/OUT) - size per entry in bytes * The debugger specifies sizeof(struct kfd_dbg_device_info_entry) in * @entry_size. KFD returns the number of bytes actually populated. The * debugger should use KFD_IOCTL_MINOR_VERSION to determine, which fields * in struct kfd_dbg_device_info_entry are valid. This allows growing the * ABI in a backwards compatible manner. * Note that entry_size(IN) should still be used to stride the snapshot buffer in the * event that it's larger than actual kfd_dbg_device_info_entry. * * Generic errors apply (see kfd_dbg_trap_operations). * Return - 0 on SUCCESS. * Copies @num_devices(IN) device snapshot entries of size @entry_size(IN) * into @snapshot_buf_ptr if @num_devices(IN) > 0. * Otherwise return @num_devices(OUT) queue snapshot entries that exist. */ struct kfd_ioctl_dbg_trap_device_snapshot_args { __u64 exception_mask; __u64 snapshot_buf_ptr; __u32 num_devices; __u32 entry_size; }; /** * kfd_ioctl_dbg_trap_args * * Arguments to debug target process. * * @pid - target process to debug * @op - debug operation (see kfd_dbg_trap_operations) * * @op determines which union struct args to use. * Refer to kern docs for each kfd_ioctl_dbg_trap_*_args struct. */ struct kfd_ioctl_dbg_trap_args { __u32 pid; __u32 op; union { struct kfd_ioctl_dbg_trap_enable_args enable; struct kfd_ioctl_dbg_trap_send_runtime_event_args send_runtime_event; struct kfd_ioctl_dbg_trap_set_exceptions_enabled_args set_exceptions_enabled; struct kfd_ioctl_dbg_trap_set_wave_launch_override_args launch_override; struct kfd_ioctl_dbg_trap_set_wave_launch_mode_args launch_mode; struct kfd_ioctl_dbg_trap_suspend_queues_args suspend_queues; struct kfd_ioctl_dbg_trap_resume_queues_args resume_queues; struct kfd_ioctl_dbg_trap_set_node_address_watch_args set_node_address_watch; struct kfd_ioctl_dbg_trap_clear_node_address_watch_args clear_node_address_watch; struct kfd_ioctl_dbg_trap_set_flags_args set_flags; struct kfd_ioctl_dbg_trap_query_debug_event_args query_debug_event; struct kfd_ioctl_dbg_trap_query_exception_info_args query_exception_info; struct kfd_ioctl_dbg_trap_queue_snapshot_args queue_snapshot; struct kfd_ioctl_dbg_trap_device_snapshot_args device_snapshot; }; }; /* Matching HSA_EVENTTYPE */ #define KFD_IOC_EVENT_SIGNAL 0 #define KFD_IOC_EVENT_NODECHANGE 1 #define KFD_IOC_EVENT_DEVICESTATECHANGE 2 #define KFD_IOC_EVENT_HW_EXCEPTION 3 #define KFD_IOC_EVENT_SYSTEM_EVENT 4 #define KFD_IOC_EVENT_DEBUG_EVENT 5 #define KFD_IOC_EVENT_PROFILE_EVENT 6 #define KFD_IOC_EVENT_QUEUE_EVENT 7 #define KFD_IOC_EVENT_MEMORY 8 #define KFD_IOC_WAIT_RESULT_COMPLETE 0 #define KFD_IOC_WAIT_RESULT_TIMEOUT 1 #define KFD_IOC_WAIT_RESULT_FAIL 2 #define KFD_SIGNAL_EVENT_LIMIT 4096 /* For kfd_event_data.hw_exception_data.reset_type. */ #define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0 #define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1 /* For kfd_event_data.hw_exception_data.reset_cause. */ #define KFD_HW_EXCEPTION_GPU_HANG 0 #define KFD_HW_EXCEPTION_ECC 1 /* For kfd_hsa_memory_exception_data.ErrorType */ #define KFD_MEM_ERR_NO_RAS 0 #define KFD_MEM_ERR_SRAM_ECC 1 #define KFD_MEM_ERR_POISON_CONSUMED 2 #define KFD_MEM_ERR_GPU_HANG 3 struct kfd_ioctl_create_event_args { __u64 event_page_offset; /* from KFD */ __u32 event_trigger_data; /* from KFD - signal events only */ __u32 event_type; /* to KFD */ __u32 auto_reset; /* to KFD */ __u32 node_id; /* to KFD - only valid for certain event types */ __u32 event_id; /* from KFD */ __u32 event_slot_index; /* from KFD */ }; struct kfd_ioctl_destroy_event_args { __u32 event_id; /* to KFD */ __u32 pad; }; struct kfd_ioctl_set_event_args { __u32 event_id; /* to KFD */ __u32 pad; }; struct kfd_ioctl_reset_event_args { __u32 event_id; /* to KFD */ __u32 pad; }; struct kfd_memory_exception_failure { __u32 NotPresent; /* Page not present or supervisor privilege */ __u32 ReadOnly; /* Write access to a read-only page */ __u32 NoExecute; /* Execute access to a page marked NX */ __u32 imprecise; /* Can't determine the exact fault address */ }; /* memory exception data */ struct kfd_hsa_memory_exception_data { struct kfd_memory_exception_failure failure; __u64 va; __u32 gpu_id; __u32 ErrorType; /* 0 = no RAS error, * 1 = ECC_SRAM, * 2 = Link_SYNFLOOD (poison), * 3 = GPU hang (not attributable to a specific cause), * other values reserved */ }; /* hw exception data */ struct kfd_hsa_hw_exception_data { __u32 reset_type; __u32 reset_cause; __u32 memory_lost; __u32 gpu_id; }; /* hsa signal event data */ struct kfd_hsa_signal_event_data { __u64 last_event_age; /* to and from KFD */ }; /* Event data */ struct kfd_event_data { union { /* From KFD */ struct kfd_hsa_memory_exception_data memory_exception_data; struct kfd_hsa_hw_exception_data hw_exception_data; /* To and From KFD */ struct kfd_hsa_signal_event_data signal_event_data; }; __u64 kfd_event_data_ext; /* pointer to an extension structure for future exception types */ __u32 event_id; /* to KFD */ __u32 pad; }; struct kfd_ioctl_wait_events_args { __u64 events_ptr; /* pointed to struct kfd_event_data array, to KFD */ __u32 num_events; /* to KFD */ __u32 wait_for_all; /* to KFD */ __u32 timeout; /* to KFD */ __u32 wait_result; /* from KFD */ }; struct kfd_ioctl_set_scratch_backing_va_args { __u64 va_addr; /* to KFD */ __u32 gpu_id; /* to KFD */ __u32 pad; }; struct kfd_ioctl_get_tile_config_args { /* to KFD: pointer to tile array */ __u64 tile_config_ptr; /* to KFD: pointer to macro tile array */ __u64 macro_tile_config_ptr; /* to KFD: array size allocated by user mode * from KFD: array size filled by kernel */ __u32 num_tile_configs; /* to KFD: array size allocated by user mode * from KFD: array size filled by kernel */ __u32 num_macro_tile_configs; __u32 gpu_id; /* to KFD */ __u32 gb_addr_config; /* from KFD */ __u32 num_banks; /* from KFD */ __u32 num_ranks; /* from KFD */ /* struct size can be extended later if needed * without breaking ABI compatibility */ }; struct kfd_ioctl_set_trap_handler_args { __u64 tba_addr; /* to KFD */ __u64 tma_addr; /* to KFD */ __u32 gpu_id; /* to KFD */ __u32 pad; }; struct kfd_ioctl_acquire_vm_args { __u32 drm_fd; /* to KFD */ __u32 gpu_id; /* to KFD */ }; /* Allocation flags: memory types */ #define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0) #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1) #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2) #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3) #define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4) /* Allocation flags: attributes/access options */ #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31) #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30) #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29) #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27) #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26) #define KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED (1 << 25) /* Allocate memory for later SVM (shared virtual memory) mapping. * * @va_addr: virtual address of the memory to be allocated * all later mappings on all GPUs will use this address * @size: size in bytes * @handle: buffer handle returned to user mode, used to refer to * this allocation for mapping, unmapping and freeing * @mmap_offset: for CPU-mapping the allocation by mmapping a render node * for userptrs this is overloaded to specify the CPU address * @gpu_id: device identifier * @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above */ struct kfd_ioctl_alloc_memory_of_gpu_args { __u64 va_addr; /* to KFD */ __u64 size; /* to KFD */ __u64 handle; /* from KFD */ __u64 mmap_offset; /* to KFD (userptr), from KFD (mmap offset) */ __u32 gpu_id; /* to KFD */ __u32 flags; }; /* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu * * @handle: memory handle returned by alloc */ struct kfd_ioctl_free_memory_of_gpu_args { __u64 handle; /* to KFD */ }; /* Inquire available memory with kfd_ioctl_get_available_memory * * @available: memory available for alloc */ struct kfd_ioctl_get_available_memory_args { __u64 available; /* from KFD */ __u32 gpu_id; /* to KFD */ __u32 pad; }; /* Map memory to one or more GPUs * * @handle: memory handle returned by alloc * @device_ids_array_ptr: array of gpu_ids (__u32 per device) * @n_devices: number of devices in the array * @n_success: number of devices mapped successfully * * @n_success returns information to the caller how many devices from * the start of the array have mapped the buffer successfully. It can * be passed into a subsequent retry call to skip those devices. For * the first call the caller should initialize it to 0. * * If the ioctl completes with return code 0 (success), n_success == * n_devices. */ struct kfd_ioctl_map_memory_to_gpu_args { __u64 handle; /* to KFD */ __u64 device_ids_array_ptr; /* to KFD */ __u32 n_devices; /* to KFD */ __u32 n_success; /* to/from KFD */ }; /* Unmap memory from one or more GPUs * * same arguments as for mapping */ struct kfd_ioctl_unmap_memory_from_gpu_args { __u64 handle; /* to KFD */ __u64 device_ids_array_ptr; /* to KFD */ __u32 n_devices; /* to KFD */ __u32 n_success; /* to/from KFD */ }; /* Allocate GWS for specific queue * * @queue_id: queue's id that GWS is allocated for * @num_gws: how many GWS to allocate * @first_gws: index of the first GWS allocated. * only support contiguous GWS allocation */ struct kfd_ioctl_alloc_queue_gws_args { __u32 queue_id; /* to KFD */ __u32 num_gws; /* to KFD */ __u32 first_gws; /* from KFD */ __u32 pad; }; struct kfd_ioctl_get_dmabuf_info_args { __u64 size; /* from KFD */ __u64 metadata_ptr; /* to KFD */ __u32 metadata_size; /* to KFD (space allocated by user) * from KFD (actual metadata size) */ __u32 gpu_id; /* from KFD */ __u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */ __u32 dmabuf_fd; /* to KFD */ }; struct kfd_ioctl_import_dmabuf_args { __u64 va_addr; /* to KFD */ __u64 handle; /* from KFD */ __u32 gpu_id; /* to KFD */ __u32 dmabuf_fd; /* to KFD */ }; struct kfd_ioctl_export_dmabuf_args { __u64 handle; /* to KFD */ __u32 flags; /* to KFD */ __u32 dmabuf_fd; /* from KFD */ }; /* * KFD SMI(System Management Interface) events */ enum kfd_smi_event { KFD_SMI_EVENT_NONE = 0, /* not used */ KFD_SMI_EVENT_VMFAULT = 1, /* event start counting at 1 */ KFD_SMI_EVENT_THERMAL_THROTTLE = 2, KFD_SMI_EVENT_GPU_PRE_RESET = 3, KFD_SMI_EVENT_GPU_POST_RESET = 4, }; #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1)) #define KFD_SMI_EVENT_MSG_SIZE 96 struct kfd_ioctl_smi_events_args { __u32 gpuid; /* to KFD */ __u32 anon_fd; /* from KFD */ }; /** * kfd_ioctl_spm_op - SPM ioctl operations * * @KFD_IOCTL_SPM_OP_ACQUIRE: acquire exclusive access to SPM * @KFD_IOCTL_SPM_OP_RELEASE: release exclusive access to SPM * @KFD_IOCTL_SPM_OP_SET_DEST_BUF: set or unset destination buffer for SPM streaming */ enum kfd_ioctl_spm_op { KFD_IOCTL_SPM_OP_ACQUIRE, KFD_IOCTL_SPM_OP_RELEASE, KFD_IOCTL_SPM_OP_SET_DEST_BUF }; /** * kfd_ioctl_spm_args - Arguments for SPM ioctl * * @op[in]: specifies the operation to perform * @gpu_id[in]: GPU ID of the GPU to profile * @dst_buf[in]: used for the address of the destination buffer * in @KFD_IOCTL_SPM_SET_DEST_BUFFER * @buf_size[in]: size of the destination buffer * @timeout[in/out]: [in]: timeout in milliseconds, [out]: amount of time left * `in the timeout window * @bytes_copied[out]: amount of data that was copied to the previous dest_buf * @has_data_loss: boolean indicating whether data was lost * (e.g. due to a ring-buffer overflow) * * This ioctl performs different functions depending on the @op parameter. * * KFD_IOCTL_SPM_OP_ACQUIRE * ------------------------ * * Acquires exclusive access of SPM on the specified @gpu_id for the calling process. * This must be called before using KFD_IOCTL_SPM_OP_SET_DEST_BUF. * * KFD_IOCTL_SPM_OP_RELEASE * ------------------------ * * Releases exclusive access of SPM on the specified @gpu_id for the calling process, * which allows another process to acquire it in the future. * * KFD_IOCTL_SPM_OP_SET_DEST_BUF * ----------------------------- * * If @dst_buf is NULL, the destination buffer address is unset and copying of counters * is stopped. * * If @dst_buf is not NULL, it specifies the pointer to a new destination buffer. * @buf_size specifies the size of the buffer. * * If @timeout is non-0, the call will wait for up to @timeout ms for the previous * buffer to be filled. If previous buffer to be filled before timeout, the @timeout * will be updated value with the time remaining. If the timeout is exceeded, the function * copies any partial data available into the previous user buffer and returns success. * The amount of valid data in the previous user buffer is indicated by @bytes_copied. * * If @timeout is 0, the function immediately replaces the previous destination buffer * without waiting for the previous buffer to be filled. That means the previous buffer * may only be partially filled, and @bytes_copied will indicate how much data has been * copied to it. * * If data was lost, e.g. due to a ring buffer overflow, @has_data_loss will be non-0. * * Returns negative error code on failure, 0 on success. */ struct kfd_ioctl_spm_args { __u64 dest_buf; __u32 buf_size; __u32 op; __u32 timeout; __u32 gpu_id; __u32 bytes_copied; __u32 has_data_loss; }; /************************************************************************************************** * CRIU IOCTLs (Checkpoint Restore In Userspace) * * When checkpointing a process, the userspace application will perform: * 1. PROCESS_INFO op to determine current process information. This pauses execution and evicts * all the queues. * 2. CHECKPOINT op to checkpoint process contents (BOs, queues, events, svm-ranges) * 3. UNPAUSE op to un-evict all the queues * * When restoring a process, the CRIU userspace application will perform: * * 1. RESTORE op to restore process contents * 2. RESUME op to start the process * * Note: Queues are forced into an evicted state after a successful PROCESS_INFO. User * application needs to perform an UNPAUSE operation after calling PROCESS_INFO. */ enum kfd_criu_op { KFD_CRIU_OP_PROCESS_INFO, KFD_CRIU_OP_CHECKPOINT, KFD_CRIU_OP_UNPAUSE, KFD_CRIU_OP_RESTORE, KFD_CRIU_OP_RESUME, }; /** * kfd_ioctl_criu_args - Arguments perform CRIU operation * @devices: [in/out] User pointer to memory location for devices information. * This is an array of type kfd_criu_device_bucket. * @bos: [in/out] User pointer to memory location for BOs information * This is an array of type kfd_criu_bo_bucket. * @priv_data: [in/out] User pointer to memory location for private data * @priv_data_size: [in/out] Size of priv_data in bytes * @num_devices: [in/out] Number of GPUs used by process. Size of @devices array. * @num_bos [in/out] Number of BOs used by process. Size of @bos array. * @num_objects: [in/out] Number of objects used by process. Objects are opaque to * user application. * @pid: [in/out] PID of the process being checkpointed * @op [in] Type of operation (kfd_criu_op) * * Return: 0 on success, -errno on failure */ struct kfd_ioctl_criu_args { __u64 devices; /* Used during ops: CHECKPOINT, RESTORE */ __u64 bos; /* Used during ops: CHECKPOINT, RESTORE */ __u64 priv_data; /* Used during ops: CHECKPOINT, RESTORE */ __u64 priv_data_size; /* Used during ops: PROCESS_INFO, RESTORE */ __u32 num_devices; /* Used during ops: PROCESS_INFO, RESTORE */ __u32 num_bos; /* Used during ops: PROCESS_INFO, RESTORE */ __u32 num_objects; /* Used during ops: PROCESS_INFO, RESTORE */ __u32 pid; /* Used during ops: PROCESS_INFO, RESUME */ __u32 op; }; struct kfd_criu_device_bucket { __u32 user_gpu_id; __u32 actual_gpu_id; __u32 drm_fd; __u32 pad; }; struct kfd_criu_bo_bucket { __u64 addr; __u64 size; __u64 offset; __u64 restored_offset; /* During restore, updated offset for BO */ __u32 gpu_id; /* This is the user_gpu_id */ __u32 alloc_flags; __u32 dmabuf_fd; __u32 pad; }; /* CRIU IOCTLs - END */ /**************************************************************************************************/ /* Register offset inside the remapped mmio page */ enum kfd_mmio_remap { KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0, KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, }; struct kfd_ioctl_ipc_export_handle_args { __u64 handle; /* to KFD */ __u32 share_handle[4]; /* from KFD */ __u32 gpu_id; /* to KFD */ __u32 flags; /* to KFD */ }; struct kfd_ioctl_ipc_import_handle_args { __u64 handle; /* from KFD */ __u64 va_addr; /* to KFD */ __u64 mmap_offset; /* from KFD */ __u32 share_handle[4]; /* to KFD */ __u32 gpu_id; /* to KFD */ __u32 flags; /* from KFD */ }; struct kfd_memory_range { __u64 va_addr; __u64 size; }; /* flags definitions * BIT0: 0: read operation, 1: write operation. * This also identifies if the src or dst array belongs to remote process */ #define KFD_CROSS_MEMORY_RW_BIT (1 << 0) #define KFD_SET_CROSS_MEMORY_READ(flags) (flags &= ~KFD_CROSS_MEMORY_RW_BIT) #define KFD_SET_CROSS_MEMORY_WRITE(flags) (flags |= KFD_CROSS_MEMORY_RW_BIT) #define KFD_IS_CROSS_MEMORY_WRITE(flags) (flags & KFD_CROSS_MEMORY_RW_BIT) struct kfd_ioctl_cross_memory_copy_args { /* to KFD: Process ID of the remote process */ __u32 pid; /* to KFD: See above definition */ __u32 flags; /* to KFD: Source GPU VM range */ __u64 src_mem_range_array; /* to KFD: Size of above array */ __u64 src_mem_array_size; /* to KFD: Destination GPU VM range */ __u64 dst_mem_range_array; /* to KFD: Size of above array */ __u64 dst_mem_array_size; /* from KFD: Total amount of bytes copied */ __u64 bytes_copied; }; /* Guarantee host access to memory */ #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 /* Fine grained coherency between all devices with access */ #define KFD_IOCTL_SVM_FLAG_COHERENT 0x00000002 /* Use any GPU in same hive as preferred device */ #define KFD_IOCTL_SVM_FLAG_HIVE_LOCAL 0x00000004 /* GPUs only read, allows replication */ #define KFD_IOCTL_SVM_FLAG_GPU_RO 0x00000008 /* Allow execution on GPU */ #define KFD_IOCTL_SVM_FLAG_GPU_EXEC 0x00000010 /* GPUs mostly read, may allow similar optimizations as RO, but writes fault */ #define KFD_IOCTL_SVM_FLAG_GPU_READ_MOSTLY 0x00000020 /* Keep GPU memory mapping always valid as if XNACK is disable */ #define KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED 0x00000040 /** * kfd_ioctl_svm_op - SVM ioctl operations * * @KFD_IOCTL_SVM_OP_SET_ATTR: Modify one or more attributes * @KFD_IOCTL_SVM_OP_GET_ATTR: Query one or more attributes */ enum kfd_ioctl_svm_op { KFD_IOCTL_SVM_OP_SET_ATTR, KFD_IOCTL_SVM_OP_GET_ATTR }; /** kfd_ioctl_svm_location - Enum for preferred and prefetch locations * * GPU IDs are used to specify GPUs as preferred and prefetch locations. * Below definitions are used for system memory or for leaving the preferred * location unspecified. */ enum kfd_ioctl_svm_location { KFD_IOCTL_SVM_LOCATION_SYSMEM = 0, KFD_IOCTL_SVM_LOCATION_UNDEFINED = 0xffffffff }; /** * kfd_ioctl_svm_attr_type - SVM attribute types * * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: gpuid of the preferred location, 0 for * system memory * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: gpuid of the prefetch location, 0 for * system memory. Setting this triggers an * immediate prefetch (migration). * @KFD_IOCTL_SVM_ATTR_ACCESS: * @KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE: * @KFD_IOCTL_SVM_ATTR_NO_ACCESS: specify memory access for the gpuid given * by the attribute value * @KFD_IOCTL_SVM_ATTR_SET_FLAGS: bitmask of flags to set (see * KFD_IOCTL_SVM_FLAG_...) * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS: bitmask of flags to clear * @KFD_IOCTL_SVM_ATTR_GRANULARITY: migration granularity * (log2 num pages) */ enum kfd_ioctl_svm_attr_type { KFD_IOCTL_SVM_ATTR_PREFERRED_LOC, KFD_IOCTL_SVM_ATTR_PREFETCH_LOC, KFD_IOCTL_SVM_ATTR_ACCESS, KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE, KFD_IOCTL_SVM_ATTR_NO_ACCESS, KFD_IOCTL_SVM_ATTR_SET_FLAGS, KFD_IOCTL_SVM_ATTR_CLR_FLAGS, KFD_IOCTL_SVM_ATTR_GRANULARITY }; /** * kfd_ioctl_svm_attribute - Attributes as pairs of type and value * * The meaning of the @value depends on the attribute type. * * @type: attribute type (see enum @kfd_ioctl_svm_attr_type) * @value: attribute value */ struct kfd_ioctl_svm_attribute { __u32 type; __u32 value; }; /** * kfd_ioctl_svm_args - Arguments for SVM ioctl * * @op specifies the operation to perform (see enum * @kfd_ioctl_svm_op). @start_addr and @size are common for all * operations. * * A variable number of attributes can be given in @attrs. * @nattr specifies the number of attributes. New attributes can be * added in the future without breaking the ABI. If unknown attributes * are given, the function returns -EINVAL. * * @KFD_IOCTL_SVM_OP_SET_ATTR sets attributes for a virtual address * range. It may overlap existing virtual address ranges. If it does, * the existing ranges will be split such that the attribute changes * only apply to the specified address range. * * @KFD_IOCTL_SVM_OP_GET_ATTR returns the intersection of attributes * over all memory in the given range and returns the result as the * attribute value. If different pages have different preferred or * prefetch locations, 0xffffffff will be returned for * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC or * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC resepctively. For * @KFD_IOCTL_SVM_ATTR_SET_FLAGS, flags of all pages will be * aggregated by bitwise AND. That means, a flag will be set in the * output, if that flag is set for all pages in the range. For * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS, flags of all pages will be * aggregated by bitwise NOR. That means, a flag will be set in the * output, if that flag is clear for all pages in the range. * The minimum migration granularity throughout the range will be * returned for @KFD_IOCTL_SVM_ATTR_GRANULARITY. * * Querying of accessibility attributes works by initializing the * attribute type to @KFD_IOCTL_SVM_ATTR_ACCESS and the value to the * GPUID being queried. Multiple attributes can be given to allow * querying multiple GPUIDs. The ioctl function overwrites the * attribute type to indicate the access for the specified GPU. */ struct kfd_ioctl_svm_args { __u64 start_addr; __u64 size; __u32 op; __u32 nattr; /* Variable length array of attributes */ struct kfd_ioctl_svm_attribute attrs[]; }; /** * kfd_ioctl_set_xnack_mode_args - Arguments for set_xnack_mode * * @xnack_enabled: [in/out] Whether to enable XNACK mode for this process * * @xnack_enabled indicates whether recoverable page faults should be * enabled for the current process. 0 means disabled, positive means * enabled, negative means leave unchanged. If enabled, virtual address * translations on GFXv9 and later AMD GPUs can return XNACK and retry * the access until a valid PTE is available. This is used to implement * device page faults. * * On output, @xnack_enabled returns the (new) current mode (0 or * positive). Therefore, a negative input value can be used to query * the current mode without changing it. * * The XNACK mode fundamentally changes the way SVM managed memory works * in the driver, with subtle effects on application performance and * functionality. * * Enabling XNACK mode requires shader programs to be compiled * differently. Furthermore, not all GPUs support changing the mode * per-process. Therefore changing the mode is only allowed while no * user mode queues exist in the process. This ensure that no shader * code is running that may be compiled for the wrong mode. And GPUs * that cannot change to the requested mode will prevent the XNACK * mode from occurring. All GPUs used by the process must be in the * same XNACK mode. * * GFXv8 or older GPUs do not support 48 bit virtual addresses or SVM. * Therefore those GPUs are not considered for the XNACK mode switch. * * Return: 0 on success, -errno on failure */ struct kfd_ioctl_set_xnack_mode_args { __s32 xnack_enabled; }; #define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) #define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type) #define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) #define AMDKFD_IOC_GET_VERSION \ AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) #define AMDKFD_IOC_CREATE_QUEUE \ AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) #define AMDKFD_IOC_DESTROY_QUEUE \ AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) #define AMDKFD_IOC_SET_MEMORY_POLICY \ AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) #define AMDKFD_IOC_GET_CLOCK_COUNTERS \ AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) #define AMDKFD_IOC_GET_PROCESS_APERTURES \ AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) #define AMDKFD_IOC_UPDATE_QUEUE \ AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) #define AMDKFD_IOC_CREATE_EVENT \ AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) #define AMDKFD_IOC_DESTROY_EVENT \ AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) #define AMDKFD_IOC_SET_EVENT \ AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) #define AMDKFD_IOC_RESET_EVENT \ AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) #define AMDKFD_IOC_WAIT_EVENTS \ AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) #define AMDKFD_IOC_DBG_REGISTER_DEPRECATED \ AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) #define AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED \ AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) #define AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED \ AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) #define AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED \ AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \ AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args) #define AMDKFD_IOC_GET_TILE_CONFIG \ AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) #define AMDKFD_IOC_SET_TRAP_HANDLER \ AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args) #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \ AMDKFD_IOWR(0x14, \ struct kfd_ioctl_get_process_apertures_new_args) #define AMDKFD_IOC_ACQUIRE_VM \ AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args) #define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \ AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args) #define AMDKFD_IOC_FREE_MEMORY_OF_GPU \ AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args) #define AMDKFD_IOC_MAP_MEMORY_TO_GPU \ AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args) #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \ AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args) #define AMDKFD_IOC_SET_CU_MASK \ AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args) #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \ AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args) #define AMDKFD_IOC_GET_DMABUF_INFO \ AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args) #define AMDKFD_IOC_IMPORT_DMABUF \ AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args) #define AMDKFD_IOC_ALLOC_QUEUE_GWS \ AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args) #define AMDKFD_IOC_SMI_EVENTS \ AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args) #define AMDKFD_IOC_SVM AMDKFD_IOWR(0x20, struct kfd_ioctl_svm_args) #define AMDKFD_IOC_SET_XNACK_MODE \ AMDKFD_IOWR(0x21, struct kfd_ioctl_set_xnack_mode_args) #define AMDKFD_IOC_CRIU_OP \ AMDKFD_IOWR(0x22, struct kfd_ioctl_criu_args) #define AMDKFD_IOC_AVAILABLE_MEMORY \ AMDKFD_IOWR(0x23, struct kfd_ioctl_get_available_memory_args) #define AMDKFD_IOC_EXPORT_DMABUF \ AMDKFD_IOWR(0x24, struct kfd_ioctl_export_dmabuf_args) #define AMDKFD_IOC_RUNTIME_ENABLE \ AMDKFD_IOWR(0x25, struct kfd_ioctl_runtime_enable_args) #define AMDKFD_IOC_DBG_TRAP \ AMDKFD_IOWR(0x26, struct kfd_ioctl_dbg_trap_args) #define AMDKFD_COMMAND_START 0x01 #define AMDKFD_COMMAND_END 0x27 /* non-upstream ioctls */ #define AMDKFD_IOC_IPC_IMPORT_HANDLE \ AMDKFD_IOWR(0x80, struct kfd_ioctl_ipc_import_handle_args) #define AMDKFD_IOC_IPC_EXPORT_HANDLE \ AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) #define AMDKFD_IOC_CROSS_MEMORY_COPY \ AMDKFD_IOWR(0x83, struct kfd_ioctl_cross_memory_copy_args) #define AMDKFD_IOC_RLC_SPM \ AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) #define AMDKFD_COMMAND_START_2 0x80 #define AMDKFD_COMMAND_END_2 0x85 #endif ROCT-Thunk-Interface-rocm-5.7.0/libhsakmt.pc.in000066400000000000000000000004701446477712600211470ustar00rootroot00000000000000prefix=@CPACK_PACKAGING_INSTALL_PREFIX@ exec_prefix=${prefix} libdir=${prefix}/@CMAKE_INSTALL_LIBDIR@ includedir=${prefix}/@CMAKE_INSTALL_INCLUDEDIR@ Name: libhsakmt Description: HSA Kernel Mode Thunk library for AMD KFD support Version: @LIB_VERSION_STRING@ Libs: -L${libdir} -lhsakmt Cflags: -I${includedir} ROCT-Thunk-Interface-rocm-5.7.0/src/000077500000000000000000000000001446477712600170265ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/src/debug.c000066400000000000000000000331221446477712600202610ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "libhsakmt.h" #include "linux/kfd_ioctl.h" #include #include #include #include static bool *is_device_debugged; static uint32_t runtime_capabilities_mask = 0; HSAKMT_STATUS init_device_debugging_memory(unsigned int NumNodes) { unsigned int i; is_device_debugged = malloc(NumNodes * sizeof(bool)); if (!is_device_debugged) return HSAKMT_STATUS_NO_MEMORY; for (i = 0; i < NumNodes; i++) is_device_debugged[i] = false; return HSAKMT_STATUS_SUCCESS; } void destroy_device_debugging_memory(void) { if (is_device_debugged) { free(is_device_debugged); is_device_debugged = NULL; } } bool debug_get_reg_status(uint32_t node_id) { return is_device_debugged[node_id]; } HSAKMT_STATUS HSAKMTAPI hsaKmtDbgRegister(HSAuint32 NodeId) { HSAKMT_STATUS result; uint32_t gpu_id; CHECK_KFD_OPEN(); if (!is_device_debugged) return HSAKMT_STATUS_NO_MEMORY; result = validate_nodeid(NodeId, &gpu_id); if (result != HSAKMT_STATUS_SUCCESS) return result; struct kfd_ioctl_dbg_register_args args = {0}; args.gpu_id = gpu_id; long err = kmtIoctl(kfd_fd, AMDKFD_IOC_DBG_REGISTER_DEPRECATED, &args); if (err == 0) result = HSAKMT_STATUS_SUCCESS; else result = HSAKMT_STATUS_ERROR; return result; } HSAKMT_STATUS HSAKMTAPI hsaKmtDbgUnregister(HSAuint32 NodeId) { uint32_t gpu_id; HSAKMT_STATUS result; CHECK_KFD_OPEN(); if (!is_device_debugged) return HSAKMT_STATUS_NO_MEMORY; result = validate_nodeid(NodeId, &gpu_id); if (result != HSAKMT_STATUS_SUCCESS) return result; struct kfd_ioctl_dbg_unregister_args args = {0}; args.gpu_id = gpu_id; long err = kmtIoctl(kfd_fd, AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED, &args); if (err) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtDbgWavefrontControl(HSAuint32 NodeId, HSA_DBG_WAVEOP Operand, HSA_DBG_WAVEMODE Mode, HSAuint32 TrapId, HsaDbgWaveMessage *DbgWaveMsgRing) { HSAKMT_STATUS result; uint32_t gpu_id; struct kfd_ioctl_dbg_wave_control_args *args; CHECK_KFD_OPEN(); result = validate_nodeid(NodeId, &gpu_id); if (result != HSAKMT_STATUS_SUCCESS) return result; /* Determine Size of the ioctl buffer */ uint32_t buff_size = sizeof(Operand) + sizeof(Mode) + sizeof(TrapId) + sizeof(DbgWaveMsgRing->DbgWaveMsg) + sizeof(DbgWaveMsgRing->MemoryVA) + sizeof(*args); args = (struct kfd_ioctl_dbg_wave_control_args *)malloc(buff_size); if (!args) return HSAKMT_STATUS_ERROR; memset(args, 0, buff_size); args->gpu_id = gpu_id; args->buf_size_in_bytes = buff_size; /* increment pointer to the start of the non fixed part */ unsigned char *run_ptr = (unsigned char *)args + sizeof(*args); /* save variable content pointer for kfd */ args->content_ptr = (uint64_t)run_ptr; /* insert items, and increment pointer accordingly */ *((HSA_DBG_WAVEOP *)run_ptr) = Operand; run_ptr += sizeof(Operand); *((HSA_DBG_WAVEMODE *)run_ptr) = Mode; run_ptr += sizeof(Mode); *((HSAuint32 *)run_ptr) = TrapId; run_ptr += sizeof(TrapId); *((HsaDbgWaveMessageAMD *)run_ptr) = DbgWaveMsgRing->DbgWaveMsg; run_ptr += sizeof(DbgWaveMsgRing->DbgWaveMsg); *((void **)run_ptr) = DbgWaveMsgRing->MemoryVA; run_ptr += sizeof(DbgWaveMsgRing->MemoryVA); /* send to kernel */ long err = kmtIoctl(kfd_fd, AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED, args); free(args); if (err) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtDbgAddressWatch(HSAuint32 NodeId, HSAuint32 NumWatchPoints, HSA_DBG_WATCH_MODE WatchMode[], void *WatchAddress[], HSAuint64 WatchMask[], HsaEvent *WatchEvent[]) { HSAKMT_STATUS result; uint32_t gpu_id; /* determine the size of the watch mask and event buffers * the value is NULL if and only if no vector data should be attached */ uint32_t watch_mask_items = WatchMask[0] > 0 ? NumWatchPoints:1; uint32_t watch_event_items = WatchEvent != NULL ? NumWatchPoints:0; struct kfd_ioctl_dbg_address_watch_args *args; HSAuint32 i = 0; CHECK_KFD_OPEN(); result = validate_nodeid(NodeId, &gpu_id); if (result != HSAKMT_STATUS_SUCCESS) return result; if (NumWatchPoints > MAX_ALLOWED_NUM_POINTS) return HSAKMT_STATUS_INVALID_PARAMETER; /* Size and structure of the ioctl buffer is dynamic in this case * Here we calculate the buff size. */ uint32_t buff_size = sizeof(NumWatchPoints) + (sizeof(WatchMode[0]) + sizeof(WatchAddress[0])) * NumWatchPoints + watch_mask_items * sizeof(HSAuint64) + watch_event_items * sizeof(HsaEvent *) + sizeof(*args); args = (struct kfd_ioctl_dbg_address_watch_args *) malloc(buff_size); if (!args) return HSAKMT_STATUS_ERROR; memset(args, 0, buff_size); args->gpu_id = gpu_id; args->buf_size_in_bytes = buff_size; /* increment pointer to the start of the non fixed part */ unsigned char *run_ptr = (unsigned char *)args + sizeof(*args); /* save variable content pointer for kfd */ args->content_ptr = (uint64_t)run_ptr; /* insert items, and increment pointer accordingly */ *((HSAuint32 *)run_ptr) = NumWatchPoints; run_ptr += sizeof(NumWatchPoints); for (i = 0; i < NumWatchPoints; i++) { *((HSA_DBG_WATCH_MODE *)run_ptr) = WatchMode[i]; run_ptr += sizeof(WatchMode[i]); } for (i = 0; i < NumWatchPoints; i++) { *((void **)run_ptr) = WatchAddress[i]; run_ptr += sizeof(WatchAddress[i]); } for (i = 0; i < watch_mask_items; i++) { *((HSAuint64 *)run_ptr) = WatchMask[i]; run_ptr += sizeof(WatchMask[i]); } for (i = 0; i < watch_event_items; i++) { *((HsaEvent **)run_ptr) = WatchEvent[i]; run_ptr += sizeof(WatchEvent[i]); } /* send to kernel */ long err = kmtIoctl(kfd_fd, AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED, args); free(args); if (err) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } #define HSA_RUNTIME_ENABLE_MAX_MAJOR 1 #define HSA_RUNTIME_ENABLE_MIN_MINOR 13 static HSAKMT_STATUS checkRuntimeDebugSupport(void) { HsaNodeProperties node = {0}; HsaSystemProperties props = {0}; HsaVersionInfo versionInfo = {0}; memset(&node, 0x00, sizeof(node)); memset(&props, 0x00, sizeof(props)); if (hsaKmtAcquireSystemProperties(&props)) return HSAKMT_STATUS_ERROR; //the firmware of gpu node doesn't support the debugger, disable it. for (uint32_t i = 0; i < props.NumNodes; i++) { if (hsaKmtGetNodeProperties(i, &node)) return HSAKMT_STATUS_ERROR; //ignore cpu node if (node.NumCPUCores) continue; if (!node.Capability.ui32.DebugSupportedFirmware) return HSAKMT_STATUS_NOT_SUPPORTED; } if (hsaKmtGetVersion(&versionInfo)) return HSAKMT_STATUS_NOT_SUPPORTED; if (versionInfo.KernelInterfaceMajorVersion < HSA_RUNTIME_ENABLE_MAX_MAJOR || (versionInfo.KernelInterfaceMajorVersion == HSA_RUNTIME_ENABLE_MAX_MAJOR && (int)versionInfo.KernelInterfaceMinorVersion < HSA_RUNTIME_ENABLE_MIN_MINOR)) return HSAKMT_STATUS_NOT_SUPPORTED; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtRuntimeEnable(void *rDebug, bool setupTtmp) { struct kfd_ioctl_runtime_enable_args args = {0}; HSAKMT_STATUS result = checkRuntimeDebugSupport(); if (result) return result; memset(&args, 0x00, sizeof(args)); args.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK | ((setupTtmp) ? KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK : 0); args.r_debug = (HSAuint64)rDebug; long err = kmtIoctl(kfd_fd, AMDKFD_IOC_RUNTIME_ENABLE, &args); if (err) { if (errno == EBUSY) return HSAKMT_STATUS_UNAVAILABLE; else return HSAKMT_STATUS_ERROR; } runtime_capabilities_mask= args.capabilities_mask; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtRuntimeDisable(void) { struct kfd_ioctl_runtime_enable_args args = {0}; HSAKMT_STATUS result = checkRuntimeDebugSupport(); if (result) return result; memset(&args, 0x00, sizeof(args)); args.mode_mask = 0; //Disable if (kmtIoctl(kfd_fd, AMDKFD_IOC_RUNTIME_ENABLE, &args)) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtGetRuntimeCapabilities(HSAuint32 *caps_mask) { *caps_mask = runtime_capabilities_mask; return HSAKMT_STATUS_SUCCESS; } static HSAKMT_STATUS dbg_trap_get_device_data(void *data, uint32_t *n_entries, uint32_t entry_size) { struct kfd_ioctl_dbg_trap_args args = {0}; args.device_snapshot.snapshot_buf_ptr = (uint64_t) data; args.device_snapshot.num_devices = *n_entries; args.device_snapshot.entry_size = entry_size; args.op = KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT; args.pid = getpid(); if (kmtIoctl(kfd_fd, AMDKFD_IOC_DBG_TRAP, &args)) return HSAKMT_STATUS_ERROR; *n_entries = args.device_snapshot.num_devices; return HSAKMT_STATUS_SUCCESS; } static HSAKMT_STATUS dbg_trap_get_queue_data(void *data, uint32_t *n_entries, uint32_t entry_size, uint32_t *queue_ids) { struct kfd_ioctl_dbg_trap_args args = {0}; args.queue_snapshot.num_queues = *n_entries; args.queue_snapshot.entry_size = entry_size; args.queue_snapshot.exception_mask = KFD_EC_MASK(EC_QUEUE_NEW); args.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; args.queue_snapshot.snapshot_buf_ptr = (uint64_t) data; args.pid = getpid(); if (kmtIoctl(kfd_fd, AMDKFD_IOC_DBG_TRAP, &args)) return HSAKMT_STATUS_ERROR; *n_entries = args.queue_snapshot.num_queues; if (queue_ids && *n_entries) { struct kfd_queue_snapshot_entry *queue_entry = (struct kfd_queue_snapshot_entry *) data; for (uint32_t i = 0; i < *n_entries; i++) queue_ids[i] = queue_entry[i].queue_id; } return HSAKMT_STATUS_SUCCESS; } static HSAKMT_STATUS dbg_trap_suspend_queues(uint32_t *queue_ids, uint32_t num_queues) { struct kfd_ioctl_dbg_trap_args args = {0}; int r; args.suspend_queues.queue_array_ptr = (uint64_t) queue_ids; args.suspend_queues.num_queues = num_queues; args.suspend_queues.exception_mask = KFD_EC_MASK(EC_QUEUE_NEW); args.op = KFD_IOC_DBG_TRAP_SUSPEND_QUEUES; args.pid = getpid(); r = kmtIoctl(kfd_fd, AMDKFD_IOC_DBG_TRAP, &args); if (r < 0) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtDbgEnable(void **runtime_info, HSAuint32 *data_size) { struct kfd_ioctl_dbg_trap_args args = {0}; CHECK_KFD_OPEN(); CHECK_KFD_MINOR_VERSION(KFD_IOCTL_MINOR_VERSION); *data_size = sizeof(struct kfd_runtime_info); args.enable.rinfo_size = *data_size; args.enable.dbg_fd = kfd_fd; *runtime_info = malloc(args.enable.rinfo_size); if (!*runtime_info) return HSAKMT_STATUS_NO_MEMORY; args.enable.rinfo_ptr = (uint64_t) *runtime_info; args.op = KFD_IOC_DBG_TRAP_ENABLE; args.pid = getpid(); if (kmtIoctl(kfd_fd, AMDKFD_IOC_DBG_TRAP, &args)) { free(*runtime_info); return HSAKMT_STATUS_ERROR; } return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtDbgDisable(void) { struct kfd_ioctl_dbg_trap_args args = {0}; CHECK_KFD_OPEN(); CHECK_KFD_MINOR_VERSION(KFD_IOCTL_MINOR_VERSION); args.enable.dbg_fd = kfd_fd; args.op = KFD_IOC_DBG_TRAP_DISABLE; args.pid = getpid(); if (kmtIoctl(kfd_fd, AMDKFD_IOC_DBG_TRAP, &args)) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtDbgGetDeviceData(void **data, HSAuint32 *n_entries, HSAuint32 *entry_size) { HSAKMT_STATUS ret = HSAKMT_STATUS_NO_MEMORY; CHECK_KFD_OPEN(); CHECK_KFD_MINOR_VERSION(KFD_IOCTL_MINOR_VERSION); *n_entries = UINT32_MAX; *entry_size = sizeof(struct kfd_dbg_device_info_entry); *data = malloc(*entry_size * *n_entries); if (!*data) return ret; ret = dbg_trap_get_device_data(*data, n_entries, *entry_size); if (ret) free(*data); return ret; } HSAKMT_STATUS HSAKMTAPI hsaKmtDbgGetQueueData(void **data, HSAuint32 *n_entries, HSAuint32 *entry_size, bool suspend_queues) { uint32_t *queue_ids = NULL; CHECK_KFD_OPEN(); CHECK_KFD_MINOR_VERSION(KFD_IOCTL_MINOR_VERSION); *entry_size = sizeof(struct kfd_queue_snapshot_entry); *n_entries = 0; if (dbg_trap_get_queue_data(NULL, n_entries, *entry_size, NULL)) return HSAKMT_STATUS_ERROR; *data = malloc(*n_entries * *entry_size); if (!*data) return HSAKMT_STATUS_NO_MEMORY; if (suspend_queues && *n_entries) queue_ids = (uint32_t *)malloc(sizeof(uint32_t) * *n_entries); if (!queue_ids || dbg_trap_get_queue_data(*data, n_entries, *entry_size, queue_ids)) goto free_data; if (queue_ids) { if (dbg_trap_suspend_queues(queue_ids, *n_entries) || dbg_trap_get_queue_data(*data, n_entries, *entry_size, NULL)) goto free_data; free(queue_ids); } return HSAKMT_STATUS_SUCCESS; free_data: free(*data); if (queue_ids) free(queue_ids); return HSAKMT_STATUS_ERROR; } ROCT-Thunk-Interface-rocm-5.7.0/src/events.c000066400000000000000000000337631446477712600205120ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "libhsakmt.h" #include #include #include #include #include #include #include #include "linux/kfd_ioctl.h" #include "fmm.h" static HSAuint64 *events_page = NULL; void clear_events_page(void) { events_page = NULL; } static bool IsSystemEventType(HSA_EVENTTYPE type) { // Debug events behave as signal events. return (type != HSA_EVENTTYPE_SIGNAL && type != HSA_EVENTTYPE_DEBUG_EVENT); } HSAKMT_STATUS HSAKMTAPI hsaKmtCreateEvent(HsaEventDescriptor *EventDesc, bool ManualReset, bool IsSignaled, HsaEvent **Event) { unsigned int event_limit = KFD_SIGNAL_EVENT_LIMIT; CHECK_KFD_OPEN(); if (EventDesc->EventType >= HSA_EVENTTYPE_MAXID) return HSAKMT_STATUS_INVALID_PARAMETER; HsaEvent *e = malloc(sizeof(HsaEvent)); if (!e) return HSAKMT_STATUS_ERROR; memset(e, 0, sizeof(*e)); struct kfd_ioctl_create_event_args args = {0}; args.event_type = EventDesc->EventType; args.node_id = EventDesc->NodeId; args.auto_reset = !ManualReset; /* dGPU code */ pthread_mutex_lock(&hsakmt_mutex); if (is_dgpu && !events_page) { events_page = allocate_exec_aligned_memory_gpu( KFD_SIGNAL_EVENT_LIMIT * 8, PAGE_SIZE, 0, true, false, true); if (!events_page) { pthread_mutex_unlock(&hsakmt_mutex); return HSAKMT_STATUS_ERROR; } fmm_get_handle(events_page, (uint64_t *)&args.event_page_offset); } if (kmtIoctl(kfd_fd, AMDKFD_IOC_CREATE_EVENT, &args) != 0) { free(e); *Event = NULL; pthread_mutex_unlock(&hsakmt_mutex); return HSAKMT_STATUS_ERROR; } e->EventId = args.event_id; if (!events_page && args.event_page_offset > 0) { events_page = mmap(NULL, event_limit * 8, PROT_WRITE | PROT_READ, MAP_SHARED, kfd_fd, args.event_page_offset); if (events_page == MAP_FAILED) { /* old kernels only support 256 events */ event_limit = 256; events_page = mmap(NULL, PAGE_SIZE, PROT_WRITE | PROT_READ, MAP_SHARED, kfd_fd, args.event_page_offset); } if (events_page == MAP_FAILED) { events_page = NULL; pthread_mutex_unlock(&hsakmt_mutex); hsaKmtDestroyEvent(e); return HSAKMT_STATUS_ERROR; } } pthread_mutex_unlock(&hsakmt_mutex); if (args.event_page_offset > 0 && args.event_slot_index < event_limit) e->EventData.HWData2 = (HSAuint64)&events_page[args.event_slot_index]; e->EventData.EventType = EventDesc->EventType; e->EventData.HWData1 = args.event_id; e->EventData.HWData3 = args.event_trigger_data; e->EventData.EventData.SyncVar.SyncVar.UserData = EventDesc->SyncVar.SyncVar.UserData; e->EventData.EventData.SyncVar.SyncVarSize = EventDesc->SyncVar.SyncVarSize; if (IsSignaled && !IsSystemEventType(e->EventData.EventType)) { struct kfd_ioctl_set_event_args set_args = {0}; set_args.event_id = args.event_id; kmtIoctl(kfd_fd, AMDKFD_IOC_SET_EVENT, &set_args); } *Event = e; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtDestroyEvent(HsaEvent *Event) { CHECK_KFD_OPEN(); if (!Event) return HSAKMT_STATUS_INVALID_HANDLE; struct kfd_ioctl_destroy_event_args args = {0}; args.event_id = Event->EventId; if (kmtIoctl(kfd_fd, AMDKFD_IOC_DESTROY_EVENT, &args) != 0) return HSAKMT_STATUS_ERROR; free(Event); return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtSetEvent(HsaEvent *Event) { CHECK_KFD_OPEN(); if (!Event) return HSAKMT_STATUS_INVALID_HANDLE; /* Although the spec is doesn't say, don't allow system-defined events * to be signaled. */ if (IsSystemEventType(Event->EventData.EventType)) return HSAKMT_STATUS_ERROR; struct kfd_ioctl_set_event_args args = {0}; args.event_id = Event->EventId; if (kmtIoctl(kfd_fd, AMDKFD_IOC_SET_EVENT, &args) == -1) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtResetEvent(HsaEvent *Event) { CHECK_KFD_OPEN(); if (!Event) return HSAKMT_STATUS_INVALID_HANDLE; /* Although the spec is doesn't say, don't allow system-defined events * to be signaled. */ if (IsSystemEventType(Event->EventData.EventType)) return HSAKMT_STATUS_ERROR; struct kfd_ioctl_reset_event_args args = {0}; args.event_id = Event->EventId; if (kmtIoctl(kfd_fd, AMDKFD_IOC_RESET_EVENT, &args) == -1) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtQueryEventState(HsaEvent *Event) { CHECK_KFD_OPEN(); if (!Event) return HSAKMT_STATUS_INVALID_HANDLE; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtWaitOnEvent(HsaEvent *Event, HSAuint32 Milliseconds) { return hsaKmtWaitOnEvent_Ext(Event, Milliseconds, NULL); } HSAKMT_STATUS HSAKMTAPI hsaKmtWaitOnEvent_Ext(HsaEvent *Event, HSAuint32 Milliseconds, uint64_t *event_age) { if (!Event) return HSAKMT_STATUS_INVALID_HANDLE; return hsaKmtWaitOnMultipleEvents_Ext(&Event, 1, true, Milliseconds, event_age); } static HSAKMT_STATUS get_mem_info_svm_api(uint64_t address, uint32_t gpu_id) { struct kfd_ioctl_svm_args *args; uint32_t node_id; HSAuint32 s_attr; HSAuint32 i; HSA_SVM_ATTRIBUTE attrs[] = { {HSA_SVM_ATTR_PREFERRED_LOC, 0}, {HSA_SVM_ATTR_PREFETCH_LOC, 0}, {HSA_SVM_ATTR_ACCESS, gpu_id}, {HSA_SVM_ATTR_SET_FLAGS, 0}, }; CHECK_KFD_OPEN(); CHECK_KFD_MINOR_VERSION(5); s_attr = sizeof(attrs); args = alloca(sizeof(*args) + s_attr); args->start_addr = address; args->size = PAGE_SIZE; args->op = KFD_IOCTL_SVM_OP_GET_ATTR; args->nattr = s_attr / sizeof(*attrs); memcpy(args->attrs, attrs, s_attr); if (kmtIoctl(kfd_fd, AMDKFD_IOC_SVM + (s_attr << _IOC_SIZESHIFT), args)) { pr_debug("op get range attrs failed %s\n", strerror(errno)); return HSAKMT_STATUS_ERROR; } pr_err("GPU address 0x%lx, is Unified memory\n", address); for (i = 0; i < args->nattr; i++) { if (args->attrs[i].value == KFD_IOCTL_SVM_LOCATION_SYSMEM || args->attrs[i].value == KFD_IOCTL_SVM_LOCATION_UNDEFINED) node_id = args->attrs[i].value; else gpuid_to_nodeid(args->attrs[i].value, &node_id); switch (args->attrs[i].type) { case KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: pr_err("Preferred location for address 0x%lx is Node id %d\n", address, node_id); break; case KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: pr_err("Prefetch location for address 0x%lx is Node id %d\n", address, node_id); break; case KFD_IOCTL_SVM_ATTR_ACCESS: pr_err("Node id %d has access to address 0x%lx\n", node_id, address); break; case KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE: pr_err("Node id %d has access in place to address 0x%lx\n", node_id, address); break; case KFD_IOCTL_SVM_ATTR_NO_ACCESS: pr_err("Node id %d has no access to address 0x%lx\n", node_id, address); break; case KFD_IOCTL_SVM_ATTR_SET_FLAGS: if (args->attrs[i].value & KFD_IOCTL_SVM_FLAG_COHERENT) pr_err("Fine grained coherency between devices\n"); if (args->attrs[i].value & KFD_IOCTL_SVM_FLAG_GPU_RO) pr_err("Read only\n"); if (args->attrs[i].value & KFD_IOCTL_SVM_FLAG_GPU_EXEC) pr_err("GPU exec allowed\n"); if (args->attrs[i].value & KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED) pr_err("GPU always mapped\n"); break; default: pr_debug("get invalid attr type 0x%x\n", args->attrs[i].type); return HSAKMT_STATUS_ERROR; } } return HSAKMT_STATUS_SUCCESS; } //Analysis memory exception data, print debug messages static void analysis_memory_exception(struct kfd_hsa_memory_exception_data * memory_exception_data) { HSAKMT_STATUS ret; HsaPointerInfo info; const uint64_t addr = memory_exception_data->va; uint32_t node_id = 0; unsigned int i; gpuid_to_nodeid(memory_exception_data->gpu_id, &node_id); pr_err("Memory exception on virtual address 0x%lx, ", addr); pr_err("node id %d : ", node_id); if (memory_exception_data->failure.NotPresent) pr_err("Page not present\n"); else if (memory_exception_data->failure.ReadOnly) pr_err("Writing to readonly page\n"); else if (memory_exception_data->failure.NoExecute) pr_err("Execute to none-executable page\n"); ret = fmm_get_mem_info((const void *)addr, &info); if (ret != HSAKMT_STATUS_SUCCESS) { ret = get_mem_info_svm_api(addr, memory_exception_data->gpu_id); if (ret != HSAKMT_STATUS_SUCCESS) pr_err("Address does not belong to a known buffer\n"); return; } pr_err("GPU address 0x%lx, node id %d, size in byte 0x%lx\n", info.GPUAddress, info.Node, info.SizeInBytes); switch (info.Type) { case HSA_POINTER_REGISTERED_SHARED: pr_err("Memory is registered shared buffer (IPC)\n"); break; case HSA_POINTER_REGISTERED_GRAPHICS: pr_err("Memory is registered graphics buffer\n"); break; case HSA_POINTER_REGISTERED_USER: pr_err("Memory is registered user pointer\n"); pr_err("CPU address of the memory is %p\n", info.CPUAddress); break; case HSA_POINTER_ALLOCATED: pr_err("Memory is allocated using hsaKmtAllocMemory\n"); pr_err("CPU address of the memory is %p\n", info.CPUAddress); break; case HSA_POINTER_RESERVED_ADDR: pr_err("Memory is allocated by OnlyAddress mode\n"); break; default: pr_err("Invalid memory type %d\n", info.Type); break; } if (info.RegisteredNodes) { pr_err("Memory is registered to node id: "); for (i = 0; i < info.NRegisteredNodes; i++) pr_err("%d ", info.RegisteredNodes[i]); pr_err("\n"); } if (info.MappedNodes) { pr_err("Memory is mapped to node id: "); for (i = 0; i < info.NMappedNodes; i++) pr_err("%d ", info.MappedNodes[i]); pr_err("\n"); } } HSAKMT_STATUS HSAKMTAPI hsaKmtWaitOnMultipleEvents(HsaEvent *Events[], HSAuint32 NumEvents, bool WaitOnAll, HSAuint32 Milliseconds) { return hsaKmtWaitOnMultipleEvents_Ext(Events, NumEvents, WaitOnAll, Milliseconds, NULL); } HSAKMT_STATUS HSAKMTAPI hsaKmtWaitOnMultipleEvents_Ext(HsaEvent *Events[], HSAuint32 NumEvents, bool WaitOnAll, HSAuint32 Milliseconds, uint64_t *event_age) { CHECK_KFD_OPEN(); if (!Events) return HSAKMT_STATUS_INVALID_HANDLE; struct kfd_event_data *event_data = calloc(NumEvents, sizeof(struct kfd_event_data)); for (HSAuint32 i = 0; i < NumEvents; i++) { event_data[i].event_id = Events[i]->EventId; event_data[i].kfd_event_data_ext = (uint64_t)(uintptr_t)NULL; if (event_age && Events[i]->EventData.EventType == HSA_EVENTTYPE_SIGNAL) event_data[i].signal_event_data.last_event_age = event_age[i]; } struct kfd_ioctl_wait_events_args args = {0}; args.wait_for_all = WaitOnAll; args.timeout = Milliseconds; args.num_events = NumEvents; args.events_ptr = (uint64_t)(uintptr_t)event_data; HSAKMT_STATUS result; if (kmtIoctl(kfd_fd, AMDKFD_IOC_WAIT_EVENTS, &args) == -1) result = HSAKMT_STATUS_ERROR; else if (args.wait_result == KFD_IOC_WAIT_RESULT_TIMEOUT) result = HSAKMT_STATUS_WAIT_TIMEOUT; else { result = HSAKMT_STATUS_SUCCESS; for (HSAuint32 i = 0; i < NumEvents; i++) { if (Events[i]->EventData.EventType == HSA_EVENTTYPE_MEMORY && event_data[i].memory_exception_data.gpu_id) { Events[i]->EventData.EventData.MemoryAccessFault.VirtualAddress = event_data[i].memory_exception_data.va; result = gpuid_to_nodeid(event_data[i].memory_exception_data.gpu_id, &Events[i]->EventData.EventData.MemoryAccessFault.NodeId); if (result != HSAKMT_STATUS_SUCCESS) goto out; Events[i]->EventData.EventData.MemoryAccessFault.Failure.NotPresent = event_data[i].memory_exception_data.failure.NotPresent; Events[i]->EventData.EventData.MemoryAccessFault.Failure.ReadOnly = event_data[i].memory_exception_data.failure.ReadOnly; Events[i]->EventData.EventData.MemoryAccessFault.Failure.NoExecute = event_data[i].memory_exception_data.failure.NoExecute; Events[i]->EventData.EventData.MemoryAccessFault.Failure.Imprecise = event_data[i].memory_exception_data.failure.imprecise; Events[i]->EventData.EventData.MemoryAccessFault.Failure.ErrorType = event_data[i].memory_exception_data.ErrorType; Events[i]->EventData.EventData.MemoryAccessFault.Failure.ECC = ((event_data[i].memory_exception_data.ErrorType == 1) || (event_data[i].memory_exception_data.ErrorType == 2)) ? 1 : 0; Events[i]->EventData.EventData.MemoryAccessFault.Flags = HSA_EVENTID_MEMORY_FATAL_PROCESS; analysis_memory_exception(&event_data[i].memory_exception_data); } } } out: for (HSAuint32 i = 0; i < NumEvents; i++) { if (event_age && Events[i]->EventData.EventType == HSA_EVENTTYPE_SIGNAL) event_age[i] = event_data[i].signal_event_data.last_event_age; } free(event_data); return result; } HSAKMT_STATUS HSAKMTAPI hsaKmtOpenSMI(HSAuint32 NodeId, int *fd) { struct kfd_ioctl_smi_events_args args; HSAKMT_STATUS result; uint32_t gpuid; CHECK_KFD_OPEN(); pr_debug("[%s] node %d\n", __func__, NodeId); result = validate_nodeid(NodeId, &gpuid); if (result != HSAKMT_STATUS_SUCCESS) { pr_err("[%s] invalid node ID: %d\n", __func__, NodeId); return result; } args.gpuid = gpuid; result = kmtIoctl(kfd_fd, AMDKFD_IOC_SMI_EVENTS, &args); if (result) { pr_debug("open SMI event fd failed %s\n", strerror(errno)); return HSAKMT_STATUS_ERROR; } *fd = args.anon_fd; return HSAKMT_STATUS_SUCCESS; } ROCT-Thunk-Interface-rocm-5.7.0/src/fmm.c000066400000000000000000003623731446477712600177670ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "libhsakmt.h" #include "fmm.h" #include "linux/kfd_ioctl.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include "rbtree.h" #include #ifndef MPOL_F_STATIC_NODES /* Bug in numaif.h, this should be defined in there. Definition copied * from linux/mempolicy.h. */ #define MPOL_F_STATIC_NODES (1 << 15) #endif #define NON_VALID_GPU_ID 0 #define INIT_MANAGEABLE_APERTURE(base_value, limit_value) { \ .base = (void *) base_value, \ .limit = (void *) limit_value, \ .align = 0, \ .guard_pages = 1, \ .vm_ranges = NULL, \ .fmm_mutex = PTHREAD_MUTEX_INITIALIZER, \ .is_cpu_accessible = false, \ .ops = &reserved_aperture_ops \ } #define container_of(ptr, type, member) ({ \ char *__mptr = (void *)(ptr); \ ((type *)(__mptr - offsetof(type, member))); }) #define rb_entry(ptr, type, member) \ container_of(ptr, type, member) #define vm_object_entry(n, is_userptr) ({ \ (is_userptr) == 0 ? \ rb_entry(n, vm_object_t, node) : \ rb_entry(n, vm_object_t, user_node); }) #define vm_object_tree(app, is_userptr) \ ((is_userptr) ? &(app)->user_tree : &(app)->tree) #define START_NON_CANONICAL_ADDR (1ULL << 47) #define END_NON_CANONICAL_ADDR (~0UL - (1UL << 47)) struct vm_object { void *start; void *userptr; uint64_t userptr_size; uint64_t size; /* size allocated on GPU. When the user requests a random * size, Thunk aligns it to page size and allocates this * aligned size on GPU */ uint64_t handle; /* opaque */ uint32_t node_id; rbtree_node_t node; rbtree_node_t user_node; HsaMemFlags mflags; /* memory allocation flags */ /* Registered nodes to map on SVM mGPU */ uint32_t *registered_device_id_array; uint32_t registered_device_id_array_size; uint32_t *registered_node_id_array; uint32_t registration_count; /* the same memory region can be registered multiple times */ /* Nodes that mapped already */ uint32_t *mapped_device_id_array; uint32_t mapped_device_id_array_size; uint32_t *mapped_node_id_array; uint32_t mapping_count; /* Metadata of imported graphics buffers */ void *metadata; /* User data associated with the memory */ void *user_data; /* Flag to indicate imported KFD buffer */ bool is_imported_kfd_bo; #ifdef SANITIZER_AMDGPU int mmap_flags; int mmap_fd; off_t mmap_offset; #endif }; typedef struct vm_object vm_object_t; struct vm_area { void *start; void *end; struct vm_area *next; struct vm_area *prev; }; typedef struct vm_area vm_area_t; /* Memory manager for an aperture */ typedef struct manageable_aperture manageable_aperture_t; /* Aperture management function pointers to allow different management * schemes. */ typedef struct { void *(*allocate_area_aligned)(manageable_aperture_t *aper, void *addr, uint64_t size, uint64_t align); void (*release_area)(manageable_aperture_t *aper, void *addr, uint64_t size); } manageable_aperture_ops_t; /* Reserved aperture type managed by its own address allocator */ static void *reserved_aperture_allocate_aligned(manageable_aperture_t *aper, void *addr, uint64_t size, uint64_t align); static void reserved_aperture_release(manageable_aperture_t *aper, void *addr, uint64_t size); static const manageable_aperture_ops_t reserved_aperture_ops = { reserved_aperture_allocate_aligned, reserved_aperture_release }; /* Unreserved aperture type using mmap to allocate virtual address space */ static void *mmap_aperture_allocate_aligned(manageable_aperture_t *aper, void *addr, uint64_t size, uint64_t align); static void mmap_aperture_release(manageable_aperture_t *aper, void *addr, uint64_t size); static const manageable_aperture_ops_t mmap_aperture_ops = { mmap_aperture_allocate_aligned, mmap_aperture_release }; struct manageable_aperture { void *base; void *limit; uint64_t align; uint32_t guard_pages; vm_area_t *vm_ranges; rbtree_t tree; rbtree_t user_tree; pthread_mutex_t fmm_mutex; bool is_cpu_accessible; const manageable_aperture_ops_t *ops; }; typedef struct { void *base; void *limit; } aperture_t; typedef struct { uint32_t gpu_id; uint32_t device_id; uint32_t node_id; uint64_t local_mem_size; HSA_ENGINE_ID EngineId; aperture_t lds_aperture; aperture_t scratch_aperture; aperture_t mmio_aperture; manageable_aperture_t scratch_physical; /* For dGPU, scratch physical is allocated from * dgpu_aperture. When requested by RT, each * GPU will get a differnt range */ manageable_aperture_t gpuvm_aperture; /* used for GPUVM on APU, outsidethe canonical address range */ int drm_render_fd; uint32_t usable_peer_id_num; uint32_t *usable_peer_id_array; int drm_render_minor; } gpu_mem_t; enum svm_aperture_type { SVM_DEFAULT = 0, SVM_COHERENT, SVM_APERTURE_NUM }; /* The main structure for dGPU Shared Virtual Memory Management */ typedef struct { /* Two apertures can have different MTypes (for coherency) */ manageable_aperture_t apertures[SVM_APERTURE_NUM]; /* Pointers to apertures, may point to the same aperture on * GFXv9 and later, where MType is not based on apertures */ manageable_aperture_t *dgpu_aperture; manageable_aperture_t *dgpu_alt_aperture; /* whether to use userptr for paged memory */ bool userptr_for_paged_mem; /* whether to check userptrs on registration */ bool check_userptr; /* whether to check reserve svm on registration */ bool reserve_svm; /* whether all memory is coherent (GPU cache disabled) */ bool disable_cache; /* specifies the alignment size as PAGE_SIZE * 2^alignment_order */ uint32_t alignment_order; /* whether to check all dGPUs in the topology support SVM API */ bool is_svm_api_supported; } svm_t; /* The other apertures are specific to each GPU. gpu_mem_t manages GPU * specific memory apertures. */ static gpu_mem_t *gpu_mem; static unsigned int gpu_mem_count; static gpu_mem_t *g_first_gpu_mem; static void *dgpu_shared_aperture_base; static void *dgpu_shared_aperture_limit; static svm_t svm = { .apertures = {INIT_MANAGEABLE_APERTURE(0, 0), INIT_MANAGEABLE_APERTURE(0, 0)}, .dgpu_aperture = NULL, .dgpu_alt_aperture = NULL, .userptr_for_paged_mem = false, .check_userptr = false, .disable_cache = false, .is_svm_api_supported = false }; /* On APU, for memory allocated on the system memory that GPU doesn't access * via GPU driver, they are not managed by GPUVM. cpuvm_aperture keeps track * of this part of memory. */ static manageable_aperture_t cpuvm_aperture = INIT_MANAGEABLE_APERTURE(0, 0); /* mem_handle_aperture is used to generate memory handles * for allocations that don't have a valid virtual address * its size is 47bits. */ static manageable_aperture_t mem_handle_aperture = INIT_MANAGEABLE_APERTURE(START_NON_CANONICAL_ADDR, (START_NON_CANONICAL_ADDR + (1ULL << 47))); /* GPU node array for default mappings */ static uint32_t all_gpu_id_array_size; static uint32_t *all_gpu_id_array; /* IPC structures and helper functions */ typedef enum _HSA_APERTURE { HSA_APERTURE_UNSUPPORTED = 0, HSA_APERTURE_DGPU, HSA_APERTURE_DGPU_ALT, HSA_APERTURE_GPUVM, HSA_APERTURE_CPUVM, HSA_APERTURE_MEMHANDLE } HSA_APERTURE; typedef struct _HsaApertureInfo { HSA_APERTURE type; // Aperture type HSAuint32 idx; // Aperture index } HsaApertureInfo; typedef struct _HsaSharedMemoryStruct { HSAuint32 ShareHandle[4]; HsaApertureInfo ApeInfo; HSAuint32 SizeInPages; HSAuint32 ExportGpuId; } HsaSharedMemoryStruct; static inline const HsaSharedMemoryStruct *to_const_hsa_shared_memory_struct( const HsaSharedMemoryHandle *SharedMemoryHandle) { return (const HsaSharedMemoryStruct *)SharedMemoryHandle; } static inline HsaSharedMemoryStruct *to_hsa_shared_memory_struct( HsaSharedMemoryHandle *SharedMemoryHandle) { return (HsaSharedMemoryStruct *)SharedMemoryHandle; } __attribute__((unused)) static inline HsaSharedMemoryHandle *to_hsa_shared_memory_handle( HsaSharedMemoryStruct *SharedMemoryStruct) { return (HsaSharedMemoryHandle *)SharedMemoryStruct; } static int __fmm_release(vm_object_t *object, manageable_aperture_t *aperture); static int _fmm_unmap_from_gpu_scratch(uint32_t gpu_id, manageable_aperture_t *aperture, void *address); static void print_device_id_array(uint32_t *device_id_array, uint32_t device_id_array_size); static vm_area_t *vm_create_and_init_area(void *start, void *end) { vm_area_t *area = (vm_area_t *) malloc(sizeof(vm_area_t)); if (area) { area->start = start; area->end = end; area->next = area->prev = NULL; } return area; } static vm_object_t *vm_create_and_init_object(void *start, uint64_t size, uint64_t handle, HsaMemFlags mflags) { vm_object_t *object = (vm_object_t *) malloc(sizeof(vm_object_t)); if (object) { object->start = start; object->userptr = NULL; object->userptr_size = 0; object->size = size; object->handle = handle; object->registered_device_id_array_size = 0; object->mapped_device_id_array_size = 0; object->registered_device_id_array = NULL; object->mapped_device_id_array = NULL; object->registered_node_id_array = NULL; object->mapped_node_id_array = NULL; object->registration_count = 0; object->mapping_count = 0; object->mflags = mflags; object->metadata = NULL; object->user_data = NULL; object->is_imported_kfd_bo = false; object->node.key = rbtree_key((unsigned long)start, size); object->user_node.key = rbtree_key(0, 0); #ifdef SANITIZER_AMDGPU object->mmap_fd = 0; #endif } return object; } static void vm_remove_area(manageable_aperture_t *app, vm_area_t *area) { vm_area_t *next; vm_area_t *prev; next = area->next; prev = area->prev; if (!prev) /* The first element */ app->vm_ranges = next; else prev->next = next; if (next) /* If not the last element */ next->prev = prev; free(area); } static void vm_remove_object(manageable_aperture_t *app, vm_object_t *object) { /* Free allocations inside the object */ if (object->registered_device_id_array) free(object->registered_device_id_array); if (object->mapped_device_id_array) free(object->mapped_device_id_array); if (object->metadata) free(object->metadata); if (object->registered_node_id_array) free(object->registered_node_id_array); if (object->mapped_node_id_array) free(object->mapped_node_id_array); rbtree_delete(&app->tree, &object->node); if (object->userptr) rbtree_delete(&app->user_tree, &object->user_node); free(object); } static void vm_add_area_after(vm_area_t *after_this, vm_area_t *new_area) { vm_area_t *next = after_this->next; after_this->next = new_area; new_area->next = next; new_area->prev = after_this; if (next) next->prev = new_area; } static void vm_split_area(manageable_aperture_t *app, vm_area_t *area, void *address, uint64_t MemorySizeInBytes) { /* * The existing area is split to: [area->start, address - 1] * and [address + MemorySizeInBytes, area->end] */ vm_area_t *new_area = vm_create_and_init_area( VOID_PTR_ADD(address, MemorySizeInBytes), area->end); /* Shrink the existing area */ area->end = VOID_PTR_SUB(address, 1); vm_add_area_after(area, new_area); } static vm_object_t *vm_find_object_by_address_userptr(manageable_aperture_t *app, const void *address, uint64_t size, int is_userptr) { vm_object_t *cur = NULL; rbtree_t *tree = vm_object_tree(app, is_userptr); rbtree_key_t key = rbtree_key((unsigned long)address, size); void *start; uint64_t s; /* rbtree_lookup_nearest(,,,RIGHT) will return a node with * its size >= key.size and its address >= key.address * if there are two nodes with format(address, size), * (0x100, 16) and (0x110, 8). the key is (0x100, 0), * then node (0x100, 16) will be returned. */ rbtree_node_t *n = rbtree_lookup_nearest(tree, &key, LKP_ALL, RIGHT); if (n) { cur = vm_object_entry(n, is_userptr); if (is_userptr == 0) { start = cur->start; s = cur->size; } else { start = cur->userptr; s = cur->userptr_size; } if (start != address) return NULL; if (size) return size == s ? cur : NULL; /* size is 0, make sure there is only one node whose address == key.address*/ key = rbtree_key((unsigned long)address, (unsigned long)-1); rbtree_node_t *rn = rbtree_lookup_nearest(tree, &key, LKP_ALL, LEFT); if (rn != n) return NULL; } return cur; /* NULL if not found */ } static vm_object_t *vm_find_object_by_address_userptr_range(manageable_aperture_t *app, const void *address, int is_userptr) { vm_object_t *cur = NULL; rbtree_t *tree = vm_object_tree(app, is_userptr); rbtree_key_t key = rbtree_key((unsigned long)address, 0); rbtree_node_t *rn = rbtree_lookup_nearest(tree, &key, LKP_ALL, RIGHT); rbtree_node_t *ln; void *start; uint64_t size; /* all nodes might sit on left side of *address*, in this case rn is NULL. * So pick up the rightest one as rn. */ if (!rn) rn = rbtree_min_max(tree, RIGHT); if (is_userptr) { /* userptr might overlap. Need walk through the tree from right to left as only left nodes * can obtain the *address* */ ln = rbtree_min_max(tree, LEFT); } else { /* if key->size is -1, it match the node with start <= address. * if key->size is 0, it match the node with start < address. */ key = rbtree_key((unsigned long)address, -1); ln = rbtree_lookup_nearest(tree, &key, LKP_ALL, LEFT); } if (!ln) return NULL; while (rn) { cur = vm_object_entry(rn, is_userptr); if (is_userptr == 0) { start = cur->start; size = cur->size; } else { start = cur->userptr; size = cur->userptr_size; } if (address >= start && (uint64_t)address < ((uint64_t)start + size)) break; cur = NULL; if (ln == rn) break; rn = rbtree_prev(tree, rn); } return cur; /* NULL if not found */ } static vm_object_t *vm_find_object_by_address(manageable_aperture_t *app, const void *address, uint64_t size) { return vm_find_object_by_address_userptr(app, address, size, 0); } static vm_object_t *vm_find_object_by_address_range(manageable_aperture_t *app, const void *address) { return vm_find_object_by_address_userptr_range(app, address, 0); } static vm_object_t *vm_find_object_by_userptr(manageable_aperture_t *app, const void *address, HSAuint64 size) { return vm_find_object_by_address_userptr(app, address, size, 1); } static vm_object_t *vm_find_object_by_userptr_range(manageable_aperture_t *app, const void *address) { return vm_find_object_by_address_userptr_range(app, address, 1); } static vm_area_t *vm_find(manageable_aperture_t *app, void *address) { vm_area_t *cur = app->vm_ranges; /* Look up the appropriate address range containing the given address */ while (cur) { if (cur->start <= address && cur->end >= address) break; cur = cur->next; }; return cur; /* NULL if not found */ } static bool aperture_is_valid(void *app_base, void *app_limit) { if (app_base && app_limit && app_base < app_limit) return true; return false; } /* Align size of a VM area * * Leave at least one guard page after every object to catch * out-of-bounds accesses with VM faults. */ static uint64_t vm_align_area_size(manageable_aperture_t *app, uint64_t size) { return size + (uint64_t)app->guard_pages * PAGE_SIZE; } /* * Assumes that fmm_mutex is locked on entry. */ static void reserved_aperture_release(manageable_aperture_t *app, void *address, uint64_t MemorySizeInBytes) { vm_area_t *area; uint64_t SizeOfRegion; MemorySizeInBytes = vm_align_area_size(app, MemorySizeInBytes); area = vm_find(app, address); if (!area) return; SizeOfRegion = VOID_PTRS_SUB(area->end, area->start) + 1; /* check if block is whole region or part of it */ if (SizeOfRegion == MemorySizeInBytes) { vm_remove_area(app, area); } else if (SizeOfRegion > MemorySizeInBytes) { /* shrink from the start */ if (area->start == address) area->start = VOID_PTR_ADD(area->start, MemorySizeInBytes); /* shrink from the end */ else if (VOID_PTRS_SUB(area->end, address) + 1 == MemorySizeInBytes) area->end = VOID_PTR_SUB(area->end, MemorySizeInBytes); /* split the area */ else vm_split_area(app, area, address, MemorySizeInBytes); } if (app->is_cpu_accessible) { void *mmap_ret; /* Reset NUMA policy */ mbind(address, MemorySizeInBytes, MPOL_DEFAULT, NULL, 0, 0); /* Remove any CPU mapping, but keep the address range reserved */ mmap_ret = mmap(address, MemorySizeInBytes, PROT_NONE, MAP_ANONYMOUS | MAP_NORESERVE | MAP_PRIVATE | MAP_FIXED, -1, 0); if (mmap_ret == MAP_FAILED && errno == ENOMEM) { /* When mmap count reaches max_map_count, any mmap will * fail. Reduce the count with munmap then map it as * NORESERVE immediately. */ munmap(address, MemorySizeInBytes); mmap(address, MemorySizeInBytes, PROT_NONE, MAP_ANONYMOUS | MAP_NORESERVE | MAP_PRIVATE | MAP_FIXED, -1, 0); } } } /* * returns allocated address or NULL. Assumes, that fmm_mutex is locked * on entry. */ static void *reserved_aperture_allocate_aligned(manageable_aperture_t *app, void *address, uint64_t MemorySizeInBytes, uint64_t align) { uint64_t offset = 0, orig_align = align; vm_area_t *cur, *next; void *start; if (align < app->align) align = app->align; /* Align big buffers to the next power-of-2 up to huge page * size for flexible fragment size TLB optimizations */ while (align < GPU_HUGE_PAGE_SIZE && MemorySizeInBytes >= (align << 1)) align <<= 1; /* If no specific alignment was requested, align the end of * buffers instead of the start. For fragment optimizations, * aligning the start or the end achieves the same effective * optimization. End alignment to the TLB cache line size is * needed as a workaround for TLB issues on some older GPUs. */ if (orig_align <= (uint64_t)PAGE_SIZE) offset = align - (MemorySizeInBytes & (align - 1)); MemorySizeInBytes = vm_align_area_size(app, MemorySizeInBytes); /* Find a big enough "hole" in the address space */ cur = NULL; next = app->vm_ranges; start = address ? address : (void *)(ALIGN_UP((uint64_t)app->base, align) + offset); while (next) { if (next->start > start && VOID_PTRS_SUB(next->start, start) >= MemorySizeInBytes) break; cur = next; next = next->next; if (!address) start = (void *)(ALIGN_UP((uint64_t)cur->end + 1, align) + offset); } if (!next && VOID_PTRS_SUB(app->limit, start) + 1 < MemorySizeInBytes) /* No hole found and not enough space after the last area */ return NULL; if (cur && address && address < (void *)ALIGN_UP((uint64_t)cur->end + 1, align)) /* Required address is not free or overlaps */ return NULL; if (cur && VOID_PTR_ADD(cur->end, 1) == start) { /* extend existing area */ cur->end = VOID_PTR_ADD(start, MemorySizeInBytes-1); } else { vm_area_t *new_area; /* create a new area between cur and next */ new_area = vm_create_and_init_area(start, VOID_PTR_ADD(start, (MemorySizeInBytes - 1))); if (!new_area) return NULL; new_area->next = next; new_area->prev = cur; if (cur) cur->next = new_area; else app->vm_ranges = new_area; if (next) next->prev = new_area; } return start; } void *mmap_allocate_aligned(int prot, int flags, uint64_t size, uint64_t align, uint64_t guard_size, void *aper_base, void *aper_limit) { void *addr, *aligned_addr, *aligned_end, *mapping_end; uint64_t aligned_padded_size; aligned_padded_size = size + guard_size * 2 + (align - PAGE_SIZE); /* Map memory PROT_NONE to alloc address space only */ addr = mmap(0, aligned_padded_size, PROT_NONE, flags, -1, 0); if (addr == MAP_FAILED) { pr_err("mmap failed: %s\n", strerror(errno)); return NULL; } /* Adjust for alignment and guard pages */ aligned_addr = (void *)ALIGN_UP((uint64_t)addr + guard_size, align); if (aligned_addr < aper_base || VOID_PTR_ADD(aligned_addr, size - 1) > aper_limit) { pr_err("mmap returned %p, out of range %p-%p\n", aligned_addr, aper_base, aper_limit); munmap(addr, aligned_padded_size); return NULL; } /* Unmap padding and guard pages */ if (aligned_addr > addr) munmap(addr, VOID_PTRS_SUB(aligned_addr, addr)); aligned_end = VOID_PTR_ADD(aligned_addr, size); mapping_end = VOID_PTR_ADD(addr, aligned_padded_size); if (mapping_end > aligned_end) munmap(aligned_end, VOID_PTRS_SUB(mapping_end, aligned_end)); if (prot == PROT_NONE) return aligned_addr; /* MAP_FIXED to the aligned address with required prot */ addr = mmap(aligned_addr, size, prot, flags | MAP_FIXED, -1, 0); if (addr == MAP_FAILED) { pr_err("mmap failed: %s\n", strerror(errno)); return NULL; } return addr; } static void *mmap_aperture_allocate_aligned(manageable_aperture_t *aper, void *address, uint64_t size, uint64_t align) { uint64_t alignment_size = PAGE_SIZE << svm.alignment_order; uint64_t guard_size; if (!aper->is_cpu_accessible) { pr_err("MMap Aperture must be CPU accessible\n"); return NULL; } if (address) { void *addr; #ifdef MAP_FIXED_NOREPLACE addr = mmap(address, size, PROT_NONE, MAP_ANONYMOUS | MAP_NORESERVE | MAP_PRIVATE | MAP_FIXED_NOREPLACE, -1, 0); #else addr = mmap(address, size, PROT_NONE, MAP_ANONYMOUS | MAP_NORESERVE | MAP_PRIVATE, -1, 0); #endif if (addr == MAP_FAILED) { pr_err("mmap failed: %s\n", strerror(errno)); return NULL; } #ifndef MAP_FIXED_NOREPLACE if (address != addr) { pr_err("mmap failed to return addr asked\n"); munmap(addr, size); return NULL; } #endif return addr; } /* Align big buffers to the next power-of-2. By default, the max alignment * size is set to 2MB. This can be modified by the env variable * HSA_MAX_VA_ALIGN. This variable sets the order of the alignment size as * PAGE_SIZE * 2^HSA_MAX_VA_ALIGN. Setting HSA_MAX_VA_ALIGN = 18 (1GB), * improves the time for memory allocation and mapping. But it might lose * performance when GFX access it, specially for big allocations (>3GB). */ while (align < alignment_size && size >= (align << 1)) align <<= 1; /* Add padding to guarantee proper alignment and leave guard * pages on both sides */ guard_size = (uint64_t)aper->guard_pages * PAGE_SIZE; return mmap_allocate_aligned(PROT_NONE, MAP_ANONYMOUS | MAP_NORESERVE | MAP_PRIVATE, size, align, guard_size, aper->base, aper->limit); } static void mmap_aperture_release(manageable_aperture_t *aper, void *addr, uint64_t size) { if (!aper->is_cpu_accessible) { pr_err("MMap Aperture must be CPU accessible\n"); return; } /* Reset NUMA policy */ mbind(addr, size, MPOL_DEFAULT, NULL, 0, 0); /* Unmap memory */ munmap(addr, size); } /* Wrapper functions to call aperture-specific VA management functions */ static void *aperture_allocate_area_aligned(manageable_aperture_t *app, void *address, uint64_t MemorySizeInBytes, uint64_t align) { return app->ops->allocate_area_aligned(app, address, MemorySizeInBytes, align); } static void *aperture_allocate_area(manageable_aperture_t *app, void *address, uint64_t MemorySizeInBytes) { return app->ops->allocate_area_aligned(app, address, MemorySizeInBytes, app->align); } static void aperture_release_area(manageable_aperture_t *app, void *address, uint64_t MemorySizeInBytes) { app->ops->release_area(app, address, MemorySizeInBytes); } /* returns 0 on success. Assumes, that fmm_mutex is locked on entry */ static vm_object_t *aperture_allocate_object(manageable_aperture_t *app, void *new_address, uint64_t handle, uint64_t MemorySizeInBytes, HsaMemFlags mflags) { vm_object_t *new_object; /* Allocate new object */ new_object = vm_create_and_init_object(new_address, MemorySizeInBytes, handle, mflags); if (!new_object) return NULL; rbtree_insert(&app->tree, &new_object->node); return new_object; } static int32_t gpu_mem_find_by_gpu_id(uint32_t gpu_id) { uint32_t i; for (i = 0 ; i < gpu_mem_count ; i++) if (gpu_mem[i].gpu_id == gpu_id) return i; return -1; } static int32_t gpu_mem_find_by_node_id(uint32_t node_id) { uint32_t i; for (i = 0 ; i < gpu_mem_count ; i++) if (gpu_mem[i].node_id == node_id) return i; return -1; } static manageable_aperture_t *fmm_get_aperture(HsaApertureInfo info) { switch (info.type) { case HSA_APERTURE_DGPU: return svm.dgpu_aperture; case HSA_APERTURE_DGPU_ALT: return svm.dgpu_alt_aperture; case HSA_APERTURE_GPUVM: return &gpu_mem[info.idx].gpuvm_aperture; case HSA_APERTURE_CPUVM: return &cpuvm_aperture; case HSA_APERTURE_MEMHANDLE: return &mem_handle_aperture; default: return NULL; } } static manageable_aperture_t *fmm_is_scratch_aperture(const void *address) { uint32_t i; for (i = 0; i < gpu_mem_count; i++) { if (gpu_mem[i].gpu_id == NON_VALID_GPU_ID) continue; if ((address >= gpu_mem[i].scratch_physical.base) && (address <= gpu_mem[i].scratch_physical.limit)) return &gpu_mem[i].scratch_physical; } return NULL; } static manageable_aperture_t *fmm_find_aperture(const void *address, HsaApertureInfo *info) { manageable_aperture_t *aperture = NULL; uint32_t i; HsaApertureInfo _info = { .type = HSA_APERTURE_UNSUPPORTED, .idx = 0}; if ((address >= mem_handle_aperture.base) && (address <= mem_handle_aperture.limit)){ aperture = &mem_handle_aperture; _info.type = HSA_APERTURE_MEMHANDLE; } else if (is_dgpu) { if (address >= svm.dgpu_aperture->base && address <= svm.dgpu_aperture->limit) { aperture = fmm_is_scratch_aperture(address); if (!aperture) { aperture = svm.dgpu_aperture; _info.type = HSA_APERTURE_DGPU; } } else if (address >= svm.dgpu_alt_aperture->base && address <= svm.dgpu_alt_aperture->limit) { aperture = svm.dgpu_alt_aperture; _info.type = HSA_APERTURE_DGPU_ALT; } else { /* Not in SVM, it can be system memory registered by userptr */ aperture = svm.dgpu_aperture; _info.type = HSA_APERTURE_DGPU; } } else { /* APU */ if (address >= svm.dgpu_aperture->base && address <= svm.dgpu_aperture->limit) { aperture = svm.dgpu_aperture; _info.type = HSA_APERTURE_DGPU; } else { /* gpuvm_aperture */ for (i = 0; i < gpu_mem_count; i++) { if ((address >= gpu_mem[i].gpuvm_aperture.base) && (address <= gpu_mem[i].gpuvm_aperture.limit)) { aperture = &gpu_mem[i].gpuvm_aperture; _info.type = HSA_APERTURE_GPUVM; _info.idx = i; } } } if (!aperture) { /* Not in GPUVM */ aperture = &cpuvm_aperture; _info.type = HSA_APERTURE_CPUVM; } } if (info) *info = _info; return aperture; } static HsaMemFlags fmm_translate_ioc_to_hsa_flags(uint32_t ioc_flags) { HsaMemFlags mflags = {0}; if (!(ioc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)) mflags.ui32.ReadOnly = 1; if (!(ioc_flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)) mflags.ui32.CoarseGrain = 1; if (ioc_flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) mflags.ui32.HostAccess = 1; return mflags; } static HSAKMT_STATUS fmm_register_mem_svm_api(void *address, uint64_t size, bool coarse_grain) { struct kfd_ioctl_svm_args *args; size_t s_attr; HSAuint32 page_offset = (HSAuint64)address & (PAGE_SIZE-1); HSAuint64 aligned_addr = (HSAuint64)address - page_offset; HSAuint64 aligned_size = PAGE_ALIGN_UP(page_offset + size); if (!g_first_gpu_mem) return HSAKMT_STATUS_ERROR; s_attr = sizeof(struct kfd_ioctl_svm_attribute); args = alloca(sizeof(*args) + s_attr); args->start_addr = aligned_addr; args->size = aligned_size; args->op = KFD_IOCTL_SVM_OP_SET_ATTR; args->nattr = 1; args->attrs[0].type = coarse_grain ? HSA_SVM_ATTR_CLR_FLAGS : HSA_SVM_ATTR_SET_FLAGS; args->attrs[0].value = HSA_SVM_FLAG_COHERENT; pr_debug("Registering to SVM %p size: %ld\n", (void*)aligned_addr, aligned_size); /* Driver does one copy_from_user, with extra attrs size */ if (kmtIoctl(kfd_fd, AMDKFD_IOC_SVM + (s_attr << _IOC_SIZESHIFT), args)) { pr_debug("op set range attrs failed %s\n", strerror(errno)); return HSAKMT_STATUS_ERROR; } return HSAKMT_STATUS_SUCCESS; } static HSAKMT_STATUS fmm_map_mem_svm_api(void *address, uint64_t size, uint32_t *nodes_to_map, uint32_t nodes_array_size) { struct kfd_ioctl_svm_args *args; size_t s_attr; uint32_t i, nattr; if (!g_first_gpu_mem) return HSAKMT_STATUS_ERROR; nattr = nodes_array_size; s_attr = sizeof(struct kfd_ioctl_svm_attribute) * nattr; args = alloca(sizeof(*args) + s_attr); args->start_addr = (uint64_t)address; args->size = size; args->op = KFD_IOCTL_SVM_OP_SET_ATTR; args->nattr = nattr; for (i = 0; i < nodes_array_size; i++) { args->attrs[i].type = HSA_SVM_ATTR_ACCESS_IN_PLACE; args->attrs[i].value = nodes_to_map[i]; } /* Driver does one copy_from_user, with extra attrs size */ if (kmtIoctl(kfd_fd, AMDKFD_IOC_SVM + (s_attr << _IOC_SIZESHIFT), args)) { pr_debug("op set range attrs failed %s\n", strerror(errno)); return HSAKMT_STATUS_ERROR; } return HSAKMT_STATUS_SUCCESS; } /* After allocating the memory, return the vm_object created for this memory. * Return NULL if any failure. */ static vm_object_t *fmm_allocate_memory_object(uint32_t gpu_id, void *mem, uint64_t MemorySizeInBytes, manageable_aperture_t *aperture, uint64_t *mmap_offset, uint32_t ioc_flags) { struct kfd_ioctl_alloc_memory_of_gpu_args args = {0}; struct kfd_ioctl_free_memory_of_gpu_args free_args = {0}; vm_object_t *vm_obj = NULL; HsaMemFlags mflags; if (!mem) return NULL; /* Allocate memory from amdkfd */ args.gpu_id = gpu_id; args.size = MemorySizeInBytes; args.flags = ioc_flags | KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE; args.va_addr = (uint64_t)mem; if (!is_dgpu && (ioc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM)) args.va_addr = VOID_PTRS_SUB(mem, aperture->base); if (ioc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) args.mmap_offset = *mmap_offset; /* if allocate vram-only, use an invalid VA */ if (aperture == &mem_handle_aperture) args.va_addr = 0; if (kmtIoctl(kfd_fd, AMDKFD_IOC_ALLOC_MEMORY_OF_GPU, &args)) return NULL; mflags = fmm_translate_ioc_to_hsa_flags(ioc_flags); /* Allocate object */ pthread_mutex_lock(&aperture->fmm_mutex); vm_obj = aperture_allocate_object(aperture, mem, args.handle, MemorySizeInBytes, mflags); if (!vm_obj) goto err_object_allocation_failed; pthread_mutex_unlock(&aperture->fmm_mutex); if (mmap_offset) *mmap_offset = args.mmap_offset; return vm_obj; err_object_allocation_failed: pthread_mutex_unlock(&aperture->fmm_mutex); free_args.handle = args.handle; kmtIoctl(kfd_fd, AMDKFD_IOC_FREE_MEMORY_OF_GPU, &free_args); return NULL; } #ifdef DEBUG_PRINT_APERTURE static void aperture_print(aperture_t *app) { pr_info("\t Base: %p\n", app->base); pr_info("\t Limit: %p\n", app->limit); } static void manageable_aperture_print(manageable_aperture_t *app) { vm_area_t *cur = app->vm_ranges; rbtree_node_t *n = rbtree_node_any(&app->tree, LEFT); vm_object_t *object; pr_info("\t Base: %p\n", app->base); pr_info("\t Limit: %p\n", app->limit); pr_info("\t Ranges:\n"); while (cur) { pr_info("\t\t Range [%p - %p]\n", cur->start, cur->end); cur = cur->next; }; pr_info("\t Objects:\n"); while (n) { object = vm_object_entry(n, 0); pr_info("\t\t Object [%p - %" PRIu64 "]\n", object->start, object->size); n = rbtree_next(&app->tree, n); } } void fmm_print(uint32_t gpu_id) { int32_t gpu_mem_id = gpu_mem_find_by_gpu_id(gpu_id); if (gpu_mem_id >= 0) { /* Found */ pr_info("LDS aperture:\n"); aperture_print(&gpu_mem[gpu_mem_id].lds_aperture); pr_info("GPUVM aperture:\n"); manageable_aperture_print(&gpu_mem[gpu_mem_id].gpuvm_aperture); pr_info("Scratch aperture:\n"); aperture_print(&gpu_mem[gpu_mem_id].scratch_aperture); pr_info("Scratch backing memory:\n"); manageable_aperture_print(&gpu_mem[gpu_mem_id].scratch_physical); } pr_info("dGPU aperture:\n"); manageable_aperture_print(svm.dgpu_aperture); pr_info("dGPU alt aperture:\n"); if (svm.dgpu_aperture == svm.dgpu_alt_aperture) pr_info("\t Alias of dGPU aperture\n"); else manageable_aperture_print(svm.dgpu_alt_aperture); } #else void fmm_print(uint32_t gpu_id) { } #endif /* vm_find_object - Find a VM object in any aperture * * @addr: VM address of the object * @size: size of the object, 0 means "don't care", * UINT64_MAX means addr can match any address within the object * @out_aper: Aperture where the object was found * * Returns a pointer to the object if found, NULL otherwise. If an * object is found, this function returns with the * (*out_aper)->fmm_mutex locked. */ static vm_object_t *vm_find_object(const void *addr, uint64_t size, manageable_aperture_t **out_aper) { manageable_aperture_t *aper = NULL; bool range = (size == UINT64_MAX); bool userptr = false; vm_object_t *obj = NULL; uint32_t i; for (i = 0; i < gpu_mem_count; i++) if (gpu_mem[i].gpu_id != NON_VALID_GPU_ID && addr >= gpu_mem[i].gpuvm_aperture.base && addr <= gpu_mem[i].gpuvm_aperture.limit) { aper = &gpu_mem[i].gpuvm_aperture; break; } if (!aper) { if ((addr >= mem_handle_aperture.base) && (addr <= mem_handle_aperture.limit)){ aper = &mem_handle_aperture; } } if (!aper) { if (!svm.dgpu_aperture) goto no_svm; if ((addr >= svm.dgpu_aperture->base) && (addr <= svm.dgpu_aperture->limit)) aper = svm.dgpu_aperture; else if ((addr >= svm.dgpu_alt_aperture->base) && (addr <= svm.dgpu_alt_aperture->limit)) aper = svm.dgpu_alt_aperture; else { aper = svm.dgpu_aperture; userptr = true; } } pthread_mutex_lock(&aper->fmm_mutex); if (range) { /* mmap_apertures can have userptrs in them. Try to * look up addresses as userptrs first to sort out any * ambiguity of multiple overlapping mappings at * different GPU addresses. */ if (userptr || aper->ops == &mmap_aperture_ops) obj = vm_find_object_by_userptr_range(aper, addr); if (!obj && !userptr) obj = vm_find_object_by_address_range(aper, addr); } else { if (userptr || aper->ops == &mmap_aperture_ops) obj = vm_find_object_by_userptr(aper, addr, size); if (!obj && !userptr) { long page_offset = (long)addr & (PAGE_SIZE-1); const void *page_addr = (const uint8_t *)addr - page_offset; obj = vm_find_object_by_address(aper, page_addr, 0); /* If we find a userptr here, it's a match on * the aligned GPU address. Make sure that the * page offset and size match too. */ if (obj && obj->userptr && (((long)obj->userptr & (PAGE_SIZE - 1)) != page_offset || (size && size != obj->userptr_size))) obj = NULL; } } no_svm: if (!obj && !is_dgpu) { /* On APUs try finding it in the CPUVM aperture */ if (aper) pthread_mutex_unlock(&aper->fmm_mutex); aper = &cpuvm_aperture; pthread_mutex_lock(&aper->fmm_mutex); if (range) obj = vm_find_object_by_address_range(aper, addr); else obj = vm_find_object_by_address(aper, addr, 0); } if (obj) { *out_aper = aper; return obj; } if (aper) pthread_mutex_unlock(&aper->fmm_mutex); return NULL; } static HSAuint8 fmm_check_user_memory(const void *addr, HSAuint64 size) { volatile const HSAuint8 *ptr = addr; volatile const HSAuint8 *end = ptr + size; HSAuint8 sum = 0; /* Access every page in the buffer to make sure the mapping is * valid. If it's not, it will die with a segfault that's easy * to debug. */ for (; ptr < end; ptr = (void *)PAGE_ALIGN_UP(ptr + 1)) sum += *ptr; return sum; } static void fmm_release_scratch(uint32_t gpu_id) { int32_t gpu_mem_id; uint64_t size; vm_object_t *obj; manageable_aperture_t *aperture; rbtree_node_t *n; gpu_mem_id = gpu_mem_find_by_gpu_id(gpu_id); if (gpu_mem_id < 0) return; aperture = &gpu_mem[gpu_mem_id].scratch_physical; size = VOID_PTRS_SUB(aperture->limit, aperture->base) + 1; if (is_dgpu) { /* unmap and remove all remaining objects */ pthread_mutex_lock(&aperture->fmm_mutex); while ((n = rbtree_node_any(&aperture->tree, MID))) { obj = vm_object_entry(n, 0); void *obj_addr = obj->start; pthread_mutex_unlock(&aperture->fmm_mutex); _fmm_unmap_from_gpu_scratch(gpu_id, aperture, obj_addr); pthread_mutex_lock(&aperture->fmm_mutex); } pthread_mutex_unlock(&aperture->fmm_mutex); /* release address space */ pthread_mutex_lock(&svm.dgpu_aperture->fmm_mutex); aperture_release_area(svm.dgpu_aperture, gpu_mem[gpu_mem_id].scratch_physical.base, size); pthread_mutex_unlock(&svm.dgpu_aperture->fmm_mutex); } else /* release address space */ munmap(gpu_mem[gpu_mem_id].scratch_physical.base, size); /* invalidate scratch backing aperture */ gpu_mem[gpu_mem_id].scratch_physical.base = NULL; gpu_mem[gpu_mem_id].scratch_physical.limit = NULL; } static uint32_t fmm_translate_hsa_to_ioc_flags(HsaMemFlags flags) { uint32_t ioc_flags = 0; if (flags.ui32.AQLQueueMemory) ioc_flags |= (KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM | KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED); if (!flags.ui32.ReadOnly) ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE; /* TODO: Since, ROCr interfaces doesn't allow caller to set page * permissions, mark all user allocations with exec permission. * Check for flags.ui32.ExecuteAccess once ROCr is ready. */ ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE; return ioc_flags; } #define SCRATCH_ALIGN 0x10000 void *fmm_allocate_scratch(uint32_t gpu_id, void *address, uint64_t MemorySizeInBytes) { manageable_aperture_t *aperture_phy; struct kfd_ioctl_set_scratch_backing_va_args args = {0}; int32_t gpu_mem_id; void *mem = NULL; uint64_t aligned_size = ALIGN_UP(MemorySizeInBytes, SCRATCH_ALIGN); /* Retrieve gpu_mem id according to gpu_id */ gpu_mem_id = gpu_mem_find_by_gpu_id(gpu_id); if (gpu_mem_id < 0) return NULL; aperture_phy = &gpu_mem[gpu_mem_id].scratch_physical; if (aperture_phy->base || aperture_phy->limit) /* Scratch was already allocated for this GPU */ return NULL; /* Allocate address space for scratch backing, 64KB aligned */ if (is_dgpu) { pthread_mutex_lock(&svm.dgpu_aperture->fmm_mutex); mem = aperture_allocate_area_aligned( svm.dgpu_aperture, address, aligned_size, SCRATCH_ALIGN); pthread_mutex_unlock(&svm.dgpu_aperture->fmm_mutex); } else { if (address) return NULL; mem = mmap_allocate_aligned(PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, aligned_size, SCRATCH_ALIGN, 0, 0, (void *)LONG_MAX); } /* Remember scratch backing aperture for later */ aperture_phy->base = mem; aperture_phy->limit = VOID_PTR_ADD(mem, aligned_size-1); aperture_phy->is_cpu_accessible = true; /* Program SH_HIDDEN_PRIVATE_BASE */ args.gpu_id = gpu_id; args.va_addr = ((uint64_t)mem) >> 16; if (kmtIoctl(kfd_fd, AMDKFD_IOC_SET_SCRATCH_BACKING_VA, &args)) { fmm_release_scratch(gpu_id); return NULL; } return mem; } static void *__fmm_allocate_device(uint32_t gpu_id, void *address, uint64_t MemorySizeInBytes, manageable_aperture_t *aperture, uint64_t *mmap_offset, uint32_t ioc_flags, vm_object_t **vm_obj) { void *mem = NULL; vm_object_t *obj; /* Check that aperture is properly initialized/supported */ if (!aperture_is_valid(aperture->base, aperture->limit)) return NULL; /* Allocate address space */ pthread_mutex_lock(&aperture->fmm_mutex); mem = aperture_allocate_area(aperture, address, MemorySizeInBytes); pthread_mutex_unlock(&aperture->fmm_mutex); /* * Now that we have the area reserved, allocate memory in the device * itself */ obj = fmm_allocate_memory_object(gpu_id, mem, MemorySizeInBytes, aperture, mmap_offset, ioc_flags); if (!obj) { /* * allocation of memory in device failed. * Release region in aperture */ pthread_mutex_lock(&aperture->fmm_mutex); aperture_release_area(aperture, mem, MemorySizeInBytes); pthread_mutex_unlock(&aperture->fmm_mutex); /* Assign NULL to mem to indicate failure to calling function */ mem = NULL; } if (vm_obj) *vm_obj = obj; return mem; } static void *fmm_map_to_cpu(void *mem, uint64_t size, bool host_access, int fd, uint64_t mmap_offset) { int flag = MAP_SHARED | MAP_FIXED; int prot = host_access ? PROT_READ | PROT_WRITE : PROT_NONE; void *ret = mmap(mem, size, prot, flag, fd, mmap_offset); if (ret != MAP_FAILED) /* This madvise() call is needed to avoid additional references * to mapped BOs in child processes that can prevent freeing * memory in the parent process and lead to out-of-memory * conditions. */ madvise(mem, size, MADV_DONTFORK); return ret; } static void *fmm_allocate_va(uint32_t gpu_id, void *address, uint64_t size, manageable_aperture_t *aperture, HsaMemFlags mflags) { void *mem = NULL; vm_object_t *vm_obj = NULL; /* Check aperture is properly initialized/supported */ if (!aperture_is_valid(aperture->base, aperture->limit)) return NULL; /* Allocate address space */ pthread_mutex_lock(&aperture->fmm_mutex); mem = aperture_allocate_area(aperture, address, size); /* assing handle 0 to vm_obj since no mem allocted */ vm_obj = aperture_allocate_object(aperture, mem, 0, size, mflags); pthread_mutex_unlock(&aperture->fmm_mutex); if (!vm_obj) { pthread_mutex_lock(&aperture->fmm_mutex); aperture_release_area(aperture, mem, size); pthread_mutex_unlock(&aperture->fmm_mutex); mem = NULL; } return mem; } void *fmm_allocate_device(uint32_t gpu_id, uint32_t node_id, void *address, uint64_t MemorySizeInBytes, HsaMemFlags mflags) { manageable_aperture_t *aperture; int32_t gpu_mem_id; uint32_t ioc_flags = KFD_IOC_ALLOC_MEM_FLAGS_VRAM; uint64_t size, mmap_offset; void *mem; vm_object_t *vm_obj = NULL; /* Retrieve gpu_mem id according to gpu_id */ gpu_mem_id = gpu_mem_find_by_gpu_id(gpu_id); if (gpu_mem_id < 0) return NULL; size = MemorySizeInBytes; if (mflags.ui32.HostAccess) ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; ioc_flags |= fmm_translate_hsa_to_ioc_flags(mflags); if (topology_is_svm_needed(gpu_mem[gpu_mem_id].EngineId)) { aperture = svm.dgpu_aperture; if (mflags.ui32.AQLQueueMemory) size = MemorySizeInBytes * 2; } else { aperture = &gpu_mem[gpu_mem_id].gpuvm_aperture; } /* special case for va allocation without vram alloc */ if (mflags.ui32.OnlyAddress) return fmm_allocate_va(gpu_id, address, size, aperture, mflags); /* special case for vram allocation without addr */ if(mflags.ui32.NoAddress) aperture = &mem_handle_aperture; if (!mflags.ui32.CoarseGrain || svm.disable_cache) ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_COHERENT; if (mflags.ui32.Uncached || svm.disable_cache) ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED; mem = __fmm_allocate_device(gpu_id, address, size, aperture, &mmap_offset, ioc_flags, &vm_obj); if (mem && vm_obj) { pthread_mutex_lock(&aperture->fmm_mutex); /* Store memory allocation flags, not ioc flags */ vm_obj->mflags = mflags; gpuid_to_nodeid(gpu_id, &vm_obj->node_id); pthread_mutex_unlock(&aperture->fmm_mutex); } /* if alloc vram-only not mmap to cpu vm since no va */ if (mem && !mflags.ui32.NoAddress) { void *ret = fmm_map_to_cpu(mem, MemorySizeInBytes, mflags.ui32.HostAccess, gpu_mem[gpu_mem_id].drm_render_fd, mmap_offset); if (ret == MAP_FAILED) { __fmm_release(vm_obj, aperture); return NULL; } #ifdef SANITIZER_AMDGPU if (vm_obj) { vm_obj->mmap_flags = mflags.ui32.HostAccess ? PROT_READ | PROT_WRITE : PROT_NONE; vm_obj->mmap_fd = gpu_mem[gpu_mem_id].drm_render_fd; vm_obj->mmap_offset = mmap_offset; } #endif } return mem; } void *fmm_allocate_doorbell(uint32_t gpu_id, uint64_t MemorySizeInBytes, uint64_t doorbell_mmap_offset) { manageable_aperture_t *aperture; int32_t gpu_mem_id; uint32_t ioc_flags; void *mem; vm_object_t *vm_obj = NULL; /* Retrieve gpu_mem id according to gpu_id */ gpu_mem_id = gpu_mem_find_by_gpu_id(gpu_id); if (gpu_mem_id < 0) return NULL; /* Use fine-grained aperture */ aperture = svm.dgpu_alt_aperture; ioc_flags = KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | KFD_IOC_ALLOC_MEM_FLAGS_COHERENT; mem = __fmm_allocate_device(gpu_id, NULL, MemorySizeInBytes, aperture, NULL, ioc_flags, &vm_obj); if (mem && vm_obj) { HsaMemFlags mflags; /* Cook up some flags for storing in the VM object */ mflags.Value = 0; mflags.ui32.NonPaged = 1; mflags.ui32.HostAccess = 1; mflags.ui32.Reserved = 0xBe1; pthread_mutex_lock(&aperture->fmm_mutex); vm_obj->mflags = mflags; gpuid_to_nodeid(gpu_id, &vm_obj->node_id); pthread_mutex_unlock(&aperture->fmm_mutex); } if (mem) { void *ret = mmap(mem, MemorySizeInBytes, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, kfd_fd, doorbell_mmap_offset); if (ret == MAP_FAILED) { __fmm_release(vm_obj, aperture); return NULL; } } return mem; } static void *fmm_allocate_host_cpu(void *address, uint64_t MemorySizeInBytes, HsaMemFlags mflags) { void *mem = NULL; vm_object_t *vm_obj; int mmap_prot = PROT_READ; if (address) return NULL; if (mflags.ui32.ExecuteAccess) mmap_prot |= PROT_EXEC; if (!mflags.ui32.ReadOnly) mmap_prot |= PROT_WRITE; /* mmap will return a pointer with alignment equal to * sysconf(_SC_PAGESIZE). */ mem = mmap(NULL, MemorySizeInBytes, mmap_prot, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); if (mem == MAP_FAILED) return NULL; pthread_mutex_lock(&cpuvm_aperture.fmm_mutex); vm_obj = aperture_allocate_object(&cpuvm_aperture, mem, 0, MemorySizeInBytes, mflags); if (vm_obj) vm_obj->node_id = 0; /* APU systems only have one CPU node */ pthread_mutex_unlock(&cpuvm_aperture.fmm_mutex); return mem; } static int bind_mem_to_numa(uint32_t node_id, void *mem, uint64_t SizeInBytes, HsaMemFlags mflags) { int mode = MPOL_F_STATIC_NODES; struct bitmask *node_mask; int num_node; long r; pr_debug("%s mem %p flags 0x%x size 0x%lx node_id %d\n", __func__, mem, mflags.Value, SizeInBytes, node_id); if (mflags.ui32.NoNUMABind) return 0; if (numa_available() == -1) return 0; num_node = numa_max_node() + 1; /* Ignore binding requests to invalid nodes IDs */ if (node_id >= (unsigned)num_node) { pr_warn("node_id %d >= num_node %d\n", node_id, num_node); return 0; } if (num_node <= 1) return 0; node_mask = numa_bitmask_alloc(num_node); if (!node_mask) return -ENOMEM; #ifdef __PPC64__ numa_bitmask_setbit(node_mask, node_id * 8); #else numa_bitmask_setbit(node_mask, node_id); #endif mode |= mflags.ui32.NoSubstitute ? MPOL_BIND : MPOL_PREFERRED; r = mbind(mem, SizeInBytes, mode, node_mask->maskp, num_node + 1, 0); numa_bitmask_free(node_mask); if (r) { /* If applcation is running inside docker, still return * ok because docker seccomp blocks mbind by default, * otherwise application cannot allocate system memory. */ if (errno == EPERM) { pr_err_once("mbind is blocked by seccomp\n"); return 0; } /* Ignore mbind failure if no memory available on node */ if (!mflags.ui32.NoSubstitute) return 0; pr_warn_once("Failed to set NUMA policy for %p: %s\n", mem, strerror(errno)); return -EFAULT; } return 0; } static void *fmm_allocate_host_gpu(uint32_t node_id, void *address, uint64_t MemorySizeInBytes, HsaMemFlags mflags) { void *mem; manageable_aperture_t *aperture; uint64_t mmap_offset; uint32_t ioc_flags; uint64_t size; int32_t gpu_drm_fd; uint32_t gpu_id; vm_object_t *vm_obj = NULL; if (!g_first_gpu_mem) return NULL; gpu_id = g_first_gpu_mem->gpu_id; gpu_drm_fd = g_first_gpu_mem->drm_render_fd; size = MemorySizeInBytes; ioc_flags = 0; if (mflags.ui32.CoarseGrain) aperture = svm.dgpu_aperture; else aperture = svm.dgpu_alt_aperture; /* always coherent */ if (!mflags.ui32.CoarseGrain || svm.disable_cache) ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_COHERENT; if (mflags.ui32.Uncached || svm.disable_cache) ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED; ioc_flags |= fmm_translate_hsa_to_ioc_flags(mflags); if (mflags.ui32.AQLQueueMemory) size = MemorySizeInBytes * 2; /* Paged memory is allocated as a userptr mapping, non-paged * memory is allocated from KFD */ if (!mflags.ui32.NonPaged && svm.userptr_for_paged_mem) { /* Allocate address space */ pthread_mutex_lock(&aperture->fmm_mutex); mem = aperture_allocate_area(aperture, address, size); pthread_mutex_unlock(&aperture->fmm_mutex); if (!mem) return NULL; /* Map anonymous pages */ if (mmap(mem, MemorySizeInBytes, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0) == MAP_FAILED) goto out_release_area; /* Bind to NUMA node */ if (bind_mem_to_numa(node_id, mem, MemorySizeInBytes, mflags)) goto out_release_area; /* Mappings in the DGPU aperture don't need to be copied on * fork. This avoids MMU notifiers and evictions due to user * memory mappings on fork. */ madvise(mem, MemorySizeInBytes, MADV_DONTFORK); /* Create userptr BO */ mmap_offset = (uint64_t)mem; ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; vm_obj = fmm_allocate_memory_object(gpu_id, mem, size, aperture, &mmap_offset, ioc_flags); if (!vm_obj) goto out_release_area; } else { ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_GTT; mem = __fmm_allocate_device(gpu_id, address, size, aperture, &mmap_offset, ioc_flags, &vm_obj); if (mem && mflags.ui32.HostAccess) { void *ret = fmm_map_to_cpu(mem, MemorySizeInBytes, mflags.ui32.HostAccess, gpu_drm_fd, mmap_offset); if (ret == MAP_FAILED) { __fmm_release(vm_obj, aperture); return NULL; } } #ifdef SANITIZER_AMDGPU if (mem && vm_obj) { vm_obj->mmap_flags = mflags.ui32.HostAccess ? PROT_READ | PROT_WRITE : PROT_NONE; vm_obj->mmap_fd = gpu_drm_fd; vm_obj->mmap_offset = mmap_offset; } #endif } if (mem && vm_obj) { /* Store memory allocation flags, not ioc flags */ pthread_mutex_lock(&aperture->fmm_mutex); vm_obj->mflags = mflags; vm_obj->node_id = node_id; pthread_mutex_unlock(&aperture->fmm_mutex); } return mem; out_release_area: /* Release address space */ pthread_mutex_lock(&aperture->fmm_mutex); aperture_release_area(aperture, mem, size); pthread_mutex_unlock(&aperture->fmm_mutex); return NULL; } void *fmm_allocate_host(uint32_t node_id, void *address, uint64_t MemorySizeInBytes, HsaMemFlags mflags) { if (is_dgpu) return fmm_allocate_host_gpu(node_id, address, MemorySizeInBytes, mflags); return fmm_allocate_host_cpu(address, MemorySizeInBytes, mflags); } static int __fmm_release(vm_object_t *object, manageable_aperture_t *aperture) { struct kfd_ioctl_free_memory_of_gpu_args args = {0}; if (!object) return -EINVAL; pthread_mutex_lock(&aperture->fmm_mutex); if (object->userptr) { object->registration_count--; if (object->registration_count > 0) { pthread_mutex_unlock(&aperture->fmm_mutex); return 0; } } /* If memory is user memory and it's still GPU mapped, munmap * would cause an eviction. If the restore happens quickly * enough, restore would also fail with an error message. So * free the BO before unmapping the pages. */ args.handle = object->handle; if (args.handle && kmtIoctl(kfd_fd, AMDKFD_IOC_FREE_MEMORY_OF_GPU, &args)) { pthread_mutex_unlock(&aperture->fmm_mutex); return -errno; } aperture_release_area(aperture, object->start, object->size); vm_remove_object(aperture, object); pthread_mutex_unlock(&aperture->fmm_mutex); return 0; } HSAKMT_STATUS fmm_release(void *address) { manageable_aperture_t *aperture = NULL; vm_object_t *object = NULL; uint32_t i; /* Special handling for scratch memory */ for (i = 0; i < gpu_mem_count; i++) if (gpu_mem[i].gpu_id != NON_VALID_GPU_ID && address >= gpu_mem[i].scratch_physical.base && address <= gpu_mem[i].scratch_physical.limit) { fmm_release_scratch(gpu_mem[i].gpu_id); return HSAKMT_STATUS_SUCCESS; } object = vm_find_object(address, 0, &aperture); if (!object) return svm.is_svm_api_supported ? HSAKMT_STATUS_SUCCESS : HSAKMT_STATUS_MEMORY_NOT_REGISTERED; if (aperture == &cpuvm_aperture) { /* APU system memory */ uint64_t size = 0; size = object->size; vm_remove_object(&cpuvm_aperture, object); pthread_mutex_unlock(&aperture->fmm_mutex); munmap(address, size); } else { pthread_mutex_unlock(&aperture->fmm_mutex); if (__fmm_release(object, aperture)) return HSAKMT_STATUS_ERROR; if (!aperture->is_cpu_accessible) fmm_print(gpu_mem[i].gpu_id); } return HSAKMT_STATUS_SUCCESS; } static int fmm_set_memory_policy(uint32_t gpu_id, int default_policy, int alt_policy, uintptr_t alt_base, uint64_t alt_size) { struct kfd_ioctl_set_memory_policy_args args = {0}; args.gpu_id = gpu_id; args.default_policy = default_policy; args.alternate_policy = alt_policy; args.alternate_aperture_base = alt_base; args.alternate_aperture_size = alt_size; return kmtIoctl(kfd_fd, AMDKFD_IOC_SET_MEMORY_POLICY, &args); } static uint32_t get_vm_alignment(uint32_t device_id) { int page_size = 0; if (device_id >= 0x6920 && device_id <= 0x6939) /* Tonga */ page_size = TONGA_PAGE_SIZE; else if (device_id >= 0x9870 && device_id <= 0x9877) /* Carrizo */ page_size = TONGA_PAGE_SIZE; return MAX(PAGE_SIZE, page_size); } static HSAKMT_STATUS get_process_apertures( struct kfd_process_device_apertures *process_apertures, uint32_t *num_of_nodes) { struct kfd_ioctl_get_process_apertures_new_args args_new = {0}; struct kfd_ioctl_get_process_apertures_args args_old; args_new.kfd_process_device_apertures_ptr = (uintptr_t)process_apertures; args_new.num_of_nodes = *num_of_nodes; if (!kmtIoctl(kfd_fd, AMDKFD_IOC_GET_PROCESS_APERTURES_NEW, (void *)&args_new)) { *num_of_nodes = args_new.num_of_nodes; return HSAKMT_STATUS_SUCCESS; } /* New IOCTL failed, try the old one in case we're running on * a really old kernel */ memset(&args_old, 0, sizeof(args_old)); if (kmtIoctl(kfd_fd, AMDKFD_IOC_GET_PROCESS_APERTURES, (void *)&args_old)) return HSAKMT_STATUS_ERROR; if (args_old.num_of_nodes < *num_of_nodes) *num_of_nodes = args_old.num_of_nodes; memcpy(process_apertures, args_old.process_apertures, sizeof(*process_apertures) * *num_of_nodes); return HSAKMT_STATUS_SUCCESS; } /* The VMs from DRM render nodes are used by KFD for the lifetime of * the process. Therefore we have to keep using the same FDs for the * lifetime of the process, even when we close and reopen KFD. There * are up to 128 render nodes that we cache in this array. */ #define DRM_FIRST_RENDER_NODE 128 #define DRM_LAST_RENDER_NODE 255 static int drm_render_fds[DRM_LAST_RENDER_NODE + 1 - DRM_FIRST_RENDER_NODE]; /* amdgpu device handle for each gpu that libdrm uses */ static struct amdgpu_device *amdgpu_handle[DRM_LAST_RENDER_NODE + 1 - DRM_FIRST_RENDER_NODE]; int open_drm_render_device(int minor) { char path[128]; int index, fd; uint32_t major_drm, minor_drm; struct amdgpu_device **device_handle; if (minor < DRM_FIRST_RENDER_NODE || minor > DRM_LAST_RENDER_NODE) { pr_err("DRM render minor %d out of range [%d, %d]\n", minor, DRM_FIRST_RENDER_NODE, DRM_LAST_RENDER_NODE); return -EINVAL; } index = minor - DRM_FIRST_RENDER_NODE; /* If the render node was already opened, keep using the same FD */ if (drm_render_fds[index]) return drm_render_fds[index]; sprintf(path, "/dev/dri/renderD%d", minor); fd = open(path, O_RDWR | O_CLOEXEC); if (fd < 0) { if (errno != ENOENT && errno != EPERM) { pr_err("Failed to open %s: %s\n", path, strerror(errno)); if (errno == EACCES) pr_info("Check user is in \"video\" group\n"); } return -errno; } drm_render_fds[index] = fd; /* if amdgpu_device_get_fd availabe query render fd that libdrm uses, * then close drm_render_fds above, replace it by fd libdrm uses. */ device_handle = &amdgpu_handle[index]; if (fn_amdgpu_device_get_fd && !amdgpu_device_initialize(fd, &major_drm, &minor_drm, device_handle)) { fd = fn_amdgpu_device_get_fd(*device_handle); if (fd > 0) { close(drm_render_fds[index]); drm_render_fds[index] = fd; } else { pr_err("amdgpu_device_get_fd failed: %d\n", fd); amdgpu_device_deinitialize(*device_handle); *device_handle = 0; } } return fd; } static HSAKMT_STATUS acquire_vm(uint32_t gpu_id, int fd) { struct kfd_ioctl_acquire_vm_args args; args.gpu_id = gpu_id; args.drm_fd = fd; pr_info("acquiring VM for %x using %d\n", gpu_id, fd); if (kmtIoctl(kfd_fd, AMDKFD_IOC_ACQUIRE_VM, (void *)&args)) { pr_err("AMDKFD_IOC_ACQUIRE_VM failed\n"); return HSAKMT_STATUS_ERROR; } return HSAKMT_STATUS_SUCCESS; } static HSAKMT_STATUS init_mmap_apertures(HSAuint64 base, HSAuint64 limit, HSAuint32 align, HSAuint32 guard_pages) { void *addr; if (align > (HSAuint32)PAGE_SIZE) { /* This should never happen. Alignment constraints * only apply to old GPUs that don't support 48-bit * virtual addresses. */ pr_info("Falling back to reserved SVM apertures due to alignment contraints.\n"); return HSAKMT_STATUS_ERROR; } /* Set up one SVM aperture */ svm.apertures[SVM_DEFAULT].base = (void *)base; svm.apertures[SVM_DEFAULT].limit = (void *)limit; svm.apertures[SVM_DEFAULT].align = align; svm.apertures[SVM_DEFAULT].guard_pages = guard_pages; svm.apertures[SVM_DEFAULT].is_cpu_accessible = true; svm.apertures[SVM_DEFAULT].ops = &mmap_aperture_ops; svm.apertures[SVM_COHERENT].base = svm.apertures[SVM_COHERENT].limit = NULL; /* Try to allocate one page. If it fails, we'll fall back to * managing our own reserved address range. */ addr = aperture_allocate_area(&svm.apertures[SVM_DEFAULT], NULL, PAGE_SIZE); if (addr) { aperture_release_area(&svm.apertures[SVM_DEFAULT], addr, PAGE_SIZE); svm.dgpu_aperture = svm.dgpu_alt_aperture = &svm.apertures[SVM_DEFAULT]; pr_info("Initialized unreserved SVM apertures: %p - %p\n", svm.apertures[SVM_DEFAULT].base, svm.apertures[SVM_DEFAULT].limit); } else { pr_info("Failed to allocate unreserved SVM address space.\n"); pr_info("Falling back to reserved SVM apertures.\n"); } return addr ? HSAKMT_STATUS_SUCCESS : HSAKMT_STATUS_ERROR; } static void *reserve_address(void *addr, unsigned long long int len) { void *ret_addr; if (len <= 0) return NULL; ret_addr = mmap(addr, len, PROT_NONE, MAP_ANONYMOUS | MAP_NORESERVE | MAP_PRIVATE, -1, 0); if (ret_addr == MAP_FAILED) return NULL; return ret_addr; } /* Managed SVM aperture limits: only reserve up to 40 bits (1TB, what * GFX8 supports). Need to find at least 4GB of usable address space. */ #define SVM_RESERVATION_LIMIT ((1ULL << 40) - 1) #define SVM_MIN_VM_SIZE (4ULL << 30) #define IS_CANONICAL_ADDR(a) ((a) < (1ULL << 47)) static HSAKMT_STATUS init_svm_apertures(HSAuint64 base, HSAuint64 limit, HSAuint32 align, HSAuint32 guard_pages) { const HSAuint64 ADDR_INC = GPU_HUGE_PAGE_SIZE; HSAuint64 len, map_size, alt_base, alt_size; bool found = false; void *addr, *ret_addr; /* If we already have an SVM aperture initialized (from a * parent process), keep using it */ if (dgpu_shared_aperture_limit) return HSAKMT_STATUS_SUCCESS; /* Align base and limit to huge page size */ base = ALIGN_UP(base, GPU_HUGE_PAGE_SIZE); limit = ((limit + 1) & ~(HSAuint64)(GPU_HUGE_PAGE_SIZE - 1)) - 1; /* If the limit is greater or equal 47-bits of address space, * it means we have GFXv9 or later GPUs only. We don't need * apertures to determine the MTYPE and the virtual address * space of the GPUs covers the full CPU address range (on * x86_64) or at least mmap is unlikely to run out of * addresses the GPUs can handle. */ if (limit >= (1ULL << 47) - 1 && !svm.reserve_svm) { HSAKMT_STATUS status = init_mmap_apertures(base, limit, align, guard_pages); if (status == HSAKMT_STATUS_SUCCESS) return status; /* fall through: fall back to reserved address space */ } if (limit > SVM_RESERVATION_LIMIT) limit = SVM_RESERVATION_LIMIT; if (base >= limit) { pr_err("No SVM range compatible with all GPU and software constraints\n"); return HSAKMT_STATUS_ERROR; } /* Try to reserve address space for SVM. * * Inner loop: try start addresses in huge-page increments up * to half the VM size we're trying to reserve * * Outer loop: reduce size of the allocation by factor 2 at a * time and print a warning for every reduction */ for (len = limit - base + 1; !found && len >= SVM_MIN_VM_SIZE; len = (len + 1) >> 1) { for (addr = (void *)base, ret_addr = NULL; (HSAuint64)addr + ((len + 1) >> 1) - 1 <= limit; addr = (void *)((HSAuint64)addr + ADDR_INC)) { HSAuint64 top = MIN((HSAuint64)addr + len, limit+1); map_size = (top - (HSAuint64)addr) & ~(HSAuint64)(PAGE_SIZE - 1); if (map_size < SVM_MIN_VM_SIZE) break; ret_addr = reserve_address(addr, map_size); if (!ret_addr) break; if ((HSAuint64)ret_addr + ((len + 1) >> 1) - 1 <= limit) /* At least half the returned address * space is GPU addressable, we'll * take it */ break; munmap(ret_addr, map_size); ret_addr = NULL; } if (!ret_addr) { pr_warn("Failed to reserve %uGB for SVM ...\n", (unsigned int)(len >> 30)); continue; } if ((HSAuint64)ret_addr + SVM_MIN_VM_SIZE - 1 > limit) { /* addressable size is less than the minimum */ pr_warn("Got %uGB for SVM at %p with only %dGB usable ...\n", (unsigned int)(map_size >> 30), ret_addr, (int)((limit - (HSAint64)ret_addr) >> 30)); munmap(ret_addr, map_size); ret_addr = NULL; continue; } else { found = true; break; } } if (!found) { pr_err("Failed to reserve SVM address range. Giving up.\n"); return HSAKMT_STATUS_ERROR; } base = (HSAuint64)ret_addr; if (base + map_size - 1 > limit) /* trim the tail that's not GPU-addressable */ munmap((void *)(limit + 1), base + map_size - 1 - limit); else limit = base + map_size - 1; /* init two apertures for non-coherent and coherent memory */ svm.apertures[SVM_DEFAULT].base = dgpu_shared_aperture_base = ret_addr; svm.apertures[SVM_DEFAULT].limit = dgpu_shared_aperture_limit = (void *)limit; svm.apertures[SVM_DEFAULT].align = align; svm.apertures[SVM_DEFAULT].guard_pages = guard_pages; svm.apertures[SVM_DEFAULT].is_cpu_accessible = true; svm.apertures[SVM_DEFAULT].ops = &reserved_aperture_ops; /* Use the first 1/4 of the dGPU aperture as * alternate aperture for coherent access. * Base and size must be 64KB aligned. */ alt_base = (HSAuint64)svm.apertures[SVM_DEFAULT].base; alt_size = (VOID_PTRS_SUB(svm.apertures[SVM_DEFAULT].limit, svm.apertures[SVM_DEFAULT].base) + 1) >> 2; alt_base = (alt_base + 0xffff) & ~0xffffULL; alt_size = (alt_size + 0xffff) & ~0xffffULL; svm.apertures[SVM_COHERENT].base = (void *)alt_base; svm.apertures[SVM_COHERENT].limit = (void *)(alt_base + alt_size - 1); svm.apertures[SVM_COHERENT].align = align; svm.apertures[SVM_COHERENT].guard_pages = guard_pages; svm.apertures[SVM_COHERENT].is_cpu_accessible = true; svm.apertures[SVM_COHERENT].ops = &reserved_aperture_ops; svm.apertures[SVM_DEFAULT].base = VOID_PTR_ADD(svm.apertures[SVM_COHERENT].limit, 1); pr_info("SVM alt (coherent): %12p - %12p\n", svm.apertures[SVM_COHERENT].base, svm.apertures[SVM_COHERENT].limit); pr_info("SVM (non-coherent): %12p - %12p\n", svm.apertures[SVM_DEFAULT].base, svm.apertures[SVM_DEFAULT].limit); svm.dgpu_aperture = &svm.apertures[SVM_DEFAULT]; svm.dgpu_alt_aperture = &svm.apertures[SVM_COHERENT]; return HSAKMT_STATUS_SUCCESS; } static void fmm_init_rbtree(void) { static int once; int i = gpu_mem_count; if (once++ == 0) { rbtree_init(&svm.apertures[SVM_DEFAULT].tree); rbtree_init(&svm.apertures[SVM_DEFAULT].user_tree); rbtree_init(&svm.apertures[SVM_COHERENT].tree); rbtree_init(&svm.apertures[SVM_COHERENT].user_tree); rbtree_init(&cpuvm_aperture.tree); rbtree_init(&cpuvm_aperture.user_tree); rbtree_init(&mem_handle_aperture.tree); rbtree_init(&mem_handle_aperture.user_tree); } while (i--) { rbtree_init(&gpu_mem[i].scratch_physical.tree); rbtree_init(&gpu_mem[i].scratch_physical.user_tree); rbtree_init(&gpu_mem[i].gpuvm_aperture.tree); rbtree_init(&gpu_mem[i].gpuvm_aperture.user_tree); } } static void *map_mmio(uint32_t node_id, uint32_t gpu_id, int mmap_fd) { void *mem; manageable_aperture_t *aperture = svm.dgpu_alt_aperture; uint32_t ioc_flags; vm_object_t *vm_obj = NULL; HsaMemFlags mflags; void *ret; uint64_t mmap_offset; /* Allocate physical memory and vm object*/ ioc_flags = KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | KFD_IOC_ALLOC_MEM_FLAGS_COHERENT; mem = __fmm_allocate_device(gpu_id, NULL, PAGE_SIZE, aperture, &mmap_offset, ioc_flags, &vm_obj); if (!mem || !vm_obj) return NULL; mflags.Value = 0; mflags.ui32.NonPaged = 1; mflags.ui32.HostAccess = 1; mflags.ui32.Reserved = 0; pthread_mutex_lock(&aperture->fmm_mutex); vm_obj->mflags = mflags; vm_obj->node_id = node_id; pthread_mutex_unlock(&aperture->fmm_mutex); /* Map for CPU access*/ ret = mmap(mem, PAGE_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, mmap_fd, mmap_offset); if (ret == MAP_FAILED) { __fmm_release(vm_obj, aperture); return NULL; } /* Map for GPU access*/ if (fmm_map_to_gpu(mem, PAGE_SIZE, NULL)) { __fmm_release(vm_obj, aperture); return NULL; } return mem; } static void release_mmio(void) { uint32_t gpu_mem_id; for (gpu_mem_id = 0; (uint32_t)gpu_mem_id < gpu_mem_count; gpu_mem_id++) { if (!gpu_mem[gpu_mem_id].mmio_aperture.base) continue; fmm_unmap_from_gpu(gpu_mem[gpu_mem_id].mmio_aperture.base); munmap(gpu_mem[gpu_mem_id].mmio_aperture.base, PAGE_SIZE); fmm_release(gpu_mem[gpu_mem_id].mmio_aperture.base); } } HSAKMT_STATUS fmm_get_amdgpu_device_handle(uint32_t node_id, HsaAMDGPUDeviceHandle *DeviceHandle) { int32_t i = gpu_mem_find_by_node_id(node_id); int index; if (i < 0) return HSAKMT_STATUS_INVALID_NODE_UNIT; index = gpu_mem[i].drm_render_minor - DRM_FIRST_RENDER_NODE; if (!amdgpu_handle[index]) return HSAKMT_STATUS_INVALID_HANDLE; *DeviceHandle = amdgpu_handle[index]; return HSAKMT_STATUS_SUCCESS; } static bool two_apertures_overlap(void *start_1, void *limit_1, void *start_2, void *limit_2) { return (start_1 >= start_2 && start_1 <= limit_2) || (start_2 >= start_1 && start_2 <= limit_1); } static bool init_mem_handle_aperture(HSAuint32 align, HSAuint32 guard_pages) { bool found; uint32_t i; /* init mem_handle_aperture for buffer handler management */ mem_handle_aperture.align = align; mem_handle_aperture.guard_pages = guard_pages; mem_handle_aperture.is_cpu_accessible = false; mem_handle_aperture.ops = &reserved_aperture_ops; while (PORT_VPTR_TO_UINT64(mem_handle_aperture.base) < END_NON_CANONICAL_ADDR - 1) { found = true; for (i = 0; i < gpu_mem_count; i++) { if (gpu_mem[i].lds_aperture.base && two_apertures_overlap(gpu_mem[i].lds_aperture.base, gpu_mem[i].lds_aperture.limit, mem_handle_aperture.base, mem_handle_aperture.limit)) { found = false; break; } if (gpu_mem[i].scratch_aperture.base && two_apertures_overlap(gpu_mem[i].scratch_aperture.base, gpu_mem[i].scratch_aperture.limit, mem_handle_aperture.base, mem_handle_aperture.limit)){ found = false; break; } if (gpu_mem[i].gpuvm_aperture.base && two_apertures_overlap(gpu_mem[i].gpuvm_aperture.base, gpu_mem[i].gpuvm_aperture.limit, mem_handle_aperture.base, mem_handle_aperture.limit)){ found = false; break; } } if (found) { pr_info("mem_handle_aperture start %p, mem_handle_aperture limit %p\n", mem_handle_aperture.base, mem_handle_aperture.limit); return true; } else { /* increase base by 1UL<<47 to check next hole */ mem_handle_aperture.base = VOID_PTR_ADD(mem_handle_aperture.base, (1UL << 47)); mem_handle_aperture.limit = VOID_PTR_ADD(mem_handle_aperture.base, (1ULL << 47)); } } /* set invalid aperture if fail locating a hole for it */ mem_handle_aperture.base = 0; mem_handle_aperture.limit = 0; return false; } HSAKMT_STATUS fmm_init_process_apertures(unsigned int NumNodes) { uint32_t i; int32_t gpu_mem_id = 0; struct kfd_process_device_apertures *process_apertures; uint32_t num_of_sysfs_nodes; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; char *disableCache, *pagedUserptr, *checkUserptr, *guardPagesStr, *reserveSvm; char *maxVaAlignStr, *useSvmStr; unsigned int guardPages = 1; uint64_t svm_base = 0, svm_limit = 0; uint32_t svm_alignment = 0; /* If HSA_DISABLE_CACHE is set to a non-0 value, disable caching */ disableCache = getenv("HSA_DISABLE_CACHE"); svm.disable_cache = (disableCache && strcmp(disableCache, "0")); /* If HSA_USERPTR_FOR_PAGED_MEM is not set or set to a non-0 * value, enable userptr for all paged memory allocations */ pagedUserptr = getenv("HSA_USERPTR_FOR_PAGED_MEM"); svm.userptr_for_paged_mem = (!pagedUserptr || strcmp(pagedUserptr, "0")); /* If HSA_CHECK_USERPTR is set to a non-0 value, check all userptrs * when they are registered */ checkUserptr = getenv("HSA_CHECK_USERPTR"); svm.check_userptr = (checkUserptr && strcmp(checkUserptr, "0")); /* If HSA_RESERVE_SVM is set to a non-0 value, * enable packet capture and replay mode. */ reserveSvm = getenv("HSA_RESERVE_SVM"); svm.reserve_svm = (reserveSvm && strcmp(reserveSvm, "0")); /* Specify number of guard pages for SVM apertures, default is 1 */ guardPagesStr = getenv("HSA_SVM_GUARD_PAGES"); if (!guardPagesStr || sscanf(guardPagesStr, "%u", &guardPages) != 1) guardPages = 1; /* Sets the max VA alignment order size during mapping. By default the order * size is set to 9(2MB) */ maxVaAlignStr = getenv("HSA_MAX_VA_ALIGN"); if (!maxVaAlignStr || sscanf(maxVaAlignStr, "%u", &svm.alignment_order) != 1) svm.alignment_order = 9; useSvmStr = getenv("HSA_USE_SVM"); svm.is_svm_api_supported = !(useSvmStr && !strcmp(useSvmStr, "0")); gpu_mem_count = 0; g_first_gpu_mem = NULL; /* Trade off - NumNodes includes GPU nodes + CPU Node. So in * systems with CPU node, slightly more memory is allocated than * necessary */ gpu_mem = (gpu_mem_t *)calloc(NumNodes, sizeof(gpu_mem_t)); if (!gpu_mem) return HSAKMT_STATUS_NO_MEMORY; /* Initialize gpu_mem[] from sysfs topology. Rest of the members are * set to 0 by calloc. This is necessary because this function * gets called before hsaKmtAcquireSystemProperties() is called. */ is_dgpu = false; for (i = 0; i < NumNodes; i++) { HsaNodeProperties props; ret = topology_get_node_props(i, &props); if (ret != HSAKMT_STATUS_SUCCESS) goto gpu_mem_init_failed; topology_setup_is_dgpu_param(&props); /* Skip non-GPU nodes */ if (props.KFDGpuID) { int fd = open_drm_render_device(props.DrmRenderMinor); if (fd <= 0) { ret = HSAKMT_STATUS_ERROR; goto gpu_mem_init_failed; } gpu_mem[gpu_mem_count].drm_render_minor = props.DrmRenderMinor; gpu_mem[gpu_mem_count].usable_peer_id_array = calloc(NumNodes, sizeof(uint32_t)); if (!gpu_mem[gpu_mem_count].usable_peer_id_array) { ret = HSAKMT_STATUS_NO_MEMORY; goto gpu_mem_init_failed; } gpu_mem[gpu_mem_count].usable_peer_id_array[0] = props.KFDGpuID; gpu_mem[gpu_mem_count].usable_peer_id_num = 1; gpu_mem[gpu_mem_count].EngineId.ui32.Major = props.EngineId.ui32.Major; gpu_mem[gpu_mem_count].EngineId.ui32.Minor = props.EngineId.ui32.Minor; gpu_mem[gpu_mem_count].EngineId.ui32.Stepping = props.EngineId.ui32.Stepping; gpu_mem[gpu_mem_count].drm_render_fd = fd; gpu_mem[gpu_mem_count].gpu_id = props.KFDGpuID; gpu_mem[gpu_mem_count].local_mem_size = props.LocalMemSize; gpu_mem[gpu_mem_count].device_id = props.DeviceId; gpu_mem[gpu_mem_count].node_id = i; svm.is_svm_api_supported &= props.Capability.ui32.SVMAPISupported; gpu_mem[gpu_mem_count].scratch_physical.align = PAGE_SIZE; gpu_mem[gpu_mem_count].scratch_physical.ops = &reserved_aperture_ops; pthread_mutex_init(&gpu_mem[gpu_mem_count].scratch_physical.fmm_mutex, NULL); gpu_mem[gpu_mem_count].gpuvm_aperture.align = get_vm_alignment(props.DeviceId); gpu_mem[gpu_mem_count].gpuvm_aperture.guard_pages = guardPages; gpu_mem[gpu_mem_count].gpuvm_aperture.ops = &reserved_aperture_ops; pthread_mutex_init(&gpu_mem[gpu_mem_count].gpuvm_aperture.fmm_mutex, NULL); if (!g_first_gpu_mem) g_first_gpu_mem = &gpu_mem[gpu_mem_count]; gpu_mem_count++; } } /* The ioctl will also return Number of Nodes if * args.kfd_process_device_apertures_ptr is set to NULL. This is not * required since Number of nodes is already known. Kernel will fill in * the apertures in kfd_process_device_apertures_ptr */ num_of_sysfs_nodes = get_num_sysfs_nodes(); if (num_of_sysfs_nodes < gpu_mem_count) { ret = HSAKMT_STATUS_ERROR; goto sysfs_parse_failed; } process_apertures = calloc(num_of_sysfs_nodes, sizeof(struct kfd_process_device_apertures)); if (!process_apertures) { ret = HSAKMT_STATUS_NO_MEMORY; goto sysfs_parse_failed; } /* GPU Resource management can disable some of the GPU nodes. * The Kernel driver could be not aware of this. * Get from Kernel driver information of all the nodes and then filter it. */ ret = get_process_apertures(process_apertures, &num_of_sysfs_nodes); if (ret != HSAKMT_STATUS_SUCCESS) goto get_aperture_ioctl_failed; all_gpu_id_array_size = 0; all_gpu_id_array = NULL; if (num_of_sysfs_nodes > 0) { all_gpu_id_array = malloc(sizeof(uint32_t) * gpu_mem_count); if (!all_gpu_id_array) { ret = HSAKMT_STATUS_NO_MEMORY; goto get_aperture_ioctl_failed; } } for (i = 0 ; i < num_of_sysfs_nodes ; i++) { HsaNodeProperties nodeProps; HsaIoLinkProperties linkProps[NumNodes]; uint32_t nodeId; uint32_t j; /* Map Kernel process device data node i <--> gpu_mem_id which * indexes into gpu_mem[] based on gpu_id */ gpu_mem_id = gpu_mem_find_by_gpu_id(process_apertures[i].gpu_id); if (gpu_mem_id < 0) continue; if (all_gpu_id_array_size == gpu_mem_count) { ret = HSAKMT_STATUS_ERROR; goto aperture_init_failed; } all_gpu_id_array[all_gpu_id_array_size++] = process_apertures[i].gpu_id; /* Add this GPU to the usable_peer_id_arrays of all GPUs that * this GPU has an IO link to. This GPU can map memory * allocated on those GPUs. */ nodeId = gpu_mem[gpu_mem_id].node_id; ret = topology_get_node_props(nodeId, &nodeProps); if (ret != HSAKMT_STATUS_SUCCESS) goto aperture_init_failed; assert(nodeProps.NumIOLinks <= NumNodes); ret = topology_get_iolink_props(nodeId, nodeProps.NumIOLinks, linkProps); if (ret != HSAKMT_STATUS_SUCCESS) goto aperture_init_failed; for (j = 0; j < nodeProps.NumIOLinks; j++) { int32_t to_gpu_mem_id = gpu_mem_find_by_node_id(linkProps[j].NodeTo); uint32_t peer; if (to_gpu_mem_id < 0) continue; assert(gpu_mem[to_gpu_mem_id].usable_peer_id_num < NumNodes); peer = gpu_mem[to_gpu_mem_id].usable_peer_id_num++; gpu_mem[to_gpu_mem_id].usable_peer_id_array[peer] = gpu_mem[gpu_mem_id].gpu_id; } gpu_mem[gpu_mem_id].lds_aperture.base = PORT_UINT64_TO_VPTR(process_apertures[i].lds_base); gpu_mem[gpu_mem_id].lds_aperture.limit = PORT_UINT64_TO_VPTR(process_apertures[i].lds_limit); gpu_mem[gpu_mem_id].scratch_aperture.base = PORT_UINT64_TO_VPTR(process_apertures[i].scratch_base); gpu_mem[gpu_mem_id].scratch_aperture.limit = PORT_UINT64_TO_VPTR(process_apertures[i].scratch_limit); if (IS_CANONICAL_ADDR(process_apertures[i].gpuvm_limit)) { uint64_t vm_alignment = get_vm_alignment( gpu_mem[gpu_mem_id].device_id); /* Set proper alignment for scratch backing aperture */ gpu_mem[gpu_mem_id].scratch_physical.align = vm_alignment; /* Non-canonical per-ASIC GPUVM aperture does * not exist on dGPUs in GPUVM64 address mode */ gpu_mem[gpu_mem_id].gpuvm_aperture.base = NULL; gpu_mem[gpu_mem_id].gpuvm_aperture.limit = NULL; /* Update SVM aperture limits and alignment */ if (process_apertures[i].gpuvm_base > svm_base) svm_base = process_apertures[i].gpuvm_base; if (process_apertures[i].gpuvm_limit < svm_limit || svm_limit == 0) svm_limit = process_apertures[i].gpuvm_limit; if (vm_alignment > svm_alignment) svm_alignment = vm_alignment; } else { gpu_mem[gpu_mem_id].gpuvm_aperture.base = PORT_UINT64_TO_VPTR(process_apertures[i].gpuvm_base); gpu_mem[gpu_mem_id].gpuvm_aperture.limit = PORT_UINT64_TO_VPTR(process_apertures[i].gpuvm_limit); /* Reserve space at the start of the * aperture. After subtracting the base, we * don't want valid pointers to become NULL. */ aperture_allocate_area( &gpu_mem[gpu_mem_id].gpuvm_aperture, NULL, gpu_mem[gpu_mem_id].gpuvm_aperture.align); } /* Acquire the VM from the DRM render node for KFD use */ ret = acquire_vm(gpu_mem[gpu_mem_id].gpu_id, gpu_mem[gpu_mem_id].drm_render_fd); if (ret != HSAKMT_STATUS_SUCCESS) goto aperture_init_failed; } all_gpu_id_array_size *= sizeof(uint32_t); if (svm_limit) { /* At least one GPU uses GPUVM in canonical address * space. Set up SVM apertures shared by all such GPUs */ ret = init_svm_apertures(svm_base, svm_limit, svm_alignment, guardPages); if (ret != HSAKMT_STATUS_SUCCESS) goto init_svm_failed; for (i = 0 ; i < num_of_sysfs_nodes ; i++) { uintptr_t alt_base; uint64_t alt_size; int err; if (!IS_CANONICAL_ADDR(process_apertures[i].gpuvm_limit)) continue; /* Set memory policy to match the SVM apertures */ alt_base = (uintptr_t)svm.dgpu_alt_aperture->base; alt_size = VOID_PTRS_SUB(svm.dgpu_alt_aperture->limit, svm.dgpu_alt_aperture->base) + 1; err = fmm_set_memory_policy(process_apertures[i].gpu_id, svm.disable_cache ? KFD_IOC_CACHE_POLICY_COHERENT : KFD_IOC_CACHE_POLICY_NONCOHERENT, KFD_IOC_CACHE_POLICY_COHERENT, alt_base, alt_size); if (err) { pr_err("Failed to set mem policy for GPU [0x%x]\n", process_apertures[i].gpu_id); ret = HSAKMT_STATUS_ERROR; goto set_memory_policy_failed; } } } cpuvm_aperture.align = PAGE_SIZE; cpuvm_aperture.limit = (void *)0x7FFFFFFFFFFF; /* 2^47 - 1 */ fmm_init_rbtree(); if (!init_mem_handle_aperture(PAGE_SIZE, guardPages)) pr_err("Failed to init mem_handle_aperture\n"); for (gpu_mem_id = 0; (uint32_t)gpu_mem_id < gpu_mem_count; gpu_mem_id++) { if (!topology_is_svm_needed(gpu_mem[gpu_mem_id].EngineId)) continue; gpu_mem[gpu_mem_id].mmio_aperture.base = map_mmio( gpu_mem[gpu_mem_id].node_id, gpu_mem[gpu_mem_id].gpu_id, kfd_fd); if (gpu_mem[gpu_mem_id].mmio_aperture.base) gpu_mem[gpu_mem_id].mmio_aperture.limit = (void *) ((char *)gpu_mem[gpu_mem_id].mmio_aperture.base + PAGE_SIZE - 1); else pr_err("Failed to map remapped mmio page on gpu_mem %d\n", gpu_mem_id); } free(process_apertures); return ret; aperture_init_failed: init_svm_failed: set_memory_policy_failed: free(all_gpu_id_array); all_gpu_id_array = NULL; get_aperture_ioctl_failed: free(process_apertures); sysfs_parse_failed: gpu_mem_init_failed: fmm_destroy_process_apertures(); return ret; } void fmm_destroy_process_apertures(void) { release_mmio(); if (gpu_mem) { while (gpu_mem_count-- > 0) free(gpu_mem[gpu_mem_count].usable_peer_id_array); free(gpu_mem); gpu_mem = NULL; } gpu_mem_count = 0; } HSAKMT_STATUS fmm_get_aperture_base_and_limit(aperture_type_e aperture_type, HSAuint32 gpu_id, HSAuint64 *aperture_base, HSAuint64 *aperture_limit) { HSAKMT_STATUS err = HSAKMT_STATUS_ERROR; int32_t slot = gpu_mem_find_by_gpu_id(gpu_id); if (slot < 0) return HSAKMT_STATUS_INVALID_PARAMETER; switch (aperture_type) { case FMM_GPUVM: if (aperture_is_valid(gpu_mem[slot].gpuvm_aperture.base, gpu_mem[slot].gpuvm_aperture.limit)) { *aperture_base = PORT_VPTR_TO_UINT64(gpu_mem[slot].gpuvm_aperture.base); *aperture_limit = PORT_VPTR_TO_UINT64(gpu_mem[slot].gpuvm_aperture.limit); err = HSAKMT_STATUS_SUCCESS; } break; case FMM_SCRATCH: if (aperture_is_valid(gpu_mem[slot].scratch_aperture.base, gpu_mem[slot].scratch_aperture.limit)) { *aperture_base = PORT_VPTR_TO_UINT64(gpu_mem[slot].scratch_aperture.base); *aperture_limit = PORT_VPTR_TO_UINT64(gpu_mem[slot].scratch_aperture.limit); err = HSAKMT_STATUS_SUCCESS; } break; case FMM_LDS: if (aperture_is_valid(gpu_mem[slot].lds_aperture.base, gpu_mem[slot].lds_aperture.limit)) { *aperture_base = PORT_VPTR_TO_UINT64(gpu_mem[slot].lds_aperture.base); *aperture_limit = PORT_VPTR_TO_UINT64(gpu_mem[slot].lds_aperture.limit); err = HSAKMT_STATUS_SUCCESS; } break; case FMM_SVM: /* Report single SVM aperture, starting at base of * fine-grained, ending at limit of coarse-grained */ if (aperture_is_valid(svm.dgpu_alt_aperture->base, svm.dgpu_aperture->limit)) { *aperture_base = PORT_VPTR_TO_UINT64(svm.dgpu_alt_aperture->base); *aperture_limit = PORT_VPTR_TO_UINT64(svm.dgpu_aperture->limit); err = HSAKMT_STATUS_SUCCESS; } break; case FMM_MMIO: if (aperture_is_valid(gpu_mem[slot].mmio_aperture.base, gpu_mem[slot].mmio_aperture.limit)) { *aperture_base = PORT_VPTR_TO_UINT64(gpu_mem[slot].mmio_aperture.base); *aperture_limit = PORT_VPTR_TO_UINT64(gpu_mem[slot].mmio_aperture.limit); err = HSAKMT_STATUS_SUCCESS; } break; default: break; } return err; } static bool id_in_array(uint32_t id, uint32_t *ids_array, uint32_t ids_array_size) { uint32_t i; for (i = 0; i < ids_array_size/sizeof(uint32_t); i++) { if (id == ids_array[i]) return true; } return false; } /* Helper function to remove ids_array from * obj->mapped_device_id_array */ static void remove_device_ids_from_mapped_array(vm_object_t *obj, uint32_t *ids_array, uint32_t ids_array_size) { uint32_t i = 0, j = 0; if (obj->mapped_device_id_array == ids_array) goto set_size_and_free; for (i = 0; i < obj->mapped_device_id_array_size/ sizeof(uint32_t); i++) { if (!id_in_array(obj->mapped_device_id_array[i], ids_array, ids_array_size)) obj->mapped_device_id_array[j++] = obj->mapped_device_id_array[i]; } set_size_and_free: obj->mapped_device_id_array_size = j*sizeof(uint32_t); if (!j) { if (obj->mapped_device_id_array) free(obj->mapped_device_id_array); obj->mapped_device_id_array = NULL; } } /* Helper function to add ids_array to * obj->mapped_device_id_array */ static void add_device_ids_to_mapped_array(vm_object_t *obj, uint32_t *ids_array, uint32_t ids_array_size) { uint32_t new_array_size; /* Remove any potential duplicated ids */ remove_device_ids_from_mapped_array(obj, ids_array, ids_array_size); new_array_size = obj->mapped_device_id_array_size + ids_array_size; obj->mapped_device_id_array = (uint32_t *)realloc( obj->mapped_device_id_array, new_array_size); memcpy(&obj->mapped_device_id_array [obj->mapped_device_id_array_size/sizeof(uint32_t)], ids_array, ids_array_size); obj->mapped_device_id_array_size = new_array_size; } /* If nodes_to_map is not NULL, map the nodes specified; otherwise map all. */ static HSAKMT_STATUS _fmm_map_to_gpu(manageable_aperture_t *aperture, void *address, uint64_t size, vm_object_t *obj, uint32_t *nodes_to_map, uint32_t nodes_array_size) { struct kfd_ioctl_map_memory_to_gpu_args args = {0}; vm_object_t *object; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; int ret_ioctl; if (!obj) pthread_mutex_lock(&aperture->fmm_mutex); object = obj; if (!object) { /* Find the object to retrieve the handle */ object = vm_find_object_by_address(aperture, address, 0); if (!object) { ret = HSAKMT_STATUS_INVALID_HANDLE; goto err_object_not_found; } } /* For a memory region that is registered by user pointer, changing * mapping nodes is not allowed, so we don't need to check the mapping * nodes or map if it's already mapped. Just increase the reference. */ if (object->userptr && object->mapping_count) { ++object->mapping_count; goto exit_ok; } args.handle = object->handle; if (nodes_to_map) { /* If specified, map the requested */ args.device_ids_array_ptr = (uint64_t)nodes_to_map; args.n_devices = nodes_array_size / sizeof(uint32_t); } else if (object->registered_device_id_array_size > 0) { /* otherwise map all registered */ args.device_ids_array_ptr = (uint64_t)object->registered_device_id_array; args.n_devices = object->registered_device_id_array_size / sizeof(uint32_t); } else { /* not specified, not registered: map all GPUs */ int32_t gpu_mem_id = gpu_mem_find_by_node_id(obj->node_id); if (!obj->userptr && get_device_id_by_node_id(obj->node_id) && gpu_mem_id >= 0) { args.device_ids_array_ptr = (uint64_t) gpu_mem[gpu_mem_id].usable_peer_id_array; args.n_devices = gpu_mem[gpu_mem_id].usable_peer_id_num; } else { args.device_ids_array_ptr = (uint64_t)all_gpu_id_array; args.n_devices = all_gpu_id_array_size / sizeof(uint32_t); } } args.n_success = 0; ret_ioctl = kmtIoctl(kfd_fd, AMDKFD_IOC_MAP_MEMORY_TO_GPU, &args); if (ret_ioctl) { pr_err("GPU mapping failed (%d) for obj at %p, userptr %p, size %lu", ret_ioctl, object->start, object->userptr, object->size); ret = HSAKMT_STATUS_ERROR; goto err_map_failed; } add_device_ids_to_mapped_array(object, (uint32_t *)args.device_ids_array_ptr, args.n_success * sizeof(uint32_t)); print_device_id_array((uint32_t *)object->mapped_device_id_array, object->mapped_device_id_array_size); object->mapping_count = 1; /* Mapping changed and lifecycle of object->mapped_node_id_array * terminates here. Free it and allocate on next query */ if (object->mapped_node_id_array) { free(object->mapped_node_id_array); object->mapped_node_id_array = NULL; } exit_ok: err_object_not_found: err_map_failed: if (!obj) pthread_mutex_unlock(&aperture->fmm_mutex); return ret; } static HSAKMT_STATUS _fmm_map_to_gpu_scratch(uint32_t gpu_id, manageable_aperture_t *aperture, void *address, uint64_t size) { int32_t gpu_mem_id; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; bool is_debugger = 0; uint32_t flags; void *mmap_ret = NULL; uint64_t mmap_offset = 0; vm_object_t *obj; /* Retrieve gpu_mem id according to gpu_id */ gpu_mem_id = gpu_mem_find_by_gpu_id(gpu_id); if (gpu_mem_id < 0) return HSAKMT_STATUS_INVALID_PARAMETER; if (!is_dgpu) return HSAKMT_STATUS_SUCCESS; /* Nothing to do on APU */ /* sanity check the address */ if (address < aperture->base || VOID_PTR_ADD(address, size - 1) > aperture->limit) return HSAKMT_STATUS_INVALID_PARAMETER; is_debugger = debug_get_reg_status(gpu_mem[gpu_mem_id].node_id); flags = is_debugger ? KFD_IOC_ALLOC_MEM_FLAGS_GTT : KFD_IOC_ALLOC_MEM_FLAGS_VRAM; flags |= KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE; /* allocate object within the scratch backing aperture */ obj = fmm_allocate_memory_object(gpu_id, address, size, aperture, &mmap_offset, flags); if (!obj) return HSAKMT_STATUS_INVALID_HANDLE; /* Create a CPU mapping for the debugger */ mmap_ret = fmm_map_to_cpu(address, size, is_debugger, gpu_mem[gpu_mem_id].drm_render_fd, mmap_offset); if (mmap_ret == MAP_FAILED) { __fmm_release(obj, aperture); return HSAKMT_STATUS_ERROR; } /* map to GPU */ ret = _fmm_map_to_gpu(aperture, address, size, NULL, &gpu_id, sizeof(uint32_t)); if (ret != HSAKMT_STATUS_SUCCESS) __fmm_release(obj, aperture); return ret; } static HSAKMT_STATUS _fmm_map_to_gpu_userptr(void *addr, uint64_t size, uint64_t *gpuvm_addr, vm_object_t *object, uint32_t *nodes_to_map, uint32_t nodes_array_size) { manageable_aperture_t *aperture; void *svm_addr; HSAuint32 page_offset = (HSAuint64)addr & (PAGE_SIZE-1); HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; aperture = svm.dgpu_aperture; /* Map and return the GPUVM address adjusted by the offset * from the start of the page */ if (svm.is_svm_api_supported) { svm_addr = (void*)((HSAuint64)addr - page_offset); if (!nodes_to_map) { nodes_to_map = all_gpu_id_array; nodes_array_size = all_gpu_id_array_size; } pr_debug("%s Mapping Address %p size aligned: %ld offset: %x\n", __func__, svm_addr, PAGE_ALIGN_UP(page_offset + size), page_offset); ret = fmm_map_mem_svm_api(svm_addr, PAGE_ALIGN_UP(page_offset + size), nodes_to_map, nodes_array_size / sizeof(uint32_t)); } else { svm_addr = object->start; ret = _fmm_map_to_gpu(aperture, svm_addr, object->size, object, NULL, 0); } if (ret == HSAKMT_STATUS_SUCCESS && gpuvm_addr) *gpuvm_addr = (uint64_t)svm_addr + page_offset; return ret; } HSAKMT_STATUS fmm_map_to_gpu(void *address, uint64_t size, uint64_t *gpuvm_address) { manageable_aperture_t *aperture; vm_object_t *object; uint32_t i; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; /* Special handling for scratch memory */ for (i = 0; i < gpu_mem_count; i++) if (gpu_mem[i].gpu_id != NON_VALID_GPU_ID && address >= gpu_mem[i].scratch_physical.base && address <= gpu_mem[i].scratch_physical.limit) return _fmm_map_to_gpu_scratch(gpu_mem[i].gpu_id, &gpu_mem[i].scratch_physical, address, size); object = vm_find_object(address, size, &aperture); if (!object && !svm.is_svm_api_supported ) { if (!is_dgpu) { /* Prefetch memory on APUs with dummy-reads */ fmm_check_user_memory(address, size); return HSAKMT_STATUS_SUCCESS; } pr_err("Object not found at %p\n", address); return HSAKMT_STATUS_INVALID_PARAMETER; } /* Successful vm_find_object returns with the aperture locked */ /* allocate VA only */ if (object && object->handle == 0) { pthread_mutex_unlock(&aperture->fmm_mutex); return HSAKMT_STATUS_INVALID_PARAMETER; } /* allocate buffer only, should be mapped by GEM API */ if (aperture == &mem_handle_aperture) { pthread_mutex_unlock(&aperture->fmm_mutex); return HSAKMT_STATUS_INVALID_PARAMETER; } if (aperture == &cpuvm_aperture) { /* Prefetch memory on APUs with dummy-reads */ fmm_check_user_memory(address, size); ret = HSAKMT_STATUS_SUCCESS; } else if ((svm.is_svm_api_supported && !object) || object->userptr) { ret = _fmm_map_to_gpu_userptr(address, size, gpuvm_address, object, NULL, 0); } else { ret = _fmm_map_to_gpu(aperture, address, size, object, NULL, 0); /* Update alternate GPUVM address only for * CPU-invisible apertures on old APUs */ if (ret == HSAKMT_STATUS_SUCCESS && gpuvm_address && !aperture->is_cpu_accessible) *gpuvm_address = VOID_PTRS_SUB(object->start, aperture->base); } if (object) pthread_mutex_unlock(&aperture->fmm_mutex); return ret; } static void print_device_id_array(uint32_t *device_id_array, uint32_t device_id_array_size) { #ifdef DEBUG_PRINT_APERTURE device_id_array_size /= sizeof(uint32_t); pr_info("device id array size %d\n", device_id_array_size); for (uint32_t i = 0 ; i < device_id_array_size; i++) pr_info("%d . 0x%x\n", (i+1), device_id_array[i]); #endif } static int _fmm_unmap_from_gpu(manageable_aperture_t *aperture, void *address, uint32_t *device_ids_array, uint32_t device_ids_array_size, vm_object_t *obj) { vm_object_t *object; int ret = 0; struct kfd_ioctl_unmap_memory_from_gpu_args args = {0}; HSAuint32 page_offset = (HSAint64)address & (PAGE_SIZE - 1); if (!obj) pthread_mutex_lock(&aperture->fmm_mutex); /* Find the object to retrieve the handle */ object = obj; if (!object) { object = vm_find_object_by_address(aperture, VOID_PTR_SUB(address, page_offset), 0); if (!object) { ret = -1; goto out; } } if (object->userptr && object->mapping_count > 1) { --object->mapping_count; goto out; } args.handle = object->handle; if (device_ids_array && device_ids_array_size > 0) { args.device_ids_array_ptr = (uint64_t)device_ids_array; args.n_devices = device_ids_array_size / sizeof(uint32_t); } else if (object->mapped_device_id_array_size > 0) { args.device_ids_array_ptr = (uint64_t)object->mapped_device_id_array; args.n_devices = object->mapped_device_id_array_size / sizeof(uint32_t); } else { /* * When unmap exits here it should return failing error code as the user tried to * unmap already unmapped buffer. Currently we returns success as KFDTEST and RT * need to deploy the change on there side before thunk fails on this case. */ ret = 0; goto out; } args.n_success = 0; print_device_id_array((void *)args.device_ids_array_ptr, args.n_devices * sizeof(uint32_t)); ret = kmtIoctl(kfd_fd, AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU, &args); remove_device_ids_from_mapped_array(object, (uint32_t *)args.device_ids_array_ptr, args.n_success * sizeof(uint32_t)); if (object->mapped_node_id_array) free(object->mapped_node_id_array); object->mapped_node_id_array = NULL; object->mapping_count = 0; out: if (!obj) pthread_mutex_unlock(&aperture->fmm_mutex); return ret; } static int _fmm_unmap_from_gpu_scratch(uint32_t gpu_id, manageable_aperture_t *aperture, void *address) { int32_t gpu_mem_id; vm_object_t *object; struct kfd_ioctl_unmap_memory_from_gpu_args args = {0}; int ret; /* Retrieve gpu_mem id according to gpu_id */ gpu_mem_id = gpu_mem_find_by_gpu_id(gpu_id); if (gpu_mem_id < 0) return -1; if (!is_dgpu) return 0; /* Nothing to do on APU */ pthread_mutex_lock(&aperture->fmm_mutex); /* Find the object to retrieve the handle and size */ object = vm_find_object_by_address(aperture, address, 0); if (!object) { ret = -EINVAL; goto err; } if (!object->mapped_device_id_array || object->mapped_device_id_array_size == 0) { pthread_mutex_unlock(&aperture->fmm_mutex); return 0; } /* unmap from GPU */ args.handle = object->handle; args.device_ids_array_ptr = (uint64_t)object->mapped_device_id_array; args.n_devices = object->mapped_device_id_array_size / sizeof(uint32_t); args.n_success = 0; ret = kmtIoctl(kfd_fd, AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU, &args); /* unmap from CPU while keeping the address space reserved */ mmap(address, object->size, PROT_NONE, MAP_ANONYMOUS | MAP_NORESERVE | MAP_PRIVATE | MAP_FIXED, -1, 0); remove_device_ids_from_mapped_array(object, (uint32_t *)args.device_ids_array_ptr, args.n_success * sizeof(uint32_t)); if (object->mapped_node_id_array) free(object->mapped_node_id_array); object->mapped_node_id_array = NULL; if (ret) goto err; pthread_mutex_unlock(&aperture->fmm_mutex); /* free object in scratch backing aperture */ return __fmm_release(object, aperture); err: pthread_mutex_unlock(&aperture->fmm_mutex); return ret; } int fmm_unmap_from_gpu(void *address) { manageable_aperture_t *aperture; vm_object_t *object; uint32_t i; int ret; /* Special handling for scratch memory */ for (i = 0; i < gpu_mem_count; i++) if (gpu_mem[i].gpu_id != NON_VALID_GPU_ID && address >= gpu_mem[i].scratch_physical.base && address <= gpu_mem[i].scratch_physical.limit) return _fmm_unmap_from_gpu_scratch(gpu_mem[i].gpu_id, &gpu_mem[i].scratch_physical, address); object = vm_find_object(address, 0, &aperture); if (!object) /* On APUs GPU unmapping of system memory is a no-op */ return (!is_dgpu || svm.is_svm_api_supported) ? 0 : -EINVAL; /* Successful vm_find_object returns with the aperture locked */ if (aperture == &cpuvm_aperture) /* On APUs GPU unmapping of system memory is a no-op */ ret = 0; else ret = _fmm_unmap_from_gpu(aperture, address, NULL, 0, object); pthread_mutex_unlock(&aperture->fmm_mutex); return ret; } bool fmm_get_handle(void *address, uint64_t *handle) { uint32_t i; manageable_aperture_t *aperture; vm_object_t *object; bool found; found = false; aperture = NULL; /* Find the aperture the requested address belongs to */ for (i = 0; i < gpu_mem_count; i++) { if (gpu_mem[i].gpu_id == NON_VALID_GPU_ID) continue; if ((address >= gpu_mem[i].gpuvm_aperture.base) && (address <= gpu_mem[i].gpuvm_aperture.limit)) { aperture = &gpu_mem[i].gpuvm_aperture; break; } } if (!aperture) { if ((address >= svm.dgpu_aperture->base) && (address <= svm.dgpu_aperture->limit)) { aperture = svm.dgpu_aperture; } else if ((address >= svm.dgpu_alt_aperture->base) && (address <= svm.dgpu_alt_aperture->limit)) { aperture = svm.dgpu_alt_aperture; } } if (!aperture) return false; pthread_mutex_lock(&aperture->fmm_mutex); /* Find the object to retrieve the handle */ object = vm_find_object_by_address(aperture, address, 0); if (object && handle) { *handle = object->handle; found = true; } pthread_mutex_unlock(&aperture->fmm_mutex); return found; } static HSAKMT_STATUS fmm_register_user_memory(void *addr, HSAuint64 size, vm_object_t **obj_ret, bool coarse_grain) { manageable_aperture_t *aperture = svm.dgpu_aperture; HSAuint32 page_offset = (HSAuint64)addr & (PAGE_SIZE-1); HSAuint64 aligned_addr = (HSAuint64)addr - page_offset; HSAuint64 aligned_size = PAGE_ALIGN_UP(page_offset + size); void *svm_addr; HSAuint32 gpu_id; vm_object_t *obj, *exist_obj; /* Find first GPU for creating the userptr BO */ if (!g_first_gpu_mem) return HSAKMT_STATUS_ERROR; gpu_id = g_first_gpu_mem->gpu_id; /* Optionally check that the CPU mapping is valid */ if (svm.check_userptr) fmm_check_user_memory(addr, size); /* Allocate BO, userptr address is passed in mmap_offset */ svm_addr = __fmm_allocate_device(gpu_id, NULL, aligned_size, aperture, &aligned_addr, KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE | (coarse_grain ? 0 : KFD_IOC_ALLOC_MEM_FLAGS_COHERENT), &obj); if (!svm_addr) return HSAKMT_STATUS_ERROR; if (!obj) return HSAKMT_STATUS_ERROR; pthread_mutex_lock(&aperture->fmm_mutex); /* catch the race condition where some other thread added the userptr * object already after the vm_find_object. */ exist_obj = vm_find_object_by_userptr(aperture, addr, size); if (exist_obj) { ++exist_obj->registration_count; } else { obj->userptr = addr; gpuid_to_nodeid(gpu_id, &obj->node_id); obj->userptr_size = size; obj->registration_count = 1; obj->user_node.key = rbtree_key((unsigned long)addr, size); rbtree_insert(&aperture->user_tree, &obj->user_node); } pthread_mutex_unlock(&aperture->fmm_mutex); if (exist_obj) __fmm_release(obj, aperture); if (obj_ret) *obj_ret = exist_obj ? exist_obj : obj; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS fmm_register_memory(void *address, uint64_t size_in_bytes, uint32_t *gpu_id_array, uint32_t gpu_id_array_size, bool coarse_grain) { manageable_aperture_t *aperture = NULL; vm_object_t *object = NULL; HSAKMT_STATUS ret; if (gpu_id_array_size > 0 && !gpu_id_array) return HSAKMT_STATUS_INVALID_PARAMETER; object = vm_find_object(address, size_in_bytes, &aperture); if (!object) { if (!is_dgpu) /* System memory registration on APUs is a no-op */ return HSAKMT_STATUS_SUCCESS; /* Register a new user ptr */ if (svm.is_svm_api_supported) return fmm_register_mem_svm_api(address, size_in_bytes, coarse_grain); ret = fmm_register_user_memory(address, size_in_bytes, &object, coarse_grain); if (ret != HSAKMT_STATUS_SUCCESS) return ret; if (gpu_id_array_size == 0) return HSAKMT_STATUS_SUCCESS; aperture = svm.dgpu_aperture; pthread_mutex_lock(&aperture->fmm_mutex); /* fall through for registered device ID array setup */ } else if (object->userptr) { /* Update an existing userptr */ ++object->registration_count; } /* Successful vm_find_object returns with aperture locked */ if (object->registered_device_id_array_size > 0) { /* Multiple registration is allowed, but not changing nodes */ if ((gpu_id_array_size != object->registered_device_id_array_size) || memcmp(object->registered_device_id_array, gpu_id_array, gpu_id_array_size)) { pr_err("Cannot change nodes in a registered addr.\n"); pthread_mutex_unlock(&aperture->fmm_mutex); return HSAKMT_STATUS_MEMORY_ALREADY_REGISTERED; } else { /* Delete the new array, keep the existing one. */ if (gpu_id_array) free(gpu_id_array); pthread_mutex_unlock(&aperture->fmm_mutex); return HSAKMT_STATUS_SUCCESS; } } if (gpu_id_array_size > 0) { object->registered_device_id_array = gpu_id_array; object->registered_device_id_array_size = gpu_id_array_size; /* Registration of object changed. Lifecycle of object-> * registered_node_id_array terminates here. Free old one * and re-allocate on next query */ if (object->registered_node_id_array) { free(object->registered_node_id_array); object->registered_node_id_array = NULL; } } pthread_mutex_unlock(&aperture->fmm_mutex); return HSAKMT_STATUS_SUCCESS; } #define GRAPHICS_METADATA_DEFAULT_SIZE 64 HSAKMT_STATUS fmm_register_graphics_handle(HSAuint64 GraphicsResourceHandle, HsaGraphicsResourceInfo *GraphicsResourceInfo, uint32_t *gpu_id_array, uint32_t gpu_id_array_size) { struct kfd_ioctl_get_dmabuf_info_args infoArgs = {0}; struct kfd_ioctl_import_dmabuf_args importArgs = {0}; struct kfd_ioctl_free_memory_of_gpu_args freeArgs = {0}; manageable_aperture_t *aperture; HsaMemFlags mflags; vm_object_t *obj; void *metadata; void *mem, *aperture_base = NULL; int32_t gpu_mem_id; int r; HSAKMT_STATUS status = HSAKMT_STATUS_ERROR; static const uint64_t IMAGE_ALIGN = 256*1024; if (gpu_id_array_size > 0 && !gpu_id_array) return HSAKMT_STATUS_INVALID_PARAMETER; infoArgs.dmabuf_fd = GraphicsResourceHandle; infoArgs.metadata_size = GRAPHICS_METADATA_DEFAULT_SIZE; metadata = calloc(infoArgs.metadata_size, 1); if (!metadata) return HSAKMT_STATUS_NO_MEMORY; infoArgs.metadata_ptr = (uint64_t)metadata; r = kmtIoctl(kfd_fd, AMDKFD_IOC_GET_DMABUF_INFO, (void *)&infoArgs); if (r && infoArgs.metadata_size > GRAPHICS_METADATA_DEFAULT_SIZE) { /* Try again with bigger metadata */ free(metadata); metadata = calloc(infoArgs.metadata_size, 1); if (!metadata) return HSAKMT_STATUS_NO_MEMORY; infoArgs.metadata_ptr = (uint64_t)metadata; r = kmtIoctl(kfd_fd, AMDKFD_IOC_GET_DMABUF_INFO, (void *)&infoArgs); } if (r) goto error_free_metadata; /* Choose aperture based on GPU and allocate virtual address */ gpu_mem_id = gpu_mem_find_by_gpu_id(infoArgs.gpu_id); if (gpu_mem_id < 0) goto error_free_metadata; /* import DMA buffer without VA assigned */ if (!gpu_id_array && gpu_id_array_size == 0) { aperture = &mem_handle_aperture; } else if (topology_is_svm_needed(gpu_mem[gpu_mem_id].EngineId)) { aperture = svm.dgpu_aperture; } else { aperture = &gpu_mem[gpu_mem_id].gpuvm_aperture; aperture_base = aperture->base; } if (!aperture_is_valid(aperture->base, aperture->limit)) goto error_free_metadata; pthread_mutex_lock(&aperture->fmm_mutex); mem = aperture_allocate_area_aligned(aperture, NULL, infoArgs.size, IMAGE_ALIGN); pthread_mutex_unlock(&aperture->fmm_mutex); if (!mem) goto error_free_metadata; /* Import DMA buffer */ if (aperture == &mem_handle_aperture) importArgs.va_addr = 0; else importArgs.va_addr = VOID_PTRS_SUB(mem, aperture_base); importArgs.gpu_id = infoArgs.gpu_id; importArgs.dmabuf_fd = GraphicsResourceHandle; r = kmtIoctl(kfd_fd, AMDKFD_IOC_IMPORT_DMABUF, (void *)&importArgs); if (r) goto error_release_aperture; pthread_mutex_lock(&aperture->fmm_mutex); mflags = fmm_translate_ioc_to_hsa_flags(infoArgs.flags); mflags.ui32.CoarseGrain = 1; obj = aperture_allocate_object(aperture, mem, importArgs.handle, infoArgs.size, mflags); if (obj) { obj->metadata = metadata; obj->registered_device_id_array = gpu_id_array; obj->registered_device_id_array_size = gpu_id_array_size; gpuid_to_nodeid(infoArgs.gpu_id, &obj->node_id); } pthread_mutex_unlock(&aperture->fmm_mutex); if (!obj) goto error_release_buffer; GraphicsResourceInfo->MemoryAddress = mem; GraphicsResourceInfo->SizeInBytes = infoArgs.size; GraphicsResourceInfo->Metadata = (void *)(unsigned long)infoArgs.metadata_ptr; GraphicsResourceInfo->MetadataSizeInBytes = infoArgs.metadata_size; gpuid_to_nodeid(infoArgs.gpu_id, &GraphicsResourceInfo->NodeId); return HSAKMT_STATUS_SUCCESS; error_release_buffer: freeArgs.handle = importArgs.handle; kmtIoctl(kfd_fd, AMDKFD_IOC_FREE_MEMORY_OF_GPU, &freeArgs); error_release_aperture: aperture_release_area(aperture, mem, infoArgs.size); error_free_metadata: free(metadata); return status; } HSAKMT_STATUS fmm_export_dma_buf_fd(void *MemoryAddress, HSAuint64 MemorySizeInBytes, int *DMABufFd, HSAuint64 *Offset) { struct kfd_ioctl_export_dmabuf_args exportArgs = {0}; manageable_aperture_t *aperture; HsaApertureInfo ApeInfo; vm_object_t *obj; HSAuint64 offset; int r; aperture = fmm_find_aperture(MemoryAddress, &ApeInfo); if (!aperture) return HSAKMT_STATUS_INVALID_PARAMETER; pthread_mutex_lock(&aperture->fmm_mutex); obj = vm_find_object_by_address_range(aperture, MemoryAddress); if (obj) { offset = VOID_PTRS_SUB(MemoryAddress, obj->start); if (offset + MemorySizeInBytes <= obj->size) { exportArgs.handle = obj->handle; exportArgs.flags = O_CLOEXEC; exportArgs.dmabuf_fd = 0; } else { obj = NULL; } } pthread_mutex_unlock(&aperture->fmm_mutex); if (!obj) return HSAKMT_STATUS_INVALID_PARAMETER; r = kmtIoctl(kfd_fd, AMDKFD_IOC_EXPORT_DMABUF, (void *)&exportArgs); if (r) return HSAKMT_STATUS_ERROR; *DMABufFd = exportArgs.dmabuf_fd; *Offset = offset; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS fmm_share_memory(void *MemoryAddress, HSAuint64 SizeInBytes, HsaSharedMemoryHandle *SharedMemoryHandle) { int r = 0; HSAuint32 gpu_id = 0; vm_object_t *obj = NULL; manageable_aperture_t *aperture = NULL; struct kfd_ioctl_ipc_export_handle_args exportArgs = {0}; HsaApertureInfo ApeInfo; HsaSharedMemoryStruct *SharedMemoryStruct = to_hsa_shared_memory_struct(SharedMemoryHandle); if (SizeInBytes >= (1ULL << ((sizeof(HSAuint32) * 8) + PAGE_SHIFT))) return HSAKMT_STATUS_INVALID_PARAMETER; aperture = fmm_find_aperture(MemoryAddress, &ApeInfo); if (!aperture) return HSAKMT_STATUS_INVALID_PARAMETER; pthread_mutex_lock(&aperture->fmm_mutex); obj = vm_find_object_by_address(aperture, MemoryAddress, 0); pthread_mutex_unlock(&aperture->fmm_mutex); if (!obj) return HSAKMT_STATUS_INVALID_PARAMETER; r = validate_nodeid(obj->node_id, &gpu_id); if (r != HSAKMT_STATUS_SUCCESS) return r; if (!gpu_id && is_dgpu) { /* Sharing non paged system memory. Use first GPU which was * used during allocation. See fmm_allocate_host_gpu() */ if (!g_first_gpu_mem) return HSAKMT_STATUS_ERROR; gpu_id = g_first_gpu_mem->gpu_id; } exportArgs.handle = obj->handle; exportArgs.gpu_id = gpu_id; exportArgs.flags = obj->mflags.Value; r = kmtIoctl(kfd_fd, AMDKFD_IOC_IPC_EXPORT_HANDLE, (void *)&exportArgs); if (r) return HSAKMT_STATUS_ERROR; memcpy(SharedMemoryStruct->ShareHandle, exportArgs.share_handle, sizeof(SharedMemoryStruct->ShareHandle)); SharedMemoryStruct->ApeInfo = ApeInfo; SharedMemoryStruct->SizeInPages = (HSAuint32) (SizeInBytes >> PAGE_SHIFT); SharedMemoryStruct->ExportGpuId = gpu_id; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS fmm_register_shared_memory(const HsaSharedMemoryHandle *SharedMemoryHandle, HSAuint64 *SizeInBytes, void **MemoryAddress, uint32_t *gpu_id_array, uint32_t gpu_id_array_size) { int r = 0; HSAKMT_STATUS err = HSAKMT_STATUS_ERROR; vm_object_t *obj = NULL; void *reservedMem = NULL; manageable_aperture_t *aperture; struct kfd_ioctl_ipc_import_handle_args importArgs = {0}; struct kfd_ioctl_free_memory_of_gpu_args freeArgs = {0}; const HsaSharedMemoryStruct *SharedMemoryStruct = to_const_hsa_shared_memory_struct(SharedMemoryHandle); HSAuint64 SizeInPages = SharedMemoryStruct->SizeInPages; HsaMemFlags mflags; if (gpu_id_array_size > 0 && !gpu_id_array) return HSAKMT_STATUS_INVALID_PARAMETER; memcpy(importArgs.share_handle, SharedMemoryStruct->ShareHandle, sizeof(importArgs.share_handle)); importArgs.gpu_id = SharedMemoryStruct->ExportGpuId; aperture = fmm_get_aperture(SharedMemoryStruct->ApeInfo); if (!aperture) return HSAKMT_STATUS_INVALID_PARAMETER; pthread_mutex_lock(&aperture->fmm_mutex); reservedMem = aperture_allocate_area(aperture, NULL, (SizeInPages << PAGE_SHIFT)); pthread_mutex_unlock(&aperture->fmm_mutex); if (!reservedMem) { err = HSAKMT_STATUS_NO_MEMORY; goto err_free_buffer; } importArgs.va_addr = (uint64_t)reservedMem; r = kmtIoctl(kfd_fd, AMDKFD_IOC_IPC_IMPORT_HANDLE, (void *)&importArgs); if (r) { err = HSAKMT_STATUS_ERROR; goto err_import; } pthread_mutex_lock(&aperture->fmm_mutex); mflags.Value = importArgs.flags; obj = aperture_allocate_object(aperture, reservedMem, importArgs.handle, (SizeInPages << PAGE_SHIFT), mflags); if (!obj) { err = HSAKMT_STATUS_NO_MEMORY; goto err_free_mem; } pthread_mutex_unlock(&aperture->fmm_mutex); if (importArgs.mmap_offset) { int32_t gpu_mem_id = gpu_mem_find_by_gpu_id(importArgs.gpu_id); void *ret; if (gpu_mem_id < 0) { err = HSAKMT_STATUS_ERROR; goto err_free_obj; } obj->node_id = gpu_mem[gpu_mem_id].node_id; ret = fmm_map_to_cpu(reservedMem, (SizeInPages << PAGE_SHIFT), true, gpu_mem[gpu_mem_id].drm_render_fd, importArgs.mmap_offset); if (ret == MAP_FAILED) { err = HSAKMT_STATUS_ERROR; goto err_free_obj; } } *MemoryAddress = reservedMem; *SizeInBytes = (SizeInPages << PAGE_SHIFT); if (gpu_id_array_size > 0) { obj->registered_device_id_array = gpu_id_array; obj->registered_device_id_array_size = gpu_id_array_size; } obj->is_imported_kfd_bo = true; return HSAKMT_STATUS_SUCCESS; err_free_obj: pthread_mutex_lock(&aperture->fmm_mutex); vm_remove_object(aperture, obj); err_free_mem: aperture_release_area(aperture, reservedMem, (SizeInPages << PAGE_SHIFT)); pthread_mutex_unlock(&aperture->fmm_mutex); err_free_buffer: freeArgs.handle = importArgs.handle; kmtIoctl(kfd_fd, AMDKFD_IOC_FREE_MEMORY_OF_GPU, &freeArgs); err_import: return err; } HSAKMT_STATUS fmm_deregister_memory(void *address) { manageable_aperture_t *aperture; vm_object_t *object; object = vm_find_object(address, 0, &aperture); if (!object) /* On APUs we assume it's a random system memory address * where registration and dergistration is a no-op */ return (!is_dgpu || svm.is_svm_api_supported) ? HSAKMT_STATUS_SUCCESS : HSAKMT_STATUS_MEMORY_NOT_REGISTERED; /* Successful vm_find_object returns with aperture locked */ if (aperture == &cpuvm_aperture) { /* API-allocated system memory on APUs, deregistration * is a no-op */ pthread_mutex_unlock(&aperture->fmm_mutex); return HSAKMT_STATUS_SUCCESS; } if (object->metadata || object->userptr || object->is_imported_kfd_bo) { /* An object with metadata is an imported graphics * buffer. Deregistering imported graphics buffers or * userptrs means releasing the BO. */ pthread_mutex_unlock(&aperture->fmm_mutex); __fmm_release(object, aperture); return HSAKMT_STATUS_SUCCESS; } if (!object->registered_device_id_array || object->registered_device_id_array_size <= 0) { pthread_mutex_unlock(&aperture->fmm_mutex); return HSAKMT_STATUS_MEMORY_NOT_REGISTERED; } if (object->registered_device_id_array) { free(object->registered_device_id_array); object->registered_device_id_array = NULL; object->registered_device_id_array_size = 0; } if (object->registered_node_id_array) free(object->registered_node_id_array); object->registered_node_id_array = NULL; object->registration_count = 0; pthread_mutex_unlock(&aperture->fmm_mutex); return HSAKMT_STATUS_SUCCESS; } /* * This function unmaps all nodes on current mapped nodes list that are not included on nodes_to_map * and maps nodes_to_map */ HSAKMT_STATUS fmm_map_to_gpu_nodes(void *address, uint64_t size, uint32_t *nodes_to_map, uint64_t num_of_nodes, uint64_t *gpuvm_address) { manageable_aperture_t *aperture = NULL; vm_object_t *object; uint32_t i; uint32_t *registered_node_id_array, registered_node_id_array_size; HSAKMT_STATUS ret = HSAKMT_STATUS_ERROR; int retcode = 0; if (!num_of_nodes || !nodes_to_map || !address) return HSAKMT_STATUS_INVALID_PARAMETER; object = vm_find_object(address, size, &aperture); if (!object && !svm.is_svm_api_supported) return HSAKMT_STATUS_ERROR; /* Successful vm_find_object returns with aperture locked */ /* allocates VA only */ if (object && object->handle == 0) { pthread_mutex_unlock(&aperture->fmm_mutex); return HSAKMT_STATUS_INVALID_PARAMETER; } /* allocates buffer only, should be mapped by GEM API */ if (aperture == &mem_handle_aperture) { pthread_mutex_unlock(&aperture->fmm_mutex); return HSAKMT_STATUS_INVALID_PARAMETER; } /* APU memory is not supported by this function */ if (aperture && (aperture == &cpuvm_aperture || !aperture->is_cpu_accessible)) { pthread_mutex_unlock(&aperture->fmm_mutex); return HSAKMT_STATUS_ERROR; } if ((svm.is_svm_api_supported && !object) || object->userptr) { retcode = _fmm_map_to_gpu_userptr(address, size, gpuvm_address, object, nodes_to_map, num_of_nodes * sizeof(uint32_t)); if (object) pthread_mutex_unlock(&aperture->fmm_mutex); return retcode ? HSAKMT_STATUS_ERROR : HSAKMT_STATUS_SUCCESS; } /* Verify that all nodes to map are registered already */ registered_node_id_array = all_gpu_id_array; registered_node_id_array_size = all_gpu_id_array_size; if (object->registered_device_id_array_size > 0 && object->registered_device_id_array) { registered_node_id_array = object->registered_device_id_array; registered_node_id_array_size = object->registered_device_id_array_size; } for (i = 0 ; i < num_of_nodes; i++) { if (!id_in_array(nodes_to_map[i], registered_node_id_array, registered_node_id_array_size)) { pthread_mutex_unlock(&aperture->fmm_mutex); return HSAKMT_STATUS_ERROR; } } /* Unmap buffer from all nodes that have this buffer mapped that are not included on nodes_to_map array */ if (object->mapped_device_id_array_size > 0) { uint32_t temp_node_id_array[object->mapped_device_id_array_size]; uint32_t temp_node_id_array_size = 0; for (i = 0 ; i < object->mapped_device_id_array_size / sizeof(uint32_t); i++) { if (!id_in_array(object->mapped_device_id_array[i], nodes_to_map, num_of_nodes*sizeof(uint32_t))) temp_node_id_array[temp_node_id_array_size++] = object->mapped_device_id_array[i]; } temp_node_id_array_size *= sizeof(uint32_t); if (temp_node_id_array_size) { ret = _fmm_unmap_from_gpu(aperture, address, temp_node_id_array, temp_node_id_array_size, object); if (ret != HSAKMT_STATUS_SUCCESS) { pthread_mutex_unlock(&aperture->fmm_mutex); return ret; } } } /* Remove already mapped nodes from nodes_to_map * to generate the final map list */ uint32_t map_node_id_array[num_of_nodes]; uint32_t map_node_id_array_size = 0; for (i = 0; i < num_of_nodes; i++) { if (!id_in_array(nodes_to_map[i], object->mapped_device_id_array, object->mapped_device_id_array_size)) map_node_id_array[map_node_id_array_size++] = nodes_to_map[i]; } if (map_node_id_array_size) retcode = _fmm_map_to_gpu(aperture, address, size, object, map_node_id_array, map_node_id_array_size * sizeof(uint32_t)); pthread_mutex_unlock(&aperture->fmm_mutex); if (retcode != 0) return HSAKMT_STATUS_ERROR; return 0; } HSAKMT_STATUS fmm_get_mem_info(const void *address, HsaPointerInfo *info) { HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; uint32_t i; manageable_aperture_t *aperture; vm_object_t *vm_obj; memset(info, 0, sizeof(HsaPointerInfo)); vm_obj = vm_find_object(address, UINT64_MAX, &aperture); if (!vm_obj) { info->Type = HSA_POINTER_UNKNOWN; return HSAKMT_STATUS_ERROR; } /* Successful vm_find_object returns with the aperture locked */ if (vm_obj->is_imported_kfd_bo) info->Type = HSA_POINTER_REGISTERED_SHARED; else if (vm_obj->metadata) info->Type = HSA_POINTER_REGISTERED_GRAPHICS; else if (vm_obj->userptr) info->Type = HSA_POINTER_REGISTERED_USER; else if (vm_obj->handle == 0) info->Type = HSA_POINTER_RESERVED_ADDR; else info->Type = HSA_POINTER_ALLOCATED; info->Node = vm_obj->node_id; info->GPUAddress = (HSAuint64)vm_obj->start; info->SizeInBytes = vm_obj->size; /* registered nodes */ info->NRegisteredNodes = vm_obj->registered_device_id_array_size / sizeof(uint32_t); if (info->NRegisteredNodes && !vm_obj->registered_node_id_array) { vm_obj->registered_node_id_array = (uint32_t *) (uint32_t *)malloc(vm_obj->registered_device_id_array_size); /* vm_obj->registered_node_id_array allocated here will be * freed whenever the registration is changed (deregistration or * register to new nodes) or the memory being freed */ for (i = 0; i < info->NRegisteredNodes; i++) gpuid_to_nodeid(vm_obj->registered_device_id_array[i], &vm_obj->registered_node_id_array[i]); } info->RegisteredNodes = vm_obj->registered_node_id_array; /* mapped nodes */ info->NMappedNodes = vm_obj->mapped_device_id_array_size / sizeof(uint32_t); if (info->NMappedNodes && !vm_obj->mapped_node_id_array) { vm_obj->mapped_node_id_array = (uint32_t *)malloc(vm_obj->mapped_device_id_array_size); /* vm_obj->mapped_node_id_array allocated here will be * freed whenever the mapping is changed (unmapped or map * to new nodes) or memory being freed */ for (i = 0; i < info->NMappedNodes; i++) gpuid_to_nodeid(vm_obj->mapped_device_id_array[i], &vm_obj->mapped_node_id_array[i]); } info->MappedNodes = vm_obj->mapped_node_id_array; info->UserData = vm_obj->user_data; info->MemFlags = vm_obj->mflags; if (info->Type == HSA_POINTER_REGISTERED_USER) { info->CPUAddress = vm_obj->userptr; info->SizeInBytes = vm_obj->userptr_size; info->GPUAddress += ((HSAuint64)info->CPUAddress & (PAGE_SIZE - 1)); } else if (info->Type == HSA_POINTER_ALLOCATED) { info->CPUAddress = vm_obj->start; } pthread_mutex_unlock(&aperture->fmm_mutex); return ret; } #ifdef SANITIZER_AMDGPU HSAKMT_STATUS fmm_replace_asan_header_page(void* address) { HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; manageable_aperture_t* aperture; vm_object_t* vm_obj; vm_obj = vm_find_object(address, UINT64_MAX, &aperture); if (!vm_obj) return HSAKMT_STATUS_ERROR; /* Successful vm_find_object returns with the aperture locked */ /* If this is a GPU-mapped memory, remap the first page to be normal system memory*/ if (vm_obj->mmap_fd) { void* p = mmap(address, PAGE_SIZE, PROT_WRITE | PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0); if (p == MAP_FAILED) ret = HSAKMT_STATUS_ERROR; } pthread_mutex_unlock(&aperture->fmm_mutex); return ret; } HSAKMT_STATUS fmm_return_asan_header_page(void* address) { HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; manageable_aperture_t* aperture; vm_object_t* vm_obj; vm_obj = vm_find_object(address, UINT64_MAX, &aperture); if (!vm_obj) return HSAKMT_STATUS_ERROR; /* Successful vm_find_object returns with the aperture locked */ /* If this is a GPU-mapped memory, remap the first page back to the original GPU memory*/ if (vm_obj->mmap_fd) { off_t mmap_offset = vm_obj->mmap_offset + ((char*)address - (char*)vm_obj->start); void* p = mmap(address, PAGE_SIZE, vm_obj->mmap_flags, MAP_SHARED | MAP_FIXED, vm_obj->mmap_fd, mmap_offset); if (p == MAP_FAILED) ret = HSAKMT_STATUS_ERROR; } pthread_mutex_unlock(&aperture->fmm_mutex); return ret; } #endif HSAKMT_STATUS fmm_set_mem_user_data(const void *mem, void *usr_data) { manageable_aperture_t *aperture; vm_object_t *vm_obj; vm_obj = vm_find_object(mem, 0, &aperture); if (!vm_obj) return HSAKMT_STATUS_ERROR; vm_obj->user_data = usr_data; pthread_mutex_unlock(&aperture->fmm_mutex); return HSAKMT_STATUS_SUCCESS; } static void fmm_clear_aperture(manageable_aperture_t *app) { rbtree_node_t *n; pthread_mutex_init(&app->fmm_mutex, NULL); while ((n = rbtree_node_any(&app->tree, MID))) vm_remove_object(app, vm_object_entry(n, 0)); while (app->vm_ranges) vm_remove_area(app, app->vm_ranges); } /* This is a special funcion that should be called only from the child process * after a fork(). This will clear all vm_objects and mmaps duplicated from * the parent. */ void fmm_clear_all_mem(void) { uint32_t i; void *map_addr; /* Close render node FDs. The child process needs to open new ones */ for (i = 0; i <= DRM_LAST_RENDER_NODE - DRM_FIRST_RENDER_NODE; i++) { if (amdgpu_handle[i]) { amdgpu_device_deinitialize(amdgpu_handle[i]); amdgpu_handle[i] = NULL; } else if (drm_render_fds[i]) { close(drm_render_fds[i]); } drm_render_fds[i] = 0; } fmm_clear_aperture(&mem_handle_aperture); fmm_clear_aperture(&cpuvm_aperture); fmm_clear_aperture(&svm.apertures[SVM_DEFAULT]); fmm_clear_aperture(&svm.apertures[SVM_COHERENT]); if (dgpu_shared_aperture_limit) { /* Use the same dgpu range as the parent. If failed, then set * is_dgpu_mem_init to false. Later on dgpu_mem_init will try * to get a new range */ map_addr = mmap(dgpu_shared_aperture_base, (HSAuint64)(dgpu_shared_aperture_limit)- (HSAuint64)(dgpu_shared_aperture_base) + 1, PROT_NONE, MAP_ANONYMOUS | MAP_NORESERVE | MAP_PRIVATE | MAP_FIXED, -1, 0); if (map_addr == MAP_FAILED) { munmap(dgpu_shared_aperture_base, (HSAuint64)(dgpu_shared_aperture_limit) - (HSAuint64)(dgpu_shared_aperture_base) + 1); dgpu_shared_aperture_base = NULL; dgpu_shared_aperture_limit = NULL; } } if (all_gpu_id_array) free(all_gpu_id_array); all_gpu_id_array_size = 0; all_gpu_id_array = NULL; /* Nothing is initialized. */ if (!gpu_mem) return; for (i = 0; i < gpu_mem_count; i++) { fmm_clear_aperture(&gpu_mem[i].gpuvm_aperture); fmm_clear_aperture(&gpu_mem[i].scratch_physical); } fmm_destroy_process_apertures(); } ROCT-Thunk-Interface-rocm-5.7.0/src/fmm.h000066400000000000000000000103761446477712600177650ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef FMM_H_ #define FMM_H_ #include "hsakmttypes.h" #include typedef enum { FMM_FIRST_APERTURE_TYPE = 0, FMM_GPUVM = FMM_FIRST_APERTURE_TYPE, FMM_LDS, FMM_SCRATCH, FMM_SVM, FMM_MMIO, FMM_LAST_APERTURE_TYPE } aperture_type_e; typedef struct { aperture_type_e app_type; uint64_t size; void *start_address; } aperture_properties_t; HSAKMT_STATUS fmm_get_amdgpu_device_handle(uint32_t node_id, HsaAMDGPUDeviceHandle *DeviceHandle); HSAKMT_STATUS fmm_init_process_apertures(unsigned int NumNodes); void fmm_destroy_process_apertures(void); /* Memory interface */ void *fmm_allocate_scratch(uint32_t gpu_id, void *address, uint64_t MemorySizeInBytes); void *fmm_allocate_device(uint32_t gpu_id, uint32_t node_id, void *address, uint64_t MemorySizeInBytes, HsaMemFlags flags); void *fmm_allocate_doorbell(uint32_t gpu_id, uint64_t MemorySizeInBytes, uint64_t doorbell_offset); void *fmm_allocate_host(uint32_t node_id, void *address, uint64_t MemorySizeInBytes, HsaMemFlags flags); void fmm_print(uint32_t node); HSAKMT_STATUS fmm_release(void *address); HSAKMT_STATUS fmm_map_to_gpu(void *address, uint64_t size, uint64_t *gpuvm_address); int fmm_unmap_from_gpu(void *address); bool fmm_get_handle(void *address, uint64_t *handle); HSAKMT_STATUS fmm_get_mem_info(const void *address, HsaPointerInfo *info); HSAKMT_STATUS fmm_set_mem_user_data(const void *mem, void *usr_data); #ifdef SANITIZER_AMDGPU HSAKMT_STATUS fmm_replace_asan_header_page(void* address); HSAKMT_STATUS fmm_return_asan_header_page(void* address); #endif /* Topology interface*/ HSAKMT_STATUS fmm_node_added(HSAuint32 gpu_id); HSAKMT_STATUS fmm_node_removed(HSAuint32 gpu_id); HSAKMT_STATUS fmm_get_aperture_base_and_limit(aperture_type_e aperture_type, HSAuint32 gpu_id, HSAuint64 *aperture_base, HSAuint64 *aperture_limit); HSAKMT_STATUS fmm_register_memory(void *address, uint64_t size_in_bytes, uint32_t *gpu_id_array, uint32_t gpu_id_array_size, bool coarse_grain); HSAKMT_STATUS fmm_register_graphics_handle(HSAuint64 GraphicsResourceHandle, HsaGraphicsResourceInfo *GraphicsResourceInfo, uint32_t *gpu_id_array, uint32_t gpu_id_array_size); HSAKMT_STATUS fmm_deregister_memory(void *address); HSAKMT_STATUS fmm_export_dma_buf_fd(void *MemoryAddress, HSAuint64 MemorySizeInBytes, int *DMABufFd, HSAuint64 *Offset); HSAKMT_STATUS fmm_share_memory(void *MemoryAddress, HSAuint64 SizeInBytes, HsaSharedMemoryHandle *SharedMemoryHandle); HSAKMT_STATUS fmm_register_shared_memory(const HsaSharedMemoryHandle *SharedMemoryHandle, HSAuint64 *SizeInBytes, void **MemoryAddress, uint32_t *gpu_id_array, uint32_t gpu_id_array_size); HSAKMT_STATUS fmm_map_to_gpu_nodes(void *address, uint64_t size, uint32_t *nodes_to_map, uint64_t num_of_nodes, uint64_t *gpuvm_address); int open_drm_render_device(int minor); void *mmap_allocate_aligned(int prot, int flags, uint64_t size, uint64_t align, uint64_t guard_size, void *aper_base, void *aper_limit); extern int (*fn_amdgpu_device_get_fd)(HsaAMDGPUDeviceHandle device_handle); #endif /* FMM_H_ */ ROCT-Thunk-Interface-rocm-5.7.0/src/globals.c000066400000000000000000000026021446477712600206150ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "libhsakmt.h" // HSAKMT global data int kfd_fd = -1; unsigned long kfd_open_count; unsigned long system_properties_count; pthread_mutex_t hsakmt_mutex = PTHREAD_MUTEX_INITIALIZER; bool is_dgpu; int PAGE_SIZE; int PAGE_SHIFT; ROCT-Thunk-Interface-rocm-5.7.0/src/libhsakmt.c000066400000000000000000000010651446477712600211520ustar00rootroot00000000000000#include #include #include #include "libhsakmt.h" /* Call ioctl, restarting if it is interrupted */ int kmtIoctl(int fd, unsigned long request, void *arg) { int ret; do { ret = ioctl(fd, request, arg); } while (ret == -1 && (errno == EINTR || errno == EAGAIN)); if (ret == -1 && errno == EBADF) { /* In case pthread_atfork didn't catch it, this will * make any subsequent hsaKmt calls fail in CHECK_KFD_OPEN. */ pr_err("KFD file descriptor not valid in this process\n"); is_forked_child(); } return ret; } ROCT-Thunk-Interface-rocm-5.7.0/src/libhsakmt.h000066400000000000000000000213271446477712600211620ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef LIBHSAKMT_H_INCLUDED #define LIBHSAKMT_H_INCLUDED #include "linux/kfd_ioctl.h" #include "hsakmt.h" #include #include #include extern int kfd_fd; extern unsigned long kfd_open_count; extern bool hsakmt_forked; extern pthread_mutex_t hsakmt_mutex; extern bool is_dgpu; extern HsaVersionInfo kfd_version_info; #undef HSAKMTAPI #define HSAKMTAPI __attribute__((visibility ("default"))) #if defined(__clang__) #if __has_feature(address_sanitizer) #define SANITIZER_AMDGPU 1 #endif #endif /*Avoid pointer-to-int-cast warning*/ #define PORT_VPTR_TO_UINT64(vptr) ((uint64_t)(unsigned long)(vptr)) /*Avoid int-to-pointer-cast warning*/ #define PORT_UINT64_TO_VPTR(v) ((void*)(unsigned long)(v)) #define CHECK_KFD_OPEN() \ do { if (kfd_open_count == 0 || hsakmt_forked) return HSAKMT_STATUS_KERNEL_IO_CHANNEL_NOT_OPENED; } while (0) #define CHECK_KFD_MINOR_VERSION(minor) \ do { if ((minor) > kfd_version_info.KernelInterfaceMinorVersion)\ return HSAKMT_STATUS_NOT_SUPPORTED; } while (0) extern int PAGE_SIZE; extern int PAGE_SHIFT; /* VI HW bug requires this virtual address alignment */ #define TONGA_PAGE_SIZE 0x8000 /* 64KB BigK fragment size for TLB efficiency */ #define GPU_BIGK_PAGE_SIZE (1 << 16) /* 2MB huge page size for 4-level page tables on Vega10 and later GPUs */ #define GPU_HUGE_PAGE_SIZE (2 << 20) #define CHECK_PAGE_MULTIPLE(x) \ do { if ((uint64_t)PORT_VPTR_TO_UINT64(x) % PAGE_SIZE) return HSAKMT_STATUS_INVALID_PARAMETER; } while(0) #define ALIGN_UP(x,align) (((uint64_t)(x) + (align) - 1) & ~(uint64_t)((align)-1)) #define ALIGN_UP_32(x,align) (((uint32_t)(x) + (align) - 1) & ~(uint32_t)((align)-1)) #define PAGE_ALIGN_UP(x) ALIGN_UP(x,PAGE_SIZE) #define BITMASK(n) ((n) ? (UINT64_MAX >> (sizeof(UINT64_MAX) * CHAR_BIT - (n))) : 0) #define ARRAY_LEN(array) (sizeof(array) / sizeof(array[0])) /* HSA Thunk logging usage */ extern int hsakmt_debug_level; #define hsakmt_print(level, fmt, ...) \ do { if (level <= hsakmt_debug_level) fprintf(stderr, fmt, ##__VA_ARGS__); } while (0) #define HSAKMT_DEBUG_LEVEL_DEFAULT -1 #define HSAKMT_DEBUG_LEVEL_ERR 3 #define HSAKMT_DEBUG_LEVEL_WARNING 4 #define HSAKMT_DEBUG_LEVEL_INFO 6 #define HSAKMT_DEBUG_LEVEL_DEBUG 7 #define pr_err(fmt, ...) \ hsakmt_print(HSAKMT_DEBUG_LEVEL_ERR, fmt, ##__VA_ARGS__) #define pr_warn(fmt, ...) \ hsakmt_print(HSAKMT_DEBUG_LEVEL_WARNING, fmt, ##__VA_ARGS__) #define pr_info(fmt, ...) \ hsakmt_print(HSAKMT_DEBUG_LEVEL_INFO, fmt, ##__VA_ARGS__) #define pr_debug(fmt, ...) \ hsakmt_print(HSAKMT_DEBUG_LEVEL_DEBUG, fmt, ##__VA_ARGS__) #define pr_err_once(fmt, ...) \ ({ \ static bool __print_once; \ if (!__print_once) { \ __print_once = true; \ pr_err(fmt, ##__VA_ARGS__); \ } \ }) #define pr_warn_once(fmt, ...) \ ({ \ static bool __print_once; \ if (!__print_once) { \ __print_once = true; \ pr_warn(fmt, ##__VA_ARGS__); \ } \ }) /* Expects gfxv (full) in decimal */ #define HSA_GET_GFX_VERSION_MAJOR(gfxv) (((gfxv) / 10000) % 100) #define HSA_GET_GFX_VERSION_MINOR(gfxv) (((gfxv) / 100) % 100) #define HSA_GET_GFX_VERSION_STEP(gfxv) ((gfxv) % 100) /* Expects HSA_ENGINE_ID.ui32, returns gfxv (full) in hex */ #define HSA_GET_GFX_VERSION_FULL(ui32) \ (((ui32.Major) << 16) | ((ui32.Minor) << 8) | (ui32.Stepping)) enum full_gfx_versions { GFX_VERSION_KAVERI = 0x070000, GFX_VERSION_HAWAII = 0x070001, GFX_VERSION_CARRIZO = 0x080001, GFX_VERSION_TONGA = 0x080002, GFX_VERSION_FIJI = 0x080003, GFX_VERSION_POLARIS10 = 0x080003, GFX_VERSION_POLARIS11 = 0x080003, GFX_VERSION_POLARIS12 = 0x080003, GFX_VERSION_VEGAM = 0x080003, GFX_VERSION_VEGA10 = 0x090000, GFX_VERSION_RAVEN = 0x090002, GFX_VERSION_VEGA12 = 0x090004, GFX_VERSION_VEGA20 = 0x090006, GFX_VERSION_ARCTURUS = 0x090008, GFX_VERSION_ALDEBARAN = 0x09000A, GFX_VERSION_AQUA_VANJARAM = 0x090400, GFX_VERSION_RENOIR = 0x09000C, GFX_VERSION_NAVI10 = 0x0A0100, GFX_VERSION_NAVI12 = 0x0A0101, GFX_VERSION_NAVI14 = 0x0A0102, GFX_VERSION_CYAN_SKILLFISH = 0x0A0103, GFX_VERSION_SIENNA_CICHLID = 0x0A0300, GFX_VERSION_NAVY_FLOUNDER = 0x0A0301, GFX_VERSION_DIMGREY_CAVEFISH = 0x0A0302, GFX_VERSION_VANGOGH = 0x0A0303, GFX_VERSION_BEIGE_GOBY = 0x0A0304, GFX_VERSION_YELLOW_CARP = 0x0A0305, GFX_VERSION_PLUM_BONITO = 0x0B0000, GFX_VERSION_WHEAT_NAS = 0x0B0001, }; struct hsa_gfxip_table { uint16_t device_id; // Device ID unsigned char major; // GFXIP Major engine version unsigned char minor; // GFXIP Minor engine version unsigned char stepping; // GFXIP Stepping info const char *amd_name; // CALName of the device }; HSAKMT_STATUS init_kfd_version(void); #define IS_SOC15(gfxv) ((gfxv) >= GFX_VERSION_VEGA10) HSAKMT_STATUS validate_nodeid(uint32_t nodeid, uint32_t *gpu_id); HSAKMT_STATUS gpuid_to_nodeid(uint32_t gpu_id, uint32_t* node_id); uint32_t get_gfxv_by_node_id(HSAuint32 node_id); bool prefer_ats(HSAuint32 node_id); uint16_t get_device_id_by_node_id(HSAuint32 node_id); uint16_t get_device_id_by_gpu_id(HSAuint32 gpu_id); uint32_t get_direct_link_cpu(uint32_t gpu_node); int get_drm_render_fd_by_gpu_id(HSAuint32 gpu_id); HSAKMT_STATUS validate_nodeid_array(uint32_t **gpu_id_array, uint32_t NumberOfNodes, uint32_t *NodeArray); HSAKMT_STATUS topology_sysfs_get_system_props(HsaSystemProperties *props); HSAKMT_STATUS topology_get_node_props(HSAuint32 NodeId, HsaNodeProperties *NodeProperties); HSAKMT_STATUS topology_get_iolink_props(HSAuint32 NodeId, HSAuint32 NumIoLinks, HsaIoLinkProperties *IoLinkProperties); void topology_setup_is_dgpu_param(HsaNodeProperties *props); bool topology_is_svm_needed(HSA_ENGINE_ID EngineId); HSAuint32 PageSizeFromFlags(unsigned int pageSizeFlags); void* allocate_exec_aligned_memory_gpu(uint32_t size, uint32_t align, uint32_t NodeId, bool NonPaged, bool DeviceLocal, bool Uncached); void free_exec_aligned_memory_gpu(void *addr, uint32_t size, uint32_t align); HSAKMT_STATUS init_process_doorbells(unsigned int NumNodes); void destroy_process_doorbells(void); HSAKMT_STATUS init_device_debugging_memory(unsigned int NumNodes); void destroy_device_debugging_memory(void); bool debug_get_reg_status(uint32_t node_id); HSAKMT_STATUS init_counter_props(unsigned int NumNodes); void destroy_counter_props(void); uint32_t *convert_queue_ids(HSAuint32 NumQueues, HSA_QUEUEID *Queues); extern int kmtIoctl(int fd, unsigned long request, void *arg); /* Void pointer arithmetic (or remove -Wpointer-arith to allow void pointers arithmetic) */ #define VOID_PTR_ADD32(ptr,n) (void*)((uint32_t*)(ptr) + n)/*ptr + offset*/ #define VOID_PTR_ADD(ptr,n) (void*)((uint8_t*)(ptr) + n)/*ptr + offset*/ #define VOID_PTR_SUB(ptr,n) (void*)((uint8_t*)(ptr) - n)/*ptr - offset*/ #define VOID_PTRS_SUB(ptr1,ptr2) (uint64_t)((uint8_t*)(ptr1) - (uint8_t*)(ptr2)) /*ptr1 - ptr2*/ #define MIN(a, b) ({ \ typeof(a) tmp1 = (a), tmp2 = (b); \ tmp1 < tmp2 ? tmp1 : tmp2; }) #define MAX(a, b) ({ \ typeof(a) tmp1 = (a), tmp2 = (b); \ tmp1 > tmp2 ? tmp1 : tmp2; }) void clear_events_page(void); void fmm_clear_all_mem(void); void clear_process_doorbells(void); uint32_t get_num_sysfs_nodes(void); bool is_forked_child(void); /* Calculate VGPR and SGPR register file size per CU */ uint32_t get_vgpr_size_per_cu(uint32_t gfxv); #define SGPR_SIZE_PER_CU 0x4000 #endif ROCT-Thunk-Interface-rocm-5.7.0/src/libhsakmt.ver000066400000000000000000000033131446477712600215220ustar00rootroot00000000000000HSAKMT_1 { global: hsaKmtOpenKFD; hsaKmtCloseKFD; hsaKmtGetVersion; hsaKmtAcquireSystemProperties; hsaKmtReleaseSystemProperties; hsaKmtGetNodeProperties; hsaKmtGetNodeMemoryProperties; hsaKmtGetNodeCacheProperties; hsaKmtGetNodeIoLinkProperties; hsaKmtCreateEvent; hsaKmtDestroyEvent; hsaKmtSetEvent; hsaKmtResetEvent; hsaKmtQueryEventState; hsaKmtWaitOnEvent; hsaKmtWaitOnMultipleEvents; hsaKmtCreateQueue; hsaKmtUpdateQueue; hsaKmtDestroyQueue; hsaKmtSetQueueCUMask; hsaKmtSetMemoryPolicy; hsaKmtAllocMemory; hsaKmtFreeMemory; hsaKmtAvailableMemory; hsaKmtRegisterMemory; hsaKmtRegisterMemoryToNodes; hsaKmtRegisterMemoryWithFlags; hsaKmtRegisterGraphicsHandleToNodes; hsaKmtShareMemory; hsaKmtRegisterSharedHandle; hsaKmtRegisterSharedHandleToNodes; hsaKmtProcessVMRead; hsaKmtProcessVMWrite; hsaKmtDeregisterMemory; hsaKmtMapMemoryToGPU; hsaKmtMapMemoryToGPUNodes; hsaKmtUnmapMemoryToGPU; hsaKmtDbgRegister; hsaKmtDbgUnregister; hsaKmtDbgWavefrontControl; hsaKmtDbgAddressWatch; hsaKmtDbgEnable; hsaKmtDbgDisable; hsaKmtDbgGetDeviceData; hsaKmtDbgGetQueueData; hsaKmtGetClockCounters; hsaKmtPmcGetCounterProperties; hsaKmtPmcRegisterTrace; hsaKmtPmcUnregisterTrace; hsaKmtPmcAcquireTraceAccess; hsaKmtPmcReleaseTraceAccess; hsaKmtPmcStartTrace; hsaKmtPmcQueryTrace; hsaKmtPmcStopTrace; hsaKmtMapGraphicHandle; hsaKmtUnmapGraphicHandle; hsaKmtSetTrapHandler; hsaKmtGetTileConfig; hsaKmtQueryPointerInfo; hsaKmtSetMemoryUserData; hsaKmtGetQueueInfo; hsaKmtAllocQueueGWS; hsaKmtRuntimeEnable; hsaKmtRuntimeDisable; hsaKmtGetRuntimeCapabilities; hsaKmtSPMAcquire; hsaKmtSPMRelease; hsaKmtSPMSetDestBuffer; hsaKmtSVMSetAttr; hsaKmtSVMGetAttr; hsaKmtSetXNACKMode; hsaKmtGetXNACKMode; hsaKmtOpenSMI; hsaKmtExportDMABufHandle; local: *; }; ROCT-Thunk-Interface-rocm-5.7.0/src/memory.c000066400000000000000000000414601446477712600205070ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "libhsakmt.h" #include "linux/kfd_ioctl.h" #include #include #include #include #include #include #include #include "fmm.h" extern int zfb_support; HSAKMT_STATUS HSAKMTAPI hsaKmtSetMemoryPolicy(HSAuint32 Node, HSAuint32 DefaultPolicy, HSAuint32 AlternatePolicy, void *MemoryAddressAlternate, HSAuint64 MemorySizeInBytes) { struct kfd_ioctl_set_memory_policy_args args = {0}; HSAKMT_STATUS result; uint32_t gpu_id; CHECK_KFD_OPEN(); pr_debug("[%s] node %d; default %d; alternate %d\n", __func__, Node, DefaultPolicy, AlternatePolicy); result = validate_nodeid(Node, &gpu_id); if (result != HSAKMT_STATUS_SUCCESS) return result; if (get_gfxv_by_node_id(Node) != GFX_VERSION_KAVERI) /* This is a legacy API useful on Kaveri only. On dGPU * the alternate aperture is setup and used * automatically for coherent allocations. Don't let * app override it. */ return HSAKMT_STATUS_NOT_IMPLEMENTED; /* * We accept any legal policy and alternate address location. * You get CC everywhere anyway. */ if ((DefaultPolicy != HSA_CACHING_CACHED && DefaultPolicy != HSA_CACHING_NONCACHED) || (AlternatePolicy != HSA_CACHING_CACHED && AlternatePolicy != HSA_CACHING_NONCACHED)) return HSAKMT_STATUS_INVALID_PARAMETER; CHECK_PAGE_MULTIPLE(MemoryAddressAlternate); CHECK_PAGE_MULTIPLE(MemorySizeInBytes); args.gpu_id = gpu_id; args.default_policy = (DefaultPolicy == HSA_CACHING_CACHED) ? KFD_IOC_CACHE_POLICY_COHERENT : KFD_IOC_CACHE_POLICY_NONCOHERENT; args.alternate_policy = (AlternatePolicy == HSA_CACHING_CACHED) ? KFD_IOC_CACHE_POLICY_COHERENT : KFD_IOC_CACHE_POLICY_NONCOHERENT; args.alternate_aperture_base = (uintptr_t) MemoryAddressAlternate; args.alternate_aperture_size = MemorySizeInBytes; int err = kmtIoctl(kfd_fd, AMDKFD_IOC_SET_MEMORY_POLICY, &args); return (err == -1) ? HSAKMT_STATUS_ERROR : HSAKMT_STATUS_SUCCESS; } HSAuint32 PageSizeFromFlags(unsigned int pageSizeFlags) { switch (pageSizeFlags) { case HSA_PAGE_SIZE_4KB: return 4*1024; case HSA_PAGE_SIZE_64KB: return 64*1024; case HSA_PAGE_SIZE_2MB: return 2*1024*1024; case HSA_PAGE_SIZE_1GB: return 1024*1024*1024; default: assert(false); return 4*1024; } } HSAKMT_STATUS HSAKMTAPI hsaKmtAllocMemory(HSAuint32 PreferredNode, HSAuint64 SizeInBytes, HsaMemFlags MemFlags, void **MemoryAddress) { HSAKMT_STATUS result; uint32_t gpu_id; HSAuint64 page_size; CHECK_KFD_OPEN(); pr_debug("[%s] node %d\n", __func__, PreferredNode); result = validate_nodeid(PreferredNode, &gpu_id); if (result != HSAKMT_STATUS_SUCCESS) { pr_err("[%s] invalid node ID: %d\n", __func__, PreferredNode); return result; } page_size = PageSizeFromFlags(MemFlags.ui32.PageSize); if (!MemoryAddress || !SizeInBytes || (SizeInBytes & (page_size-1))) return HSAKMT_STATUS_INVALID_PARAMETER; if (MemFlags.ui32.FixedAddress) { if (*MemoryAddress == NULL) return HSAKMT_STATUS_INVALID_PARAMETER; } else *MemoryAddress = NULL; if (MemFlags.ui32.Scratch) { *MemoryAddress = fmm_allocate_scratch(gpu_id, *MemoryAddress, SizeInBytes); if (!(*MemoryAddress)) { pr_err("[%s] failed to allocate %lu bytes from scratch\n", __func__, SizeInBytes); return HSAKMT_STATUS_NO_MEMORY; } return HSAKMT_STATUS_SUCCESS; } /* GPU allocated system memory */ if (!gpu_id || !MemFlags.ui32.NonPaged || zfb_support) { /* Backwards compatibility hack: Allocate system memory if app * asks for paged memory from a GPU node. */ /* If allocate VRAM under ZFB mode */ if (zfb_support && gpu_id && MemFlags.ui32.NonPaged == 1) MemFlags.ui32.CoarseGrain = 1; *MemoryAddress = fmm_allocate_host(PreferredNode, *MemoryAddress, SizeInBytes, MemFlags); if (!(*MemoryAddress)) { pr_err("[%s] failed to allocate %lu bytes from host\n", __func__, SizeInBytes); return HSAKMT_STATUS_ERROR; } return HSAKMT_STATUS_SUCCESS; } /* GPU allocated VRAM */ /* sanity check cannot do OnlyAddress and NoAddress alloc at same time */ if (MemFlags.ui32.OnlyAddress && MemFlags.ui32.NoAddress) { pr_err("[%s] allocate addr-only and memory-only at same time\n", __func__); return HSAKMT_STATUS_INVALID_PARAMETER; } *MemoryAddress = fmm_allocate_device(gpu_id, PreferredNode, *MemoryAddress, SizeInBytes, MemFlags); if (!(*MemoryAddress)) { pr_err("[%s] failed to allocate %lu bytes from device\n", __func__, SizeInBytes); return HSAKMT_STATUS_NO_MEMORY; } return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtFreeMemory(void *MemoryAddress, HSAuint64 SizeInBytes) { CHECK_KFD_OPEN(); pr_debug("[%s] address %p\n", __func__, MemoryAddress); if (!MemoryAddress) { pr_err("FIXME: freeing NULL pointer\n"); return HSAKMT_STATUS_ERROR; } return fmm_release(MemoryAddress); } HSAKMT_STATUS HSAKMTAPI hsaKmtAvailableMemory(HSAuint32 Node, HSAuint64 *AvailableBytes) { struct kfd_ioctl_get_available_memory_args args = {}; HSAKMT_STATUS result; CHECK_KFD_OPEN(); CHECK_KFD_MINOR_VERSION(9); pr_debug("[%s] node %d\n", __func__, Node); result = validate_nodeid(Node, &args.gpu_id); if (result != HSAKMT_STATUS_SUCCESS) { pr_err("[%s] invalid node ID: %d\n", __func__, Node); return result; } if (kmtIoctl(kfd_fd, AMDKFD_IOC_AVAILABLE_MEMORY, &args)) return HSAKMT_STATUS_ERROR; *AvailableBytes = args.available; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterMemory(void *MemoryAddress, HSAuint64 MemorySizeInBytes) { CHECK_KFD_OPEN(); pr_debug("[%s] address %p\n", __func__, MemoryAddress); if (!is_dgpu) /* TODO: support mixed APU and dGPU configurations */ return HSAKMT_STATUS_SUCCESS; return fmm_register_memory(MemoryAddress, MemorySizeInBytes, NULL, 0, true); } HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterMemoryToNodes(void *MemoryAddress, HSAuint64 MemorySizeInBytes, HSAuint64 NumberOfNodes, HSAuint32 *NodeArray) { CHECK_KFD_OPEN(); uint32_t *gpu_id_array; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; pr_debug("[%s] address %p number of nodes %lu\n", __func__, MemoryAddress, NumberOfNodes); if (!is_dgpu) /* TODO: support mixed APU and dGPU configurations */ return HSAKMT_STATUS_NOT_SUPPORTED; ret = validate_nodeid_array(&gpu_id_array, NumberOfNodes, NodeArray); if (ret == HSAKMT_STATUS_SUCCESS) { ret = fmm_register_memory(MemoryAddress, MemorySizeInBytes, gpu_id_array, NumberOfNodes*sizeof(uint32_t), true); if (ret != HSAKMT_STATUS_SUCCESS) free(gpu_id_array); } return ret; } HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterMemoryWithFlags(void *MemoryAddress, HSAuint64 MemorySizeInBytes, HsaMemFlags MemFlags) { CHECK_KFD_OPEN(); HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; pr_debug("[%s] address %p\n", __func__, MemoryAddress); // Registered memory should be ordinary paged host memory. if ((MemFlags.ui32.HostAccess != 1) || (MemFlags.ui32.NonPaged == 1)) return HSAKMT_STATUS_NOT_SUPPORTED; if (!is_dgpu) /* TODO: support mixed APU and dGPU configurations */ return HSAKMT_STATUS_NOT_SUPPORTED; ret = fmm_register_memory(MemoryAddress, MemorySizeInBytes, NULL, 0, MemFlags.ui32.CoarseGrain); return ret; } HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterGraphicsHandleToNodes(HSAuint64 GraphicsResourceHandle, HsaGraphicsResourceInfo *GraphicsResourceInfo, HSAuint64 NumberOfNodes, HSAuint32 *NodeArray) { CHECK_KFD_OPEN(); uint32_t *gpu_id_array = NULL; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; pr_debug("[%s] number of nodes %lu\n", __func__, NumberOfNodes); if (NodeArray != NULL || NumberOfNodes != 0) { ret = validate_nodeid_array(&gpu_id_array, NumberOfNodes, NodeArray); } if (ret == HSAKMT_STATUS_SUCCESS) { ret = fmm_register_graphics_handle( GraphicsResourceHandle, GraphicsResourceInfo, gpu_id_array, NumberOfNodes * sizeof(uint32_t)); if (ret != HSAKMT_STATUS_SUCCESS) free(gpu_id_array); } return ret; } HSAKMT_STATUS HSAKMTAPI hsaKmtExportDMABufHandle(void *MemoryAddress, HSAuint64 MemorySizeInBytes, int *DMABufFd, HSAuint64 *Offset) { CHECK_KFD_OPEN(); CHECK_KFD_MINOR_VERSION(12); pr_debug("[%s] address %p\n", __func__, MemoryAddress); return fmm_export_dma_buf_fd(MemoryAddress, MemorySizeInBytes, DMABufFd, Offset); } HSAKMT_STATUS HSAKMTAPI hsaKmtShareMemory(void *MemoryAddress, HSAuint64 SizeInBytes, HsaSharedMemoryHandle *SharedMemoryHandle) { CHECK_KFD_OPEN(); pr_debug("[%s] address %p\n", __func__, MemoryAddress); if (!SharedMemoryHandle) return HSAKMT_STATUS_INVALID_PARAMETER; return fmm_share_memory(MemoryAddress, SizeInBytes, SharedMemoryHandle); } HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterSharedHandle(const HsaSharedMemoryHandle *SharedMemoryHandle, void **MemoryAddress, HSAuint64 *SizeInBytes) { CHECK_KFD_OPEN(); pr_debug("[%s] handle %p\n", __func__, SharedMemoryHandle); return hsaKmtRegisterSharedHandleToNodes(SharedMemoryHandle, MemoryAddress, SizeInBytes, 0, NULL); } HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterSharedHandleToNodes(const HsaSharedMemoryHandle *SharedMemoryHandle, void **MemoryAddress, HSAuint64 *SizeInBytes, HSAuint64 NumberOfNodes, HSAuint32 *NodeArray) { CHECK_KFD_OPEN(); uint32_t *gpu_id_array = NULL; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; pr_debug("[%s] handle %p number of nodes %lu\n", __func__, SharedMemoryHandle, NumberOfNodes); if (!SharedMemoryHandle) return HSAKMT_STATUS_INVALID_PARAMETER; if (NodeArray) { ret = validate_nodeid_array(&gpu_id_array, NumberOfNodes, NodeArray); if (ret != HSAKMT_STATUS_SUCCESS) goto error; } ret = fmm_register_shared_memory(SharedMemoryHandle, SizeInBytes, MemoryAddress, gpu_id_array, NumberOfNodes*sizeof(uint32_t)); if (ret != HSAKMT_STATUS_SUCCESS) goto error; return ret; error: if (gpu_id_array) free(gpu_id_array); return ret; } HSAKMT_STATUS HSAKMTAPI hsaKmtProcessVMRead(HSAuint32 Pid, HsaMemoryRange *LocalMemoryArray, HSAuint64 LocalMemoryArrayCount, HsaMemoryRange *RemoteMemoryArray, HSAuint64 RemoteMemoryArrayCount, HSAuint64 *SizeCopied) { pr_err("[%s] Deprecated\n", __func__); return HSAKMT_STATUS_NOT_IMPLEMENTED; } HSAKMT_STATUS HSAKMTAPI hsaKmtProcessVMWrite(HSAuint32 Pid, HsaMemoryRange *LocalMemoryArray, HSAuint64 LocalMemoryArrayCount, HsaMemoryRange *RemoteMemoryArray, HSAuint64 RemoteMemoryArrayCount, HSAuint64 *SizeCopied) { pr_err("[%s] Deprecated\n", __func__); return HSAKMT_STATUS_NOT_IMPLEMENTED; } HSAKMT_STATUS HSAKMTAPI hsaKmtDeregisterMemory(void *MemoryAddress) { CHECK_KFD_OPEN(); pr_debug("[%s] address %p\n", __func__, MemoryAddress); return fmm_deregister_memory(MemoryAddress); } HSAKMT_STATUS HSAKMTAPI hsaKmtMapMemoryToGPU(void *MemoryAddress, HSAuint64 MemorySizeInBytes, HSAuint64 *AlternateVAGPU) { CHECK_KFD_OPEN(); pr_debug("[%s] address %p\n", __func__, MemoryAddress); if (!MemoryAddress) { pr_err("FIXME: mapping NULL pointer\n"); return HSAKMT_STATUS_ERROR; } if (AlternateVAGPU) *AlternateVAGPU = 0; return fmm_map_to_gpu(MemoryAddress, MemorySizeInBytes, AlternateVAGPU); } HSAKMT_STATUS HSAKMTAPI hsaKmtMapMemoryToGPUNodes(void *MemoryAddress, HSAuint64 MemorySizeInBytes, HSAuint64 *AlternateVAGPU, HsaMemMapFlags MemMapFlags, HSAuint64 NumberOfNodes, HSAuint32 *NodeArray) { uint32_t *gpu_id_array; HSAKMT_STATUS ret; pr_debug("[%s] address %p number of nodes %lu\n", __func__, MemoryAddress, NumberOfNodes); if (!MemoryAddress) { pr_err("FIXME: mapping NULL pointer\n"); return HSAKMT_STATUS_ERROR; } if (!is_dgpu && NumberOfNodes == 1) return hsaKmtMapMemoryToGPU(MemoryAddress, MemorySizeInBytes, AlternateVAGPU); ret = validate_nodeid_array(&gpu_id_array, NumberOfNodes, NodeArray); if (ret != HSAKMT_STATUS_SUCCESS) return ret; ret = fmm_map_to_gpu_nodes(MemoryAddress, MemorySizeInBytes, gpu_id_array, NumberOfNodes, AlternateVAGPU); if (gpu_id_array) free(gpu_id_array); return ret; } HSAKMT_STATUS HSAKMTAPI hsaKmtUnmapMemoryToGPU(void *MemoryAddress) { CHECK_KFD_OPEN(); pr_debug("[%s] address %p\n", __func__, MemoryAddress); if (!MemoryAddress) { /* Workaround for runtime bug */ pr_err("FIXME: Unmapping NULL pointer\n"); return HSAKMT_STATUS_SUCCESS; } if (!fmm_unmap_from_gpu(MemoryAddress)) return HSAKMT_STATUS_SUCCESS; else return HSAKMT_STATUS_ERROR; } HSAKMT_STATUS HSAKMTAPI hsaKmtMapGraphicHandle(HSAuint32 NodeId, HSAuint64 GraphicDeviceHandle, HSAuint64 GraphicResourceHandle, HSAuint64 GraphicResourceOffset, HSAuint64 GraphicResourceSize, HSAuint64 *FlatMemoryAddress) { /* This API was only ever implemented in KFD for Kaveri and * was never upstreamed. There are no open-source users of * this interface. It has been superseded by * RegisterGraphicsHandleToNodes. */ return HSAKMT_STATUS_NOT_IMPLEMENTED; } HSAKMT_STATUS HSAKMTAPI hsaKmtUnmapGraphicHandle(HSAuint32 NodeId, HSAuint64 FlatMemoryAddress, HSAuint64 SizeInBytes) { return hsaKmtUnmapMemoryToGPU(PORT_UINT64_TO_VPTR(FlatMemoryAddress)); } HSAKMT_STATUS HSAKMTAPI hsaKmtGetTileConfig(HSAuint32 NodeId, HsaGpuTileConfig *config) { struct kfd_ioctl_get_tile_config_args args = {0}; uint32_t gpu_id; HSAKMT_STATUS result; pr_debug("[%s] node %d\n", __func__, NodeId); result = validate_nodeid(NodeId, &gpu_id); if (result != HSAKMT_STATUS_SUCCESS) return result; /* Avoid Valgrind warnings about uninitialized data. Valgrind doesn't * know that KFD writes this. */ memset(config->TileConfig, 0, sizeof(*config->TileConfig) * config->NumTileConfigs); memset(config->MacroTileConfig, 0, sizeof(*config->MacroTileConfig) * config->NumMacroTileConfigs); args.gpu_id = gpu_id; args.tile_config_ptr = (uint64_t)config->TileConfig; args.macro_tile_config_ptr = (uint64_t)config->MacroTileConfig; args.num_tile_configs = config->NumTileConfigs; args.num_macro_tile_configs = config->NumMacroTileConfigs; if (kmtIoctl(kfd_fd, AMDKFD_IOC_GET_TILE_CONFIG, &args) != 0) return HSAKMT_STATUS_ERROR; config->NumTileConfigs = args.num_tile_configs; config->NumMacroTileConfigs = args.num_macro_tile_configs; config->GbAddrConfig = args.gb_addr_config; config->NumBanks = args.num_banks; config->NumRanks = args.num_ranks; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtQueryPointerInfo(const void *Pointer, HsaPointerInfo *PointerInfo) { pr_debug("[%s] pointer %p\n", __func__, Pointer); if (!PointerInfo) return HSAKMT_STATUS_INVALID_PARAMETER; return fmm_get_mem_info(Pointer, PointerInfo); } HSAKMT_STATUS HSAKMTAPI hsaKmtSetMemoryUserData(const void *Pointer, void *UserData) { pr_debug("[%s] pointer %p\n", __func__, Pointer); return fmm_set_mem_user_data(Pointer, UserData); } HSAKMT_STATUS HSAKMTAPI hsaKmtReplaceAsanHeaderPage(void *addr) { #ifdef SANITIZER_AMDGPU pr_debug("[%s] address %p\n", __func__, addr); CHECK_KFD_OPEN(); return fmm_replace_asan_header_page(addr); #else return HSAKMT_STATUS_NOT_SUPPORTED; #endif } HSAKMT_STATUS HSAKMTAPI hsaKmtReturnAsanHeaderPage(void *addr) { #ifdef SANITIZER_AMDGPU pr_debug("[%s] address %p\n", __func__, addr); CHECK_KFD_OPEN(); return fmm_return_asan_header_page(addr); #else return HSAKMT_STATUS_NOT_SUPPORTED; #endif } HSAKMT_STATUS HSAKMTAPI hsaKmtGetAMDGPUDeviceHandle( HSAuint32 NodeId, HsaAMDGPUDeviceHandle *DeviceHandle) { CHECK_KFD_OPEN(); return fmm_get_amdgpu_device_handle(NodeId, DeviceHandle); } ROCT-Thunk-Interface-rocm-5.7.0/src/openclose.c000066400000000000000000000143721446477712600211700ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ /* glibc macro that enables access some nonstandard GNU/Linux extensions * such as RTLD_DEFAULT used by dlsym */ #define _GNU_SOURCE #include "libhsakmt.h" #include #include #include #include #include #include #include #include #include "fmm.h" #include int (*fn_amdgpu_device_get_fd)(HsaAMDGPUDeviceHandle device_handle); static const char kfd_device_name[] = "/dev/kfd"; static pid_t parent_pid = -1; int hsakmt_debug_level; bool hsakmt_forked; /* zfb is mainly used during emulation */ int zfb_support; /* is_forked_child detects when the process has forked since the last * time this function was called. We cannot rely on pthread_atfork * because the process can fork without calling the fork function in * libc (using clone or calling the system call directly). */ bool is_forked_child(void) { pid_t cur_pid; if (hsakmt_forked) return true; cur_pid = getpid(); if (parent_pid == -1) { parent_pid = cur_pid; return false; } if (parent_pid != cur_pid) { hsakmt_forked = true; return true; } return false; } /* Callbacks from pthread_atfork */ static void prepare_fork_handler(void) { pthread_mutex_lock(&hsakmt_mutex); } static void parent_fork_handler(void) { pthread_mutex_unlock(&hsakmt_mutex); } static void child_fork_handler(void) { pthread_mutex_init(&hsakmt_mutex, NULL); hsakmt_forked = true; } /* Call this from the child process after fork. This will clear all * data that is duplicated from the parent process, that is not valid * in the child. * The topology information is duplicated from the parent is valid * in the child process so it is not cleared */ static void clear_after_fork(void) { clear_process_doorbells(); clear_events_page(); fmm_clear_all_mem(); destroy_device_debugging_memory(); if (kfd_fd) { close(kfd_fd); kfd_fd = -1; } kfd_open_count = 0; parent_pid = -1; hsakmt_forked = false; } static inline void init_page_size(void) { PAGE_SIZE = sysconf(_SC_PAGESIZE); PAGE_SHIFT = ffs(PAGE_SIZE) - 1; } static HSAKMT_STATUS init_vars_from_env(void) { char *envvar; int debug_level; /* Normally libraries don't print messages. For debugging purpose, we'll * print messages if an environment variable, HSAKMT_DEBUG_LEVEL, is set. */ hsakmt_debug_level = HSAKMT_DEBUG_LEVEL_DEFAULT; envvar = getenv("HSAKMT_DEBUG_LEVEL"); if (envvar) { debug_level = atoi(envvar); if (debug_level >= HSAKMT_DEBUG_LEVEL_ERR && debug_level <= HSAKMT_DEBUG_LEVEL_DEBUG) hsakmt_debug_level = debug_level; } /* Check whether to support Zero frame buffer */ envvar = getenv("HSA_ZFB"); if (envvar) zfb_support = atoi(envvar); return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtOpenKFD(void) { HSAKMT_STATUS result; int fd = -1; HsaSystemProperties sys_props; char *error; pthread_mutex_lock(&hsakmt_mutex); /* If the process has forked, the child process must re-initialize * it's connection to KFD. Any references tracked by kfd_open_count * belong to the parent */ if (is_forked_child()) clear_after_fork(); if (kfd_open_count == 0) { static bool atfork_installed = false; fn_amdgpu_device_get_fd = dlsym(RTLD_DEFAULT, "amdgpu_device_get_fd"); if ((error = dlerror()) != NULL) pr_err("amdgpu_device_get_fd is not available: %s\n", error); else pr_info("amdgpu_device_get_fd is available %p\n", fn_amdgpu_device_get_fd); result = init_vars_from_env(); if (result != HSAKMT_STATUS_SUCCESS) goto open_failed; if (kfd_fd < 0) { fd = open(kfd_device_name, O_RDWR | O_CLOEXEC); if (fd == -1) { result = HSAKMT_STATUS_KERNEL_IO_CHANNEL_NOT_OPENED; goto open_failed; } kfd_fd = fd; } init_page_size(); result = init_kfd_version(); if (result != HSAKMT_STATUS_SUCCESS) goto kfd_version_failed; result = topology_sysfs_get_system_props(&sys_props); if (result != HSAKMT_STATUS_SUCCESS) goto topology_sysfs_failed; kfd_open_count = 1; if (init_device_debugging_memory(sys_props.NumNodes) != HSAKMT_STATUS_SUCCESS) pr_warn("Insufficient Memory. Debugging unavailable\n"); init_counter_props(sys_props.NumNodes); if (!atfork_installed) { /* Atfork handlers cannot be uninstalled and * must be installed only once. Otherwise * prepare will deadlock when trying to take * the same lock multiple times. */ pthread_atfork(prepare_fork_handler, parent_fork_handler, child_fork_handler); atfork_installed = true; } } else { kfd_open_count++; result = HSAKMT_STATUS_KERNEL_ALREADY_OPENED; } pthread_mutex_unlock(&hsakmt_mutex); return result; topology_sysfs_failed: kfd_version_failed: close(fd); open_failed: pthread_mutex_unlock(&hsakmt_mutex); return result; } HSAKMT_STATUS HSAKMTAPI hsaKmtCloseKFD(void) { HSAKMT_STATUS result; pthread_mutex_lock(&hsakmt_mutex); if (kfd_open_count > 0) { if (--kfd_open_count == 0) { destroy_counter_props(); destroy_device_debugging_memory(); } result = HSAKMT_STATUS_SUCCESS; } else result = HSAKMT_STATUS_KERNEL_IO_CHANNEL_NOT_OPENED; pthread_mutex_unlock(&hsakmt_mutex); return result; } ROCT-Thunk-Interface-rocm-5.7.0/src/perfctr.c000066400000000000000000000602221446477712600206410ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include "libhsakmt.h" #include "pmc_table.h" #include "linux/kfd_ioctl.h" #include #include #include #include #include #include #define BITS_PER_BYTE CHAR_BIT #define HSA_PERF_MAGIC4CC 0x54415348 enum perf_trace_state { PERF_TRACE_STATE__STOPPED = 0, PERF_TRACE_STATE__STARTED }; struct perf_trace_block { enum perf_block_id block_id; uint32_t num_counters; uint64_t *counter_id; int *perf_event_fd; }; struct perf_trace { uint32_t magic4cc; uint32_t gpu_id; enum perf_trace_state state; uint32_t num_blocks; void *buf; uint64_t buf_size; struct perf_trace_block blocks[0]; }; enum perf_trace_action { PERF_TRACE_ACTION__ACQUIRE = 0, PERF_TRACE_ACTION__RELEASE }; struct perf_shared_table { uint32_t magic4cc; uint32_t iommu_slots_left; }; struct perf_counts_values { union { struct { uint64_t val; uint64_t ena; uint64_t run; }; uint64_t values[3]; }; }; static HsaCounterProperties **counter_props; static unsigned int counter_props_count; static const char shmem_name[] = "/hsakmt_shared_mem"; static int shmem_fd; static const char sem_name[] = "hsakmt_semaphore"; static sem_t *sem = SEM_FAILED; struct perf_shared_table *shared_table; static ssize_t readn(int fd, void *buf, size_t n) { size_t left = n; ssize_t bytes; while (left) { bytes = read(fd, buf, left); if (!bytes) /* reach EOF */ return (n - left); if (bytes < 0) { if (errno == EINTR) /* read got interrupted */ continue; else return -errno; } left -= bytes; buf = VOID_PTR_ADD(buf, bytes); } return n; } static HSAKMT_STATUS init_shared_region(void) { sem = sem_open(sem_name, O_CREAT, 0666, 1); if (sem == SEM_FAILED) return HSAKMT_STATUS_ERROR; shmem_fd = shm_open(shmem_name, O_CREAT | O_RDWR, 0666); if (shmem_fd < 0) goto exit_1; if (ftruncate(shmem_fd, sizeof(struct perf_shared_table)) < 0) goto exit_2; shared_table = mmap(NULL, sizeof(*shared_table), PROT_READ | PROT_WRITE, MAP_SHARED, shmem_fd, 0); if (shared_table == MAP_FAILED) goto exit_2; return HSAKMT_STATUS_SUCCESS; exit_2: shm_unlink(shmem_name); shmem_fd = 0; exit_1: sem_close(sem); sem_unlink(sem_name); sem = SEM_FAILED; return HSAKMT_STATUS_ERROR; } static void destroy_shared_region(void) { if (shared_table && shared_table != MAP_FAILED) munmap(shared_table, sizeof(*shared_table)); if (shmem_fd > 0) { close(shmem_fd); shm_unlink(shmem_name); } if (sem != SEM_FAILED) { sem_close(sem); sem_unlink(sem_name); sem = SEM_FAILED; } } static void init_perf_shared_table(void) { sem_wait(sem); /* If the magic number exists, the perf shared table has been * initialized by another process and is in use. Don't overwrite it. */ if (shared_table->magic4cc == HSA_PERF_MAGIC4CC) { sem_post(sem); return; } /* write the perf content */ shared_table->magic4cc = HSA_PERF_MAGIC4CC; shared_table->iommu_slots_left = pmc_table_get_max_concurrent(PERFCOUNTER_BLOCKID__IOMMUV2); sem_post(sem); } HSAKMT_STATUS init_counter_props(unsigned int NumNodes) { counter_props = calloc(NumNodes, sizeof(struct HsaCounterProperties *)); if (!counter_props) { pr_warn("Profiling is not available.\n"); return HSAKMT_STATUS_NO_MEMORY; } counter_props_count = NumNodes; alloc_pmc_blocks(); if (init_shared_region() != HSAKMT_STATUS_SUCCESS) { pr_warn("Profiling of privileged blocks is not available.\n"); return HSAKMT_STATUS_ERROR; } init_perf_shared_table(); return HSAKMT_STATUS_SUCCESS; } void destroy_counter_props(void) { unsigned int i; destroy_shared_region(); if (!counter_props) return; for (i = 0; i < counter_props_count; i++) if (counter_props[i]) { free(counter_props[i]); counter_props[i] = NULL; } free(counter_props); free_pmc_blocks(); } static int blockid2uuid(enum perf_block_id block_id, HSA_UUID *uuid) { int rc = 0; switch (block_id) { case PERFCOUNTER_BLOCKID__CB: *uuid = HSA_PROFILEBLOCK_AMD_CB; break; case PERFCOUNTER_BLOCKID__CPF: *uuid = HSA_PROFILEBLOCK_AMD_CPF; break; case PERFCOUNTER_BLOCKID__CPG: *uuid = HSA_PROFILEBLOCK_AMD_CPG; break; case PERFCOUNTER_BLOCKID__DB: *uuid = HSA_PROFILEBLOCK_AMD_DB; break; case PERFCOUNTER_BLOCKID__GDS: *uuid = HSA_PROFILEBLOCK_AMD_GDS; break; case PERFCOUNTER_BLOCKID__GRBM: *uuid = HSA_PROFILEBLOCK_AMD_GRBM; break; case PERFCOUNTER_BLOCKID__GRBMSE: *uuid = HSA_PROFILEBLOCK_AMD_GRBMSE; break; case PERFCOUNTER_BLOCKID__IA: *uuid = HSA_PROFILEBLOCK_AMD_IA; break; case PERFCOUNTER_BLOCKID__MC: *uuid = HSA_PROFILEBLOCK_AMD_MC; break; case PERFCOUNTER_BLOCKID__PASC: *uuid = HSA_PROFILEBLOCK_AMD_PASC; break; case PERFCOUNTER_BLOCKID__PASU: *uuid = HSA_PROFILEBLOCK_AMD_PASU; break; case PERFCOUNTER_BLOCKID__SPI: *uuid = HSA_PROFILEBLOCK_AMD_SPI; break; case PERFCOUNTER_BLOCKID__SRBM: *uuid = HSA_PROFILEBLOCK_AMD_SRBM; break; case PERFCOUNTER_BLOCKID__SQ: *uuid = HSA_PROFILEBLOCK_AMD_SQ; break; case PERFCOUNTER_BLOCKID__SX: *uuid = HSA_PROFILEBLOCK_AMD_SX; break; case PERFCOUNTER_BLOCKID__TA: *uuid = HSA_PROFILEBLOCK_AMD_TA; break; case PERFCOUNTER_BLOCKID__TCA: *uuid = HSA_PROFILEBLOCK_AMD_TCA; break; case PERFCOUNTER_BLOCKID__TCC: *uuid = HSA_PROFILEBLOCK_AMD_TCC; break; case PERFCOUNTER_BLOCKID__TCP: *uuid = HSA_PROFILEBLOCK_AMD_TCP; break; case PERFCOUNTER_BLOCKID__TCS: *uuid = HSA_PROFILEBLOCK_AMD_TCS; break; case PERFCOUNTER_BLOCKID__TD: *uuid = HSA_PROFILEBLOCK_AMD_TD; break; case PERFCOUNTER_BLOCKID__VGT: *uuid = HSA_PROFILEBLOCK_AMD_VGT; break; case PERFCOUNTER_BLOCKID__WD: *uuid = HSA_PROFILEBLOCK_AMD_WD; break; case PERFCOUNTER_BLOCKID__IOMMUV2: *uuid = HSA_PROFILEBLOCK_AMD_IOMMUV2; break; default: /* If we reach this point, it's a bug */ rc = -1; break; } return rc; } static HSAuint32 get_block_concurrent_limit(uint32_t node_id, HSAuint32 block_id) { uint32_t i; HsaCounterBlockProperties *block = &counter_props[node_id]->Blocks[0]; for (i = 0; i < PERFCOUNTER_BLOCKID__MAX; i++) { if (block->Counters[0].BlockIndex == block_id) return block->NumConcurrent; block = (HsaCounterBlockProperties *)&block->Counters[block->NumCounters]; } return 0; } static HSAKMT_STATUS update_block_slots(enum perf_trace_action action, uint32_t block_id, uint32_t num_slots) { uint32_t *slots_left; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; if (shmem_fd <= 0) return HSAKMT_STATUS_UNAVAILABLE; if (sem == SEM_FAILED) return HSAKMT_STATUS_UNAVAILABLE; sem_wait(sem); if (block_id == PERFCOUNTER_BLOCKID__IOMMUV2) slots_left = &shared_table->iommu_slots_left; else { ret = HSAKMT_STATUS_UNAVAILABLE; goto out; } switch (action) { case PERF_TRACE_ACTION__ACQUIRE: if (*slots_left >= num_slots) *slots_left -= num_slots; else ret = HSAKMT_STATUS_UNAVAILABLE; break; case PERF_TRACE_ACTION__RELEASE: if ((*slots_left + num_slots) <= pmc_table_get_max_concurrent(block_id)) *slots_left += num_slots; else ret = HSAKMT_STATUS_ERROR; break; default: ret = HSAKMT_STATUS_INVALID_PARAMETER; break; } out: sem_post(sem); return ret; } static unsigned int get_perf_event_type(enum perf_block_id block_id) { FILE *file = NULL; unsigned int type = 0; if (block_id == PERFCOUNTER_BLOCKID__IOMMUV2) { /* Starting from kernel 4.12, amd_iommu_0 is used */ file = fopen("/sys/bus/event_source/devices/amd_iommu_0/type", "r"); if (!file) file = fopen(/* kernel 4.11 and older */ "/sys/bus/event_source/devices/amd_iommu/type", "r"); } if (!file) return 0; if (fscanf(file, "%d", &type) != 1) type = 0; fclose(file); return type; } /* close_perf_event_fd - Close all FDs opened for this block. * When RT acquires the trace access, RT has no ideas about each * individual FD opened for this block. We should treat the whole * block as one and close all of them. */ static void close_perf_event_fd(struct perf_trace_block *block) { uint32_t i; if (!block || !block->perf_event_fd) return; for (i = 0; i < block->num_counters; i++) if (block->perf_event_fd[i] > 0) { close(block->perf_event_fd[i]); block->perf_event_fd[i] = 0; } } /* open_perf_event_fd - Open FDs required for this block. * If one of them fails, we should close all FDs that have been * opened because RT has no ideas about those FDs successfully * opened and it won't send anything to close them. */ static HSAKMT_STATUS open_perf_event_fd(struct perf_trace_block *block) { struct perf_event_attr attr; uint32_t i; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; if (!block || !block->perf_event_fd) return HSAKMT_STATUS_INVALID_HANDLE; if (getuid()) { pr_err("Must be root to open perf_event.\n"); return HSAKMT_STATUS_ERROR; } memset(&attr, 0, sizeof(struct perf_event_attr)); attr.type = get_perf_event_type(block->block_id); if (!attr.type) return HSAKMT_STATUS_ERROR; for (i = 0; i < block->num_counters; i++) { attr.size = sizeof(struct perf_event_attr); attr.config = block->counter_id[i]; attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_TOTAL_TIME_RUNNING; attr.disabled = 1; attr.inherit = 1; /* We are profiling system wide, not per cpu, so no threads, * no groups -> pid=-1 and group_fd=-1. cpu = 0 * flags=PERF_FLAG_FD_NO_GROUP */ block->perf_event_fd[i] = syscall(__NR_perf_event_open, &attr, -1, 0, -1, PERF_FLAG_FD_NO_GROUP); if (block->perf_event_fd[i] < 0) { ret = HSAKMT_STATUS_ERROR; close_perf_event_fd(block); break; } } return ret; } static HSAKMT_STATUS perf_trace_ioctl(struct perf_trace_block *block, uint32_t cmd) { uint32_t i; for (i = 0; i < block->num_counters; i++) { if (block->perf_event_fd[i] < 0) return HSAKMT_STATUS_UNAVAILABLE; if (ioctl(block->perf_event_fd[i], cmd, NULL)) return HSAKMT_STATUS_ERROR; } return HSAKMT_STATUS_SUCCESS; } static HSAKMT_STATUS query_trace(int fd, uint64_t *buf) { struct perf_counts_values content; if (fd < 0) return HSAKMT_STATUS_ERROR; if (readn(fd, &content, sizeof(content)) != sizeof(content)) return HSAKMT_STATUS_ERROR; *buf = content.val; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtPmcGetCounterProperties(HSAuint32 NodeId, HsaCounterProperties **CounterProperties) { HSAKMT_STATUS rc = HSAKMT_STATUS_SUCCESS; uint32_t gpu_id, i, block_id; uint32_t counter_props_size = 0; uint32_t total_counters = 0; uint32_t total_concurrent = 0; struct perf_counter_block block = {0}; uint32_t total_blocks = 0; HsaCounterBlockProperties *block_prop; if (!counter_props) return HSAKMT_STATUS_NO_MEMORY; if (!CounterProperties) return HSAKMT_STATUS_INVALID_PARAMETER; if (validate_nodeid(NodeId, &gpu_id) != HSAKMT_STATUS_SUCCESS) return HSAKMT_STATUS_INVALID_NODE_UNIT; if (counter_props[NodeId]) { *CounterProperties = counter_props[NodeId]; return HSAKMT_STATUS_SUCCESS; } for (i = 0; i < PERFCOUNTER_BLOCKID__MAX; i++) { rc = get_block_properties(NodeId, i, &block); if (rc != HSAKMT_STATUS_SUCCESS) return rc; total_concurrent += block.num_of_slots; total_counters += block.num_of_counters; /* If num_of_slots=0, this block doesn't exist */ if (block.num_of_slots) total_blocks++; } counter_props_size = sizeof(HsaCounterProperties) + sizeof(HsaCounterBlockProperties) * (total_blocks - 1) + sizeof(HsaCounter) * (total_counters - total_blocks); counter_props[NodeId] = malloc(counter_props_size); if (!counter_props[NodeId]) return HSAKMT_STATUS_NO_MEMORY; counter_props[NodeId]->NumBlocks = total_blocks; counter_props[NodeId]->NumConcurrent = total_concurrent; block_prop = &counter_props[NodeId]->Blocks[0]; for (block_id = 0; block_id < PERFCOUNTER_BLOCKID__MAX; block_id++) { rc = get_block_properties(NodeId, block_id, &block); if (rc != HSAKMT_STATUS_SUCCESS) { free(counter_props[NodeId]); counter_props[NodeId] = NULL; return rc; } if (!block.num_of_slots) /* not a valid block */ continue; blockid2uuid(block_id, &block_prop->BlockId); block_prop->NumCounters = block.num_of_counters; block_prop->NumConcurrent = block.num_of_slots; for (i = 0; i < block.num_of_counters; i++) { block_prop->Counters[i].BlockIndex = block_id; block_prop->Counters[i].CounterId = block.counter_ids[i]; block_prop->Counters[i].CounterSizeInBits = block.counter_size_in_bits; block_prop->Counters[i].CounterMask = block.counter_mask; block_prop->Counters[i].Flags.ui32.Global = 1; if (block_id == PERFCOUNTER_BLOCKID__IOMMUV2) block_prop->Counters[i].Type = HSA_PROFILE_TYPE_PRIVILEGED_IMMEDIATE; else block_prop->Counters[i].Type = HSA_PROFILE_TYPE_NONPRIV_IMMEDIATE; } block_prop = (HsaCounterBlockProperties *)&block_prop->Counters[block_prop->NumCounters]; } *CounterProperties = counter_props[NodeId]; return HSAKMT_STATUS_SUCCESS; } /* Registers a set of (HW) counters to be used for tracing/profiling */ HSAKMT_STATUS HSAKMTAPI hsaKmtPmcRegisterTrace(HSAuint32 NodeId, HSAuint32 NumberOfCounters, HsaCounter *Counters, HsaPmcTraceRoot *TraceRoot) { uint32_t gpu_id, i, j; uint64_t min_buf_size = 0; struct perf_trace *trace = NULL; uint32_t concurrent_limit; const uint32_t MAX_COUNTERS = 512; uint64_t counter_id[PERFCOUNTER_BLOCKID__MAX][MAX_COUNTERS]; uint32_t num_counters[PERFCOUNTER_BLOCKID__MAX] = {0}; uint32_t block, num_blocks = 0, total_counters = 0; uint64_t *counter_id_ptr; int *fd_ptr; pr_debug("[%s] Number of counters %d\n", __func__, NumberOfCounters); if (!counter_props) return HSAKMT_STATUS_NO_MEMORY; if (!Counters || !TraceRoot || NumberOfCounters == 0) return HSAKMT_STATUS_INVALID_PARAMETER; if (validate_nodeid(NodeId, &gpu_id) != HSAKMT_STATUS_SUCCESS) return HSAKMT_STATUS_INVALID_NODE_UNIT; if (NumberOfCounters > MAX_COUNTERS) { pr_err("MAX_COUNTERS is too small for %d.\n", NumberOfCounters); return HSAKMT_STATUS_NO_MEMORY; } /* Calculating the minimum buffer size */ for (i = 0; i < NumberOfCounters; i++) { if (Counters[i].BlockIndex >= PERFCOUNTER_BLOCKID__MAX) return HSAKMT_STATUS_INVALID_PARAMETER; /* Only privileged counters need to register */ if (Counters[i].Type > HSA_PROFILE_TYPE_PRIVILEGED_STREAMING) continue; min_buf_size += Counters[i].CounterSizeInBits/BITS_PER_BYTE; /* j: the first blank entry in the block to record counter_id */ j = num_counters[Counters[i].BlockIndex]; counter_id[Counters[i].BlockIndex][j] = Counters[i].CounterId; num_counters[Counters[i].BlockIndex]++; total_counters++; } /* Verify that the number of counters per block is not larger than the * number of slots. */ for (i = 0; i < PERFCOUNTER_BLOCKID__MAX; i++) { if (!num_counters[i]) continue; concurrent_limit = get_block_concurrent_limit(NodeId, i); if (!concurrent_limit) { pr_err("Invalid block ID: %d\n", i); return HSAKMT_STATUS_INVALID_PARAMETER; } if (num_counters[i] > concurrent_limit) { pr_err("Counters exceed the limit.\n"); return HSAKMT_STATUS_INVALID_PARAMETER; } num_blocks++; } if (!num_blocks) return HSAKMT_STATUS_INVALID_PARAMETER; /* Now we have sorted blocks/counters information in * num_counters[block_id] and counter_id[block_id][]. Allocate trace * and record the information. */ trace = (struct perf_trace *)calloc(sizeof(struct perf_trace) + sizeof(struct perf_trace_block) * num_blocks + sizeof(uint64_t) * total_counters + sizeof(int) * total_counters, 1); if (!trace) return HSAKMT_STATUS_NO_MEMORY; /* Allocated area is partitioned as: * +---------------------------------+ trace * | perf_trace | * |---------------------------------| trace->blocks[0] * | perf_trace_block 0 | * | .... | * | perf_trace_block N-1 | trace->blocks[N-1] * |---------------------------------| <-- counter_id_ptr starts here * | block 0's counter IDs(uint64_t) | * | ...... | * | block N-1's counter IDs | * |---------------------------------| <-- perf_event_fd starts here * | block 0's perf_event_fds(int) | * | ...... | * | block N-1's perf_event_fds | * +---------------------------------+ */ block = 0; counter_id_ptr = (uint64_t *)((char *) trace + sizeof(struct perf_trace) + sizeof(struct perf_trace_block) * num_blocks); fd_ptr = (int *)(counter_id_ptr + total_counters); /* Fill in each block's information to the TraceId */ for (i = 0; i < PERFCOUNTER_BLOCKID__MAX; i++) { if (!num_counters[i]) /* not a block to trace */ continue; /* Following perf_trace + perf_trace_block x N are those * counter_id arrays. Assign the counter_id array belonging to * this block. */ trace->blocks[block].counter_id = counter_id_ptr; /* Fill in counter IDs to the counter_id array. */ for (j = 0; j < num_counters[i]; j++) trace->blocks[block].counter_id[j] = counter_id[i][j]; trace->blocks[block].perf_event_fd = fd_ptr; /* how many counters to trace */ trace->blocks[block].num_counters = num_counters[i]; /* block index in "enum perf_block_id" */ trace->blocks[block].block_id = i; block++; /* move to next */ counter_id_ptr += num_counters[i]; fd_ptr += num_counters[i]; } trace->magic4cc = HSA_PERF_MAGIC4CC; trace->gpu_id = gpu_id; trace->state = PERF_TRACE_STATE__STOPPED; trace->num_blocks = num_blocks; TraceRoot->NumberOfPasses = 1; TraceRoot->TraceBufferMinSizeBytes = PAGE_ALIGN_UP(min_buf_size); TraceRoot->TraceId = PORT_VPTR_TO_UINT64(trace); return HSAKMT_STATUS_SUCCESS; } /* Unregisters a set of (HW) counters used for tracing/profiling */ HSAKMT_STATUS HSAKMTAPI hsaKmtPmcUnregisterTrace(HSAuint32 NodeId, HSATraceId TraceId) { uint32_t gpu_id; struct perf_trace *trace; pr_debug("[%s] Trace ID 0x%lx\n", __func__, TraceId); if (TraceId == 0) return HSAKMT_STATUS_INVALID_PARAMETER; if (validate_nodeid(NodeId, &gpu_id) != HSAKMT_STATUS_SUCCESS) return HSAKMT_STATUS_INVALID_NODE_UNIT; trace = (struct perf_trace *)PORT_UINT64_TO_VPTR(TraceId); if (trace->magic4cc != HSA_PERF_MAGIC4CC) return HSAKMT_STATUS_INVALID_HANDLE; if (trace->gpu_id != gpu_id) return HSAKMT_STATUS_INVALID_NODE_UNIT; /* If the trace is in the running state, stop it */ if (trace->state == PERF_TRACE_STATE__STARTED) { HSAKMT_STATUS status = hsaKmtPmcStopTrace(TraceId); if (status != HSAKMT_STATUS_SUCCESS) return status; } free(trace); return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtPmcAcquireTraceAccess(HSAuint32 NodeId, HSATraceId TraceId) { struct perf_trace *trace; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; uint32_t gpu_id, i; int j; pr_debug("[%s] Trace ID 0x%lx\n", __func__, TraceId); if (TraceId == 0) return HSAKMT_STATUS_INVALID_PARAMETER; trace = (struct perf_trace *)PORT_UINT64_TO_VPTR(TraceId); if (trace->magic4cc != HSA_PERF_MAGIC4CC) return HSAKMT_STATUS_INVALID_HANDLE; if (validate_nodeid(NodeId, &gpu_id) != HSAKMT_STATUS_SUCCESS) return HSAKMT_STATUS_INVALID_NODE_UNIT; for (i = 0; i < trace->num_blocks; i++) { ret = update_block_slots(PERF_TRACE_ACTION__ACQUIRE, trace->blocks[i].block_id, trace->blocks[i].num_counters); if (ret != HSAKMT_STATUS_SUCCESS) goto out; ret = open_perf_event_fd(&trace->blocks[i]); if (ret != HSAKMT_STATUS_SUCCESS) { i++; /* to release slots just reserved */ goto out; } } out: if (ret != HSAKMT_STATUS_SUCCESS) { for (j = i-1; j >= 0; j--) { update_block_slots(PERF_TRACE_ACTION__RELEASE, trace->blocks[j].block_id, trace->blocks[j].num_counters); close_perf_event_fd(&trace->blocks[j]); } } return ret; } HSAKMT_STATUS HSAKMTAPI hsaKmtPmcReleaseTraceAccess(HSAuint32 NodeId, HSATraceId TraceId) { struct perf_trace *trace; uint32_t i; pr_debug("[%s] Trace ID 0x%lx\n", __func__, TraceId); if (TraceId == 0) return HSAKMT_STATUS_INVALID_PARAMETER; trace = (struct perf_trace *)PORT_UINT64_TO_VPTR(TraceId); if (trace->magic4cc != HSA_PERF_MAGIC4CC) return HSAKMT_STATUS_INVALID_HANDLE; for (i = 0; i < trace->num_blocks; i++) { update_block_slots(PERF_TRACE_ACTION__RELEASE, trace->blocks[i].block_id, trace->blocks[i].num_counters); close_perf_event_fd(&trace->blocks[i]); } return HSAKMT_STATUS_SUCCESS; } /* Starts tracing operation on a previously established set of performance counters */ HSAKMT_STATUS HSAKMTAPI hsaKmtPmcStartTrace(HSATraceId TraceId, void *TraceBuffer, HSAuint64 TraceBufferSizeBytes) { struct perf_trace *trace = (struct perf_trace *)PORT_UINT64_TO_VPTR(TraceId); uint32_t i; int32_t j; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; pr_debug("[%s] Trace ID 0x%lx\n", __func__, TraceId); if (TraceId == 0 || !TraceBuffer || TraceBufferSizeBytes == 0) return HSAKMT_STATUS_INVALID_PARAMETER; if (trace->magic4cc != HSA_PERF_MAGIC4CC) return HSAKMT_STATUS_INVALID_HANDLE; for (i = 0; i < trace->num_blocks; i++) { ret = perf_trace_ioctl(&trace->blocks[i], PERF_EVENT_IOC_ENABLE); if (ret != HSAKMT_STATUS_SUCCESS) break; } if (ret != HSAKMT_STATUS_SUCCESS) { /* Disable enabled blocks before returning the failure. */ j = (int32_t)i; while (--j >= 0) perf_trace_ioctl(&trace->blocks[j], PERF_EVENT_IOC_DISABLE); return ret; } trace->state = PERF_TRACE_STATE__STARTED; trace->buf = TraceBuffer; trace->buf_size = TraceBufferSizeBytes; return HSAKMT_STATUS_SUCCESS; } /*Forces an update of all the counters that a previously started trace operation has registered */ HSAKMT_STATUS HSAKMTAPI hsaKmtPmcQueryTrace(HSATraceId TraceId) { struct perf_trace *trace = (struct perf_trace *)PORT_UINT64_TO_VPTR(TraceId); uint32_t i, j; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; uint64_t *buf; uint64_t buf_filled = 0; if (TraceId == 0) return HSAKMT_STATUS_INVALID_PARAMETER; if (trace->magic4cc != HSA_PERF_MAGIC4CC) return HSAKMT_STATUS_INVALID_HANDLE; buf = (uint64_t *)trace->buf; pr_debug("[%s] Trace buffer(%p): ", __func__, buf); for (i = 0; i < trace->num_blocks; i++) for (j = 0; j < trace->blocks[i].num_counters; j++) { buf_filled += sizeof(uint64_t); if (buf_filled > trace->buf_size) return HSAKMT_STATUS_NO_MEMORY; ret = query_trace(trace->blocks[i].perf_event_fd[j], buf); if (ret != HSAKMT_STATUS_SUCCESS) return ret; pr_debug("%lu_", *buf); buf++; } pr_debug("\n"); return HSAKMT_STATUS_SUCCESS; } /* Stops tracing operation on a previously established set of performance counters */ HSAKMT_STATUS HSAKMTAPI hsaKmtPmcStopTrace(HSATraceId TraceId) { struct perf_trace *trace = (struct perf_trace *)PORT_UINT64_TO_VPTR(TraceId); uint32_t i; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; pr_debug("[%s] Trace ID 0x%lx\n", __func__, TraceId); if (TraceId == 0) return HSAKMT_STATUS_INVALID_PARAMETER; if (trace->magic4cc != HSA_PERF_MAGIC4CC) return HSAKMT_STATUS_INVALID_HANDLE; for (i = 0; i < trace->num_blocks; i++) { ret = perf_trace_ioctl(&trace->blocks[i], PERF_EVENT_IOC_DISABLE); if (ret != HSAKMT_STATUS_SUCCESS) return ret; } trace->state = PERF_TRACE_STATE__STOPPED; return ret; } ROCT-Thunk-Interface-rocm-5.7.0/src/pmc_table.c000066400000000000000000002643411446477712600211320ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include "libhsakmt.h" #include "pmc_table.h" /****** CB ******/ static uint32_t gfx7_cb_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225 }; static uint32_t gfx8_cb_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395 }; static uint32_t gfx9_cb_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431, 432, 433, 434, 435, 436, 437 }; static uint32_t gfx10_cb_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431, 432, 433, 434, 435, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 455, 456, 457, 458, 459, 460 }; /****** CPF ******/ static uint32_t gfx7_cpf_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 }; static uint32_t gfx8_cpf_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 }; static uint32_t gfx9_cpf_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, }; static uint32_t gfx10_cpf_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 }; /****** CPG ******/ static uint32_t gfx7_cpg_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45 }; static uint32_t gfx8_cpg_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48 }; static uint32_t gfx9_cpg_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58 }; static uint32_t gfx10_cpg_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81 }; /****** DB ******/ static uint32_t gfx7_db_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256 }; /* gfx8_db_counter_ids are the same as gfx7_db_counter_ids */ static uint32_t gfx9_db_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327 }; static uint32_t gfx10_db_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369 }; /****** GDS ******/ static uint32_t gfx7_gds_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120 }; /* gfx8_gds_counter_ids are the same as gfx7_gds_counter_ids */ /* gfx9_gds_counter_ids are the same as gfx7_gds_counter_ids */ static uint32_t gfx10_gds_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122 }; /****** GRBM ******/ static uint32_t gfx7_grbm_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 }; /* gfx8_grbm_counter_ids are the same as gfx7_grbm_counter_ids */ static uint32_t gfx9_grbm_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 }; static uint32_t gfx10_grbm_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46 }; /****** GRBMSE ******/ static uint32_t gfx7_grbmse_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; /* gfx8_grbmse_counter_ids are the same as gfx7_grbmse_counter_ids */ static uint32_t gfx9_grbmse_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; static uint32_t gfx10_grbmse_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 }; /****** IA ******/ static uint32_t gfx7_ia_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 }; static uint32_t gfx8_ia_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; static uint32_t gfx9_ia_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 }; /* gfx10 doesn't have IA */ /****** PASC ******/ static uint32_t gfx7_pasc_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394 }; static uint32_t gfx8_pasc_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 396 }; static uint32_t gfx9_pasc_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431, 432, 433, 434, 435, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, 461, 462, 463, 464, 465, 466, 467, 468, 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, 488, 489, 490 }; static uint32_t gfx10_pasc_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431, 432, 433, 434, 435, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, 461, 462, 463, 464, 465, 466, 467, 468, 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, 527, 528, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551 }; /****** PASU ******/ static uint32_t gfx7_pasu_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152 }; /* gfx8_pasu_counter_ids are the same as gfx7_pasu_counter_ids */ static uint32_t gfx9_pasu_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291 }; static uint32_t gfx10_pasu_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265 }; /****** SPI ******/ static uint32_t gfx7_spi_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185 }; static uint32_t gfx8_spi_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196 }; static uint32_t gfx9_spi_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195 }; static uint32_t gfx10_spi_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328 }; /****** SQ ******/ /* Unused counters - 163-167 */ static uint32_t gfx7_sq_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250 }; /* Unused counters - 166, 292 - 297 */ static uint32_t gfx8_sq_counter_ids[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 298 }; /* Polaris 10/11/12 have the same SQ cpunter IDs but different from other gfx8's. */ /* Unused counters - 167 and 275 are *_DUMMY_LAST */ static uint32_t gfx8_pl_sq_counter_ids[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295 }; static uint32_t gfx9_sq_counter_ids[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372 }; static uint32_t gfx10_sq_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431, 432, 433, 434, 435, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, 461, 462, 463, 464, 465, 466, 467, 468, 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511 }; /****** SRBM ******/ static uint32_t gfx7_srbm_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 }; static uint32_t gfx8_srbm_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 }; /* gfx9 doesn't have SRBM */ /* gfx10 doesn't have SRBM */ /****** SX ******/ static uint32_t gfx7_sx_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 }; /* gfx8_sx_counter_ids are the same as gfx7_sx_counter_ids */ static uint32_t gfx9_sx_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207 }; static uint32_t gfx10_sx_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224 }; /****** TA ******/ static uint32_t gfx7_ta_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110 }; static uint32_t gfx8_ta_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118 }; /* gfx9_ta_counter_ids is same as gfx8_ta_counter_ids */ static uint32_t gfx10_ta_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225 }; /****** TCA ******/ static uint32_t gfx7_tca_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38 }; static uint32_t gfx8_tca_counter_ids[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 }; /* gfx9_tca_counter_ids is same as gfx8_tca_counter_ids */ /* gfx10 doesn't have TCA */ /****** TCC ******/ static uint32_t gfx7_tcc_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 159 }; static uint32_t gfx8_tcc_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255 }; static uint32_t gfx8_cz_tcc_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191 }; /* gfx9_tcc_counter_ids is same as gfx8_tcc_counter_ids */ /* gfx10 doesn't have TCC */ /****** TCP ******/ static uint32_t gfx7_tcp_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153 }; static uint32_t gfx8_tcp_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182 }; static uint32_t gfx9_tcp_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84 }; static uint32_t gfx10_tcp_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76 }; /****** TCS ******/ static uint32_t gfx7_tcs_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127 }; /* gfx8 doesn't have TCS */ /* gfx9 doesn't have TCS */ /* gfx10 doesn't have TCS */ /****** TD ******/ static uint32_t gfx7_td_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54 }; /* gfx8_td_counter_ids are the same as gfx7_td_counter_ids */ static uint32_t gfx9_td_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 }; static uint32_t gfx10_td_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60 }; /****** VGT ******/ static uint32_t gfx7_vgt_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139 }; static uint32_t gfx8_vgt_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145 }; static uint32_t gfx8_pl_vgt_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146 }; static uint32_t gfx9_vgt_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147 }; /* gfx10 doesn't have VGT */ /****** WD ******/ static uint32_t gfx7_wd_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 }; static uint32_t gfx8_wd_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 }; static uint32_t gfx9_wd_counter_ids[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57 }; /* gfx10 doesn't have WD */ static struct perf_counter_block kaveri_blocks[PERFCOUNTER_BLOCKID__MAX] = { [PERFCOUNTER_BLOCKID__SQ] = { .num_of_slots = 8, .num_of_counters = sizeof(gfx7_sq_counter_ids) / sizeof(*gfx7_sq_counter_ids), .counter_ids = gfx7_sq_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, }; static struct perf_counter_block hawaii_blocks[PERFCOUNTER_BLOCKID__MAX] = { [PERFCOUNTER_BLOCKID__CB] = { .num_of_slots = 7, .num_of_counters = sizeof(gfx7_cb_counter_ids) / sizeof(*gfx7_cb_counter_ids), .counter_ids = gfx7_cb_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__CPF] = { .num_of_slots = 5, .num_of_counters = sizeof(gfx7_cpf_counter_ids) / sizeof(*gfx7_cpf_counter_ids), .counter_ids = gfx7_cpf_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__CPG] = { .num_of_slots = 5, .num_of_counters = sizeof(gfx7_cpg_counter_ids) / sizeof(*gfx7_cpg_counter_ids), .counter_ids = gfx7_cpg_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__DB] = { .num_of_slots = 12, .num_of_counters = sizeof(gfx7_db_counter_ids) / sizeof(*gfx7_db_counter_ids), .counter_ids = gfx7_db_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GDS] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx7_gds_counter_ids) / sizeof(*gfx7_gds_counter_ids), .counter_ids = gfx7_gds_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GRBM] = { .num_of_slots = 2, .num_of_counters = sizeof(gfx7_grbm_counter_ids) / sizeof(*gfx7_grbm_counter_ids), .counter_ids = gfx7_grbm_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GRBMSE] = { .num_of_slots = 1, .num_of_counters = sizeof(gfx7_grbmse_counter_ids) / sizeof(*gfx7_grbmse_counter_ids), .counter_ids = gfx7_grbmse_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__IA] = { .num_of_slots = 7, .num_of_counters = sizeof(gfx7_ia_counter_ids) / sizeof(*gfx7_ia_counter_ids), .counter_ids = gfx7_ia_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__PASC] = { .num_of_slots = 11, .num_of_counters = sizeof(gfx7_pasc_counter_ids) / sizeof(*gfx7_pasc_counter_ids), .counter_ids = gfx7_pasc_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__PASU] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx7_pasu_counter_ids) / sizeof(*gfx7_pasu_counter_ids), .counter_ids = gfx7_pasu_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SPI] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx7_spi_counter_ids) / sizeof(*gfx7_spi_counter_ids), .counter_ids = gfx7_spi_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SRBM] = { .num_of_slots = 2, .num_of_counters = sizeof(gfx7_srbm_counter_ids) / sizeof(*gfx7_srbm_counter_ids), .counter_ids = gfx7_srbm_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SQ] = { .num_of_slots = 8, .num_of_counters = sizeof(gfx7_sq_counter_ids) / sizeof(*gfx7_sq_counter_ids), .counter_ids = gfx7_sq_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SX] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx7_sx_counter_ids) / sizeof(*gfx7_sx_counter_ids), .counter_ids = gfx7_sx_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TA] = { .num_of_slots = 6, .num_of_counters = sizeof(gfx7_ta_counter_ids) / sizeof(*gfx7_ta_counter_ids), .counter_ids = gfx7_ta_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCA] = { .num_of_slots = 10, /* same as CZ */ .num_of_counters = sizeof(gfx7_tca_counter_ids) / sizeof(*gfx7_tca_counter_ids), .counter_ids = gfx7_tca_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCC] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx7_tcc_counter_ids) / sizeof(*gfx7_tcc_counter_ids), .counter_ids = gfx7_tcc_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCP] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx7_tcp_counter_ids) / sizeof(*gfx7_tcp_counter_ids), .counter_ids = gfx7_tcp_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCS] = { .num_of_slots = 7, .num_of_counters = sizeof(gfx7_tcs_counter_ids) / sizeof(*gfx7_tcs_counter_ids), .counter_ids = gfx7_tcs_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TD] = { .num_of_slots = 6, .num_of_counters = sizeof(gfx7_td_counter_ids) / sizeof(*gfx7_td_counter_ids), .counter_ids = gfx7_td_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__VGT] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx7_vgt_counter_ids) / sizeof(*gfx7_vgt_counter_ids), .counter_ids = gfx7_vgt_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__WD] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx7_wd_counter_ids) / sizeof(*gfx7_wd_counter_ids), .counter_ids = gfx7_wd_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, }; static struct perf_counter_block carrizo_blocks[PERFCOUNTER_BLOCKID__MAX] = { [PERFCOUNTER_BLOCKID__CB] = { .num_of_slots = 7, .num_of_counters = sizeof(gfx8_cb_counter_ids) / sizeof(*gfx8_cb_counter_ids), .counter_ids = gfx8_cb_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__CPF] = { .num_of_slots = 5, .num_of_counters = sizeof(gfx8_cpf_counter_ids) / sizeof(*gfx8_cpf_counter_ids), .counter_ids = gfx8_cpf_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__CPG] = { .num_of_slots = 5, .num_of_counters = sizeof(gfx8_cpg_counter_ids) / sizeof(*gfx8_cpg_counter_ids), .counter_ids = gfx8_cpg_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__DB] = { .num_of_slots = 12, .num_of_counters = sizeof(gfx7_db_counter_ids) / sizeof(*gfx7_db_counter_ids), .counter_ids = gfx7_db_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GDS] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx7_gds_counter_ids) / sizeof(*gfx7_gds_counter_ids), .counter_ids = gfx7_gds_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GRBM] = { .num_of_slots = 2, .num_of_counters = sizeof(gfx7_grbm_counter_ids) / sizeof(*gfx7_grbm_counter_ids), .counter_ids = gfx7_grbm_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GRBMSE] = { .num_of_slots = 1, .num_of_counters = sizeof(gfx7_grbmse_counter_ids) / sizeof(*gfx7_grbmse_counter_ids), .counter_ids = gfx7_grbmse_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__IA] = { .num_of_slots = 7, .num_of_counters = sizeof(gfx8_ia_counter_ids) / sizeof(*gfx8_ia_counter_ids), .counter_ids = gfx8_ia_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__PASC] = { .num_of_slots = 11, .num_of_counters = sizeof(gfx8_pasc_counter_ids) / sizeof(*gfx8_pasc_counter_ids), .counter_ids = gfx8_pasc_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__PASU] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx7_pasu_counter_ids) / sizeof(*gfx7_pasu_counter_ids), .counter_ids = gfx7_pasu_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SPI] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx8_spi_counter_ids) / sizeof(*gfx8_spi_counter_ids), .counter_ids = gfx8_spi_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SRBM] = { .num_of_slots = 2, .num_of_counters = sizeof(gfx8_srbm_counter_ids) / sizeof(*gfx8_srbm_counter_ids), .counter_ids = gfx8_srbm_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SQ] = { .num_of_slots = 8, .num_of_counters = sizeof(gfx8_sq_counter_ids) / sizeof(*gfx8_sq_counter_ids), .counter_ids = gfx8_sq_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SX] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx7_sx_counter_ids) / sizeof(*gfx7_sx_counter_ids), .counter_ids = gfx7_sx_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TA] = { .num_of_slots = 6, .num_of_counters = sizeof(gfx8_ta_counter_ids) / sizeof(*gfx8_ta_counter_ids), .counter_ids = gfx8_ta_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCA] = { /* PMC0: PERF_SEL~PERF_SEL3, PMC1: PERF_SEL~PERF_SEL3, * PMC2: PERF_SEL, PMC3: PERF_SEL. So 10 PERF_SELs in total */ .num_of_slots = 10, .num_of_counters = sizeof(gfx8_tca_counter_ids) / sizeof(*gfx8_tca_counter_ids), .counter_ids = gfx8_tca_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCC] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx8_cz_tcc_counter_ids) / sizeof(*gfx8_cz_tcc_counter_ids), .counter_ids = gfx8_cz_tcc_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCP] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx8_tcp_counter_ids) / sizeof(*gfx8_tcp_counter_ids), .counter_ids = gfx8_tcp_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TD] = { .num_of_slots = 6, .num_of_counters = sizeof(gfx7_td_counter_ids) / sizeof(*gfx7_td_counter_ids), .counter_ids = gfx7_td_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__VGT] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx8_vgt_counter_ids) / sizeof(*gfx8_vgt_counter_ids), .counter_ids = gfx8_vgt_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__WD] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx8_wd_counter_ids) / sizeof(*gfx8_wd_counter_ids), .counter_ids = gfx8_wd_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, }; static struct perf_counter_block fiji_blocks[PERFCOUNTER_BLOCKID__MAX] = { [PERFCOUNTER_BLOCKID__CB] = { .num_of_slots = 7, .num_of_counters = sizeof(gfx8_cb_counter_ids) / sizeof(*gfx8_cb_counter_ids), .counter_ids = gfx8_cb_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__CPF] = { .num_of_slots = 5, .num_of_counters = sizeof(gfx8_cpf_counter_ids) / sizeof(*gfx8_cpf_counter_ids), .counter_ids = gfx8_cpf_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__CPG] = { .num_of_slots = 5, .num_of_counters = sizeof(gfx8_cpg_counter_ids) / sizeof(*gfx8_cpg_counter_ids), .counter_ids = gfx8_cpg_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__DB] = { .num_of_slots = 12, .num_of_counters = sizeof(gfx7_db_counter_ids) / sizeof(*gfx7_db_counter_ids), .counter_ids = gfx7_db_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GDS] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx7_gds_counter_ids) / sizeof(*gfx7_gds_counter_ids), .counter_ids = gfx7_gds_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GRBM] = { .num_of_slots = 2, .num_of_counters = sizeof(gfx7_grbm_counter_ids) / sizeof(*gfx7_grbm_counter_ids), .counter_ids = gfx7_grbm_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GRBMSE] = { .num_of_slots = 1, .num_of_counters = sizeof(gfx7_grbmse_counter_ids) / sizeof(*gfx7_grbmse_counter_ids), .counter_ids = gfx7_grbmse_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__IA] = { .num_of_slots = 7, .num_of_counters = sizeof(gfx8_ia_counter_ids) / sizeof(*gfx8_ia_counter_ids), .counter_ids = gfx8_ia_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__PASC] = { .num_of_slots = 11, .num_of_counters = sizeof(gfx8_pasc_counter_ids) / sizeof(*gfx8_pasc_counter_ids), .counter_ids = gfx8_pasc_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__PASU] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx7_pasu_counter_ids) / sizeof(*gfx7_pasu_counter_ids), .counter_ids = gfx7_pasu_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SPI] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx8_spi_counter_ids) / sizeof(*gfx8_spi_counter_ids), .counter_ids = gfx8_spi_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SRBM] = { .num_of_slots = 2, .num_of_counters = sizeof(gfx8_srbm_counter_ids) / sizeof(*gfx8_srbm_counter_ids), .counter_ids = gfx8_srbm_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SQ] = { .num_of_slots = 8, .num_of_counters = sizeof(gfx8_sq_counter_ids) / sizeof(*gfx8_sq_counter_ids), .counter_ids = gfx8_sq_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SX] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx7_sx_counter_ids) / sizeof(*gfx7_sx_counter_ids), .counter_ids = gfx7_sx_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TA] = { .num_of_slots = 6, .num_of_counters = sizeof(gfx8_ta_counter_ids) / sizeof(*gfx8_ta_counter_ids), .counter_ids = gfx8_ta_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCA] = { .num_of_slots = 10, /* same as CZ */ .num_of_counters = sizeof(gfx8_tca_counter_ids) / sizeof(*gfx8_tca_counter_ids), .counter_ids = gfx8_tca_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCC] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx8_tcc_counter_ids) / sizeof(*gfx8_tcc_counter_ids), .counter_ids = gfx8_tcc_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCP] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx8_tcp_counter_ids) / sizeof(*gfx8_tcp_counter_ids), .counter_ids = gfx8_tcp_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TD] = { .num_of_slots = 6, .num_of_counters = sizeof(gfx7_td_counter_ids) / sizeof(*gfx7_td_counter_ids), .counter_ids = gfx7_td_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__VGT] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx8_vgt_counter_ids) / sizeof(*gfx8_vgt_counter_ids), .counter_ids = gfx8_vgt_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__WD] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx8_wd_counter_ids) / sizeof(*gfx8_wd_counter_ids), .counter_ids = gfx8_wd_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, }; static struct perf_counter_block polaris_blocks[PERFCOUNTER_BLOCKID__MAX] = { [PERFCOUNTER_BLOCKID__CB] = { .num_of_slots = 7, .num_of_counters = sizeof(gfx8_cb_counter_ids) / sizeof(*gfx8_cb_counter_ids), .counter_ids = gfx8_cb_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__CPF] = { .num_of_slots = 5, .num_of_counters = sizeof(gfx8_cpf_counter_ids) / sizeof(*gfx8_cpf_counter_ids), .counter_ids = gfx8_cpf_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__CPG] = { .num_of_slots = 5, .num_of_counters = sizeof(gfx8_cpg_counter_ids) / sizeof(*gfx8_cpg_counter_ids), .counter_ids = gfx8_cpg_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__DB] = { .num_of_slots = 12, .num_of_counters = sizeof(gfx7_db_counter_ids) / sizeof(*gfx7_db_counter_ids), .counter_ids = gfx7_db_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GDS] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx7_gds_counter_ids) / sizeof(*gfx7_gds_counter_ids), .counter_ids = gfx7_gds_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GRBM] = { .num_of_slots = 2, .num_of_counters = sizeof(gfx7_grbm_counter_ids) / sizeof(*gfx7_grbm_counter_ids), .counter_ids = gfx7_grbm_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GRBMSE] = { .num_of_slots = 1, .num_of_counters = sizeof(gfx7_grbmse_counter_ids) / sizeof(*gfx7_grbmse_counter_ids), .counter_ids = gfx7_grbmse_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__IA] = { .num_of_slots = 7, .num_of_counters = sizeof(gfx8_ia_counter_ids) / sizeof(*gfx8_ia_counter_ids), .counter_ids = gfx8_ia_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__PASC] = { .num_of_slots = 11, .num_of_counters = sizeof(gfx8_pasc_counter_ids) / sizeof(*gfx8_pasc_counter_ids), .counter_ids = gfx8_pasc_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__PASU] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx7_pasu_counter_ids) / sizeof(*gfx7_pasu_counter_ids), .counter_ids = gfx7_pasu_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SPI] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx8_spi_counter_ids) / sizeof(*gfx8_spi_counter_ids), .counter_ids = gfx8_spi_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SQ] = { .num_of_slots = 8, .num_of_counters = sizeof(gfx8_pl_sq_counter_ids) / sizeof(*gfx8_pl_sq_counter_ids), .counter_ids = gfx8_pl_sq_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SRBM] = { .num_of_slots = 2, .num_of_counters = sizeof(gfx8_srbm_counter_ids) / sizeof(*gfx8_srbm_counter_ids), .counter_ids = gfx8_srbm_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SX] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx7_sx_counter_ids) / sizeof(*gfx7_sx_counter_ids), .counter_ids = gfx7_sx_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TA] = { .num_of_slots = 6, .num_of_counters = sizeof(gfx8_ta_counter_ids) / sizeof(*gfx8_ta_counter_ids), .counter_ids = gfx8_ta_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCA] = { .num_of_slots = 10, /* same as CZ */ .num_of_counters = sizeof(gfx8_tca_counter_ids) / sizeof(*gfx8_tca_counter_ids), .counter_ids = gfx8_tca_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCC] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx8_tcc_counter_ids) / sizeof(*gfx8_tcc_counter_ids), .counter_ids = gfx8_tcc_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCP] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx8_tcp_counter_ids) / sizeof(*gfx8_tcp_counter_ids), .counter_ids = gfx8_tcp_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TD] = { .num_of_slots = 6, .num_of_counters = sizeof(gfx7_td_counter_ids) / sizeof(*gfx7_td_counter_ids), .counter_ids = gfx7_td_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__VGT] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx8_pl_vgt_counter_ids) / sizeof(*gfx8_pl_vgt_counter_ids), .counter_ids = gfx8_pl_vgt_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__WD] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx8_wd_counter_ids) / sizeof(*gfx8_wd_counter_ids), .counter_ids = gfx8_wd_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, }; static struct perf_counter_block vega_blocks[PERFCOUNTER_BLOCKID__MAX] = { [PERFCOUNTER_BLOCKID__CB] = { .num_of_slots = 7, .num_of_counters = sizeof(gfx9_cb_counter_ids) / sizeof(*gfx9_cb_counter_ids), .counter_ids = gfx9_cb_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__CPF] = { .num_of_slots = 5, .num_of_counters = sizeof(gfx9_cpf_counter_ids) / sizeof(*gfx9_cpf_counter_ids), .counter_ids = gfx9_cpf_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__CPG] = { .num_of_slots = 5, .num_of_counters = sizeof(gfx9_cpg_counter_ids) / sizeof(*gfx9_cpg_counter_ids), .counter_ids = gfx9_cpg_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__DB] = { .num_of_slots = 12, .num_of_counters = sizeof(gfx9_db_counter_ids) / sizeof(*gfx9_db_counter_ids), .counter_ids = gfx9_db_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GDS] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx7_gds_counter_ids) / sizeof(*gfx7_gds_counter_ids), .counter_ids = gfx7_gds_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GRBM] = { .num_of_slots = 2, .num_of_counters = sizeof(gfx9_grbm_counter_ids) / sizeof(*gfx9_grbm_counter_ids), .counter_ids = gfx9_grbm_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GRBMSE] = { .num_of_slots = 1, .num_of_counters = sizeof(gfx9_grbmse_counter_ids) / sizeof(*gfx9_grbmse_counter_ids), .counter_ids = gfx9_grbmse_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__IA] = { .num_of_slots = 7, .num_of_counters = sizeof(gfx9_ia_counter_ids) / sizeof(*gfx9_ia_counter_ids), .counter_ids = gfx9_ia_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__PASC] = { .num_of_slots = 11, .num_of_counters = sizeof(gfx9_pasc_counter_ids) / sizeof(*gfx9_pasc_counter_ids), .counter_ids = gfx9_pasc_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__PASU] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx9_pasu_counter_ids) / sizeof(*gfx9_pasu_counter_ids), .counter_ids = gfx9_pasu_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SPI] = { .num_of_slots = 18, .num_of_counters = sizeof(gfx9_spi_counter_ids) / sizeof(*gfx9_spi_counter_ids), .counter_ids = gfx9_spi_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SQ] = { .num_of_slots = 16, .num_of_counters = sizeof(gfx9_sq_counter_ids) / sizeof(*gfx9_sq_counter_ids), .counter_ids = gfx9_sq_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SX] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx9_sx_counter_ids) / sizeof(*gfx9_sx_counter_ids), .counter_ids = gfx9_sx_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TA] = { .num_of_slots = 6, .num_of_counters = sizeof(gfx8_ta_counter_ids) / sizeof(*gfx8_ta_counter_ids), .counter_ids = gfx8_ta_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCA] = { .num_of_slots = 10, /* same as Fiji */ /* Greenland has the same TCA counter IDs with Fiji */ .num_of_counters = sizeof(gfx8_tca_counter_ids) / sizeof(*gfx8_tca_counter_ids), .counter_ids = gfx8_tca_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCC] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx8_tcc_counter_ids) / sizeof(*gfx8_tcc_counter_ids), .counter_ids = gfx8_tcc_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCP] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx9_tcp_counter_ids) / sizeof(*gfx9_tcp_counter_ids), .counter_ids = gfx9_tcp_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TD] = { .num_of_slots = 6, .num_of_counters = sizeof(gfx9_td_counter_ids) / sizeof(*gfx9_td_counter_ids), .counter_ids = gfx9_td_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__VGT] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx9_vgt_counter_ids) / sizeof(*gfx9_vgt_counter_ids), .counter_ids = gfx9_vgt_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__WD] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx9_wd_counter_ids) / sizeof(*gfx9_wd_counter_ids), .counter_ids = gfx9_wd_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, }; static struct perf_counter_block navi_blocks[PERFCOUNTER_BLOCKID__MAX] = { [PERFCOUNTER_BLOCKID__CB] = { .num_of_slots = 7, .num_of_counters = sizeof(gfx10_cb_counter_ids) / sizeof(*gfx10_cb_counter_ids), .counter_ids = gfx10_cb_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__CPF] = { .num_of_slots = 6, .num_of_counters = sizeof(gfx10_cpf_counter_ids) / sizeof(*gfx10_cpf_counter_ids), .counter_ids = gfx10_cpf_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__CPG] = { .num_of_slots = 6, .num_of_counters = sizeof(gfx10_cpg_counter_ids) / sizeof(*gfx10_cpg_counter_ids), .counter_ids = gfx10_cpg_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__DB] = { .num_of_slots = 12, .num_of_counters = sizeof(gfx10_db_counter_ids) / sizeof(*gfx10_db_counter_ids), .counter_ids = gfx10_db_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GDS] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx10_gds_counter_ids) / sizeof(*gfx10_gds_counter_ids), .counter_ids = gfx10_gds_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GRBM] = { .num_of_slots = 2, .num_of_counters = sizeof(gfx10_grbm_counter_ids) / sizeof(*gfx10_grbm_counter_ids), .counter_ids = gfx10_grbm_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__GRBMSE] = { .num_of_slots = 1, .num_of_counters = sizeof(gfx10_grbmse_counter_ids) / sizeof(*gfx10_grbmse_counter_ids), .counter_ids = gfx10_grbmse_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__PASC] = { .num_of_slots = 11, .num_of_counters = sizeof(gfx10_pasc_counter_ids) / sizeof(*gfx10_pasc_counter_ids), .counter_ids = gfx10_pasc_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__PASU] = { .num_of_slots = 16, .num_of_counters = sizeof(gfx10_pasu_counter_ids) / sizeof(*gfx10_pasu_counter_ids), .counter_ids = gfx10_pasu_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SPI] = { .num_of_slots = 18, .num_of_counters = sizeof(gfx10_spi_counter_ids) / sizeof(*gfx10_spi_counter_ids), .counter_ids = gfx10_spi_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SQ] = { .num_of_slots = 16, .num_of_counters = sizeof(gfx10_sq_counter_ids) / sizeof(*gfx10_sq_counter_ids), .counter_ids = gfx10_sq_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__SX] = { .num_of_slots = 4, .num_of_counters = sizeof(gfx10_sx_counter_ids) / sizeof(*gfx10_sx_counter_ids), .counter_ids = gfx10_sx_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TA] = { .num_of_slots = 5, .num_of_counters = sizeof(gfx10_ta_counter_ids) / sizeof(*gfx10_ta_counter_ids), .counter_ids = gfx10_ta_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TCP] = { .num_of_slots = 10, .num_of_counters = sizeof(gfx10_tcp_counter_ids) / sizeof(*gfx10_tcp_counter_ids), .counter_ids = gfx10_tcp_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, [PERFCOUNTER_BLOCKID__TD] = { .num_of_slots = 5, .num_of_counters = sizeof(gfx10_td_counter_ids) / sizeof(*gfx10_td_counter_ids), .counter_ids = gfx10_td_counter_ids, .counter_size_in_bits = 64, .counter_mask = BITMASK(64) }, }; /* Current APUs only have one IOMMU. If NUMA is introduced to APUs, we'll need * to expand the struct here to an array. */ static struct perf_counter_block iommu_block; uint32_t pmc_table_get_max_concurrent(int block_id) { switch (block_id) { case PERFCOUNTER_BLOCKID__IOMMUV2: return iommu_block.num_of_slots; default: return 0; } } static HSAKMT_STATUS alloc_pmc_blocks_iommu(void) { DIR *dir; struct dirent *dent; const char *sysfs_amdiommu_event_path = "/sys/bus/event_source/devices/amd_iommu_0/events"; /* Counter source in IOMMU's Counter Bank Addressing register is 8 bits, * so the biggest counter number/id possible is 0xff. */ const int max_counter_id = 0xff; char path[256]; const int len = sizeof(path); FILE *file; int num; char counter_id[max_counter_id + 1]; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; uint32_t *ptr; struct perf_counter_block *block = &iommu_block; memset(block, 0, sizeof(struct perf_counter_block)); dir = opendir(sysfs_amdiommu_event_path); if (!dir) { /* Before kernel 4.12, amd_iommu is the path */ sysfs_amdiommu_event_path = "/sys/bus/event_source/devices/amd_iommu/events"; dir = opendir(sysfs_amdiommu_event_path); if (!dir) goto out; } memset(counter_id, 0, max_counter_id + 1); while ((dent = readdir(dir))) { if (!strcmp(dent->d_name, ".") || !strcmp(dent->d_name, "..")) continue; if (snprintf(path, len, "%s/%s", sysfs_amdiommu_event_path, dent->d_name) >= len) { pr_err("Increase path length.\n"); ret = HSAKMT_STATUS_NO_MEMORY; goto out; } file = fopen(path, "r"); if (!file) { ret = HSAKMT_STATUS_ERROR; goto out; } if (fscanf(file, "csource=0x%x", &num) != 1) { ret = HSAKMT_STATUS_ERROR; fclose(file); goto out; } if (num > max_counter_id) /* This should never happen. If it does, check IOMMU driver. */ pr_err("max_counter_id %d is set too small.\n", max_counter_id); else { counter_id[num] = 1; ++block->num_of_counters; } fclose(file); } block->counter_ids = malloc(sizeof(uint32_t) * block->num_of_counters); if (!block->counter_ids) { ret = HSAKMT_STATUS_NO_MEMORY; goto out; } ptr = block->counter_ids; for (num = 0; num < (max_counter_id + 1); num++) { if (counter_id[num]) { ptr[0] = num; ++ptr; } } if (snprintf(path, len, "%s/%d/%s", "/sys/devices/virtual/kfd/kfd/topology/nodes", 0, /* IOMMU is in node 0. Change this if NUMA is introduced to APU. */ "perf/iommu/max_concurrent") >= len) { pr_err("Increase path length\n"); ret = HSAKMT_STATUS_NO_MEMORY; goto out; }; file = fopen(path, "r"); if (!file) { ret = HSAKMT_STATUS_ERROR; goto out; } if (fscanf(file, "%d", &block->num_of_slots) != 1) ret = HSAKMT_STATUS_ERROR; fclose(file); out: if (dir) closedir(dir); return ret; } HSAKMT_STATUS alloc_pmc_blocks(void) { return alloc_pmc_blocks_iommu(); } void free_pmc_blocks(void) { if (iommu_block.counter_ids) free(iommu_block.counter_ids); iommu_block.counter_ids = NULL; iommu_block.num_of_counters = 0; } HSAKMT_STATUS get_block_properties(uint32_t node_id, enum perf_block_id block_id, struct perf_counter_block *block) { uint32_t gfxv = get_gfxv_by_node_id(node_id); uint16_t dev_id = get_device_id_by_node_id(node_id); if (block_id > PERFCOUNTER_BLOCKID__MAX || block_id < PERFCOUNTER_BLOCKID__FIRST) return HSAKMT_STATUS_INVALID_PARAMETER; if (block_id == PERFCOUNTER_BLOCKID__IOMMUV2) { *block = iommu_block; return HSAKMT_STATUS_SUCCESS; } /* Major GFX Version */ switch (gfxv >> 16) { case 7: if (gfxv == GFX_VERSION_KAVERI) *block = kaveri_blocks[block_id]; else *block = hawaii_blocks[block_id]; break; case 8: if (gfxv == GFX_VERSION_TONGA) return HSAKMT_STATUS_INVALID_PARAMETER; else if (gfxv == GFX_VERSION_CARRIZO) *block = carrizo_blocks[block_id]; else { /* * Fiji/Polaris/VegaM cards are of the same GFXIP Engine Version (8.0.3). * Only way to differentiate b/t Fiji and Polaris/VegaM is via DID. */ if (dev_id == 0x7300 || dev_id == 0x730F) *block = fiji_blocks[block_id]; else *block = polaris_blocks[block_id]; } break; case 9: *block = vega_blocks[block_id]; break; case 10: *block = navi_blocks[block_id]; break; default: return HSAKMT_STATUS_INVALID_PARAMETER; } return HSAKMT_STATUS_SUCCESS; } ROCT-Thunk-Interface-rocm-5.7.0/src/pmc_table.h000066400000000000000000000047311446477712600211320ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef PMC_TABLE_H #define PMC_TABLE_H #include "libhsakmt.h" enum perf_block_id { PERFCOUNTER_BLOCKID__FIRST = 0, /* non-privileged */ PERFCOUNTER_BLOCKID__CB = PERFCOUNTER_BLOCKID__FIRST, PERFCOUNTER_BLOCKID__CPC, PERFCOUNTER_BLOCKID__CPF, PERFCOUNTER_BLOCKID__CPG, PERFCOUNTER_BLOCKID__DB, PERFCOUNTER_BLOCKID__GDS, PERFCOUNTER_BLOCKID__GRBM, PERFCOUNTER_BLOCKID__GRBMSE, PERFCOUNTER_BLOCKID__IA, PERFCOUNTER_BLOCKID__MC, PERFCOUNTER_BLOCKID__PASC, PERFCOUNTER_BLOCKID__PASU, PERFCOUNTER_BLOCKID__SPI, PERFCOUNTER_BLOCKID__SRBM, PERFCOUNTER_BLOCKID__SQ, PERFCOUNTER_BLOCKID__SX, PERFCOUNTER_BLOCKID__TA, PERFCOUNTER_BLOCKID__TCA, PERFCOUNTER_BLOCKID__TCC, PERFCOUNTER_BLOCKID__TCP, PERFCOUNTER_BLOCKID__TCS, PERFCOUNTER_BLOCKID__TD, PERFCOUNTER_BLOCKID__VGT, PERFCOUNTER_BLOCKID__WD, /* privileged */ PERFCOUNTER_BLOCKID__IOMMUV2, PERFCOUNTER_BLOCKID__MAX }; struct perf_counter_block { uint32_t num_of_slots; uint32_t num_of_counters; uint32_t *counter_ids; uint32_t counter_size_in_bits; uint64_t counter_mask; }; HSAKMT_STATUS alloc_pmc_blocks(void); void free_pmc_blocks(void); uint32_t pmc_table_get_max_concurrent(int block_id); HSAKMT_STATUS get_block_properties(uint32_t node_id, enum perf_block_id block_id, struct perf_counter_block *block); #endif // PMC_TABLE_H ROCT-Thunk-Interface-rocm-5.7.0/src/queues.c000066400000000000000000000573451446477712600205170ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "libhsakmt.h" #include "fmm.h" #include "linux/kfd_ioctl.h" #include #include #include #include #include #include #include #include #include /* 1024 doorbells, 4 or 8 bytes each doorbell depending on ASIC generation */ #define DOORBELL_SIZE(gfxv) (((gfxv) >= 0x90000) ? 8 : 4) #define DOORBELLS_PAGE_SIZE(ds) (1024 * (ds)) #define WG_CONTEXT_DATA_SIZE_PER_CU(gfxv) \ (get_vgpr_size_per_cu(gfxv) + SGPR_SIZE_PER_CU + \ LDS_SIZE_PER_CU + HWREG_SIZE_PER_CU) #define CNTL_STACK_BYTES_PER_WAVE(gfxv) \ ((gfxv) >= GFX_VERSION_NAVI10 ? 12 : 8) #define LDS_SIZE_PER_CU 0x10000 #define HWREG_SIZE_PER_CU 0x1000 #define DEBUGGER_BYTES_ALIGN 64 #define DEBUGGER_BYTES_PER_WAVE 32 struct queue { uint32_t queue_id; uint64_t wptr; uint64_t rptr; void *eop_buffer; void *ctx_save_restore; uint32_t ctx_save_restore_size; uint32_t ctl_stack_size; uint32_t debug_memory_size; uint32_t eop_buffer_size; uint32_t total_mem_alloc_size; uint32_t gfxv; bool use_ats; bool unified_ctx_save_restore; /* This queue structure is allocated from GPU with page aligned size * but only small bytes are used. We use the extra space in the end for * cu_mask bits array. */ uint32_t cu_mask_count; /* in bits */ uint32_t cu_mask[0]; }; struct process_doorbells { bool use_gpuvm; uint32_t size; void *mapping; pthread_mutex_t mutex; }; static unsigned int num_doorbells; static struct process_doorbells *doorbells; uint32_t get_vgpr_size_per_cu(uint32_t gfxv) { uint32_t vgpr_size = 0x40000; if ((gfxv & ~(0xff)) == GFX_VERSION_AQUA_VANJARAM || gfxv == GFX_VERSION_ALDEBARAN || gfxv == GFX_VERSION_ARCTURUS) vgpr_size = 0x80000; else if (gfxv == GFX_VERSION_PLUM_BONITO || gfxv == GFX_VERSION_WHEAT_NAS) vgpr_size = 0x60000; return vgpr_size; } HSAKMT_STATUS init_process_doorbells(unsigned int NumNodes) { unsigned int i; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; /* doorbells[] is accessed using Topology NodeId. This means doorbells[0], * which corresponds to CPU only Node, might not be used */ doorbells = malloc(NumNodes * sizeof(struct process_doorbells)); if (!doorbells) return HSAKMT_STATUS_NO_MEMORY; for (i = 0; i < NumNodes; i++) { doorbells[i].use_gpuvm = false; doorbells[i].size = 0; doorbells[i].mapping = NULL; pthread_mutex_init(&doorbells[i].mutex, NULL); } num_doorbells = NumNodes; return ret; } static void get_doorbell_map_info(uint32_t node_id, struct process_doorbells *doorbell) { /* * GPUVM doorbell on Tonga requires a workaround for VM TLB ACTIVE bit * lookup bug. Remove ASIC check when this is implemented in amdgpu. */ uint32_t gfxv = get_gfxv_by_node_id(node_id); doorbell->use_gpuvm = (is_dgpu && gfxv != GFX_VERSION_TONGA); doorbell->size = DOORBELLS_PAGE_SIZE(DOORBELL_SIZE(gfxv)); return; } void destroy_process_doorbells(void) { unsigned int i; if (!doorbells) return; for (i = 0; i < num_doorbells; i++) { if (!doorbells[i].size) continue; if (doorbells[i].use_gpuvm) { fmm_unmap_from_gpu(doorbells[i].mapping); fmm_release(doorbells[i].mapping); } else munmap(doorbells[i].mapping, doorbells[i].size); } free(doorbells); doorbells = NULL; num_doorbells = 0; } /* This is a special funcion that should be called only from the child process * after a fork(). This will clear doorbells duplicated from the parent. */ void clear_process_doorbells(void) { unsigned int i; if (!doorbells) return; for (i = 0; i < num_doorbells; i++) { if (!doorbells[i].size) continue; if (!doorbells[i].use_gpuvm) munmap(doorbells[i].mapping, doorbells[i].size); } free(doorbells); doorbells = NULL; num_doorbells = 0; } static HSAKMT_STATUS map_doorbell_apu(HSAuint32 NodeId, HSAuint32 gpu_id, HSAuint64 doorbell_mmap_offset) { void *ptr; ptr = mmap(0, doorbells[NodeId].size, PROT_READ|PROT_WRITE, MAP_SHARED, kfd_fd, doorbell_mmap_offset); if (ptr == MAP_FAILED) return HSAKMT_STATUS_ERROR; doorbells[NodeId].mapping = ptr; return HSAKMT_STATUS_SUCCESS; } static HSAKMT_STATUS map_doorbell_dgpu(HSAuint32 NodeId, HSAuint32 gpu_id, HSAuint64 doorbell_mmap_offset) { void *ptr; ptr = fmm_allocate_doorbell(gpu_id, doorbells[NodeId].size, doorbell_mmap_offset); if (!ptr) return HSAKMT_STATUS_ERROR; /* map for GPU access */ if (fmm_map_to_gpu(ptr, doorbells[NodeId].size, NULL)) { fmm_release(ptr); return HSAKMT_STATUS_ERROR; } doorbells[NodeId].mapping = ptr; return HSAKMT_STATUS_SUCCESS; } static HSAKMT_STATUS map_doorbell(HSAuint32 NodeId, HSAuint32 gpu_id, HSAuint64 doorbell_mmap_offset) { HSAKMT_STATUS status = HSAKMT_STATUS_SUCCESS; pthread_mutex_lock(&doorbells[NodeId].mutex); if (doorbells[NodeId].size) { pthread_mutex_unlock(&doorbells[NodeId].mutex); return HSAKMT_STATUS_SUCCESS; } get_doorbell_map_info(NodeId, &doorbells[NodeId]); if (doorbells[NodeId].use_gpuvm) { status = map_doorbell_dgpu(NodeId, gpu_id, doorbell_mmap_offset); if (status != HSAKMT_STATUS_SUCCESS) { /* Fall back to the old method if KFD doesn't * support doorbells in GPUVM */ doorbells[NodeId].use_gpuvm = false; status = map_doorbell_apu(NodeId, gpu_id, doorbell_mmap_offset); } } else status = map_doorbell_apu(NodeId, gpu_id, doorbell_mmap_offset); if (status != HSAKMT_STATUS_SUCCESS) doorbells[NodeId].size = 0; pthread_mutex_unlock(&doorbells[NodeId].mutex); return status; } static void *allocate_exec_aligned_memory_cpu(uint32_t size) { void *ptr; /* mmap will return a pointer with alignment equal to * sysconf(_SC_PAGESIZE). * * MAP_ANONYMOUS initializes the memory to zero. */ ptr = mmap(NULL, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); if (ptr == MAP_FAILED) return NULL; return ptr; } /* The bool return indicate whether the queue needs a context-save-restore area*/ static bool update_ctx_save_restore_size(uint32_t nodeid, struct queue *q) { HsaNodeProperties node; if (q->gfxv < GFX_VERSION_CARRIZO) return false; if (hsaKmtGetNodeProperties(nodeid, &node)) return false; if (node.NumFComputeCores && node.NumSIMDPerCU) { uint32_t ctl_stack_size, wg_data_size; uint32_t cu_num = node.NumFComputeCores / node.NumSIMDPerCU / node.NumXcc; uint32_t wave_num = (q->gfxv < GFX_VERSION_NAVI10) ? MIN(cu_num * 40, node.NumShaderBanks / node.NumArrays * 512) : cu_num * 32; ctl_stack_size = wave_num * CNTL_STACK_BYTES_PER_WAVE(q->gfxv) + 8; wg_data_size = cu_num * WG_CONTEXT_DATA_SIZE_PER_CU(q->gfxv); q->ctl_stack_size = PAGE_ALIGN_UP(sizeof(HsaUserContextSaveAreaHeader) + ctl_stack_size); if ((q->gfxv & 0x3f0000) == 0xA0000) { /* HW design limits control stack size to 0x7000. * This is insufficient for theoretical PM4 cases * but sufficient for AQL, limited by SPI events. */ q->ctl_stack_size = MIN(q->ctl_stack_size, 0x7000); } q->debug_memory_size = ALIGN_UP(wave_num * DEBUGGER_BYTES_PER_WAVE, DEBUGGER_BYTES_ALIGN); q->ctx_save_restore_size = q->ctl_stack_size + PAGE_ALIGN_UP(wg_data_size); return true; } return false; } void *allocate_exec_aligned_memory_gpu(uint32_t size, uint32_t align, uint32_t NodeId, bool nonPaged, bool DeviceLocal, bool Uncached) { void *mem; HSAuint64 gpu_va; HsaMemFlags flags; HSAKMT_STATUS ret; HSAuint32 cpu_id = 0; flags.Value = 0; flags.ui32.HostAccess = !DeviceLocal; flags.ui32.ExecuteAccess = 1; flags.ui32.NonPaged = nonPaged; flags.ui32.PageSize = HSA_PAGE_SIZE_4KB; flags.ui32.CoarseGrain = DeviceLocal; flags.ui32.Uncached = Uncached; /* Get the closest cpu_id to GPU NodeId for system memory allocation * nonPaged=1 system memory allocation uses GTT path */ if (!DeviceLocal && !nonPaged) { cpu_id = get_direct_link_cpu(NodeId); if (cpu_id == INVALID_NODEID) { flags.ui32.NoNUMABind = 1; cpu_id = 0; } } size = ALIGN_UP(size, align); ret = hsaKmtAllocMemory(DeviceLocal ? NodeId : cpu_id, size, flags, &mem); if (ret != HSAKMT_STATUS_SUCCESS) return NULL; if (NodeId != 0) { uint32_t nodes_array[1] = {NodeId}; if (hsaKmtRegisterMemoryToNodes(mem, size, 1, nodes_array) != HSAKMT_STATUS_SUCCESS) { hsaKmtFreeMemory(mem, size); return NULL; } } if (hsaKmtMapMemoryToGPU(mem, size, &gpu_va) != HSAKMT_STATUS_SUCCESS) { hsaKmtFreeMemory(mem, size); return NULL; } return mem; } void free_exec_aligned_memory_gpu(void *addr, uint32_t size, uint32_t align) { size = ALIGN_UP(size, align); if (hsaKmtUnmapMemoryToGPU(addr) == HSAKMT_STATUS_SUCCESS) hsaKmtFreeMemory(addr, size); } /* * Allocates memory aligned to sysconf(_SC_PAGESIZE) */ static void *allocate_exec_aligned_memory(uint32_t size, bool use_ats, uint32_t NodeId, bool nonPaged, bool DeviceLocal, bool Uncached) { if (!use_ats) return allocate_exec_aligned_memory_gpu(size, PAGE_SIZE, NodeId, nonPaged, DeviceLocal, Uncached); return allocate_exec_aligned_memory_cpu(size); } static void free_exec_aligned_memory(void *addr, uint32_t size, uint32_t align, bool use_ats) { if (!use_ats) free_exec_aligned_memory_gpu(addr, size, align); else munmap(addr, size); } static HSAKMT_STATUS register_svm_range(void *mem, uint32_t size, uint32_t gpuNode, uint32_t prefetchNode, uint32_t preferredNode, bool alwaysMapped) { HSA_SVM_ATTRIBUTE *attrs; HSAuint64 s_attr; HSAuint32 nattr; HSAuint32 flags; flags = HSA_SVM_FLAG_HOST_ACCESS | HSA_SVM_FLAG_GPU_EXEC; if (alwaysMapped) { CHECK_KFD_MINOR_VERSION(11); flags |= HSA_SVM_FLAG_GPU_ALWAYS_MAPPED; } nattr = 5; s_attr = sizeof(*attrs) * nattr; attrs = (HSA_SVM_ATTRIBUTE *)alloca(s_attr); attrs[0].type = HSA_SVM_ATTR_PREFETCH_LOC; attrs[0].value = prefetchNode; attrs[1].type = HSA_SVM_ATTR_PREFERRED_LOC; attrs[1].value = preferredNode; attrs[2].type = HSA_SVM_ATTR_CLR_FLAGS; attrs[2].value = ~flags; attrs[3].type = HSA_SVM_ATTR_SET_FLAGS; attrs[3].value = flags; attrs[4].type = HSA_SVM_ATTR_ACCESS; attrs[4].value = gpuNode; return hsaKmtSVMSetAttr(mem, size, nattr, attrs); } static void free_queue(struct queue *q) { if (q->eop_buffer) free_exec_aligned_memory(q->eop_buffer, q->eop_buffer_size, PAGE_SIZE, q->use_ats); if (q->unified_ctx_save_restore) munmap(q->ctx_save_restore, q->total_mem_alloc_size); else if (q->ctx_save_restore) free_exec_aligned_memory(q->ctx_save_restore, q->total_mem_alloc_size, PAGE_SIZE, q->use_ats); free_exec_aligned_memory((void *)q, sizeof(*q), PAGE_SIZE, q->use_ats); } static inline void fill_cwsr_header(struct queue *q, void *addr, HsaEvent *Event, volatile HSAint64 *ErrPayload, HSAuint32 NumXcc) { uint32_t i; HsaUserContextSaveAreaHeader *header; for (i = 0; i < NumXcc; i++) { header = (HsaUserContextSaveAreaHeader *) ((uintptr_t)addr + (i * q->ctx_save_restore_size)); header->ErrorEventId = 0; if (Event) header->ErrorEventId = Event->EventId; header->ErrorReason = ErrPayload; header->DebugOffset = (NumXcc - i) * q->ctx_save_restore_size; header->DebugSize = q->debug_memory_size * NumXcc; } } static int handle_concrete_asic(struct queue *q, struct kfd_ioctl_create_queue_args *args, uint32_t NodeId, HsaEvent *Event, volatile HSAint64 *ErrPayload) { bool ret; if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA || args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI) return HSAKMT_STATUS_SUCCESS; if (q->eop_buffer_size > 0) { q->eop_buffer = allocate_exec_aligned_memory(q->eop_buffer_size, q->use_ats, NodeId, true, true, /* Unused for VRAM */false); if (!q->eop_buffer) return HSAKMT_STATUS_NO_MEMORY; args->eop_buffer_address = (uintptr_t)q->eop_buffer; args->eop_buffer_size = q->eop_buffer_size; } ret = update_ctx_save_restore_size(NodeId, q); if (ret) { HsaNodeProperties node; bool svm_api; if (hsaKmtGetNodeProperties(NodeId, &node)) return HSAKMT_STATUS_ERROR; args->ctx_save_restore_size = q->ctx_save_restore_size; args->ctl_stack_size = q->ctl_stack_size; /* Total memory to be allocated is = * (Control Stack size + WG size + * Debug memory area size) * num_xcc */ q->total_mem_alloc_size = (q->ctx_save_restore_size + q->debug_memory_size) * node.NumXcc; svm_api = node.Capability.ui32.SVMAPISupported && (node.EngineId.ui32.Major < 11 || node.DeviceId == 0x7461); /* Allocate unified memory for context save restore * area on dGPU. */ if (!q->use_ats && svm_api) { uint32_t size = PAGE_ALIGN_UP(q->total_mem_alloc_size); void *addr; HSAKMT_STATUS r = HSAKMT_STATUS_ERROR; addr = mmap_allocate_aligned(PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, size, GPU_HUGE_PAGE_SIZE, 0, 0, (void *)LONG_MAX); if (!addr) { pr_err("mmap failed to alloc ctx area size 0x%x: %s\n", size, strerror(errno)); } else { /* * To avoid fork child process COW MMU notifier * callback evict parent process queues. */ if (madvise(addr, size, MADV_DONTFORK)) pr_err("madvise failed -%d\n", errno); fill_cwsr_header(q, addr, Event, ErrPayload, node.NumXcc); r = register_svm_range(addr, size, NodeId, NodeId, 0, true); if (r == HSAKMT_STATUS_SUCCESS) { q->ctx_save_restore = addr; q->unified_ctx_save_restore = true; } else { munmap(addr, size); } } } if (!q->unified_ctx_save_restore) { q->ctx_save_restore = allocate_exec_aligned_memory( q->total_mem_alloc_size, q->use_ats, NodeId, false, false, false); if (!q->ctx_save_restore) return HSAKMT_STATUS_NO_MEMORY; fill_cwsr_header(q, q->ctx_save_restore, Event, ErrPayload, node.NumXcc); } args->ctx_save_restore_address = (uintptr_t)q->ctx_save_restore; } return HSAKMT_STATUS_SUCCESS; } /* A map to translate thunk queue priority (-3 to +3) * to KFD queue priority (0 to 15) * Indexed by thunk_queue_priority+3 */ static uint32_t priority_map[] = {0, 3, 5, 7, 9, 11, 15}; HSAKMT_STATUS HSAKMTAPI hsaKmtCreateQueue(HSAuint32 NodeId, HSA_QUEUE_TYPE Type, HSAuint32 QueuePercentage, HSA_QUEUE_PRIORITY Priority, void *QueueAddress, HSAuint64 QueueSizeInBytes, HsaEvent *Event, HsaQueueResource *QueueResource) { HSAKMT_STATUS result; uint32_t gpu_id; uint64_t doorbell_mmap_offset; unsigned int doorbell_offset; int err; HsaNodeProperties props; uint32_t cu_num, i; CHECK_KFD_OPEN(); if (Priority < HSA_QUEUE_PRIORITY_MINIMUM || Priority > HSA_QUEUE_PRIORITY_MAXIMUM) return HSAKMT_STATUS_INVALID_PARAMETER; result = validate_nodeid(NodeId, &gpu_id); if (result != HSAKMT_STATUS_SUCCESS) return result; struct queue *q = allocate_exec_aligned_memory(sizeof(*q), false, NodeId, true, false, true); if (!q) return HSAKMT_STATUS_NO_MEMORY; memset(q, 0, sizeof(*q)); q->gfxv = get_gfxv_by_node_id(NodeId); q->use_ats = false; if (q->gfxv == GFX_VERSION_TONGA) q->eop_buffer_size = TONGA_PAGE_SIZE; else if ((q->gfxv & ~(0xff)) == GFX_VERSION_AQUA_VANJARAM) q->eop_buffer_size = ((Type == HSA_QUEUE_COMPUTE) ? 4096 : 0); else if (q->gfxv >= 0x80000) q->eop_buffer_size = 4096; /* By default, CUs are all turned on. Initialize cu_mask to '1 * for all CU bits. */ if (hsaKmtGetNodeProperties(NodeId, &props)) q->cu_mask_count = 0; else { cu_num = props.NumFComputeCores / props.NumSIMDPerCU; /* cu_mask_count counts bits. It must be multiple of 32 */ q->cu_mask_count = ALIGN_UP_32(cu_num, 32); for (i = 0; i < cu_num; i++) q->cu_mask[i/32] |= (1 << (i % 32)); } struct kfd_ioctl_create_queue_args args = {0}; args.gpu_id = gpu_id; switch (Type) { case HSA_QUEUE_COMPUTE: args.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE; break; case HSA_QUEUE_SDMA: args.queue_type = KFD_IOC_QUEUE_TYPE_SDMA; break; case HSA_QUEUE_SDMA_XGMI: args.queue_type = KFD_IOC_QUEUE_TYPE_SDMA_XGMI; break; case HSA_QUEUE_COMPUTE_AQL: args.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; break; default: return HSAKMT_STATUS_INVALID_PARAMETER; } if (Type != HSA_QUEUE_COMPUTE_AQL) { QueueResource->QueueRptrValue = (uintptr_t)&q->rptr; QueueResource->QueueWptrValue = (uintptr_t)&q->wptr; } err = handle_concrete_asic(q, &args, NodeId, Event, QueueResource->ErrorReason); if (err != HSAKMT_STATUS_SUCCESS) { free_queue(q); return err; } args.read_pointer_address = QueueResource->QueueRptrValue; args.write_pointer_address = QueueResource->QueueWptrValue; args.ring_base_address = (uintptr_t)QueueAddress; args.ring_size = QueueSizeInBytes; args.queue_percentage = QueuePercentage; args.queue_priority = priority_map[Priority+3]; err = kmtIoctl(kfd_fd, AMDKFD_IOC_CREATE_QUEUE, &args); if (err == -1) { free_queue(q); return HSAKMT_STATUS_ERROR; } q->queue_id = args.queue_id; if (IS_SOC15(q->gfxv)) { HSAuint64 mask = DOORBELLS_PAGE_SIZE(DOORBELL_SIZE(q->gfxv)) - 1; /* On SOC15 chips, the doorbell offset within the * doorbell page is included in the doorbell offset * returned by KFD. This allows CP queue doorbells to be * allocated dynamically (while SDMA queue doorbells fixed) * rather than based on the its process queue ID. */ doorbell_mmap_offset = args.doorbell_offset & ~mask; doorbell_offset = args.doorbell_offset & mask; } else { /* On older chips, the doorbell offset within the * doorbell page is based on the queue ID. */ doorbell_mmap_offset = args.doorbell_offset; doorbell_offset = q->queue_id * DOORBELL_SIZE(q->gfxv); } err = map_doorbell(NodeId, gpu_id, doorbell_mmap_offset); if (err != HSAKMT_STATUS_SUCCESS) { hsaKmtDestroyQueue(q->queue_id); return HSAKMT_STATUS_ERROR; } QueueResource->QueueId = PORT_VPTR_TO_UINT64(q); QueueResource->Queue_DoorBell = VOID_PTR_ADD(doorbells[NodeId].mapping, doorbell_offset); return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtUpdateQueue(HSA_QUEUEID QueueId, HSAuint32 QueuePercentage, HSA_QUEUE_PRIORITY Priority, void *QueueAddress, HSAuint64 QueueSize, HsaEvent *Event) { struct kfd_ioctl_update_queue_args arg = {0}; struct queue *q = PORT_UINT64_TO_VPTR(QueueId); CHECK_KFD_OPEN(); if (Priority < HSA_QUEUE_PRIORITY_MINIMUM || Priority > HSA_QUEUE_PRIORITY_MAXIMUM) return HSAKMT_STATUS_INVALID_PARAMETER; if (!q) return HSAKMT_STATUS_INVALID_PARAMETER; arg.queue_id = (HSAuint32)q->queue_id; arg.ring_base_address = (uintptr_t)QueueAddress; arg.ring_size = QueueSize; arg.queue_percentage = QueuePercentage; arg.queue_priority = priority_map[Priority+3]; int err = kmtIoctl(kfd_fd, AMDKFD_IOC_UPDATE_QUEUE, &arg); if (err == -1) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtDestroyQueue(HSA_QUEUEID QueueId) { CHECK_KFD_OPEN(); struct queue *q = PORT_UINT64_TO_VPTR(QueueId); struct kfd_ioctl_destroy_queue_args args = {0}; if (!q) return HSAKMT_STATUS_INVALID_PARAMETER; args.queue_id = q->queue_id; int err = kmtIoctl(kfd_fd, AMDKFD_IOC_DESTROY_QUEUE, &args); if (err == -1) { pr_err("Failed to destroy queue: %s\n", strerror(errno)); return HSAKMT_STATUS_ERROR; } free_queue(q); return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtSetQueueCUMask(HSA_QUEUEID QueueId, HSAuint32 CUMaskCount, HSAuint32 *QueueCUMask) { struct queue *q = PORT_UINT64_TO_VPTR(QueueId); struct kfd_ioctl_set_cu_mask_args args = {0}; CHECK_KFD_OPEN(); if (CUMaskCount == 0 || !QueueCUMask || ((CUMaskCount % 32) != 0)) return HSAKMT_STATUS_INVALID_PARAMETER; args.queue_id = q->queue_id; args.num_cu_mask = CUMaskCount; args.cu_mask_ptr = (uintptr_t)QueueCUMask; int err = kmtIoctl(kfd_fd, AMDKFD_IOC_SET_CU_MASK, &args); if (err == -1) return HSAKMT_STATUS_ERROR; memcpy(q->cu_mask, QueueCUMask, CUMaskCount / 8); q->cu_mask_count = CUMaskCount; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtGetQueueInfo( HSA_QUEUEID QueueId, HsaQueueInfo *QueueInfo ) { struct queue *q = PORT_UINT64_TO_VPTR(QueueId); struct kfd_ioctl_get_queue_wave_state_args args = {0}; CHECK_KFD_OPEN(); if (QueueInfo == NULL || q == NULL) return HSAKMT_STATUS_INVALID_PARAMETER; if (q->ctx_save_restore == NULL) return HSAKMT_STATUS_ERROR; args.queue_id = q->queue_id; args.ctl_stack_address = (uintptr_t)q->ctx_save_restore; if (kmtIoctl(kfd_fd, AMDKFD_IOC_GET_QUEUE_WAVE_STATE, &args) < 0) return HSAKMT_STATUS_ERROR; QueueInfo->ControlStackTop = (void *)(args.ctl_stack_address + q->ctl_stack_size - args.ctl_stack_used_size); QueueInfo->UserContextSaveArea = (void *) (args.ctl_stack_address + q->ctl_stack_size); QueueInfo->SaveAreaSizeInBytes = args.save_area_used_size; QueueInfo->ControlStackUsedInBytes = args.ctl_stack_used_size; QueueInfo->NumCUAssigned = q->cu_mask_count; QueueInfo->CUMaskInfo = q->cu_mask; QueueInfo->QueueDetailError = 0; QueueInfo->QueueTypeExtended = 0; QueueInfo->SaveAreaHeader = q->ctx_save_restore; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtSetTrapHandler(HSAuint32 Node, void *TrapHandlerBaseAddress, HSAuint64 TrapHandlerSizeInBytes, void *TrapBufferBaseAddress, HSAuint64 TrapBufferSizeInBytes) { struct kfd_ioctl_set_trap_handler_args args = {0}; HSAKMT_STATUS result; uint32_t gpu_id; CHECK_KFD_OPEN(); result = validate_nodeid(Node, &gpu_id); if (result != HSAKMT_STATUS_SUCCESS) return result; args.gpu_id = gpu_id; args.tba_addr = (uintptr_t)TrapHandlerBaseAddress; args.tma_addr = (uintptr_t)TrapBufferBaseAddress; int err = kmtIoctl(kfd_fd, AMDKFD_IOC_SET_TRAP_HANDLER, &args); return (err == -1) ? HSAKMT_STATUS_ERROR : HSAKMT_STATUS_SUCCESS; } uint32_t *convert_queue_ids(HSAuint32 NumQueues, HSA_QUEUEID *Queues) { uint32_t *queue_ids_ptr; unsigned int i; queue_ids_ptr = malloc(NumQueues * sizeof(uint32_t)); if (!queue_ids_ptr) return NULL; for (i = 0; i < NumQueues; i++) { struct queue *q = PORT_UINT64_TO_VPTR(Queues[i]); queue_ids_ptr[i] = q->queue_id; } return queue_ids_ptr; } HSAKMT_STATUS HSAKMTAPI hsaKmtAllocQueueGWS( HSA_QUEUEID QueueId, HSAuint32 nGWS, HSAuint32 *firstGWS) { struct kfd_ioctl_alloc_queue_gws_args args = {0}; struct queue *q = PORT_UINT64_TO_VPTR(QueueId); CHECK_KFD_OPEN(); args.queue_id = (HSAuint32)q->queue_id; args.num_gws = nGWS; int err = kmtIoctl(kfd_fd, AMDKFD_IOC_ALLOC_QUEUE_GWS, &args); if (!err && firstGWS) *firstGWS = args.first_gws; if (!err) return HSAKMT_STATUS_SUCCESS; else if (errno == EINVAL) return HSAKMT_STATUS_INVALID_PARAMETER; else if (errno == EBUSY) return HSAKMT_STATUS_OUT_OF_RESOURCES; else if (errno == ENODEV) return HSAKMT_STATUS_NOT_SUPPORTED; else return HSAKMT_STATUS_ERROR; } ROCT-Thunk-Interface-rocm-5.7.0/src/rbtree.c000066400000000000000000000175071446477712600204670ustar00rootroot00000000000000/* * Copyright (C) 2002-2018 Igor Sysoev * Copyright (C) 2011-2018 Nginx, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "rbtree.h" static inline void rbtree_left_rotate(rbtree_node_t **root, rbtree_node_t *sentinel, rbtree_node_t *node); static inline void rbtree_right_rotate(rbtree_node_t **root, rbtree_node_t *sentinel, rbtree_node_t *node); static void rbtree_insert_value(rbtree_node_t *temp, rbtree_node_t *node, rbtree_node_t *sentinel) { rbtree_node_t **p; for ( ;; ) { p = rbtree_key_compare(LKP_ALL, &node->key, &temp->key) < 0 ? &temp->left : &temp->right; if (*p == sentinel) { break; } temp = *p; } *p = node; node->parent = temp; node->left = sentinel; node->right = sentinel; rbt_red(node); } void rbtree_insert(rbtree_t *tree, rbtree_node_t *node) { rbtree_node_t **root, *temp, *sentinel; /* a binary tree insert */ root = &tree->root; sentinel = &tree->sentinel; if (*root == sentinel) { node->parent = NULL; node->left = sentinel; node->right = sentinel; rbt_black(node); *root = node; return; } rbtree_insert_value(*root, node, sentinel); /* re-balance tree */ while (node != *root && rbt_is_red(node->parent)) { if (node->parent == node->parent->parent->left) { temp = node->parent->parent->right; if (rbt_is_red(temp)) { rbt_black(node->parent); rbt_black(temp); rbt_red(node->parent->parent); node = node->parent->parent; } else { if (node == node->parent->right) { node = node->parent; rbtree_left_rotate(root, sentinel, node); } rbt_black(node->parent); rbt_red(node->parent->parent); rbtree_right_rotate(root, sentinel, node->parent->parent); } } else { temp = node->parent->parent->left; if (rbt_is_red(temp)) { rbt_black(node->parent); rbt_black(temp); rbt_red(node->parent->parent); node = node->parent->parent; } else { if (node == node->parent->left) { node = node->parent; rbtree_right_rotate(root, sentinel, node); } rbt_black(node->parent); rbt_red(node->parent->parent); rbtree_left_rotate(root, sentinel, node->parent->parent); } } } rbt_black(*root); } void rbtree_delete(rbtree_t *tree, rbtree_node_t *node) { unsigned int red; rbtree_node_t **root, *sentinel, *subst, *temp, *w; /* a binary tree delete */ root = &tree->root; sentinel = &tree->sentinel; if (node->left == sentinel) { temp = node->right; subst = node; } else if (node->right == sentinel) { temp = node->left; subst = node; } else { subst = rbtree_min(node->right, sentinel); if (subst->left != sentinel) { temp = subst->left; } else { temp = subst->right; } } if (subst == *root) { *root = temp; rbt_black(temp); return; } red = rbt_is_red(subst); if (subst == subst->parent->left) { subst->parent->left = temp; } else { subst->parent->right = temp; } if (subst == node) { temp->parent = subst->parent; } else { if (subst->parent == node) { temp->parent = subst; } else { temp->parent = subst->parent; } subst->left = node->left; subst->right = node->right; subst->parent = node->parent; rbt_copy_color(subst, node); if (node == *root) { *root = subst; } else { if (node == node->parent->left) { node->parent->left = subst; } else { node->parent->right = subst; } } if (subst->left != sentinel) { subst->left->parent = subst; } if (subst->right != sentinel) { subst->right->parent = subst; } } if (red) { return; } /* a delete fixup */ while (temp != *root && rbt_is_black(temp)) { if (temp == temp->parent->left) { w = temp->parent->right; if (rbt_is_red(w)) { rbt_black(w); rbt_red(temp->parent); rbtree_left_rotate(root, sentinel, temp->parent); w = temp->parent->right; } if (rbt_is_black(w->left) && rbt_is_black(w->right)) { rbt_red(w); temp = temp->parent; } else { if (rbt_is_black(w->right)) { rbt_black(w->left); rbt_red(w); rbtree_right_rotate(root, sentinel, w); w = temp->parent->right; } rbt_copy_color(w, temp->parent); rbt_black(temp->parent); rbt_black(w->right); rbtree_left_rotate(root, sentinel, temp->parent); temp = *root; } } else { w = temp->parent->left; if (rbt_is_red(w)) { rbt_black(w); rbt_red(temp->parent); rbtree_right_rotate(root, sentinel, temp->parent); w = temp->parent->left; } if (rbt_is_black(w->left) && rbt_is_black(w->right)) { rbt_red(w); temp = temp->parent; } else { if (rbt_is_black(w->left)) { rbt_black(w->right); rbt_red(w); rbtree_left_rotate(root, sentinel, w); w = temp->parent->left; } rbt_copy_color(w, temp->parent); rbt_black(temp->parent); rbt_black(w->left); rbtree_right_rotate(root, sentinel, temp->parent); temp = *root; } } } rbt_black(temp); } static inline void rbtree_left_rotate(rbtree_node_t **root, rbtree_node_t *sentinel, rbtree_node_t *node) { rbtree_node_t *temp; temp = node->right; node->right = temp->left; if (temp->left != sentinel) { temp->left->parent = node; } temp->parent = node->parent; if (node == *root) { *root = temp; } else if (node == node->parent->left) { node->parent->left = temp; } else { node->parent->right = temp; } temp->left = node; node->parent = temp; } static inline void rbtree_right_rotate(rbtree_node_t **root, rbtree_node_t *sentinel, rbtree_node_t *node) { rbtree_node_t *temp; temp = node->left; node->left = temp->right; if (temp->right != sentinel) { temp->right->parent = node; } temp->parent = node->parent; if (node == *root) { *root = temp; } else if (node == node->parent->right) { node->parent->right = temp; } else { node->parent->left = temp; } temp->right = node; node->parent = temp; } rbtree_node_t * rbtree_next(rbtree_t *tree, rbtree_node_t *node) { rbtree_node_t *root, *sentinel, *parent; sentinel = &tree->sentinel; if (node->right != sentinel) { return rbtree_min(node->right, sentinel); } root = tree->root; for ( ;; ) { parent = node->parent; if (node == root) { return NULL; } if (node == parent->left) { return parent; } node = parent; } } rbtree_node_t * rbtree_prev(rbtree_t *tree, rbtree_node_t *node) { rbtree_node_t *root, *sentinel, *parent; sentinel = &tree->sentinel; if (node->left != sentinel) { return rbtree_max(node->left, sentinel); } root = tree->root; for ( ;; ) { parent = node->parent; if (node == root) { return NULL; } if (node == parent->right) { return parent; } node = parent; } } ROCT-Thunk-Interface-rocm-5.7.0/src/rbtree.h000066400000000000000000000054611446477712600204700ustar00rootroot00000000000000/* * Copyright (C) 2002-2018 Igor Sysoev * Copyright (C) 2011-2018 Nginx, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #ifndef _RBTREE_H_ #define _RBTREE_H_ #include #include #include #include #include #include #include #include #include #include #include "rbtree_amd.h" typedef struct rbtree_node_s rbtree_node_t; struct rbtree_node_s { rbtree_key_t key; rbtree_node_t *left; rbtree_node_t *right; rbtree_node_t *parent; unsigned char color; unsigned char data; }; typedef struct rbtree_s rbtree_t; struct rbtree_s { rbtree_node_t *root; rbtree_node_t sentinel; }; #define rbtree_init(tree) \ rbtree_sentinel_init(&(tree)->sentinel); \ (tree)->root = &(tree)->sentinel; void rbtree_insert(rbtree_t *tree, rbtree_node_t *node); void rbtree_delete(rbtree_t *tree, rbtree_node_t *node); rbtree_node_t *rbtree_prev(rbtree_t *tree, rbtree_node_t *node); rbtree_node_t *rbtree_next(rbtree_t *tree, rbtree_node_t *node); #define rbt_red(node) ((node)->color = 1) #define rbt_black(node) ((node)->color = 0) #define rbt_is_red(node) ((node)->color) #define rbt_is_black(node) (!rbt_is_red(node)) #define rbt_copy_color(n1, n2) (n1->color = n2->color) /* a sentinel must be black */ #define rbtree_sentinel_init(node) rbt_black(node) static inline rbtree_node_t * rbtree_min(rbtree_node_t *node, rbtree_node_t *sentinel) { while (node->left != sentinel) { node = node->left; } return node; } #include "rbtree_amd.h" #endif ROCT-Thunk-Interface-rocm-5.7.0/src/rbtree_amd.h000066400000000000000000000072201446477712600213040ustar00rootroot00000000000000/* * Copyright © 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef _RBTREE_AMD_H_ #define _RBTREE_AMD_H_ typedef struct rbtree_key_s rbtree_key_t; struct rbtree_key_s { #define ADDR_BIT 0 #define SIZE_BIT 1 unsigned long addr; unsigned long size; }; #define BIT(x) (1<<(x)) #define LKP_ALL (BIT(ADDR_BIT) | BIT(SIZE_BIT)) #define LKP_ADDR (BIT(ADDR_BIT)) #define LKP_ADDR_SIZE (BIT(ADDR_BIT) | BIT(SIZE_BIT)) static inline rbtree_key_t rbtree_key(unsigned long addr, unsigned long size) { return (rbtree_key_t){addr, size}; } /* * compare addr, size one by one */ static inline int rbtree_key_compare(unsigned int type, rbtree_key_t *key1, rbtree_key_t *key2) { if ((type & 1 << ADDR_BIT) && (key1->addr != key2->addr)) return key1->addr > key2->addr ? 1 : -1; if ((type & 1 << SIZE_BIT) && (key1->size != key2->size)) return key1->size > key2->size ? 1 : -1; return 0; } #endif /*_RBTREE_AMD_H_*/ /*inlcude this file again with RBTREE_HELPER defined*/ #ifndef RBTREE_HELPER #define RBTREE_HELPER #else #ifndef _RBTREE_AMD_H_HELPER_ #define _RBTREE_AMD_H_HELPER_ static inline rbtree_node_t * rbtree_max(rbtree_node_t *node, rbtree_node_t *sentinel) { while (node->right != sentinel) node = node->right; return node; } #define LEFT 0 #define RIGHT 1 #define MID 2 static inline rbtree_node_t * rbtree_min_max(rbtree_t *tree, int lr) { rbtree_node_t *sentinel = &tree->sentinel; rbtree_node_t *node = tree->root; if (node == sentinel) return NULL; if (lr == LEFT) node = rbtree_min(node, sentinel); else if (lr == RIGHT) node = rbtree_max(node, sentinel); return node; } static inline rbtree_node_t * rbtree_node_any(rbtree_t *tree, int lmr) { rbtree_node_t *sentinel = &tree->sentinel; rbtree_node_t *node = tree->root; if (node == sentinel) return NULL; if (lmr == MID) return node; return rbtree_min_max(tree, lmr); } static inline rbtree_node_t * rbtree_lookup_nearest(rbtree_t *rbtree, rbtree_key_t *key, unsigned int type, int lr) { int rc; rbtree_node_t *node, *sentinel, *n = NULL; node = rbtree->root; sentinel = &rbtree->sentinel; while (node != sentinel) { rc = rbtree_key_compare(type, key, &node->key); if (rc < 0) { if (lr == RIGHT) n = node; node = node->left; continue; } if (rc > 0) { if (lr == LEFT) n = node; node = node->right; continue; } return node; } return n; } static inline rbtree_node_t * rbtree_lookup(rbtree_t *rbtree, rbtree_key_t *key, unsigned int type) { return rbtree_lookup_nearest(rbtree, key, type, -1); } #endif /*_RBTREE_AMD_H_HELPER_*/ #endif /*RBTREE_HELPER*/ ROCT-Thunk-Interface-rocm-5.7.0/src/spm.c000066400000000000000000000055401446477712600177750ustar00rootroot00000000000000/* * Copyright © 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "libhsakmt.h" #include "linux/kfd_ioctl.h" #include #include HSAKMT_STATUS HSAKMTAPI hsaKmtSPMAcquire(HSAuint32 PreferredNode) { int ret; struct kfd_ioctl_spm_args args = {0}; uint32_t gpu_id; ret = validate_nodeid(PreferredNode, &gpu_id); if (ret != HSAKMT_STATUS_SUCCESS) { pr_err("[%s] invalid node ID: %d\n", __func__, PreferredNode); return ret; } ret = HSAKMT_STATUS_SUCCESS; args.op = KFD_IOCTL_SPM_OP_ACQUIRE; args.gpu_id = gpu_id; ret = kmtIoctl(kfd_fd, AMDKFD_IOC_RLC_SPM, &args); return ret; } HSAKMT_STATUS HSAKMTAPI hsaKmtSPMSetDestBuffer(HSAuint32 PreferredNode, HSAuint32 SizeInBytes, HSAuint32 * timeout, HSAuint32 * SizeCopied, void *DestMemoryAddress, bool *isSPMDataLoss) { int ret; struct kfd_ioctl_spm_args args = {0}; uint32_t gpu_id; ret = HSAKMT_STATUS_SUCCESS; ret = validate_nodeid(PreferredNode, &gpu_id); args.timeout = *timeout; args.dest_buf = (uint64_t)DestMemoryAddress; args.buf_size = SizeInBytes; args.op = KFD_IOCTL_SPM_OP_SET_DEST_BUF; args.gpu_id = gpu_id; ret = kmtIoctl(kfd_fd, AMDKFD_IOC_RLC_SPM, &args); *SizeCopied = args.bytes_copied; *isSPMDataLoss = args.has_data_loss; *timeout = args.timeout; return ret; } HSAKMT_STATUS HSAKMTAPI hsaKmtSPMRelease(HSAuint32 PreferredNode) { int ret = HSAKMT_STATUS_SUCCESS; struct kfd_ioctl_spm_args args = {0}; uint32_t gpu_id; ret = validate_nodeid(PreferredNode, &gpu_id); if (ret != HSAKMT_STATUS_SUCCESS) { pr_err("[%s] invalid node ID: %d\n", __func__, PreferredNode); return ret; } args.op = KFD_IOCTL_SPM_OP_RELEASE; args.gpu_id = gpu_id; ret = kmtIoctl(kfd_fd, AMDKFD_IOC_RLC_SPM, &args); return ret; } ROCT-Thunk-Interface-rocm-5.7.0/src/svm.c000066400000000000000000000150101446477712600177740ustar00rootroot00000000000000/* * Copyright © 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "libhsakmt.h" #include #include #include #include #include #include #include #include #include #include /* Helper functions for calling KFD SVM ioctl */ HSAKMT_STATUS HSAKMTAPI hsaKmtSVMSetAttr(void *start_addr, HSAuint64 size, unsigned int nattr, HSA_SVM_ATTRIBUTE *attrs) { struct kfd_ioctl_svm_args *args; HSAuint64 s_attr; HSAKMT_STATUS r; HSAuint32 i; CHECK_KFD_OPEN(); CHECK_KFD_MINOR_VERSION(5); pr_debug("%s: address 0x%p size 0x%lx\n", __func__, start_addr, size); if (!start_addr || !size) return HSAKMT_STATUS_INVALID_PARAMETER; if ((uint64_t)start_addr & (PAGE_SIZE - 1)) return HSAKMT_STATUS_INVALID_PARAMETER; if (size & (PAGE_SIZE - 1)) return HSAKMT_STATUS_INVALID_PARAMETER; s_attr = sizeof(*attrs) * nattr; args = alloca(sizeof(*args) + s_attr); args->start_addr = (uint64_t)start_addr; args->size = size; args->op = KFD_IOCTL_SVM_OP_SET_ATTR; args->nattr = nattr; memcpy(args->attrs, attrs, s_attr); for (i = 0; i < nattr; i++) { if (attrs[i].type != KFD_IOCTL_SVM_ATTR_PREFERRED_LOC && attrs[i].type != KFD_IOCTL_SVM_ATTR_PREFETCH_LOC && attrs[i].type != KFD_IOCTL_SVM_ATTR_ACCESS && attrs[i].type != KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE && attrs[i].type != KFD_IOCTL_SVM_ATTR_NO_ACCESS) continue; if (attrs[i].type == KFD_IOCTL_SVM_ATTR_PREFERRED_LOC && attrs[i].value == INVALID_NODEID) { args->attrs[i].value = KFD_IOCTL_SVM_LOCATION_UNDEFINED; continue; } r = validate_nodeid(attrs[i].value, &args->attrs[i].value); if (r != HSAKMT_STATUS_SUCCESS) { pr_debug("invalid node ID: %d\n", attrs[i].value); return r; } else if (!args->attrs[i].value && (attrs[i].type == KFD_IOCTL_SVM_ATTR_ACCESS || attrs[i].type == KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE || attrs[i].type == KFD_IOCTL_SVM_ATTR_NO_ACCESS)) { pr_debug("CPU node invalid for access attribute\n"); return HSAKMT_STATUS_INVALID_NODE_UNIT; } } /* Driver does one copy_from_user, with extra attrs size */ r = kmtIoctl(kfd_fd, AMDKFD_IOC_SVM + (s_attr << _IOC_SIZESHIFT), args); if (r) { pr_debug("op set range attrs failed %s\n", strerror(errno)); return HSAKMT_STATUS_ERROR; } return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtSVMGetAttr(void *start_addr, HSAuint64 size, unsigned int nattr, HSA_SVM_ATTRIBUTE *attrs) { struct kfd_ioctl_svm_args *args; HSAuint64 s_attr; HSAKMT_STATUS r; HSAuint32 i; CHECK_KFD_OPEN(); CHECK_KFD_MINOR_VERSION(5); pr_debug("%s: address 0x%p size 0x%lx\n", __func__, start_addr, size); if (!start_addr || !size) return HSAKMT_STATUS_INVALID_PARAMETER; if ((uint64_t)start_addr & (PAGE_SIZE - 1)) return HSAKMT_STATUS_INVALID_PARAMETER; if (size & (PAGE_SIZE - 1)) return HSAKMT_STATUS_INVALID_PARAMETER; s_attr = sizeof(*attrs) * nattr; args = alloca(sizeof(*args) + s_attr); args->start_addr = (uint64_t)start_addr; args->size = size; args->op = KFD_IOCTL_SVM_OP_GET_ATTR; args->nattr = nattr; memcpy(args->attrs, attrs, s_attr); for (i = 0; i < nattr; i++) { if (attrs[i].type != KFD_IOCTL_SVM_ATTR_ACCESS && attrs[i].type != KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE && attrs[i].type != KFD_IOCTL_SVM_ATTR_NO_ACCESS) continue; r = validate_nodeid(attrs[i].value, &args->attrs[i].value); if (r != HSAKMT_STATUS_SUCCESS) { pr_debug("invalid node ID: %d\n", attrs[i].value); return r; } else if (!args->attrs[i].value) { pr_debug("CPU node invalid for access attribute\n"); return HSAKMT_STATUS_INVALID_NODE_UNIT; } } /* Driver does one copy_from_user, with extra attrs size */ r = kmtIoctl(kfd_fd, AMDKFD_IOC_SVM + (s_attr << _IOC_SIZESHIFT), args); if (r) { pr_debug("op get range attrs failed %s\n", strerror(errno)); return HSAKMT_STATUS_ERROR; } memcpy(attrs, args->attrs, s_attr); for (i = 0; i < nattr; i++) { if (attrs[i].type != KFD_IOCTL_SVM_ATTR_PREFERRED_LOC && attrs[i].type != KFD_IOCTL_SVM_ATTR_PREFETCH_LOC && attrs[i].type != KFD_IOCTL_SVM_ATTR_ACCESS && attrs[i].type != KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE && attrs[i].type != KFD_IOCTL_SVM_ATTR_NO_ACCESS) continue; switch (attrs[i].value) { case KFD_IOCTL_SVM_LOCATION_SYSMEM: attrs[i].value = 0; break; case KFD_IOCTL_SVM_LOCATION_UNDEFINED: attrs[i].value = INVALID_NODEID; break; default: r = gpuid_to_nodeid(attrs[i].value, &attrs[i].value); if (r != HSAKMT_STATUS_SUCCESS) { pr_debug("invalid GPU ID: %d\n", attrs[i].value); return r; } } } return HSAKMT_STATUS_SUCCESS; } static HSAKMT_STATUS hsaKmtSetGetXNACKMode(HSAint32 * enable) { struct kfd_ioctl_set_xnack_mode_args args; CHECK_KFD_OPEN(); CHECK_KFD_MINOR_VERSION(5); args.xnack_enabled = *enable; if (kmtIoctl(kfd_fd, AMDKFD_IOC_SET_XNACK_MODE, &args)) { if (errno == EPERM) { pr_debug("set mode not supported %s\n", strerror(errno)); return HSAKMT_STATUS_NOT_SUPPORTED; } else if (errno == EBUSY) { pr_debug("kmtIoctl queues not empty %s\n", strerror(errno)); } return HSAKMT_STATUS_ERROR; } *enable = args.xnack_enabled; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtSetXNACKMode(HSAint32 enable) { return hsaKmtSetGetXNACKMode(&enable); } HSAKMT_STATUS HSAKMTAPI hsaKmtGetXNACKMode(HSAint32 * enable) { *enable = -1; return hsaKmtSetGetXNACKMode(enable); } ROCT-Thunk-Interface-rocm-5.7.0/src/time.c000066400000000000000000000037461446477712600201420ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "libhsakmt.h" #include "linux/kfd_ioctl.h" HSAKMT_STATUS HSAKMTAPI hsaKmtGetClockCounters(HSAuint32 NodeId, HsaClockCounters *Counters) { HSAKMT_STATUS result; uint32_t gpu_id; struct kfd_ioctl_get_clock_counters_args args = {0}; int err; CHECK_KFD_OPEN(); result = validate_nodeid(NodeId, &gpu_id); if (result != HSAKMT_STATUS_SUCCESS) return result; args.gpu_id = gpu_id; err = kmtIoctl(kfd_fd, AMDKFD_IOC_GET_CLOCK_COUNTERS, &args); if (err < 0) { result = HSAKMT_STATUS_ERROR; } else { /* At this point the result is already HSAKMT_STATUS_SUCCESS */ Counters->GPUClockCounter = args.gpu_clock_counter; Counters->CPUClockCounter = args.cpu_clock_counter; Counters->SystemClockCounter = args.system_clock_counter; Counters->SystemClockFrequencyHz = args.system_clock_freq; } return result; } ROCT-Thunk-Interface-rocm-5.7.0/src/topology.c000066400000000000000000002162001446477712600210470ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * Copyright 2016-2018 Raptor Engineering, LLC. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include "libhsakmt.h" #include "fmm.h" /* Number of memory banks added by thunk on top of topology * This only includes static heaps like LDS, scratch and SVM, * not for MMIO_REMAP heap. MMIO_REMAP memory bank is reported * dynamically based on whether mmio aperture was mapped * successfully on this node. */ #define NUM_OF_IGPU_HEAPS 3 #define NUM_OF_DGPU_HEAPS 3 /* SYSFS related */ #define KFD_SYSFS_PATH_GENERATION_ID "/sys/devices/virtual/kfd/kfd/topology/generation_id" #define KFD_SYSFS_PATH_SYSTEM_PROPERTIES "/sys/devices/virtual/kfd/kfd/topology/system_properties" #define KFD_SYSFS_PATH_NODES "/sys/devices/virtual/kfd/kfd/topology/nodes" typedef struct { HsaNodeProperties node; HsaMemoryProperties *mem; /* node->NumBanks elements */ HsaCacheProperties *cache; HsaIoLinkProperties *link; } node_props_t; static HsaSystemProperties *g_system; static node_props_t *g_props; /* This array caches sysfs based node IDs of CPU nodes + all supported GPU nodes. * It will be used to map user-node IDs to sysfs-node IDs. */ static uint32_t *map_user_to_sysfs_node_id; static uint32_t map_user_to_sysfs_node_id_size; static uint32_t num_sysfs_nodes; static int processor_vendor = -1; /* Supported System Vendors */ enum SUPPORTED_PROCESSOR_VENDORS { GENUINE_INTEL = 0, AUTHENTIC_AMD, IBM_POWER }; /* Adding newline to make the search easier */ static const char *supported_processor_vendor_name[] = { "GenuineIntel\n", "AuthenticAMD\n", "\n" // POWER requires a different search method }; static HSAKMT_STATUS topology_take_snapshot(void); static void topology_drop_snapshot(void); static const struct hsa_gfxip_table gfxip_lookup_table[] = { /* Kaveri Family */ { 0x1304, 7, 0, 0, "Spectre" }, { 0x1305, 7, 0, 0, "Spectre" }, { 0x1306, 7, 0, 0, "Spectre" }, { 0x1307, 7, 0, 0, "Spectre" }, { 0x1309, 7, 0, 0, "Spectre" }, { 0x130A, 7, 0, 0, "Spectre" }, { 0x130B, 7, 0, 0, "Spectre" }, { 0x130C, 7, 0, 0, "Spectre" }, { 0x130D, 7, 0, 0, "Spectre" }, { 0x130E, 7, 0, 0, "Spectre" }, { 0x130F, 7, 0, 0, "Spectre" }, { 0x1310, 7, 0, 0, "Spectre" }, { 0x1311, 7, 0, 0, "Spectre" }, { 0x1312, 7, 0, 0, "Spooky" }, { 0x1313, 7, 0, 0, "Spectre" }, { 0x1315, 7, 0, 0, "Spectre" }, { 0x1316, 7, 0, 0, "Spooky" }, { 0x1317, 7, 0, 0, "Spooky" }, { 0x1318, 7, 0, 0, "Spectre" }, { 0x131B, 7, 0, 0, "Spectre" }, { 0x131C, 7, 0, 0, "Spectre" }, { 0x131D, 7, 0, 0, "Spectre" }, /* Hawaii Family */ { 0x67A0, 7, 0, 1, "Hawaii" }, { 0x67A1, 7, 0, 1, "Hawaii" }, { 0x67A2, 7, 0, 1, "Hawaii" }, { 0x67A8, 7, 0, 1, "Hawaii" }, { 0x67A9, 7, 0, 1, "Hawaii" }, { 0x67AA, 7, 0, 1, "Hawaii" }, { 0x67B0, 7, 0, 1, "Hawaii" }, { 0x67B1, 7, 0, 1, "Hawaii" }, { 0x67B8, 7, 0, 1, "Hawaii" }, { 0x67B9, 7, 0, 1, "Hawaii" }, { 0x67BA, 7, 0, 1, "Hawaii" }, { 0x67BE, 7, 0, 1, "Hawaii" }, /* Carrizo Family */ { 0x9870, 8, 0, 1, "Carrizo" }, { 0x9874, 8, 0, 1, "Carrizo" }, { 0x9875, 8, 0, 1, "Carrizo" }, { 0x9876, 8, 0, 1, "Carrizo" }, { 0x9877, 8, 0, 1, "Carrizo" }, /* Tonga Family */ { 0x6920, 8, 0, 2, "Tonga" }, { 0x6921, 8, 0, 2, "Tonga" }, { 0x6928, 8, 0, 2, "Tonga" }, { 0x6929, 8, 0, 2, "Tonga" }, { 0x692B, 8, 0, 2, "Tonga" }, { 0x692F, 8, 0, 2, "Tonga" }, { 0x6930, 8, 0, 2, "Tonga" }, { 0x6938, 8, 0, 2, "Tonga" }, { 0x6939, 8, 0, 2, "Tonga" }, /* Fiji */ { 0x7300, 8, 0, 3, "Fiji" }, { 0x730F, 8, 0, 3, "Fiji" }, /* Polaris10 */ { 0x67C0, 8, 0, 3, "Polaris10" }, { 0x67C1, 8, 0, 3, "Polaris10" }, { 0x67C2, 8, 0, 3, "Polaris10" }, { 0x67C4, 8, 0, 3, "Polaris10" }, { 0x67C7, 8, 0, 3, "Polaris10" }, { 0x67C8, 8, 0, 3, "Polaris10" }, { 0x67C9, 8, 0, 3, "Polaris10" }, { 0x67CA, 8, 0, 3, "Polaris10" }, { 0x67CC, 8, 0, 3, "Polaris10" }, { 0x67CF, 8, 0, 3, "Polaris10" }, { 0x67D0, 8, 0, 3, "Polaris10" }, { 0x67DF, 8, 0, 3, "Polaris10" }, { 0x6FDF, 8, 0, 3, "Polaris10" }, /* Polaris11 */ { 0x67E0, 8, 0, 3, "Polaris11" }, { 0x67E1, 8, 0, 3, "Polaris11" }, { 0x67E3, 8, 0, 3, "Polaris11" }, { 0x67E7, 8, 0, 3, "Polaris11" }, { 0x67E8, 8, 0, 3, "Polaris11" }, { 0x67E9, 8, 0, 3, "Polaris11" }, { 0x67EB, 8, 0, 3, "Polaris11" }, { 0x67EF, 8, 0, 3, "Polaris11" }, { 0x67FF, 8, 0, 3, "Polaris11" }, /* Polaris12 */ { 0x6980, 8, 0, 3, "Polaris12" }, { 0x6981, 8, 0, 3, "Polaris12" }, { 0x6985, 8, 0, 3, "Polaris12" }, { 0x6986, 8, 0, 3, "Polaris12" }, { 0x6987, 8, 0, 3, "Polaris12" }, { 0x6995, 8, 0, 3, "Polaris12" }, { 0x6997, 8, 0, 3, "Polaris12" }, { 0x699F, 8, 0, 3, "Polaris12" }, /* VegaM */ { 0x694C, 8, 0, 3, "VegaM" }, { 0x694E, 8, 0, 3, "VegaM" }, { 0x694F, 8, 0, 3, "VegaM" }, /* Vega10 */ { 0x6860, 9, 0, 0, "Vega10" }, { 0x6861, 9, 0, 0, "Vega10" }, { 0x6862, 9, 0, 0, "Vega10" }, { 0x6863, 9, 0, 0, "Vega10" }, { 0x6864, 9, 0, 0, "Vega10" }, { 0x6867, 9, 0, 0, "Vega10" }, { 0x6868, 9, 0, 0, "Vega10" }, { 0x6869, 9, 0, 0, "Vega10" }, { 0x686A, 9, 0, 0, "Vega10" }, { 0x686B, 9, 0, 0, "Vega10" }, { 0x686C, 9, 0, 0, "Vega10" }, { 0x686D, 9, 0, 0, "Vega10" }, { 0x686E, 9, 0, 0, "Vega10" }, { 0x687F, 9, 0, 0, "Vega10" }, /* Vega12 */ { 0x69A0, 9, 0, 4, "Vega12" }, { 0x69A1, 9, 0, 4, "Vega12" }, { 0x69A2, 9, 0, 4, "Vega12" }, { 0x69A3, 9, 0, 4, "Vega12" }, { 0x69Af, 9, 0, 4, "Vega12" }, /* Raven */ { 0x15DD, 9, 0, 2, "Raven" }, { 0x15D8, 9, 0, 2, "Raven" }, /* Vega20 */ { 0x66A0, 9, 0, 6, "Vega20" }, { 0x66A1, 9, 0, 6, "Vega20" }, { 0x66A2, 9, 0, 6, "Vega20" }, { 0x66A3, 9, 0, 6, "Vega20" }, { 0x66A4, 9, 0, 6, "Vega20" }, { 0x66A7, 9, 0, 6, "Vega20" }, { 0x66AF, 9, 0, 6, "Vega20" }, /* Arcturus */ { 0x7388, 9, 0, 8, "Arcturus" }, { 0x738C, 9, 0, 8, "Arcturus" }, { 0x738E, 9, 0, 8, "Arcturus" }, { 0x7390, 9, 0, 8, "Arcturus" }, /* Aldebaran */ { 0x7408, 9, 0, 10, "Aldebaran" }, { 0x740C, 9, 0, 10, "Aldebaran" }, { 0x740F, 9, 0, 10, "Aldebaran" }, { 0x7410, 9, 0, 10, "Aldebaran" }, /* Renoir */ { 0x15E7, 9, 0, 12, "Renoir" }, { 0x1636, 9, 0, 12, "Renoir" }, { 0x1638, 9, 0, 12, "Renoir" }, { 0x164C, 9, 0, 12, "Renoir" }, /* Navi10 */ { 0x7310, 10, 1, 0, "Navi10" }, { 0x7312, 10, 1, 0, "Navi10" }, { 0x7318, 10, 1, 0, "Navi10" }, { 0x731A, 10, 1, 0, "Navi10" }, { 0x731E, 10, 1, 0, "Navi10" }, { 0x731F, 10, 1, 0, "Navi10" }, /* cyan_skillfish */ { 0x13F9, 10, 1, 3, "cyan_skillfish" }, { 0x13FA, 10, 1, 3, "cyan_skillfish" }, { 0x13FB, 10, 1, 3, "cyan_skillfish" }, { 0x13FC, 10, 1, 3, "cyan_skillfish" }, { 0x13FE, 10, 1, 3, "cyan_skillfish" }, { 0x143F, 10, 1, 3, "cyan_skillfish" }, /* Navi14 */ { 0x7340, 10, 1, 2, "Navi14" }, { 0x7341, 10, 1, 2, "Navi14" }, { 0x7347, 10, 1, 2, "Navi14" }, /* Navi12 */ { 0x7360, 10, 1, 1, "Navi12" }, { 0x7362, 10, 1, 1, "Navi12" }, /* SIENNA_CICHLID */ { 0x73A0, 10, 3, 0, "SIENNA_CICHLID" }, { 0x73A1, 10, 3, 0, "SIENNA_CICHLID" }, { 0x73A2, 10, 3, 0, "SIENNA_CICHLID" }, { 0x73A3, 10, 3, 0, "SIENNA_CICHLID" }, { 0x73A5, 10, 3, 0, "SIENNA_CICHLID" }, { 0x73A8, 10, 3, 0, "SIENNA_CICHLID" }, { 0x73A9, 10, 3, 0, "SIENNA_CICHLID" }, { 0x73AC, 10, 3, 0, "SIENNA_CICHLID" }, { 0x73AD, 10, 3, 0, "SIENNA_CICHLID" }, { 0x73AB, 10, 3, 0, "SIENNA_CICHLID" }, { 0x73AE, 10, 3, 0, "SIENNA_CICHLID" }, { 0x73BF, 10, 3, 0, "SIENNA_CICHLID" }, /* NAVY_FLOUNDER */ { 0x73C0, 10, 3, 1, "NAVY_FLOUNDER" }, { 0x73C1, 10, 3, 1, "NAVY_FLOUNDER" }, { 0x73C3, 10, 3, 1, "NAVY_FLOUNDER" }, { 0x73DA, 10, 3, 1, "NAVY_FLOUNDER" }, { 0x73DB, 10, 3, 1, "NAVY_FLOUNDER" }, { 0x73DC, 10, 3, 1, "NAVY_FLOUNDER" }, { 0x73DD, 10, 3, 1, "NAVY_FLOUNDER" }, { 0x73DE, 10, 3, 1, "NAVY_FLOUNDER" }, { 0x73DF, 10, 3, 1, "NAVY_FLOUNDER" }, /* DIMGREY_CAVEFISH */ { 0x73E0, 10, 3, 2, "DIMGREY_CAVEFISH" }, { 0x73E1, 10, 3, 2, "DIMGREY_CAVEFISH" }, { 0x73E2, 10, 3, 2, "DIMGREY_CAVEFISH" }, { 0x73E8, 10, 3, 2, "DIMGREY_CAVEFISH" }, { 0x73E9, 10, 3, 2, "DIMGREY_CAVEFISH" }, { 0x73EA, 10, 3, 2, "DIMGREY_CAVEFISH" }, { 0x73EB, 10, 3, 2, "DIMGREY_CAVEFISH" }, { 0x73EC, 10, 3, 2, "DIMGREY_CAVEFISH" }, { 0x73ED, 10, 3, 2, "DIMGREY_CAVEFISH" }, { 0x73EF, 10, 3, 2, "DIMGREY_CAVEFISH" }, { 0x73FF, 10, 3, 2, "DIMGREY_CAVEFISH" }, /* VanGogh */ { 0x163F, 10, 3, 3, "VanGogh" }, /* BEIGE_GOBY */ { 0x7420, 10, 3, 4, "BEIGE_GOBY" }, { 0x7421, 10, 3, 4, "BEIGE_GOBY" }, { 0x7422, 10, 3, 4, "BEIGE_GOBY" }, { 0x7423, 10, 3, 4, "BEIGE_GOBY" }, { 0x743F, 10, 3, 4, "BEIGE_GOBY" }, /* Yellow_Carp */ { 0x164D, 10, 3, 5, "YELLOW_CARP" }, { 0x1681, 10, 3, 5, "YELLOW_CARP" }, }; /* information from /proc/cpuinfo */ struct proc_cpuinfo { uint32_t proc_num; /* processor */ uint32_t apicid; /* apicid */ char model_name[HSA_PUBLIC_NAME_SIZE]; /* model name */ }; /* CPU cache table for all CPUs on the system. Each entry has the relative CPU * info and caches connected to that CPU. */ typedef struct cpu_cacheinfo { uint32_t len; /* length of the table = number of online procs */ int32_t proc_num; /* this cpu's processor number */ uint32_t num_caches; /* number of caches reported by this cpu */ HsaCacheProperties *cache_prop; /* a list of cache properties */ } cpu_cacheinfo_t; static void free_properties(node_props_t *props, int size) { if (props) { int i; for (i = 0; i < size; i++) { free(props[i].mem); free(props[i].cache); free(props[i].link); } free(props); } } /* num_subdirs - find the number of sub-directories in the specified path * @dirpath - directory path to find sub-directories underneath * @prefix - only count sub-directory names starting with prefix. * Use blank string, "", to count all. * Return - number of sub-directories */ static int num_subdirs(char *dirpath, char *prefix) { int count = 0; DIR *dirp; struct dirent *dir; int prefix_len = strlen(prefix); dirp = opendir(dirpath); if (dirp) { while ((dir = readdir(dirp)) != 0) { if ((strcmp(dir->d_name, ".") == 0) || (strcmp(dir->d_name, "..") == 0)) continue; if (prefix_len && strncmp(dir->d_name, prefix, prefix_len)) continue; count++; } closedir(dirp); } return count; } /* fscanf_dec - read a file whose content is a decimal number * @file [IN ] file to read * @num [OUT] number in the file */ static HSAKMT_STATUS fscanf_dec(char *file, uint32_t *num) { FILE *fd; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; fd = fopen(file, "r"); if (!fd) { pr_err("Failed to open %s\n", file); return HSAKMT_STATUS_INVALID_PARAMETER; } if (fscanf(fd, "%u", num) != 1) { pr_err("Failed to parse %s as a decimal.\n", file); ret = HSAKMT_STATUS_ERROR; } fclose(fd); return ret; } /* fscanf_str - read a file whose content is a string * @file [IN ] file to read * @str [OUT] string in the file */ static HSAKMT_STATUS fscanf_str(char *file, char *str) { FILE *fd; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; fd = fopen(file, "r"); if (!fd) { pr_err("Failed to open %s\n", file); return HSAKMT_STATUS_INVALID_PARAMETER; } if (fscanf(fd, "%s", str) != 1) { pr_err("Failed to parse %s as a string.\n", file); ret = HSAKMT_STATUS_ERROR; } fclose(fd); return ret; } /* fscanf_size - read a file whose content represents size as a string * @file [IN ] file to read * @bytes [OUT] sizes in bytes */ static HSAKMT_STATUS fscanf_size(char *file, uint32_t *bytes) { FILE *fd; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; char unit; int n; fd = fopen(file, "r"); if (!fd) { pr_err("Failed to open %s\n", file); return HSAKMT_STATUS_INVALID_PARAMETER; } n = fscanf(fd, "%u%c", bytes, &unit); if (n < 1) { pr_err("Failed to parse %s\n", file); ret = HSAKMT_STATUS_ERROR; } if (n == 2) { switch (unit) { case 'K': *bytes <<= 10; break; case 'M': *bytes <<= 20; break; case 'G': *bytes <<= 30; break; default: ret = HSAKMT_STATUS_ERROR; break; } } fclose(fd); return ret; } /* cpumap_to_cpu_ci - translate shared_cpu_map string + cpuinfo->apicid into * SiblingMap in cache * @shared_cpu_map [IN ] shared_cpu_map string * @cpuinfo [IN ] cpuinfo to get apicid * @this_cache [OUT] CPU cache to fill in SiblingMap */ static void cpumap_to_cpu_ci(char *shared_cpu_map, struct proc_cpuinfo *cpuinfo, HsaCacheProperties *this_cache) { int num_hexs, bit; uint32_t proc, apicid, mask; char *ch_ptr; /* shared_cpu_map is shown as ...X3,X2,X1 Each X is a hex without 0x * and it's up to 8 characters(32 bits). For the first 32 CPUs(actually * procs), it's presented in X1. The next 32 is in X2, and so on. */ num_hexs = (strlen(shared_cpu_map) + 8) / 9; /* 8 characters + "," */ ch_ptr = strtok(shared_cpu_map, ","); while (num_hexs-- > 0) { mask = strtol(ch_ptr, NULL, 16); /* each X */ for (bit = 0; bit < 32; bit++) { if (!((1 << bit) & mask)) continue; proc = num_hexs * 32 + bit; apicid = cpuinfo[proc].apicid; if (apicid >= HSA_CPU_SIBLINGS) { pr_warn("SiblingMap buffer %d is too small\n", HSA_CPU_SIBLINGS); continue; } this_cache->SiblingMap[apicid] = 1; } ch_ptr = strtok(NULL, ","); } } /* get_cpu_cache_info - get specified CPU's cache information from sysfs * @prefix [IN] sysfs path for target cpu cache, * /sys/devices/system/node/nodeX/cpuY/cache * @cpuinfo [IN] /proc/cpuinfo data to get apicid * @cpu_ci: CPU specified. This parameter is an input and also an output. * [IN] cpu_ci->num_caches: number of index dirs * [OUT] cpu_ci->cache_info: to store cache info collected * [OUT] cpu_ci->num_caches: reduces when shared with other cpu(s) * Return: number of cache reported from this cpu */ static int get_cpu_cache_info(const char *prefix, struct proc_cpuinfo *cpuinfo, cpu_cacheinfo_t *cpu_ci) { int idx, num_idx, n; HsaCacheProperties *this_cache; char path[256], str[256]; bool is_power9 = false; if (processor_vendor == IBM_POWER) { if (strcmp(cpuinfo[0].model_name, "POWER9") == 0) { is_power9 = true; } } this_cache = cpu_ci->cache_prop; num_idx = cpu_ci->num_caches; for (idx = 0; idx < num_idx; idx++) { /* If this cache is shared by multiple CPUs, we only need * to list it in the first CPU. */ if (is_power9) { // POWER9 has SMT4 if (cpu_ci->proc_num & 0x3) { /* proc is not 0,4,8,etc. Skip and reduce the cache count. */ --cpu_ci->num_caches; continue; } } else { snprintf(path, 256, "%s/index%d/shared_cpu_list", prefix, idx); /* shared_cpu_list is shown as n1,n2... or n1-n2,n3-n4... * For both cases, this cache is listed to proc n1 only. */ fscanf_dec(path, (uint32_t *)&n); if (cpu_ci->proc_num != n) { /* proc is not n1. Skip and reduce the cache count. */ --cpu_ci->num_caches; continue; } this_cache->ProcessorIdLow = cpuinfo[cpu_ci->proc_num].apicid; } /* CacheLevel */ snprintf(path, 256, "%s/index%d/level", prefix, idx); fscanf_dec(path, &this_cache->CacheLevel); /* CacheType */ snprintf(path, 256, "%s/index%d/type", prefix, idx); memset(str, 0, sizeof(str)); fscanf_str(path, str); if (!strcmp(str, "Data")) this_cache->CacheType.ui32.Data = 1; if (!strcmp(str, "Instruction")) this_cache->CacheType.ui32.Instruction = 1; if (!strcmp(str, "Unified")) { this_cache->CacheType.ui32.Data = 1; this_cache->CacheType.ui32.Instruction = 1; } this_cache->CacheType.ui32.CPU = 1; /* CacheSize */ snprintf(path, 256, "%s/index%d/size", prefix, idx); fscanf_size(path, &this_cache->CacheSize); /* CacheLineSize */ snprintf(path, 256, "%s/index%d/coherency_line_size", prefix, idx); fscanf_dec(path, &this_cache->CacheLineSize); /* CacheAssociativity */ snprintf(path, 256, "%s/index%d/ways_of_associativity", prefix, idx); fscanf_dec(path, &this_cache->CacheAssociativity); /* CacheLinesPerTag */ snprintf(path, 256, "%s/index%d/physical_line_partition", prefix, idx); fscanf_dec(path, &this_cache->CacheLinesPerTag); /* CacheSiblings */ snprintf(path, 256, "%s/index%d/shared_cpu_map", prefix, idx); fscanf_str(path, str); cpumap_to_cpu_ci(str, cpuinfo, this_cache); ++this_cache; } return cpu_ci->num_caches; } static HSAKMT_STATUS topology_sysfs_get_generation(uint32_t *gen) { FILE *fd; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; assert(gen); fd = fopen(KFD_SYSFS_PATH_GENERATION_ID, "r"); if (!fd) return HSAKMT_STATUS_ERROR; if (fscanf(fd, "%ul", gen) != 1) { ret = HSAKMT_STATUS_ERROR; goto err; } err: fclose(fd); return ret; } static HSAKMT_STATUS topology_sysfs_map_node_id(uint32_t node_id, uint32_t *sys_node_id) { if ((!map_user_to_sysfs_node_id) || (node_id >= map_user_to_sysfs_node_id_size)) return HSAKMT_STATUS_NOT_SUPPORTED; *sys_node_id = map_user_to_sysfs_node_id[node_id]; return HSAKMT_STATUS_SUCCESS; } static HSAKMT_STATUS topology_sysfs_get_gpu_id(uint32_t sysfs_node_id, uint32_t *gpu_id) { FILE *fd; char path[256]; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; assert(gpu_id); snprintf(path, 256, "%s/%d/gpu_id", KFD_SYSFS_PATH_NODES, sysfs_node_id); fd = fopen(path, "r"); if (!fd) return HSAKMT_STATUS_ERROR; if (fscanf(fd, "%ul", gpu_id) != 1) ret = (errno == EPERM) ? HSAKMT_STATUS_NOT_SUPPORTED : HSAKMT_STATUS_ERROR; fclose(fd); return ret; } /* Check if the @sysfs_node_id is supported. This function will be passed with sysfs node id. * This function can not use topology_* help functions, because those functions are * using user node id. * A sysfs node is not supported * - if corresponding drm render node is not available. * - if node information is not accessible (EPERM) */ static HSAKMT_STATUS topology_sysfs_check_node_supported(uint32_t sysfs_node_id, bool *is_node_supported) { uint32_t gpu_id; FILE *fd; char *read_buf, *p; int read_size; char prop_name[256]; char path[256]; unsigned long long prop_val; uint32_t prog; uint32_t drm_render_minor = 0; int ret_value; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; *is_node_supported = false; /* Retrieve the GPU ID */ ret = topology_sysfs_get_gpu_id(sysfs_node_id, &gpu_id); if (ret == HSAKMT_STATUS_NOT_SUPPORTED) return HSAKMT_STATUS_SUCCESS; if (ret != HSAKMT_STATUS_SUCCESS) return ret; if (gpu_id == 0) { *is_node_supported = true; return HSAKMT_STATUS_SUCCESS; } read_buf = malloc(PAGE_SIZE); if (!read_buf) return HSAKMT_STATUS_NO_MEMORY; /* Retrieve the node properties */ snprintf(path, 256, "%s/%d/properties", KFD_SYSFS_PATH_NODES, sysfs_node_id); fd = fopen(path, "r"); if (!fd) { ret = HSAKMT_STATUS_ERROR; goto err; } read_size = fread(read_buf, 1, PAGE_SIZE, fd); if (read_size <= 0) { ret = HSAKMT_STATUS_ERROR; goto err; } /* Since we're using the buffer as a string, we make sure the string terminates */ if (read_size >= PAGE_SIZE) read_size = PAGE_SIZE - 1; read_buf[read_size] = 0; /* Read the node properties */ prog = 0; p = read_buf; while (sscanf(p += prog, "%s %llu\n%n", prop_name, &prop_val, &prog) == 2) { if (strcmp(prop_name, "drm_render_minor") == 0) { drm_render_minor = (int32_t)prop_val; break; } } if (!drm_render_minor) { ret = HSAKMT_STATUS_ERROR; goto err; } /* Open DRM Render device */ ret_value = open_drm_render_device(drm_render_minor); if (ret_value > 0) *is_node_supported = true; else if (ret_value != -ENOENT && ret_value != -EPERM) ret = HSAKMT_STATUS_ERROR; err: free(read_buf); fclose(fd); return ret; } HSAKMT_STATUS topology_sysfs_get_system_props(HsaSystemProperties *props) { FILE *fd; char *read_buf, *p; char prop_name[256]; unsigned long long prop_val; uint32_t prog; int read_size; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; bool is_node_supported = true; uint32_t num_supported_nodes = 0; assert(props); fd = fopen(KFD_SYSFS_PATH_SYSTEM_PROPERTIES, "r"); if (!fd) return HSAKMT_STATUS_ERROR; read_buf = malloc(PAGE_SIZE); if (!read_buf) { ret = HSAKMT_STATUS_NO_MEMORY; goto err1; } read_size = fread(read_buf, 1, PAGE_SIZE, fd); if (read_size <= 0) { ret = HSAKMT_STATUS_ERROR; goto err2; } /* Since we're using the buffer as a string, we make sure the string terminates */ if (read_size >= PAGE_SIZE) read_size = PAGE_SIZE - 1; read_buf[read_size] = 0; /* Read the system properties */ prog = 0; p = read_buf; while (sscanf(p += prog, "%s %llu\n%n", prop_name, &prop_val, &prog) == 2) { if (strcmp(prop_name, "platform_oem") == 0) props->PlatformOem = (uint32_t)prop_val; else if (strcmp(prop_name, "platform_id") == 0) props->PlatformId = (uint32_t)prop_val; else if (strcmp(prop_name, "platform_rev") == 0) props->PlatformRev = (uint32_t)prop_val; } /* * Discover the number of sysfs nodes: * Assuming that inside nodes folder there are only folders * which represent the node numbers */ num_sysfs_nodes = num_subdirs(KFD_SYSFS_PATH_NODES, ""); if (map_user_to_sysfs_node_id == NULL) { /* Trade off - num_sysfs_nodes includes all CPU and GPU nodes. * Slightly more memory is allocated than necessary. */ map_user_to_sysfs_node_id = calloc(num_sysfs_nodes, sizeof(uint32_t)); if (map_user_to_sysfs_node_id == NULL) { ret = HSAKMT_STATUS_NO_MEMORY; goto err2; } map_user_to_sysfs_node_id_size = num_sysfs_nodes; } else if (num_sysfs_nodes > map_user_to_sysfs_node_id_size) { free(map_user_to_sysfs_node_id); map_user_to_sysfs_node_id = calloc(num_sysfs_nodes, sizeof(uint32_t)); if (map_user_to_sysfs_node_id == NULL) { ret = HSAKMT_STATUS_NO_MEMORY; goto err2; } map_user_to_sysfs_node_id_size = num_sysfs_nodes; } for (uint32_t i = 0; i < num_sysfs_nodes; i++) { ret = topology_sysfs_check_node_supported(i, &is_node_supported); if (ret != HSAKMT_STATUS_SUCCESS) goto sysfs_parse_failed; if (is_node_supported) map_user_to_sysfs_node_id[num_supported_nodes++] = i; } props->NumNodes = num_supported_nodes; free(read_buf); fclose(fd); return ret; sysfs_parse_failed: free(map_user_to_sysfs_node_id); map_user_to_sysfs_node_id = NULL; err2: free(read_buf); err1: fclose(fd); return ret; } static const struct hsa_gfxip_table *find_hsa_gfxip_device(uint16_t device_id, uint8_t gfxv_major) { if (gfxv_major > 10) return NULL; uint32_t i, table_size; table_size = sizeof(gfxip_lookup_table)/sizeof(struct hsa_gfxip_table); for (i = 0; i < table_size; i++) { if (gfxip_lookup_table[i].device_id == device_id) return &gfxip_lookup_table[i]; } return NULL; } void topology_setup_is_dgpu_param(HsaNodeProperties *props) { /* if we found a dGPU node, then treat the whole system as dGPU */ if (!props->NumCPUCores && props->NumFComputeCores) is_dgpu = true; } bool topology_is_svm_needed(HSA_ENGINE_ID EngineId) { if (is_dgpu) return true; if (HSA_GET_GFX_VERSION_FULL(EngineId.ui32) >= GFX_VERSION_VEGA10) return true; return false; } static HSAKMT_STATUS topology_get_cpu_model_name(HsaNodeProperties *props, struct proc_cpuinfo *cpuinfo, int num_procs) { int i, j; if (!props) { pr_err("Invalid props to get cpu model name\n"); return HSAKMT_STATUS_INVALID_PARAMETER; } for (i = 0; i < num_procs; i++, cpuinfo++) { if (props->CComputeIdLo == cpuinfo->apicid) { if (!props->DeviceId) /* CPU-only node */ strncpy((char *)props->AMDName, cpuinfo->model_name, sizeof(props->AMDName)); /* Convert from UTF8 to UTF16 */ for (j = 0; cpuinfo->model_name[j] != '\0' && j < HSA_PUBLIC_NAME_SIZE - 1; j++) props->MarketingName[j] = cpuinfo->model_name[j]; props->MarketingName[j] = '\0'; return HSAKMT_STATUS_SUCCESS; } } return HSAKMT_STATUS_ERROR; } static int topology_search_processor_vendor(const char *processor_name) { unsigned int i; for (i = 0; i < ARRAY_LEN(supported_processor_vendor_name); i++) { if (!strcmp(processor_name, supported_processor_vendor_name[i])) return i; if (!strcmp(processor_name, "POWER9, altivec supported\n")) return IBM_POWER; } return -1; } /* topology_parse_cpuinfo - Parse /proc/cpuinfo and fill up required * topology information * cpuinfo [OUT]: output buffer to hold cpu information * num_procs: number of processors the output buffer can hold */ static HSAKMT_STATUS topology_parse_cpuinfo(struct proc_cpuinfo *cpuinfo, uint32_t num_procs) { HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; FILE *fd; char read_buf[256]; char *p; uint32_t proc = 0; size_t p_len; const char *proc_cpuinfo_path = "/proc/cpuinfo"; if (!cpuinfo) { pr_err("CPU information will be missing\n"); return HSAKMT_STATUS_INVALID_PARAMETER; } fd = fopen(proc_cpuinfo_path, "r"); if (!fd) { pr_err("Failed to open [%s]. Unable to get CPU information", proc_cpuinfo_path); return HSAKMT_STATUS_ERROR; } #ifdef __PPC64__ char *p2; /* Each line in /proc/cpuinfo that read_buf is constructed, the format * is like this: * "token : value\n" * where token is our target like vendor_id, model name, apicid ... * and value is the answer */ while (fgets(read_buf, sizeof(read_buf), fd)) { /* processor number */ if (!strncmp("processor ", read_buf, sizeof("processor ") - 1)) { p = strchr(read_buf, ':'); p += 2; /* remove ": " */ proc = atoi(p); if (proc >= num_procs) { pr_warn("cpuinfo contains processor %d larger than %u\n", proc, num_procs); ret = HSAKMT_STATUS_NO_MEMORY; goto exit; } continue; } /* vendor name / model name */ if (!strncmp("cpu ", read_buf, sizeof("cpu ") - 1) && (processor_vendor == -1)) { p = strchr(read_buf, ':'); p += 2; /* remove ": " */ processor_vendor = topology_search_processor_vendor(p); p2 = strchr(p, ','); if (p2 != NULL) { p2++; *p2 = 0; } if (strlen(p) < HSA_PUBLIC_NAME_SIZE) { /* -1 to remove \n from p */ strncpy(cpuinfo[proc].model_name, p, strlen(p) - 1); cpuinfo[proc].model_name[strlen(p) - 1] = '\0'; } else strncpy(cpuinfo[proc].model_name, p, HSA_PUBLIC_NAME_SIZE); continue; } } #else /* Each line in /proc/cpuinfo that read_buf is constructed, the format * is like this: * "token : value\n" * where token is our target like vendor_id, model name, apicid ... * and value is the answer */ while (fgets(read_buf, sizeof(read_buf), fd)) { /* processor number */ if (!strncmp("processor", read_buf, sizeof("processor") - 1)) { p = strchr(read_buf, ':'); p += 2; /* remove ": " */ proc = atoi(p); if (proc >= num_procs) { pr_warn("cpuinfo contains processor %d larger than %u\n", proc, num_procs); ret = HSAKMT_STATUS_NO_MEMORY; goto exit; } continue; } /* vendor name */ if (!strncmp("vendor_id", read_buf, sizeof("vendor_id") - 1) && (processor_vendor == -1)) { p = strchr(read_buf, ':'); p += 2; /* remove ": " */ processor_vendor = topology_search_processor_vendor(p); continue; } /* model name */ if (!strncmp("model name", read_buf, sizeof("model name") - 1)) { p = strchr(read_buf, ':'); p += 2; /* remove ": " */ p_len = strlen(p); if (p_len > HSA_PUBLIC_NAME_SIZE) p_len = HSA_PUBLIC_NAME_SIZE; memcpy(cpuinfo[proc].model_name, p, p_len); cpuinfo[proc].model_name[p_len - 1] = '\0'; continue; } /* apicid */ if (!strncmp("apicid", read_buf, sizeof("apicid") - 1)) { p = strchr(read_buf, ':'); p += 2; /* remove ": " */ cpuinfo[proc].apicid = atoi(p); } } #endif if (processor_vendor < 0) { pr_err("Failed to get Processor Vendor. Setting to %s", supported_processor_vendor_name[GENUINE_INTEL]); processor_vendor = GENUINE_INTEL; } exit: fclose(fd); return ret; } static int topology_get_node_props_from_drm(HsaNodeProperties *props) { int drm_fd; uint32_t major_version; uint32_t minor_version; amdgpu_device_handle device_handle; struct amdgpu_gpu_info gpu_info; const char *name; int i, ret = 0; if (props == NULL) return -1; drm_fd = drmOpenRender(props->DrmRenderMinor); if (drm_fd < 0) return -1; if (amdgpu_device_initialize(drm_fd, &major_version, &minor_version, &device_handle) < 0) { ret = -1; goto err_device_initialize; } name = amdgpu_get_marketing_name(device_handle); if (name != NULL) { for (i = 0; name[i] != 0 && i < HSA_PUBLIC_NAME_SIZE - 1; i++) props->MarketingName[i] = name[i]; props->MarketingName[i] = '\0'; } if (amdgpu_query_gpu_info(device_handle, &gpu_info)) { ret = -1; goto err_query_gpu_info; } props->FamilyID = gpu_info.family_id; err_query_gpu_info: amdgpu_device_deinitialize(device_handle); err_device_initialize: drmClose(drm_fd); return ret; } static HSAKMT_STATUS topology_sysfs_get_node_props(uint32_t node_id, HsaNodeProperties *props, bool *p2p_links, uint32_t *num_p2pLinks) { FILE *fd; char *read_buf, *p, *envvar, dummy = '\0'; char prop_name[256]; char path[256]; unsigned long long prop_val = 0; uint32_t prog, major = 0, minor = 0, step = 0; int read_size; const struct hsa_gfxip_table *hsa_gfxip; uint32_t sys_node_id; uint32_t gfxv = 0; uint8_t gfxv_major, gfxv_minor, gfxv_stepping; uint32_t simd_arrays_count = 0; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; assert(props); ret = topology_sysfs_map_node_id(node_id, &sys_node_id); if (ret != HSAKMT_STATUS_SUCCESS) return ret; /* Retrieve the GPU ID */ ret = topology_sysfs_get_gpu_id(sys_node_id, &props->KFDGpuID); if (ret != HSAKMT_STATUS_SUCCESS) return ret; read_buf = malloc(PAGE_SIZE); if (!read_buf) return HSAKMT_STATUS_NO_MEMORY; /* Retrieve the node properties */ snprintf(path, 256, "%s/%d/properties", KFD_SYSFS_PATH_NODES, sys_node_id); fd = fopen(path, "r"); if (!fd) { free(read_buf); return HSAKMT_STATUS_ERROR; } read_size = fread(read_buf, 1, PAGE_SIZE, fd); if (read_size <= 0) { ret = HSAKMT_STATUS_ERROR; goto out; } /* Since we're using the buffer as a string, we make sure the string terminates */ if (read_size >= PAGE_SIZE) read_size = PAGE_SIZE - 1; read_buf[read_size] = 0; /* Read the node properties */ prog = 0; p = read_buf; while (sscanf(p += prog, "%s %llu\n%n", prop_name, &prop_val, &prog) == 2) { if (strcmp(prop_name, "cpu_cores_count") == 0) props->NumCPUCores = (uint32_t)prop_val; else if (strcmp(prop_name, "simd_count") == 0) props->NumFComputeCores = (uint32_t)prop_val; else if (strcmp(prop_name, "mem_banks_count") == 0) props->NumMemoryBanks = (uint32_t)prop_val; else if (strcmp(prop_name, "caches_count") == 0) props->NumCaches = (uint32_t)prop_val; else if (strcmp(prop_name, "io_links_count") == 0) props->NumIOLinks = (uint32_t)prop_val; else if (strcmp(prop_name, "p2p_links_count") == 0) { props->NumIOLinks += (uint32_t)prop_val; if (num_p2pLinks) *num_p2pLinks = (uint32_t)prop_val; if (p2p_links) *p2p_links = true; } else if (strcmp(prop_name, "cpu_core_id_base") == 0) props->CComputeIdLo = (uint32_t)prop_val; else if (strcmp(prop_name, "simd_id_base") == 0) props->FComputeIdLo = (uint32_t)prop_val; else if (strcmp(prop_name, "capability") == 0) props->Capability.Value = (uint32_t)prop_val; else if (strcmp(prop_name, "debug_prop") == 0) props->DebugProperties.Value = (uint64_t)prop_val; else if (strcmp(prop_name, "max_waves_per_simd") == 0) props->MaxWavesPerSIMD = (uint32_t)prop_val; else if (strcmp(prop_name, "lds_size_in_kb") == 0) props->LDSSizeInKB = (uint32_t)prop_val; else if (strcmp(prop_name, "gds_size_in_kb") == 0) props->GDSSizeInKB = (uint32_t)prop_val; else if (strcmp(prop_name, "wave_front_size") == 0) props->WaveFrontSize = (uint32_t)prop_val; else if (strcmp(prop_name, "array_count") == 0) simd_arrays_count = (uint32_t)prop_val; else if (strcmp(prop_name, "simd_arrays_per_engine") == 0) props->NumArrays = (uint32_t)prop_val; else if (strcmp(prop_name, "cu_per_simd_array") == 0) props->NumCUPerArray = (uint32_t)prop_val; else if (strcmp(prop_name, "simd_per_cu") == 0) props->NumSIMDPerCU = (uint32_t)prop_val; else if (strcmp(prop_name, "max_slots_scratch_cu") == 0) props->MaxSlotsScratchCU = (uint32_t)prop_val; else if (strcmp(prop_name, "fw_version") == 0) props->EngineId.Value = (uint32_t)prop_val & 0x3ff; else if (strcmp(prop_name, "vendor_id") == 0) props->VendorId = (uint32_t)prop_val; else if (strcmp(prop_name, "device_id") == 0) props->DeviceId = (uint32_t)prop_val; else if (strcmp(prop_name, "location_id") == 0) props->LocationId = (uint32_t)prop_val; else if (strcmp(prop_name, "domain") == 0) props->Domain = (uint32_t)prop_val; else if (strcmp(prop_name, "max_engine_clk_fcompute") == 0) props->MaxEngineClockMhzFCompute = (uint32_t)prop_val; else if (strcmp(prop_name, "max_engine_clk_ccompute") == 0) props->MaxEngineClockMhzCCompute = (uint32_t)prop_val; else if (strcmp(prop_name, "local_mem_size") == 0) props->LocalMemSize = prop_val; else if (strcmp(prop_name, "drm_render_minor") == 0) props->DrmRenderMinor = (int32_t)prop_val; else if (strcmp(prop_name, "sdma_fw_version") == 0) props->uCodeEngineVersions.Value = (uint32_t)prop_val & 0x3ff; else if (strcmp(prop_name, "hive_id") == 0) props->HiveID = prop_val; else if (strcmp(prop_name, "unique_id") == 0) props->UniqueID = prop_val; else if (strcmp(prop_name, "num_sdma_engines") == 0) props->NumSdmaEngines = prop_val; else if (strcmp(prop_name, "num_sdma_xgmi_engines") == 0) props->NumSdmaXgmiEngines = prop_val; else if (strcmp(prop_name, "num_gws") == 0) props->NumGws = prop_val; else if (strcmp(prop_name, "num_sdma_queues_per_engine") == 0) props->NumSdmaQueuesPerEngine = prop_val; else if (strcmp(prop_name, "num_cp_queues") == 0) props->NumCpQueues = prop_val; else if (strcmp(prop_name, "num_xcc") == 0) props->NumXcc = prop_val; else if (strcmp(prop_name, "gfx_target_version") == 0) gfxv = (uint32_t)prop_val; } /* Bail out early, if a CPU node */ if (!props->NumFComputeCores) goto out; if (props->NumArrays != 0) props->NumShaderBanks = simd_arrays_count/props->NumArrays; gfxv_major = HSA_GET_GFX_VERSION_MAJOR(gfxv); gfxv_minor = HSA_GET_GFX_VERSION_MINOR(gfxv); gfxv_stepping = HSA_GET_GFX_VERSION_STEP(gfxv); hsa_gfxip = find_hsa_gfxip_device(props->DeviceId, gfxv_major); if (hsa_gfxip || gfxv) { envvar = getenv("HSA_OVERRIDE_GFX_VERSION"); if (envvar) { /* HSA_OVERRIDE_GFX_VERSION=major.minor.stepping */ if ((sscanf(envvar, "%u.%u.%u%c", &major, &minor, &step, &dummy) != 3) || (major > 63 || minor > 255 || step > 255)) { pr_err("HSA_OVERRIDE_GFX_VERSION %s is invalid\n", envvar); ret = HSAKMT_STATUS_ERROR; goto out; } props->EngineId.ui32.Major = major & 0x3f; props->EngineId.ui32.Minor = minor & 0xff; props->EngineId.ui32.Stepping = step & 0xff; } else if (hsa_gfxip) { props->EngineId.ui32.Major = hsa_gfxip->major & 0x3f; props->EngineId.ui32.Minor = hsa_gfxip->minor & 0xff; props->EngineId.ui32.Stepping = hsa_gfxip->stepping & 0xff; } else { props->EngineId.ui32.Major = gfxv_major & 0x3f; props->EngineId.ui32.Minor = gfxv_minor & 0xff; props->EngineId.ui32.Stepping = gfxv_stepping & 0xff; } /* Set the CAL name of the node. If DID-based hsa_gfxip lookup was * successful, use that name. Otherwise, set to GFX. */ if (hsa_gfxip && hsa_gfxip->amd_name) strncpy((char *)props->AMDName, hsa_gfxip->amd_name, sizeof(props->AMDName)-1); else snprintf((char *)props->AMDName, sizeof(props->AMDName)-1, "GFX%06x", HSA_GET_GFX_VERSION_FULL(props->EngineId.ui32)); /* Is dGPU Node, not APU * Retrieve the marketing name of the node. */ if (topology_get_node_props_from_drm(props)) pr_info("failed to get marketing name for device ID 0x%x\n", props->DeviceId); /* Get VGPR/SGPR size in byte per CU */ props->SGPRSizePerCU = SGPR_SIZE_PER_CU; props->VGPRSizePerCU = get_vgpr_size_per_cu(HSA_GET_GFX_VERSION_FULL(props->EngineId.ui32)); } else if (props->DeviceId) /* still return success */ pr_err("device ID 0x%x is not supported in libhsakmt\n", props->DeviceId); if (props->NumFComputeCores) assert(props->EngineId.ui32.Major && "HSA_OVERRIDE_GFX_VERSION may be needed"); /* On Older kernels, num_xcc may not be present in system properties. * Set it to 1 if system properties do not report num_xcc. */ if (!props->NumXcc) props->NumXcc = 1; out: free(read_buf); fclose(fd); return ret; } static HSAKMT_STATUS topology_sysfs_get_mem_props(uint32_t node_id, uint32_t mem_id, HsaMemoryProperties *props) { FILE *fd; char *read_buf, *p; char prop_name[256]; char path[256]; unsigned long long prop_val; uint32_t prog; int read_size; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; uint32_t sys_node_id; assert(props); ret = topology_sysfs_map_node_id(node_id, &sys_node_id); if (ret != HSAKMT_STATUS_SUCCESS) return ret; snprintf(path, 256, "%s/%d/mem_banks/%d/properties", KFD_SYSFS_PATH_NODES, sys_node_id, mem_id); fd = fopen(path, "r"); if (!fd) return HSAKMT_STATUS_ERROR; read_buf = malloc(PAGE_SIZE); if (!read_buf) { ret = HSAKMT_STATUS_NO_MEMORY; goto err1; } read_size = fread(read_buf, 1, PAGE_SIZE, fd); if (read_size <= 0) { ret = HSAKMT_STATUS_ERROR; goto err2; } /* Since we're using the buffer as a string, we make sure the string terminates */ if (read_size >= PAGE_SIZE) read_size = PAGE_SIZE - 1; read_buf[read_size] = 0; prog = 0; p = read_buf; while (sscanf(p += prog, "%s %llu\n%n", prop_name, &prop_val, &prog) == 2) { if (strcmp(prop_name, "heap_type") == 0) props->HeapType = (uint32_t)prop_val; else if (strcmp(prop_name, "size_in_bytes") == 0) props->SizeInBytes = (uint64_t)prop_val; else if (strcmp(prop_name, "flags") == 0) props->Flags.MemoryProperty = (uint32_t)prop_val; else if (strcmp(prop_name, "width") == 0) props->Width = (uint32_t)prop_val; else if (strcmp(prop_name, "mem_clk_max") == 0) props->MemoryClockMax = (uint32_t)prop_val; } err2: free(read_buf); err1: fclose(fd); return ret; } /* topology_destroy_temp_cpu_cache_list - * Free the memory allocated in topology_create_temp_cpu_cache_list(). */ static void topology_destroy_temp_cpu_cache_list( cpu_cacheinfo_t *temp_cpu_ci_list) { uint32_t n; cpu_cacheinfo_t *p_temp_cpu_ci_list = temp_cpu_ci_list; cpu_cacheinfo_t *cpu_ci = p_temp_cpu_ci_list; if (p_temp_cpu_ci_list) { for (n = 0; n < p_temp_cpu_ci_list->len; n++, cpu_ci++) free(cpu_ci->cache_prop); free(p_temp_cpu_ci_list); } p_temp_cpu_ci_list = NULL; } /* topology_create_temp_cpu_cache_list - Create a temporary cpu-cache list to * store cpu cache information. This list will be used to copy * HsaCacheProperties in the CPU node. Two buffers are allocated * inside this function: cpu_ci list and cache_prop under each * cpu_ci. Must call topology_destroy_temp_cpu_cache_list to free * the memory after the information is copied. * @node [IN] CPU node number * @cpuinfo [IN] /proc/cpuinfo data * @temp_cpu_ci_list [OUT] cpu-cache-info list with data filled * Return: total number of caches under this CPU node */ static int topology_create_temp_cpu_cache_list(int node, struct proc_cpuinfo *cpuinfo, cpu_cacheinfo_t **temp_cpu_ci_list) { /* Get max path size from /sys/devices/system/node/node%d/%s/cache * below, which will max out according to the largest filename, * which can be present twice in the string above. 29 is for the prefix * and the +6 is for the cache suffix */ const uint32_t MAXPATHSIZE = 29 + MAXNAMLEN + (MAXNAMLEN + 6); cpu_cacheinfo_t *p_temp_cpu_ci_list; /* a list of cpu_ci */ char path[MAXPATHSIZE], node_dir[MAXPATHSIZE]; int max_cpus; cpu_cacheinfo_t *this_cpu; /* one cpu_ci in cpu_ci_list */ int cache_cnt = 0; DIR *dirp = NULL; struct dirent *dir; char *p; if (!temp_cpu_ci_list) { pr_err("Invalid temp_cpu_ci_list\n"); goto exit; } *temp_cpu_ci_list = NULL; /* Get info from /sys/devices/system/node/nodeX/cpuY/cache */ int node_real = node; if (processor_vendor == IBM_POWER) { if (!strcmp(cpuinfo[0].model_name, "POWER9")) { node_real = node * 8; } } snprintf(node_dir, MAXPATHSIZE, "/sys/devices/system/node/node%d", node_real); /* Other than cpuY folders, this dir also has cpulist and cpumap */ max_cpus = num_subdirs(node_dir, "cpu"); if (max_cpus <= 0) { /* If CONFIG_NUMA is not enabled in the kernel, * /sys/devices/system/node doesn't exist. */ if (node) { /* CPU node must be 0 or something is wrong */ pr_err("Fail to get cpu* dirs under %s.", node_dir); goto exit; } /* Fall back to use /sys/devices/system/cpu */ snprintf(node_dir, MAXPATHSIZE, "/sys/devices/system/cpu"); max_cpus = num_subdirs(node_dir, "cpu"); if (max_cpus <= 0) { pr_err("Fail to get cpu* dirs under %s\n", node_dir); goto exit; } } p_temp_cpu_ci_list = calloc(max_cpus, sizeof(cpu_cacheinfo_t)); if (!p_temp_cpu_ci_list) { pr_err("Fail to allocate p_temp_cpu_ci_list\n"); goto exit; } p_temp_cpu_ci_list->len = 0; this_cpu = p_temp_cpu_ci_list; dirp = opendir(node_dir); while ((dir = readdir(dirp)) != 0) { if (strncmp(dir->d_name, "cpu", 3)) continue; if (!isdigit(dir->d_name[3])) /* ignore files like cpulist */ continue; snprintf(path, MAXPATHSIZE, "%s/%s/cache", node_dir, dir->d_name); this_cpu->num_caches = num_subdirs(path, "index"); this_cpu->cache_prop = calloc(this_cpu->num_caches, sizeof(HsaCacheProperties)); if (!this_cpu->cache_prop) { pr_err("Fail to allocate cache_info\n"); goto exit; } p = &dir->d_name[3]; this_cpu->proc_num = atoi(p); cache_cnt += get_cpu_cache_info(path, cpuinfo, this_cpu); ++p_temp_cpu_ci_list->len; ++this_cpu; } *temp_cpu_ci_list = p_temp_cpu_ci_list; exit: if (dirp) closedir(dirp); return cache_cnt; } /* topology_get_cpu_cache_props - Read CPU cache information from sysfs * @node [IN] CPU node number * @cpuinfo [IN] /proc/cpuinfo data * @tbl [OUT] the node table to fill up * Return: HSAKMT_STATUS_SUCCESS in success or error number in failure */ static HSAKMT_STATUS topology_get_cpu_cache_props(int node, struct proc_cpuinfo *cpuinfo, node_props_t *tbl) { HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; cpu_cacheinfo_t *cpu_ci_list = NULL; uint32_t n, cache_cnt, i; cpu_cacheinfo_t *cpu_ci; HsaCacheProperties *this_cache; tbl->node.NumCaches = topology_create_temp_cpu_cache_list( node, cpuinfo, &cpu_ci_list); if (!tbl->node.NumCaches) { pr_err("Fail to get cache info for node %d\n", node); ret = HSAKMT_STATUS_ERROR; goto exit; } tbl->cache = calloc(tbl->node.NumCaches, sizeof(HsaCacheProperties)); if (!tbl->cache) { ret = HSAKMT_STATUS_NO_MEMORY; goto exit; } /* Now fill in the information to cache properties. */ cache_cnt = 0; cpu_ci = cpu_ci_list; for (n = 0; n < cpu_ci_list->len; n++, cpu_ci++) { this_cache = cpu_ci->cache_prop; for (i = 0; i < cpu_ci->num_caches; i++, this_cache++) { memcpy(&tbl->cache[cache_cnt++], this_cache, sizeof(HsaCacheProperties)); if (cache_cnt >= tbl->node.NumCaches) goto exit; } } exit: topology_destroy_temp_cpu_cache_list(cpu_ci_list); return ret; } static HSAKMT_STATUS topology_sysfs_get_cache_props(uint32_t node_id, uint32_t cache_id, HsaCacheProperties *props) { FILE *fd; char *read_buf, *p; char prop_name[256]; char path[256]; unsigned long long prop_val; uint32_t i, prog; int read_size; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; uint32_t sys_node_id; assert(props); ret = topology_sysfs_map_node_id(node_id, &sys_node_id); if (ret != HSAKMT_STATUS_SUCCESS) return ret; snprintf(path, 256, "%s/%d/caches/%d/properties", KFD_SYSFS_PATH_NODES, sys_node_id, cache_id); fd = fopen(path, "r"); if (!fd) return HSAKMT_STATUS_ERROR; read_buf = malloc(PAGE_SIZE); if (!read_buf) { ret = HSAKMT_STATUS_NO_MEMORY; goto err1; } read_size = fread(read_buf, 1, PAGE_SIZE, fd); if (read_size <= 0) { ret = HSAKMT_STATUS_ERROR; goto err2; } /* Since we're using the buffer as a string, we make sure the string terminates */ if (read_size >= PAGE_SIZE) read_size = PAGE_SIZE - 1; read_buf[read_size] = 0; prog = 0; p = read_buf; while (sscanf(p += prog, "%s %llu\n%n", prop_name, &prop_val, &prog) == 2) { if (strcmp(prop_name, "processor_id_low") == 0) props->ProcessorIdLow = (uint32_t)prop_val; else if (strcmp(prop_name, "level") == 0) props->CacheLevel = (uint32_t)prop_val; else if (strcmp(prop_name, "size") == 0) props->CacheSize = (uint32_t)prop_val; else if (strcmp(prop_name, "cache_line_size") == 0) props->CacheLineSize = (uint32_t)prop_val; else if (strcmp(prop_name, "cache_lines_per_tag") == 0) props->CacheLinesPerTag = (uint32_t)prop_val; else if (strcmp(prop_name, "association") == 0) props->CacheAssociativity = (uint32_t)prop_val; else if (strcmp(prop_name, "latency") == 0) props->CacheLatency = (uint32_t)prop_val; else if (strcmp(prop_name, "type") == 0) props->CacheType.Value = (uint32_t)prop_val; else if (strcmp(prop_name, "sibling_map") == 0) break; } prog = 0; if ((sscanf(p, "sibling_map %n", &prog)) == 0 && prog) { i = 0; while ((i < HSA_CPU_SIBLINGS) && (sscanf(p += prog, "%u%*[,\n]%n", &props->SiblingMap[i++], &prog) == 1)) continue; } err2: free(read_buf); err1: fclose(fd); return ret; } static HSAKMT_STATUS topology_map_sysfs_to_user_node_id(uint32_t sys_node_id, uint32_t *user_node_id) { uint32_t node_id; for (node_id = 0; node_id < map_user_to_sysfs_node_id_size; node_id++) if (map_user_to_sysfs_node_id[node_id] == sys_node_id) { *user_node_id = node_id; return HSAKMT_STATUS_SUCCESS; } return HSAKMT_STATUS_INVALID_NODE_UNIT; } /* For a give Node @node_id the function gets @iolink_id information i.e. parses sysfs the following sysfs entry * ./nodes/@node_id/io_links/@iolink_id/properties. @node_id has to be valid accessible node. * * If node_to specified by the @iolink_id is not accessible the function returns HSAKMT_STATUS_NOT_SUPPORTED. * If node_to is accessible, then node_to is mapped from sysfs_node to user_node and returns HSAKMT_STATUS_SUCCESS. */ static HSAKMT_STATUS topology_sysfs_get_iolink_props(uint32_t node_id, uint32_t iolink_id, HsaIoLinkProperties *props, bool p2pLink) { FILE *fd; char *read_buf, *p; char prop_name[256]; char path[256]; unsigned long long prop_val; uint32_t prog; int read_size; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; uint32_t sys_node_id; assert(props); ret = topology_sysfs_map_node_id(node_id, &sys_node_id); if (ret != HSAKMT_STATUS_SUCCESS) return ret; if (p2pLink) snprintf(path, 256, "%s/%d/p2p_links/%d/properties", KFD_SYSFS_PATH_NODES, sys_node_id, iolink_id); else snprintf(path, 256, "%s/%d/io_links/%d/properties", KFD_SYSFS_PATH_NODES, sys_node_id, iolink_id); fd = fopen(path, "r"); if (!fd) return HSAKMT_STATUS_ERROR; read_buf = malloc(PAGE_SIZE); if (!read_buf) { ret = HSAKMT_STATUS_NO_MEMORY; goto err1; } read_size = fread(read_buf, 1, PAGE_SIZE, fd); if (read_size <= 0) { ret = (errno == EPERM) ? HSAKMT_STATUS_NOT_SUPPORTED : HSAKMT_STATUS_ERROR; goto err2; } /* Since we're using the buffer as a string, we make sure the string terminates */ if (read_size >= PAGE_SIZE) read_size = PAGE_SIZE - 1; read_buf[read_size] = 0; prog = 0; p = read_buf; while (sscanf(p += prog, "%s %llu\n%n", prop_name, &prop_val, &prog) == 2) { if (strcmp(prop_name, "type") == 0) props->IoLinkType = (uint32_t)prop_val; else if (strcmp(prop_name, "version_major") == 0) props->VersionMajor = (uint32_t)prop_val; else if (strcmp(prop_name, "version_minor") == 0) props->VersionMinor = (uint32_t)prop_val; else if (strcmp(prop_name, "node_from") == 0) { if (sys_node_id != (uint32_t)prop_val) { ret = HSAKMT_STATUS_INVALID_NODE_UNIT; goto err2; } props->NodeFrom = node_id; } else if (strcmp(prop_name, "node_to") == 0) { bool is_node_supported; uint32_t sysfs_node_id; sysfs_node_id = (uint32_t)prop_val; ret = topology_sysfs_check_node_supported(sysfs_node_id, &is_node_supported); if (!is_node_supported) { ret = HSAKMT_STATUS_NOT_SUPPORTED; memset(props, 0, sizeof(*props)); goto err2; } ret = topology_map_sysfs_to_user_node_id(sysfs_node_id, &props->NodeTo); if (ret != HSAKMT_STATUS_SUCCESS) goto err2; } else if (strcmp(prop_name, "weight") == 0) props->Weight = (uint32_t)prop_val; else if (strcmp(prop_name, "min_latency") == 0) props->MinimumLatency = (uint32_t)prop_val; else if (strcmp(prop_name, "max_latency") == 0) props->MaximumLatency = (uint32_t)prop_val; else if (strcmp(prop_name, "min_bandwidth") == 0) props->MinimumBandwidth = (uint32_t)prop_val; else if (strcmp(prop_name, "max_bandwidth") == 0) props->MaximumBandwidth = (uint32_t)prop_val; else if (strcmp(prop_name, "recommended_transfer_size") == 0) props->RecTransferSize = (uint32_t)prop_val; else if (strcmp(prop_name, "flags") == 0) props->Flags.LinkProperty = (uint32_t)prop_val; } err2: free(read_buf); err1: fclose(fd); return ret; } /* topology_get_free_io_link_slot_for_node - For the given node_id, find the * next available free slot to add an io_link */ static HsaIoLinkProperties *topology_get_free_io_link_slot_for_node(uint32_t node_id, const HsaSystemProperties *sys_props, node_props_t *node_props) { HsaIoLinkProperties *props; if (node_id >= sys_props->NumNodes) { pr_err("Invalid node [%d]\n", node_id); return NULL; } props = node_props[node_id].link; if (!props) { pr_err("No io_link reported for Node [%d]\n", node_id); return NULL; } if (node_props[node_id].node.NumIOLinks >= sys_props->NumNodes - 1) { pr_err("No more space for io_link for Node [%d]\n", node_id); return NULL; } return &props[node_props[node_id].node.NumIOLinks]; } /* topology_add_io_link_for_node - If a free slot is available, * add io_link for the given Node. * TODO: Add other members of HsaIoLinkProperties */ static HSAKMT_STATUS topology_add_io_link_for_node(uint32_t node_from, const HsaSystemProperties *sys_props, node_props_t *node_props, HSA_IOLINKTYPE IoLinkType, uint32_t node_to, uint32_t Weight) { HsaIoLinkProperties *props; props = topology_get_free_io_link_slot_for_node(node_from, sys_props, node_props); if (!props) return HSAKMT_STATUS_NO_MEMORY; props->IoLinkType = IoLinkType; props->NodeFrom = node_from; props->NodeTo = node_to; props->Weight = Weight; node_props[node_from].node.NumIOLinks++; return HSAKMT_STATUS_SUCCESS; } /* Find the CPU that this GPU (gpu_node) directly connects to */ static int32_t gpu_get_direct_link_cpu(uint32_t gpu_node, node_props_t *node_props) { HsaIoLinkProperties *props = node_props[gpu_node].link; uint32_t i; if (!node_props[gpu_node].node.KFDGpuID || !props || node_props[gpu_node].node.NumIOLinks == 0) return -1; for (i = 0; i < node_props[gpu_node].node.NumIOLinks; i++) if (props[i].IoLinkType == HSA_IOLINKTYPE_PCIEXPRESS && props[i].Weight <= 20) /* >20 is GPU->CPU->GPU */ return props[i].NodeTo; return -1; } /* Get node1->node2 IO link information. This should be a direct link that has * been created in the kernel. */ static HSAKMT_STATUS get_direct_iolink_info(uint32_t node1, uint32_t node2, node_props_t *node_props, HSAuint32 *weight, HSA_IOLINKTYPE *type) { HsaIoLinkProperties *props = node_props[node1].link; uint32_t i; if (!props) return HSAKMT_STATUS_INVALID_NODE_UNIT; for (i = 0; i < node_props[node1].node.NumIOLinks; i++) if (props[i].NodeTo == node2) { if (weight) *weight = props[i].Weight; if (type) *type = props[i].IoLinkType; return HSAKMT_STATUS_SUCCESS; } return HSAKMT_STATUS_INVALID_PARAMETER; } static HSAKMT_STATUS get_indirect_iolink_info(uint32_t node1, uint32_t node2, node_props_t *node_props, HSAuint32 *weight, HSA_IOLINKTYPE *type) { int32_t dir_cpu1 = -1, dir_cpu2 = -1; HSAuint32 weight1 = 0, weight2 = 0, weight3 = 0; HSAKMT_STATUS ret; uint32_t i; *weight = 0; *type = HSA_IOLINKTYPE_UNDEFINED; if (node1 == node2) return HSAKMT_STATUS_INVALID_PARAMETER; /* CPU->CPU is not an indirect link */ if (!node_props[node1].node.KFDGpuID && !node_props[node2].node.KFDGpuID) return HSAKMT_STATUS_INVALID_NODE_UNIT; if (node_props[node1].node.HiveID && node_props[node2].node.HiveID && node_props[node1].node.HiveID == node_props[node2].node.HiveID) return HSAKMT_STATUS_INVALID_PARAMETER; if (node_props[node1].node.KFDGpuID) dir_cpu1 = gpu_get_direct_link_cpu(node1, node_props); if (node_props[node2].node.KFDGpuID) dir_cpu2 = gpu_get_direct_link_cpu(node2, node_props); if (dir_cpu1 < 0 && dir_cpu2 < 0) return HSAKMT_STATUS_ERROR; /* if the node2(dst) is GPU , it need to be large bar for host access*/ if (node_props[node2].node.KFDGpuID) { for (i = 0; i < node_props[node2].node.NumMemoryBanks; ++i) if (node_props[node2].mem[i].HeapType == HSA_HEAPTYPE_FRAME_BUFFER_PUBLIC) break; if (i >= node_props[node2].node.NumMemoryBanks) return HSAKMT_STATUS_ERROR; } /* Possible topology: * GPU --(weight1) -- CPU -- (weight2) -- GPU * GPU --(weight1) -- CPU -- (weight2) -- CPU -- (weight3) -- GPU * GPU --(weight1) -- CPU -- (weight2) -- CPU * CPU -- (weight2) -- CPU -- (weight3) -- GPU */ if (dir_cpu1 >= 0) { /* GPU->CPU ... */ if (dir_cpu2 >= 0) { if (dir_cpu1 == dir_cpu2) /* GPU->CPU->GPU*/ { ret = get_direct_iolink_info(node1, dir_cpu1, node_props, &weight1, NULL); if (ret != HSAKMT_STATUS_SUCCESS) return ret; ret = get_direct_iolink_info(dir_cpu1, node2, node_props, &weight2, type); } else /* GPU->CPU->CPU->GPU*/ { ret = get_direct_iolink_info(node1, dir_cpu1, node_props, &weight1, NULL); if (ret != HSAKMT_STATUS_SUCCESS) return ret; ret = get_direct_iolink_info(dir_cpu1, dir_cpu2, node_props, &weight2, type); if (ret != HSAKMT_STATUS_SUCCESS) return ret; /* On QPI interconnection, GPUs can't access * each other if they are attached to different * CPU sockets. CPU<->CPU weight larger than 20 * means the two CPUs are in different sockets. */ if (*type == HSA_IOLINK_TYPE_QPI_1_1 && weight2 > 20) return HSAKMT_STATUS_NOT_SUPPORTED; ret = get_direct_iolink_info(dir_cpu2, node2, node_props, &weight3, NULL); } } else /* GPU->CPU->CPU */ { ret = get_direct_iolink_info(node1, dir_cpu1, node_props, &weight1, NULL); if (ret != HSAKMT_STATUS_SUCCESS) return ret; ret = get_direct_iolink_info(dir_cpu1, node2, node_props, &weight2, type); } } else { /* CPU->CPU->GPU */ ret = get_direct_iolink_info(node1, dir_cpu2, node_props, &weight2, type); if (ret != HSAKMT_STATUS_SUCCESS) return ret; ret = get_direct_iolink_info(dir_cpu2, node2, node_props, &weight3, NULL); } if (ret != HSAKMT_STATUS_SUCCESS) return ret; *weight = weight1 + weight2 + weight3; return HSAKMT_STATUS_SUCCESS; } static void topology_create_indirect_gpu_links(const HsaSystemProperties *sys_props, node_props_t *node_props) { uint32_t i, j; HSAuint32 weight; HSA_IOLINKTYPE type; for (i = 0; i < sys_props->NumNodes - 1; i++) { for (j = i + 1; j < sys_props->NumNodes; j++) { get_indirect_iolink_info(i, j, node_props, &weight, &type); if (!weight) goto try_alt_dir; if (topology_add_io_link_for_node(i, sys_props, node_props, type, j, weight) != HSAKMT_STATUS_SUCCESS) pr_err("Fail to add IO link %d->%d\n", i, j); try_alt_dir: get_indirect_iolink_info(j, i, node_props, &weight, &type); if (!weight) continue; if (topology_add_io_link_for_node(j, sys_props, node_props, type, i, weight) != HSAKMT_STATUS_SUCCESS) pr_err("Fail to add IO link %d->%d\n", j, i); } } } HSAKMT_STATUS topology_take_snapshot(void) { uint32_t gen_start, gen_end, i, mem_id, cache_id; HsaSystemProperties sys_props; node_props_t *temp_props = 0; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; struct proc_cpuinfo *cpuinfo; const uint32_t num_procs = get_nprocs(); uint32_t num_ioLinks; bool p2p_links = false; uint32_t num_p2pLinks = 0; cpuinfo = calloc(num_procs, sizeof(struct proc_cpuinfo)); if (!cpuinfo) { pr_err("Fail to allocate memory for CPU info\n"); return HSAKMT_STATUS_NO_MEMORY; } topology_parse_cpuinfo(cpuinfo, num_procs); retry: ret = topology_sysfs_get_generation(&gen_start); if (ret != HSAKMT_STATUS_SUCCESS) goto err; ret = topology_sysfs_get_system_props(&sys_props); if (ret != HSAKMT_STATUS_SUCCESS) goto err; if (sys_props.NumNodes > 0) { temp_props = calloc(sys_props.NumNodes * sizeof(node_props_t), 1); if (!temp_props) { ret = HSAKMT_STATUS_NO_MEMORY; goto err; } for (i = 0; i < sys_props.NumNodes; i++) { ret = topology_sysfs_get_node_props(i, &temp_props[i].node, &p2p_links, &num_p2pLinks); if (ret != HSAKMT_STATUS_SUCCESS) { free_properties(temp_props, i); goto err; } if (temp_props[i].node.NumCPUCores) topology_get_cpu_model_name(&temp_props[i].node, cpuinfo, num_procs); if (temp_props[i].node.NumMemoryBanks) { temp_props[i].mem = calloc(temp_props[i].node.NumMemoryBanks * sizeof(HsaMemoryProperties), 1); if (!temp_props[i].mem) { ret = HSAKMT_STATUS_NO_MEMORY; free_properties(temp_props, i + 1); goto err; } for (mem_id = 0; mem_id < temp_props[i].node.NumMemoryBanks; mem_id++) { ret = topology_sysfs_get_mem_props(i, mem_id, &temp_props[i].mem[mem_id]); if (ret != HSAKMT_STATUS_SUCCESS) { free_properties(temp_props, i + 1); goto err; } } } if (temp_props[i].node.NumCaches) { temp_props[i].cache = calloc(temp_props[i].node.NumCaches * sizeof(HsaCacheProperties), 1); if (!temp_props[i].cache) { ret = HSAKMT_STATUS_NO_MEMORY; free_properties(temp_props, i + 1); goto err; } for (cache_id = 0; cache_id < temp_props[i].node.NumCaches; cache_id++) { ret = topology_sysfs_get_cache_props(i, cache_id, &temp_props[i].cache[cache_id]); if (ret != HSAKMT_STATUS_SUCCESS) { free_properties(temp_props, i + 1); goto err; } } } else if (!temp_props[i].node.KFDGpuID) { /* a CPU node */ ret = topology_get_cpu_cache_props( i, cpuinfo, &temp_props[i]); if (ret != HSAKMT_STATUS_SUCCESS) { free_properties(temp_props, i + 1); goto err; } } /* To simplify, allocate maximum needed memory for io_links for each node. This * removes the need for realloc when indirect and QPI links are added later */ temp_props[i].link = calloc(sys_props.NumNodes - 1, sizeof(HsaIoLinkProperties)); if (!temp_props[i].link) { ret = HSAKMT_STATUS_NO_MEMORY; free_properties(temp_props, i + 1); goto err; } num_ioLinks = temp_props[i].node.NumIOLinks - num_p2pLinks; uint32_t link_id = 0; if (num_ioLinks) { uint32_t sys_link_id = 0; /* Parse all the sysfs specified io links. Skip the ones where the * remote node (node_to) is not accessible */ while (sys_link_id < num_ioLinks && link_id < sys_props.NumNodes - 1) { ret = topology_sysfs_get_iolink_props(i, sys_link_id++, &temp_props[i].link[link_id], false); if (ret == HSAKMT_STATUS_NOT_SUPPORTED) { ret = HSAKMT_STATUS_SUCCESS; continue; } else if (ret != HSAKMT_STATUS_SUCCESS) { free_properties(temp_props, i + 1); goto err; } link_id++; } /* sysfs specifies all the io links. Limit the number to valid ones */ temp_props[i].node.NumIOLinks = link_id; } if (num_p2pLinks) { uint32_t sys_link_id = 0; /* Parse all the sysfs specified p2p links. */ while (sys_link_id < num_p2pLinks && link_id < sys_props.NumNodes - 1) { ret = topology_sysfs_get_iolink_props(i, sys_link_id++, &temp_props[i].link[link_id], true); if (ret == HSAKMT_STATUS_NOT_SUPPORTED) { ret = HSAKMT_STATUS_SUCCESS; continue; } else if (ret != HSAKMT_STATUS_SUCCESS) { free_properties(temp_props, i + 1); goto err; } link_id++; } temp_props[i].node.NumIOLinks = link_id; } } } if (!p2p_links) { /* All direct IO links are created in the kernel. Here we need to * connect GPU<->GPU or GPU<->CPU indirect IO links. */ topology_create_indirect_gpu_links(&sys_props, temp_props); } ret = topology_sysfs_get_generation(&gen_end); if (ret != HSAKMT_STATUS_SUCCESS) { free_properties(temp_props, sys_props.NumNodes); goto err; } if (gen_start != gen_end) { free_properties(temp_props, sys_props.NumNodes); temp_props = 0; goto retry; } if (!g_system) { g_system = malloc(sizeof(HsaSystemProperties)); if (!g_system) { free_properties(temp_props, sys_props.NumNodes); ret = HSAKMT_STATUS_NO_MEMORY; goto err; } } *g_system = sys_props; if (g_props) free(g_props); g_props = temp_props; err: free(cpuinfo); return ret; } /* Drop the Snashot of the HSA topology information. Assume lock is held. */ void topology_drop_snapshot(void) { if (!!g_system != !!g_props) pr_warn("Probably inconsistency?\n"); if (g_props) { /* Remove state */ free_properties(g_props, g_system->NumNodes); g_props = NULL; } free(g_system); g_system = NULL; if (map_user_to_sysfs_node_id) { free(map_user_to_sysfs_node_id); map_user_to_sysfs_node_id = NULL; map_user_to_sysfs_node_id_size = 0; } } HSAKMT_STATUS validate_nodeid(uint32_t nodeid, uint32_t *gpu_id) { if (!g_props || !g_system || g_system->NumNodes <= nodeid) return HSAKMT_STATUS_INVALID_NODE_UNIT; if (gpu_id) *gpu_id = g_props[nodeid].node.KFDGpuID; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS gpuid_to_nodeid(uint32_t gpu_id, uint32_t *node_id) { uint64_t node_idx; for (node_idx = 0; node_idx < g_system->NumNodes; node_idx++) { if (g_props[node_idx].node.KFDGpuID == gpu_id) { *node_id = node_idx; return HSAKMT_STATUS_SUCCESS; } } return HSAKMT_STATUS_INVALID_NODE_UNIT; } HSAKMT_STATUS HSAKMTAPI hsaKmtAcquireSystemProperties(HsaSystemProperties *SystemProperties) { HSAKMT_STATUS err = HSAKMT_STATUS_SUCCESS; CHECK_KFD_OPEN(); if (!SystemProperties) return HSAKMT_STATUS_INVALID_PARAMETER; pthread_mutex_lock(&hsakmt_mutex); /* We already have a valid snapshot. Avoid double initialization that * would leak memory. */ if (g_system) { *SystemProperties = *g_system; goto out; } err = topology_take_snapshot(); if (err != HSAKMT_STATUS_SUCCESS) goto out; assert(g_system); err = fmm_init_process_apertures(g_system->NumNodes); if (err != HSAKMT_STATUS_SUCCESS) goto init_process_apertures_failed; err = init_process_doorbells(g_system->NumNodes); if (err != HSAKMT_STATUS_SUCCESS) goto init_doorbells_failed; *SystemProperties = *g_system; goto out; init_doorbells_failed: fmm_destroy_process_apertures(); init_process_apertures_failed: topology_drop_snapshot(); out: pthread_mutex_unlock(&hsakmt_mutex); return err; } HSAKMT_STATUS HSAKMTAPI hsaKmtReleaseSystemProperties(void) { pthread_mutex_lock(&hsakmt_mutex); destroy_process_doorbells(); fmm_destroy_process_apertures(); topology_drop_snapshot(); pthread_mutex_unlock(&hsakmt_mutex); return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS topology_get_node_props(HSAuint32 NodeId, HsaNodeProperties *NodeProperties) { if (!g_system || !g_props || NodeId >= g_system->NumNodes) return HSAKMT_STATUS_ERROR; *NodeProperties = g_props[NodeId].node; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtGetNodeProperties(HSAuint32 NodeId, HsaNodeProperties *NodeProperties) { HSAKMT_STATUS err; uint32_t gpu_id; if (!NodeProperties) return HSAKMT_STATUS_INVALID_PARAMETER; CHECK_KFD_OPEN(); pthread_mutex_lock(&hsakmt_mutex); err = validate_nodeid(NodeId, &gpu_id); if (err != HSAKMT_STATUS_SUCCESS) goto out; err = topology_get_node_props(NodeId, NodeProperties); if (err != HSAKMT_STATUS_SUCCESS) goto out; /* For CPU only node don't add any additional GPU memory banks. */ if (gpu_id) { uint64_t base, limit; if (is_dgpu) NodeProperties->NumMemoryBanks += NUM_OF_DGPU_HEAPS; else NodeProperties->NumMemoryBanks += NUM_OF_IGPU_HEAPS; if (fmm_get_aperture_base_and_limit(FMM_MMIO, gpu_id, &base, &limit) == HSAKMT_STATUS_SUCCESS) NodeProperties->NumMemoryBanks += 1; } out: pthread_mutex_unlock(&hsakmt_mutex); return err; } HSAKMT_STATUS HSAKMTAPI hsaKmtGetNodeMemoryProperties(HSAuint32 NodeId, HSAuint32 NumBanks, HsaMemoryProperties *MemoryProperties) { HSAKMT_STATUS err = HSAKMT_STATUS_SUCCESS; uint32_t i, gpu_id; HSAuint64 aperture_limit; if (!MemoryProperties) return HSAKMT_STATUS_INVALID_PARAMETER; CHECK_KFD_OPEN(); pthread_mutex_lock(&hsakmt_mutex); err = validate_nodeid(NodeId, &gpu_id); if (err != HSAKMT_STATUS_SUCCESS) goto out; memset(MemoryProperties, 0, NumBanks * sizeof(HsaMemoryProperties)); for (i = 0; i < MIN(g_props[NodeId].node.NumMemoryBanks, NumBanks); i++) { assert(g_props[NodeId].mem); MemoryProperties[i] = g_props[NodeId].mem[i]; } /* The following memory banks does not apply to CPU only node */ if (gpu_id == 0) goto out; /*Add LDS*/ if (i < NumBanks && fmm_get_aperture_base_and_limit(FMM_LDS, gpu_id, &MemoryProperties[i].VirtualBaseAddress, &aperture_limit) == HSAKMT_STATUS_SUCCESS) { MemoryProperties[i].HeapType = HSA_HEAPTYPE_GPU_LDS; MemoryProperties[i].SizeInBytes = g_props[NodeId].node.LDSSizeInKB * 1024; i++; } /* Add Local memory - HSA_HEAPTYPE_FRAME_BUFFER_PRIVATE. * For dGPU the topology node contains Local Memory and it is added by * the for loop above */ if (get_gfxv_by_node_id(NodeId) == GFX_VERSION_KAVERI && i < NumBanks && g_props[NodeId].node.LocalMemSize > 0 && fmm_get_aperture_base_and_limit(FMM_GPUVM, gpu_id, &MemoryProperties[i].VirtualBaseAddress, &aperture_limit) == HSAKMT_STATUS_SUCCESS) { MemoryProperties[i].HeapType = HSA_HEAPTYPE_FRAME_BUFFER_PRIVATE; MemoryProperties[i].SizeInBytes = g_props[NodeId].node.LocalMemSize; i++; } /* Add SCRATCH */ if (i < NumBanks && fmm_get_aperture_base_and_limit(FMM_SCRATCH, gpu_id, &MemoryProperties[i].VirtualBaseAddress, &aperture_limit) == HSAKMT_STATUS_SUCCESS) { MemoryProperties[i].HeapType = HSA_HEAPTYPE_GPU_SCRATCH; MemoryProperties[i].SizeInBytes = (aperture_limit - MemoryProperties[i].VirtualBaseAddress) + 1; i++; } /* Add SVM aperture */ if (topology_is_svm_needed(g_props[NodeId].node.EngineId) && i < NumBanks && fmm_get_aperture_base_and_limit( FMM_SVM, gpu_id, &MemoryProperties[i].VirtualBaseAddress, &aperture_limit) == HSAKMT_STATUS_SUCCESS) { MemoryProperties[i].HeapType = HSA_HEAPTYPE_DEVICE_SVM; MemoryProperties[i].SizeInBytes = (aperture_limit - MemoryProperties[i].VirtualBaseAddress) + 1; i++; } /* Add mmio aperture */ if (i < NumBanks && fmm_get_aperture_base_and_limit(FMM_MMIO, gpu_id, &MemoryProperties[i].VirtualBaseAddress, &aperture_limit) == HSAKMT_STATUS_SUCCESS) { MemoryProperties[i].HeapType = HSA_HEAPTYPE_MMIO_REMAP; MemoryProperties[i].SizeInBytes = (aperture_limit - MemoryProperties[i].VirtualBaseAddress) + 1; i++; } out: pthread_mutex_unlock(&hsakmt_mutex); return err; } HSAKMT_STATUS HSAKMTAPI hsaKmtGetNodeCacheProperties(HSAuint32 NodeId, HSAuint32 ProcessorId, HSAuint32 NumCaches, HsaCacheProperties *CacheProperties) { HSAKMT_STATUS err; uint32_t i; if (!CacheProperties) return HSAKMT_STATUS_INVALID_PARAMETER; CHECK_KFD_OPEN(); pthread_mutex_lock(&hsakmt_mutex); /* KFD ADD page 18, snapshot protocol violation */ if (!g_system || NodeId >= g_system->NumNodes) { err = HSAKMT_STATUS_INVALID_NODE_UNIT; goto out; } if (NumCaches > g_props[NodeId].node.NumCaches) { err = HSAKMT_STATUS_INVALID_PARAMETER; goto out; } for (i = 0; i < MIN(g_props[NodeId].node.NumCaches, NumCaches); i++) { assert(g_props[NodeId].cache); CacheProperties[i] = g_props[NodeId].cache[i]; } err = HSAKMT_STATUS_SUCCESS; out: pthread_mutex_unlock(&hsakmt_mutex); return err; } HSAKMT_STATUS topology_get_iolink_props(HSAuint32 NodeId, HSAuint32 NumIoLinks, HsaIoLinkProperties *IoLinkProperties) { if (!g_system || !g_props || NodeId >= g_system->NumNodes) return HSAKMT_STATUS_ERROR; memcpy(IoLinkProperties, g_props[NodeId].link, NumIoLinks * sizeof(*IoLinkProperties)); return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS HSAKMTAPI hsaKmtGetNodeIoLinkProperties(HSAuint32 NodeId, HSAuint32 NumIoLinks, HsaIoLinkProperties *IoLinkProperties) { HSAKMT_STATUS err; if (!IoLinkProperties) return HSAKMT_STATUS_INVALID_PARAMETER; CHECK_KFD_OPEN(); pthread_mutex_lock(&hsakmt_mutex); /* KFD ADD page 18, snapshot protocol violation */ if (!g_system || NodeId >= g_system->NumNodes ) { err = HSAKMT_STATUS_INVALID_NODE_UNIT; goto out; } if (NumIoLinks > g_props[NodeId].node.NumIOLinks) { err = HSAKMT_STATUS_INVALID_PARAMETER; goto out; } assert(g_props[NodeId].link); err = topology_get_iolink_props(NodeId, NumIoLinks, IoLinkProperties); out: pthread_mutex_unlock(&hsakmt_mutex); return err; } uint32_t get_gfxv_by_node_id(HSAuint32 node_id) { return HSA_GET_GFX_VERSION_FULL(g_props[node_id].node.EngineId.ui32); } uint16_t get_device_id_by_node_id(HSAuint32 node_id) { if (!g_props || !g_system || g_system->NumNodes <= node_id) return 0; return g_props[node_id].node.DeviceId; } bool prefer_ats(HSAuint32 node_id) { return g_props[node_id].node.Capability.ui32.HSAMMUPresent && g_props[node_id].node.NumCPUCores && g_props[node_id].node.NumFComputeCores; } uint16_t get_device_id_by_gpu_id(HSAuint32 gpu_id) { unsigned int i; if (!g_props || !g_system) return 0; for (i = 0; i < g_system->NumNodes; i++) { if (g_props[i].node.KFDGpuID == gpu_id) return g_props[i].node.DeviceId; } return 0; } uint32_t get_direct_link_cpu(uint32_t gpu_node) { HSAuint64 size = 0; int32_t cpu_id; HSAuint32 i; cpu_id = gpu_get_direct_link_cpu(gpu_node, g_props); if (cpu_id == -1) return INVALID_NODEID; assert(g_props[cpu_id].mem); for (i = 0; i < g_props[cpu_id].node.NumMemoryBanks; i++) size += g_props[cpu_id].mem[i].SizeInBytes; return size ? (uint32_t)cpu_id : INVALID_NODEID; } HSAKMT_STATUS validate_nodeid_array(uint32_t **gpu_id_array, uint32_t NumberOfNodes, uint32_t *NodeArray) { HSAKMT_STATUS ret; unsigned int i; if (NumberOfNodes == 0 || !NodeArray || !gpu_id_array) return HSAKMT_STATUS_INVALID_PARAMETER; /* Translate Node IDs to gpu_ids */ *gpu_id_array = malloc(NumberOfNodes * sizeof(uint32_t)); if (!(*gpu_id_array)) return HSAKMT_STATUS_NO_MEMORY; for (i = 0; i < NumberOfNodes; i++) { ret = validate_nodeid(NodeArray[i], *gpu_id_array + i); if (ret != HSAKMT_STATUS_SUCCESS) { free(*gpu_id_array); break; } } return ret; } inline uint32_t get_num_sysfs_nodes(void) { return num_sysfs_nodes; } ROCT-Thunk-Interface-rocm-5.7.0/src/version.c000066400000000000000000000035311446477712600206610ustar00rootroot00000000000000/* * Copyright © 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including * the next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "libhsakmt.h" #include #include #include "linux/kfd_ioctl.h" HsaVersionInfo kfd_version_info; HSAKMT_STATUS HSAKMTAPI hsaKmtGetVersion(HsaVersionInfo *VersionInfo) { CHECK_KFD_OPEN(); *VersionInfo = kfd_version_info; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS init_kfd_version(void) { struct kfd_ioctl_get_version_args args = {0}; if (kmtIoctl(kfd_fd, AMDKFD_IOC_GET_VERSION, &args) == -1) return HSAKMT_STATUS_ERROR; kfd_version_info.KernelInterfaceMajorVersion = args.major_version; kfd_version_info.KernelInterfaceMinorVersion = args.minor_version; if (args.major_version != 1) return HSAKMT_STATUS_DRIVER_MISMATCH; return HSAKMT_STATUS_SUCCESS; } ROCT-Thunk-Interface-rocm-5.7.0/tests/000077500000000000000000000000001446477712600174015ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/000077500000000000000000000000001446477712600210455ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/.gitignore000066400000000000000000000000001446477712600230230ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/CMakeLists.txt000066400000000000000000000225271446477712600236150ustar00rootroot00000000000000# # Copyright (C) 2018 Advanced Micro Devices, Inc. All Rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR # OTHER DEALINGS IN THE SOFTWARE. # # # If environment variable DRM_DIR or LIBHSAKMT_PATH is set, the script # will pick up the corresponding libraries from those pathes. cmake_minimum_required(VERSION 3.5 FATAL_ERROR) project(KFDTest) # For DEB/RPM generation set ( CPACK_PACKAGE_NAME "kfdtest" ) set ( CPACK_PACKAGE_CONTACT "Advanced Micro Devices Inc." ) set ( CPACK_PACKAGE_DESCRIPTION "This package includes kfdtest, the list of excluded tests for each ASIC, and a convenience script to run the test suite" ) set ( CPACK_PACKAGE_DESCRIPTION_SUMMARY "Test suite for ROCK/KFD" ) # Make proper version for appending # Default Value is 99999, setting it first set(ROCM_VERSION_FOR_PACKAGE "99999") if(DEFINED ENV{ROCM_LIBPATCH_VERSION}) set(ROCM_VERSION_FOR_PACKAGE $ENV{ROCM_LIBPATCH_VERSION}) endif() set ( CPACK_PACKAGE_VERSION_MAJOR "1" ) set ( CPACK_PACKAGE_VERSION_MINOR "0" ) set ( CPACK_PACKAGE_VERSION_PATCH "0" ) set ( CPACK_PACKAGE_HOMEPAGE_URL "https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface" ) set ( CPACK_DEBIAN_FILE_NAME "DEB-DEFAULT") set ( CPACK_RPM_FILE_NAME "RPM-DEFAULT") ## Debian package values set ( CPACK_DEBIAN_PACKAGE_RELEASE "local" ) if( DEFINED ENV{CPACK_DEBIAN_PACKAGE_RELEASE} ) set ( CPACK_DEBIAN_PACKAGE_RELEASE $ENV{CPACK_DEBIAN_PACKAGE_RELEASE} ) endif() ## RPM package variables set ( CPACK_RPM_PACKAGE_RELEASE "local" ) if( DEFINED ENV{CPACK_RPM_PACKAGE_RELEASE} ) set ( CPACK_RPM_PACKAGE_RELEASE $ENV{CPACK_RPM_PACKAGE_RELEASE} ) endif() ## Note: rpm --eval %{?dist} will evaluate to NULL in Debian ## So Debian distros won't append dist tag to CPACK_RPM_PACKAGE_RELEASE. ## Also for debian package name , the dist tag is added from build env execute_process( COMMAND rpm --eval %{?dist} RESULT_VARIABLE PROC_RESULT OUTPUT_VARIABLE EVAL_RESULT OUTPUT_STRIP_TRAILING_WHITESPACE ) message("RESULT_VARIABLE ${PROC_RESULT} OUTPUT_VARIABLE: ${EVAL_RESULT}") ## Add distribution tag to rpm package name if ( PROC_RESULT EQUAL "0" AND NOT EVAL_RESULT STREQUAL "" ) string ( APPEND CPACK_RPM_PACKAGE_RELEASE "%{?dist}" ) endif() set(PACKAGE_VERSION_STR "${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}.${ROCM_VERSION_FOR_PACKAGE}") set(CPACK_PACKAGE_VERSION "${PACKAGE_VERSION_STR}") ## Define default variable and variables for the optional build target hsakmt-dev set ( SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR} CACHE STRING "Location of hsakmt source code." ) set ( CMAKE_INSTALL_PREFIX "/opt/rocm" CACHE STRING "Default installation directory." ) set ( CPACK_PACKAGING_INSTALL_PREFIX "${CMAKE_INSTALL_PREFIX}" CACHE STRING "Default packaging prefix." ) set ( CPACK_GENERATOR "DEB;RPM" CACHE STRING "Default packaging generators." ) # Debian package specific variables set ( CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface" ) set (CPACK_DEBIAN_PACKAGE_DEPENDS "rocm-core") # RPM package specific variables set (CPACK_RPM_PACKAGE_REQUIRES "rocm-core") #set ( CMAKE_VERBOSE_MAKEFILE on ) find_package(PkgConfig) list (PREPEND CMAKE_PREFIX_PATH "${DRM_DIR}") # The module name passed to pkg_check_modules() is determined by the # name of file *.pc pkg_check_modules(DRM REQUIRED libdrm) pkg_check_modules(DRM_AMDGPU REQUIRED libdrm_amdgpu) include_directories(${DRM_AMDGPU_INCLUDE_DIRS}) if( DEFINED ENV{LIBHSAKMT_PATH} ) set ( LIBHSAKMT_PATH $ENV{LIBHSAKMT_PATH} ) message ( "LIBHSAKMT_PATH environment variable is set" ) else() if ( ${ROCM_INSTALL_PATH} ) set ( ENV{PKG_CONFIG_PATH} ${ROCM_INSTALL_PATH}/share/pkgconfig ) else() set ( ENV{PKG_CONFIG_PATH} /opt/rocm/share/pkgconfig ) endif() pkg_check_modules(HSAKMT libhsakmt) if( NOT HSAKMT_FOUND ) set ( LIBHSAKMT_PATH $ENV{OUT_DIR} ) endif() endif() if( DEFINED LIBHSAKMT_PATH ) set ( HSAKMT_LIBRARY_DIRS ${LIBHSAKMT_PATH}/lib ) set ( HSAKMT_LIBRARIES hsakmt ) endif() message ( "Find libhsakmt at ${HSAKMT_LIBRARY_DIRS}" ) if ( POLICY CMP0074 ) cmake_policy( SET CMP0074 NEW ) endif() find_path( LIGHTNING_CMAKE_DIR NAMES LLVMConfig.cmake PATHS $ENV{OUT_DIR}/llvm/lib/cmake/llvm NO_CACHE NO_DEFAULT_PATH) if ( DEFINED LIGHTNING_CMAKE_DIR AND EXISTS ${LIGHTNING_CMAKE_DIR} ) set ( LLVM_DIR ${LIGHTNING_CMAKE_DIR} ) else() message( STATUS "Couldn't find Lightning build in compute directory. " "Searching LLVM_DIR then defaulting to system LLVM install if still not found..." ) endif() find_package( LLVM REQUIRED CONFIG ) if( ${LLVM_PACKAGE_VERSION} VERSION_LESS "7.0" ) message( FATAL_ERROR "Requires LLVM 7.0 or greater " "(found ${LLVM_PACKAGE_VERSION})" ) elseif( ${LLVM_PACKAGE_VERSION} VERSION_LESS "14.0" ) message( WARNING "Not using latest LLVM version. " "Some ASIC targets may not work!" ) endif() message( STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}" ) message( STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}" ) include_directories(${LLVM_INCLUDE_DIRS}) separate_arguments(LLVM_DEFINITIONS_LIST NATIVE_COMMAND ${LLVM_DEFINITIONS}) add_definitions(${LLVM_DEFINITIONS_LIST}) llvm_map_components_to_libnames(llvm_libs AMDGPUAsmParser Core Support) include_directories(${PROJECT_SOURCE_DIR}/gtest-1.6.0) include_directories(${PROJECT_SOURCE_DIR}/include) include_directories(${PROJECT_SOURCE_DIR}/../../include) include_directories(${PROJECT_SOURCE_DIR}/../../libhsakmt/include) include_directories(${DRM_INCLUDE_DIRS}) set (SRC_FILES gtest-1.6.0/gtest-all.cpp src/AqlQueue.cpp src/BasePacket.cpp src/BaseQueue.cpp src/Dispatch.cpp src/GoogleTestExtension.cpp src/IndirectBuffer.cpp src/Assemble.cpp src/ShaderStore.cpp src/LinuxOSWrapper.cpp src/PM4Packet.cpp src/PM4Queue.cpp src/RDMAUtil.cpp src/SDMAPacket.cpp src/SDMAQueue.cpp src/KFDBaseComponentTest.cpp src/KFDMultiProcessTest.cpp src/KFDTestMain.cpp src/KFDTestUtil.cpp src/KFDTestUtilQueue.cpp src/KFDOpenCloseKFDTest.cpp src/KFDTopologyTest.cpp src/KFDMemoryTest.cpp src/KFDLocalMemoryTest.cpp src/KFDEventTest.cpp src/KFDQMTest.cpp src/KFDCWSRTest.cpp src/KFDExceptionTest.cpp src/KFDGraphicsInterop.cpp src/KFDPerfCounters.cpp src/KFDGWSTest.cpp src/KFDIPCTest.cpp src/KFDASMTest.cpp src/KFDEvictTest.cpp src/KFDHWSTest.cpp src/KFDPerformanceTest.cpp src/KFDPMTest.cpp src/KFDSVMRangeTest.cpp src/KFDSVMEvictTest.cpp src/KFDRASTest.cpp src/RDMATest.cpp) message( STATUS "PROJECT_SOURCE_DIR:" ${PROJECT_SOURCE_DIR} ) #message( STATUS "SRC_FILES: ") #foreach(file ${SRC_FILES}) # message(STATUS "${file}") #endforeach() #add_definitions(-Wall -std=c++11) if ( "${CMAKE_C_COMPILER_VERSION}" STRGREATER "4.8.0") ## Add --enable-new-dtags to generate DT_RUNPATH set ( CMAKE_CXX_FLAGS "-std=gnu++17 -Wl,--enable-new-dtags" ) endif() if ( "${CMAKE_BUILD_TYPE}" STREQUAL Release ) set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -O2" ) else () set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -g" ) endif () ## Address Sanitize Flag if ( ${ADDRESS_SANITIZER} ) set ( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fsanitize=address" ) set ( CMAKE_EXE_LINKER_FLAGS -fsanitize=address ) endif () # link_directories() has to be put before add_executable() # The modules found by pkg_check_modules() in the default pkg config # path do not need to use link_directories() here. link_directories(${HSAKMT_LIBRARY_DIRS}) add_executable(kfdtest ${SRC_FILES}) target_link_libraries(kfdtest ${HSAKMT_LIBRARIES} ${DRM_LDFLAGS} ${DRM_AMDGPU_LDFLAGS} ${llvm_libs} pthread m stdc++ rt numa) configure_file ( scripts/kfdtest.exclude kfdtest.exclude COPYONLY ) configure_file ( scripts/run_kfdtest.sh run_kfdtest.sh COPYONLY ) install( FILES ${CMAKE_CURRENT_BINARY_DIR}/kfdtest ${CMAKE_CURRENT_BINARY_DIR}/run_kfdtest.sh PERMISSIONS OWNER_EXECUTE OWNER_WRITE OWNER_READ GROUP_EXECUTE GROUP_WRITE GROUP_READ WORLD_EXECUTE WORLD_READ DESTINATION bin ) install( FILES ${CMAKE_CURRENT_BINARY_DIR}/kfdtest.exclude PERMISSIONS OWNER_WRITE OWNER_READ GROUP_WRITE GROUP_READ WORLD_READ DESTINATION share/kfdtest ) # Remove dependency on rocm-core if -DROCM_DEP_ROCMCORE=ON not given to cmake if(NOT ROCM_DEP_ROCMCORE) string(REGEX REPLACE ",? ?rocm-core" "" CPACK_RPM_PACKAGE_REQUIRES ${CPACK_RPM_PACKAGE_REQUIRES}) string(REGEX REPLACE ",? ?rocm-core" "" CPACK_DEBIAN_PACKAGE_DEPENDS ${CPACK_DEBIAN_PACKAGE_DEPENDS}) endif() include ( CPack ) ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/LICENSE.kfdtest000066400000000000000000000105451446477712600235220ustar00rootroot00000000000000KFDTest - KFD unit tests LICENSE /* The following license applies to all parts of kfdtest except the * SP3 shader assembler. See separate license terms below. */ Copyright (C) 2018 Advanced Micro Devices, Inc. All Rights Reserved. MIT LICENSE: Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ----------------------------------------------- libamdsp3 - AMD SP3 shader assembler library LICENSE /* The following license applies to the SP3 shader assembler, which is * named as libamdsp3.a and will be built into the kfdtest binary. */ Copyright (C) 2018 Advanced Micro Devices, Inc. All rights reserved. REDISTRIBUTION: Permission is hereby granted, free of any license fees, to any person obtaining a copy of this program (the "Software"), to install, reproduce, copy and distribute copies, in binary form only, of the Software and to permit persons to whom the Software is provided to do the same, provided that the following conditions are met: No reverse engineering, decompilation, or disassembly of this Software is permitted. Redistributions must reproduce the above copyright notice, this permission notice, and the following disclaimers and notices in the Software documentation and/or other materials provided with the Software. DISCLAIMER: THE USE OF THE SOFTWARE IS AT YOUR SOLE RISK. THE SOFTWARE IS PROVIDED "AS IS" AND WITHOUT WARRANTY OF ANY KIND AND COPYRIGHT HOLDER AND ITS LICENSORS EXPRESSLY DISCLAIM ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. COPYRIGHT HOLDER AND ITS LICENSORS DO NOT WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. THE ENTIRE RISK ASSOCIATED WITH THE USE OF THE SOFTWARE IS ASSUMED BY YOU. FURTHERMORE, COPYRIGHT HOLDER AND ITS LICENSORS DO NOT WARRANT OR MAKE ANY REPRESENTATIONS REGARDING THE USE OR THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY, CURRENTNESS, OR OTHERWISE. DISCLAIMER: UNDER NO CIRCUMSTANCES INCLUDING NEGLIGENCE, SHALL COPYRIGHT HOLDER AND ITS LICENSORS OR ITS DIRECTORS, OFFICERS, EMPLOYEES OR AGENTS ("AUTHORIZED REPRESENTATIVES") BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES (INCLUDING DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, AND THE LIKE) ARISING OUT OF THE USE, MISUSE OR INABILITY TO USE THE SOFTWARE, BREACH OR DEFAULT, INCLUDING THOSE ARISING FROM INFRINGEMENT OR ALLEGED INFRINGEMENT OF ANY PATENT, TRADEMARK, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT EVEN IF COPYRIGHT HOLDER AND ITS AUTHORIZED REPRESENTATIVES HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN NO EVENT SHALL COPYRIGHT HOLDER OR ITS AUTHORIZED REPRESENTATIVES TOTAL LIABILITY FOR ALL DAMAGES, LOSSES, AND CAUSES OF ACTION (WHETHER IN CONTRACT, TORT (INCLUDING NEGLIGENCE) OR OTHERWISE) EXCEED THE AMOUNT OF US$10. Notice: The Software is subject to United States export laws and regulations. You agree to comply with all domestic and international export laws and regulations that apply to the Software, including but not limited to the Export Administration Regulations administered by the U.S. Department of Commerce and International Traffic in Arm Regulations administered by the U.S. Department of State. These laws include restrictions on destinations, end users and end use. ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/README.txt000066400000000000000000000013151446477712600225430ustar00rootroot000000000000001. Note on building kfdtest To build this kfdtest application, the following libraries should be already installed on the building machine: libdrm libdrm_amdgpu libhsakmt If libhsakmt is not installed, but the headers and libraries are present locally, you can specify its directory by export LIBHSAKMT_PATH=/*your local libhsakmt folder*/ With that, the headers and libraries are searched under LIBHSAKMT_PATH/include and LIBHSAKMT_PATH/lib respectively. 2. How to run kfdtest Just run "./run_kfdtest.sh" under the building output folder. You may need to specify library path through: export LD_LIBRARY_PATH=/*your library path containing libhsakmt*/ Note: you can use "run_kfdtest.sh -h" to see more options. ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/gtest-1.6.0/000077500000000000000000000000001446477712600226335ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/gtest-1.6.0/gtest-all.cpp000066400000000000000000012235001446477712600252360ustar00rootroot00000000000000// Copyright 2008, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: mheule@google.com (Markus Heule) // // Google C++ Testing Framework (Google Test) // // Sometimes it's desirable to build Google Test by compiling a single file. // This file serves this purpose. // This line ensures that gtest.h can be compiled on its own, even // when it's fused. #include "gtest/gtest.h" // The following lines pull in the real gtest *.cc files. // Copyright 2005, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan) // // The Google C++ Testing Framework (Google Test) // Copyright 2007, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan) // // Utilities for testing Google Test itself and code that uses Google Test // (e.g. frameworks built on top of Google Test). #ifndef GTEST_INCLUDE_GTEST_GTEST_SPI_H_ #define GTEST_INCLUDE_GTEST_GTEST_SPI_H_ namespace testing { // This helper class can be used to mock out Google Test failure reporting // so that we can test Google Test or code that builds on Google Test. // // An object of this class appends a TestPartResult object to the // TestPartResultArray object given in the constructor whenever a Google Test // failure is reported. It can either intercept only failures that are // generated in the same thread that created this object or it can intercept // all generated failures. The scope of this mock object can be controlled with // the second argument to the two arguments constructor. class GTEST_API_ ScopedFakeTestPartResultReporter : public TestPartResultReporterInterface { public: // The two possible mocking modes of this object. enum InterceptMode { INTERCEPT_ONLY_CURRENT_THREAD, // Intercepts only thread local failures. INTERCEPT_ALL_THREADS // Intercepts all failures. }; // The c'tor sets this object as the test part result reporter used // by Google Test. The 'result' parameter specifies where to report the // results. This reporter will only catch failures generated in the current // thread. DEPRECATED explicit ScopedFakeTestPartResultReporter(TestPartResultArray* result); // Same as above, but you can choose the interception scope of this object. ScopedFakeTestPartResultReporter(InterceptMode intercept_mode, TestPartResultArray* result); // The d'tor restores the previous test part result reporter. virtual ~ScopedFakeTestPartResultReporter(); // Appends the TestPartResult object to the TestPartResultArray // received in the constructor. // // This method is from the TestPartResultReporterInterface // interface. virtual void ReportTestPartResult(const TestPartResult& result); private: void Init(); const InterceptMode intercept_mode_; TestPartResultReporterInterface* old_reporter_; TestPartResultArray* const result_; GTEST_DISALLOW_COPY_AND_ASSIGN_(ScopedFakeTestPartResultReporter); }; namespace internal { // A helper class for implementing EXPECT_FATAL_FAILURE() and // EXPECT_NONFATAL_FAILURE(). Its destructor verifies that the given // TestPartResultArray contains exactly one failure that has the given // type and contains the given substring. If that's not the case, a // non-fatal failure will be generated. class GTEST_API_ SingleFailureChecker { public: // The constructor remembers the arguments. SingleFailureChecker(const TestPartResultArray* results, TestPartResult::Type type, const string& substr); ~SingleFailureChecker(); private: const TestPartResultArray* const results_; const TestPartResult::Type type_; const string substr_; GTEST_DISALLOW_COPY_AND_ASSIGN_(SingleFailureChecker); }; } // namespace internal } // namespace testing // A set of macros for testing Google Test assertions or code that's expected // to generate Google Test fatal failures. It verifies that the given // statement will cause exactly one fatal Google Test failure with 'substr' // being part of the failure message. // // There are two different versions of this macro. EXPECT_FATAL_FAILURE only // affects and considers failures generated in the current thread and // EXPECT_FATAL_FAILURE_ON_ALL_THREADS does the same but for all threads. // // The verification of the assertion is done correctly even when the statement // throws an exception or aborts the current function. // // Known restrictions: // - 'statement' cannot reference local non-static variables or // non-static members of the current object. // - 'statement' cannot return a value. // - You cannot stream a failure message to this macro. // // Note that even though the implementations of the following two // macros are much alike, we cannot refactor them to use a common // helper macro, due to some peculiarity in how the preprocessor // works. The AcceptsMacroThatExpandsToUnprotectedComma test in // gtest_unittest.cc will fail to compile if we do that. #define EXPECT_FATAL_FAILURE(statement, substr) \ do { \ class GTestExpectFatalFailureHelper {\ public:\ static void Execute() { statement; }\ };\ ::testing::TestPartResultArray gtest_failures;\ ::testing::internal::SingleFailureChecker gtest_checker(\ >est_failures, ::testing::TestPartResult::kFatalFailure, (substr));\ {\ ::testing::ScopedFakeTestPartResultReporter gtest_reporter(\ ::testing::ScopedFakeTestPartResultReporter:: \ INTERCEPT_ONLY_CURRENT_THREAD, >est_failures);\ GTestExpectFatalFailureHelper::Execute();\ }\ } while (::testing::internal::AlwaysFalse()) #define EXPECT_FATAL_FAILURE_ON_ALL_THREADS(statement, substr) \ do { \ class GTestExpectFatalFailureHelper {\ public:\ static void Execute() { statement; }\ };\ ::testing::TestPartResultArray gtest_failures;\ ::testing::internal::SingleFailureChecker gtest_checker(\ >est_failures, ::testing::TestPartResult::kFatalFailure, (substr));\ {\ ::testing::ScopedFakeTestPartResultReporter gtest_reporter(\ ::testing::ScopedFakeTestPartResultReporter:: \ INTERCEPT_ALL_THREADS, >est_failures);\ GTestExpectFatalFailureHelper::Execute();\ }\ } while (::testing::internal::AlwaysFalse()) // A macro for testing Google Test assertions or code that's expected to // generate Google Test non-fatal failures. It asserts that the given // statement will cause exactly one non-fatal Google Test failure with 'substr' // being part of the failure message. // // There are two different versions of this macro. EXPECT_NONFATAL_FAILURE only // affects and considers failures generated in the current thread and // EXPECT_NONFATAL_FAILURE_ON_ALL_THREADS does the same but for all threads. // // 'statement' is allowed to reference local variables and members of // the current object. // // The verification of the assertion is done correctly even when the statement // throws an exception or aborts the current function. // // Known restrictions: // - You cannot stream a failure message to this macro. // // Note that even though the implementations of the following two // macros are much alike, we cannot refactor them to use a common // helper macro, due to some peculiarity in how the preprocessor // works. If we do that, the code won't compile when the user gives // EXPECT_NONFATAL_FAILURE() a statement that contains a macro that // expands to code containing an unprotected comma. The // AcceptsMacroThatExpandsToUnprotectedComma test in gtest_unittest.cc // catches that. // // For the same reason, we have to write // if (::testing::internal::AlwaysTrue()) { statement; } // instead of // GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement) // to avoid an MSVC warning on unreachable code. #define EXPECT_NONFATAL_FAILURE(statement, substr) \ do {\ ::testing::TestPartResultArray gtest_failures;\ ::testing::internal::SingleFailureChecker gtest_checker(\ >est_failures, ::testing::TestPartResult::kNonFatalFailure, \ (substr));\ {\ ::testing::ScopedFakeTestPartResultReporter gtest_reporter(\ ::testing::ScopedFakeTestPartResultReporter:: \ INTERCEPT_ONLY_CURRENT_THREAD, >est_failures);\ if (::testing::internal::AlwaysTrue()) { statement; }\ }\ } while (::testing::internal::AlwaysFalse()) #define EXPECT_NONFATAL_FAILURE_ON_ALL_THREADS(statement, substr) \ do {\ ::testing::TestPartResultArray gtest_failures;\ ::testing::internal::SingleFailureChecker gtest_checker(\ >est_failures, ::testing::TestPartResult::kNonFatalFailure, \ (substr));\ {\ ::testing::ScopedFakeTestPartResultReporter gtest_reporter(\ ::testing::ScopedFakeTestPartResultReporter::INTERCEPT_ALL_THREADS,\ >est_failures);\ if (::testing::internal::AlwaysTrue()) { statement; }\ }\ } while (::testing::internal::AlwaysFalse()) #endif // GTEST_INCLUDE_GTEST_GTEST_SPI_H_ #include #include #include #include #include #include #include #include #include // NOLINT #include #include #if GTEST_OS_LINUX // TODO(kenton@google.com): Use autoconf to detect availability of // gettimeofday(). # define GTEST_HAS_GETTIMEOFDAY_ 1 # include // NOLINT # include // NOLINT # include // NOLINT // Declares vsnprintf(). This header is not available on Windows. # include // NOLINT # include // NOLINT # include // NOLINT # include // NOLINT # include #elif GTEST_OS_SYMBIAN # define GTEST_HAS_GETTIMEOFDAY_ 1 # include // NOLINT #elif GTEST_OS_ZOS # define GTEST_HAS_GETTIMEOFDAY_ 1 # include // NOLINT // On z/OS we additionally need strings.h for strcasecmp. # include // NOLINT #elif GTEST_OS_WINDOWS_MOBILE // We are on Windows CE. # include // NOLINT #elif GTEST_OS_WINDOWS // We are on Windows proper. # include // NOLINT # include // NOLINT # include // NOLINT # include // NOLINT # if GTEST_OS_WINDOWS_MINGW // MinGW has gettimeofday() but not _ftime64(). // TODO(kenton@google.com): Use autoconf to detect availability of // gettimeofday(). // TODO(kenton@google.com): There are other ways to get the time on // Windows, like GetTickCount() or GetSystemTimeAsFileTime(). MinGW // supports these. consider using them instead. # define GTEST_HAS_GETTIMEOFDAY_ 1 # include // NOLINT # endif // GTEST_OS_WINDOWS_MINGW // cpplint thinks that the header is already included, so we want to // silence it. # include // NOLINT #else // Assume other platforms have gettimeofday(). // TODO(kenton@google.com): Use autoconf to detect availability of // gettimeofday(). # define GTEST_HAS_GETTIMEOFDAY_ 1 // cpplint thinks that the header is already included, so we want to // silence it. # include // NOLINT # include // NOLINT #endif // GTEST_OS_LINUX #if GTEST_HAS_EXCEPTIONS # include #endif #if GTEST_CAN_STREAM_RESULTS_ # include // NOLINT # include // NOLINT #endif // Indicates that this translation unit is part of Google Test's // implementation. It must come before gtest-internal-inl.h is // included, or there will be a compiler error. This trick is to // prevent a user from accidentally including gtest-internal-inl.h in // his code. #define GTEST_IMPLEMENTATION_ 1 // Copyright 2005, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // Utility functions and classes used by the Google C++ testing framework. // // Author: wan@google.com (Zhanyong Wan) // // This file contains purely Google Test's internal implementation. Please // DO NOT #INCLUDE IT IN A USER PROGRAM. #ifndef GTEST_SRC_GTEST_INTERNAL_INL_H_ #define GTEST_SRC_GTEST_INTERNAL_INL_H_ // GTEST_IMPLEMENTATION_ is defined to 1 iff the current translation unit is // part of Google Test's implementation; otherwise it's undefined. #if !GTEST_IMPLEMENTATION_ // A user is trying to include this from his code - just say no. # error "gtest-internal-inl.h is part of Google Test's internal implementation." # error "It must not be included except by Google Test itself." #endif // GTEST_IMPLEMENTATION_ #ifndef _WIN32_WCE # include #endif // !_WIN32_WCE #include #include // For strtoll/_strtoul64/malloc/free. #include // For memmove. #include #include #include #if GTEST_OS_WINDOWS # include // NOLINT #endif // GTEST_OS_WINDOWS namespace testing { // Declares the flags. // // We don't want the users to modify this flag in the code, but want // Google Test's own unit tests to be able to access it. Therefore we // declare it here as opposed to in gtest.h. GTEST_DECLARE_bool_(death_test_use_fork); namespace internal { // The value of GetTestTypeId() as seen from within the Google Test // library. This is solely for testing GetTestTypeId(). GTEST_API_ extern const TypeId kTestTypeIdInGoogleTest; // Names of the flags (needed for parsing Google Test flags). const char kAlsoRunDisabledTestsFlag[] = "also_run_disabled_tests"; const char kBreakOnFailureFlag[] = "break_on_failure"; const char kCatchExceptionsFlag[] = "catch_exceptions"; const char kColorFlag[] = "color"; const char kFilterFlag[] = "filter"; const char kListTestsFlag[] = "list_tests"; const char kOutputFlag[] = "output"; const char kPrintTimeFlag[] = "print_time"; const char kRandomSeedFlag[] = "random_seed"; const char kRepeatFlag[] = "repeat"; const char kShuffleFlag[] = "shuffle"; const char kStackTraceDepthFlag[] = "stack_trace_depth"; const char kStreamResultToFlag[] = "stream_result_to"; const char kThrowOnFailureFlag[] = "throw_on_failure"; // A valid random seed must be in [1, kMaxRandomSeed]. const int kMaxRandomSeed = 99999; // g_help_flag is true iff the --help flag or an equivalent form is // specified on the command line. GTEST_API_ extern bool g_help_flag; // Returns the current time in milliseconds. GTEST_API_ TimeInMillis GetTimeInMillis(); // Returns true iff Google Test should use colors in the output. GTEST_API_ bool ShouldUseColor(bool stdout_is_tty); // Formats the given time in milliseconds as seconds. GTEST_API_ std::string FormatTimeInMillisAsSeconds(TimeInMillis ms); // Parses a string for an Int32 flag, in the form of "--flag=value". // // On success, stores the value of the flag in *value, and returns // true. On failure, returns false without changing *value. GTEST_API_ bool ParseInt32Flag( const char* str, const char* flag, Int32* value); // Returns a random seed in range [1, kMaxRandomSeed] based on the // given --gtest_random_seed flag value. inline int GetRandomSeedFromFlag(Int32 random_seed_flag) { const unsigned int raw_seed = (random_seed_flag == 0) ? static_cast(GetTimeInMillis()) : static_cast(random_seed_flag); // Normalizes the actual seed to range [1, kMaxRandomSeed] such that // it's easy to type. const int normalized_seed = static_cast((raw_seed - 1U) % static_cast(kMaxRandomSeed)) + 1; return normalized_seed; } // Returns the first valid random seed after 'seed'. The behavior is // undefined if 'seed' is invalid. The seed after kMaxRandomSeed is // considered to be 1. inline int GetNextRandomSeed(int seed) { GTEST_CHECK_(1 <= seed && seed <= kMaxRandomSeed) << "Invalid random seed " << seed << " - must be in [1, " << kMaxRandomSeed << "]."; const int next_seed = seed + 1; return (next_seed > kMaxRandomSeed) ? 1 : next_seed; } // This class saves the values of all Google Test flags in its c'tor, and // restores them in its d'tor. class GTestFlagSaver { public: // The c'tor. GTestFlagSaver() { also_run_disabled_tests_ = GTEST_FLAG(also_run_disabled_tests); break_on_failure_ = GTEST_FLAG(break_on_failure); catch_exceptions_ = GTEST_FLAG(catch_exceptions); color_ = GTEST_FLAG(color); death_test_style_ = GTEST_FLAG(death_test_style); death_test_use_fork_ = GTEST_FLAG(death_test_use_fork); filter_ = GTEST_FLAG(filter); internal_run_death_test_ = GTEST_FLAG(internal_run_death_test); list_tests_ = GTEST_FLAG(list_tests); output_ = GTEST_FLAG(output); print_time_ = GTEST_FLAG(print_time); random_seed_ = GTEST_FLAG(random_seed); repeat_ = GTEST_FLAG(repeat); shuffle_ = GTEST_FLAG(shuffle); stack_trace_depth_ = GTEST_FLAG(stack_trace_depth); stream_result_to_ = GTEST_FLAG(stream_result_to); throw_on_failure_ = GTEST_FLAG(throw_on_failure); } // The d'tor is not virtual. DO NOT INHERIT FROM THIS CLASS. ~GTestFlagSaver() { GTEST_FLAG(also_run_disabled_tests) = also_run_disabled_tests_; GTEST_FLAG(break_on_failure) = break_on_failure_; GTEST_FLAG(catch_exceptions) = catch_exceptions_; GTEST_FLAG(color) = color_; GTEST_FLAG(death_test_style) = death_test_style_; GTEST_FLAG(death_test_use_fork) = death_test_use_fork_; GTEST_FLAG(filter) = filter_; GTEST_FLAG(internal_run_death_test) = internal_run_death_test_; GTEST_FLAG(list_tests) = list_tests_; GTEST_FLAG(output) = output_; GTEST_FLAG(print_time) = print_time_; GTEST_FLAG(random_seed) = random_seed_; GTEST_FLAG(repeat) = repeat_; GTEST_FLAG(shuffle) = shuffle_; GTEST_FLAG(stack_trace_depth) = stack_trace_depth_; GTEST_FLAG(stream_result_to) = stream_result_to_; GTEST_FLAG(throw_on_failure) = throw_on_failure_; } private: // Fields for saving the original values of flags. bool also_run_disabled_tests_; bool break_on_failure_; bool catch_exceptions_; String color_; String death_test_style_; bool death_test_use_fork_; String filter_; String internal_run_death_test_; bool list_tests_; String output_; bool print_time_; bool pretty_; internal::Int32 random_seed_; internal::Int32 repeat_; bool shuffle_; internal::Int32 stack_trace_depth_; String stream_result_to_; bool throw_on_failure_; } GTEST_ATTRIBUTE_UNUSED_; // Converts a Unicode code point to a narrow string in UTF-8 encoding. // code_point parameter is of type UInt32 because wchar_t may not be // wide enough to contain a code point. // The output buffer str must containt at least 32 characters. // The function returns the address of the output buffer. // If the code_point is not a valid Unicode code point // (i.e. outside of Unicode range U+0 to U+10FFFF) it will be output // as '(Invalid Unicode 0xXXXXXXXX)'. GTEST_API_ char* CodePointToUtf8(UInt32 code_point, char* str); // Converts a wide string to a narrow string in UTF-8 encoding. // The wide string is assumed to have the following encoding: // UTF-16 if sizeof(wchar_t) == 2 (on Windows, Cygwin, Symbian OS) // UTF-32 if sizeof(wchar_t) == 4 (on Linux) // Parameter str points to a null-terminated wide string. // Parameter num_chars may additionally limit the number // of wchar_t characters processed. -1 is used when the entire string // should be processed. // If the string contains code points that are not valid Unicode code points // (i.e. outside of Unicode range U+0 to U+10FFFF) they will be output // as '(Invalid Unicode 0xXXXXXXXX)'. If the string is in UTF16 encoding // and contains invalid UTF-16 surrogate pairs, values in those pairs // will be encoded as individual Unicode characters from Basic Normal Plane. GTEST_API_ String WideStringToUtf8(const wchar_t* str, int num_chars); // Reads the GTEST_SHARD_STATUS_FILE environment variable, and creates the file // if the variable is present. If a file already exists at this location, this // function will write over it. If the variable is present, but the file cannot // be created, prints an error and exits. void WriteToShardStatusFileIfNeeded(); // Checks whether sharding is enabled by examining the relevant // environment variable values. If the variables are present, // but inconsistent (e.g., shard_index >= total_shards), prints // an error and exits. If in_subprocess_for_death_test, sharding is // disabled because it must only be applied to the original test // process. Otherwise, we could filter out death tests we intended to execute. GTEST_API_ bool ShouldShard(const char* total_shards_str, const char* shard_index_str, bool in_subprocess_for_death_test); // Parses the environment variable var as an Int32. If it is unset, // returns default_val. If it is not an Int32, prints an error and // and aborts. GTEST_API_ Int32 Int32FromEnvOrDie(const char* env_var, Int32 default_val); // Given the total number of shards, the shard index, and the test id, // returns true iff the test should be run on this shard. The test id is // some arbitrary but unique non-negative integer assigned to each test // method. Assumes that 0 <= shard_index < total_shards. GTEST_API_ bool ShouldRunTestOnShard( int total_shards, int shard_index, int test_id); // STL container utilities. // Returns the number of elements in the given container that satisfy // the given predicate. template inline int CountIf(const Container& c, Predicate predicate) { // Implemented as an explicit loop since std::count_if() in libCstd on // Solaris has a non-standard signature. int count = 0; for (typename Container::const_iterator it = c.begin(); it != c.end(); ++it) { if (predicate(*it)) ++count; } return count; } // Applies a function/functor to each element in the container. template void ForEach(const Container& c, Functor functor) { std::for_each(c.begin(), c.end(), functor); } // Returns the i-th element of the vector, or default_value if i is not // in range [0, v.size()). template inline E GetElementOr(const std::vector& v, int i, E default_value) { return (i < 0 || i >= static_cast(v.size())) ? default_value : v[i]; } // Performs an in-place shuffle of a range of the vector's elements. // 'begin' and 'end' are element indices as an STL-style range; // i.e. [begin, end) are shuffled, where 'end' == size() means to // shuffle to the end of the vector. template void ShuffleRange(internal::Random* random, int begin, int end, std::vector* v) { const int size = static_cast(v->size()); GTEST_CHECK_(0 <= begin && begin <= size) << "Invalid shuffle range start " << begin << ": must be in range [0, " << size << "]."; GTEST_CHECK_(begin <= end && end <= size) << "Invalid shuffle range finish " << end << ": must be in range [" << begin << ", " << size << "]."; // Fisher-Yates shuffle, from // http://en.wikipedia.org/wiki/Fisher-Yates_shuffle for (int range_width = end - begin; range_width >= 2; range_width--) { const int last_in_range = begin + range_width - 1; const int selected = begin + random->Generate(range_width); std::swap((*v)[selected], (*v)[last_in_range]); } } // Performs an in-place shuffle of the vector's elements. template inline void Shuffle(internal::Random* random, std::vector* v) { ShuffleRange(random, 0, static_cast(v->size()), v); } // A function for deleting an object. Handy for being used as a // functor. template static void Delete(T* x) { delete x; } // A predicate that checks the key of a TestProperty against a known key. // // TestPropertyKeyIs is copyable. class TestPropertyKeyIs { public: // Constructor. // // TestPropertyKeyIs has NO default constructor. explicit TestPropertyKeyIs(const char* key) : key_(key) {} // Returns true iff the test name of test property matches on key_. bool operator()(const TestProperty& test_property) const { return String(test_property.key()).Compare(key_) == 0; } private: String key_; }; // Class UnitTestOptions. // // This class contains functions for processing options the user // specifies when running the tests. It has only static members. // // In most cases, the user can specify an option using either an // environment variable or a command line flag. E.g. you can set the // test filter using either GTEST_FILTER or --gtest_filter. If both // the variable and the flag are present, the latter overrides the // former. class GTEST_API_ UnitTestOptions { public: // Functions for processing the gtest_output flag. // Returns the output format, or "" for normal printed output. static String GetOutputFormat(); // Returns the absolute path of the requested output file, or the // default (test_detail.xml in the original working directory) if // none was explicitly specified. static String GetAbsolutePathToOutputFile(); // Functions for processing the gtest_filter flag. // Returns true iff the wildcard pattern matches the string. The // first ':' or '\0' character in pattern marks the end of it. // // This recursive algorithm isn't very efficient, but is clear and // works well enough for matching test names, which are short. static bool PatternMatchesString(const char *pattern, const char *str); // Returns true iff the user-specified filter matches the test case // name and the test name. static bool FilterMatchesTest(const String &test_case_name, const String &test_name); #if GTEST_OS_WINDOWS // Function for supporting the gtest_catch_exception flag. // Returns EXCEPTION_EXECUTE_HANDLER if Google Test should handle the // given SEH exception, or EXCEPTION_CONTINUE_SEARCH otherwise. // This function is useful as an __except condition. static int GTestShouldProcessSEH(DWORD exception_code); #endif // GTEST_OS_WINDOWS // Returns true if "name" matches the ':' separated list of glob-style // filters in "filter". static bool MatchesFilter(const String& name, const char* filter); }; // Returns the current application's name, removing directory path if that // is present. Used by UnitTestOptions::GetOutputFile. GTEST_API_ FilePath GetCurrentExecutableName(); // The role interface for getting the OS stack trace as a string. class OsStackTraceGetterInterface { public: OsStackTraceGetterInterface() {} virtual ~OsStackTraceGetterInterface() {} // Returns the current OS stack trace as a String. Parameters: // // max_depth - the maximum number of stack frames to be included // in the trace. // skip_count - the number of top frames to be skipped; doesn't count // against max_depth. virtual String CurrentStackTrace(int max_depth, int skip_count) = 0; // UponLeavingGTest() should be called immediately before Google Test calls // user code. It saves some information about the current stack that // CurrentStackTrace() will use to find and hide Google Test stack frames. virtual void UponLeavingGTest() = 0; private: GTEST_DISALLOW_COPY_AND_ASSIGN_(OsStackTraceGetterInterface); }; // A working implementation of the OsStackTraceGetterInterface interface. class OsStackTraceGetter : public OsStackTraceGetterInterface { public: OsStackTraceGetter() : caller_frame_(NULL) {} virtual String CurrentStackTrace(int max_depth, int skip_count); virtual void UponLeavingGTest(); // This string is inserted in place of stack frames that are part of // Google Test's implementation. static const char* const kElidedFramesMarker; private: Mutex mutex_; // protects all internal state // We save the stack frame below the frame that calls user code. // We do this because the address of the frame immediately below // the user code changes between the call to UponLeavingGTest() // and any calls to CurrentStackTrace() from within the user code. void* caller_frame_; GTEST_DISALLOW_COPY_AND_ASSIGN_(OsStackTraceGetter); }; // Information about a Google Test trace point. struct TraceInfo { const char* file; int line; String message; }; // This is the default global test part result reporter used in UnitTestImpl. // This class should only be used by UnitTestImpl. class DefaultGlobalTestPartResultReporter : public TestPartResultReporterInterface { public: explicit DefaultGlobalTestPartResultReporter(UnitTestImpl* unit_test); // Implements the TestPartResultReporterInterface. Reports the test part // result in the current test. virtual void ReportTestPartResult(const TestPartResult& result); private: UnitTestImpl* const unit_test_; GTEST_DISALLOW_COPY_AND_ASSIGN_(DefaultGlobalTestPartResultReporter); }; // This is the default per thread test part result reporter used in // UnitTestImpl. This class should only be used by UnitTestImpl. class DefaultPerThreadTestPartResultReporter : public TestPartResultReporterInterface { public: explicit DefaultPerThreadTestPartResultReporter(UnitTestImpl* unit_test); // Implements the TestPartResultReporterInterface. The implementation just // delegates to the current global test part result reporter of *unit_test_. virtual void ReportTestPartResult(const TestPartResult& result); private: UnitTestImpl* const unit_test_; GTEST_DISALLOW_COPY_AND_ASSIGN_(DefaultPerThreadTestPartResultReporter); }; // The private implementation of the UnitTest class. We don't protect // the methods under a mutex, as this class is not accessible by a // user and the UnitTest class that delegates work to this class does // proper locking. class GTEST_API_ UnitTestImpl { public: explicit UnitTestImpl(UnitTest* parent); virtual ~UnitTestImpl(); // There are two different ways to register your own TestPartResultReporter. // You can register your own repoter to listen either only for test results // from the current thread or for results from all threads. // By default, each per-thread test result repoter just passes a new // TestPartResult to the global test result reporter, which registers the // test part result for the currently running test. // Returns the global test part result reporter. TestPartResultReporterInterface* GetGlobalTestPartResultReporter(); // Sets the global test part result reporter. void SetGlobalTestPartResultReporter( TestPartResultReporterInterface* reporter); // Returns the test part result reporter for the current thread. TestPartResultReporterInterface* GetTestPartResultReporterForCurrentThread(); // Sets the test part result reporter for the current thread. void SetTestPartResultReporterForCurrentThread( TestPartResultReporterInterface* reporter); // Gets the number of successful test cases. int successful_test_case_count() const; // Gets the number of failed test cases. int failed_test_case_count() const; // Gets the number of all test cases. int total_test_case_count() const; // Gets the number of all test cases that contain at least one test // that should run. int test_case_to_run_count() const; // Gets the number of successful tests. int successful_test_count() const; // Gets the number of failed tests. int failed_test_count() const; // Gets the number of disabled tests. int disabled_test_count() const; // Gets the number of all tests. int total_test_count() const; // Gets the number of tests that should run. int test_to_run_count() const; // Gets the elapsed time, in milliseconds. TimeInMillis elapsed_time() const { return elapsed_time_; } // Returns true iff the unit test passed (i.e. all test cases passed). bool Passed() const { return !Failed(); } // Returns true iff the unit test failed (i.e. some test case failed // or something outside of all tests failed). bool Failed() const { return failed_test_case_count() > 0 || ad_hoc_test_result()->Failed(); } // Gets the i-th test case among all the test cases. i can range from 0 to // total_test_case_count() - 1. If i is not in that range, returns NULL. const TestCase* GetTestCase(int i) const { const int index = GetElementOr(test_case_indices_, i, -1); return index < 0 ? NULL : test_cases_[i]; } // Gets the i-th test case among all the test cases. i can range from 0 to // total_test_case_count() - 1. If i is not in that range, returns NULL. TestCase* GetMutableTestCase(int i) { const int index = GetElementOr(test_case_indices_, i, -1); return index < 0 ? NULL : test_cases_[index]; } // Provides access to the event listener list. TestEventListeners* listeners() { return &listeners_; } // Returns the TestResult for the test that's currently running, or // the TestResult for the ad hoc test if no test is running. TestResult* current_test_result(); // Returns the TestResult for the ad hoc test. const TestResult* ad_hoc_test_result() const { return &ad_hoc_test_result_; } // Sets the OS stack trace getter. // // Does nothing if the input and the current OS stack trace getter // are the same; otherwise, deletes the old getter and makes the // input the current getter. void set_os_stack_trace_getter(OsStackTraceGetterInterface* getter); // Returns the current OS stack trace getter if it is not NULL; // otherwise, creates an OsStackTraceGetter, makes it the current // getter, and returns it. OsStackTraceGetterInterface* os_stack_trace_getter(); // Returns the current OS stack trace as a String. // // The maximum number of stack frames to be included is specified by // the gtest_stack_trace_depth flag. The skip_count parameter // specifies the number of top frames to be skipped, which doesn't // count against the number of frames to be included. // // For example, if Foo() calls Bar(), which in turn calls // CurrentOsStackTraceExceptTop(1), Foo() will be included in the // trace but Bar() and CurrentOsStackTraceExceptTop() won't. String CurrentOsStackTraceExceptTop(int skip_count); // Finds and returns a TestCase with the given name. If one doesn't // exist, creates one and returns it. // // Arguments: // // test_case_name: name of the test case // type_param: the name of the test's type parameter, or NULL if // this is not a typed or a type-parameterized test. // set_up_tc: pointer to the function that sets up the test case // tear_down_tc: pointer to the function that tears down the test case TestCase* GetTestCase(const char* test_case_name, const char* type_param, Test::SetUpTestCaseFunc set_up_tc, Test::TearDownTestCaseFunc tear_down_tc); // Adds a TestInfo to the unit test. // // Arguments: // // set_up_tc: pointer to the function that sets up the test case // tear_down_tc: pointer to the function that tears down the test case // test_info: the TestInfo object void AddTestInfo(Test::SetUpTestCaseFunc set_up_tc, Test::TearDownTestCaseFunc tear_down_tc, TestInfo* test_info) { // In order to support thread-safe death tests, we need to // remember the original working directory when the test program // was first invoked. We cannot do this in RUN_ALL_TESTS(), as // the user may have changed the current directory before calling // RUN_ALL_TESTS(). Therefore we capture the current directory in // AddTestInfo(), which is called to register a TEST or TEST_F // before main() is reached. if (original_working_dir_.IsEmpty()) { original_working_dir_.Set(FilePath::GetCurrentDir()); GTEST_CHECK_(!original_working_dir_.IsEmpty()) << "Failed to get the current working directory."; } GetTestCase(test_info->test_case_name(), test_info->type_param(), set_up_tc, tear_down_tc)->AddTestInfo(test_info); } #if GTEST_HAS_PARAM_TEST // Returns ParameterizedTestCaseRegistry object used to keep track of // value-parameterized tests and instantiate and register them. internal::ParameterizedTestCaseRegistry& parameterized_test_registry() { return parameterized_test_registry_; } #endif // GTEST_HAS_PARAM_TEST // Sets the TestCase object for the test that's currently running. void set_current_test_case(TestCase* a_current_test_case) { current_test_case_ = a_current_test_case; } // Sets the TestInfo object for the test that's currently running. If // current_test_info is NULL, the assertion results will be stored in // ad_hoc_test_result_. void set_current_test_info(TestInfo* a_current_test_info) { current_test_info_ = a_current_test_info; } // Registers all parameterized tests defined using TEST_P and // INSTANTIATE_TEST_CASE_P, creating regular tests for each test/parameter // combination. This method can be called more then once; it has guards // protecting from registering the tests more then once. If // value-parameterized tests are disabled, RegisterParameterizedTests is // present but does nothing. void RegisterParameterizedTests(); // Runs all tests in this UnitTest object, prints the result, and // returns true if all tests are successful. If any exception is // thrown during a test, this test is considered to be failed, but // the rest of the tests will still be run. bool RunAllTests(); // Clears the results of all tests, except the ad hoc tests. void ClearNonAdHocTestResult() { ForEach(test_cases_, TestCase::ClearTestCaseResult); } // Clears the results of ad-hoc test assertions. void ClearAdHocTestResult() { ad_hoc_test_result_.Clear(); } enum ReactionToSharding { HONOR_SHARDING_PROTOCOL, IGNORE_SHARDING_PROTOCOL }; // Matches the full name of each test against the user-specified // filter to decide whether the test should run, then records the // result in each TestCase and TestInfo object. // If shard_tests == HONOR_SHARDING_PROTOCOL, further filters tests // based on sharding variables in the environment. // Returns the number of tests that should run. int FilterTests(ReactionToSharding shard_tests); // Prints the names of the tests matching the user-specified filter flag. void ListTestsMatchingFilter(); const TestCase* current_test_case() const { return current_test_case_; } TestInfo* current_test_info() { return current_test_info_; } const TestInfo* current_test_info() const { return current_test_info_; } // Returns the vector of environments that need to be set-up/torn-down // before/after the tests are run. std::vector& environments() { return environments_; } // Getters for the per-thread Google Test trace stack. std::vector& gtest_trace_stack() { return *(gtest_trace_stack_.pointer()); } const std::vector& gtest_trace_stack() const { return gtest_trace_stack_.get(); } #if GTEST_HAS_DEATH_TEST void InitDeathTestSubprocessControlInfo() { internal_run_death_test_flag_.reset(ParseInternalRunDeathTestFlag()); } // Returns a pointer to the parsed --gtest_internal_run_death_test // flag, or NULL if that flag was not specified. // This information is useful only in a death test child process. // Must not be called before a call to InitGoogleTest. const InternalRunDeathTestFlag* internal_run_death_test_flag() const { return internal_run_death_test_flag_.get(); } // Returns a pointer to the current death test factory. internal::DeathTestFactory* death_test_factory() { return death_test_factory_.get(); } void SuppressTestEventsIfInSubprocess(); friend class ReplaceDeathTestFactory; #endif // GTEST_HAS_DEATH_TEST // Initializes the event listener performing XML output as specified by // UnitTestOptions. Must not be called before InitGoogleTest. void ConfigureXmlOutput(); #if GTEST_CAN_STREAM_RESULTS_ // Initializes the event listener for streaming test results to a socket. // Must not be called before InitGoogleTest. void ConfigureStreamingOutput(); #endif // Performs initialization dependent upon flag values obtained in // ParseGoogleTestFlagsOnly. Is called from InitGoogleTest after the call to // ParseGoogleTestFlagsOnly. In case a user neglects to call InitGoogleTest // this function is also called from RunAllTests. Since this function can be // called more than once, it has to be idempotent. void PostFlagParsingInit(); // Gets the random seed used at the start of the current test iteration. int random_seed() const { return random_seed_; } // Gets the random number generator. internal::Random* random() { return &random_; } // Shuffles all test cases, and the tests within each test case, // making sure that death tests are still run first. void ShuffleTests(); // Restores the test cases and tests to their order before the first shuffle. void UnshuffleTests(); // Returns the value of GTEST_FLAG(catch_exceptions) at the moment // UnitTest::Run() starts. bool catch_exceptions() const { return catch_exceptions_; } private: friend class ::testing::UnitTest; // Used by UnitTest::Run() to capture the state of // GTEST_FLAG(catch_exceptions) at the moment it starts. void set_catch_exceptions(bool value) { catch_exceptions_ = value; } // The UnitTest object that owns this implementation object. UnitTest* const parent_; // The working directory when the first TEST() or TEST_F() was // executed. internal::FilePath original_working_dir_; // The default test part result reporters. DefaultGlobalTestPartResultReporter default_global_test_part_result_reporter_; DefaultPerThreadTestPartResultReporter default_per_thread_test_part_result_reporter_; // Points to (but doesn't own) the global test part result reporter. TestPartResultReporterInterface* global_test_part_result_repoter_; // Protects read and write access to global_test_part_result_reporter_. internal::Mutex global_test_part_result_reporter_mutex_; // Points to (but doesn't own) the per-thread test part result reporter. internal::ThreadLocal per_thread_test_part_result_reporter_; // The vector of environments that need to be set-up/torn-down // before/after the tests are run. std::vector environments_; // The vector of TestCases in their original order. It owns the // elements in the vector. std::vector test_cases_; // Provides a level of indirection for the test case list to allow // easy shuffling and restoring the test case order. The i-th // element of this vector is the index of the i-th test case in the // shuffled order. std::vector test_case_indices_; #if GTEST_HAS_PARAM_TEST // ParameterizedTestRegistry object used to register value-parameterized // tests. internal::ParameterizedTestCaseRegistry parameterized_test_registry_; // Indicates whether RegisterParameterizedTests() has been called already. bool parameterized_tests_registered_; #endif // GTEST_HAS_PARAM_TEST // Index of the last death test case registered. Initially -1. int last_death_test_case_; // This points to the TestCase for the currently running test. It // changes as Google Test goes through one test case after another. // When no test is running, this is set to NULL and Google Test // stores assertion results in ad_hoc_test_result_. Initially NULL. TestCase* current_test_case_; // This points to the TestInfo for the currently running test. It // changes as Google Test goes through one test after another. When // no test is running, this is set to NULL and Google Test stores // assertion results in ad_hoc_test_result_. Initially NULL. TestInfo* current_test_info_; // Normally, a user only writes assertions inside a TEST or TEST_F, // or inside a function called by a TEST or TEST_F. Since Google // Test keeps track of which test is current running, it can // associate such an assertion with the test it belongs to. // // If an assertion is encountered when no TEST or TEST_F is running, // Google Test attributes the assertion result to an imaginary "ad hoc" // test, and records the result in ad_hoc_test_result_. TestResult ad_hoc_test_result_; // The list of event listeners that can be used to track events inside // Google Test. TestEventListeners listeners_; // The OS stack trace getter. Will be deleted when the UnitTest // object is destructed. By default, an OsStackTraceGetter is used, // but the user can set this field to use a custom getter if that is // desired. OsStackTraceGetterInterface* os_stack_trace_getter_; // True iff PostFlagParsingInit() has been called. bool post_flag_parse_init_performed_; // The random number seed used at the beginning of the test run. int random_seed_; // Our random number generator. internal::Random random_; // How long the test took to run, in milliseconds. TimeInMillis elapsed_time_; #if GTEST_HAS_DEATH_TEST // The decomposed components of the gtest_internal_run_death_test flag, // parsed when RUN_ALL_TESTS is called. internal::scoped_ptr internal_run_death_test_flag_; internal::scoped_ptr death_test_factory_; #endif // GTEST_HAS_DEATH_TEST // A per-thread stack of traces created by the SCOPED_TRACE() macro. internal::ThreadLocal > gtest_trace_stack_; // The value of GTEST_FLAG(catch_exceptions) at the moment RunAllTests() // starts. bool catch_exceptions_; GTEST_DISALLOW_COPY_AND_ASSIGN_(UnitTestImpl); }; // class UnitTestImpl // Convenience function for accessing the global UnitTest // implementation object. inline UnitTestImpl* GetUnitTestImpl() { return UnitTest::GetInstance()->impl(); } #if GTEST_USES_SIMPLE_RE // Internal helper functions for implementing the simple regular // expression matcher. GTEST_API_ bool IsInSet(char ch, const char* str); GTEST_API_ bool IsAsciiDigit(char ch); GTEST_API_ bool IsAsciiPunct(char ch); GTEST_API_ bool IsRepeat(char ch); GTEST_API_ bool IsAsciiWhiteSpace(char ch); GTEST_API_ bool IsAsciiWordChar(char ch); GTEST_API_ bool IsValidEscape(char ch); GTEST_API_ bool AtomMatchesChar(bool escaped, char pattern, char ch); GTEST_API_ bool ValidateRegex(const char* regex); GTEST_API_ bool MatchRegexAtHead(const char* regex, const char* str); GTEST_API_ bool MatchRepetitionAndRegexAtHead( bool escaped, char ch, char repeat, const char* regex, const char* str); GTEST_API_ bool MatchRegexAnywhere(const char* regex, const char* str); #endif // GTEST_USES_SIMPLE_RE // Parses the command line for Google Test flags, without initializing // other parts of Google Test. GTEST_API_ void ParseGoogleTestFlagsOnly(int* argc, char** argv); GTEST_API_ void ParseGoogleTestFlagsOnly(int* argc, wchar_t** argv); #if GTEST_HAS_DEATH_TEST // Returns the message describing the last system error, regardless of the // platform. GTEST_API_ String GetLastErrnoDescription(); # if GTEST_OS_WINDOWS // Provides leak-safe Windows kernel handle ownership. class AutoHandle { public: AutoHandle() : handle_(INVALID_HANDLE_VALUE) {} explicit AutoHandle(HANDLE handle) : handle_(handle) {} ~AutoHandle() { Reset(); } HANDLE Get() const { return handle_; } void Reset() { Reset(INVALID_HANDLE_VALUE); } void Reset(HANDLE handle) { if (handle != handle_) { if (handle_ != INVALID_HANDLE_VALUE) ::CloseHandle(handle_); handle_ = handle; } } private: HANDLE handle_; GTEST_DISALLOW_COPY_AND_ASSIGN_(AutoHandle); }; # endif // GTEST_OS_WINDOWS // Attempts to parse a string into a positive integer pointed to by the // number parameter. Returns true if that is possible. // GTEST_HAS_DEATH_TEST implies that we have ::std::string, so we can use // it here. template bool ParseNaturalNumber(const ::std::string& str, Integer* number) { // Fail fast if the given string does not begin with a digit; // this bypasses strtoXXX's "optional leading whitespace and plus // or minus sign" semantics, which are undesirable here. if (str.empty() || !IsDigit(str[0])) { return false; } errno = 0; char* end; // BiggestConvertible is the largest integer type that system-provided // string-to-number conversion routines can return. # if GTEST_OS_WINDOWS && !defined(__GNUC__) // MSVC and C++ Builder define __int64 instead of the standard long long. typedef unsigned __int64 BiggestConvertible; const BiggestConvertible parsed = _strtoui64(str.c_str(), &end, 10); # else typedef unsigned long long BiggestConvertible; // NOLINT const BiggestConvertible parsed = strtoull(str.c_str(), &end, 10); # endif // GTEST_OS_WINDOWS && !defined(__GNUC__) const bool parse_success = *end == '\0' && errno == 0; // TODO(vladl@google.com): Convert this to compile time assertion when it is // available. GTEST_CHECK_(sizeof(Integer) <= sizeof(parsed)); const Integer result = static_cast(parsed); if (parse_success && static_cast(result) == parsed) { *number = result; return true; } return false; } #endif // GTEST_HAS_DEATH_TEST // TestResult contains some private methods that should be hidden from // Google Test user but are required for testing. This class allow our tests // to access them. // // This class is supplied only for the purpose of testing Google Test's own // constructs. Do not use it in user tests, either directly or indirectly. class TestResultAccessor { public: static void RecordProperty(TestResult* test_result, const TestProperty& property) { test_result->RecordProperty(property); } static void ClearTestPartResults(TestResult* test_result) { test_result->ClearTestPartResults(); } static const std::vector& test_part_results( const TestResult& test_result) { return test_result.test_part_results(); } }; } // namespace internal } // namespace testing #endif // GTEST_SRC_GTEST_INTERNAL_INL_H_ #undef GTEST_IMPLEMENTATION_ #if GTEST_OS_WINDOWS # define vsnprintf _vsnprintf #endif // GTEST_OS_WINDOWS namespace testing { using internal::CountIf; using internal::ForEach; using internal::GetElementOr; using internal::Shuffle; // Constants. // A test whose test case name or test name matches this filter is // disabled and not run. static const char kDisableTestFilter[] = "DISABLED_*:*/DISABLED_*"; // A test case whose name matches this filter is considered a death // test case and will be run before test cases whose name doesn't // match this filter. static const char kDeathTestCaseFilter[] = "*DeathTest:*DeathTest/*"; // A test filter that matches everything. static const char kUniversalFilter[] = "*"; // The default output file for XML output. static const char kDefaultOutputFile[] = "test_detail.xml"; // The environment variable name for the test shard index. static const char kTestShardIndex[] = "GTEST_SHARD_INDEX"; // The environment variable name for the total number of test shards. static const char kTestTotalShards[] = "GTEST_TOTAL_SHARDS"; // The environment variable name for the test shard status file. static const char kTestShardStatusFile[] = "GTEST_SHARD_STATUS_FILE"; namespace internal { // The text used in failure messages to indicate the start of the // stack trace. const char kStackTraceMarker[] = "\nStack trace:\n"; // g_help_flag is true iff the --help flag or an equivalent form is // specified on the command line. bool g_help_flag = false; } // namespace internal GTEST_DEFINE_bool_( also_run_disabled_tests, internal::BoolFromGTestEnv("also_run_disabled_tests", false), "Run disabled tests too, in addition to the tests normally being run."); GTEST_DEFINE_bool_( break_on_failure, internal::BoolFromGTestEnv("break_on_failure", false), "True iff a failed assertion should be a debugger break-point."); GTEST_DEFINE_bool_( catch_exceptions, internal::BoolFromGTestEnv("catch_exceptions", true), "True iff " GTEST_NAME_ " should catch exceptions and treat them as test failures."); GTEST_DEFINE_string_( color, internal::StringFromGTestEnv("color", "auto"), "Whether to use colors in the output. Valid values: yes, no, " "and auto. 'auto' means to use colors if the output is " "being sent to a terminal and the TERM environment variable " "is set to xterm, xterm-color, xterm-256color, linux or cygwin."); GTEST_DEFINE_string_( filter, internal::StringFromGTestEnv("filter", kUniversalFilter), "A colon-separated list of glob (not regex) patterns " "for filtering the tests to run, optionally followed by a " "'-' and a : separated list of negative patterns (tests to " "exclude). A test is run if it matches one of the positive " "patterns and does not match any of the negative patterns."); GTEST_DEFINE_bool_(list_tests, false, "List all tests without running them."); GTEST_DEFINE_string_( output, internal::StringFromGTestEnv("output", ""), "A format (currently must be \"xml\"), optionally followed " "by a colon and an output file name or directory. A directory " "is indicated by a trailing pathname separator. " "Examples: \"xml:filename.xml\", \"xml::directoryname/\". " "If a directory is specified, output files will be created " "within that directory, with file-names based on the test " "executable's name and, if necessary, made unique by adding " "digits."); GTEST_DEFINE_bool_( print_time, internal::BoolFromGTestEnv("print_time", true), "True iff " GTEST_NAME_ " should display elapsed time in text output."); GTEST_DEFINE_int32_( random_seed, internal::Int32FromGTestEnv("random_seed", 0), "Random number seed to use when shuffling test orders. Must be in range " "[1, 99999], or 0 to use a seed based on the current time."); GTEST_DEFINE_int32_( repeat, internal::Int32FromGTestEnv("repeat", 1), "How many times to repeat each test. Specify a negative number " "for repeating forever. Useful for shaking out flaky tests."); GTEST_DEFINE_bool_( show_internal_stack_frames, false, "True iff " GTEST_NAME_ " should include internal stack frames when " "printing test failure stack traces."); GTEST_DEFINE_bool_( shuffle, internal::BoolFromGTestEnv("shuffle", false), "True iff " GTEST_NAME_ " should randomize tests' order on every run."); GTEST_DEFINE_int32_( stack_trace_depth, internal::Int32FromGTestEnv("stack_trace_depth", kMaxStackTraceDepth), "The maximum number of stack frames to print when an " "assertion fails. The valid range is 0 through 100, inclusive."); GTEST_DEFINE_string_( stream_result_to, internal::StringFromGTestEnv("stream_result_to", ""), "This flag specifies the host name and the port number on which to stream " "test results. Example: \"localhost:555\". The flag is effective only on " "Linux."); GTEST_DEFINE_bool_( throw_on_failure, internal::BoolFromGTestEnv("throw_on_failure", false), "When this flag is specified, a failed assertion will throw an exception " "if exceptions are enabled or exit the program with a non-zero code " "otherwise."); namespace internal { // Generates a random number from [0, range), using a Linear // Congruential Generator (LCG). Crashes if 'range' is 0 or greater // than kMaxRange. UInt32 Random::Generate(UInt32 range) { // These constants are the same as are used in glibc's rand(3). state_ = (1103515245U*state_ + 12345U) % kMaxRange; GTEST_CHECK_(range > 0) << "Cannot generate a number in the range [0, 0)."; GTEST_CHECK_(range <= kMaxRange) << "Generation of a number in [0, " << range << ") was requested, " << "but this can only generate numbers in [0, " << kMaxRange << ")."; // Converting via modulus introduces a bit of downward bias, but // it's simple, and a linear congruential generator isn't too good // to begin with. return state_ % range; } // GTestIsInitialized() returns true iff the user has initialized // Google Test. Useful for catching the user mistake of not initializing // Google Test before calling RUN_ALL_TESTS(). // // A user must call testing::InitGoogleTest() to initialize Google // Test. g_init_gtest_count is set to the number of times // InitGoogleTest() has been called. We don't protect this variable // under a mutex as it is only accessed in the main thread. int g_init_gtest_count = 0; static bool GTestIsInitialized() { return g_init_gtest_count != 0; } // Iterates over a vector of TestCases, keeping a running sum of the // results of calling a given int-returning method on each. // Returns the sum. static int SumOverTestCaseList(const std::vector& case_list, int (TestCase::*method)() const) { int sum = 0; for (size_t i = 0; i < case_list.size(); i++) { sum += (case_list[i]->*method)(); } return sum; } // Returns true iff the test case passed. static bool TestCasePassed(const TestCase* test_case) { return test_case->should_run() && test_case->Passed(); } // Returns true iff the test case failed. static bool TestCaseFailed(const TestCase* test_case) { return test_case->should_run() && test_case->Failed(); } // Returns true iff test_case contains at least one test that should // run. static bool ShouldRunTestCase(const TestCase* test_case) { return test_case->should_run(); } // AssertHelper constructor. AssertHelper::AssertHelper(TestPartResult::Type type, const char* file, int line, const char* message) : data_(new AssertHelperData(type, file, line, message)) { } AssertHelper::~AssertHelper() { delete data_; } // Message assignment, for assertion streaming support. void AssertHelper::operator=(const Message& message) const { UnitTest::GetInstance()-> AddTestPartResult(data_->type, data_->file, data_->line, AppendUserMessage(data_->message, message), UnitTest::GetInstance()->impl() ->CurrentOsStackTraceExceptTop(1) // Skips the stack frame for this function itself. ); // NOLINT } // Mutex for linked pointers. GTEST_DEFINE_STATIC_MUTEX_(g_linked_ptr_mutex); // Application pathname gotten in InitGoogleTest. String g_executable_path; // Returns the current application's name, removing directory path if that // is present. FilePath GetCurrentExecutableName() { FilePath result; #if GTEST_OS_WINDOWS result.Set(FilePath(g_executable_path).RemoveExtension("exe")); #else result.Set(FilePath(g_executable_path)); #endif // GTEST_OS_WINDOWS return result.RemoveDirectoryName(); } // Functions for processing the gtest_output flag. // Returns the output format, or "" for normal printed output. String UnitTestOptions::GetOutputFormat() { const char* const gtest_output_flag = GTEST_FLAG(output).c_str(); if (gtest_output_flag == NULL) return String(""); const char* const colon = strchr(gtest_output_flag, ':'); return (colon == NULL) ? String(gtest_output_flag) : String(gtest_output_flag, colon - gtest_output_flag); } // Returns the name of the requested output file, or the default if none // was explicitly specified. String UnitTestOptions::GetAbsolutePathToOutputFile() { const char* const gtest_output_flag = GTEST_FLAG(output).c_str(); if (gtest_output_flag == NULL) return String(""); const char* const colon = strchr(gtest_output_flag, ':'); if (colon == NULL) return String(internal::FilePath::ConcatPaths( internal::FilePath( UnitTest::GetInstance()->original_working_dir()), internal::FilePath(kDefaultOutputFile)).ToString() ); internal::FilePath output_name(colon + 1); if (!output_name.IsAbsolutePath()) // TODO(wan@google.com): on Windows \some\path is not an absolute // path (as its meaning depends on the current drive), yet the // following logic for turning it into an absolute path is wrong. // Fix it. output_name = internal::FilePath::ConcatPaths( internal::FilePath(UnitTest::GetInstance()->original_working_dir()), internal::FilePath(colon + 1)); if (!output_name.IsDirectory()) return output_name.ToString(); internal::FilePath result(internal::FilePath::GenerateUniqueFileName( output_name, internal::GetCurrentExecutableName(), GetOutputFormat().c_str())); return result.ToString(); } // Returns true iff the wildcard pattern matches the string. The // first ':' or '\0' character in pattern marks the end of it. // // This recursive algorithm isn't very efficient, but is clear and // works well enough for matching test names, which are short. bool UnitTestOptions::PatternMatchesString(const char *pattern, const char *str) { switch (*pattern) { case '\0': case ':': // Either ':' or '\0' marks the end of the pattern. return *str == '\0'; case '?': // Matches any single character. return *str != '\0' && PatternMatchesString(pattern + 1, str + 1); case '*': // Matches any string (possibly empty) of characters. return (*str != '\0' && PatternMatchesString(pattern, str + 1)) || PatternMatchesString(pattern + 1, str); default: // Non-special character. Matches itself. return *pattern == *str && PatternMatchesString(pattern + 1, str + 1); } } bool UnitTestOptions::MatchesFilter(const String& name, const char* filter) { const char *cur_pattern = filter; for (;;) { if (PatternMatchesString(cur_pattern, name.c_str())) { return true; } // Finds the next pattern in the filter. cur_pattern = strchr(cur_pattern, ':'); // Returns if no more pattern can be found. if (cur_pattern == NULL) { return false; } // Skips the pattern separater (the ':' character). cur_pattern++; } } // TODO(keithray): move String function implementations to gtest-string.cc. // Returns true iff the user-specified filter matches the test case // name and the test name. bool UnitTestOptions::FilterMatchesTest(const String &test_case_name, const String &test_name) { const String& full_name = String::Format("%s.%s", test_case_name.c_str(), test_name.c_str()); // Split --gtest_filter at '-', if there is one, to separate into // positive filter and negative filter portions const char* const p = GTEST_FLAG(filter).c_str(); const char* const dash = strchr(p, '-'); String positive; String negative; if (dash == NULL) { positive = GTEST_FLAG(filter).c_str(); // Whole string is a positive filter negative = String(""); } else { positive = String(p, dash - p); // Everything up to the dash negative = String(dash+1); // Everything after the dash if (positive.empty()) { // Treat '-test1' as the same as '*-test1' positive = kUniversalFilter; } } // A filter is a colon-separated list of patterns. It matches a // test if any pattern in it matches the test. return (MatchesFilter(full_name, positive.c_str()) && !MatchesFilter(full_name, negative.c_str())); } #if GTEST_HAS_SEH // Returns EXCEPTION_EXECUTE_HANDLER if Google Test should handle the // given SEH exception, or EXCEPTION_CONTINUE_SEARCH otherwise. // This function is useful as an __except condition. int UnitTestOptions::GTestShouldProcessSEH(DWORD exception_code) { // Google Test should handle a SEH exception if: // 1. the user wants it to, AND // 2. this is not a breakpoint exception, AND // 3. this is not a C++ exception (VC++ implements them via SEH, // apparently). // // SEH exception code for C++ exceptions. // (see http://support.microsoft.com/kb/185294 for more information). const DWORD kCxxExceptionCode = 0xe06d7363; bool should_handle = true; if (!GTEST_FLAG(catch_exceptions)) should_handle = false; else if (exception_code == EXCEPTION_BREAKPOINT) should_handle = false; else if (exception_code == kCxxExceptionCode) should_handle = false; return should_handle ? EXCEPTION_EXECUTE_HANDLER : EXCEPTION_CONTINUE_SEARCH; } #endif // GTEST_HAS_SEH } // namespace internal // The c'tor sets this object as the test part result reporter used by // Google Test. The 'result' parameter specifies where to report the // results. Intercepts only failures from the current thread. ScopedFakeTestPartResultReporter::ScopedFakeTestPartResultReporter( TestPartResultArray* result) : intercept_mode_(INTERCEPT_ONLY_CURRENT_THREAD), result_(result) { Init(); } // The c'tor sets this object as the test part result reporter used by // Google Test. The 'result' parameter specifies where to report the // results. ScopedFakeTestPartResultReporter::ScopedFakeTestPartResultReporter( InterceptMode intercept_mode, TestPartResultArray* result) : intercept_mode_(intercept_mode), result_(result) { Init(); } void ScopedFakeTestPartResultReporter::Init() { internal::UnitTestImpl* const impl = internal::GetUnitTestImpl(); if (intercept_mode_ == INTERCEPT_ALL_THREADS) { old_reporter_ = impl->GetGlobalTestPartResultReporter(); impl->SetGlobalTestPartResultReporter(this); } else { old_reporter_ = impl->GetTestPartResultReporterForCurrentThread(); impl->SetTestPartResultReporterForCurrentThread(this); } } // The d'tor restores the test part result reporter used by Google Test // before. ScopedFakeTestPartResultReporter::~ScopedFakeTestPartResultReporter() { internal::UnitTestImpl* const impl = internal::GetUnitTestImpl(); if (intercept_mode_ == INTERCEPT_ALL_THREADS) { impl->SetGlobalTestPartResultReporter(old_reporter_); } else { impl->SetTestPartResultReporterForCurrentThread(old_reporter_); } } // Increments the test part result count and remembers the result. // This method is from the TestPartResultReporterInterface interface. void ScopedFakeTestPartResultReporter::ReportTestPartResult( const TestPartResult& result) { result_->Append(result); } namespace internal { // Returns the type ID of ::testing::Test. We should always call this // instead of GetTypeId< ::testing::Test>() to get the type ID of // testing::Test. This is to work around a suspected linker bug when // using Google Test as a framework on Mac OS X. The bug causes // GetTypeId< ::testing::Test>() to return different values depending // on whether the call is from the Google Test framework itself or // from user test code. GetTestTypeId() is guaranteed to always // return the same value, as it always calls GetTypeId<>() from the // gtest.cc, which is within the Google Test framework. TypeId GetTestTypeId() { return GetTypeId(); } // The value of GetTestTypeId() as seen from within the Google Test // library. This is solely for testing GetTestTypeId(). extern const TypeId kTestTypeIdInGoogleTest = GetTestTypeId(); // This predicate-formatter checks that 'results' contains a test part // failure of the given type and that the failure message contains the // given substring. AssertionResult HasOneFailure(const char* /* results_expr */, const char* /* type_expr */, const char* /* substr_expr */, const TestPartResultArray& results, TestPartResult::Type type, const string& substr) { const String expected(type == TestPartResult::kFatalFailure ? "1 fatal failure" : "1 non-fatal failure"); Message msg; if (results.size() != 1) { msg << "Expected: " << expected << "\n" << " Actual: " << results.size() << " failures"; for (int i = 0; i < results.size(); i++) { msg << "\n" << results.GetTestPartResult(i); } return AssertionFailure() << msg; } const TestPartResult& r = results.GetTestPartResult(0); if (r.type() != type) { return AssertionFailure() << "Expected: " << expected << "\n" << " Actual:\n" << r; } if (strstr(r.message(), substr.c_str()) == NULL) { return AssertionFailure() << "Expected: " << expected << " containing \"" << substr << "\"\n" << " Actual:\n" << r; } return AssertionSuccess(); } // The constructor of SingleFailureChecker remembers where to look up // test part results, what type of failure we expect, and what // substring the failure message should contain. SingleFailureChecker:: SingleFailureChecker( const TestPartResultArray* results, TestPartResult::Type type, const string& substr) : results_(results), type_(type), substr_(substr) {} // The destructor of SingleFailureChecker verifies that the given // TestPartResultArray contains exactly one failure that has the given // type and contains the given substring. If that's not the case, a // non-fatal failure will be generated. SingleFailureChecker::~SingleFailureChecker() { EXPECT_PRED_FORMAT3(HasOneFailure, *results_, type_, substr_); } DefaultGlobalTestPartResultReporter::DefaultGlobalTestPartResultReporter( UnitTestImpl* unit_test) : unit_test_(unit_test) {} void DefaultGlobalTestPartResultReporter::ReportTestPartResult( const TestPartResult& result) { unit_test_->current_test_result()->AddTestPartResult(result); unit_test_->listeners()->repeater()->OnTestPartResult(result); } DefaultPerThreadTestPartResultReporter::DefaultPerThreadTestPartResultReporter( UnitTestImpl* unit_test) : unit_test_(unit_test) {} void DefaultPerThreadTestPartResultReporter::ReportTestPartResult( const TestPartResult& result) { unit_test_->GetGlobalTestPartResultReporter()->ReportTestPartResult(result); } // Returns the global test part result reporter. TestPartResultReporterInterface* UnitTestImpl::GetGlobalTestPartResultReporter() { internal::MutexLock lock(&global_test_part_result_reporter_mutex_); return global_test_part_result_repoter_; } // Sets the global test part result reporter. void UnitTestImpl::SetGlobalTestPartResultReporter( TestPartResultReporterInterface* reporter) { internal::MutexLock lock(&global_test_part_result_reporter_mutex_); global_test_part_result_repoter_ = reporter; } // Returns the test part result reporter for the current thread. TestPartResultReporterInterface* UnitTestImpl::GetTestPartResultReporterForCurrentThread() { return per_thread_test_part_result_reporter_.get(); } // Sets the test part result reporter for the current thread. void UnitTestImpl::SetTestPartResultReporterForCurrentThread( TestPartResultReporterInterface* reporter) { per_thread_test_part_result_reporter_.set(reporter); } // Gets the number of successful test cases. int UnitTestImpl::successful_test_case_count() const { return CountIf(test_cases_, TestCasePassed); } // Gets the number of failed test cases. int UnitTestImpl::failed_test_case_count() const { return CountIf(test_cases_, TestCaseFailed); } // Gets the number of all test cases. int UnitTestImpl::total_test_case_count() const { return static_cast(test_cases_.size()); } // Gets the number of all test cases that contain at least one test // that should run. int UnitTestImpl::test_case_to_run_count() const { return CountIf(test_cases_, ShouldRunTestCase); } // Gets the number of successful tests. int UnitTestImpl::successful_test_count() const { return SumOverTestCaseList(test_cases_, &TestCase::successful_test_count); } // Gets the number of failed tests. int UnitTestImpl::failed_test_count() const { return SumOverTestCaseList(test_cases_, &TestCase::failed_test_count); } // Gets the number of disabled tests. int UnitTestImpl::disabled_test_count() const { return SumOverTestCaseList(test_cases_, &TestCase::disabled_test_count); } // Gets the number of all tests. int UnitTestImpl::total_test_count() const { return SumOverTestCaseList(test_cases_, &TestCase::total_test_count); } // Gets the number of tests that should run. int UnitTestImpl::test_to_run_count() const { return SumOverTestCaseList(test_cases_, &TestCase::test_to_run_count); } // Returns the current OS stack trace as a String. // // The maximum number of stack frames to be included is specified by // the gtest_stack_trace_depth flag. The skip_count parameter // specifies the number of top frames to be skipped, which doesn't // count against the number of frames to be included. // // For example, if Foo() calls Bar(), which in turn calls // CurrentOsStackTraceExceptTop(1), Foo() will be included in the // trace but Bar() and CurrentOsStackTraceExceptTop() won't. String UnitTestImpl::CurrentOsStackTraceExceptTop(int skip_count) { (void)skip_count; return String(""); } // Returns the current time in milliseconds. TimeInMillis GetTimeInMillis() { #if GTEST_OS_WINDOWS_MOBILE || defined(__BORLANDC__) // Difference between 1970-01-01 and 1601-01-01 in milliseconds. // http://analogous.blogspot.com/2005/04/epoch.html const TimeInMillis kJavaEpochToWinFileTimeDelta = static_cast(116444736UL) * 100000UL; const DWORD kTenthMicrosInMilliSecond = 10000; SYSTEMTIME now_systime; FILETIME now_filetime; ULARGE_INTEGER now_int64; // TODO(kenton@google.com): Shouldn't this just use // GetSystemTimeAsFileTime()? GetSystemTime(&now_systime); if (SystemTimeToFileTime(&now_systime, &now_filetime)) { now_int64.LowPart = now_filetime.dwLowDateTime; now_int64.HighPart = now_filetime.dwHighDateTime; now_int64.QuadPart = (now_int64.QuadPart / kTenthMicrosInMilliSecond) - kJavaEpochToWinFileTimeDelta; return now_int64.QuadPart; } return 0; #elif GTEST_OS_WINDOWS && !GTEST_HAS_GETTIMEOFDAY_ __timeb64 now; # ifdef _MSC_VER // MSVC 8 deprecates _ftime64(), so we want to suppress warning 4996 // (deprecated function) there. // TODO(kenton@google.com): Use GetTickCount()? Or use // SystemTimeToFileTime() # pragma warning(push) // Saves the current warning state. # pragma warning(disable:4996) // Temporarily disables warning 4996. _ftime64(&now); # pragma warning(pop) // Restores the warning state. # else _ftime64(&now); # endif // _MSC_VER return static_cast(now.time) * 1000 + now.millitm; #elif GTEST_HAS_GETTIMEOFDAY_ struct timeval now; gettimeofday(&now, NULL); return static_cast(now.tv_sec) * 1000 + now.tv_usec / 1000; #else # error "Don't know how to get the current time on your system." #endif } // Utilities // class String // Returns the input enclosed in double quotes if it's not NULL; // otherwise returns "(null)". For example, "\"Hello\"" is returned // for input "Hello". // // This is useful for printing a C string in the syntax of a literal. // // Known issue: escape sequences are not handled yet. String String::ShowCStringQuoted(const char* c_str) { return c_str ? String::Format("\"%s\"", c_str) : String("(null)"); } // Copies at most length characters from str into a newly-allocated // piece of memory of size length+1. The memory is allocated with new[]. // A terminating null byte is written to the memory, and a pointer to it // is returned. If str is NULL, NULL is returned. static char* CloneString(const char* str, size_t length) { if (str == NULL) { return NULL; } else { char* const clone = new char[length + 1]; posix::StrNCpy(clone, str, length); clone[length] = '\0'; return clone; } } // Clones a 0-terminated C string, allocating memory using new. The // caller is responsible for deleting[] the return value. Returns the // cloned string, or NULL if the input is NULL. const char * String::CloneCString(const char* c_str) { return (c_str == NULL) ? NULL : CloneString(c_str, strlen(c_str)); } #if GTEST_OS_WINDOWS_MOBILE // Creates a UTF-16 wide string from the given ANSI string, allocating // memory using new. The caller is responsible for deleting the return // value using delete[]. Returns the wide string, or NULL if the // input is NULL. LPCWSTR String::AnsiToUtf16(const char* ansi) { if (!ansi) return NULL; const int length = strlen(ansi); const int unicode_length = MultiByteToWideChar(CP_ACP, 0, ansi, length, NULL, 0); WCHAR* unicode = new WCHAR[unicode_length + 1]; MultiByteToWideChar(CP_ACP, 0, ansi, length, unicode, unicode_length); unicode[unicode_length] = 0; return unicode; } // Creates an ANSI string from the given wide string, allocating // memory using new. The caller is responsible for deleting the return // value using delete[]. Returns the ANSI string, or NULL if the // input is NULL. const char* String::Utf16ToAnsi(LPCWSTR utf16_str) { if (!utf16_str) return NULL; const int ansi_length = WideCharToMultiByte(CP_ACP, 0, utf16_str, -1, NULL, 0, NULL, NULL); char* ansi = new char[ansi_length + 1]; WideCharToMultiByte(CP_ACP, 0, utf16_str, -1, ansi, ansi_length, NULL, NULL); ansi[ansi_length] = 0; return ansi; } #endif // GTEST_OS_WINDOWS_MOBILE // Compares two C strings. Returns true iff they have the same content. // // Unlike strcmp(), this function can handle NULL argument(s). A NULL // C string is considered different to any non-NULL C string, // including the empty string. bool String::CStringEquals(const char * lhs, const char * rhs) { if ( lhs == NULL ) return rhs == NULL; if ( rhs == NULL ) return false; return strcmp(lhs, rhs) == 0; } #if GTEST_HAS_STD_WSTRING || GTEST_HAS_GLOBAL_WSTRING // Converts an array of wide chars to a narrow string using the UTF-8 // encoding, and streams the result to the given Message object. static void StreamWideCharsToMessage(const wchar_t* wstr, size_t length, Message* msg) { // TODO(wan): consider allowing a testing::String object to // contain '\0'. This will make it behave more like std::string, // and will allow ToUtf8String() to return the correct encoding // for '\0' s.t. we can get rid of the conditional here (and in // several other places). for (size_t i = 0; i != length; ) { // NOLINT if (wstr[i] != L'\0') { *msg << WideStringToUtf8(wstr + i, static_cast(length - i)); while (i != length && wstr[i] != L'\0') i++; } else { *msg << '\0'; i++; } } } #endif // GTEST_HAS_STD_WSTRING || GTEST_HAS_GLOBAL_WSTRING } // namespace internal #if GTEST_HAS_STD_WSTRING // Converts the given wide string to a narrow string using the UTF-8 // encoding, and streams the result to this Message object. Message& Message::operator <<(const ::std::wstring& wstr) { internal::StreamWideCharsToMessage(wstr.c_str(), wstr.length(), this); return *this; } #endif // GTEST_HAS_STD_WSTRING #if GTEST_HAS_GLOBAL_WSTRING // Converts the given wide string to a narrow string using the UTF-8 // encoding, and streams the result to this Message object. Message& Message::operator <<(const ::wstring& wstr) { internal::StreamWideCharsToMessage(wstr.c_str(), wstr.length(), this); return *this; } #endif // GTEST_HAS_GLOBAL_WSTRING // AssertionResult constructors. // Used in EXPECT_TRUE/FALSE(assertion_result). AssertionResult::AssertionResult(const AssertionResult& other) : success_(other.success_), message_(other.message_.get() != NULL ? new ::std::string(*other.message_) : static_cast< ::std::string*>(NULL)) { } // Returns the assertion's negation. Used with EXPECT/ASSERT_FALSE. AssertionResult AssertionResult::operator!() const { AssertionResult negation(!success_); if (message_.get() != NULL) negation << *message_; return negation; } // Makes a successful assertion result. AssertionResult AssertionSuccess() { return AssertionResult(true); } // Makes a failed assertion result. AssertionResult AssertionFailure() { return AssertionResult(false); } // Makes a failed assertion result with the given failure message. // Deprecated; use AssertionFailure() << message. AssertionResult AssertionFailure(const Message& message) { return AssertionFailure() << message; } namespace internal { // Constructs and returns the message for an equality assertion // (e.g. ASSERT_EQ, EXPECT_STREQ, etc) failure. // // The first four parameters are the expressions used in the assertion // and their values, as strings. For example, for ASSERT_EQ(foo, bar) // where foo is 5 and bar is 6, we have: // // expected_expression: "foo" // actual_expression: "bar" // expected_value: "5" // actual_value: "6" // // The ignoring_case parameter is true iff the assertion is a // *_STRCASEEQ*. When it's true, the string " (ignoring case)" will // be inserted into the message. AssertionResult EqFailure(const char* expected_expression, const char* actual_expression, const String& expected_value, const String& actual_value, bool ignoring_case) { Message msg; msg << "Value of: " << actual_expression; if (actual_value != actual_expression) { msg << "\n Actual: " << actual_value; } msg << "\nExpected: " << expected_expression; if (ignoring_case) { msg << " (ignoring case)"; } if (expected_value != expected_expression) { msg << "\nWhich is: " << expected_value; } return AssertionFailure() << msg; } // Constructs a failure message for Boolean assertions such as EXPECT_TRUE. String GetBoolAssertionFailureMessage(const AssertionResult& assertion_result, const char* expression_text, const char* actual_predicate_value, const char* expected_predicate_value) { const char* actual_message = assertion_result.message(); Message msg; msg << "Value of: " << expression_text << "\n Actual: " << actual_predicate_value; if (actual_message[0] != '\0') msg << " (" << actual_message << ")"; msg << "\nExpected: " << expected_predicate_value; return msg.GetString(); } // Helper function for implementing ASSERT_NEAR. AssertionResult DoubleNearPredFormat(const char* expr1, const char* expr2, const char* abs_error_expr, double val1, double val2, double abs_error) { const double diff = fabs(val1 - val2); if (diff <= abs_error) return AssertionSuccess(); // TODO(wan): do not print the value of an expression if it's // already a literal. return AssertionFailure() << "The difference between " << expr1 << " and " << expr2 << " is " << diff << ", which exceeds " << abs_error_expr << ", where\n" << expr1 << " evaluates to " << val1 << ",\n" << expr2 << " evaluates to " << val2 << ", and\n" << abs_error_expr << " evaluates to " << abs_error << "."; } // Helper template for implementing FloatLE() and DoubleLE(). template AssertionResult FloatingPointLE(const char* expr1, const char* expr2, RawType val1, RawType val2) { // Returns success if val1 is less than val2, if (val1 < val2) { return AssertionSuccess(); } // or if val1 is almost equal to val2. const FloatingPoint lhs(val1), rhs(val2); if (lhs.AlmostEquals(rhs)) { return AssertionSuccess(); } // Note that the above two checks will both fail if either val1 or // val2 is NaN, as the IEEE floating-point standard requires that // any predicate involving a NaN must return false. ::std::stringstream val1_ss; val1_ss << std::setprecision(std::numeric_limits::digits10 + 2) << val1; ::std::stringstream val2_ss; val2_ss << std::setprecision(std::numeric_limits::digits10 + 2) << val2; return AssertionFailure() << "Expected: (" << expr1 << ") <= (" << expr2 << ")\n" << " Actual: " << StringStreamToString(&val1_ss) << " vs " << StringStreamToString(&val2_ss); } } // namespace internal // Asserts that val1 is less than, or almost equal to, val2. Fails // otherwise. In particular, it fails if either val1 or val2 is NaN. AssertionResult FloatLE(const char* expr1, const char* expr2, float val1, float val2) { return internal::FloatingPointLE(expr1, expr2, val1, val2); } // Asserts that val1 is less than, or almost equal to, val2. Fails // otherwise. In particular, it fails if either val1 or val2 is NaN. AssertionResult DoubleLE(const char* expr1, const char* expr2, double val1, double val2) { return internal::FloatingPointLE(expr1, expr2, val1, val2); } namespace internal { // The helper function for {ASSERT|EXPECT}_EQ with int or enum // arguments. AssertionResult CmpHelperEQ(const char* expected_expression, const char* actual_expression, BiggestInt expected, BiggestInt actual) { if (expected == actual) { return AssertionSuccess(); } return EqFailure(expected_expression, actual_expression, FormatForComparisonFailureMessage(expected, actual), FormatForComparisonFailureMessage(actual, expected), false); } // A macro for implementing the helper functions needed to implement // ASSERT_?? and EXPECT_?? with integer or enum arguments. It is here // just to avoid copy-and-paste of similar code. #define GTEST_IMPL_CMP_HELPER_(op_name, op)\ AssertionResult CmpHelper##op_name(const char* expr1, const char* expr2, \ BiggestInt val1, BiggestInt val2) {\ if (val1 op val2) {\ return AssertionSuccess();\ } else {\ return AssertionFailure() \ << "Expected: (" << expr1 << ") " #op " (" << expr2\ << "), actual: " << FormatForComparisonFailureMessage(val1, val2)\ << " vs " << FormatForComparisonFailureMessage(val2, val1);\ }\ } // Implements the helper function for {ASSERT|EXPECT}_NE with int or // enum arguments. GTEST_IMPL_CMP_HELPER_(NE, !=) // Implements the helper function for {ASSERT|EXPECT}_LE with int or // enum arguments. GTEST_IMPL_CMP_HELPER_(LE, <=) // Implements the helper function for {ASSERT|EXPECT}_LT with int or // enum arguments. GTEST_IMPL_CMP_HELPER_(LT, < ) // Implements the helper function for {ASSERT|EXPECT}_GE with int or // enum arguments. GTEST_IMPL_CMP_HELPER_(GE, >=) // Implements the helper function for {ASSERT|EXPECT}_GT with int or // enum arguments. GTEST_IMPL_CMP_HELPER_(GT, > ) #undef GTEST_IMPL_CMP_HELPER_ // The helper function for {ASSERT|EXPECT}_STREQ. AssertionResult CmpHelperSTREQ(const char* expected_expression, const char* actual_expression, const char* expected, const char* actual) { if (String::CStringEquals(expected, actual)) { return AssertionSuccess(); } return EqFailure(expected_expression, actual_expression, String::ShowCStringQuoted(expected), String::ShowCStringQuoted(actual), false); } // The helper function for {ASSERT|EXPECT}_STRCASEEQ. AssertionResult CmpHelperSTRCASEEQ(const char* expected_expression, const char* actual_expression, const char* expected, const char* actual) { if (String::CaseInsensitiveCStringEquals(expected, actual)) { return AssertionSuccess(); } return EqFailure(expected_expression, actual_expression, String::ShowCStringQuoted(expected), String::ShowCStringQuoted(actual), true); } // The helper function for {ASSERT|EXPECT}_STRNE. AssertionResult CmpHelperSTRNE(const char* s1_expression, const char* s2_expression, const char* s1, const char* s2) { if (!String::CStringEquals(s1, s2)) { return AssertionSuccess(); } else { return AssertionFailure() << "Expected: (" << s1_expression << ") != (" << s2_expression << "), actual: \"" << s1 << "\" vs \"" << s2 << "\""; } } // The helper function for {ASSERT|EXPECT}_STRCASENE. AssertionResult CmpHelperSTRCASENE(const char* s1_expression, const char* s2_expression, const char* s1, const char* s2) { if (!String::CaseInsensitiveCStringEquals(s1, s2)) { return AssertionSuccess(); } else { return AssertionFailure() << "Expected: (" << s1_expression << ") != (" << s2_expression << ") (ignoring case), actual: \"" << s1 << "\" vs \"" << s2 << "\""; } } } // namespace internal namespace { // Helper functions for implementing IsSubString() and IsNotSubstring(). // This group of overloaded functions return true iff needle is a // substring of haystack. NULL is considered a substring of itself // only. bool IsSubstringPred(const char* needle, const char* haystack) { if (needle == NULL || haystack == NULL) return needle == haystack; return strstr(haystack, needle) != NULL; } bool IsSubstringPred(const wchar_t* needle, const wchar_t* haystack) { if (needle == NULL || haystack == NULL) return needle == haystack; return wcsstr(haystack, needle) != NULL; } // StringType here can be either ::std::string or ::std::wstring. template bool IsSubstringPred(const StringType& needle, const StringType& haystack) { return haystack.find(needle) != StringType::npos; } // This function implements either IsSubstring() or IsNotSubstring(), // depending on the value of the expected_to_be_substring parameter. // StringType here can be const char*, const wchar_t*, ::std::string, // or ::std::wstring. template AssertionResult IsSubstringImpl( bool expected_to_be_substring, const char* needle_expr, const char* haystack_expr, const StringType& needle, const StringType& haystack) { if (IsSubstringPred(needle, haystack) == expected_to_be_substring) return AssertionSuccess(); const bool is_wide_string = sizeof(needle[0]) > 1; const char* const begin_string_quote = is_wide_string ? "L\"" : "\""; return AssertionFailure() << "Value of: " << needle_expr << "\n" << " Actual: " << begin_string_quote << needle << "\"\n" << "Expected: " << (expected_to_be_substring ? "" : "not ") << "a substring of " << haystack_expr << "\n" << "Which is: " << begin_string_quote << haystack << "\""; } } // namespace // IsSubstring() and IsNotSubstring() check whether needle is a // substring of haystack (NULL is considered a substring of itself // only), and return an appropriate error message when they fail. AssertionResult IsSubstring( const char* needle_expr, const char* haystack_expr, const char* needle, const char* haystack) { return IsSubstringImpl(true, needle_expr, haystack_expr, needle, haystack); } AssertionResult IsSubstring( const char* needle_expr, const char* haystack_expr, const wchar_t* needle, const wchar_t* haystack) { return IsSubstringImpl(true, needle_expr, haystack_expr, needle, haystack); } AssertionResult IsNotSubstring( const char* needle_expr, const char* haystack_expr, const char* needle, const char* haystack) { return IsSubstringImpl(false, needle_expr, haystack_expr, needle, haystack); } AssertionResult IsNotSubstring( const char* needle_expr, const char* haystack_expr, const wchar_t* needle, const wchar_t* haystack) { return IsSubstringImpl(false, needle_expr, haystack_expr, needle, haystack); } AssertionResult IsSubstring( const char* needle_expr, const char* haystack_expr, const ::std::string& needle, const ::std::string& haystack) { return IsSubstringImpl(true, needle_expr, haystack_expr, needle, haystack); } AssertionResult IsNotSubstring( const char* needle_expr, const char* haystack_expr, const ::std::string& needle, const ::std::string& haystack) { return IsSubstringImpl(false, needle_expr, haystack_expr, needle, haystack); } #if GTEST_HAS_STD_WSTRING AssertionResult IsSubstring( const char* needle_expr, const char* haystack_expr, const ::std::wstring& needle, const ::std::wstring& haystack) { return IsSubstringImpl(true, needle_expr, haystack_expr, needle, haystack); } AssertionResult IsNotSubstring( const char* needle_expr, const char* haystack_expr, const ::std::wstring& needle, const ::std::wstring& haystack) { return IsSubstringImpl(false, needle_expr, haystack_expr, needle, haystack); } #endif // GTEST_HAS_STD_WSTRING namespace internal { #if GTEST_OS_WINDOWS namespace { // Helper function for IsHRESULT{SuccessFailure} predicates AssertionResult HRESULTFailureHelper(const char* expr, const char* expected, long hr) { // NOLINT # if GTEST_OS_WINDOWS_MOBILE // Windows CE doesn't support FormatMessage. const char error_text[] = ""; # else // Looks up the human-readable system message for the HRESULT code // and since we're not passing any params to FormatMessage, we don't // want inserts expanded. const DWORD kFlags = FORMAT_MESSAGE_FROM_SYSTEM | FORMAT_MESSAGE_IGNORE_INSERTS; const DWORD kBufSize = 4096; // String::Format can't exceed this length. // Gets the system's human readable message string for this HRESULT. char error_text[kBufSize] = { '\0' }; DWORD message_length = ::FormatMessageA(kFlags, 0, // no source, we're asking system hr, // the error 0, // no line width restrictions error_text, // output buffer kBufSize, // buf size NULL); // no arguments for inserts // Trims tailing white space (FormatMessage leaves a trailing cr-lf) for (; message_length && IsSpace(error_text[message_length - 1]); --message_length) { error_text[message_length - 1] = '\0'; } # endif // GTEST_OS_WINDOWS_MOBILE const String error_hex(String::Format("0x%08X ", hr)); return ::testing::AssertionFailure() << "Expected: " << expr << " " << expected << ".\n" << " Actual: " << error_hex << error_text << "\n"; } } // namespace AssertionResult IsHRESULTSuccess(const char* expr, long hr) { // NOLINT if (SUCCEEDED(hr)) { return AssertionSuccess(); } return HRESULTFailureHelper(expr, "succeeds", hr); } AssertionResult IsHRESULTFailure(const char* expr, long hr) { // NOLINT if (FAILED(hr)) { return AssertionSuccess(); } return HRESULTFailureHelper(expr, "fails", hr); } #endif // GTEST_OS_WINDOWS // Utility functions for encoding Unicode text (wide strings) in // UTF-8. // A Unicode code-point can have upto 21 bits, and is encoded in UTF-8 // like this: // // Code-point length Encoding // 0 - 7 bits 0xxxxxxx // 8 - 11 bits 110xxxxx 10xxxxxx // 12 - 16 bits 1110xxxx 10xxxxxx 10xxxxxx // 17 - 21 bits 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx // The maximum code-point a one-byte UTF-8 sequence can represent. const UInt32 kMaxCodePoint1 = (static_cast(1) << 7) - 1; // The maximum code-point a two-byte UTF-8 sequence can represent. const UInt32 kMaxCodePoint2 = (static_cast(1) << (5 + 6)) - 1; // The maximum code-point a three-byte UTF-8 sequence can represent. const UInt32 kMaxCodePoint3 = (static_cast(1) << (4 + 2*6)) - 1; // The maximum code-point a four-byte UTF-8 sequence can represent. const UInt32 kMaxCodePoint4 = (static_cast(1) << (3 + 3*6)) - 1; // Chops off the n lowest bits from a bit pattern. Returns the n // lowest bits. As a side effect, the original bit pattern will be // shifted to the right by n bits. inline UInt32 ChopLowBits(UInt32* bits, int n) { const UInt32 low_bits = *bits & ((static_cast(1) << n) - 1); *bits >>= n; return low_bits; } // Converts a Unicode code point to a narrow string in UTF-8 encoding. // code_point parameter is of type UInt32 because wchar_t may not be // wide enough to contain a code point. // The output buffer str must containt at least 32 characters. // The function returns the address of the output buffer. // If the code_point is not a valid Unicode code point // (i.e. outside of Unicode range U+0 to U+10FFFF) it will be output // as '(Invalid Unicode 0xXXXXXXXX)'. char* CodePointToUtf8(UInt32 code_point, char* str) { if (code_point <= kMaxCodePoint1) { str[1] = '\0'; str[0] = static_cast(code_point); // 0xxxxxxx } else if (code_point <= kMaxCodePoint2) { str[2] = '\0'; str[1] = static_cast(0x80 | ChopLowBits(&code_point, 6)); // 10xxxxxx str[0] = static_cast(0xC0 | code_point); // 110xxxxx } else if (code_point <= kMaxCodePoint3) { str[3] = '\0'; str[2] = static_cast(0x80 | ChopLowBits(&code_point, 6)); // 10xxxxxx str[1] = static_cast(0x80 | ChopLowBits(&code_point, 6)); // 10xxxxxx str[0] = static_cast(0xE0 | code_point); // 1110xxxx } else if (code_point <= kMaxCodePoint4) { str[4] = '\0'; str[3] = static_cast(0x80 | ChopLowBits(&code_point, 6)); // 10xxxxxx str[2] = static_cast(0x80 | ChopLowBits(&code_point, 6)); // 10xxxxxx str[1] = static_cast(0x80 | ChopLowBits(&code_point, 6)); // 10xxxxxx str[0] = static_cast(0xF0 | code_point); // 11110xxx } else { // The longest string String::Format can produce when invoked // with these parameters is 28 character long (not including // the terminating nul character). We are asking for 32 character // buffer just in case. This is also enough for strncpy to // null-terminate the destination string. posix::StrNCpy( str, String::Format("(Invalid Unicode 0x%X)", code_point).c_str(), 32); str[31] = '\0'; // Makes sure no change in the format to strncpy leaves // the result unterminated. } return str; } // The following two functions only make sense if the the system // uses UTF-16 for wide string encoding. All supported systems // with 16 bit wchar_t (Windows, Cygwin, Symbian OS) do use UTF-16. // Determines if the arguments constitute UTF-16 surrogate pair // and thus should be combined into a single Unicode code point // using CreateCodePointFromUtf16SurrogatePair. inline bool IsUtf16SurrogatePair(wchar_t first, wchar_t second) { return sizeof(wchar_t) == 2 && (first & 0xFC00) == 0xD800 && (second & 0xFC00) == 0xDC00; } // Creates a Unicode code point from UTF16 surrogate pair. inline UInt32 CreateCodePointFromUtf16SurrogatePair(wchar_t first, wchar_t second) { const UInt32 mask = (1 << 10) - 1; return (sizeof(wchar_t) == 2) ? (((first & mask) << 10) | (second & mask)) + 0x10000 : // This function should not be called when the condition is // false, but we provide a sensible default in case it is. static_cast(first); } // Converts a wide string to a narrow string in UTF-8 encoding. // The wide string is assumed to have the following encoding: // UTF-16 if sizeof(wchar_t) == 2 (on Windows, Cygwin, Symbian OS) // UTF-32 if sizeof(wchar_t) == 4 (on Linux) // Parameter str points to a null-terminated wide string. // Parameter num_chars may additionally limit the number // of wchar_t characters processed. -1 is used when the entire string // should be processed. // If the string contains code points that are not valid Unicode code points // (i.e. outside of Unicode range U+0 to U+10FFFF) they will be output // as '(Invalid Unicode 0xXXXXXXXX)'. If the string is in UTF16 encoding // and contains invalid UTF-16 surrogate pairs, values in those pairs // will be encoded as individual Unicode characters from Basic Normal Plane. String WideStringToUtf8(const wchar_t* str, int num_chars) { if (num_chars == -1) num_chars = static_cast(wcslen(str)); ::std::stringstream stream; for (int i = 0; i < num_chars; ++i) { UInt32 unicode_code_point; if (str[i] == L'\0') { break; } else if (i + 1 < num_chars && IsUtf16SurrogatePair(str[i], str[i + 1])) { unicode_code_point = CreateCodePointFromUtf16SurrogatePair(str[i], str[i + 1]); i++; } else { unicode_code_point = static_cast(str[i]); } char buffer[32]; // CodePointToUtf8 requires a buffer this big. stream << CodePointToUtf8(unicode_code_point, buffer); } return StringStreamToString(&stream); } // Converts a wide C string to a String using the UTF-8 encoding. // NULL will be converted to "(null)". String String::ShowWideCString(const wchar_t * wide_c_str) { if (wide_c_str == NULL) return String("(null)"); return String(internal::WideStringToUtf8(wide_c_str, -1).c_str()); } // Similar to ShowWideCString(), except that this function encloses // the converted string in double quotes. String String::ShowWideCStringQuoted(const wchar_t* wide_c_str) { if (wide_c_str == NULL) return String("(null)"); return String::Format("L\"%s\"", String::ShowWideCString(wide_c_str).c_str()); } // Compares two wide C strings. Returns true iff they have the same // content. // // Unlike wcscmp(), this function can handle NULL argument(s). A NULL // C string is considered different to any non-NULL C string, // including the empty string. bool String::WideCStringEquals(const wchar_t * lhs, const wchar_t * rhs) { if (lhs == NULL) return rhs == NULL; if (rhs == NULL) return false; return wcscmp(lhs, rhs) == 0; } // Helper function for *_STREQ on wide strings. AssertionResult CmpHelperSTREQ(const char* expected_expression, const char* actual_expression, const wchar_t* expected, const wchar_t* actual) { if (String::WideCStringEquals(expected, actual)) { return AssertionSuccess(); } return EqFailure(expected_expression, actual_expression, String::ShowWideCStringQuoted(expected), String::ShowWideCStringQuoted(actual), false); } // Helper function for *_STRNE on wide strings. AssertionResult CmpHelperSTRNE(const char* s1_expression, const char* s2_expression, const wchar_t* s1, const wchar_t* s2) { if (!String::WideCStringEquals(s1, s2)) { return AssertionSuccess(); } return AssertionFailure() << "Expected: (" << s1_expression << ") != (" << s2_expression << "), actual: " << String::ShowWideCStringQuoted(s1) << " vs " << String::ShowWideCStringQuoted(s2); } // Compares two C strings, ignoring case. Returns true iff they have // the same content. // // Unlike strcasecmp(), this function can handle NULL argument(s). A // NULL C string is considered different to any non-NULL C string, // including the empty string. bool String::CaseInsensitiveCStringEquals(const char * lhs, const char * rhs) { if (lhs == NULL) return rhs == NULL; if (rhs == NULL) return false; return posix::StrCaseCmp(lhs, rhs) == 0; } // Compares two wide C strings, ignoring case. Returns true iff they // have the same content. // // Unlike wcscasecmp(), this function can handle NULL argument(s). // A NULL C string is considered different to any non-NULL wide C string, // including the empty string. // NB: The implementations on different platforms slightly differ. // On windows, this method uses _wcsicmp which compares according to LC_CTYPE // environment variable. On GNU platform this method uses wcscasecmp // which compares according to LC_CTYPE category of the current locale. // On MacOS X, it uses towlower, which also uses LC_CTYPE category of the // current locale. bool String::CaseInsensitiveWideCStringEquals(const wchar_t* lhs, const wchar_t* rhs) { if (lhs == NULL) return rhs == NULL; if (rhs == NULL) return false; #if GTEST_OS_WINDOWS return _wcsicmp(lhs, rhs) == 0; #elif GTEST_OS_LINUX && !GTEST_OS_LINUX_ANDROID return wcscasecmp(lhs, rhs) == 0; #else // Android, Mac OS X and Cygwin don't define wcscasecmp. // Other unknown OSes may not define it either. wint_t left, right; do { left = towlower(*lhs++); right = towlower(*rhs++); } while (left && left == right); return left == right; #endif // OS selector } // Compares this with another String. // Returns < 0 if this is less than rhs, 0 if this is equal to rhs, or > 0 // if this is greater than rhs. int String::Compare(const String & rhs) const { const char* const lhs_c_str = c_str(); const char* const rhs_c_str = rhs.c_str(); if (lhs_c_str == NULL) { return rhs_c_str == NULL ? 0 : -1; // NULL < anything except NULL } else if (rhs_c_str == NULL) { return 1; } const size_t shorter_str_len = length() <= rhs.length() ? length() : rhs.length(); for (size_t i = 0; i != shorter_str_len; i++) { if (lhs_c_str[i] < rhs_c_str[i]) { return -1; } else if (lhs_c_str[i] > rhs_c_str[i]) { return 1; } } return (length() < rhs.length()) ? -1 : (length() > rhs.length()) ? 1 : 0; } // Returns true iff this String ends with the given suffix. *Any* // String is considered to end with a NULL or empty suffix. bool String::EndsWith(const char* suffix) const { if (suffix == NULL || CStringEquals(suffix, "")) return true; if (c_str() == NULL) return false; const size_t this_len = strlen(c_str()); const size_t suffix_len = strlen(suffix); return (this_len >= suffix_len) && CStringEquals(c_str() + this_len - suffix_len, suffix); } // Returns true iff this String ends with the given suffix, ignoring case. // Any String is considered to end with a NULL or empty suffix. bool String::EndsWithCaseInsensitive(const char* suffix) const { if (suffix == NULL || CStringEquals(suffix, "")) return true; if (c_str() == NULL) return false; const size_t this_len = strlen(c_str()); const size_t suffix_len = strlen(suffix); return (this_len >= suffix_len) && CaseInsensitiveCStringEquals(c_str() + this_len - suffix_len, suffix); } // Formats a list of arguments to a String, using the same format // spec string as for printf. // // We do not use the StringPrintf class as it is not universally // available. // // The result is limited to 4096 characters (including the tailing 0). // If 4096 characters are not enough to format the input, or if // there's an error, "" is // returned. String String::Format(const char * format, ...) { va_list args; va_start(args, format); char buffer[4096]; const int kBufferSize = sizeof(buffer)/sizeof(buffer[0]); // MSVC 8 deprecates vsnprintf(), so we want to suppress warning // 4996 (deprecated function) there. #ifdef _MSC_VER // We are using MSVC. # pragma warning(push) // Saves the current warning state. # pragma warning(disable:4996) // Temporarily disables warning 4996. const int size = vsnprintf(buffer, kBufferSize, format, args); # pragma warning(pop) // Restores the warning state. #else // We are not using MSVC. const int size = vsnprintf(buffer, kBufferSize, format, args); #endif // _MSC_VER va_end(args); // vsnprintf()'s behavior is not portable. When the buffer is not // big enough, it returns a negative value in MSVC, and returns the // needed buffer size on Linux. When there is an output error, it // always returns a negative value. For simplicity, we lump the two // error cases together. if (size < 0 || size >= kBufferSize) { return String(""); } else { return String(buffer, size); } } // Converts the buffer in a stringstream to a String, converting NUL // bytes to "\\0" along the way. String StringStreamToString(::std::stringstream* ss) { const ::std::string& str = ss->str(); const char* const start = str.c_str(); const char* const end = start + str.length(); // We need to use a helper stringstream to do this transformation // because String doesn't support push_back(). ::std::stringstream helper; for (const char* ch = start; ch != end; ++ch) { if (*ch == '\0') { helper << "\\0"; // Replaces NUL with "\\0"; } else { helper.put(*ch); } } return String(helper.str().c_str()); } // Appends the user-supplied message to the Google-Test-generated message. String AppendUserMessage(const String& gtest_msg, const Message& user_msg) { // Appends the user message if it's non-empty. const String user_msg_string = user_msg.GetString(); if (user_msg_string.empty()) { return gtest_msg; } Message msg; msg << gtest_msg << "\n" << user_msg_string; return msg.GetString(); } } // namespace internal // class TestResult // Creates an empty TestResult. TestResult::TestResult() : death_test_count_(0), elapsed_time_(0) { } // D'tor. TestResult::~TestResult() { } // Returns the i-th test part result among all the results. i can // range from 0 to total_part_count() - 1. If i is not in that range, // aborts the program. const TestPartResult& TestResult::GetTestPartResult(int i) const { if (i < 0 || i >= total_part_count()) internal::posix::Abort(); return test_part_results_.at(i); } // Returns the i-th test property. i can range from 0 to // test_property_count() - 1. If i is not in that range, aborts the // program. const TestProperty& TestResult::GetTestProperty(int i) const { if (i < 0 || i >= test_property_count()) internal::posix::Abort(); return test_properties_.at(i); } // Clears the test part results. void TestResult::ClearTestPartResults() { test_part_results_.clear(); } // Adds a test part result to the list. void TestResult::AddTestPartResult(const TestPartResult& test_part_result) { test_part_results_.push_back(test_part_result); } // Adds a test property to the list. If a property with the same key as the // supplied property is already represented, the value of this test_property // replaces the old value for that key. void TestResult::RecordProperty(const TestProperty& test_property) { if (!ValidateTestProperty(test_property)) { return; } internal::MutexLock lock(&test_properites_mutex_); const std::vector::iterator property_with_matching_key = std::find_if(test_properties_.begin(), test_properties_.end(), internal::TestPropertyKeyIs(test_property.key())); if (property_with_matching_key == test_properties_.end()) { test_properties_.push_back(test_property); return; } property_with_matching_key->SetValue(test_property.value()); } // Adds a failure if the key is a reserved attribute of Google Test // testcase tags. Returns true if the property is valid. bool TestResult::ValidateTestProperty(const TestProperty& test_property) { internal::String key(test_property.key()); if (key == "name" || key == "status" || key == "time" || key == "classname") { ADD_FAILURE() << "Reserved key used in RecordProperty(): " << key << " ('name', 'status', 'time', and 'classname' are reserved by " << GTEST_NAME_ << ")"; return false; } return true; } // Clears the object. void TestResult::Clear() { test_part_results_.clear(); test_properties_.clear(); death_test_count_ = 0; elapsed_time_ = 0; } // Returns true iff the test failed. bool TestResult::Failed() const { for (int i = 0; i < total_part_count(); ++i) { if (GetTestPartResult(i).failed()) return true; } return false; } // Returns true iff the test part fatally failed. static bool TestPartFatallyFailed(const TestPartResult& result) { return result.fatally_failed(); } // Returns true iff the test fatally failed. bool TestResult::HasFatalFailure() const { return CountIf(test_part_results_, TestPartFatallyFailed) > 0; } // Returns true iff the test part non-fatally failed. static bool TestPartNonfatallyFailed(const TestPartResult& result) { return result.nonfatally_failed(); } // Returns true iff the test has a non-fatal failure. bool TestResult::HasNonfatalFailure() const { return CountIf(test_part_results_, TestPartNonfatallyFailed) > 0; } // Gets the number of all test parts. This is the sum of the number // of successful test parts and the number of failed test parts. int TestResult::total_part_count() const { return static_cast(test_part_results_.size()); } // Returns the number of the test properties. int TestResult::test_property_count() const { return static_cast(test_properties_.size()); } // class Test // Creates a Test object. // The c'tor saves the values of all Google Test flags. Test::Test() : gtest_flag_saver_(new internal::GTestFlagSaver) { } // The d'tor restores the values of all Google Test flags. Test::~Test() { delete gtest_flag_saver_; } // Sets up the test fixture. // // A sub-class may override this. void Test::SetUp() { } // Tears down the test fixture. // // A sub-class may override this. void Test::TearDown() { } // Allows user supplied key value pairs to be recorded for later output. void Test::RecordProperty(const char* key, const char* value) { UnitTest::GetInstance()->RecordPropertyForCurrentTest(key, value); } // Allows user supplied key value pairs to be recorded for later output. void Test::RecordProperty(const char* key, int value) { Message value_message; value_message << value; RecordProperty(key, value_message.GetString().c_str()); } namespace internal { void ReportFailureInUnknownLocation(TestPartResult::Type result_type, const String& message) { // This function is a friend of UnitTest and as such has access to // AddTestPartResult. UnitTest::GetInstance()->AddTestPartResult( result_type, NULL, // No info about the source file where the exception occurred. -1, // We have no info on which line caused the exception. message, String()); // No stack trace, either. } } // namespace internal // Google Test requires all tests in the same test case to use the same test // fixture class. This function checks if the current test has the // same fixture class as the first test in the current test case. If // yes, it returns true; otherwise it generates a Google Test failure and // returns false. bool Test::HasSameFixtureClass() { internal::UnitTestImpl* const impl = internal::GetUnitTestImpl(); const TestCase* const test_case = impl->current_test_case(); // Info about the first test in the current test case. const TestInfo* const first_test_info = test_case->test_info_list()[0]; const internal::TypeId first_fixture_id = first_test_info->fixture_class_id_; const char* const first_test_name = first_test_info->name(); // Info about the current test. const TestInfo* const this_test_info = impl->current_test_info(); const internal::TypeId this_fixture_id = this_test_info->fixture_class_id_; const char* const this_test_name = this_test_info->name(); if (this_fixture_id != first_fixture_id) { // Is the first test defined using TEST? const bool first_is_TEST = first_fixture_id == internal::GetTestTypeId(); // Is this test defined using TEST? const bool this_is_TEST = this_fixture_id == internal::GetTestTypeId(); if (first_is_TEST || this_is_TEST) { // The user mixed TEST and TEST_F in this test case - we'll tell // him/her how to fix it. // Gets the name of the TEST and the name of the TEST_F. Note // that first_is_TEST and this_is_TEST cannot both be true, as // the fixture IDs are different for the two tests. const char* const TEST_name = first_is_TEST ? first_test_name : this_test_name; const char* const TEST_F_name = first_is_TEST ? this_test_name : first_test_name; ADD_FAILURE() << "All tests in the same test case must use the same test fixture\n" << "class, so mixing TEST_F and TEST in the same test case is\n" << "illegal. In test case " << this_test_info->test_case_name() << ",\n" << "test " << TEST_F_name << " is defined using TEST_F but\n" << "test " << TEST_name << " is defined using TEST. You probably\n" << "want to change the TEST to TEST_F or move it to another test\n" << "case."; } else { // The user defined two fixture classes with the same name in // two namespaces - we'll tell him/her how to fix it. ADD_FAILURE() << "All tests in the same test case must use the same test fixture\n" << "class. However, in test case " << this_test_info->test_case_name() << ",\n" << "you defined test " << first_test_name << " and test " << this_test_name << "\n" << "using two different test fixture classes. This can happen if\n" << "the two classes are from different namespaces or translation\n" << "units and have the same name. You should probably rename one\n" << "of the classes to put the tests into different test cases."; } return false; } return true; } #if GTEST_HAS_SEH // Adds an "exception thrown" fatal failure to the current test. This // function returns its result via an output parameter pointer because VC++ // prohibits creation of objects with destructors on stack in functions // using __try (see error C2712). static internal::String* FormatSehExceptionMessage(DWORD exception_code, const char* location) { Message message; message << "SEH exception with code 0x" << std::setbase(16) << exception_code << std::setbase(10) << " thrown in " << location << "."; return new internal::String(message.GetString()); } #endif // GTEST_HAS_SEH #if GTEST_HAS_EXCEPTIONS // Adds an "exception thrown" fatal failure to the current test. static internal::String FormatCxxExceptionMessage(const char* description, const char* location) { Message message; if (description != NULL) { message << "C++ exception with description \"" << description << "\""; } else { message << "Unknown C++ exception"; } message << " thrown in " << location << "."; return message.GetString(); } static internal::String PrintTestPartResultToString( const TestPartResult& test_part_result); // A failed Google Test assertion will throw an exception of this type when // GTEST_FLAG(throw_on_failure) is true (if exceptions are enabled). We // derive it from std::runtime_error, which is for errors presumably // detectable only at run time. Since std::runtime_error inherits from // std::exception, many testing frameworks know how to extract and print the // message inside it. class GoogleTestFailureException : public ::std::runtime_error { public: explicit GoogleTestFailureException(const TestPartResult& failure) : ::std::runtime_error(PrintTestPartResultToString(failure).c_str()) {} }; #endif // GTEST_HAS_EXCEPTIONS namespace internal { // We put these helper functions in the internal namespace as IBM's xlC // compiler rejects the code if they were declared static. // Runs the given method and handles SEH exceptions it throws, when // SEH is supported; returns the 0-value for type Result in case of an // SEH exception. (Microsoft compilers cannot handle SEH and C++ // exceptions in the same function. Therefore, we provide a separate // wrapper function for handling SEH exceptions.) template Result HandleSehExceptionsInMethodIfSupported( T* object, Result (T::*method)(), const char* location) { #if GTEST_HAS_SEH __try { return (object->*method)(); } __except (internal::UnitTestOptions::GTestShouldProcessSEH( // NOLINT GetExceptionCode())) { // We create the exception message on the heap because VC++ prohibits // creation of objects with destructors on stack in functions using __try // (see error C2712). internal::String* exception_message = FormatSehExceptionMessage( GetExceptionCode(), location); internal::ReportFailureInUnknownLocation(TestPartResult::kFatalFailure, *exception_message); delete exception_message; return static_cast(0); } #else (void)location; return (object->*method)(); #endif // GTEST_HAS_SEH } // Runs the given method and catches and reports C++ and/or SEH-style // exceptions, if they are supported; returns the 0-value for type // Result in case of an SEH exception. template Result HandleExceptionsInMethodIfSupported( T* object, Result (T::*method)(), const char* location) { // NOTE: The user code can affect the way in which Google Test handles // exceptions by setting GTEST_FLAG(catch_exceptions), but only before // RUN_ALL_TESTS() starts. It is technically possible to check the flag // after the exception is caught and either report or re-throw the // exception based on the flag's value: // // try { // // Perform the test method. // } catch (...) { // if (GTEST_FLAG(catch_exceptions)) // // Report the exception as failure. // else // throw; // Re-throws the original exception. // } // // However, the purpose of this flag is to allow the program to drop into // the debugger when the exception is thrown. On most platforms, once the // control enters the catch block, the exception origin information is // lost and the debugger will stop the program at the point of the // re-throw in this function -- instead of at the point of the original // throw statement in the code under test. For this reason, we perform // the check early, sacrificing the ability to affect Google Test's // exception handling in the method where the exception is thrown. if (internal::GetUnitTestImpl()->catch_exceptions()) { #if GTEST_HAS_EXCEPTIONS try { return HandleSehExceptionsInMethodIfSupported(object, method, location); } catch (const GoogleTestFailureException&) { // NOLINT // This exception doesn't originate in code under test. It makes no // sense to report it as a test failure. throw; } catch (const std::exception& e) { // NOLINT internal::ReportFailureInUnknownLocation( TestPartResult::kFatalFailure, FormatCxxExceptionMessage(e.what(), location)); } catch (...) { // NOLINT internal::ReportFailureInUnknownLocation( TestPartResult::kFatalFailure, FormatCxxExceptionMessage(NULL, location)); } return static_cast(0); #else return HandleSehExceptionsInMethodIfSupported(object, method, location); #endif // GTEST_HAS_EXCEPTIONS } else { return (object->*method)(); } } } // namespace internal // Runs the test and updates the test result. void Test::Run() { if (!HasSameFixtureClass()) return; internal::UnitTestImpl* const impl = internal::GetUnitTestImpl(); impl->os_stack_trace_getter()->UponLeavingGTest(); internal::HandleExceptionsInMethodIfSupported(this, &Test::SetUp, "SetUp()"); // We will run the test only if SetUp() was successful. if (!HasFatalFailure()) { impl->os_stack_trace_getter()->UponLeavingGTest(); internal::HandleExceptionsInMethodIfSupported( this, &Test::TestBody, "the test body"); } // However, we want to clean up as much as possible. Hence we will // always call TearDown(), even if SetUp() or the test body has // failed. impl->os_stack_trace_getter()->UponLeavingGTest(); internal::HandleExceptionsInMethodIfSupported( this, &Test::TearDown, "TearDown()"); } // Returns true iff the current test has a fatal failure. bool Test::HasFatalFailure() { return internal::GetUnitTestImpl()->current_test_result()->HasFatalFailure(); } // Returns true iff the current test has a non-fatal failure. bool Test::HasNonfatalFailure() { return internal::GetUnitTestImpl()->current_test_result()-> HasNonfatalFailure(); } // class TestInfo // Constructs a TestInfo object. It assumes ownership of the test factory // object. // TODO(vladl@google.com): Make a_test_case_name and a_name const string&'s // to signify they cannot be NULLs. TestInfo::TestInfo(const char* a_test_case_name, const char* a_name, const char* a_type_param, const char* a_value_param, internal::TypeId fixture_class_id, internal::TestFactoryBase* factory) : test_case_name_(a_test_case_name), name_(a_name), type_param_(a_type_param ? new std::string(a_type_param) : NULL), value_param_(a_value_param ? new std::string(a_value_param) : NULL), fixture_class_id_(fixture_class_id), should_run_(false), is_disabled_(false), matches_filter_(false), factory_(factory), result_() {} // Destructs a TestInfo object. TestInfo::~TestInfo() { delete factory_; } namespace internal { // Creates a new TestInfo object and registers it with Google Test; // returns the created object. // // Arguments: // // test_case_name: name of the test case // name: name of the test // type_param: the name of the test's type parameter, or NULL if // this is not a typed or a type-parameterized test. // value_param: text representation of the test's value parameter, // or NULL if this is not a value-parameterized test. // fixture_class_id: ID of the test fixture class // set_up_tc: pointer to the function that sets up the test case // tear_down_tc: pointer to the function that tears down the test case // factory: pointer to the factory that creates a test object. // The newly created TestInfo instance will assume // ownership of the factory object. TestInfo* MakeAndRegisterTestInfo( const char* test_case_name, const char* name, const char* type_param, const char* value_param, TypeId fixture_class_id, SetUpTestCaseFunc set_up_tc, TearDownTestCaseFunc tear_down_tc, TestFactoryBase* factory) { TestInfo* const test_info = new TestInfo(test_case_name, name, type_param, value_param, fixture_class_id, factory); GetUnitTestImpl()->AddTestInfo(set_up_tc, tear_down_tc, test_info); return test_info; } #if GTEST_HAS_PARAM_TEST void ReportInvalidTestCaseType(const char* test_case_name, const char* file, int line) { Message errors; errors << "Attempted redefinition of test case " << test_case_name << ".\n" << "All tests in the same test case must use the same test fixture\n" << "class. However, in test case " << test_case_name << ", you tried\n" << "to define a test using a fixture class different from the one\n" << "used earlier. This can happen if the two fixture classes are\n" << "from different namespaces and have the same name. You should\n" << "probably rename one of the classes to put the tests into different\n" << "test cases."; fprintf(stderr, "%s %s", FormatFileLocation(file, line).c_str(), errors.GetString().c_str()); } #endif // GTEST_HAS_PARAM_TEST } // namespace internal namespace { // A predicate that checks the test name of a TestInfo against a known // value. // // This is used for implementation of the TestCase class only. We put // it in the anonymous namespace to prevent polluting the outer // namespace. // // TestNameIs is copyable. class TestNameIs { public: // Constructor. // // TestNameIs has NO default constructor. explicit TestNameIs(const char* name) : name_(name) {} // Returns true iff the test name of test_info matches name_. bool operator()(const TestInfo * test_info) const { return test_info && internal::String(test_info->name()).Compare(name_) == 0; } private: internal::String name_; }; } // namespace namespace internal { // This method expands all parameterized tests registered with macros TEST_P // and INSTANTIATE_TEST_CASE_P into regular tests and registers those. // This will be done just once during the program runtime. void UnitTestImpl::RegisterParameterizedTests() { #if GTEST_HAS_PARAM_TEST if (!parameterized_tests_registered_) { parameterized_test_registry_.RegisterTests(); parameterized_tests_registered_ = true; } #endif } } // namespace internal // Creates the test object, runs it, records its result, and then // deletes it. void TestInfo::Run() { if (!should_run_) return; // Tells UnitTest where to store test result. internal::UnitTestImpl* const impl = internal::GetUnitTestImpl(); impl->set_current_test_info(this); TestEventListener* repeater = UnitTest::GetInstance()->listeners().repeater(); // Notifies the unit test event listeners that a test is about to start. repeater->OnTestStart(*this); const TimeInMillis start = internal::GetTimeInMillis(); impl->os_stack_trace_getter()->UponLeavingGTest(); // Creates the test object. Test* const test = internal::HandleExceptionsInMethodIfSupported( factory_, &internal::TestFactoryBase::CreateTest, "the test fixture's constructor"); // Runs the test only if the test object was created and its // constructor didn't generate a fatal failure. if ((test != NULL) && !Test::HasFatalFailure()) { // This doesn't throw as all user code that can throw are wrapped into // exception handling code. test->Run(); } // Deletes the test object. impl->os_stack_trace_getter()->UponLeavingGTest(); internal::HandleExceptionsInMethodIfSupported( test, &Test::DeleteSelf_, "the test fixture's destructor"); result_.set_elapsed_time(internal::GetTimeInMillis() - start); // Notifies the unit test event listener that a test has just finished. repeater->OnTestEnd(*this); // Tells UnitTest to stop associating assertion results to this // test. impl->set_current_test_info(NULL); } // class TestCase // Gets the number of successful tests in this test case. int TestCase::successful_test_count() const { return CountIf(test_info_list_, TestPassed); } // Gets the number of failed tests in this test case. int TestCase::failed_test_count() const { return CountIf(test_info_list_, TestFailed); } int TestCase::disabled_test_count() const { return CountIf(test_info_list_, TestDisabled); } // Get the number of tests in this test case that should run. int TestCase::test_to_run_count() const { return CountIf(test_info_list_, ShouldRunTest); } // Gets the number of all tests. int TestCase::total_test_count() const { return static_cast(test_info_list_.size()); } // Creates a TestCase with the given name. // // Arguments: // // name: name of the test case // a_type_param: the name of the test case's type parameter, or NULL if // this is not a typed or a type-parameterized test case. // set_up_tc: pointer to the function that sets up the test case // tear_down_tc: pointer to the function that tears down the test case TestCase::TestCase(const char* a_name, const char* a_type_param, Test::SetUpTestCaseFunc set_up_tc, Test::TearDownTestCaseFunc tear_down_tc) : name_(a_name), type_param_(a_type_param ? new std::string(a_type_param) : NULL), set_up_tc_(set_up_tc), tear_down_tc_(tear_down_tc), should_run_(false), elapsed_time_(0) { } // Destructor of TestCase. TestCase::~TestCase() { // Deletes every Test in the collection. ForEach(test_info_list_, internal::Delete); } // Returns the i-th test among all the tests. i can range from 0 to // total_test_count() - 1. If i is not in that range, returns NULL. const TestInfo* TestCase::GetTestInfo(int i) const { const int index = GetElementOr(test_indices_, i, -1); return index < 0 ? NULL : test_info_list_[index]; } // Returns the i-th test among all the tests. i can range from 0 to // total_test_count() - 1. If i is not in that range, returns NULL. TestInfo* TestCase::GetMutableTestInfo(int i) { const int index = GetElementOr(test_indices_, i, -1); return index < 0 ? NULL : test_info_list_[index]; } // Adds a test to this test case. Will delete the test upon // destruction of the TestCase object. void TestCase::AddTestInfo(TestInfo * test_info) { test_info_list_.push_back(test_info); test_indices_.push_back(static_cast(test_indices_.size())); } // Runs every test in this TestCase. void TestCase::Run() { if (!should_run_) return; internal::UnitTestImpl* const impl = internal::GetUnitTestImpl(); impl->set_current_test_case(this); TestEventListener* repeater = UnitTest::GetInstance()->listeners().repeater(); repeater->OnTestCaseStart(*this); impl->os_stack_trace_getter()->UponLeavingGTest(); internal::HandleExceptionsInMethodIfSupported( this, &TestCase::RunSetUpTestCase, "SetUpTestCase()"); const internal::TimeInMillis start = internal::GetTimeInMillis(); for (int i = 0; i < total_test_count(); i++) { GetMutableTestInfo(i)->Run(); } elapsed_time_ = internal::GetTimeInMillis() - start; impl->os_stack_trace_getter()->UponLeavingGTest(); internal::HandleExceptionsInMethodIfSupported( this, &TestCase::RunTearDownTestCase, "TearDownTestCase()"); repeater->OnTestCaseEnd(*this); impl->set_current_test_case(NULL); } // Clears the results of all tests in this test case. void TestCase::ClearResult() { ForEach(test_info_list_, TestInfo::ClearTestResult); } // Shuffles the tests in this test case. void TestCase::ShuffleTests(internal::Random* random) { Shuffle(random, &test_indices_); } // Restores the test order to before the first shuffle. void TestCase::UnshuffleTests() { for (size_t i = 0; i < test_indices_.size(); i++) { test_indices_[i] = static_cast(i); } } // Formats a countable noun. Depending on its quantity, either the // singular form or the plural form is used. e.g. // // FormatCountableNoun(1, "formula", "formuli") returns "1 formula". // FormatCountableNoun(5, "book", "books") returns "5 books". static internal::String FormatCountableNoun(int count, const char * singular_form, const char * plural_form) { return internal::String::Format("%d %s", count, count == 1 ? singular_form : plural_form); } // Formats the count of tests. static internal::String FormatTestCount(int test_count) { return FormatCountableNoun(test_count, "test", "tests"); } // Formats the count of test cases. static internal::String FormatTestCaseCount(int test_case_count) { return FormatCountableNoun(test_case_count, "test case", "test cases"); } // Converts a TestPartResult::Type enum to human-friendly string // representation. Both kNonFatalFailure and kFatalFailure are translated // to "Failure", as the user usually doesn't care about the difference // between the two when viewing the test result. static const char * TestPartResultTypeToString(TestPartResult::Type type) { switch (type) { case TestPartResult::kSuccess: return "Success"; case TestPartResult::kNonFatalFailure: case TestPartResult::kFatalFailure: #ifdef _MSC_VER return "error: "; #else return "Failure\n"; #endif default: return "Unknown result type"; } } // Prints a TestPartResult to a String. static internal::String PrintTestPartResultToString( const TestPartResult& test_part_result) { return (Message() << internal::FormatFileLocation(test_part_result.file_name(), test_part_result.line_number()) << " " << TestPartResultTypeToString(test_part_result.type()) << test_part_result.message()).GetString(); } // Prints a TestPartResult. static void PrintTestPartResult(const TestPartResult& test_part_result) { const internal::String& result = PrintTestPartResultToString(test_part_result); printf("%s\n", result.c_str()); fflush(stdout); // If the test program runs in Visual Studio or a debugger, the // following statements add the test part result message to the Output // window such that the user can double-click on it to jump to the // corresponding source code location; otherwise they do nothing. #if GTEST_OS_WINDOWS && !GTEST_OS_WINDOWS_MOBILE // We don't call OutputDebugString*() on Windows Mobile, as printing // to stdout is done by OutputDebugString() there already - we don't // want the same message printed twice. ::OutputDebugStringA(result.c_str()); ::OutputDebugStringA("\n"); #endif } // class PrettyUnitTestResultPrinter namespace internal { enum GTestColor { COLOR_DEFAULT, COLOR_RED, COLOR_GREEN, COLOR_YELLOW }; #if GTEST_OS_WINDOWS && !GTEST_OS_WINDOWS_MOBILE // Returns the character attribute for the given color. WORD GetColorAttribute(GTestColor color) { switch (color) { case COLOR_RED: return FOREGROUND_RED; case COLOR_GREEN: return FOREGROUND_GREEN; case COLOR_YELLOW: return FOREGROUND_RED | FOREGROUND_GREEN; default: return 0; } } #else // Returns the ANSI color code for the given color. COLOR_DEFAULT is // an invalid input. const char* GetAnsiColorCode(GTestColor color) { switch (color) { case COLOR_RED: return "1"; case COLOR_GREEN: return "2"; case COLOR_YELLOW: return "3"; default: return NULL; }; } #endif // GTEST_OS_WINDOWS && !GTEST_OS_WINDOWS_MOBILE // Returns true iff Google Test should use colors in the output. bool ShouldUseColor(bool stdout_is_tty) { const char* const gtest_color = GTEST_FLAG(color).c_str(); if (String::CaseInsensitiveCStringEquals(gtest_color, "auto")) { #if GTEST_OS_WINDOWS // On Windows the TERM variable is usually not set, but the // console there does support colors. return stdout_is_tty; #else // On non-Windows platforms, we rely on the TERM variable. const char* const term = posix::GetEnv("TERM"); const bool term_supports_color = String::CStringEquals(term, "xterm") || String::CStringEquals(term, "xterm-color") || String::CStringEquals(term, "xterm-256color") || String::CStringEquals(term, "screen") || String::CStringEquals(term, "linux") || String::CStringEquals(term, "cygwin"); return stdout_is_tty && term_supports_color; #endif // GTEST_OS_WINDOWS } return String::CaseInsensitiveCStringEquals(gtest_color, "yes") || String::CaseInsensitiveCStringEquals(gtest_color, "true") || String::CaseInsensitiveCStringEquals(gtest_color, "t") || String::CStringEquals(gtest_color, "1"); // We take "yes", "true", "t", and "1" as meaning "yes". If the // value is neither one of these nor "auto", we treat it as "no" to // be conservative. } // Helpers for printing colored strings to stdout. Note that on Windows, we // cannot simply emit special characters and have the terminal change colors. // This routine must actually emit the characters rather than return a string // that would be colored when printed, as can be done on Linux. void ColoredPrintf(GTestColor color, const char* fmt, ...) { va_list args; va_start(args, fmt); #if GTEST_OS_WINDOWS_MOBILE || GTEST_OS_SYMBIAN || GTEST_OS_ZOS const bool use_color = false; #else static const bool in_color_mode = ShouldUseColor(posix::IsATTY(posix::FileNo(stdout)) != 0); const bool use_color = in_color_mode && (color != COLOR_DEFAULT); #endif // GTEST_OS_WINDOWS_MOBILE || GTEST_OS_SYMBIAN || GTEST_OS_ZOS // The '!= 0' comparison is necessary to satisfy MSVC 7.1. if (!use_color) { vprintf(fmt, args); va_end(args); return; } #if GTEST_OS_WINDOWS && !GTEST_OS_WINDOWS_MOBILE const HANDLE stdout_handle = GetStdHandle(STD_OUTPUT_HANDLE); // Gets the current text color. CONSOLE_SCREEN_BUFFER_INFO buffer_info; GetConsoleScreenBufferInfo(stdout_handle, &buffer_info); const WORD old_color_attrs = buffer_info.wAttributes; // We need to flush the stream buffers into the console before each // SetConsoleTextAttribute call lest it affect the text that is already // printed but has not yet reached the console. fflush(stdout); SetConsoleTextAttribute(stdout_handle, GetColorAttribute(color) | FOREGROUND_INTENSITY); vprintf(fmt, args); fflush(stdout); // Restores the text color. SetConsoleTextAttribute(stdout_handle, old_color_attrs); #else printf("\033[0;3%sm", GetAnsiColorCode(color)); vprintf(fmt, args); printf("\033[m"); // Resets the terminal to default. #endif // GTEST_OS_WINDOWS && !GTEST_OS_WINDOWS_MOBILE va_end(args); } void PrintFullTestCommentIfPresent(const TestInfo& test_info) { const char* const type_param = test_info.type_param(); const char* const value_param = test_info.value_param(); if (type_param != NULL || value_param != NULL) { printf(", where "); if (type_param != NULL) { printf("TypeParam = %s", type_param); if (value_param != NULL) printf(" and "); } if (value_param != NULL) { printf("GetParam() = %s", value_param); } } } // This class implements the TestEventListener interface. // // Class PrettyUnitTestResultPrinter is copyable. class PrettyUnitTestResultPrinter : public TestEventListener { public: PrettyUnitTestResultPrinter() {} static void PrintTestName(const char * test_case, const char * test) { printf("%s.%s", test_case, test); } // The following methods override what's in the TestEventListener class. virtual void OnTestProgramStart(const UnitTest& /*unit_test*/) {} virtual void OnTestIterationStart(const UnitTest& unit_test, int iteration); virtual void OnEnvironmentsSetUpStart(const UnitTest& unit_test); virtual void OnEnvironmentsSetUpEnd(const UnitTest& /*unit_test*/) {} virtual void OnTestCaseStart(const TestCase& test_case); virtual void OnTestStart(const TestInfo& test_info); virtual void OnTestPartResult(const TestPartResult& result); virtual void OnTestEnd(const TestInfo& test_info); virtual void OnTestCaseEnd(const TestCase& test_case); virtual void OnEnvironmentsTearDownStart(const UnitTest& unit_test); virtual void OnEnvironmentsTearDownEnd(const UnitTest& /*unit_test*/) {} virtual void OnTestIterationEnd(const UnitTest& unit_test, int iteration); virtual void OnTestProgramEnd(const UnitTest& /*unit_test*/) {} private: static void PrintFailedTests(const UnitTest& unit_test); internal::String test_case_name_; }; // Fired before each iteration of tests starts. void PrettyUnitTestResultPrinter::OnTestIterationStart( const UnitTest& unit_test, int iteration) { if (GTEST_FLAG(repeat) != 1) printf("\nRepeating all tests (iteration %d) . . .\n\n", iteration + 1); const char* const filter = GTEST_FLAG(filter).c_str(); // Prints the filter if it's not *. This reminds the user that some // tests may be skipped. if (!internal::String::CStringEquals(filter, kUniversalFilter)) { ColoredPrintf(COLOR_YELLOW, "Note: %s filter = %s\n", GTEST_NAME_, filter); } if (internal::ShouldShard(kTestTotalShards, kTestShardIndex, false)) { const Int32 shard_index = Int32FromEnvOrDie(kTestShardIndex, -1); ColoredPrintf(COLOR_YELLOW, "Note: This is test shard %d of %s.\n", static_cast(shard_index) + 1, internal::posix::GetEnv(kTestTotalShards)); } if (GTEST_FLAG(shuffle)) { ColoredPrintf(COLOR_YELLOW, "Note: Randomizing tests' orders with a seed of %d .\n", unit_test.random_seed()); } ColoredPrintf(COLOR_GREEN, "[==========] "); printf("Running %s from %s.\n", FormatTestCount(unit_test.test_to_run_count()).c_str(), FormatTestCaseCount(unit_test.test_case_to_run_count()).c_str()); fflush(stdout); } void PrettyUnitTestResultPrinter::OnEnvironmentsSetUpStart( const UnitTest& /*unit_test*/) { ColoredPrintf(COLOR_GREEN, "[----------] "); printf("Global test environment set-up.\n"); fflush(stdout); } void PrettyUnitTestResultPrinter::OnTestCaseStart(const TestCase& test_case) { test_case_name_ = test_case.name(); const internal::String counts = FormatCountableNoun(test_case.test_to_run_count(), "test", "tests"); ColoredPrintf(COLOR_GREEN, "[----------] "); printf("%s from %s", counts.c_str(), test_case_name_.c_str()); if (test_case.type_param() == NULL) { printf("\n"); } else { printf(", where TypeParam = %s\n", test_case.type_param()); } fflush(stdout); } void PrettyUnitTestResultPrinter::OnTestStart(const TestInfo& test_info) { ColoredPrintf(COLOR_GREEN, "[ RUN ] "); PrintTestName(test_case_name_.c_str(), test_info.name()); printf("\n"); fflush(stdout); } // Called after an assertion failure. void PrettyUnitTestResultPrinter::OnTestPartResult( const TestPartResult& result) { // If the test part succeeded, we don't need to do anything. if (result.type() == TestPartResult::kSuccess) return; // Print failure message from the assertion (e.g. expected this and got that). PrintTestPartResult(result); fflush(stdout); } void PrettyUnitTestResultPrinter::OnTestEnd(const TestInfo& test_info) { if (test_info.result()->Passed()) { ColoredPrintf(COLOR_GREEN, "[ OK ] "); } else { ColoredPrintf(COLOR_RED, "[ FAILED ] "); } PrintTestName(test_case_name_.c_str(), test_info.name()); if (test_info.result()->Failed()) PrintFullTestCommentIfPresent(test_info); if (GTEST_FLAG(print_time)) { printf(" (%s ms)\n", internal::StreamableToString( test_info.result()->elapsed_time()).c_str()); } else { printf("\n"); } fflush(stdout); } void PrettyUnitTestResultPrinter::OnTestCaseEnd(const TestCase& test_case) { if (!GTEST_FLAG(print_time)) return; test_case_name_ = test_case.name(); const internal::String counts = FormatCountableNoun(test_case.test_to_run_count(), "test", "tests"); ColoredPrintf(COLOR_GREEN, "[----------] "); printf("%s from %s (%s ms total)\n\n", counts.c_str(), test_case_name_.c_str(), internal::StreamableToString(test_case.elapsed_time()).c_str()); fflush(stdout); } void PrettyUnitTestResultPrinter::OnEnvironmentsTearDownStart( const UnitTest& /*unit_test*/) { ColoredPrintf(COLOR_GREEN, "[----------] "); printf("Global test environment tear-down\n"); fflush(stdout); } // Internal helper for printing the list of failed tests. void PrettyUnitTestResultPrinter::PrintFailedTests(const UnitTest& unit_test) { const int failed_test_count = unit_test.failed_test_count(); if (failed_test_count == 0) { return; } for (int i = 0; i < unit_test.total_test_case_count(); ++i) { const TestCase& test_case = *unit_test.GetTestCase(i); if (!test_case.should_run() || (test_case.failed_test_count() == 0)) { continue; } for (int j = 0; j < test_case.total_test_count(); ++j) { const TestInfo& test_info = *test_case.GetTestInfo(j); if (!test_info.should_run() || test_info.result()->Passed()) { continue; } ColoredPrintf(COLOR_RED, "[ FAILED ] "); printf("%s.%s", test_case.name(), test_info.name()); PrintFullTestCommentIfPresent(test_info); printf("\n"); } } } void PrettyUnitTestResultPrinter::OnTestIterationEnd(const UnitTest& unit_test, int /*iteration*/) { ColoredPrintf(COLOR_GREEN, "[==========] "); printf("%s from %s ran.", FormatTestCount(unit_test.test_to_run_count()).c_str(), FormatTestCaseCount(unit_test.test_case_to_run_count()).c_str()); if (GTEST_FLAG(print_time)) { printf(" (%s ms total)", internal::StreamableToString(unit_test.elapsed_time()).c_str()); } printf("\n"); ColoredPrintf(COLOR_GREEN, "[ PASSED ] "); printf("%s.\n", FormatTestCount(unit_test.successful_test_count()).c_str()); int num_failures = unit_test.failed_test_count(); if (!unit_test.Passed()) { const int failed_test_count = unit_test.failed_test_count(); ColoredPrintf(COLOR_RED, "[ FAILED ] "); printf("%s, listed below:\n", FormatTestCount(failed_test_count).c_str()); PrintFailedTests(unit_test); printf("\n%2d FAILED %s\n", num_failures, num_failures == 1 ? "TEST" : "TESTS"); } int num_disabled = unit_test.disabled_test_count(); if (num_disabled && !GTEST_FLAG(also_run_disabled_tests)) { if (!num_failures) { printf("\n"); // Add a spacer if no FAILURE banner is displayed. } ColoredPrintf(COLOR_YELLOW, " YOU HAVE %d DISABLED %s\n\n", num_disabled, num_disabled == 1 ? "TEST" : "TESTS"); } // Ensure that Google Test output is printed before, e.g., heapchecker output. fflush(stdout); } // End PrettyUnitTestResultPrinter // class TestEventRepeater // // This class forwards events to other event listeners. class TestEventRepeater : public TestEventListener { public: TestEventRepeater() : forwarding_enabled_(true) {} virtual ~TestEventRepeater(); void Append(TestEventListener *listener); TestEventListener* Release(TestEventListener* listener); // Controls whether events will be forwarded to listeners_. Set to false // in death test child processes. bool forwarding_enabled() const { return forwarding_enabled_; } void set_forwarding_enabled(bool enable) { forwarding_enabled_ = enable; } virtual void OnTestProgramStart(const UnitTest& unit_test); virtual void OnTestIterationStart(const UnitTest& unit_test, int iteration); virtual void OnEnvironmentsSetUpStart(const UnitTest& unit_test); virtual void OnEnvironmentsSetUpEnd(const UnitTest& unit_test); virtual void OnTestCaseStart(const TestCase& test_case); virtual void OnTestStart(const TestInfo& test_info); virtual void OnTestPartResult(const TestPartResult& result); virtual void OnTestEnd(const TestInfo& test_info); virtual void OnTestCaseEnd(const TestCase& test_case); virtual void OnEnvironmentsTearDownStart(const UnitTest& unit_test); virtual void OnEnvironmentsTearDownEnd(const UnitTest& unit_test); virtual void OnTestIterationEnd(const UnitTest& unit_test, int iteration); virtual void OnTestProgramEnd(const UnitTest& unit_test); private: // Controls whether events will be forwarded to listeners_. Set to false // in death test child processes. bool forwarding_enabled_; // The list of listeners that receive events. std::vector listeners_; GTEST_DISALLOW_COPY_AND_ASSIGN_(TestEventRepeater); }; TestEventRepeater::~TestEventRepeater() { ForEach(listeners_, Delete); } void TestEventRepeater::Append(TestEventListener *listener) { listeners_.push_back(listener); } // TODO(vladl@google.com): Factor the search functionality into Vector::Find. TestEventListener* TestEventRepeater::Release(TestEventListener *listener) { for (size_t i = 0; i < listeners_.size(); ++i) { if (listeners_[i] == listener) { listeners_.erase(listeners_.begin() + i); return listener; } } return NULL; } // Since most methods are very similar, use macros to reduce boilerplate. // This defines a member that forwards the call to all listeners. #define GTEST_REPEATER_METHOD_(Name, Type) \ void TestEventRepeater::Name(const Type& parameter) { \ if (forwarding_enabled_) { \ for (size_t i = 0; i < listeners_.size(); i++) { \ listeners_[i]->Name(parameter); \ } \ } \ } // This defines a member that forwards the call to all listeners in reverse // order. #define GTEST_REVERSE_REPEATER_METHOD_(Name, Type) \ void TestEventRepeater::Name(const Type& parameter) { \ if (forwarding_enabled_) { \ for (int i = static_cast(listeners_.size()) - 1; i >= 0; i--) { \ listeners_[i]->Name(parameter); \ } \ } \ } GTEST_REPEATER_METHOD_(OnTestProgramStart, UnitTest) GTEST_REPEATER_METHOD_(OnEnvironmentsSetUpStart, UnitTest) GTEST_REPEATER_METHOD_(OnTestCaseStart, TestCase) GTEST_REPEATER_METHOD_(OnTestStart, TestInfo) GTEST_REPEATER_METHOD_(OnTestPartResult, TestPartResult) GTEST_REPEATER_METHOD_(OnEnvironmentsTearDownStart, UnitTest) GTEST_REVERSE_REPEATER_METHOD_(OnEnvironmentsSetUpEnd, UnitTest) GTEST_REVERSE_REPEATER_METHOD_(OnEnvironmentsTearDownEnd, UnitTest) GTEST_REVERSE_REPEATER_METHOD_(OnTestEnd, TestInfo) GTEST_REVERSE_REPEATER_METHOD_(OnTestCaseEnd, TestCase) GTEST_REVERSE_REPEATER_METHOD_(OnTestProgramEnd, UnitTest) #undef GTEST_REPEATER_METHOD_ #undef GTEST_REVERSE_REPEATER_METHOD_ void TestEventRepeater::OnTestIterationStart(const UnitTest& unit_test, int iteration) { if (forwarding_enabled_) { for (size_t i = 0; i < listeners_.size(); i++) { listeners_[i]->OnTestIterationStart(unit_test, iteration); } } } void TestEventRepeater::OnTestIterationEnd(const UnitTest& unit_test, int iteration) { if (forwarding_enabled_) { for (int i = static_cast(listeners_.size()) - 1; i >= 0; i--) { listeners_[i]->OnTestIterationEnd(unit_test, iteration); } } } // End TestEventRepeater // This class generates an XML output file. class XmlUnitTestResultPrinter : public EmptyTestEventListener { public: explicit XmlUnitTestResultPrinter(const char* output_file); virtual void OnTestIterationEnd(const UnitTest& unit_test, int iteration); private: // Is c a whitespace character that is normalized to a space character // when it appears in an XML attribute value? static bool IsNormalizableWhitespace(char c) { return c == 0x9 || c == 0xA || c == 0xD; } // May c appear in a well-formed XML document? static bool IsValidXmlCharacter(char c) { return IsNormalizableWhitespace(c) || c >= 0x20; } // Returns an XML-escaped copy of the input string str. If // is_attribute is true, the text is meant to appear as an attribute // value, and normalizable whitespace is preserved by replacing it // with character references. static String EscapeXml(const char* str, bool is_attribute); // Returns the given string with all characters invalid in XML removed. static string RemoveInvalidXmlCharacters(const string& str); // Convenience wrapper around EscapeXml when str is an attribute value. static String EscapeXmlAttribute(const char* str) { return EscapeXml(str, true); } // Convenience wrapper around EscapeXml when str is not an attribute value. static String EscapeXmlText(const char* str) { return EscapeXml(str, false); } // Streams an XML CDATA section, escaping invalid CDATA sequences as needed. static void OutputXmlCDataSection(::std::ostream* stream, const char* data); // Streams an XML representation of a TestInfo object. static void OutputXmlTestInfo(::std::ostream* stream, const char* test_case_name, const TestInfo& test_info); // Prints an XML representation of a TestCase object static void PrintXmlTestCase(FILE* out, const TestCase& test_case); // Prints an XML summary of unit_test to output stream out. static void PrintXmlUnitTest(FILE* out, const UnitTest& unit_test); // Produces a string representing the test properties in a result as space // delimited XML attributes based on the property key="value" pairs. // When the String is not empty, it includes a space at the beginning, // to delimit this attribute from prior attributes. static String TestPropertiesAsXmlAttributes(const TestResult& result); // The output file. const String output_file_; GTEST_DISALLOW_COPY_AND_ASSIGN_(XmlUnitTestResultPrinter); }; // Creates a new XmlUnitTestResultPrinter. XmlUnitTestResultPrinter::XmlUnitTestResultPrinter(const char* output_file) : output_file_(output_file) { if (output_file_.c_str() == NULL || output_file_.empty()) { fprintf(stderr, "XML output file may not be null\n"); fflush(stderr); exit(EXIT_FAILURE); } } // Called after the unit test ends. void XmlUnitTestResultPrinter::OnTestIterationEnd(const UnitTest& unit_test, int /*iteration*/) { FILE* xmlout = NULL; FilePath output_file(output_file_); FilePath output_dir(output_file.RemoveFileName()); if (output_dir.CreateDirectoriesRecursively()) { xmlout = posix::FOpen(output_file_.c_str(), "w"); } if (xmlout == NULL) { // TODO(wan): report the reason of the failure. // // We don't do it for now as: // // 1. There is no urgent need for it. // 2. It's a bit involved to make the errno variable thread-safe on // all three operating systems (Linux, Windows, and Mac OS). // 3. To interpret the meaning of errno in a thread-safe way, // we need the strerror_r() function, which is not available on // Windows. fprintf(stderr, "Unable to open file \"%s\"\n", output_file_.c_str()); fflush(stderr); exit(EXIT_FAILURE); } PrintXmlUnitTest(xmlout, unit_test); fclose(xmlout); } // Returns an XML-escaped copy of the input string str. If is_attribute // is true, the text is meant to appear as an attribute value, and // normalizable whitespace is preserved by replacing it with character // references. // // Invalid XML characters in str, if any, are stripped from the output. // It is expected that most, if not all, of the text processed by this // module will consist of ordinary English text. // If this module is ever modified to produce version 1.1 XML output, // most invalid characters can be retained using character references. // TODO(wan): It might be nice to have a minimally invasive, human-readable // escaping scheme for invalid characters, rather than dropping them. String XmlUnitTestResultPrinter::EscapeXml(const char* str, bool is_attribute) { Message m; if (str != NULL) { for (const char* src = str; *src; ++src) { switch (*src) { case '<': m << "<"; break; case '>': m << ">"; break; case '&': m << "&"; break; case '\'': if (is_attribute) m << "'"; else m << '\''; break; case '"': if (is_attribute) m << """; else m << '"'; break; default: if (IsValidXmlCharacter(*src)) { if (is_attribute && IsNormalizableWhitespace(*src)) m << String::Format("&#x%02X;", unsigned(*src)); else m << *src; } break; } } } return m.GetString(); } // Returns the given string with all characters invalid in XML removed. // Currently invalid characters are dropped from the string. An // alternative is to replace them with certain characters such as . or ?. string XmlUnitTestResultPrinter::RemoveInvalidXmlCharacters(const string& str) { string output; output.reserve(str.size()); for (string::const_iterator it = str.begin(); it != str.end(); ++it) if (IsValidXmlCharacter(*it)) output.push_back(*it); return output; } // The following routines generate an XML representation of a UnitTest // object. // // This is how Google Test concepts map to the DTD: // // <-- corresponds to a UnitTest object // <-- corresponds to a TestCase object // <-- corresponds to a TestInfo object // ... // ... // ... // <-- individual assertion failures // // // // Formats the given time in milliseconds as seconds. std::string FormatTimeInMillisAsSeconds(TimeInMillis ms) { ::std::stringstream ss; ss << ms/1000.0; return ss.str(); } // Streams an XML CDATA section, escaping invalid CDATA sequences as needed. void XmlUnitTestResultPrinter::OutputXmlCDataSection(::std::ostream* stream, const char* data) { const char* segment = data; *stream << ""); if (next_segment != NULL) { stream->write( segment, static_cast(next_segment - segment)); *stream << "]]>]]>"); } else { *stream << segment; break; } } *stream << "]]>"; } // Prints an XML representation of a TestInfo object. // TODO(wan): There is also value in printing properties with the plain printer. void XmlUnitTestResultPrinter::OutputXmlTestInfo(::std::ostream* stream, const char* test_case_name, const TestInfo& test_info) { const TestResult& result = *test_info.result(); *stream << " \n"; *stream << " "; const string location = internal::FormatCompilerIndependentFileLocation( part.file_name(), part.line_number()); const string message = location + "\n" + part.message(); OutputXmlCDataSection(stream, RemoveInvalidXmlCharacters(message).c_str()); *stream << "\n"; } } if (failures == 0) *stream << " />\n"; else *stream << " \n"; } // Prints an XML representation of a TestCase object void XmlUnitTestResultPrinter::PrintXmlTestCase(FILE* out, const TestCase& test_case) { fprintf(out, " \n", FormatTimeInMillisAsSeconds(test_case.elapsed_time()).c_str()); for (int i = 0; i < test_case.total_test_count(); ++i) { ::std::stringstream stream; OutputXmlTestInfo(&stream, test_case.name(), *test_case.GetTestInfo(i)); fprintf(out, "%s", StringStreamToString(&stream).c_str()); } fprintf(out, " \n"); } // Prints an XML summary of unit_test to output stream out. void XmlUnitTestResultPrinter::PrintXmlUnitTest(FILE* out, const UnitTest& unit_test) { fprintf(out, "\n"); fprintf(out, "\n"); for (int i = 0; i < unit_test.total_test_case_count(); ++i) PrintXmlTestCase(out, *unit_test.GetTestCase(i)); fprintf(out, "\n"); } // Produces a string representing the test properties in a result as space // delimited XML attributes based on the property key="value" pairs. String XmlUnitTestResultPrinter::TestPropertiesAsXmlAttributes( const TestResult& result) { Message attributes; for (int i = 0; i < result.test_property_count(); ++i) { const TestProperty& property = result.GetTestProperty(i); attributes << " " << property.key() << "=" << "\"" << EscapeXmlAttribute(property.value()) << "\""; } return attributes.GetString(); } // End XmlUnitTestResultPrinter #if GTEST_CAN_STREAM_RESULTS_ // Streams test results to the given port on the given host machine. class StreamingListener : public EmptyTestEventListener { public: // Escapes '=', '&', '%', and '\n' characters in str as "%xx". static string UrlEncode(const char* str); StreamingListener(const string& host, const string& port) : sockfd_(-1), host_name_(host), port_num_(port) { MakeConnection(); Send("gtest_streaming_protocol_version=1.0\n"); } virtual ~StreamingListener() { if (sockfd_ != -1) CloseConnection(); } void OnTestProgramStart(const UnitTest& /* unit_test */) { Send("event=TestProgramStart\n"); } void OnTestProgramEnd(const UnitTest& unit_test) { // Note that Google Test current only report elapsed time for each // test iteration, not for the entire test program. Send(String::Format("event=TestProgramEnd&passed=%d\n", unit_test.Passed())); // Notify the streaming server to stop. CloseConnection(); } void OnTestIterationStart(const UnitTest& /* unit_test */, int iteration) { Send(String::Format("event=TestIterationStart&iteration=%d\n", iteration)); } void OnTestIterationEnd(const UnitTest& unit_test, int /* iteration */) { Send(String::Format("event=TestIterationEnd&passed=%d&elapsed_time=%sms\n", unit_test.Passed(), StreamableToString(unit_test.elapsed_time()).c_str())); } void OnTestCaseStart(const TestCase& test_case) { Send(String::Format("event=TestCaseStart&name=%s\n", test_case.name())); } void OnTestCaseEnd(const TestCase& test_case) { Send(String::Format("event=TestCaseEnd&passed=%d&elapsed_time=%sms\n", test_case.Passed(), StreamableToString(test_case.elapsed_time()).c_str())); } void OnTestStart(const TestInfo& test_info) { Send(String::Format("event=TestStart&name=%s\n", test_info.name())); } void OnTestEnd(const TestInfo& test_info) { Send(String::Format( "event=TestEnd&passed=%d&elapsed_time=%sms\n", (test_info.result())->Passed(), StreamableToString((test_info.result())->elapsed_time()).c_str())); } void OnTestPartResult(const TestPartResult& test_part_result) { const char* file_name = test_part_result.file_name(); if (file_name == NULL) file_name = ""; Send(String::Format("event=TestPartResult&file=%s&line=%d&message=", UrlEncode(file_name).c_str(), test_part_result.line_number())); Send(UrlEncode(test_part_result.message()) + "\n"); } private: // Creates a client socket and connects to the server. void MakeConnection(); // Closes the socket. void CloseConnection() { GTEST_CHECK_(sockfd_ != -1) << "CloseConnection() can be called only when there is a connection."; close(sockfd_); sockfd_ = -1; } // Sends a string to the socket. void Send(const string& message) { GTEST_CHECK_(sockfd_ != -1) << "Send() can be called only when there is a connection."; const int len = static_cast(message.length()); if (write(sockfd_, message.c_str(), len) != len) { GTEST_LOG_(WARNING) << "stream_result_to: failed to stream to " << host_name_ << ":" << port_num_; } } int sockfd_; // socket file descriptor const string host_name_; const string port_num_; GTEST_DISALLOW_COPY_AND_ASSIGN_(StreamingListener); }; // class StreamingListener // Checks if str contains '=', '&', '%' or '\n' characters. If yes, // replaces them by "%xx" where xx is their hexadecimal value. For // example, replaces "=" with "%3D". This algorithm is O(strlen(str)) // in both time and space -- important as the input str may contain an // arbitrarily long test failure message and stack trace. string StreamingListener::UrlEncode(const char* str) { string result; result.reserve(strlen(str) + 1); for (char ch = *str; ch != '\0'; ch = *++str) { switch (ch) { case '%': case '=': case '&': case '\n': result.append(String::Format("%%%02x", static_cast(ch))); break; default: result.push_back(ch); break; } } return result; } void StreamingListener::MakeConnection() { GTEST_CHECK_(sockfd_ == -1) << "MakeConnection() can't be called when there is already a connection."; addrinfo hints; memset(&hints, 0, sizeof(hints)); hints.ai_family = AF_UNSPEC; // To allow both IPv4 and IPv6 addresses. hints.ai_socktype = SOCK_STREAM; addrinfo* servinfo = NULL; // Use the getaddrinfo() to get a linked list of IP addresses for // the given host name. const int error_num = getaddrinfo( host_name_.c_str(), port_num_.c_str(), &hints, &servinfo); if (error_num != 0) { GTEST_LOG_(WARNING) << "stream_result_to: getaddrinfo() failed: " << gai_strerror(error_num); } // Loop through all the results and connect to the first we can. for (addrinfo* cur_addr = servinfo; sockfd_ == -1 && cur_addr != NULL; cur_addr = cur_addr->ai_next) { sockfd_ = socket( cur_addr->ai_family, cur_addr->ai_socktype, cur_addr->ai_protocol); if (sockfd_ != -1) { // Connect the client socket to the server socket. if (connect(sockfd_, cur_addr->ai_addr, cur_addr->ai_addrlen) == -1) { close(sockfd_); sockfd_ = -1; } } } freeaddrinfo(servinfo); // all done with this structure if (sockfd_ == -1) { GTEST_LOG_(WARNING) << "stream_result_to: failed to connect to " << host_name_ << ":" << port_num_; } } // End of class Streaming Listener #endif // GTEST_CAN_STREAM_RESULTS__ // Class ScopedTrace // Pushes the given source file location and message onto a per-thread // trace stack maintained by Google Test. // L < UnitTest::mutex_ ScopedTrace::ScopedTrace(const char* file, int line, const Message& message) { TraceInfo trace; trace.file = file; trace.line = line; trace.message = message.GetString(); UnitTest::GetInstance()->PushGTestTrace(trace); } // Pops the info pushed by the c'tor. // L < UnitTest::mutex_ ScopedTrace::~ScopedTrace() { UnitTest::GetInstance()->PopGTestTrace(); } // class OsStackTraceGetter // Returns the current OS stack trace as a String. Parameters: // // max_depth - the maximum number of stack frames to be included // in the trace. // skip_count - the number of top frames to be skipped; doesn't count // against max_depth. // // L < mutex_ // We use "L < mutex_" to denote that the function may acquire mutex_. String OsStackTraceGetter::CurrentStackTrace(int, int) { return String(""); } // L < mutex_ void OsStackTraceGetter::UponLeavingGTest() { } const char* const OsStackTraceGetter::kElidedFramesMarker = "... " GTEST_NAME_ " internal frames ..."; } // namespace internal // class TestEventListeners TestEventListeners::TestEventListeners() : repeater_(new internal::TestEventRepeater()), default_result_printer_(NULL), default_xml_generator_(NULL) { } TestEventListeners::~TestEventListeners() { delete repeater_; } // Returns the standard listener responsible for the default console // output. Can be removed from the listeners list to shut down default // console output. Note that removing this object from the listener list // with Release transfers its ownership to the user. void TestEventListeners::Append(TestEventListener* listener) { repeater_->Append(listener); } // Removes the given event listener from the list and returns it. It then // becomes the caller's responsibility to delete the listener. Returns // NULL if the listener is not found in the list. TestEventListener* TestEventListeners::Release(TestEventListener* listener) { if (listener == default_result_printer_) default_result_printer_ = NULL; else if (listener == default_xml_generator_) default_xml_generator_ = NULL; return repeater_->Release(listener); } // Returns repeater that broadcasts the TestEventListener events to all // subscribers. TestEventListener* TestEventListeners::repeater() { return repeater_; } // Sets the default_result_printer attribute to the provided listener. // The listener is also added to the listener list and previous // default_result_printer is removed from it and deleted. The listener can // also be NULL in which case it will not be added to the list. Does // nothing if the previous and the current listener objects are the same. void TestEventListeners::SetDefaultResultPrinter(TestEventListener* listener) { if (default_result_printer_ != listener) { // It is an error to pass this method a listener that is already in the // list. delete Release(default_result_printer_); default_result_printer_ = listener; if (listener != NULL) Append(listener); } } // Sets the default_xml_generator attribute to the provided listener. The // listener is also added to the listener list and previous // default_xml_generator is removed from it and deleted. The listener can // also be NULL in which case it will not be added to the list. Does // nothing if the previous and the current listener objects are the same. void TestEventListeners::SetDefaultXmlGenerator(TestEventListener* listener) { if (default_xml_generator_ != listener) { // It is an error to pass this method a listener that is already in the // list. delete Release(default_xml_generator_); default_xml_generator_ = listener; if (listener != NULL) Append(listener); } } // Controls whether events will be forwarded by the repeater to the // listeners in the list. bool TestEventListeners::EventForwardingEnabled() const { return repeater_->forwarding_enabled(); } void TestEventListeners::SuppressEventForwarding() { repeater_->set_forwarding_enabled(false); } // class UnitTest // Gets the singleton UnitTest object. The first time this method is // called, a UnitTest object is constructed and returned. Consecutive // calls will return the same object. // // We don't protect this under mutex_ as a user is not supposed to // call this before main() starts, from which point on the return // value will never change. UnitTest * UnitTest::GetInstance() { // When compiled with MSVC 7.1 in optimized mode, destroying the // UnitTest object upon exiting the program messes up the exit code, // causing successful tests to appear failed. We have to use a // different implementation in this case to bypass the compiler bug. // This implementation makes the compiler happy, at the cost of // leaking the UnitTest object. // CodeGear C++Builder insists on a public destructor for the // default implementation. Use this implementation to keep good OO // design with private destructor. #if (_MSC_VER == 1310 && !defined(_DEBUG)) || defined(__BORLANDC__) static UnitTest* const instance = new UnitTest; return instance; #else static UnitTest instance; return &instance; #endif // (_MSC_VER == 1310 && !defined(_DEBUG)) || defined(__BORLANDC__) } // Gets the number of successful test cases. int UnitTest::successful_test_case_count() const { return impl()->successful_test_case_count(); } // Gets the number of failed test cases. int UnitTest::failed_test_case_count() const { return impl()->failed_test_case_count(); } // Gets the number of all test cases. int UnitTest::total_test_case_count() const { return impl()->total_test_case_count(); } // Gets the number of all test cases that contain at least one test // that should run. int UnitTest::test_case_to_run_count() const { return impl()->test_case_to_run_count(); } // Gets the number of successful tests. int UnitTest::successful_test_count() const { return impl()->successful_test_count(); } // Gets the number of failed tests. int UnitTest::failed_test_count() const { return impl()->failed_test_count(); } // Gets the number of disabled tests. int UnitTest::disabled_test_count() const { return impl()->disabled_test_count(); } // Gets the number of all tests. int UnitTest::total_test_count() const { return impl()->total_test_count(); } // Gets the number of tests that should run. int UnitTest::test_to_run_count() const { return impl()->test_to_run_count(); } // Gets the elapsed time, in milliseconds. internal::TimeInMillis UnitTest::elapsed_time() const { return impl()->elapsed_time(); } // Returns true iff the unit test passed (i.e. all test cases passed). bool UnitTest::Passed() const { return impl()->Passed(); } // Returns true iff the unit test failed (i.e. some test case failed // or something outside of all tests failed). bool UnitTest::Failed() const { return impl()->Failed(); } // Gets the i-th test case among all the test cases. i can range from 0 to // total_test_case_count() - 1. If i is not in that range, returns NULL. const TestCase* UnitTest::GetTestCase(int i) const { return impl()->GetTestCase(i); } // Gets the i-th test case among all the test cases. i can range from 0 to // total_test_case_count() - 1. If i is not in that range, returns NULL. TestCase* UnitTest::GetMutableTestCase(int i) { return impl()->GetMutableTestCase(i); } // Returns the list of event listeners that can be used to track events // inside Google Test. TestEventListeners& UnitTest::listeners() { return *impl()->listeners(); } // Registers and returns a global test environment. When a test // program is run, all global test environments will be set-up in the // order they were registered. After all tests in the program have // finished, all global test environments will be torn-down in the // *reverse* order they were registered. // // The UnitTest object takes ownership of the given environment. // // We don't protect this under mutex_, as we only support calling it // from the main thread. Environment* UnitTest::AddEnvironment(Environment* env) { if (env == NULL) { return NULL; } impl_->environments().push_back(env); return env; } // Adds a TestPartResult to the current TestResult object. All Google Test // assertion macros (e.g. ASSERT_TRUE, EXPECT_EQ, etc) eventually call // this to report their results. The user code should use the // assertion macros instead of calling this directly. // L < mutex_ void UnitTest::AddTestPartResult(TestPartResult::Type result_type, const char* file_name, int line_number, const internal::String& message, const internal::String& os_stack_trace) { Message msg; msg << message; internal::MutexLock lock(&mutex_); if (impl_->gtest_trace_stack().size() > 0) { msg << "\n" << GTEST_NAME_ << " trace:"; for (int i = static_cast(impl_->gtest_trace_stack().size()); i > 0; --i) { const internal::TraceInfo& trace = impl_->gtest_trace_stack()[i - 1]; msg << "\n" << internal::FormatFileLocation(trace.file, trace.line) << " " << trace.message; } } if (os_stack_trace.c_str() != NULL && !os_stack_trace.empty()) { msg << internal::kStackTraceMarker << os_stack_trace; } const TestPartResult result = TestPartResult(result_type, file_name, line_number, msg.GetString().c_str()); impl_->GetTestPartResultReporterForCurrentThread()-> ReportTestPartResult(result); if (result_type != TestPartResult::kSuccess) { // gtest_break_on_failure takes precedence over // gtest_throw_on_failure. This allows a user to set the latter // in the code (perhaps in order to use Google Test assertions // with another testing framework) and specify the former on the // command line for debugging. if (GTEST_FLAG(break_on_failure)) { #if GTEST_OS_WINDOWS // Using DebugBreak on Windows allows gtest to still break into a debugger // when a failure happens and both the --gtest_break_on_failure and // the --gtest_catch_exceptions flags are specified. DebugBreak(); #else // Dereference NULL through a volatile pointer to prevent the compiler // from removing. We use this rather than abort() or __builtin_trap() for // portability: Symbian doesn't implement abort() well, and some debuggers // don't correctly trap abort(). *static_cast(NULL) = 1; #endif // GTEST_OS_WINDOWS } else if (GTEST_FLAG(throw_on_failure)) { #if GTEST_HAS_EXCEPTIONS throw GoogleTestFailureException(result); #else // We cannot call abort() as it generates a pop-up in debug mode // that cannot be suppressed in VC 7.1 or below. exit(1); #endif } } } // Creates and adds a property to the current TestResult. If a property matching // the supplied value already exists, updates its value instead. void UnitTest::RecordPropertyForCurrentTest(const char* key, const char* value) { const TestProperty test_property(key, value); impl_->current_test_result()->RecordProperty(test_property); } // Runs all tests in this UnitTest object and prints the result. // Returns 0 if successful, or 1 otherwise. // // We don't protect this under mutex_, as we only support calling it // from the main thread. int UnitTest::Run() { // Captures the value of GTEST_FLAG(catch_exceptions). This value will be // used for the duration of the program. impl()->set_catch_exceptions(GTEST_FLAG(catch_exceptions)); #if GTEST_HAS_SEH const bool in_death_test_child_process = internal::GTEST_FLAG(internal_run_death_test).length() > 0; // Either the user wants Google Test to catch exceptions thrown by the // tests or this is executing in the context of death test child // process. In either case the user does not want to see pop-up dialogs // about crashes - they are expected. if (impl()->catch_exceptions() || in_death_test_child_process) { # if !GTEST_OS_WINDOWS_MOBILE // SetErrorMode doesn't exist on CE. SetErrorMode(SEM_FAILCRITICALERRORS | SEM_NOALIGNMENTFAULTEXCEPT | SEM_NOGPFAULTERRORBOX | SEM_NOOPENFILEERRORBOX); # endif // !GTEST_OS_WINDOWS_MOBILE # if (defined(_MSC_VER) || GTEST_OS_WINDOWS_MINGW) && !GTEST_OS_WINDOWS_MOBILE // Death test children can be terminated with _abort(). On Windows, // _abort() can show a dialog with a warning message. This forces the // abort message to go to stderr instead. _set_error_mode(_OUT_TO_STDERR); # endif # if _MSC_VER >= 1400 && !GTEST_OS_WINDOWS_MOBILE // In the debug version, Visual Studio pops up a separate dialog // offering a choice to debug the aborted program. We need to suppress // this dialog or it will pop up for every EXPECT/ASSERT_DEATH statement // executed. Google Test will notify the user of any unexpected // failure via stderr. // // VC++ doesn't define _set_abort_behavior() prior to the version 8.0. // Users of prior VC versions shall suffer the agony and pain of // clicking through the countless debug dialogs. // TODO(vladl@google.com): find a way to suppress the abort dialog() in the // debug mode when compiled with VC 7.1 or lower. if (!GTEST_FLAG(break_on_failure)) _set_abort_behavior( 0x0, // Clear the following flags: _WRITE_ABORT_MSG | _CALL_REPORTFAULT); // pop-up window, core dump. # endif #if _MSC_VER >= 1310 && !GTEST_OS_WINDOWS_MOBILE // Suppress the "Debug Assertion Failed" dialog in the debug mode. (As far // as I know, these functions are available on Visual Studio .NET 2003 or // later.) _CrtSetReportMode(_CRT_ASSERT, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG); _CrtSetReportFile(_CRT_ASSERT, _CRTDBG_FILE_STDERR); _CrtSetReportMode(_CRT_WARN, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG); _CrtSetReportFile(_CRT_WARN, _CRTDBG_FILE_STDERR); _CrtSetReportMode(_CRT_ERROR, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG); _CrtSetReportFile(_CRT_ERROR, _CRTDBG_FILE_STDERR); #endif } #endif // GTEST_HAS_SEH return internal::HandleExceptionsInMethodIfSupported( impl(), &internal::UnitTestImpl::RunAllTests, "auxiliary test code (environments or event listeners)") ? 0 : 1; } // Returns the working directory when the first TEST() or TEST_F() was // executed. const char* UnitTest::original_working_dir() const { return impl_->original_working_dir_.c_str(); } // Returns the TestCase object for the test that's currently running, // or NULL if no test is running. // L < mutex_ const TestCase* UnitTest::current_test_case() const { internal::MutexLock lock(&mutex_); return impl_->current_test_case(); } // Returns the TestInfo object for the test that's currently running, // or NULL if no test is running. // L < mutex_ const TestInfo* UnitTest::current_test_info() const { internal::MutexLock lock(&mutex_); return impl_->current_test_info(); } // Returns the random seed used at the start of the current test run. int UnitTest::random_seed() const { return impl_->random_seed(); } #if GTEST_HAS_PARAM_TEST // Returns ParameterizedTestCaseRegistry object used to keep track of // value-parameterized tests and instantiate and register them. // L < mutex_ internal::ParameterizedTestCaseRegistry& UnitTest::parameterized_test_registry() { return impl_->parameterized_test_registry(); } #endif // GTEST_HAS_PARAM_TEST // Creates an empty UnitTest. UnitTest::UnitTest() { impl_ = new internal::UnitTestImpl(this); } // Destructor of UnitTest. UnitTest::~UnitTest() { delete impl_; } // Pushes a trace defined by SCOPED_TRACE() on to the per-thread // Google Test trace stack. // L < mutex_ void UnitTest::PushGTestTrace(const internal::TraceInfo& trace) { internal::MutexLock lock(&mutex_); impl_->gtest_trace_stack().push_back(trace); } // Pops a trace from the per-thread Google Test trace stack. // L < mutex_ void UnitTest::PopGTestTrace() { internal::MutexLock lock(&mutex_); impl_->gtest_trace_stack().pop_back(); } namespace internal { UnitTestImpl::UnitTestImpl(UnitTest* parent) : parent_(parent), #ifdef _MSC_VER # pragma warning(push) // Saves the current warning state. # pragma warning(disable:4355) // Temporarily disables warning 4355 // (using this in initializer). default_global_test_part_result_reporter_(this), default_per_thread_test_part_result_reporter_(this), # pragma warning(pop) // Restores the warning state again. #else default_global_test_part_result_reporter_(this), default_per_thread_test_part_result_reporter_(this), #endif // _MSC_VER global_test_part_result_repoter_( &default_global_test_part_result_reporter_), per_thread_test_part_result_reporter_( &default_per_thread_test_part_result_reporter_), #if GTEST_HAS_PARAM_TEST parameterized_test_registry_(), parameterized_tests_registered_(false), #endif // GTEST_HAS_PARAM_TEST last_death_test_case_(-1), current_test_case_(NULL), current_test_info_(NULL), ad_hoc_test_result_(), os_stack_trace_getter_(NULL), post_flag_parse_init_performed_(false), random_seed_(0), // Will be overridden by the flag before first use. random_(0), // Will be reseeded before first use. elapsed_time_(0), #if GTEST_HAS_DEATH_TEST internal_run_death_test_flag_(NULL), death_test_factory_(new DefaultDeathTestFactory), #endif // Will be overridden by the flag before first use. catch_exceptions_(false) { listeners()->SetDefaultResultPrinter(new PrettyUnitTestResultPrinter); } UnitTestImpl::~UnitTestImpl() { // Deletes every TestCase. ForEach(test_cases_, internal::Delete); // Deletes every Environment. ForEach(environments_, internal::Delete); delete os_stack_trace_getter_; } #if GTEST_HAS_DEATH_TEST // Disables event forwarding if the control is currently in a death test // subprocess. Must not be called before InitGoogleTest. void UnitTestImpl::SuppressTestEventsIfInSubprocess() { if (internal_run_death_test_flag_.get() != NULL) listeners()->SuppressEventForwarding(); } #endif // GTEST_HAS_DEATH_TEST // Initializes event listeners performing XML output as specified by // UnitTestOptions. Must not be called before InitGoogleTest. void UnitTestImpl::ConfigureXmlOutput() { const String& output_format = UnitTestOptions::GetOutputFormat(); if (output_format == "xml") { listeners()->SetDefaultXmlGenerator(new XmlUnitTestResultPrinter( UnitTestOptions::GetAbsolutePathToOutputFile().c_str())); } else if (output_format != "") { printf("WARNING: unrecognized output format \"%s\" ignored.\n", output_format.c_str()); fflush(stdout); } } #if GTEST_CAN_STREAM_RESULTS_ // Initializes event listeners for streaming test results in String form. // Must not be called before InitGoogleTest. void UnitTestImpl::ConfigureStreamingOutput() { const string& target = GTEST_FLAG(stream_result_to); if (!target.empty()) { const size_t pos = target.find(':'); if (pos != string::npos) { listeners()->Append(new StreamingListener(target.substr(0, pos), target.substr(pos+1))); } else { printf("WARNING: unrecognized streaming target \"%s\" ignored.\n", target.c_str()); fflush(stdout); } } } #endif // GTEST_CAN_STREAM_RESULTS_ // Performs initialization dependent upon flag values obtained in // ParseGoogleTestFlagsOnly. Is called from InitGoogleTest after the call to // ParseGoogleTestFlagsOnly. In case a user neglects to call InitGoogleTest // this function is also called from RunAllTests. Since this function can be // called more than once, it has to be idempotent. void UnitTestImpl::PostFlagParsingInit() { // Ensures that this function does not execute more than once. if (!post_flag_parse_init_performed_) { post_flag_parse_init_performed_ = true; #if GTEST_HAS_DEATH_TEST InitDeathTestSubprocessControlInfo(); SuppressTestEventsIfInSubprocess(); #endif // GTEST_HAS_DEATH_TEST // Registers parameterized tests. This makes parameterized tests // available to the UnitTest reflection API without running // RUN_ALL_TESTS. RegisterParameterizedTests(); // Configures listeners for XML output. This makes it possible for users // to shut down the default XML output before invoking RUN_ALL_TESTS. ConfigureXmlOutput(); #if GTEST_CAN_STREAM_RESULTS_ // Configures listeners for streaming test results to the specified server. ConfigureStreamingOutput(); #endif // GTEST_CAN_STREAM_RESULTS_ } } // A predicate that checks the name of a TestCase against a known // value. // // This is used for implementation of the UnitTest class only. We put // it in the anonymous namespace to prevent polluting the outer // namespace. // // TestCaseNameIs is copyable. class TestCaseNameIs { public: // Constructor. explicit TestCaseNameIs(const String& name) : name_(name) {} // Returns true iff the name of test_case matches name_. bool operator()(const TestCase* test_case) const { return test_case != NULL && strcmp(test_case->name(), name_.c_str()) == 0; } private: String name_; }; // Finds and returns a TestCase with the given name. If one doesn't // exist, creates one and returns it. It's the CALLER'S // RESPONSIBILITY to ensure that this function is only called WHEN THE // TESTS ARE NOT SHUFFLED. // // Arguments: // // test_case_name: name of the test case // type_param: the name of the test case's type parameter, or NULL if // this is not a typed or a type-parameterized test case. // set_up_tc: pointer to the function that sets up the test case // tear_down_tc: pointer to the function that tears down the test case TestCase* UnitTestImpl::GetTestCase(const char* test_case_name, const char* type_param, Test::SetUpTestCaseFunc set_up_tc, Test::TearDownTestCaseFunc tear_down_tc) { // Can we find a TestCase with the given name? const std::vector::const_iterator test_case = std::find_if(test_cases_.begin(), test_cases_.end(), TestCaseNameIs(test_case_name)); if (test_case != test_cases_.end()) return *test_case; // No. Let's create one. TestCase* const new_test_case = new TestCase(test_case_name, type_param, set_up_tc, tear_down_tc); // Is this a death test case? if (internal::UnitTestOptions::MatchesFilter(String(test_case_name), kDeathTestCaseFilter)) { // Yes. Inserts the test case after the last death test case // defined so far. This only works when the test cases haven't // been shuffled. Otherwise we may end up running a death test // after a non-death test. ++last_death_test_case_; test_cases_.insert(test_cases_.begin() + last_death_test_case_, new_test_case); } else { // No. Appends to the end of the list. test_cases_.push_back(new_test_case); } test_case_indices_.push_back(static_cast(test_case_indices_.size())); return new_test_case; } // Helpers for setting up / tearing down the given environment. They // are for use in the ForEach() function. static void SetUpEnvironment(Environment* env) { env->SetUp(); } static void TearDownEnvironment(Environment* env) { env->TearDown(); } // Runs all tests in this UnitTest object, prints the result, and // returns true if all tests are successful. If any exception is // thrown during a test, the test is considered to be failed, but the // rest of the tests will still be run. // // When parameterized tests are enabled, it expands and registers // parameterized tests first in RegisterParameterizedTests(). // All other functions called from RunAllTests() may safely assume that // parameterized tests are ready to be counted and run. bool UnitTestImpl::RunAllTests() { // Makes sure InitGoogleTest() was called. if (!GTestIsInitialized()) { printf("%s", "\nThis test program did NOT call ::testing::InitGoogleTest " "before calling RUN_ALL_TESTS(). Please fix it.\n"); return false; } // Do not run any test if the --help flag was specified. if (g_help_flag) return true; // Repeats the call to the post-flag parsing initialization in case the // user didn't call InitGoogleTest. PostFlagParsingInit(); // Even if sharding is not on, test runners may want to use the // GTEST_SHARD_STATUS_FILE to query whether the test supports the sharding // protocol. internal::WriteToShardStatusFileIfNeeded(); // True iff we are in a subprocess for running a thread-safe-style // death test. bool in_subprocess_for_death_test = false; #if GTEST_HAS_DEATH_TEST in_subprocess_for_death_test = (internal_run_death_test_flag_.get() != NULL); #endif // GTEST_HAS_DEATH_TEST const bool should_shard = ShouldShard(kTestTotalShards, kTestShardIndex, in_subprocess_for_death_test); // Compares the full test names with the filter to decide which // tests to run. const bool has_tests_to_run = FilterTests(should_shard ? HONOR_SHARDING_PROTOCOL : IGNORE_SHARDING_PROTOCOL) > 0; // Lists the tests and exits if the --gtest_list_tests flag was specified. if (GTEST_FLAG(list_tests)) { // This must be called *after* FilterTests() has been called. ListTestsMatchingFilter(); return true; } random_seed_ = GTEST_FLAG(shuffle) ? GetRandomSeedFromFlag(GTEST_FLAG(random_seed)) : 0; // True iff at least one test has failed. bool failed = false; TestEventListener* repeater = listeners()->repeater(); repeater->OnTestProgramStart(*parent_); // How many times to repeat the tests? We don't want to repeat them // when we are inside the subprocess of a death test. const int repeat = in_subprocess_for_death_test ? 1 : GTEST_FLAG(repeat); // Repeats forever if the repeat count is negative. const bool forever = repeat < 0; for (int i = 0; forever || i != repeat; i++) { // We want to preserve failures generated by ad-hoc test // assertions executed before RUN_ALL_TESTS(). ClearNonAdHocTestResult(); const TimeInMillis start = GetTimeInMillis(); // Shuffles test cases and tests if requested. if (has_tests_to_run && GTEST_FLAG(shuffle)) { random()->Reseed(random_seed_); // This should be done before calling OnTestIterationStart(), // such that a test event listener can see the actual test order // in the event. ShuffleTests(); } // Tells the unit test event listeners that the tests are about to start. repeater->OnTestIterationStart(*parent_, i); // Runs each test case if there is at least one test to run. if (has_tests_to_run) { // Sets up all environments beforehand. repeater->OnEnvironmentsSetUpStart(*parent_); ForEach(environments_, SetUpEnvironment); repeater->OnEnvironmentsSetUpEnd(*parent_); // Runs the tests only if there was no fatal failure during global // set-up. if (!Test::HasFatalFailure()) { for (int test_index = 0; test_index < total_test_case_count(); test_index++) { GetMutableTestCase(test_index)->Run(); } } // Tears down all environments in reverse order afterwards. repeater->OnEnvironmentsTearDownStart(*parent_); std::for_each(environments_.rbegin(), environments_.rend(), TearDownEnvironment); repeater->OnEnvironmentsTearDownEnd(*parent_); } elapsed_time_ = GetTimeInMillis() - start; // Tells the unit test event listener that the tests have just finished. repeater->OnTestIterationEnd(*parent_, i); // Gets the result and clears it. if (!Passed()) { failed = true; } // Restores the original test order after the iteration. This // allows the user to quickly repro a failure that happens in the // N-th iteration without repeating the first (N - 1) iterations. // This is not enclosed in "if (GTEST_FLAG(shuffle)) { ... }", in // case the user somehow changes the value of the flag somewhere // (it's always safe to unshuffle the tests). UnshuffleTests(); if (GTEST_FLAG(shuffle)) { // Picks a new random seed for each iteration. random_seed_ = GetNextRandomSeed(random_seed_); } } repeater->OnTestProgramEnd(*parent_); return !failed; } // Reads the GTEST_SHARD_STATUS_FILE environment variable, and creates the file // if the variable is present. If a file already exists at this location, this // function will write over it. If the variable is present, but the file cannot // be created, prints an error and exits. void WriteToShardStatusFileIfNeeded() { const char* const test_shard_file = posix::GetEnv(kTestShardStatusFile); if (test_shard_file != NULL) { FILE* const file = posix::FOpen(test_shard_file, "w"); if (file == NULL) { ColoredPrintf(COLOR_RED, "Could not write to the test shard status file \"%s\" " "specified by the %s environment variable.\n", test_shard_file, kTestShardStatusFile); fflush(stdout); exit(EXIT_FAILURE); } fclose(file); } } // Checks whether sharding is enabled by examining the relevant // environment variable values. If the variables are present, // but inconsistent (i.e., shard_index >= total_shards), prints // an error and exits. If in_subprocess_for_death_test, sharding is // disabled because it must only be applied to the original test // process. Otherwise, we could filter out death tests we intended to execute. bool ShouldShard(const char* total_shards_env, const char* shard_index_env, bool in_subprocess_for_death_test) { if (in_subprocess_for_death_test) { return false; } const Int32 total_shards = Int32FromEnvOrDie(total_shards_env, -1); const Int32 shard_index = Int32FromEnvOrDie(shard_index_env, -1); if (total_shards == -1 && shard_index == -1) { return false; } else if (total_shards == -1 && shard_index != -1) { const Message msg = Message() << "Invalid environment variables: you have " << kTestShardIndex << " = " << shard_index << ", but have left " << kTestTotalShards << " unset.\n"; ColoredPrintf(COLOR_RED, msg.GetString().c_str()); fflush(stdout); exit(EXIT_FAILURE); } else if (total_shards != -1 && shard_index == -1) { const Message msg = Message() << "Invalid environment variables: you have " << kTestTotalShards << " = " << total_shards << ", but have left " << kTestShardIndex << " unset.\n"; ColoredPrintf(COLOR_RED, msg.GetString().c_str()); fflush(stdout); exit(EXIT_FAILURE); } else if (shard_index < 0 || shard_index >= total_shards) { const Message msg = Message() << "Invalid environment variables: we require 0 <= " << kTestShardIndex << " < " << kTestTotalShards << ", but you have " << kTestShardIndex << "=" << shard_index << ", " << kTestTotalShards << "=" << total_shards << ".\n"; ColoredPrintf(COLOR_RED, msg.GetString().c_str()); fflush(stdout); exit(EXIT_FAILURE); } return total_shards > 1; } // Parses the environment variable var as an Int32. If it is unset, // returns default_val. If it is not an Int32, prints an error // and aborts. Int32 Int32FromEnvOrDie(const char* var, Int32 default_val) { const char* str_val = posix::GetEnv(var); if (str_val == NULL) { return default_val; } Int32 result; if (!ParseInt32(Message() << "The value of environment variable " << var, str_val, &result)) { exit(EXIT_FAILURE); } return result; } // Given the total number of shards, the shard index, and the test id, // returns true iff the test should be run on this shard. The test id is // some arbitrary but unique non-negative integer assigned to each test // method. Assumes that 0 <= shard_index < total_shards. bool ShouldRunTestOnShard(int total_shards, int shard_index, int test_id) { return (test_id % total_shards) == shard_index; } // Compares the name of each test with the user-specified filter to // decide whether the test should be run, then records the result in // each TestCase and TestInfo object. // If shard_tests == true, further filters tests based on sharding // variables in the environment - see // http://code.google.com/p/googletest/wiki/GoogleTestAdvancedGuide. // Returns the number of tests that should run. int UnitTestImpl::FilterTests(ReactionToSharding shard_tests) { const Int32 total_shards = shard_tests == HONOR_SHARDING_PROTOCOL ? Int32FromEnvOrDie(kTestTotalShards, -1) : -1; const Int32 shard_index = shard_tests == HONOR_SHARDING_PROTOCOL ? Int32FromEnvOrDie(kTestShardIndex, -1) : -1; // num_runnable_tests are the number of tests that will // run across all shards (i.e., match filter and are not disabled). // num_selected_tests are the number of tests to be run on // this shard. int num_runnable_tests = 0; int num_selected_tests = 0; for (size_t i = 0; i < test_cases_.size(); i++) { TestCase* const test_case = test_cases_[i]; const String &test_case_name = test_case->name(); test_case->set_should_run(false); for (size_t j = 0; j < test_case->test_info_list().size(); j++) { TestInfo* const test_info = test_case->test_info_list()[j]; const String test_name(test_info->name()); // A test is disabled if test case name or test name matches // kDisableTestFilter. const bool is_disabled = internal::UnitTestOptions::MatchesFilter(test_case_name, kDisableTestFilter) || internal::UnitTestOptions::MatchesFilter(test_name, kDisableTestFilter); test_info->is_disabled_ = is_disabled; const bool matches_filter = internal::UnitTestOptions::FilterMatchesTest(test_case_name, test_name); test_info->matches_filter_ = matches_filter; const bool is_runnable = (GTEST_FLAG(also_run_disabled_tests) || !is_disabled) && matches_filter; const bool is_selected = is_runnable && (shard_tests == IGNORE_SHARDING_PROTOCOL || ShouldRunTestOnShard(total_shards, shard_index, num_runnable_tests)); num_runnable_tests += is_runnable; num_selected_tests += is_selected; test_info->should_run_ = is_selected; test_case->set_should_run(test_case->should_run() || is_selected); } } return num_selected_tests; } // Prints the names of the tests matching the user-specified filter flag. void UnitTestImpl::ListTestsMatchingFilter() { for (size_t i = 0; i < test_cases_.size(); i++) { const TestCase* const test_case = test_cases_[i]; bool printed_test_case_name = false; for (size_t j = 0; j < test_case->test_info_list().size(); j++) { const TestInfo* const test_info = test_case->test_info_list()[j]; if (test_info->matches_filter_) { if (!printed_test_case_name) { printed_test_case_name = true; printf("%s.\n", test_case->name()); } printf(" %s\n", test_info->name()); } } } fflush(stdout); } // Sets the OS stack trace getter. // // Does nothing if the input and the current OS stack trace getter are // the same; otherwise, deletes the old getter and makes the input the // current getter. void UnitTestImpl::set_os_stack_trace_getter( OsStackTraceGetterInterface* getter) { if (os_stack_trace_getter_ != getter) { delete os_stack_trace_getter_; os_stack_trace_getter_ = getter; } } // Returns the current OS stack trace getter if it is not NULL; // otherwise, creates an OsStackTraceGetter, makes it the current // getter, and returns it. OsStackTraceGetterInterface* UnitTestImpl::os_stack_trace_getter() { if (os_stack_trace_getter_ == NULL) { os_stack_trace_getter_ = new OsStackTraceGetter; } return os_stack_trace_getter_; } // Returns the TestResult for the test that's currently running, or // the TestResult for the ad hoc test if no test is running. TestResult* UnitTestImpl::current_test_result() { return current_test_info_ ? &(current_test_info_->result_) : &ad_hoc_test_result_; } // Shuffles all test cases, and the tests within each test case, // making sure that death tests are still run first. void UnitTestImpl::ShuffleTests() { // Shuffles the death test cases. ShuffleRange(random(), 0, last_death_test_case_ + 1, &test_case_indices_); // Shuffles the non-death test cases. ShuffleRange(random(), last_death_test_case_ + 1, static_cast(test_cases_.size()), &test_case_indices_); // Shuffles the tests inside each test case. for (size_t i = 0; i < test_cases_.size(); i++) { test_cases_[i]->ShuffleTests(random()); } } // Restores the test cases and tests to their order before the first shuffle. void UnitTestImpl::UnshuffleTests() { for (size_t i = 0; i < test_cases_.size(); i++) { // Unshuffles the tests in each test case. test_cases_[i]->UnshuffleTests(); // Resets the index of each test case. test_case_indices_[i] = static_cast(i); } } // Returns the current OS stack trace as a String. // // The maximum number of stack frames to be included is specified by // the gtest_stack_trace_depth flag. The skip_count parameter // specifies the number of top frames to be skipped, which doesn't // count against the number of frames to be included. // // For example, if Foo() calls Bar(), which in turn calls // GetCurrentOsStackTraceExceptTop(..., 1), Foo() will be included in // the trace but Bar() and GetCurrentOsStackTraceExceptTop() won't. String GetCurrentOsStackTraceExceptTop(UnitTest* /*unit_test*/, int skip_count) { // We pass skip_count + 1 to skip this wrapper function in addition // to what the user really wants to skip. return GetUnitTestImpl()->CurrentOsStackTraceExceptTop(skip_count + 1); } // Used by the GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_ macro to // suppress unreachable code warnings. namespace { class ClassUniqueToAlwaysTrue {}; } bool IsTrue(bool condition) { return condition; } bool AlwaysTrue() { #if GTEST_HAS_EXCEPTIONS // This condition is always false so AlwaysTrue() never actually throws, // but it makes the compiler think that it may throw. if (IsTrue(false)) throw ClassUniqueToAlwaysTrue(); #endif // GTEST_HAS_EXCEPTIONS return true; } // If *pstr starts with the given prefix, modifies *pstr to be right // past the prefix and returns true; otherwise leaves *pstr unchanged // and returns false. None of pstr, *pstr, and prefix can be NULL. bool SkipPrefix(const char* prefix, const char** pstr) { const size_t prefix_len = strlen(prefix); if (strncmp(*pstr, prefix, prefix_len) == 0) { *pstr += prefix_len; return true; } return false; } // Parses a string as a command line flag. The string should have // the format "--flag=value". When def_optional is true, the "=value" // part can be omitted. // // Returns the value of the flag, or NULL if the parsing failed. const char* ParseFlagValue(const char* str, const char* flag, bool def_optional) { // str and flag must not be NULL. if (str == NULL || flag == NULL) return NULL; // The flag must start with "--" followed by GTEST_FLAG_PREFIX_. const String flag_str = String::Format("--%s%s", GTEST_FLAG_PREFIX_, flag); const size_t flag_len = flag_str.length(); if (strncmp(str, flag_str.c_str(), flag_len) != 0) return NULL; // Skips the flag name. const char* flag_end = str + flag_len; // When def_optional is true, it's OK to not have a "=value" part. if (def_optional && (flag_end[0] == '\0')) { return flag_end; } // If def_optional is true and there are more characters after the // flag name, or if def_optional is false, there must be a '=' after // the flag name. if (flag_end[0] != '=') return NULL; // Returns the string after "=". return flag_end + 1; } // Parses a string for a bool flag, in the form of either // "--flag=value" or "--flag". // // In the former case, the value is taken as true as long as it does // not start with '0', 'f', or 'F'. // // In the latter case, the value is taken as true. // // On success, stores the value of the flag in *value, and returns // true. On failure, returns false without changing *value. bool ParseBoolFlag(const char* str, const char* flag, bool* value) { // Gets the value of the flag as a string. const char* const value_str = ParseFlagValue(str, flag, true); // Aborts if the parsing failed. if (value_str == NULL) return false; // Converts the string value to a bool. *value = !(*value_str == '0' || *value_str == 'f' || *value_str == 'F'); return true; } // Parses a string for an Int32 flag, in the form of // "--flag=value". // // On success, stores the value of the flag in *value, and returns // true. On failure, returns false without changing *value. bool ParseInt32Flag(const char* str, const char* flag, Int32* value) { // Gets the value of the flag as a string. const char* const value_str = ParseFlagValue(str, flag, false); // Aborts if the parsing failed. if (value_str == NULL) return false; // Sets *value to the value of the flag. return ParseInt32(Message() << "The value of flag --" << flag, value_str, value); } // Parses a string for a string flag, in the form of // "--flag=value". // // On success, stores the value of the flag in *value, and returns // true. On failure, returns false without changing *value. bool ParseStringFlag(const char* str, const char* flag, String* value) { // Gets the value of the flag as a string. const char* const value_str = ParseFlagValue(str, flag, false); // Aborts if the parsing failed. if (value_str == NULL) return false; // Sets *value to the value of the flag. *value = value_str; return true; } // Determines whether a string has a prefix that Google Test uses for its // flags, i.e., starts with GTEST_FLAG_PREFIX_ or GTEST_FLAG_PREFIX_DASH_. // If Google Test detects that a command line flag has its prefix but is not // recognized, it will print its help message. Flags starting with // GTEST_INTERNAL_PREFIX_ followed by "internal_" are considered Google Test // internal flags and do not trigger the help message. static bool HasGoogleTestFlagPrefix(const char* str) { return (SkipPrefix("--", &str) || SkipPrefix("-", &str) || SkipPrefix("/", &str)) && !SkipPrefix(GTEST_FLAG_PREFIX_ "internal_", &str) && (SkipPrefix(GTEST_FLAG_PREFIX_, &str) || SkipPrefix(GTEST_FLAG_PREFIX_DASH_, &str)); } // Prints a string containing code-encoded text. The following escape // sequences can be used in the string to control the text color: // // @@ prints a single '@' character. // @R changes the color to red. // @G changes the color to green. // @Y changes the color to yellow. // @D changes to the default terminal text color. // // TODO(wan@google.com): Write tests for this once we add stdout // capturing to Google Test. static void PrintColorEncoded(const char* str) { GTestColor color = COLOR_DEFAULT; // The current color. // Conceptually, we split the string into segments divided by escape // sequences. Then we print one segment at a time. At the end of // each iteration, the str pointer advances to the beginning of the // next segment. for (;;) { const char* p = strchr(str, '@'); if (p == NULL) { ColoredPrintf(color, "%s", str); return; } ColoredPrintf(color, "%s", String(str, p - str).c_str()); const char ch = p[1]; str = p + 2; if (ch == '@') { ColoredPrintf(color, "@"); } else if (ch == 'D') { color = COLOR_DEFAULT; } else if (ch == 'R') { color = COLOR_RED; } else if (ch == 'G') { color = COLOR_GREEN; } else if (ch == 'Y') { color = COLOR_YELLOW; } else { --str; } } } static const char kColorEncodedHelpMessage[] = "This program contains tests written using " GTEST_NAME_ ". You can use the\n" "following command line flags to control its behavior:\n" "\n" "Test Selection:\n" " @G--" GTEST_FLAG_PREFIX_ "list_tests@D\n" " List the names of all tests instead of running them. The name of\n" " TEST(Foo, Bar) is \"Foo.Bar\".\n" " @G--" GTEST_FLAG_PREFIX_ "filter=@YPOSTIVE_PATTERNS" "[@G-@YNEGATIVE_PATTERNS]@D\n" " Run only the tests whose name matches one of the positive patterns but\n" " none of the negative patterns. '?' matches any single character; '*'\n" " matches any substring; ':' separates two patterns.\n" " @G--" GTEST_FLAG_PREFIX_ "also_run_disabled_tests@D\n" " Run all disabled tests too.\n" "\n" "Test Execution:\n" " @G--" GTEST_FLAG_PREFIX_ "repeat=@Y[COUNT]@D\n" " Run the tests repeatedly; use a negative count to repeat forever.\n" " @G--" GTEST_FLAG_PREFIX_ "shuffle@D\n" " Randomize tests' orders on every iteration.\n" " @G--" GTEST_FLAG_PREFIX_ "random_seed=@Y[NUMBER]@D\n" " Random number seed to use for shuffling test orders (between 1 and\n" " 99999, or 0 to use a seed based on the current time).\n" "\n" "Test Output:\n" " @G--" GTEST_FLAG_PREFIX_ "color=@Y(@Gyes@Y|@Gno@Y|@Gauto@Y)@D\n" " Enable/disable colored output. The default is @Gauto@D.\n" " -@G-" GTEST_FLAG_PREFIX_ "print_time=0@D\n" " Don't print the elapsed time of each test.\n" " @G--" GTEST_FLAG_PREFIX_ "output=xml@Y[@G:@YDIRECTORY_PATH@G" GTEST_PATH_SEP_ "@Y|@G:@YFILE_PATH]@D\n" " Generate an XML report in the given directory or with the given file\n" " name. @YFILE_PATH@D defaults to @Gtest_details.xml@D.\n" #if GTEST_CAN_STREAM_RESULTS_ " @G--" GTEST_FLAG_PREFIX_ "stream_result_to=@YHOST@G:@YPORT@D\n" " Stream test results to the given server.\n" #endif // GTEST_CAN_STREAM_RESULTS_ "\n" "Assertion Behavior:\n" #if GTEST_HAS_DEATH_TEST && !GTEST_OS_WINDOWS " @G--" GTEST_FLAG_PREFIX_ "death_test_style=@Y(@Gfast@Y|@Gthreadsafe@Y)@D\n" " Set the default death test style.\n" #endif // GTEST_HAS_DEATH_TEST && !GTEST_OS_WINDOWS " @G--" GTEST_FLAG_PREFIX_ "break_on_failure@D\n" " Turn assertion failures into debugger break-points.\n" " @G--" GTEST_FLAG_PREFIX_ "throw_on_failure@D\n" " Turn assertion failures into C++ exceptions.\n" " @G--" GTEST_FLAG_PREFIX_ "catch_exceptions=0@D\n" " Do not report exceptions as test failures. Instead, allow them\n" " to crash the program or throw a pop-up (on Windows).\n" "\n" "Except for @G--" GTEST_FLAG_PREFIX_ "list_tests@D, you can alternatively set " "the corresponding\n" "environment variable of a flag (all letters in upper-case). For example, to\n" "disable colored text output, you can either specify @G--" GTEST_FLAG_PREFIX_ "color=no@D or set\n" "the @G" GTEST_FLAG_PREFIX_UPPER_ "COLOR@D environment variable to @Gno@D.\n" "\n" "For more information, please read the " GTEST_NAME_ " documentation at\n" "@G" GTEST_PROJECT_URL_ "@D. If you find a bug in " GTEST_NAME_ "\n" "(not one in your own code or tests), please report it to\n" "@G<" GTEST_DEV_EMAIL_ ">@D.\n"; // Parses the command line for Google Test flags, without initializing // other parts of Google Test. The type parameter CharType can be // instantiated to either char or wchar_t. template void ParseGoogleTestFlagsOnlyImpl(int* argc, CharType** argv) { for (int i = 1; i < *argc; i++) { const String arg_string = StreamableToString(argv[i]); const char* const arg = arg_string.c_str(); using internal::ParseBoolFlag; using internal::ParseInt32Flag; using internal::ParseStringFlag; // Do we see a Google Test flag? if (ParseBoolFlag(arg, kAlsoRunDisabledTestsFlag, >EST_FLAG(also_run_disabled_tests)) || ParseBoolFlag(arg, kBreakOnFailureFlag, >EST_FLAG(break_on_failure)) || ParseBoolFlag(arg, kCatchExceptionsFlag, >EST_FLAG(catch_exceptions)) || ParseStringFlag(arg, kColorFlag, >EST_FLAG(color)) || ParseStringFlag(arg, kDeathTestStyleFlag, >EST_FLAG(death_test_style)) || ParseBoolFlag(arg, kDeathTestUseFork, >EST_FLAG(death_test_use_fork)) || ParseStringFlag(arg, kFilterFlag, >EST_FLAG(filter)) || ParseStringFlag(arg, kInternalRunDeathTestFlag, >EST_FLAG(internal_run_death_test)) || ParseBoolFlag(arg, kListTestsFlag, >EST_FLAG(list_tests)) || ParseStringFlag(arg, kOutputFlag, >EST_FLAG(output)) || ParseBoolFlag(arg, kPrintTimeFlag, >EST_FLAG(print_time)) || ParseInt32Flag(arg, kRandomSeedFlag, >EST_FLAG(random_seed)) || ParseInt32Flag(arg, kRepeatFlag, >EST_FLAG(repeat)) || ParseBoolFlag(arg, kShuffleFlag, >EST_FLAG(shuffle)) || ParseInt32Flag(arg, kStackTraceDepthFlag, >EST_FLAG(stack_trace_depth)) || ParseStringFlag(arg, kStreamResultToFlag, >EST_FLAG(stream_result_to)) || ParseBoolFlag(arg, kThrowOnFailureFlag, >EST_FLAG(throw_on_failure)) ) { // Yes. Shift the remainder of the argv list left by one. Note // that argv has (*argc + 1) elements, the last one always being // NULL. The following loop moves the trailing NULL element as // well. for (int j = i; j != *argc; j++) { argv[j] = argv[j + 1]; } // Decrements the argument count. (*argc)--; // We also need to decrement the iterator as we just removed // an element. i--; } else if (arg_string == "--help" || arg_string == "-h" || arg_string == "-?" || arg_string == "/?" || HasGoogleTestFlagPrefix(arg)) { // Both help flag and unrecognized Google Test flags (excluding // internal ones) trigger help display. g_help_flag = true; } } if (g_help_flag) { // We print the help here instead of in RUN_ALL_TESTS(), as the // latter may not be called at all if the user is using Google // Test with another testing framework. PrintColorEncoded(kColorEncodedHelpMessage); } } // Parses the command line for Google Test flags, without initializing // other parts of Google Test. void ParseGoogleTestFlagsOnly(int* argc, char** argv) { ParseGoogleTestFlagsOnlyImpl(argc, argv); } void ParseGoogleTestFlagsOnly(int* argc, wchar_t** argv) { ParseGoogleTestFlagsOnlyImpl(argc, argv); } // The internal implementation of InitGoogleTest(). // // The type parameter CharType can be instantiated to either char or // wchar_t. template void InitGoogleTestImpl(int* argc, CharType** argv) { g_init_gtest_count++; // We don't want to run the initialization code twice. if (g_init_gtest_count != 1) return; if (*argc <= 0) return; internal::g_executable_path = internal::StreamableToString(argv[0]); #if GTEST_HAS_DEATH_TEST g_argvs.clear(); for (int i = 0; i != *argc; i++) { g_argvs.push_back(StreamableToString(argv[i])); } #endif // GTEST_HAS_DEATH_TEST ParseGoogleTestFlagsOnly(argc, argv); GetUnitTestImpl()->PostFlagParsingInit(); } } // namespace internal // Initializes Google Test. This must be called before calling // RUN_ALL_TESTS(). In particular, it parses a command line for the // flags that Google Test recognizes. Whenever a Google Test flag is // seen, it is removed from argv, and *argc is decremented. // // No value is returned. Instead, the Google Test flag variables are // updated. // // Calling the function for the second time has no user-visible effect. void InitGoogleTest(int* argc, char** argv) { internal::InitGoogleTestImpl(argc, argv); } // This overloaded version can be used in Windows programs compiled in // UNICODE mode. void InitGoogleTest(int* argc, wchar_t** argv) { internal::InitGoogleTestImpl(argc, argv); } } // namespace testing // Copyright 2005, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan), vladl@google.com (Vlad Losev) // // This file implements death tests. #if GTEST_HAS_DEATH_TEST # if GTEST_OS_MAC # include # endif // GTEST_OS_MAC # include # include # include # include # if GTEST_OS_WINDOWS # include # else # include # include # endif // GTEST_OS_WINDOWS #endif // GTEST_HAS_DEATH_TEST // Indicates that this translation unit is part of Google Test's // implementation. It must come before gtest-internal-inl.h is // included, or there will be a compiler error. This trick is to // prevent a user from accidentally including gtest-internal-inl.h in // his code. #define GTEST_IMPLEMENTATION_ 1 #undef GTEST_IMPLEMENTATION_ namespace testing { // Constants. // The default death test style. static const char kDefaultDeathTestStyle[] = "fast"; GTEST_DEFINE_string_( death_test_style, internal::StringFromGTestEnv("death_test_style", kDefaultDeathTestStyle), "Indicates how to run a death test in a forked child process: " "\"threadsafe\" (child process re-executes the test binary " "from the beginning, running only the specific death test) or " "\"fast\" (child process runs the death test immediately " "after forking)."); GTEST_DEFINE_bool_( death_test_use_fork, internal::BoolFromGTestEnv("death_test_use_fork", false), "Instructs to use fork()/_exit() instead of clone() in death tests. " "Ignored and always uses fork() on POSIX systems where clone() is not " "implemented. Useful when running under valgrind or similar tools if " "those do not support clone(). Valgrind 3.3.1 will just fail if " "it sees an unsupported combination of clone() flags. " "It is not recommended to use this flag w/o valgrind though it will " "work in 99% of the cases. Once valgrind is fixed, this flag will " "most likely be removed."); namespace internal { GTEST_DEFINE_string_( internal_run_death_test, "", "Indicates the file, line number, temporal index of " "the single death test to run, and a file descriptor to " "which a success code may be sent, all separated by " "colons. This flag is specified if and only if the current " "process is a sub-process launched for running a thread-safe " "death test. FOR INTERNAL USE ONLY."); } // namespace internal #if GTEST_HAS_DEATH_TEST // ExitedWithCode constructor. ExitedWithCode::ExitedWithCode(int exit_code) : exit_code_(exit_code) { } // ExitedWithCode function-call operator. bool ExitedWithCode::operator()(int exit_status) const { # if GTEST_OS_WINDOWS return exit_status == exit_code_; # else return WIFEXITED(exit_status) && WEXITSTATUS(exit_status) == exit_code_; # endif // GTEST_OS_WINDOWS } # if !GTEST_OS_WINDOWS // KilledBySignal constructor. KilledBySignal::KilledBySignal(int signum) : signum_(signum) { } // KilledBySignal function-call operator. bool KilledBySignal::operator()(int exit_status) const { return WIFSIGNALED(exit_status) && WTERMSIG(exit_status) == signum_; } # endif // !GTEST_OS_WINDOWS namespace internal { // Utilities needed for death tests. // Generates a textual description of a given exit code, in the format // specified by wait(2). static String ExitSummary(int exit_code) { Message m; # if GTEST_OS_WINDOWS m << "Exited with exit status " << exit_code; # else if (WIFEXITED(exit_code)) { m << "Exited with exit status " << WEXITSTATUS(exit_code); } else if (WIFSIGNALED(exit_code)) { m << "Terminated by signal " << WTERMSIG(exit_code); } # ifdef WCOREDUMP if (WCOREDUMP(exit_code)) { m << " (core dumped)"; } # endif # endif // GTEST_OS_WINDOWS return m.GetString(); } // Returns true if exit_status describes a process that was terminated // by a signal, or exited normally with a nonzero exit code. bool ExitedUnsuccessfully(int exit_status) { return !ExitedWithCode(0)(exit_status); } # if !GTEST_OS_WINDOWS // Generates a textual failure message when a death test finds more than // one thread running, or cannot determine the number of threads, prior // to executing the given statement. It is the responsibility of the // caller not to pass a thread_count of 1. static String DeathTestThreadWarning(size_t thread_count) { Message msg; msg << "Death tests use fork(), which is unsafe particularly" << " in a threaded context. For this test, " << GTEST_NAME_ << " "; if (thread_count == 0) msg << "couldn't detect the number of threads."; else msg << "detected " << thread_count << " threads."; return msg.GetString(); } # endif // !GTEST_OS_WINDOWS // Flag characters for reporting a death test that did not die. static const char kDeathTestLived = 'L'; static const char kDeathTestReturned = 'R'; static const char kDeathTestThrew = 'T'; static const char kDeathTestInternalError = 'I'; // An enumeration describing all of the possible ways that a death test can // conclude. DIED means that the process died while executing the test // code; LIVED means that process lived beyond the end of the test code; // RETURNED means that the test statement attempted to execute a return // statement, which is not allowed; THREW means that the test statement // returned control by throwing an exception. IN_PROGRESS means the test // has not yet concluded. // TODO(vladl@google.com): Unify names and possibly values for // AbortReason, DeathTestOutcome, and flag characters above. enum DeathTestOutcome { IN_PROGRESS, DIED, LIVED, RETURNED, THREW }; // Routine for aborting the program which is safe to call from an // exec-style death test child process, in which case the error // message is propagated back to the parent process. Otherwise, the // message is simply printed to stderr. In either case, the program // then exits with status 1. void DeathTestAbort(const String& message) { // On a POSIX system, this function may be called from a threadsafe-style // death test child process, which operates on a very small stack. Use // the heap for any additional non-minuscule memory requirements. const InternalRunDeathTestFlag* const flag = GetUnitTestImpl()->internal_run_death_test_flag(); if (flag != NULL) { FILE* parent = posix::FDOpen(flag->write_fd(), "w"); fputc(kDeathTestInternalError, parent); fprintf(parent, "%s", message.c_str()); fflush(parent); _exit(1); } else { fprintf(stderr, "%s", message.c_str()); fflush(stderr); posix::Abort(); } } // A replacement for CHECK that calls DeathTestAbort if the assertion // fails. # define GTEST_DEATH_TEST_CHECK_(expression) \ do { \ if (!::testing::internal::IsTrue(expression)) { \ DeathTestAbort(::testing::internal::String::Format( \ "CHECK failed: File %s, line %d: %s", \ __FILE__, __LINE__, #expression)); \ } \ } while (::testing::internal::AlwaysFalse()) // This macro is similar to GTEST_DEATH_TEST_CHECK_, but it is meant for // evaluating any system call that fulfills two conditions: it must return // -1 on failure, and set errno to EINTR when it is interrupted and // should be tried again. The macro expands to a loop that repeatedly // evaluates the expression as long as it evaluates to -1 and sets // errno to EINTR. If the expression evaluates to -1 but errno is // something other than EINTR, DeathTestAbort is called. # define GTEST_DEATH_TEST_CHECK_SYSCALL_(expression) \ do { \ int gtest_retval; \ do { \ gtest_retval = (expression); \ } while (gtest_retval == -1 && errno == EINTR); \ if (gtest_retval == -1) { \ DeathTestAbort(::testing::internal::String::Format( \ "CHECK failed: File %s, line %d: %s != -1", \ __FILE__, __LINE__, #expression)); \ } \ } while (::testing::internal::AlwaysFalse()) // Returns the message describing the last system error in errno. String GetLastErrnoDescription() { return String(errno == 0 ? "" : posix::StrError(errno)); } // This is called from a death test parent process to read a failure // message from the death test child process and log it with the FATAL // severity. On Windows, the message is read from a pipe handle. On other // platforms, it is read from a file descriptor. static void FailFromInternalError(int fd) { Message error; char buffer[256]; int num_read; do { while ((num_read = posix::Read(fd, buffer, 255)) > 0) { buffer[num_read] = '\0'; error << buffer; } } while (num_read == -1 && errno == EINTR); if (num_read == 0) { GTEST_LOG_(FATAL) << error.GetString(); } else { const int last_error = errno; GTEST_LOG_(FATAL) << "Error while reading death test internal: " << GetLastErrnoDescription() << " [" << last_error << "]"; } } // Death test constructor. Increments the running death test count // for the current test. DeathTest::DeathTest() { TestInfo* const info = GetUnitTestImpl()->current_test_info(); if (info == NULL) { DeathTestAbort("Cannot run a death test outside of a TEST or " "TEST_F construct"); } } // Creates and returns a death test by dispatching to the current // death test factory. bool DeathTest::Create(const char* statement, const RE* regex, const char* file, int line, DeathTest** test) { return GetUnitTestImpl()->death_test_factory()->Create( statement, regex, file, line, test); } const char* DeathTest::LastMessage() { return last_death_test_message_.c_str(); } void DeathTest::set_last_death_test_message(const String& message) { last_death_test_message_ = message; } String DeathTest::last_death_test_message_; // Provides cross platform implementation for some death functionality. class DeathTestImpl : public DeathTest { protected: DeathTestImpl(const char* a_statement, const RE* a_regex) : statement_(a_statement), regex_(a_regex), spawned_(false), status_(-1), outcome_(IN_PROGRESS), read_fd_(-1), write_fd_(-1) {} // read_fd_ is expected to be closed and cleared by a derived class. ~DeathTestImpl() { GTEST_DEATH_TEST_CHECK_(read_fd_ == -1); } void Abort(AbortReason reason); virtual bool Passed(bool status_ok); const char* statement() const { return statement_; } const RE* regex() const { return regex_; } bool spawned() const { return spawned_; } void set_spawned(bool is_spawned) { spawned_ = is_spawned; } int status() const { return status_; } void set_status(int a_status) { status_ = a_status; } DeathTestOutcome outcome() const { return outcome_; } void set_outcome(DeathTestOutcome an_outcome) { outcome_ = an_outcome; } int read_fd() const { return read_fd_; } void set_read_fd(int fd) { read_fd_ = fd; } int write_fd() const { return write_fd_; } void set_write_fd(int fd) { write_fd_ = fd; } // Called in the parent process only. Reads the result code of the death // test child process via a pipe, interprets it to set the outcome_ // member, and closes read_fd_. Outputs diagnostics and terminates in // case of unexpected codes. void ReadAndInterpretStatusByte(); private: // The textual content of the code this object is testing. This class // doesn't own this string and should not attempt to delete it. const char* const statement_; // The regular expression which test output must match. DeathTestImpl // doesn't own this object and should not attempt to delete it. const RE* const regex_; // True if the death test child process has been successfully spawned. bool spawned_; // The exit status of the child process. int status_; // How the death test concluded. DeathTestOutcome outcome_; // Descriptor to the read end of the pipe to the child process. It is // always -1 in the child process. The child keeps its write end of the // pipe in write_fd_. int read_fd_; // Descriptor to the child's write end of the pipe to the parent process. // It is always -1 in the parent process. The parent keeps its end of the // pipe in read_fd_. int write_fd_; }; // Called in the parent process only. Reads the result code of the death // test child process via a pipe, interprets it to set the outcome_ // member, and closes read_fd_. Outputs diagnostics and terminates in // case of unexpected codes. void DeathTestImpl::ReadAndInterpretStatusByte() { char flag; int bytes_read; // The read() here blocks until data is available (signifying the // failure of the death test) or until the pipe is closed (signifying // its success), so it's okay to call this in the parent before // the child process has exited. do { bytes_read = posix::Read(read_fd(), &flag, 1); } while (bytes_read == -1 && errno == EINTR); if (bytes_read == 0) { set_outcome(DIED); } else if (bytes_read == 1) { switch (flag) { case kDeathTestReturned: set_outcome(RETURNED); break; case kDeathTestThrew: set_outcome(THREW); break; case kDeathTestLived: set_outcome(LIVED); break; case kDeathTestInternalError: FailFromInternalError(read_fd()); // Does not return. break; default: GTEST_LOG_(FATAL) << "Death test child process reported " << "unexpected status byte (" << static_cast(flag) << ")"; } } else { GTEST_LOG_(FATAL) << "Read from death test child process failed: " << GetLastErrnoDescription(); } GTEST_DEATH_TEST_CHECK_SYSCALL_(posix::Close(read_fd())); set_read_fd(-1); } // Signals that the death test code which should have exited, didn't. // Should be called only in a death test child process. // Writes a status byte to the child's status file descriptor, then // calls _exit(1). void DeathTestImpl::Abort(AbortReason reason) { // The parent process considers the death test to be a failure if // it finds any data in our pipe. So, here we write a single flag byte // to the pipe, then exit. const char status_ch = reason == TEST_DID_NOT_DIE ? kDeathTestLived : reason == TEST_THREW_EXCEPTION ? kDeathTestThrew : kDeathTestReturned; GTEST_DEATH_TEST_CHECK_SYSCALL_(posix::Write(write_fd(), &status_ch, 1)); // We are leaking the descriptor here because on some platforms (i.e., // when built as Windows DLL), destructors of global objects will still // run after calling _exit(). On such systems, write_fd_ will be // indirectly closed from the destructor of UnitTestImpl, causing double // close if it is also closed here. On debug configurations, double close // may assert. As there are no in-process buffers to flush here, we are // relying on the OS to close the descriptor after the process terminates // when the destructors are not run. _exit(1); // Exits w/o any normal exit hooks (we were supposed to crash) } // Returns an indented copy of stderr output for a death test. // This makes distinguishing death test output lines from regular log lines // much easier. static ::std::string FormatDeathTestOutput(const ::std::string& output) { ::std::string ret; for (size_t at = 0; ; ) { const size_t line_end = output.find('\n', at); ret += "[ DEATH ] "; if (line_end == ::std::string::npos) { ret += output.substr(at); break; } ret += output.substr(at, line_end + 1 - at); at = line_end + 1; } return ret; } // Assesses the success or failure of a death test, using both private // members which have previously been set, and one argument: // // Private data members: // outcome: An enumeration describing how the death test // concluded: DIED, LIVED, THREW, or RETURNED. The death test // fails in the latter three cases. // status: The exit status of the child process. On *nix, it is in the // in the format specified by wait(2). On Windows, this is the // value supplied to the ExitProcess() API or a numeric code // of the exception that terminated the program. // regex: A regular expression object to be applied to // the test's captured standard error output; the death test // fails if it does not match. // // Argument: // status_ok: true if exit_status is acceptable in the context of // this particular death test, which fails if it is false // // Returns true iff all of the above conditions are met. Otherwise, the // first failing condition, in the order given above, is the one that is // reported. Also sets the last death test message string. bool DeathTestImpl::Passed(bool status_ok) { if (!spawned()) return false; const String error_message = GetCapturedStderr(); bool success = false; Message buffer; buffer << "Death test: " << statement() << "\n"; switch (outcome()) { case LIVED: buffer << " Result: failed to die.\n" << " Error msg:\n" << FormatDeathTestOutput(error_message); break; case THREW: buffer << " Result: threw an exception.\n" << " Error msg:\n" << FormatDeathTestOutput(error_message); break; case RETURNED: buffer << " Result: illegal return in test statement.\n" << " Error msg:\n" << FormatDeathTestOutput(error_message); break; case DIED: if (status_ok) { const bool matched = RE::PartialMatch(error_message.c_str(), *regex()); if (matched) { success = true; } else { buffer << " Result: died but not with expected error.\n" << " Expected: " << regex()->pattern() << "\n" << "Actual msg:\n" << FormatDeathTestOutput(error_message); } } else { buffer << " Result: died but not with expected exit code:\n" << " " << ExitSummary(status()) << "\n" << "Actual msg:\n" << FormatDeathTestOutput(error_message); } break; case IN_PROGRESS: default: GTEST_LOG_(FATAL) << "DeathTest::Passed somehow called before conclusion of test"; } DeathTest::set_last_death_test_message(buffer.GetString()); return success; } # if GTEST_OS_WINDOWS // WindowsDeathTest implements death tests on Windows. Due to the // specifics of starting new processes on Windows, death tests there are // always threadsafe, and Google Test considers the // --gtest_death_test_style=fast setting to be equivalent to // --gtest_death_test_style=threadsafe there. // // A few implementation notes: Like the Linux version, the Windows // implementation uses pipes for child-to-parent communication. But due to // the specifics of pipes on Windows, some extra steps are required: // // 1. The parent creates a communication pipe and stores handles to both // ends of it. // 2. The parent starts the child and provides it with the information // necessary to acquire the handle to the write end of the pipe. // 3. The child acquires the write end of the pipe and signals the parent // using a Windows event. // 4. Now the parent can release the write end of the pipe on its side. If // this is done before step 3, the object's reference count goes down to // 0 and it is destroyed, preventing the child from acquiring it. The // parent now has to release it, or read operations on the read end of // the pipe will not return when the child terminates. // 5. The parent reads child's output through the pipe (outcome code and // any possible error messages) from the pipe, and its stderr and then // determines whether to fail the test. // // Note: to distinguish Win32 API calls from the local method and function // calls, the former are explicitly resolved in the global namespace. // class WindowsDeathTest : public DeathTestImpl { public: WindowsDeathTest(const char* a_statement, const RE* a_regex, const char* file, int line) : DeathTestImpl(a_statement, a_regex), file_(file), line_(line) {} // All of these virtual functions are inherited from DeathTest. virtual int Wait(); virtual TestRole AssumeRole(); private: // The name of the file in which the death test is located. const char* const file_; // The line number on which the death test is located. const int line_; // Handle to the write end of the pipe to the child process. AutoHandle write_handle_; // Child process handle. AutoHandle child_handle_; // Event the child process uses to signal the parent that it has // acquired the handle to the write end of the pipe. After seeing this // event the parent can release its own handles to make sure its // ReadFile() calls return when the child terminates. AutoHandle event_handle_; }; // Waits for the child in a death test to exit, returning its exit // status, or 0 if no child process exists. As a side effect, sets the // outcome data member. int WindowsDeathTest::Wait() { if (!spawned()) return 0; // Wait until the child either signals that it has acquired the write end // of the pipe or it dies. const HANDLE wait_handles[2] = { child_handle_.Get(), event_handle_.Get() }; switch (::WaitForMultipleObjects(2, wait_handles, FALSE, // Waits for any of the handles. INFINITE)) { case WAIT_OBJECT_0: case WAIT_OBJECT_0 + 1: break; default: GTEST_DEATH_TEST_CHECK_(false); // Should not get here. } // The child has acquired the write end of the pipe or exited. // We release the handle on our side and continue. write_handle_.Reset(); event_handle_.Reset(); ReadAndInterpretStatusByte(); // Waits for the child process to exit if it haven't already. This // returns immediately if the child has already exited, regardless of // whether previous calls to WaitForMultipleObjects synchronized on this // handle or not. GTEST_DEATH_TEST_CHECK_( WAIT_OBJECT_0 == ::WaitForSingleObject(child_handle_.Get(), INFINITE)); DWORD status_code; GTEST_DEATH_TEST_CHECK_( ::GetExitCodeProcess(child_handle_.Get(), &status_code) != FALSE); child_handle_.Reset(); set_status(static_cast(status_code)); return status(); } // The AssumeRole process for a Windows death test. It creates a child // process with the same executable as the current process to run the // death test. The child process is given the --gtest_filter and // --gtest_internal_run_death_test flags such that it knows to run the // current death test only. DeathTest::TestRole WindowsDeathTest::AssumeRole() { const UnitTestImpl* const impl = GetUnitTestImpl(); const InternalRunDeathTestFlag* const flag = impl->internal_run_death_test_flag(); const TestInfo* const info = impl->current_test_info(); const int death_test_index = info->result()->death_test_count(); if (flag != NULL) { // ParseInternalRunDeathTestFlag() has performed all the necessary // processing. set_write_fd(flag->write_fd()); return EXECUTE_TEST; } // WindowsDeathTest uses an anonymous pipe to communicate results of // a death test. SECURITY_ATTRIBUTES handles_are_inheritable = { sizeof(SECURITY_ATTRIBUTES), NULL, TRUE }; HANDLE read_handle, write_handle; GTEST_DEATH_TEST_CHECK_( ::CreatePipe(&read_handle, &write_handle, &handles_are_inheritable, 0) // Default buffer size. != FALSE); set_read_fd(::_open_osfhandle(reinterpret_cast(read_handle), O_RDONLY)); write_handle_.Reset(write_handle); event_handle_.Reset(::CreateEvent( &handles_are_inheritable, TRUE, // The event will automatically reset to non-signaled state. FALSE, // The initial state is non-signalled. NULL)); // The even is unnamed. GTEST_DEATH_TEST_CHECK_(event_handle_.Get() != NULL); const String filter_flag = String::Format("--%s%s=%s.%s", GTEST_FLAG_PREFIX_, kFilterFlag, info->test_case_name(), info->name()); const String internal_flag = String::Format( "--%s%s=%s|%d|%d|%u|%Iu|%Iu", GTEST_FLAG_PREFIX_, kInternalRunDeathTestFlag, file_, line_, death_test_index, static_cast(::GetCurrentProcessId()), // size_t has the same with as pointers on both 32-bit and 64-bit // Windows platforms. // See http://msdn.microsoft.com/en-us/library/tcxf1dw6.aspx. reinterpret_cast(write_handle), reinterpret_cast(event_handle_.Get())); char executable_path[_MAX_PATH + 1]; // NOLINT GTEST_DEATH_TEST_CHECK_( _MAX_PATH + 1 != ::GetModuleFileNameA(NULL, executable_path, _MAX_PATH)); String command_line = String::Format("%s %s \"%s\"", ::GetCommandLineA(), filter_flag.c_str(), internal_flag.c_str()); DeathTest::set_last_death_test_message(""); CaptureStderr(); // Flush the log buffers since the log streams are shared with the child. FlushInfoLog(); // The child process will share the standard handles with the parent. STARTUPINFOA startup_info; memset(&startup_info, 0, sizeof(STARTUPINFO)); startup_info.dwFlags = STARTF_USESTDHANDLES; startup_info.hStdInput = ::GetStdHandle(STD_INPUT_HANDLE); startup_info.hStdOutput = ::GetStdHandle(STD_OUTPUT_HANDLE); startup_info.hStdError = ::GetStdHandle(STD_ERROR_HANDLE); PROCESS_INFORMATION process_info; GTEST_DEATH_TEST_CHECK_(::CreateProcessA( executable_path, const_cast(command_line.c_str()), NULL, // Retuned process handle is not inheritable. NULL, // Retuned thread handle is not inheritable. TRUE, // Child inherits all inheritable handles (for write_handle_). 0x0, // Default creation flags. NULL, // Inherit the parent's environment. UnitTest::GetInstance()->original_working_dir(), &startup_info, &process_info) != FALSE); child_handle_.Reset(process_info.hProcess); ::CloseHandle(process_info.hThread); set_spawned(true); return OVERSEE_TEST; } # else // We are not on Windows. // ForkingDeathTest provides implementations for most of the abstract // methods of the DeathTest interface. Only the AssumeRole method is // left undefined. class ForkingDeathTest : public DeathTestImpl { public: ForkingDeathTest(const char* statement, const RE* regex); // All of these virtual functions are inherited from DeathTest. virtual int Wait(); protected: void set_child_pid(pid_t child_pid) { child_pid_ = child_pid; } private: // PID of child process during death test; 0 in the child process itself. pid_t child_pid_; }; // Constructs a ForkingDeathTest. ForkingDeathTest::ForkingDeathTest(const char* a_statement, const RE* a_regex) : DeathTestImpl(a_statement, a_regex), child_pid_(-1) {} // Waits for the child in a death test to exit, returning its exit // status, or 0 if no child process exists. As a side effect, sets the // outcome data member. int ForkingDeathTest::Wait() { if (!spawned()) return 0; ReadAndInterpretStatusByte(); int status_value; GTEST_DEATH_TEST_CHECK_SYSCALL_(waitpid(child_pid_, &status_value, 0)); set_status(status_value); return status_value; } // A concrete death test class that forks, then immediately runs the test // in the child process. class NoExecDeathTest : public ForkingDeathTest { public: NoExecDeathTest(const char* a_statement, const RE* a_regex) : ForkingDeathTest(a_statement, a_regex) { } virtual TestRole AssumeRole(); }; // The AssumeRole process for a fork-and-run death test. It implements a // straightforward fork, with a simple pipe to transmit the status byte. DeathTest::TestRole NoExecDeathTest::AssumeRole() { const size_t thread_count = GetThreadCount(); if (thread_count != 1) { GTEST_LOG_(WARNING) << DeathTestThreadWarning(thread_count); } int pipe_fd[2]; GTEST_DEATH_TEST_CHECK_(pipe(pipe_fd) != -1); DeathTest::set_last_death_test_message(""); CaptureStderr(); // When we fork the process below, the log file buffers are copied, but the // file descriptors are shared. We flush all log files here so that closing // the file descriptors in the child process doesn't throw off the // synchronization between descriptors and buffers in the parent process. // This is as close to the fork as possible to avoid a race condition in case // there are multiple threads running before the death test, and another // thread writes to the log file. FlushInfoLog(); const pid_t child_pid = fork(); GTEST_DEATH_TEST_CHECK_(child_pid != -1); set_child_pid(child_pid); if (child_pid == 0) { GTEST_DEATH_TEST_CHECK_SYSCALL_(close(pipe_fd[0])); set_write_fd(pipe_fd[1]); // Redirects all logging to stderr in the child process to prevent // concurrent writes to the log files. We capture stderr in the parent // process and append the child process' output to a log. LogToStderr(); // Event forwarding to the listeners of event listener API mush be shut // down in death test subprocesses. GetUnitTestImpl()->listeners()->SuppressEventForwarding(); return EXECUTE_TEST; } else { GTEST_DEATH_TEST_CHECK_SYSCALL_(close(pipe_fd[1])); set_read_fd(pipe_fd[0]); set_spawned(true); return OVERSEE_TEST; } } // A concrete death test class that forks and re-executes the main // program from the beginning, with command-line flags set that cause // only this specific death test to be run. class ExecDeathTest : public ForkingDeathTest { public: ExecDeathTest(const char* a_statement, const RE* a_regex, const char* file, int line) : ForkingDeathTest(a_statement, a_regex), file_(file), line_(line) { } virtual TestRole AssumeRole(); private: // The name of the file in which the death test is located. const char* const file_; // The line number on which the death test is located. const int line_; }; // Utility class for accumulating command-line arguments. class Arguments { public: Arguments() { args_.push_back(NULL); } ~Arguments() { for (std::vector::iterator i = args_.begin(); i != args_.end(); ++i) { free(*i); } } void AddArgument(const char* argument) { args_.insert(args_.end() - 1, posix::StrDup(argument)); } template void AddArguments(const ::std::vector& arguments) { for (typename ::std::vector::const_iterator i = arguments.begin(); i != arguments.end(); ++i) { args_.insert(args_.end() - 1, posix::StrDup(i->c_str())); } } char* const* Argv() { return &args_[0]; } private: std::vector args_; }; // A struct that encompasses the arguments to the child process of a // threadsafe-style death test process. struct ExecDeathTestArgs { char* const* argv; // Command-line arguments for the child's call to exec int close_fd; // File descriptor to close; the read end of a pipe }; # if GTEST_OS_MAC inline char** GetEnviron() { // When Google Test is built as a framework on MacOS X, the environ variable // is unavailable. Apple's documentation (man environ) recommends using // _NSGetEnviron() instead. return *_NSGetEnviron(); } # else // Some POSIX platforms expect you to declare environ. extern "C" makes // it reside in the global namespace. extern "C" char** environ; inline char** GetEnviron() { return environ; } # endif // GTEST_OS_MAC // The main function for a threadsafe-style death test child process. // This function is called in a clone()-ed process and thus must avoid // any potentially unsafe operations like malloc or libc functions. static int ExecDeathTestChildMain(void* child_arg) { ExecDeathTestArgs* const args = static_cast(child_arg); GTEST_DEATH_TEST_CHECK_SYSCALL_(close(args->close_fd)); // We need to execute the test program in the same environment where // it was originally invoked. Therefore we change to the original // working directory first. const char* const original_dir = UnitTest::GetInstance()->original_working_dir(); // We can safely call chdir() as it's a direct system call. if (chdir(original_dir) != 0) { DeathTestAbort(String::Format("chdir(\"%s\") failed: %s", original_dir, GetLastErrnoDescription().c_str())); return EXIT_FAILURE; } // We can safely call execve() as it's a direct system call. We // cannot use execvp() as it's a libc function and thus potentially // unsafe. Since execve() doesn't search the PATH, the user must // invoke the test program via a valid path that contains at least // one path separator. execve(args->argv[0], args->argv, GetEnviron()); DeathTestAbort(String::Format("execve(%s, ...) in %s failed: %s", args->argv[0], original_dir, GetLastErrnoDescription().c_str())); return EXIT_FAILURE; } // Two utility routines that together determine the direction the stack // grows. // This could be accomplished more elegantly by a single recursive // function, but we want to guard against the unlikely possibility of // a smart compiler optimizing the recursion away. // // GTEST_NO_INLINE_ is required to prevent GCC 4.6 from inlining // StackLowerThanAddress into StackGrowsDown, which then doesn't give // correct answer. bool StackLowerThanAddress(const void* ptr) GTEST_NO_INLINE_; bool StackLowerThanAddress(const void* ptr) { int dummy; return &dummy < ptr; } bool StackGrowsDown() { int dummy; return StackLowerThanAddress(&dummy); } // A threadsafe implementation of fork(2) for threadsafe-style death tests // that uses clone(2). It dies with an error message if anything goes // wrong. static pid_t ExecDeathTestFork(char* const* argv, int close_fd) { ExecDeathTestArgs args = { argv, close_fd }; pid_t child_pid = -1; # if GTEST_HAS_CLONE const bool use_fork = GTEST_FLAG(death_test_use_fork); if (!use_fork) { static const bool stack_grows_down = StackGrowsDown(); const size_t stack_size = getpagesize(); // MMAP_ANONYMOUS is not defined on Mac, so we use MAP_ANON instead. void* const stack = mmap(NULL, stack_size, PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0); GTEST_DEATH_TEST_CHECK_(stack != MAP_FAILED); void* const stack_top = static_cast(stack) + (stack_grows_down ? stack_size : 0); child_pid = clone(&ExecDeathTestChildMain, stack_top, SIGCHLD, &args); GTEST_DEATH_TEST_CHECK_(munmap(stack, stack_size) != -1); } # else const bool use_fork = true; # endif // GTEST_HAS_CLONE if (use_fork && (child_pid = fork()) == 0) { ExecDeathTestChildMain(&args); _exit(0); } GTEST_DEATH_TEST_CHECK_(child_pid != -1); return child_pid; } // The AssumeRole process for a fork-and-exec death test. It re-executes the // main program from the beginning, setting the --gtest_filter // and --gtest_internal_run_death_test flags to cause only the current // death test to be re-run. DeathTest::TestRole ExecDeathTest::AssumeRole() { const UnitTestImpl* const impl = GetUnitTestImpl(); const InternalRunDeathTestFlag* const flag = impl->internal_run_death_test_flag(); const TestInfo* const info = impl->current_test_info(); const int death_test_index = info->result()->death_test_count(); if (flag != NULL) { set_write_fd(flag->write_fd()); return EXECUTE_TEST; } int pipe_fd[2]; GTEST_DEATH_TEST_CHECK_(pipe(pipe_fd) != -1); // Clear the close-on-exec flag on the write end of the pipe, lest // it be closed when the child process does an exec: GTEST_DEATH_TEST_CHECK_(fcntl(pipe_fd[1], F_SETFD, 0) != -1); const String filter_flag = String::Format("--%s%s=%s.%s", GTEST_FLAG_PREFIX_, kFilterFlag, info->test_case_name(), info->name()); const String internal_flag = String::Format("--%s%s=%s|%d|%d|%d", GTEST_FLAG_PREFIX_, kInternalRunDeathTestFlag, file_, line_, death_test_index, pipe_fd[1]); Arguments args; args.AddArguments(GetArgvs()); args.AddArgument(filter_flag.c_str()); args.AddArgument(internal_flag.c_str()); DeathTest::set_last_death_test_message(""); CaptureStderr(); // See the comment in NoExecDeathTest::AssumeRole for why the next line // is necessary. FlushInfoLog(); const pid_t child_pid = ExecDeathTestFork(args.Argv(), pipe_fd[0]); GTEST_DEATH_TEST_CHECK_SYSCALL_(close(pipe_fd[1])); set_child_pid(child_pid); set_read_fd(pipe_fd[0]); set_spawned(true); return OVERSEE_TEST; } # endif // !GTEST_OS_WINDOWS // Creates a concrete DeathTest-derived class that depends on the // --gtest_death_test_style flag, and sets the pointer pointed to // by the "test" argument to its address. If the test should be // skipped, sets that pointer to NULL. Returns true, unless the // flag is set to an invalid value. bool DefaultDeathTestFactory::Create(const char* statement, const RE* regex, const char* file, int line, DeathTest** test) { UnitTestImpl* const impl = GetUnitTestImpl(); const InternalRunDeathTestFlag* const flag = impl->internal_run_death_test_flag(); const int death_test_index = impl->current_test_info() ->increment_death_test_count(); if (flag != NULL) { if (death_test_index > flag->index()) { DeathTest::set_last_death_test_message(String::Format( "Death test count (%d) somehow exceeded expected maximum (%d)", death_test_index, flag->index())); return false; } if (!(flag->file() == file && flag->line() == line && flag->index() == death_test_index)) { *test = NULL; return true; } } # if GTEST_OS_WINDOWS if (GTEST_FLAG(death_test_style) == "threadsafe" || GTEST_FLAG(death_test_style) == "fast") { *test = new WindowsDeathTest(statement, regex, file, line); } # else if (GTEST_FLAG(death_test_style) == "threadsafe") { *test = new ExecDeathTest(statement, regex, file, line); } else if (GTEST_FLAG(death_test_style) == "fast") { *test = new NoExecDeathTest(statement, regex); } # endif // GTEST_OS_WINDOWS else { // NOLINT - this is more readable than unbalanced brackets inside #if. DeathTest::set_last_death_test_message(String::Format( "Unknown death test style \"%s\" encountered", GTEST_FLAG(death_test_style).c_str())); return false; } return true; } // Splits a given string on a given delimiter, populating a given // vector with the fields. GTEST_HAS_DEATH_TEST implies that we have // ::std::string, so we can use it here. static void SplitString(const ::std::string& str, char delimiter, ::std::vector< ::std::string>* dest) { ::std::vector< ::std::string> parsed; ::std::string::size_type pos = 0; while (::testing::internal::AlwaysTrue()) { const ::std::string::size_type colon = str.find(delimiter, pos); if (colon == ::std::string::npos) { parsed.push_back(str.substr(pos)); break; } else { parsed.push_back(str.substr(pos, colon - pos)); pos = colon + 1; } } dest->swap(parsed); } # if GTEST_OS_WINDOWS // Recreates the pipe and event handles from the provided parameters, // signals the event, and returns a file descriptor wrapped around the pipe // handle. This function is called in the child process only. int GetStatusFileDescriptor(unsigned int parent_process_id, size_t write_handle_as_size_t, size_t event_handle_as_size_t) { AutoHandle parent_process_handle(::OpenProcess(PROCESS_DUP_HANDLE, FALSE, // Non-inheritable. parent_process_id)); if (parent_process_handle.Get() == INVALID_HANDLE_VALUE) { DeathTestAbort(String::Format("Unable to open parent process %u", parent_process_id)); } // TODO(vladl@google.com): Replace the following check with a // compile-time assertion when available. GTEST_CHECK_(sizeof(HANDLE) <= sizeof(size_t)); const HANDLE write_handle = reinterpret_cast(write_handle_as_size_t); HANDLE dup_write_handle; // The newly initialized handle is accessible only in in the parent // process. To obtain one accessible within the child, we need to use // DuplicateHandle. if (!::DuplicateHandle(parent_process_handle.Get(), write_handle, ::GetCurrentProcess(), &dup_write_handle, 0x0, // Requested privileges ignored since // DUPLICATE_SAME_ACCESS is used. FALSE, // Request non-inheritable handler. DUPLICATE_SAME_ACCESS)) { DeathTestAbort(String::Format( "Unable to duplicate the pipe handle %Iu from the parent process %u", write_handle_as_size_t, parent_process_id)); } const HANDLE event_handle = reinterpret_cast(event_handle_as_size_t); HANDLE dup_event_handle; if (!::DuplicateHandle(parent_process_handle.Get(), event_handle, ::GetCurrentProcess(), &dup_event_handle, 0x0, FALSE, DUPLICATE_SAME_ACCESS)) { DeathTestAbort(String::Format( "Unable to duplicate the event handle %Iu from the parent process %u", event_handle_as_size_t, parent_process_id)); } const int write_fd = ::_open_osfhandle(reinterpret_cast(dup_write_handle), O_APPEND); if (write_fd == -1) { DeathTestAbort(String::Format( "Unable to convert pipe handle %Iu to a file descriptor", write_handle_as_size_t)); } // Signals the parent that the write end of the pipe has been acquired // so the parent can release its own write end. ::SetEvent(dup_event_handle); return write_fd; } # endif // GTEST_OS_WINDOWS // Returns a newly created InternalRunDeathTestFlag object with fields // initialized from the GTEST_FLAG(internal_run_death_test) flag if // the flag is specified; otherwise returns NULL. InternalRunDeathTestFlag* ParseInternalRunDeathTestFlag() { if (GTEST_FLAG(internal_run_death_test) == "") return NULL; // GTEST_HAS_DEATH_TEST implies that we have ::std::string, so we // can use it here. int line = -1; int index = -1; ::std::vector< ::std::string> fields; SplitString(GTEST_FLAG(internal_run_death_test).c_str(), '|', &fields); int write_fd = -1; # if GTEST_OS_WINDOWS unsigned int parent_process_id = 0; size_t write_handle_as_size_t = 0; size_t event_handle_as_size_t = 0; if (fields.size() != 6 || !ParseNaturalNumber(fields[1], &line) || !ParseNaturalNumber(fields[2], &index) || !ParseNaturalNumber(fields[3], &parent_process_id) || !ParseNaturalNumber(fields[4], &write_handle_as_size_t) || !ParseNaturalNumber(fields[5], &event_handle_as_size_t)) { DeathTestAbort(String::Format( "Bad --gtest_internal_run_death_test flag: %s", GTEST_FLAG(internal_run_death_test).c_str())); } write_fd = GetStatusFileDescriptor(parent_process_id, write_handle_as_size_t, event_handle_as_size_t); # else if (fields.size() != 4 || !ParseNaturalNumber(fields[1], &line) || !ParseNaturalNumber(fields[2], &index) || !ParseNaturalNumber(fields[3], &write_fd)) { DeathTestAbort(String::Format( "Bad --gtest_internal_run_death_test flag: %s", GTEST_FLAG(internal_run_death_test).c_str())); } # endif // GTEST_OS_WINDOWS return new InternalRunDeathTestFlag(fields[0], line, index, write_fd); } } // namespace internal #endif // GTEST_HAS_DEATH_TEST } // namespace testing // Copyright 2008, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Authors: keith.ray@gmail.com (Keith Ray) #include #if GTEST_OS_WINDOWS_MOBILE # include #elif GTEST_OS_WINDOWS # include # include #elif GTEST_OS_SYMBIAN || GTEST_OS_NACL // Symbian OpenC and NaCl have PATH_MAX in sys/syslimits.h # include #else # include # include // Some Linux distributions define PATH_MAX here. #endif // GTEST_OS_WINDOWS_MOBILE #if GTEST_OS_WINDOWS # define GTEST_PATH_MAX_ _MAX_PATH #elif defined(PATH_MAX) # define GTEST_PATH_MAX_ PATH_MAX #elif defined(_XOPEN_PATH_MAX) # define GTEST_PATH_MAX_ _XOPEN_PATH_MAX #elif defined(_POSIX_PATH_MAX) # define GTEST_PATH_MAX_ _POSIX_PATH_MAX #else // conservately set to 256 #define GTEST_PATH_MAX_ 256 #endif // GTEST_OS_WINDOWS namespace testing { namespace internal { #if GTEST_OS_WINDOWS // On Windows, '\\' is the standard path separator, but many tools and the // Windows API also accept '/' as an alternate path separator. Unless otherwise // noted, a file path can contain either kind of path separators, or a mixture // of them. const char kPathSeparator = '\\'; const char kAlternatePathSeparator = '/'; const char kPathSeparatorString[] = "\\"; const char kAlternatePathSeparatorString[] = "/"; # if GTEST_OS_WINDOWS_MOBILE // Windows CE doesn't have a current directory. You should not use // the current directory in tests on Windows CE, but this at least // provides a reasonable fallback. const char kCurrentDirectoryString[] = "\\"; // Windows CE doesn't define INVALID_FILE_ATTRIBUTES const DWORD kInvalidFileAttributes = 0xffffffff; # else const char kCurrentDirectoryString[] = ".\\"; # endif // GTEST_OS_WINDOWS_MOBILE #else const char kPathSeparator = '/'; const char kPathSeparatorString[] = "/"; const char kCurrentDirectoryString[] = "./"; #endif // GTEST_OS_WINDOWS // Returns whether the given character is a valid path separator. static bool IsPathSeparator(char c) { #if GTEST_HAS_ALT_PATH_SEP_ return (c == kPathSeparator) || (c == kAlternatePathSeparator); #else return c == kPathSeparator; #endif } // Returns the current working directory, or "" if unsuccessful. FilePath FilePath::GetCurrentDir() { #if GTEST_OS_WINDOWS_MOBILE // Windows CE doesn't have a current directory, so we just return // something reasonable. return FilePath(kCurrentDirectoryString); #elif GTEST_OS_WINDOWS char cwd[GTEST_PATH_MAX_ + 1] = { '\0' }; return FilePath(_getcwd(cwd, sizeof(cwd)) == NULL ? "" : cwd); #else char cwd[GTEST_PATH_MAX_ + 1] = { '\0' }; return FilePath(getcwd(cwd, sizeof(cwd)) == NULL ? "" : cwd); #endif // GTEST_OS_WINDOWS_MOBILE } // Returns a copy of the FilePath with the case-insensitive extension removed. // Example: FilePath("dir/file.exe").RemoveExtension("EXE") returns // FilePath("dir/file"). If a case-insensitive extension is not // found, returns a copy of the original FilePath. FilePath FilePath::RemoveExtension(const char* extension) const { String dot_extension(String::Format(".%s", extension)); if (pathname_.EndsWithCaseInsensitive(dot_extension.c_str())) { return FilePath(String(pathname_.c_str(), pathname_.length() - 4)); } return *this; } // Returns a pointer to the last occurence of a valid path separator in // the FilePath. On Windows, for example, both '/' and '\' are valid path // separators. Returns NULL if no path separator was found. const char* FilePath::FindLastPathSeparator() const { const char* const last_sep = strrchr(c_str(), kPathSeparator); #if GTEST_HAS_ALT_PATH_SEP_ const char* const last_alt_sep = strrchr(c_str(), kAlternatePathSeparator); // Comparing two pointers of which only one is NULL is undefined. if (last_alt_sep != NULL && (last_sep == NULL || last_alt_sep > last_sep)) { return last_alt_sep; } #endif return last_sep; } // Returns a copy of the FilePath with the directory part removed. // Example: FilePath("path/to/file").RemoveDirectoryName() returns // FilePath("file"). If there is no directory part ("just_a_file"), it returns // the FilePath unmodified. If there is no file part ("just_a_dir/") it // returns an empty FilePath (""). // On Windows platform, '\' is the path separator, otherwise it is '/'. FilePath FilePath::RemoveDirectoryName() const { const char* const last_sep = FindLastPathSeparator(); return last_sep ? FilePath(String(last_sep + 1)) : *this; } // RemoveFileName returns the directory path with the filename removed. // Example: FilePath("path/to/file").RemoveFileName() returns "path/to/". // If the FilePath is "a_file" or "/a_file", RemoveFileName returns // FilePath("./") or, on Windows, FilePath(".\\"). If the filepath does // not have a file, like "just/a/dir/", it returns the FilePath unmodified. // On Windows platform, '\' is the path separator, otherwise it is '/'. FilePath FilePath::RemoveFileName() const { const char* const last_sep = FindLastPathSeparator(); String dir; if (last_sep) { dir = String(c_str(), last_sep + 1 - c_str()); } else { dir = kCurrentDirectoryString; } return FilePath(dir); } // Helper functions for naming files in a directory for xml output. // Given directory = "dir", base_name = "test", number = 0, // extension = "xml", returns "dir/test.xml". If number is greater // than zero (e.g., 12), returns "dir/test_12.xml". // On Windows platform, uses \ as the separator rather than /. FilePath FilePath::MakeFileName(const FilePath& directory, const FilePath& base_name, int number, const char* extension) { String file; if (number == 0) { file = String::Format("%s.%s", base_name.c_str(), extension); } else { file = String::Format("%s_%d.%s", base_name.c_str(), number, extension); } return ConcatPaths(directory, FilePath(file)); } // Given directory = "dir", relative_path = "test.xml", returns "dir/test.xml". // On Windows, uses \ as the separator rather than /. FilePath FilePath::ConcatPaths(const FilePath& directory, const FilePath& relative_path) { if (directory.IsEmpty()) return relative_path; const FilePath dir(directory.RemoveTrailingPathSeparator()); return FilePath(String::Format("%s%c%s", dir.c_str(), kPathSeparator, relative_path.c_str())); } // Returns true if pathname describes something findable in the file-system, // either a file, directory, or whatever. bool FilePath::FileOrDirectoryExists() const { #if GTEST_OS_WINDOWS_MOBILE LPCWSTR unicode = String::AnsiToUtf16(pathname_.c_str()); const DWORD attributes = GetFileAttributes(unicode); delete [] unicode; return attributes != kInvalidFileAttributes; #else posix::StatStruct file_stat; return posix::Stat(pathname_.c_str(), &file_stat) == 0; #endif // GTEST_OS_WINDOWS_MOBILE } // Returns true if pathname describes a directory in the file-system // that exists. bool FilePath::DirectoryExists() const { bool result = false; #if GTEST_OS_WINDOWS // Don't strip off trailing separator if path is a root directory on // Windows (like "C:\\"). const FilePath& path(IsRootDirectory() ? *this : RemoveTrailingPathSeparator()); #else const FilePath& path(*this); #endif #if GTEST_OS_WINDOWS_MOBILE LPCWSTR unicode = String::AnsiToUtf16(path.c_str()); const DWORD attributes = GetFileAttributes(unicode); delete [] unicode; if ((attributes != kInvalidFileAttributes) && (attributes & FILE_ATTRIBUTE_DIRECTORY)) { result = true; } #else posix::StatStruct file_stat; result = posix::Stat(path.c_str(), &file_stat) == 0 && posix::IsDir(file_stat); #endif // GTEST_OS_WINDOWS_MOBILE return result; } // Returns true if pathname describes a root directory. (Windows has one // root directory per disk drive.) bool FilePath::IsRootDirectory() const { #if GTEST_OS_WINDOWS // TODO(wan@google.com): on Windows a network share like // \\server\share can be a root directory, although it cannot be the // current directory. Handle this properly. return pathname_.length() == 3 && IsAbsolutePath(); #else return pathname_.length() == 1 && IsPathSeparator(pathname_.c_str()[0]); #endif } // Returns true if pathname describes an absolute path. bool FilePath::IsAbsolutePath() const { const char* const name = pathname_.c_str(); #if GTEST_OS_WINDOWS return pathname_.length() >= 3 && ((name[0] >= 'a' && name[0] <= 'z') || (name[0] >= 'A' && name[0] <= 'Z')) && name[1] == ':' && IsPathSeparator(name[2]); #else return IsPathSeparator(name[0]); #endif } // Returns a pathname for a file that does not currently exist. The pathname // will be directory/base_name.extension or // directory/base_name_.extension if directory/base_name.extension // already exists. The number will be incremented until a pathname is found // that does not already exist. // Examples: 'dir/foo_test.xml' or 'dir/foo_test_1.xml'. // There could be a race condition if two or more processes are calling this // function at the same time -- they could both pick the same filename. FilePath FilePath::GenerateUniqueFileName(const FilePath& directory, const FilePath& base_name, const char* extension) { FilePath full_pathname; int number = 0; do { full_pathname.Set(MakeFileName(directory, base_name, number++, extension)); } while (full_pathname.FileOrDirectoryExists()); return full_pathname; } // Returns true if FilePath ends with a path separator, which indicates that // it is intended to represent a directory. Returns false otherwise. // This does NOT check that a directory (or file) actually exists. bool FilePath::IsDirectory() const { return !pathname_.empty() && IsPathSeparator(pathname_.c_str()[pathname_.length() - 1]); } // Create directories so that path exists. Returns true if successful or if // the directories already exist; returns false if unable to create directories // for any reason. bool FilePath::CreateDirectoriesRecursively() const { if (!this->IsDirectory()) { return false; } if (pathname_.length() == 0 || this->DirectoryExists()) { return true; } const FilePath parent(this->RemoveTrailingPathSeparator().RemoveFileName()); return parent.CreateDirectoriesRecursively() && this->CreateFolder(); } // Create the directory so that path exists. Returns true if successful or // if the directory already exists; returns false if unable to create the // directory for any reason, including if the parent directory does not // exist. Not named "CreateDirectory" because that's a macro on Windows. bool FilePath::CreateFolder() const { #if GTEST_OS_WINDOWS_MOBILE FilePath removed_sep(this->RemoveTrailingPathSeparator()); LPCWSTR unicode = String::AnsiToUtf16(removed_sep.c_str()); int result = CreateDirectory(unicode, NULL) ? 0 : -1; delete [] unicode; #elif GTEST_OS_WINDOWS int result = _mkdir(pathname_.c_str()); #else int result = mkdir(pathname_.c_str(), 0777); #endif // GTEST_OS_WINDOWS_MOBILE if (result == -1) { return this->DirectoryExists(); // An error is OK if the directory exists. } return true; // No error. } // If input name has a trailing separator character, remove it and return the // name, otherwise return the name string unmodified. // On Windows platform, uses \ as the separator, other platforms use /. FilePath FilePath::RemoveTrailingPathSeparator() const { return IsDirectory() ? FilePath(String(pathname_.c_str(), pathname_.length() - 1)) : *this; } // Removes any redundant separators that might be in the pathname. // For example, "bar///foo" becomes "bar/foo". Does not eliminate other // redundancies that might be in a pathname involving "." or "..". // TODO(wan@google.com): handle Windows network shares (e.g. \\server\share). void FilePath::Normalize() { if (pathname_.c_str() == NULL) { pathname_ = ""; return; } const char* src = pathname_.c_str(); char* const dest = new char[pathname_.length() + 1]; char* dest_ptr = dest; memset(dest_ptr, 0, pathname_.length() + 1); while (*src != '\0') { *dest_ptr = *src; if (!IsPathSeparator(*src)) { src++; } else { #if GTEST_HAS_ALT_PATH_SEP_ if (*dest_ptr == kAlternatePathSeparator) { *dest_ptr = kPathSeparator; } #endif while (IsPathSeparator(*src)) src++; } dest_ptr++; } *dest_ptr = '\0'; pathname_ = dest; delete[] dest; } } // namespace internal } // namespace testing // Copyright 2008, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan) #include #include #include #include #if GTEST_OS_WINDOWS_MOBILE # include // For TerminateProcess() #elif GTEST_OS_WINDOWS # include # include #else # include #endif // GTEST_OS_WINDOWS_MOBILE #if GTEST_OS_MAC # include # include # include #endif // GTEST_OS_MAC // Indicates that this translation unit is part of Google Test's // implementation. It must come before gtest-internal-inl.h is // included, or there will be a compiler error. This trick is to // prevent a user from accidentally including gtest-internal-inl.h in // his code. #define GTEST_IMPLEMENTATION_ 1 #undef GTEST_IMPLEMENTATION_ namespace testing { namespace internal { #if defined(_MSC_VER) || defined(__BORLANDC__) // MSVC and C++Builder do not provide a definition of STDERR_FILENO. const int kStdOutFileno = 1; const int kStdErrFileno = 2; #else const int kStdOutFileno = STDOUT_FILENO; const int kStdErrFileno = STDERR_FILENO; #endif // _MSC_VER #if GTEST_OS_MAC // Returns the number of threads running in the process, or 0 to indicate that // we cannot detect it. size_t GetThreadCount() { const task_t task = mach_task_self(); mach_msg_type_number_t thread_count; thread_act_array_t thread_list; const kern_return_t status = task_threads(task, &thread_list, &thread_count); if (status == KERN_SUCCESS) { // task_threads allocates resources in thread_list and we need to free them // to avoid leaks. vm_deallocate(task, reinterpret_cast(thread_list), sizeof(thread_t) * thread_count); return static_cast(thread_count); } else { return 0; } } #else size_t GetThreadCount() { // There's no portable way to detect the number of threads, so we just // return 0 to indicate that we cannot detect it. return 0; } #endif // GTEST_OS_MAC #if GTEST_USES_POSIX_RE // Implements RE. Currently only needed for death tests. RE::~RE() { if (is_valid_) { // regfree'ing an invalid regex might crash because the content // of the regex is undefined. Since the regex's are essentially // the same, one cannot be valid (or invalid) without the other // being so too. regfree(&partial_regex_); regfree(&full_regex_); } free(const_cast(pattern_)); } // Returns true iff regular expression re matches the entire str. bool RE::FullMatch(const char* str, const RE& re) { if (!re.is_valid_) return false; regmatch_t match; return regexec(&re.full_regex_, str, 1, &match, 0) == 0; } // Returns true iff regular expression re matches a substring of str // (including str itself). bool RE::PartialMatch(const char* str, const RE& re) { if (!re.is_valid_) return false; regmatch_t match; return regexec(&re.partial_regex_, str, 1, &match, 0) == 0; } // Initializes an RE from its string representation. void RE::Init(const char* regex) { pattern_ = posix::StrDup(regex); // Reserves enough bytes to hold the regular expression used for a // full match. const size_t full_regex_len = strlen(regex) + 10; char* const full_pattern = new char[full_regex_len]; snprintf(full_pattern, full_regex_len, "^(%s)$", regex); is_valid_ = regcomp(&full_regex_, full_pattern, REG_EXTENDED) == 0; // We want to call regcomp(&partial_regex_, ...) even if the // previous expression returns false. Otherwise partial_regex_ may // not be properly initialized can may cause trouble when it's // freed. // // Some implementation of POSIX regex (e.g. on at least some // versions of Cygwin) doesn't accept the empty string as a valid // regex. We change it to an equivalent form "()" to be safe. if (is_valid_) { const char* const partial_regex = (*regex == '\0') ? "()" : regex; is_valid_ = regcomp(&partial_regex_, partial_regex, REG_EXTENDED) == 0; } EXPECT_TRUE(is_valid_) << "Regular expression \"" << regex << "\" is not a valid POSIX Extended regular expression."; delete[] full_pattern; } #elif GTEST_USES_SIMPLE_RE // Returns true iff ch appears anywhere in str (excluding the // terminating '\0' character). bool IsInSet(char ch, const char* str) { return ch != '\0' && strchr(str, ch) != NULL; } // Returns true iff ch belongs to the given classification. Unlike // similar functions in , these aren't affected by the // current locale. bool IsAsciiDigit(char ch) { return '0' <= ch && ch <= '9'; } bool IsAsciiPunct(char ch) { return IsInSet(ch, "^-!\"#$%&'()*+,./:;<=>?@[\\]_`{|}~"); } bool IsRepeat(char ch) { return IsInSet(ch, "?*+"); } bool IsAsciiWhiteSpace(char ch) { return IsInSet(ch, " \f\n\r\t\v"); } bool IsAsciiWordChar(char ch) { return ('a' <= ch && ch <= 'z') || ('A' <= ch && ch <= 'Z') || ('0' <= ch && ch <= '9') || ch == '_'; } // Returns true iff "\\c" is a supported escape sequence. bool IsValidEscape(char c) { return (IsAsciiPunct(c) || IsInSet(c, "dDfnrsStvwW")); } // Returns true iff the given atom (specified by escaped and pattern) // matches ch. The result is undefined if the atom is invalid. bool AtomMatchesChar(bool escaped, char pattern_char, char ch) { if (escaped) { // "\\p" where p is pattern_char. switch (pattern_char) { case 'd': return IsAsciiDigit(ch); case 'D': return !IsAsciiDigit(ch); case 'f': return ch == '\f'; case 'n': return ch == '\n'; case 'r': return ch == '\r'; case 's': return IsAsciiWhiteSpace(ch); case 'S': return !IsAsciiWhiteSpace(ch); case 't': return ch == '\t'; case 'v': return ch == '\v'; case 'w': return IsAsciiWordChar(ch); case 'W': return !IsAsciiWordChar(ch); } return IsAsciiPunct(pattern_char) && pattern_char == ch; } return (pattern_char == '.' && ch != '\n') || pattern_char == ch; } // Helper function used by ValidateRegex() to format error messages. String FormatRegexSyntaxError(const char* regex, int index) { return (Message() << "Syntax error at index " << index << " in simple regular expression \"" << regex << "\": ").GetString(); } // Generates non-fatal failures and returns false if regex is invalid; // otherwise returns true. bool ValidateRegex(const char* regex) { if (regex == NULL) { // TODO(wan@google.com): fix the source file location in the // assertion failures to match where the regex is used in user // code. ADD_FAILURE() << "NULL is not a valid simple regular expression."; return false; } bool is_valid = true; // True iff ?, *, or + can follow the previous atom. bool prev_repeatable = false; for (int i = 0; regex[i]; i++) { if (regex[i] == '\\') { // An escape sequence i++; if (regex[i] == '\0') { ADD_FAILURE() << FormatRegexSyntaxError(regex, i - 1) << "'\\' cannot appear at the end."; return false; } if (!IsValidEscape(regex[i])) { ADD_FAILURE() << FormatRegexSyntaxError(regex, i - 1) << "invalid escape sequence \"\\" << regex[i] << "\"."; is_valid = false; } prev_repeatable = true; } else { // Not an escape sequence. const char ch = regex[i]; if (ch == '^' && i > 0) { ADD_FAILURE() << FormatRegexSyntaxError(regex, i) << "'^' can only appear at the beginning."; is_valid = false; } else if (ch == '$' && regex[i + 1] != '\0') { ADD_FAILURE() << FormatRegexSyntaxError(regex, i) << "'$' can only appear at the end."; is_valid = false; } else if (IsInSet(ch, "()[]{}|")) { ADD_FAILURE() << FormatRegexSyntaxError(regex, i) << "'" << ch << "' is unsupported."; is_valid = false; } else if (IsRepeat(ch) && !prev_repeatable) { ADD_FAILURE() << FormatRegexSyntaxError(regex, i) << "'" << ch << "' can only follow a repeatable token."; is_valid = false; } prev_repeatable = !IsInSet(ch, "^$?*+"); } } return is_valid; } // Matches a repeated regex atom followed by a valid simple regular // expression. The regex atom is defined as c if escaped is false, // or \c otherwise. repeat is the repetition meta character (?, *, // or +). The behavior is undefined if str contains too many // characters to be indexable by size_t, in which case the test will // probably time out anyway. We are fine with this limitation as // std::string has it too. bool MatchRepetitionAndRegexAtHead( bool escaped, char c, char repeat, const char* regex, const char* str) { const size_t min_count = (repeat == '+') ? 1 : 0; const size_t max_count = (repeat == '?') ? 1 : static_cast(-1) - 1; // We cannot call numeric_limits::max() as it conflicts with the // max() macro on Windows. for (size_t i = 0; i <= max_count; ++i) { // We know that the atom matches each of the first i characters in str. if (i >= min_count && MatchRegexAtHead(regex, str + i)) { // We have enough matches at the head, and the tail matches too. // Since we only care about *whether* the pattern matches str // (as opposed to *how* it matches), there is no need to find a // greedy match. return true; } if (str[i] == '\0' || !AtomMatchesChar(escaped, c, str[i])) return false; } return false; } // Returns true iff regex matches a prefix of str. regex must be a // valid simple regular expression and not start with "^", or the // result is undefined. bool MatchRegexAtHead(const char* regex, const char* str) { if (*regex == '\0') // An empty regex matches a prefix of anything. return true; // "$" only matches the end of a string. Note that regex being // valid guarantees that there's nothing after "$" in it. if (*regex == '$') return *str == '\0'; // Is the first thing in regex an escape sequence? const bool escaped = *regex == '\\'; if (escaped) ++regex; if (IsRepeat(regex[1])) { // MatchRepetitionAndRegexAtHead() calls MatchRegexAtHead(), so // here's an indirect recursion. It terminates as the regex gets // shorter in each recursion. return MatchRepetitionAndRegexAtHead( escaped, regex[0], regex[1], regex + 2, str); } else { // regex isn't empty, isn't "$", and doesn't start with a // repetition. We match the first atom of regex with the first // character of str and recurse. return (*str != '\0') && AtomMatchesChar(escaped, *regex, *str) && MatchRegexAtHead(regex + 1, str + 1); } } // Returns true iff regex matches any substring of str. regex must be // a valid simple regular expression, or the result is undefined. // // The algorithm is recursive, but the recursion depth doesn't exceed // the regex length, so we won't need to worry about running out of // stack space normally. In rare cases the time complexity can be // exponential with respect to the regex length + the string length, // but usually it's must faster (often close to linear). bool MatchRegexAnywhere(const char* regex, const char* str) { if (regex == NULL || str == NULL) return false; if (*regex == '^') return MatchRegexAtHead(regex + 1, str); // A successful match can be anywhere in str. do { if (MatchRegexAtHead(regex, str)) return true; } while (*str++ != '\0'); return false; } // Implements the RE class. RE::~RE() { free(const_cast(pattern_)); free(const_cast(full_pattern_)); } // Returns true iff regular expression re matches the entire str. bool RE::FullMatch(const char* str, const RE& re) { return re.is_valid_ && MatchRegexAnywhere(re.full_pattern_, str); } // Returns true iff regular expression re matches a substring of str // (including str itself). bool RE::PartialMatch(const char* str, const RE& re) { return re.is_valid_ && MatchRegexAnywhere(re.pattern_, str); } // Initializes an RE from its string representation. void RE::Init(const char* regex) { pattern_ = full_pattern_ = NULL; if (regex != NULL) { pattern_ = posix::StrDup(regex); } is_valid_ = ValidateRegex(regex); if (!is_valid_) { // No need to calculate the full pattern when the regex is invalid. return; } const size_t len = strlen(regex); // Reserves enough bytes to hold the regular expression used for a // full match: we need space to prepend a '^', append a '$', and // terminate the string with '\0'. char* buffer = static_cast(malloc(len + 3)); full_pattern_ = buffer; if (*regex != '^') *buffer++ = '^'; // Makes sure full_pattern_ starts with '^'. // We don't use snprintf or strncpy, as they trigger a warning when // compiled with VC++ 8.0. memcpy(buffer, regex, len); buffer += len; if (len == 0 || regex[len - 1] != '$') *buffer++ = '$'; // Makes sure full_pattern_ ends with '$'. *buffer = '\0'; } #endif // GTEST_USES_POSIX_RE const char kUnknownFile[] = "unknown file"; // Formats a source file path and a line number as they would appear // in an error message from the compiler used to compile this code. GTEST_API_ ::std::string FormatFileLocation(const char* file, int line) { const char* const file_name = file == NULL ? kUnknownFile : file; if (line < 0) { return String::Format("%s:", file_name).c_str(); } #ifdef _MSC_VER return String::Format("%s(%d):", file_name, line).c_str(); #else return String::Format("%s:%d:", file_name, line).c_str(); #endif // _MSC_VER } // Formats a file location for compiler-independent XML output. // Although this function is not platform dependent, we put it next to // FormatFileLocation in order to contrast the two functions. // Note that FormatCompilerIndependentFileLocation() does NOT append colon // to the file location it produces, unlike FormatFileLocation(). GTEST_API_ ::std::string FormatCompilerIndependentFileLocation( const char* file, int line) { const char* const file_name = file == NULL ? kUnknownFile : file; if (line < 0) return file_name; else return String::Format("%s:%d", file_name, line).c_str(); } GTestLog::GTestLog(GTestLogSeverity severity, const char* file, int line) : severity_(severity) { const char* const marker = severity == GTEST_INFO ? "[ INFO ]" : severity == GTEST_WARNING ? "[WARNING]" : severity == GTEST_ERROR ? "[ ERROR ]" : "[ FATAL ]"; GetStream() << ::std::endl << marker << " " << FormatFileLocation(file, line).c_str() << ": "; } // Flushes the buffers and, if severity is GTEST_FATAL, aborts the program. GTestLog::~GTestLog() { GetStream() << ::std::endl; if (severity_ == GTEST_FATAL) { fflush(stderr); posix::Abort(); } } // Disable Microsoft deprecation warnings for POSIX functions called from // this class (creat, dup, dup2, and close) #ifdef _MSC_VER # pragma warning(push) # pragma warning(disable: 4996) #endif // _MSC_VER #if GTEST_HAS_STREAM_REDIRECTION // Object that captures an output stream (stdout/stderr). class CapturedStream { public: // The ctor redirects the stream to a temporary file. CapturedStream(int fd) : fd_(fd), uncaptured_fd_(dup(fd)) { # if GTEST_OS_WINDOWS char temp_dir_path[MAX_PATH + 1] = { '\0' }; // NOLINT char temp_file_path[MAX_PATH + 1] = { '\0' }; // NOLINT ::GetTempPathA(sizeof(temp_dir_path), temp_dir_path); const UINT success = ::GetTempFileNameA(temp_dir_path, "gtest_redir", 0, // Generate unique file name. temp_file_path); GTEST_CHECK_(success != 0) << "Unable to create a temporary file in " << temp_dir_path; const int captured_fd = creat(temp_file_path, _S_IREAD | _S_IWRITE); GTEST_CHECK_(captured_fd != -1) << "Unable to open temporary file " << temp_file_path; filename_ = temp_file_path; # else // There's no guarantee that a test has write access to the // current directory, so we create the temporary file in the /tmp // directory instead. char name_template[] = "/tmp/captured_stream.XXXXXX"; const int captured_fd = mkstemp(name_template); filename_ = name_template; # endif // GTEST_OS_WINDOWS fflush(NULL); dup2(captured_fd, fd_); close(captured_fd); } ~CapturedStream() { remove(filename_.c_str()); } String GetCapturedString() { if (uncaptured_fd_ != -1) { // Restores the original stream. fflush(NULL); dup2(uncaptured_fd_, fd_); close(uncaptured_fd_); uncaptured_fd_ = -1; } FILE* const file = posix::FOpen(filename_.c_str(), "r"); const String content = ReadEntireFile(file); posix::FClose(file); return content; } private: // Reads the entire content of a file as a String. static String ReadEntireFile(FILE* file); // Returns the size (in bytes) of a file. static size_t GetFileSize(FILE* file); const int fd_; // A stream to capture. int uncaptured_fd_; // Name of the temporary file holding the stderr output. ::std::string filename_; GTEST_DISALLOW_COPY_AND_ASSIGN_(CapturedStream); }; // Returns the size (in bytes) of a file. size_t CapturedStream::GetFileSize(FILE* file) { fseek(file, 0, SEEK_END); return static_cast(ftell(file)); } // Reads the entire content of a file as a string. String CapturedStream::ReadEntireFile(FILE* file) { const size_t file_size = GetFileSize(file); char* const buffer = new char[file_size]; size_t bytes_last_read = 0; // # of bytes read in the last fread() size_t bytes_read = 0; // # of bytes read so far fseek(file, 0, SEEK_SET); // Keeps reading the file until we cannot read further or the // pre-determined file size is reached. do { bytes_last_read = fread(buffer+bytes_read, 1, file_size-bytes_read, file); bytes_read += bytes_last_read; } while (bytes_last_read > 0 && bytes_read < file_size); const String content(buffer, bytes_read); delete[] buffer; return content; } # ifdef _MSC_VER # pragma warning(pop) # endif // _MSC_VER static CapturedStream* g_captured_stderr = NULL; static CapturedStream* g_captured_stdout = NULL; // Starts capturing an output stream (stdout/stderr). void CaptureStream(int fd, const char* stream_name, CapturedStream** stream) { if (*stream != NULL) { GTEST_LOG_(FATAL) << "Only one " << stream_name << " capturer can exist at a time."; } *stream = new CapturedStream(fd); } // Stops capturing the output stream and returns the captured string. String GetCapturedStream(CapturedStream** captured_stream) { const String content = (*captured_stream)->GetCapturedString(); delete *captured_stream; *captured_stream = NULL; return content; } // Starts capturing stdout. void CaptureStdout() { CaptureStream(kStdOutFileno, "stdout", &g_captured_stdout); } // Starts capturing stderr. void CaptureStderr() { CaptureStream(kStdErrFileno, "stderr", &g_captured_stderr); } // Stops capturing stdout and returns the captured string. String GetCapturedStdout() { return GetCapturedStream(&g_captured_stdout); } // Stops capturing stderr and returns the captured string. String GetCapturedStderr() { return GetCapturedStream(&g_captured_stderr); } #endif // GTEST_HAS_STREAM_REDIRECTION #if GTEST_HAS_DEATH_TEST // A copy of all command line arguments. Set by InitGoogleTest(). ::std::vector g_argvs; // Returns the command line as a vector of strings. const ::std::vector& GetArgvs() { return g_argvs; } #endif // GTEST_HAS_DEATH_TEST #if GTEST_OS_WINDOWS_MOBILE namespace posix { void Abort() { DebugBreak(); TerminateProcess(GetCurrentProcess(), 1); } } // namespace posix #endif // GTEST_OS_WINDOWS_MOBILE // Returns the name of the environment variable corresponding to the // given flag. For example, FlagToEnvVar("foo") will return // "GTEST_FOO" in the open-source version. static String FlagToEnvVar(const char* flag) { const String full_flag = (Message() << GTEST_FLAG_PREFIX_ << flag).GetString(); Message env_var; for (size_t i = 0; i != full_flag.length(); i++) { env_var << ToUpper(full_flag.c_str()[i]); } return env_var.GetString(); } // Parses 'str' for a 32-bit signed integer. If successful, writes // the result to *value and returns true; otherwise leaves *value // unchanged and returns false. bool ParseInt32(const Message& src_text, const char* str, Int32* value) { // Parses the environment variable as a decimal integer. char* end = NULL; const long long_value = strtol(str, &end, 10); // NOLINT // Has strtol() consumed all characters in the string? if (*end != '\0') { // No - an invalid character was encountered. Message msg; msg << "WARNING: " << src_text << " is expected to be a 32-bit integer, but actually" << " has value \"" << str << "\".\n"; printf("%s", msg.GetString().c_str()); fflush(stdout); return false; } // Is the parsed value in the range of an Int32? const Int32 result = static_cast(long_value); if (long_value == LONG_MAX || long_value == LONG_MIN || // The parsed value overflows as a long. (strtol() returns // LONG_MAX or LONG_MIN when the input overflows.) result != long_value // The parsed value overflows as an Int32. ) { Message msg; msg << "WARNING: " << src_text << " is expected to be a 32-bit integer, but actually" << " has value " << str << ", which overflows.\n"; printf("%s", msg.GetString().c_str()); fflush(stdout); return false; } *value = result; return true; } // Reads and returns the Boolean environment variable corresponding to // the given flag; if it's not set, returns default_value. // // The value is considered true iff it's not "0". bool BoolFromGTestEnv(const char* flag, bool default_value) { const String env_var = FlagToEnvVar(flag); const char* const string_value = posix::GetEnv(env_var.c_str()); return string_value == NULL ? default_value : strcmp(string_value, "0") != 0; } // Reads and returns a 32-bit integer stored in the environment // variable corresponding to the given flag; if it isn't set or // doesn't represent a valid 32-bit integer, returns default_value. Int32 Int32FromGTestEnv(const char* flag, Int32 default_value) { const String env_var = FlagToEnvVar(flag); const char* const string_value = posix::GetEnv(env_var.c_str()); if (string_value == NULL) { // The environment variable is not set. return default_value; } Int32 result = default_value; if (!ParseInt32(Message() << "Environment variable " << env_var, string_value, &result)) { printf("The default value %s is used.\n", (Message() << default_value).GetString().c_str()); fflush(stdout); return default_value; } return result; } // Reads and returns the string environment variable corresponding to // the given flag; if it's not set, returns default_value. const char* StringFromGTestEnv(const char* flag, const char* default_value) { const String env_var = FlagToEnvVar(flag); const char* const value = posix::GetEnv(env_var.c_str()); return value == NULL ? default_value : value; } } // namespace internal } // namespace testing // Copyright 2007, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan) // Google Test - The Google C++ Testing Framework // // This file implements a universal value printer that can print a // value of any type T: // // void ::testing::internal::UniversalPrinter::Print(value, ostream_ptr); // // It uses the << operator when possible, and prints the bytes in the // object otherwise. A user can override its behavior for a class // type Foo by defining either operator<<(::std::ostream&, const Foo&) // or void PrintTo(const Foo&, ::std::ostream*) in the namespace that // defines Foo. #include #include #include // NOLINT #include namespace testing { namespace { using ::std::ostream; #if GTEST_OS_WINDOWS_MOBILE // Windows CE does not define _snprintf_s. # define snprintf _snprintf #elif _MSC_VER >= 1400 // VC 8.0 and later deprecate snprintf and _snprintf. # define snprintf _snprintf_s #elif _MSC_VER # define snprintf _snprintf #endif // GTEST_OS_WINDOWS_MOBILE // Prints a segment of bytes in the given object. void PrintByteSegmentInObjectTo(const unsigned char* obj_bytes, size_t start, size_t count, ostream* os) { char text[5] = ""; for (size_t i = 0; i != count; i++) { const size_t j = start + i; if (i != 0) { // Organizes the bytes into groups of 2 for easy parsing by // human. if ((j % 2) == 0) *os << ' '; else *os << '-'; } snprintf(text, sizeof(text), "%02X", obj_bytes[j]); *os << text; } } // Prints the bytes in the given value to the given ostream. void PrintBytesInObjectToImpl(const unsigned char* obj_bytes, size_t count, ostream* os) { // Tells the user how big the object is. *os << count << "-byte object <"; const size_t kThreshold = 132; const size_t kChunkSize = 64; // If the object size is bigger than kThreshold, we'll have to omit // some details by printing only the first and the last kChunkSize // bytes. // TODO(wan): let the user control the threshold using a flag. if (count < kThreshold) { PrintByteSegmentInObjectTo(obj_bytes, 0, count, os); } else { PrintByteSegmentInObjectTo(obj_bytes, 0, kChunkSize, os); *os << " ... "; // Rounds up to 2-byte boundary. const size_t resume_pos = (count - kChunkSize + 1)/2*2; PrintByteSegmentInObjectTo(obj_bytes, resume_pos, count - resume_pos, os); } *os << ">"; } } // namespace namespace internal2 { // Delegates to PrintBytesInObjectToImpl() to print the bytes in the // given object. The delegation simplifies the implementation, which // uses the << operator and thus is easier done outside of the // ::testing::internal namespace, which contains a << operator that // sometimes conflicts with the one in STL. void PrintBytesInObjectTo(const unsigned char* obj_bytes, size_t count, ostream* os) { PrintBytesInObjectToImpl(obj_bytes, count, os); } } // namespace internal2 namespace internal { // Depending on the value of a char (or wchar_t), we print it in one // of three formats: // - as is if it's a printable ASCII (e.g. 'a', '2', ' '), // - as a hexidecimal escape sequence (e.g. '\x7F'), or // - as a special escape sequence (e.g. '\r', '\n'). enum CharFormat { kAsIs, kHexEscape, kSpecialEscape }; // Returns true if c is a printable ASCII character. We test the // value of c directly instead of calling isprint(), which is buggy on // Windows Mobile. inline bool IsPrintableAscii(wchar_t c) { return 0x20 <= c && c <= 0x7E; } // Prints a wide or narrow char c as a character literal without the // quotes, escaping it when necessary; returns how c was formatted. // The template argument UnsignedChar is the unsigned version of Char, // which is the type of c. template static CharFormat PrintAsCharLiteralTo(Char c, ostream* os) { switch (static_cast(c)) { case L'\0': *os << "\\0"; break; case L'\'': *os << "\\'"; break; case L'\\': *os << "\\\\"; break; case L'\a': *os << "\\a"; break; case L'\b': *os << "\\b"; break; case L'\f': *os << "\\f"; break; case L'\n': *os << "\\n"; break; case L'\r': *os << "\\r"; break; case L'\t': *os << "\\t"; break; case L'\v': *os << "\\v"; break; default: if (IsPrintableAscii(c)) { *os << static_cast(c); return kAsIs; } else { *os << String::Format("\\x%X", static_cast(c)); return kHexEscape; } } return kSpecialEscape; } // Prints a char c as if it's part of a string literal, escaping it when // necessary; returns how c was formatted. static CharFormat PrintAsWideStringLiteralTo(wchar_t c, ostream* os) { switch (c) { case L'\'': *os << "'"; return kAsIs; case L'"': *os << "\\\""; return kSpecialEscape; default: return PrintAsCharLiteralTo(c, os); } } // Prints a char c as if it's part of a string literal, escaping it when // necessary; returns how c was formatted. static CharFormat PrintAsNarrowStringLiteralTo(char c, ostream* os) { return PrintAsWideStringLiteralTo(static_cast(c), os); } // Prints a wide or narrow character c and its code. '\0' is printed // as "'\\0'", other unprintable characters are also properly escaped // using the standard C++ escape sequence. The template argument // UnsignedChar is the unsigned version of Char, which is the type of c. template void PrintCharAndCodeTo(Char c, ostream* os) { // First, print c as a literal in the most readable form we can find. *os << ((sizeof(c) > 1) ? "L'" : "'"); const CharFormat format = PrintAsCharLiteralTo(c, os); *os << "'"; // To aid user debugging, we also print c's code in decimal, unless // it's 0 (in which case c was printed as '\\0', making the code // obvious). if (c == 0) return; *os << " (" << String::Format("%d", c).c_str(); // For more convenience, we print c's code again in hexidecimal, // unless c was already printed in the form '\x##' or the code is in // [1, 9]. if (format == kHexEscape || (1 <= c && c <= 9)) { // Do nothing. } else { *os << String::Format(", 0x%X", static_cast(c)).c_str(); } *os << ")"; } void PrintTo(unsigned char c, ::std::ostream* os) { PrintCharAndCodeTo(c, os); } void PrintTo(signed char c, ::std::ostream* os) { PrintCharAndCodeTo(c, os); } // Prints a wchar_t as a symbol if it is printable or as its internal // code otherwise and also as its code. L'\0' is printed as "L'\\0'". void PrintTo(wchar_t wc, ostream* os) { PrintCharAndCodeTo(wc, os); } // Prints the given array of characters to the ostream. // The array starts at *begin, the length is len, it may include '\0' characters // and may not be null-terminated. static void PrintCharsAsStringTo(const char* begin, size_t len, ostream* os) { *os << "\""; bool is_previous_hex = false; for (size_t index = 0; index < len; ++index) { const char cur = begin[index]; if (is_previous_hex && IsXDigit(cur)) { // Previous character is of '\x..' form and this character can be // interpreted as another hexadecimal digit in its number. Break string to // disambiguate. *os << "\" \""; } is_previous_hex = PrintAsNarrowStringLiteralTo(cur, os) == kHexEscape; } *os << "\""; } // Prints a (const) char array of 'len' elements, starting at address 'begin'. void UniversalPrintArray(const char* begin, size_t len, ostream* os) { PrintCharsAsStringTo(begin, len, os); } // Prints the given array of wide characters to the ostream. // The array starts at *begin, the length is len, it may include L'\0' // characters and may not be null-terminated. static void PrintWideCharsAsStringTo(const wchar_t* begin, size_t len, ostream* os) { *os << "L\""; bool is_previous_hex = false; for (size_t index = 0; index < len; ++index) { const wchar_t cur = begin[index]; if (is_previous_hex && isascii(cur) && IsXDigit(static_cast(cur))) { // Previous character is of '\x..' form and this character can be // interpreted as another hexadecimal digit in its number. Break string to // disambiguate. *os << "\" L\""; } is_previous_hex = PrintAsWideStringLiteralTo(cur, os) == kHexEscape; } *os << "\""; } // Prints the given C string to the ostream. void PrintTo(const char* s, ostream* os) { if (s == NULL) { *os << "NULL"; } else { *os << ImplicitCast_(s) << " pointing to "; PrintCharsAsStringTo(s, strlen(s), os); } } // MSVC compiler can be configured to define whar_t as a typedef // of unsigned short. Defining an overload for const wchar_t* in that case // would cause pointers to unsigned shorts be printed as wide strings, // possibly accessing more memory than intended and causing invalid // memory accesses. MSVC defines _NATIVE_WCHAR_T_DEFINED symbol when // wchar_t is implemented as a native type. #if !defined(_MSC_VER) || defined(_NATIVE_WCHAR_T_DEFINED) // Prints the given wide C string to the ostream. void PrintTo(const wchar_t* s, ostream* os) { if (s == NULL) { *os << "NULL"; } else { *os << ImplicitCast_(s) << " pointing to "; PrintWideCharsAsStringTo(s, wcslen(s), os); } } #endif // wchar_t is native // Prints a ::string object. #if GTEST_HAS_GLOBAL_STRING void PrintStringTo(const ::string& s, ostream* os) { PrintCharsAsStringTo(s.data(), s.size(), os); } #endif // GTEST_HAS_GLOBAL_STRING void PrintStringTo(const ::std::string& s, ostream* os) { PrintCharsAsStringTo(s.data(), s.size(), os); } // Prints a ::wstring object. #if GTEST_HAS_GLOBAL_WSTRING void PrintWideStringTo(const ::wstring& s, ostream* os) { PrintWideCharsAsStringTo(s.data(), s.size(), os); } #endif // GTEST_HAS_GLOBAL_WSTRING #if GTEST_HAS_STD_WSTRING void PrintWideStringTo(const ::std::wstring& s, ostream* os) { PrintWideCharsAsStringTo(s.data(), s.size(), os); } #endif // GTEST_HAS_STD_WSTRING } // namespace internal } // namespace testing // Copyright 2008, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: mheule@google.com (Markus Heule) // // The Google C++ Testing Framework (Google Test) // Indicates that this translation unit is part of Google Test's // implementation. It must come before gtest-internal-inl.h is // included, or there will be a compiler error. This trick is to // prevent a user from accidentally including gtest-internal-inl.h in // his code. #define GTEST_IMPLEMENTATION_ 1 #undef GTEST_IMPLEMENTATION_ namespace testing { using internal::GetUnitTestImpl; // Gets the summary of the failure message by omitting the stack trace // in it. internal::String TestPartResult::ExtractSummary(const char* message) { const char* const stack_trace = strstr(message, internal::kStackTraceMarker); return stack_trace == NULL ? internal::String(message) : internal::String(message, stack_trace - message); } // Prints a TestPartResult object. std::ostream& operator<<(std::ostream& os, const TestPartResult& result) { return os << result.file_name() << ":" << result.line_number() << ": " << (result.type() == TestPartResult::kSuccess ? "Success" : result.type() == TestPartResult::kFatalFailure ? "Fatal failure" : "Non-fatal failure") << ":\n" << result.message() << std::endl; } // Appends a TestPartResult to the array. void TestPartResultArray::Append(const TestPartResult& result) { array_.push_back(result); } // Returns the TestPartResult at the given index (0-based). const TestPartResult& TestPartResultArray::GetTestPartResult(int index) const { if (index < 0 || index >= size()) { printf("\nInvalid index (%d) into TestPartResultArray.\n", index); internal::posix::Abort(); } return array_[index]; } // Returns the number of TestPartResult objects in the array. int TestPartResultArray::size() const { return static_cast(array_.size()); } namespace internal { HasNewFatalFailureHelper::HasNewFatalFailureHelper() : has_new_fatal_failure_(false), original_reporter_(GetUnitTestImpl()-> GetTestPartResultReporterForCurrentThread()) { GetUnitTestImpl()->SetTestPartResultReporterForCurrentThread(this); } HasNewFatalFailureHelper::~HasNewFatalFailureHelper() { GetUnitTestImpl()->SetTestPartResultReporterForCurrentThread( original_reporter_); } void HasNewFatalFailureHelper::ReportTestPartResult( const TestPartResult& result) { if (result.fatally_failed()) has_new_fatal_failure_ = true; original_reporter_->ReportTestPartResult(result); } } // namespace internal } // namespace testing // Copyright 2008 Google Inc. // All Rights Reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan) namespace testing { namespace internal { #if GTEST_HAS_TYPED_TEST_P // Skips to the first non-space char in str. Returns an empty string if str // contains only whitespace characters. static const char* SkipSpaces(const char* str) { while (IsSpace(*str)) str++; return str; } // Verifies that registered_tests match the test names in // defined_test_names_; returns registered_tests if successful, or // aborts the program otherwise. const char* TypedTestCasePState::VerifyRegisteredTestNames( const char* file, int line, const char* registered_tests) { typedef ::std::set::const_iterator DefinedTestIter; registered_ = true; // Skip initial whitespace in registered_tests since some // preprocessors prefix stringizied literals with whitespace. registered_tests = SkipSpaces(registered_tests); Message errors; ::std::set tests; for (const char* names = registered_tests; names != NULL; names = SkipComma(names)) { const String name = GetPrefixUntilComma(names); if (tests.count(name) != 0) { errors << "Test " << name << " is listed more than once.\n"; continue; } bool found = false; for (DefinedTestIter it = defined_test_names_.begin(); it != defined_test_names_.end(); ++it) { if (name == *it) { found = true; break; } } if (found) { tests.insert(name); } else { errors << "No test named " << name << " can be found in this test case.\n"; } } for (DefinedTestIter it = defined_test_names_.begin(); it != defined_test_names_.end(); ++it) { if (tests.count(*it) == 0) { errors << "You forgot to list test " << *it << ".\n"; } } const String& errors_str = errors.GetString(); if (errors_str != "") { fprintf(stderr, "%s %s", FormatFileLocation(file, line).c_str(), errors_str.c_str()); fflush(stderr); posix::Abort(); } return registered_tests; } #endif // GTEST_HAS_TYPED_TEST_P } // namespace internal } // namespace testing ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/gtest-1.6.0/gtest/000077500000000000000000000000001446477712600237615ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/gtest-1.6.0/gtest/gtest.h000066400000000000000000030427531446477712600252760ustar00rootroot00000000000000// Copyright 2005, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan) // // The Google C++ Testing Framework (Google Test) // // This header file defines the public API for Google Test. It should be // included by any test program that uses Google Test. // // IMPORTANT NOTE: Due to limitation of the C++ language, we have to // leave some internal implementation details in this header file. // They are clearly marked by comments like this: // // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. // // Such code is NOT meant to be used by a user directly, and is subject // to CHANGE WITHOUT NOTICE. Therefore DO NOT DEPEND ON IT in a user // program! // // Acknowledgment: Google Test borrowed the idea of automatic test // registration from Barthelemy Dagenais' (barthelemy@prologique.com) // easyUnit framework. #ifndef GTEST_INCLUDE_GTEST_GTEST_H_ #define GTEST_INCLUDE_GTEST_GTEST_H_ #include #include #include // Copyright 2005, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Authors: wan@google.com (Zhanyong Wan), eefacm@gmail.com (Sean Mcafee) // // The Google C++ Testing Framework (Google Test) // // This header file declares functions and macros used internally by // Google Test. They are subject to change without notice. #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_INTERNAL_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_INTERNAL_H_ // Copyright 2005, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Authors: wan@google.com (Zhanyong Wan) // // Low-level types and utilities for porting Google Test to various // platforms. They are subject to change without notice. DO NOT USE // THEM IN USER CODE. #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_PORT_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_PORT_H_ // The user can define the following macros in the build script to // control Google Test's behavior. If the user doesn't define a macro // in this list, Google Test will define it. // // GTEST_HAS_CLONE - Define it to 1/0 to indicate that clone(2) // is/isn't available. // GTEST_HAS_EXCEPTIONS - Define it to 1/0 to indicate that exceptions // are enabled. // GTEST_HAS_GLOBAL_STRING - Define it to 1/0 to indicate that ::string // is/isn't available (some systems define // ::string, which is different to std::string). // GTEST_HAS_GLOBAL_WSTRING - Define it to 1/0 to indicate that ::string // is/isn't available (some systems define // ::wstring, which is different to std::wstring). // GTEST_HAS_POSIX_RE - Define it to 1/0 to indicate that POSIX regular // expressions are/aren't available. // GTEST_HAS_PTHREAD - Define it to 1/0 to indicate that // is/isn't available. // GTEST_HAS_RTTI - Define it to 1/0 to indicate that RTTI is/isn't // enabled. // GTEST_HAS_STD_WSTRING - Define it to 1/0 to indicate that // std::wstring does/doesn't work (Google Test can // be used where std::wstring is unavailable). // GTEST_HAS_TR1_TUPLE - Define it to 1/0 to indicate tr1::tuple // is/isn't available. // GTEST_HAS_SEH - Define it to 1/0 to indicate whether the // compiler supports Microsoft's "Structured // Exception Handling". // GTEST_HAS_STREAM_REDIRECTION // - Define it to 1/0 to indicate whether the // platform supports I/O stream redirection using // dup() and dup2(). // GTEST_USE_OWN_TR1_TUPLE - Define it to 1/0 to indicate whether Google // Test's own tr1 tuple implementation should be // used. Unused when the user sets // GTEST_HAS_TR1_TUPLE to 0. // GTEST_LINKED_AS_SHARED_LIBRARY // - Define to 1 when compiling tests that use // Google Test as a shared library (known as // DLL on Windows). // GTEST_CREATE_SHARED_LIBRARY // - Define to 1 when compiling Google Test itself // as a shared library. // This header defines the following utilities: // // Macros indicating the current platform (defined to 1 if compiled on // the given platform; otherwise undefined): // GTEST_OS_AIX - IBM AIX // GTEST_OS_CYGWIN - Cygwin // GTEST_OS_HPUX - HP-UX // GTEST_OS_LINUX - Linux // GTEST_OS_LINUX_ANDROID - Google Android // GTEST_OS_MAC - Mac OS X // GTEST_OS_NACL - Google Native Client (NaCl) // GTEST_OS_SOLARIS - Sun Solaris // GTEST_OS_SYMBIAN - Symbian // GTEST_OS_WINDOWS - Windows (Desktop, MinGW, or Mobile) // GTEST_OS_WINDOWS_DESKTOP - Windows Desktop // GTEST_OS_WINDOWS_MINGW - MinGW // GTEST_OS_WINDOWS_MOBILE - Windows Mobile // GTEST_OS_ZOS - z/OS // // Among the platforms, Cygwin, Linux, Max OS X, and Windows have the // most stable support. Since core members of the Google Test project // don't have access to other platforms, support for them may be less // stable. If you notice any problems on your platform, please notify // googletestframework@googlegroups.com (patches for fixing them are // even more welcome!). // // Note that it is possible that none of the GTEST_OS_* macros are defined. // // Macros indicating available Google Test features (defined to 1 if // the corresponding feature is supported; otherwise undefined): // GTEST_HAS_COMBINE - the Combine() function (for value-parameterized // tests) // GTEST_HAS_DEATH_TEST - death tests // GTEST_HAS_PARAM_TEST - value-parameterized tests // GTEST_HAS_TYPED_TEST - typed tests // GTEST_HAS_TYPED_TEST_P - type-parameterized tests // GTEST_USES_POSIX_RE - enhanced POSIX regex is used. Do not confuse with // GTEST_HAS_POSIX_RE (see above) which users can // define themselves. // GTEST_USES_SIMPLE_RE - our own simple regex is used; // the above two are mutually exclusive. // GTEST_CAN_COMPARE_NULL - accepts untyped NULL in EXPECT_EQ(). // // Macros for basic C++ coding: // GTEST_AMBIGUOUS_ELSE_BLOCKER_ - for disabling a gcc warning. // GTEST_ATTRIBUTE_UNUSED_ - declares that a class' instances or a // variable don't have to be used. // GTEST_DISALLOW_ASSIGN_ - disables operator=. // GTEST_DISALLOW_COPY_AND_ASSIGN_ - disables copy ctor and operator=. // GTEST_MUST_USE_RESULT_ - declares that a function's result must be used. // // Synchronization: // Mutex, MutexLock, ThreadLocal, GetThreadCount() // - synchronization primitives. // GTEST_IS_THREADSAFE - defined to 1 to indicate that the above // synchronization primitives have real implementations // and Google Test is thread-safe; or 0 otherwise. // // Template meta programming: // is_pointer - as in TR1; needed on Symbian and IBM XL C/C++ only. // IteratorTraits - partial implementation of std::iterator_traits, which // is not available in libCstd when compiled with Sun C++. // // Smart pointers: // scoped_ptr - as in TR2. // // Regular expressions: // RE - a simple regular expression class using the POSIX // Extended Regular Expression syntax on UNIX-like // platforms, or a reduced regular exception syntax on // other platforms, including Windows. // // Logging: // GTEST_LOG_() - logs messages at the specified severity level. // LogToStderr() - directs all log messages to stderr. // FlushInfoLog() - flushes informational log messages. // // Stdout and stderr capturing: // CaptureStdout() - starts capturing stdout. // GetCapturedStdout() - stops capturing stdout and returns the captured // string. // CaptureStderr() - starts capturing stderr. // GetCapturedStderr() - stops capturing stderr and returns the captured // string. // // Integer types: // TypeWithSize - maps an integer to a int type. // Int32, UInt32, Int64, UInt64, TimeInMillis // - integers of known sizes. // BiggestInt - the biggest signed integer type. // // Command-line utilities: // GTEST_FLAG() - references a flag. // GTEST_DECLARE_*() - declares a flag. // GTEST_DEFINE_*() - defines a flag. // GetArgvs() - returns the command line as a vector of strings. // // Environment variable utilities: // GetEnv() - gets the value of an environment variable. // BoolFromGTestEnv() - parses a bool environment variable. // Int32FromGTestEnv() - parses an Int32 environment variable. // StringFromGTestEnv() - parses a string environment variable. #include // for isspace, etc #include // for ptrdiff_t #include #include #include #ifndef _WIN32_WCE # include # include #endif // !_WIN32_WCE #include // NOLINT #include // NOLINT #include // NOLINT #define GTEST_DEV_EMAIL_ "googletestframework@@googlegroups.com" #define GTEST_FLAG_PREFIX_ "gtest_" #define GTEST_FLAG_PREFIX_DASH_ "gtest-" #define GTEST_FLAG_PREFIX_UPPER_ "GTEST_" #define GTEST_NAME_ "Google Test" #define GTEST_PROJECT_URL_ "http://code.google.com/p/googletest/" // Determines the version of gcc that is used to compile this. #ifdef __GNUC__ // 40302 means version 4.3.2. # define GTEST_GCC_VER_ \ (__GNUC__*10000 + __GNUC_MINOR__*100 + __GNUC_PATCHLEVEL__) #endif // __GNUC__ // Determines the platform on which Google Test is compiled. #ifdef __CYGWIN__ # define GTEST_OS_CYGWIN 1 #elif defined __SYMBIAN32__ # define GTEST_OS_SYMBIAN 1 #elif defined _WIN32 # define GTEST_OS_WINDOWS 1 # ifdef _WIN32_WCE # define GTEST_OS_WINDOWS_MOBILE 1 # elif defined(__MINGW__) || defined(__MINGW32__) # define GTEST_OS_WINDOWS_MINGW 1 # else # define GTEST_OS_WINDOWS_DESKTOP 1 # endif // _WIN32_WCE #elif defined __APPLE__ # define GTEST_OS_MAC 1 #elif defined __linux__ # define GTEST_OS_LINUX 1 # ifdef ANDROID # define GTEST_OS_LINUX_ANDROID 1 # endif // ANDROID #elif defined __MVS__ # define GTEST_OS_ZOS 1 #elif defined(__sun) && defined(__SVR4) # define GTEST_OS_SOLARIS 1 #elif defined(_AIX) # define GTEST_OS_AIX 1 #elif defined(__hpux) # define GTEST_OS_HPUX 1 #elif defined __native_client__ # define GTEST_OS_NACL 1 #endif // __CYGWIN__ // Brings in definitions for functions used in the testing::internal::posix // namespace (read, write, close, chdir, isatty, stat). We do not currently // use them on Windows Mobile. #if !GTEST_OS_WINDOWS // This assumes that non-Windows OSes provide unistd.h. For OSes where this // is not the case, we need to include headers that provide the functions // mentioned above. # include # if !GTEST_OS_NACL // TODO(vladl@google.com): Remove this condition when Native Client SDK adds // strings.h (tracked in // http://code.google.com/p/nativeclient/issues/detail?id=1175). # include // Native Client doesn't provide strings.h. # endif #elif !GTEST_OS_WINDOWS_MOBILE # include # include #endif #if defined(_MSC_VER) # include #endif // Defines this to true iff Google Test can use POSIX regular expressions. #ifndef GTEST_HAS_POSIX_RE # define GTEST_HAS_POSIX_RE (!GTEST_OS_WINDOWS) #endif #if GTEST_HAS_POSIX_RE // On some platforms, needs someone to define size_t, and // won't compile otherwise. We can #include it here as we already // included , which is guaranteed to define size_t through // . # include // NOLINT # define GTEST_USES_POSIX_RE 1 #elif GTEST_OS_WINDOWS // is not available on Windows. Use our own simple regex // implementation instead. # define GTEST_USES_SIMPLE_RE 1 #else // may not be available on this platform. Use our own // simple regex implementation instead. # define GTEST_USES_SIMPLE_RE 1 #endif // GTEST_HAS_POSIX_RE #ifndef GTEST_HAS_EXCEPTIONS // The user didn't tell us whether exceptions are enabled, so we need // to figure it out. # if defined(_MSC_VER) || defined(__BORLANDC__) // MSVC's and C++Builder's implementations of the STL use the _HAS_EXCEPTIONS // macro to enable exceptions, so we'll do the same. // Assumes that exceptions are enabled by default. # ifndef _HAS_EXCEPTIONS # define _HAS_EXCEPTIONS 1 # endif // _HAS_EXCEPTIONS # define GTEST_HAS_EXCEPTIONS _HAS_EXCEPTIONS # elif defined(__GNUC__) && __EXCEPTIONS // gcc defines __EXCEPTIONS to 1 iff exceptions are enabled. # define GTEST_HAS_EXCEPTIONS 1 # elif defined(__SUNPRO_CC) // Sun Pro CC supports exceptions. However, there is no compile-time way of // detecting whether they are enabled or not. Therefore, we assume that // they are enabled unless the user tells us otherwise. # define GTEST_HAS_EXCEPTIONS 1 # elif defined(__IBMCPP__) && __EXCEPTIONS // xlC defines __EXCEPTIONS to 1 iff exceptions are enabled. # define GTEST_HAS_EXCEPTIONS 1 # elif defined(__HP_aCC) // Exception handling is in effect by default in HP aCC compiler. It has to // be turned of by +noeh compiler option if desired. # define GTEST_HAS_EXCEPTIONS 1 # else // For other compilers, we assume exceptions are disabled to be // conservative. # define GTEST_HAS_EXCEPTIONS 0 # endif // defined(_MSC_VER) || defined(__BORLANDC__) #endif // GTEST_HAS_EXCEPTIONS #if !defined(GTEST_HAS_STD_STRING) // Even though we don't use this macro any longer, we keep it in case // some clients still depend on it. # define GTEST_HAS_STD_STRING 1 #elif !GTEST_HAS_STD_STRING // The user told us that ::std::string isn't available. # error "Google Test cannot be used where ::std::string isn't available." #endif // !defined(GTEST_HAS_STD_STRING) #ifndef GTEST_HAS_GLOBAL_STRING // The user didn't tell us whether ::string is available, so we need // to figure it out. # define GTEST_HAS_GLOBAL_STRING 0 #endif // GTEST_HAS_GLOBAL_STRING #ifndef GTEST_HAS_STD_WSTRING // The user didn't tell us whether ::std::wstring is available, so we need // to figure it out. // TODO(wan@google.com): uses autoconf to detect whether ::std::wstring // is available. // Cygwin 1.7 and below doesn't support ::std::wstring. // Solaris' libc++ doesn't support it either. Android has // no support for it at least as recent as Froyo (2.2). # define GTEST_HAS_STD_WSTRING \ (!(GTEST_OS_LINUX_ANDROID || GTEST_OS_CYGWIN || GTEST_OS_SOLARIS)) #endif // GTEST_HAS_STD_WSTRING #ifndef GTEST_HAS_GLOBAL_WSTRING // The user didn't tell us whether ::wstring is available, so we need // to figure it out. # define GTEST_HAS_GLOBAL_WSTRING \ (GTEST_HAS_STD_WSTRING && GTEST_HAS_GLOBAL_STRING) #endif // GTEST_HAS_GLOBAL_WSTRING // Determines whether RTTI is available. #ifndef GTEST_HAS_RTTI // The user didn't tell us whether RTTI is enabled, so we need to // figure it out. # ifdef _MSC_VER # ifdef _CPPRTTI // MSVC defines this macro iff RTTI is enabled. # define GTEST_HAS_RTTI 1 # else # define GTEST_HAS_RTTI 0 # endif // Starting with version 4.3.2, gcc defines __GXX_RTTI iff RTTI is enabled. # elif defined(__GNUC__) && (GTEST_GCC_VER_ >= 40302) # ifdef __GXX_RTTI # define GTEST_HAS_RTTI 1 # else # define GTEST_HAS_RTTI 0 # endif // __GXX_RTTI // Starting with version 9.0 IBM Visual Age defines __RTTI_ALL__ to 1 if // both the typeid and dynamic_cast features are present. # elif defined(__IBMCPP__) && (__IBMCPP__ >= 900) # ifdef __RTTI_ALL__ # define GTEST_HAS_RTTI 1 # else # define GTEST_HAS_RTTI 0 # endif # else // For all other compilers, we assume RTTI is enabled. # define GTEST_HAS_RTTI 1 # endif // _MSC_VER #endif // GTEST_HAS_RTTI // It's this header's responsibility to #include when RTTI // is enabled. #if GTEST_HAS_RTTI # include #endif // Determines whether Google Test can use the pthreads library. #ifndef GTEST_HAS_PTHREAD // The user didn't tell us explicitly, so we assume pthreads support is // available on Linux and Mac. // // To disable threading support in Google Test, add -DGTEST_HAS_PTHREAD=0 // to your compiler flags. # define GTEST_HAS_PTHREAD (GTEST_OS_LINUX || GTEST_OS_MAC || GTEST_OS_HPUX) #endif // GTEST_HAS_PTHREAD #if GTEST_HAS_PTHREAD // gtest-port.h guarantees to #include when GTEST_HAS_PTHREAD is // true. # include // NOLINT // For timespec and nanosleep, used below. # include // NOLINT #endif // Determines whether Google Test can use tr1/tuple. You can define // this macro to 0 to prevent Google Test from using tuple (any // feature depending on tuple with be disabled in this mode). #ifndef GTEST_HAS_TR1_TUPLE // The user didn't tell us not to do it, so we assume it's OK. # define GTEST_HAS_TR1_TUPLE 0 #endif // GTEST_HAS_TR1_TUPLE // Determines whether Google Test's own tr1 tuple implementation // should be used. #ifndef GTEST_USE_OWN_TR1_TUPLE // The user didn't tell us, so we need to figure it out. // We use our own TR1 tuple if we aren't sure the user has an // implementation of it already. At this time, GCC 4.0.0+ and MSVC // 2010 are the only mainstream compilers that come with a TR1 tuple // implementation. NVIDIA's CUDA NVCC compiler pretends to be GCC by // defining __GNUC__ and friends, but cannot compile GCC's tuple // implementation. MSVC 2008 (9.0) provides TR1 tuple in a 323 MB // Feature Pack download, which we cannot assume the user has. # if (defined(__GNUC__) && !defined(__CUDACC__) && (GTEST_GCC_VER_ >= 40000)) \ || _MSC_VER >= 1600 # define GTEST_USE_OWN_TR1_TUPLE 0 # else # define GTEST_USE_OWN_TR1_TUPLE 1 # endif #endif // GTEST_USE_OWN_TR1_TUPLE // To avoid conditional compilation everywhere, we make it // gtest-port.h's responsibility to #include the header implementing // tr1/tuple. #if GTEST_HAS_TR1_TUPLE # if GTEST_USE_OWN_TR1_TUPLE // This file was GENERATED by a script. DO NOT EDIT BY HAND!!! // Copyright 2009 Google Inc. // All Rights Reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan) // Implements a subset of TR1 tuple needed by Google Test and Google Mock. #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_TUPLE_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_TUPLE_H_ #include // For ::std::pair. // The compiler used in Symbian has a bug that prevents us from declaring the // tuple template as a friend (it complains that tuple is redefined). This // hack bypasses the bug by declaring the members that should otherwise be // private as public. // Sun Studio versions < 12 also have the above bug. #if defined(__SYMBIAN32__) || (defined(__SUNPRO_CC) && __SUNPRO_CC < 0x590) # define GTEST_DECLARE_TUPLE_AS_FRIEND_ public: #else # define GTEST_DECLARE_TUPLE_AS_FRIEND_ \ template friend class tuple; \ private: #endif // GTEST_n_TUPLE_(T) is the type of an n-tuple. #define GTEST_0_TUPLE_(T) tuple<> #define GTEST_1_TUPLE_(T) tuple #define GTEST_2_TUPLE_(T) tuple #define GTEST_3_TUPLE_(T) tuple #define GTEST_4_TUPLE_(T) tuple #define GTEST_5_TUPLE_(T) tuple #define GTEST_6_TUPLE_(T) tuple #define GTEST_7_TUPLE_(T) tuple #define GTEST_8_TUPLE_(T) tuple #define GTEST_9_TUPLE_(T) tuple #define GTEST_10_TUPLE_(T) tuple // GTEST_n_TYPENAMES_(T) declares a list of n typenames. #define GTEST_0_TYPENAMES_(T) #define GTEST_1_TYPENAMES_(T) typename T##0 #define GTEST_2_TYPENAMES_(T) typename T##0, typename T##1 #define GTEST_3_TYPENAMES_(T) typename T##0, typename T##1, typename T##2 #define GTEST_4_TYPENAMES_(T) typename T##0, typename T##1, typename T##2, \ typename T##3 #define GTEST_5_TYPENAMES_(T) typename T##0, typename T##1, typename T##2, \ typename T##3, typename T##4 #define GTEST_6_TYPENAMES_(T) typename T##0, typename T##1, typename T##2, \ typename T##3, typename T##4, typename T##5 #define GTEST_7_TYPENAMES_(T) typename T##0, typename T##1, typename T##2, \ typename T##3, typename T##4, typename T##5, typename T##6 #define GTEST_8_TYPENAMES_(T) typename T##0, typename T##1, typename T##2, \ typename T##3, typename T##4, typename T##5, typename T##6, typename T##7 #define GTEST_9_TYPENAMES_(T) typename T##0, typename T##1, typename T##2, \ typename T##3, typename T##4, typename T##5, typename T##6, \ typename T##7, typename T##8 #define GTEST_10_TYPENAMES_(T) typename T##0, typename T##1, typename T##2, \ typename T##3, typename T##4, typename T##5, typename T##6, \ typename T##7, typename T##8, typename T##9 // In theory, defining stuff in the ::std namespace is undefined // behavior. We can do this as we are playing the role of a standard // library vendor. namespace std { namespace tr1 { template class tuple; // Anything in namespace gtest_internal is Google Test's INTERNAL // IMPLEMENTATION DETAIL and MUST NOT BE USED DIRECTLY in user code. namespace gtest_internal { // ByRef::type is T if T is a reference; otherwise it's const T&. template struct ByRef { typedef const T& type; }; // NOLINT template struct ByRef { typedef T& type; }; // NOLINT // A handy wrapper for ByRef. #define GTEST_BY_REF_(T) typename ::std::tr1::gtest_internal::ByRef::type // AddRef::type is T if T is a reference; otherwise it's T&. This // is the same as tr1::add_reference::type. template struct AddRef { typedef T& type; }; // NOLINT template struct AddRef { typedef T& type; }; // NOLINT // A handy wrapper for AddRef. #define GTEST_ADD_REF_(T) typename ::std::tr1::gtest_internal::AddRef::type // A helper for implementing get(). template class Get; // A helper for implementing tuple_element. kIndexValid is true // iff k < the number of fields in tuple type T. template struct TupleElement; template struct TupleElement { typedef T0 type; }; template struct TupleElement { typedef T1 type; }; template struct TupleElement { typedef T2 type; }; template struct TupleElement { typedef T3 type; }; template struct TupleElement { typedef T4 type; }; template struct TupleElement { typedef T5 type; }; template struct TupleElement { typedef T6 type; }; template struct TupleElement { typedef T7 type; }; template struct TupleElement { typedef T8 type; }; template struct TupleElement { typedef T9 type; }; } // namespace gtest_internal template <> class tuple<> { public: tuple() {} tuple(const tuple& /* t */) {} tuple& operator=(const tuple& /* t */) { return *this; } }; template class GTEST_1_TUPLE_(T) { public: template friend class gtest_internal::Get; tuple() : f0_() {} explicit tuple(GTEST_BY_REF_(T0) f0) : f0_(f0) {} tuple(const tuple& t) : f0_(t.f0_) {} template tuple(const GTEST_1_TUPLE_(U)& t) : f0_(t.f0_) {} tuple& operator=(const tuple& t) { return CopyFrom(t); } template tuple& operator=(const GTEST_1_TUPLE_(U)& t) { return CopyFrom(t); } GTEST_DECLARE_TUPLE_AS_FRIEND_ template tuple& CopyFrom(const GTEST_1_TUPLE_(U)& t) { f0_ = t.f0_; return *this; } T0 f0_; }; template class GTEST_2_TUPLE_(T) { public: template friend class gtest_internal::Get; tuple() : f0_(), f1_() {} explicit tuple(GTEST_BY_REF_(T0) f0, GTEST_BY_REF_(T1) f1) : f0_(f0), f1_(f1) {} tuple(const tuple& t) : f0_(t.f0_), f1_(t.f1_) {} template tuple(const GTEST_2_TUPLE_(U)& t) : f0_(t.f0_), f1_(t.f1_) {} template tuple(const ::std::pair& p) : f0_(p.first), f1_(p.second) {} tuple& operator=(const tuple& t) { return CopyFrom(t); } template tuple& operator=(const GTEST_2_TUPLE_(U)& t) { return CopyFrom(t); } template tuple& operator=(const ::std::pair& p) { f0_ = p.first; f1_ = p.second; return *this; } GTEST_DECLARE_TUPLE_AS_FRIEND_ template tuple& CopyFrom(const GTEST_2_TUPLE_(U)& t) { f0_ = t.f0_; f1_ = t.f1_; return *this; } T0 f0_; T1 f1_; }; template class GTEST_3_TUPLE_(T) { public: template friend class gtest_internal::Get; tuple() : f0_(), f1_(), f2_() {} explicit tuple(GTEST_BY_REF_(T0) f0, GTEST_BY_REF_(T1) f1, GTEST_BY_REF_(T2) f2) : f0_(f0), f1_(f1), f2_(f2) {} tuple(const tuple& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_) {} template tuple(const GTEST_3_TUPLE_(U)& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_) {} tuple& operator=(const tuple& t) { return CopyFrom(t); } template tuple& operator=(const GTEST_3_TUPLE_(U)& t) { return CopyFrom(t); } GTEST_DECLARE_TUPLE_AS_FRIEND_ template tuple& CopyFrom(const GTEST_3_TUPLE_(U)& t) { f0_ = t.f0_; f1_ = t.f1_; f2_ = t.f2_; return *this; } T0 f0_; T1 f1_; T2 f2_; }; template class GTEST_4_TUPLE_(T) { public: template friend class gtest_internal::Get; tuple() : f0_(), f1_(), f2_(), f3_() {} explicit tuple(GTEST_BY_REF_(T0) f0, GTEST_BY_REF_(T1) f1, GTEST_BY_REF_(T2) f2, GTEST_BY_REF_(T3) f3) : f0_(f0), f1_(f1), f2_(f2), f3_(f3) {} tuple(const tuple& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_) {} template tuple(const GTEST_4_TUPLE_(U)& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_) {} tuple& operator=(const tuple& t) { return CopyFrom(t); } template tuple& operator=(const GTEST_4_TUPLE_(U)& t) { return CopyFrom(t); } GTEST_DECLARE_TUPLE_AS_FRIEND_ template tuple& CopyFrom(const GTEST_4_TUPLE_(U)& t) { f0_ = t.f0_; f1_ = t.f1_; f2_ = t.f2_; f3_ = t.f3_; return *this; } T0 f0_; T1 f1_; T2 f2_; T3 f3_; }; template class GTEST_5_TUPLE_(T) { public: template friend class gtest_internal::Get; tuple() : f0_(), f1_(), f2_(), f3_(), f4_() {} explicit tuple(GTEST_BY_REF_(T0) f0, GTEST_BY_REF_(T1) f1, GTEST_BY_REF_(T2) f2, GTEST_BY_REF_(T3) f3, GTEST_BY_REF_(T4) f4) : f0_(f0), f1_(f1), f2_(f2), f3_(f3), f4_(f4) {} tuple(const tuple& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_), f4_(t.f4_) {} template tuple(const GTEST_5_TUPLE_(U)& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_), f4_(t.f4_) {} tuple& operator=(const tuple& t) { return CopyFrom(t); } template tuple& operator=(const GTEST_5_TUPLE_(U)& t) { return CopyFrom(t); } GTEST_DECLARE_TUPLE_AS_FRIEND_ template tuple& CopyFrom(const GTEST_5_TUPLE_(U)& t) { f0_ = t.f0_; f1_ = t.f1_; f2_ = t.f2_; f3_ = t.f3_; f4_ = t.f4_; return *this; } T0 f0_; T1 f1_; T2 f2_; T3 f3_; T4 f4_; }; template class GTEST_6_TUPLE_(T) { public: template friend class gtest_internal::Get; tuple() : f0_(), f1_(), f2_(), f3_(), f4_(), f5_() {} explicit tuple(GTEST_BY_REF_(T0) f0, GTEST_BY_REF_(T1) f1, GTEST_BY_REF_(T2) f2, GTEST_BY_REF_(T3) f3, GTEST_BY_REF_(T4) f4, GTEST_BY_REF_(T5) f5) : f0_(f0), f1_(f1), f2_(f2), f3_(f3), f4_(f4), f5_(f5) {} tuple(const tuple& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_), f4_(t.f4_), f5_(t.f5_) {} template tuple(const GTEST_6_TUPLE_(U)& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_), f4_(t.f4_), f5_(t.f5_) {} tuple& operator=(const tuple& t) { return CopyFrom(t); } template tuple& operator=(const GTEST_6_TUPLE_(U)& t) { return CopyFrom(t); } GTEST_DECLARE_TUPLE_AS_FRIEND_ template tuple& CopyFrom(const GTEST_6_TUPLE_(U)& t) { f0_ = t.f0_; f1_ = t.f1_; f2_ = t.f2_; f3_ = t.f3_; f4_ = t.f4_; f5_ = t.f5_; return *this; } T0 f0_; T1 f1_; T2 f2_; T3 f3_; T4 f4_; T5 f5_; }; template class GTEST_7_TUPLE_(T) { public: template friend class gtest_internal::Get; tuple() : f0_(), f1_(), f2_(), f3_(), f4_(), f5_(), f6_() {} explicit tuple(GTEST_BY_REF_(T0) f0, GTEST_BY_REF_(T1) f1, GTEST_BY_REF_(T2) f2, GTEST_BY_REF_(T3) f3, GTEST_BY_REF_(T4) f4, GTEST_BY_REF_(T5) f5, GTEST_BY_REF_(T6) f6) : f0_(f0), f1_(f1), f2_(f2), f3_(f3), f4_(f4), f5_(f5), f6_(f6) {} tuple(const tuple& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_), f4_(t.f4_), f5_(t.f5_), f6_(t.f6_) {} template tuple(const GTEST_7_TUPLE_(U)& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_), f4_(t.f4_), f5_(t.f5_), f6_(t.f6_) {} tuple& operator=(const tuple& t) { return CopyFrom(t); } template tuple& operator=(const GTEST_7_TUPLE_(U)& t) { return CopyFrom(t); } GTEST_DECLARE_TUPLE_AS_FRIEND_ template tuple& CopyFrom(const GTEST_7_TUPLE_(U)& t) { f0_ = t.f0_; f1_ = t.f1_; f2_ = t.f2_; f3_ = t.f3_; f4_ = t.f4_; f5_ = t.f5_; f6_ = t.f6_; return *this; } T0 f0_; T1 f1_; T2 f2_; T3 f3_; T4 f4_; T5 f5_; T6 f6_; }; template class GTEST_8_TUPLE_(T) { public: template friend class gtest_internal::Get; tuple() : f0_(), f1_(), f2_(), f3_(), f4_(), f5_(), f6_(), f7_() {} explicit tuple(GTEST_BY_REF_(T0) f0, GTEST_BY_REF_(T1) f1, GTEST_BY_REF_(T2) f2, GTEST_BY_REF_(T3) f3, GTEST_BY_REF_(T4) f4, GTEST_BY_REF_(T5) f5, GTEST_BY_REF_(T6) f6, GTEST_BY_REF_(T7) f7) : f0_(f0), f1_(f1), f2_(f2), f3_(f3), f4_(f4), f5_(f5), f6_(f6), f7_(f7) {} tuple(const tuple& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_), f4_(t.f4_), f5_(t.f5_), f6_(t.f6_), f7_(t.f7_) {} template tuple(const GTEST_8_TUPLE_(U)& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_), f4_(t.f4_), f5_(t.f5_), f6_(t.f6_), f7_(t.f7_) {} tuple& operator=(const tuple& t) { return CopyFrom(t); } template tuple& operator=(const GTEST_8_TUPLE_(U)& t) { return CopyFrom(t); } GTEST_DECLARE_TUPLE_AS_FRIEND_ template tuple& CopyFrom(const GTEST_8_TUPLE_(U)& t) { f0_ = t.f0_; f1_ = t.f1_; f2_ = t.f2_; f3_ = t.f3_; f4_ = t.f4_; f5_ = t.f5_; f6_ = t.f6_; f7_ = t.f7_; return *this; } T0 f0_; T1 f1_; T2 f2_; T3 f3_; T4 f4_; T5 f5_; T6 f6_; T7 f7_; }; template class GTEST_9_TUPLE_(T) { public: template friend class gtest_internal::Get; tuple() : f0_(), f1_(), f2_(), f3_(), f4_(), f5_(), f6_(), f7_(), f8_() {} explicit tuple(GTEST_BY_REF_(T0) f0, GTEST_BY_REF_(T1) f1, GTEST_BY_REF_(T2) f2, GTEST_BY_REF_(T3) f3, GTEST_BY_REF_(T4) f4, GTEST_BY_REF_(T5) f5, GTEST_BY_REF_(T6) f6, GTEST_BY_REF_(T7) f7, GTEST_BY_REF_(T8) f8) : f0_(f0), f1_(f1), f2_(f2), f3_(f3), f4_(f4), f5_(f5), f6_(f6), f7_(f7), f8_(f8) {} tuple(const tuple& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_), f4_(t.f4_), f5_(t.f5_), f6_(t.f6_), f7_(t.f7_), f8_(t.f8_) {} template tuple(const GTEST_9_TUPLE_(U)& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_), f4_(t.f4_), f5_(t.f5_), f6_(t.f6_), f7_(t.f7_), f8_(t.f8_) {} tuple& operator=(const tuple& t) { return CopyFrom(t); } template tuple& operator=(const GTEST_9_TUPLE_(U)& t) { return CopyFrom(t); } GTEST_DECLARE_TUPLE_AS_FRIEND_ template tuple& CopyFrom(const GTEST_9_TUPLE_(U)& t) { f0_ = t.f0_; f1_ = t.f1_; f2_ = t.f2_; f3_ = t.f3_; f4_ = t.f4_; f5_ = t.f5_; f6_ = t.f6_; f7_ = t.f7_; f8_ = t.f8_; return *this; } T0 f0_; T1 f1_; T2 f2_; T3 f3_; T4 f4_; T5 f5_; T6 f6_; T7 f7_; T8 f8_; }; template class tuple { public: template friend class gtest_internal::Get; tuple() : f0_(), f1_(), f2_(), f3_(), f4_(), f5_(), f6_(), f7_(), f8_(), f9_() {} explicit tuple(GTEST_BY_REF_(T0) f0, GTEST_BY_REF_(T1) f1, GTEST_BY_REF_(T2) f2, GTEST_BY_REF_(T3) f3, GTEST_BY_REF_(T4) f4, GTEST_BY_REF_(T5) f5, GTEST_BY_REF_(T6) f6, GTEST_BY_REF_(T7) f7, GTEST_BY_REF_(T8) f8, GTEST_BY_REF_(T9) f9) : f0_(f0), f1_(f1), f2_(f2), f3_(f3), f4_(f4), f5_(f5), f6_(f6), f7_(f7), f8_(f8), f9_(f9) {} tuple(const tuple& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_), f4_(t.f4_), f5_(t.f5_), f6_(t.f6_), f7_(t.f7_), f8_(t.f8_), f9_(t.f9_) {} template tuple(const GTEST_10_TUPLE_(U)& t) : f0_(t.f0_), f1_(t.f1_), f2_(t.f2_), f3_(t.f3_), f4_(t.f4_), f5_(t.f5_), f6_(t.f6_), f7_(t.f7_), f8_(t.f8_), f9_(t.f9_) {} tuple& operator=(const tuple& t) { return CopyFrom(t); } template tuple& operator=(const GTEST_10_TUPLE_(U)& t) { return CopyFrom(t); } GTEST_DECLARE_TUPLE_AS_FRIEND_ template tuple& CopyFrom(const GTEST_10_TUPLE_(U)& t) { f0_ = t.f0_; f1_ = t.f1_; f2_ = t.f2_; f3_ = t.f3_; f4_ = t.f4_; f5_ = t.f5_; f6_ = t.f6_; f7_ = t.f7_; f8_ = t.f8_; f9_ = t.f9_; return *this; } T0 f0_; T1 f1_; T2 f2_; T3 f3_; T4 f4_; T5 f5_; T6 f6_; T7 f7_; T8 f8_; T9 f9_; }; // 6.1.3.2 Tuple creation functions. // Known limitations: we don't support passing an // std::tr1::reference_wrapper to make_tuple(). And we don't // implement tie(). inline tuple<> make_tuple() { return tuple<>(); } template inline GTEST_1_TUPLE_(T) make_tuple(const T0& f0) { return GTEST_1_TUPLE_(T)(f0); } template inline GTEST_2_TUPLE_(T) make_tuple(const T0& f0, const T1& f1) { return GTEST_2_TUPLE_(T)(f0, f1); } template inline GTEST_3_TUPLE_(T) make_tuple(const T0& f0, const T1& f1, const T2& f2) { return GTEST_3_TUPLE_(T)(f0, f1, f2); } template inline GTEST_4_TUPLE_(T) make_tuple(const T0& f0, const T1& f1, const T2& f2, const T3& f3) { return GTEST_4_TUPLE_(T)(f0, f1, f2, f3); } template inline GTEST_5_TUPLE_(T) make_tuple(const T0& f0, const T1& f1, const T2& f2, const T3& f3, const T4& f4) { return GTEST_5_TUPLE_(T)(f0, f1, f2, f3, f4); } template inline GTEST_6_TUPLE_(T) make_tuple(const T0& f0, const T1& f1, const T2& f2, const T3& f3, const T4& f4, const T5& f5) { return GTEST_6_TUPLE_(T)(f0, f1, f2, f3, f4, f5); } template inline GTEST_7_TUPLE_(T) make_tuple(const T0& f0, const T1& f1, const T2& f2, const T3& f3, const T4& f4, const T5& f5, const T6& f6) { return GTEST_7_TUPLE_(T)(f0, f1, f2, f3, f4, f5, f6); } template inline GTEST_8_TUPLE_(T) make_tuple(const T0& f0, const T1& f1, const T2& f2, const T3& f3, const T4& f4, const T5& f5, const T6& f6, const T7& f7) { return GTEST_8_TUPLE_(T)(f0, f1, f2, f3, f4, f5, f6, f7); } template inline GTEST_9_TUPLE_(T) make_tuple(const T0& f0, const T1& f1, const T2& f2, const T3& f3, const T4& f4, const T5& f5, const T6& f6, const T7& f7, const T8& f8) { return GTEST_9_TUPLE_(T)(f0, f1, f2, f3, f4, f5, f6, f7, f8); } template inline GTEST_10_TUPLE_(T) make_tuple(const T0& f0, const T1& f1, const T2& f2, const T3& f3, const T4& f4, const T5& f5, const T6& f6, const T7& f7, const T8& f8, const T9& f9) { return GTEST_10_TUPLE_(T)(f0, f1, f2, f3, f4, f5, f6, f7, f8, f9); } // 6.1.3.3 Tuple helper classes. template struct tuple_size; template struct tuple_size { static const int value = 0; }; template struct tuple_size { static const int value = 1; }; template struct tuple_size { static const int value = 2; }; template struct tuple_size { static const int value = 3; }; template struct tuple_size { static const int value = 4; }; template struct tuple_size { static const int value = 5; }; template struct tuple_size { static const int value = 6; }; template struct tuple_size { static const int value = 7; }; template struct tuple_size { static const int value = 8; }; template struct tuple_size { static const int value = 9; }; template struct tuple_size { static const int value = 10; }; template struct tuple_element { typedef typename gtest_internal::TupleElement< k < (tuple_size::value), k, Tuple>::type type; }; #define GTEST_TUPLE_ELEMENT_(k, Tuple) typename tuple_element::type // 6.1.3.4 Element access. namespace gtest_internal { template <> class Get<0> { public: template static GTEST_ADD_REF_(GTEST_TUPLE_ELEMENT_(0, Tuple)) Field(Tuple& t) { return t.f0_; } // NOLINT template static GTEST_BY_REF_(GTEST_TUPLE_ELEMENT_(0, Tuple)) ConstField(const Tuple& t) { return t.f0_; } }; template <> class Get<1> { public: template static GTEST_ADD_REF_(GTEST_TUPLE_ELEMENT_(1, Tuple)) Field(Tuple& t) { return t.f1_; } // NOLINT template static GTEST_BY_REF_(GTEST_TUPLE_ELEMENT_(1, Tuple)) ConstField(const Tuple& t) { return t.f1_; } }; template <> class Get<2> { public: template static GTEST_ADD_REF_(GTEST_TUPLE_ELEMENT_(2, Tuple)) Field(Tuple& t) { return t.f2_; } // NOLINT template static GTEST_BY_REF_(GTEST_TUPLE_ELEMENT_(2, Tuple)) ConstField(const Tuple& t) { return t.f2_; } }; template <> class Get<3> { public: template static GTEST_ADD_REF_(GTEST_TUPLE_ELEMENT_(3, Tuple)) Field(Tuple& t) { return t.f3_; } // NOLINT template static GTEST_BY_REF_(GTEST_TUPLE_ELEMENT_(3, Tuple)) ConstField(const Tuple& t) { return t.f3_; } }; template <> class Get<4> { public: template static GTEST_ADD_REF_(GTEST_TUPLE_ELEMENT_(4, Tuple)) Field(Tuple& t) { return t.f4_; } // NOLINT template static GTEST_BY_REF_(GTEST_TUPLE_ELEMENT_(4, Tuple)) ConstField(const Tuple& t) { return t.f4_; } }; template <> class Get<5> { public: template static GTEST_ADD_REF_(GTEST_TUPLE_ELEMENT_(5, Tuple)) Field(Tuple& t) { return t.f5_; } // NOLINT template static GTEST_BY_REF_(GTEST_TUPLE_ELEMENT_(5, Tuple)) ConstField(const Tuple& t) { return t.f5_; } }; template <> class Get<6> { public: template static GTEST_ADD_REF_(GTEST_TUPLE_ELEMENT_(6, Tuple)) Field(Tuple& t) { return t.f6_; } // NOLINT template static GTEST_BY_REF_(GTEST_TUPLE_ELEMENT_(6, Tuple)) ConstField(const Tuple& t) { return t.f6_; } }; template <> class Get<7> { public: template static GTEST_ADD_REF_(GTEST_TUPLE_ELEMENT_(7, Tuple)) Field(Tuple& t) { return t.f7_; } // NOLINT template static GTEST_BY_REF_(GTEST_TUPLE_ELEMENT_(7, Tuple)) ConstField(const Tuple& t) { return t.f7_; } }; template <> class Get<8> { public: template static GTEST_ADD_REF_(GTEST_TUPLE_ELEMENT_(8, Tuple)) Field(Tuple& t) { return t.f8_; } // NOLINT template static GTEST_BY_REF_(GTEST_TUPLE_ELEMENT_(8, Tuple)) ConstField(const Tuple& t) { return t.f8_; } }; template <> class Get<9> { public: template static GTEST_ADD_REF_(GTEST_TUPLE_ELEMENT_(9, Tuple)) Field(Tuple& t) { return t.f9_; } // NOLINT template static GTEST_BY_REF_(GTEST_TUPLE_ELEMENT_(9, Tuple)) ConstField(const Tuple& t) { return t.f9_; } }; } // namespace gtest_internal template GTEST_ADD_REF_(GTEST_TUPLE_ELEMENT_(k, GTEST_10_TUPLE_(T))) get(GTEST_10_TUPLE_(T)& t) { return gtest_internal::Get::Field(t); } template GTEST_BY_REF_(GTEST_TUPLE_ELEMENT_(k, GTEST_10_TUPLE_(T))) get(const GTEST_10_TUPLE_(T)& t) { return gtest_internal::Get::ConstField(t); } // 6.1.3.5 Relational operators // We only implement == and !=, as we don't have a need for the rest yet. namespace gtest_internal { // SameSizeTuplePrefixComparator::Eq(t1, t2) returns true if the // first k fields of t1 equals the first k fields of t2. // SameSizeTuplePrefixComparator(k1, k2) would be a compiler error if // k1 != k2. template struct SameSizeTuplePrefixComparator; template <> struct SameSizeTuplePrefixComparator<0, 0> { template static bool Eq(const Tuple1& /* t1 */, const Tuple2& /* t2 */) { return true; } }; template struct SameSizeTuplePrefixComparator { template static bool Eq(const Tuple1& t1, const Tuple2& t2) { return SameSizeTuplePrefixComparator::Eq(t1, t2) && ::std::tr1::get(t1) == ::std::tr1::get(t2); } }; } // namespace gtest_internal template inline bool operator==(const GTEST_10_TUPLE_(T)& t, const GTEST_10_TUPLE_(U)& u) { return gtest_internal::SameSizeTuplePrefixComparator< tuple_size::value, tuple_size::value>::Eq(t, u); } template inline bool operator!=(const GTEST_10_TUPLE_(T)& t, const GTEST_10_TUPLE_(U)& u) { return !(t == u); } // 6.1.4 Pairs. // Unimplemented. } // namespace tr1 } // namespace std #undef GTEST_0_TUPLE_ #undef GTEST_1_TUPLE_ #undef GTEST_2_TUPLE_ #undef GTEST_3_TUPLE_ #undef GTEST_4_TUPLE_ #undef GTEST_5_TUPLE_ #undef GTEST_6_TUPLE_ #undef GTEST_7_TUPLE_ #undef GTEST_8_TUPLE_ #undef GTEST_9_TUPLE_ #undef GTEST_10_TUPLE_ #undef GTEST_0_TYPENAMES_ #undef GTEST_1_TYPENAMES_ #undef GTEST_2_TYPENAMES_ #undef GTEST_3_TYPENAMES_ #undef GTEST_4_TYPENAMES_ #undef GTEST_5_TYPENAMES_ #undef GTEST_6_TYPENAMES_ #undef GTEST_7_TYPENAMES_ #undef GTEST_8_TYPENAMES_ #undef GTEST_9_TYPENAMES_ #undef GTEST_10_TYPENAMES_ #undef GTEST_DECLARE_TUPLE_AS_FRIEND_ #undef GTEST_BY_REF_ #undef GTEST_ADD_REF_ #undef GTEST_TUPLE_ELEMENT_ #endif // GTEST_INCLUDE_GTEST_INTERNAL_GTEST_TUPLE_H_ # elif GTEST_OS_SYMBIAN // On Symbian, BOOST_HAS_TR1_TUPLE causes Boost's TR1 tuple library to // use STLport's tuple implementation, which unfortunately doesn't // work as the copy of STLport distributed with Symbian is incomplete. // By making sure BOOST_HAS_TR1_TUPLE is undefined, we force Boost to // use its own tuple implementation. # ifdef BOOST_HAS_TR1_TUPLE # undef BOOST_HAS_TR1_TUPLE # endif // BOOST_HAS_TR1_TUPLE // This prevents , which defines // BOOST_HAS_TR1_TUPLE, from being #included by Boost's . # define BOOST_TR1_DETAIL_CONFIG_HPP_INCLUDED # include # elif defined(__GNUC__) && (GTEST_GCC_VER_ >= 40000) // GCC 4.0+ implements tr1/tuple in the header. This does // not conform to the TR1 spec, which requires the header to be . # if !GTEST_HAS_RTTI && GTEST_GCC_VER_ < 40302 // Until version 4.3.2, gcc has a bug that causes , // which is #included by , to not compile when RTTI is // disabled. _TR1_FUNCTIONAL is the header guard for // . Hence the following #define is a hack to prevent // from being included. # define _TR1_FUNCTIONAL 1 # include # undef _TR1_FUNCTIONAL // Allows the user to #include // if he chooses to. # else # include // NOLINT # endif // !GTEST_HAS_RTTI && GTEST_GCC_VER_ < 40302 # else // If the compiler is not GCC 4.0+, we assume the user is using a // spec-conforming TR1 implementation. # include // NOLINT # endif // GTEST_USE_OWN_TR1_TUPLE #endif // GTEST_HAS_TR1_TUPLE // Determines whether clone(2) is supported. // Usually it will only be available on Linux, excluding // Linux on the Itanium architecture. // Also see http://linux.die.net/man/2/clone. #ifndef GTEST_HAS_CLONE // The user didn't tell us, so we need to figure it out. # if GTEST_OS_LINUX && !defined(__ia64__) # define GTEST_HAS_CLONE 1 # else # define GTEST_HAS_CLONE 0 # endif // GTEST_OS_LINUX && !defined(__ia64__) #endif // GTEST_HAS_CLONE // Determines whether to support stream redirection. This is used to test // output correctness and to implement death tests. #ifndef GTEST_HAS_STREAM_REDIRECTION // By default, we assume that stream redirection is supported on all // platforms except known mobile ones. # if GTEST_OS_WINDOWS_MOBILE || GTEST_OS_SYMBIAN # define GTEST_HAS_STREAM_REDIRECTION 0 # else # define GTEST_HAS_STREAM_REDIRECTION 1 # endif // !GTEST_OS_WINDOWS_MOBILE && !GTEST_OS_SYMBIAN #endif // GTEST_HAS_STREAM_REDIRECTION // Determines whether to support death tests. // Google Test does not support death tests for VC 7.1 and earlier as // abort() in a VC 7.1 application compiled as GUI in debug config // pops up a dialog window that cannot be suppressed programmatically. #if (GTEST_OS_LINUX || GTEST_OS_MAC || GTEST_OS_CYGWIN || GTEST_OS_SOLARIS || \ (GTEST_OS_WINDOWS_DESKTOP && _MSC_VER >= 1400) || \ GTEST_OS_WINDOWS_MINGW || GTEST_OS_AIX || GTEST_OS_HPUX) # define GTEST_HAS_DEATH_TEST 1 # include // NOLINT #endif // We don't support MSVC 7.1 with exceptions disabled now. Therefore // all the compilers we care about are adequate for supporting // value-parameterized tests. #define GTEST_HAS_PARAM_TEST 1 // Determines whether to support type-driven tests. // Typed tests need and variadic macros, which GCC, VC++ 8.0, // Sun Pro CC, IBM Visual Age, and HP aCC support. #if defined(__GNUC__) || (_MSC_VER >= 1400) || defined(__SUNPRO_CC) || \ defined(__IBMCPP__) || defined(__HP_aCC) # define GTEST_HAS_TYPED_TEST 1 # define GTEST_HAS_TYPED_TEST_P 1 #endif // Determines whether to support Combine(). This only makes sense when // value-parameterized tests are enabled. The implementation doesn't // work on Sun Studio since it doesn't understand templated conversion // operators. #if GTEST_HAS_PARAM_TEST && GTEST_HAS_TR1_TUPLE && !defined(__SUNPRO_CC) # define GTEST_HAS_COMBINE 1 #endif // Determines whether the system compiler uses UTF-16 for encoding wide strings. #define GTEST_WIDE_STRING_USES_UTF16_ \ (GTEST_OS_WINDOWS || GTEST_OS_CYGWIN || GTEST_OS_SYMBIAN || GTEST_OS_AIX) // Determines whether test results can be streamed to a socket. #if GTEST_OS_LINUX # define GTEST_CAN_STREAM_RESULTS_ 1 #endif // Defines some utility macros. // The GNU compiler emits a warning if nested "if" statements are followed by // an "else" statement and braces are not used to explicitly disambiguate the // "else" binding. This leads to problems with code like: // // if (gate) // ASSERT_*(condition) << "Some message"; // // The "switch (0) case 0:" idiom is used to suppress this. #ifdef __INTEL_COMPILER # define GTEST_AMBIGUOUS_ELSE_BLOCKER_ #else # define GTEST_AMBIGUOUS_ELSE_BLOCKER_ switch (0) case 0: default: // NOLINT #endif // Use this annotation at the end of a struct/class definition to // prevent the compiler from optimizing away instances that are never // used. This is useful when all interesting logic happens inside the // c'tor and / or d'tor. Example: // // struct Foo { // Foo() { ... } // } GTEST_ATTRIBUTE_UNUSED_; // // Also use it after a variable or parameter declaration to tell the // compiler the variable/parameter does not have to be used. #if defined(__GNUC__) && !defined(COMPILER_ICC) # define GTEST_ATTRIBUTE_UNUSED_ __attribute__ ((unused)) #else # define GTEST_ATTRIBUTE_UNUSED_ #endif // A macro to disallow operator= // This should be used in the private: declarations for a class. #define GTEST_DISALLOW_ASSIGN_(type)\ void operator=(type const &) // A macro to disallow copy constructor and operator= // This should be used in the private: declarations for a class. #define GTEST_DISALLOW_COPY_AND_ASSIGN_(type)\ type(type const &);\ GTEST_DISALLOW_ASSIGN_(type) // Tell the compiler to warn about unused return values for functions declared // with this macro. The macro should be used on function declarations // following the argument list: // // Sprocket* AllocateSprocket() GTEST_MUST_USE_RESULT_; #if defined(__GNUC__) && (GTEST_GCC_VER_ >= 30400) && !defined(COMPILER_ICC) # define GTEST_MUST_USE_RESULT_ __attribute__ ((warn_unused_result)) #else # define GTEST_MUST_USE_RESULT_ #endif // __GNUC__ && (GTEST_GCC_VER_ >= 30400) && !COMPILER_ICC // Determine whether the compiler supports Microsoft's Structured Exception // Handling. This is supported by several Windows compilers but generally // does not exist on any other system. #ifndef GTEST_HAS_SEH // The user didn't tell us, so we need to figure it out. # if defined(_MSC_VER) || defined(__BORLANDC__) // These two compilers are known to support SEH. # define GTEST_HAS_SEH 1 # else // Assume no SEH. # define GTEST_HAS_SEH 0 # endif #endif // GTEST_HAS_SEH #ifdef _MSC_VER # if GTEST_LINKED_AS_SHARED_LIBRARY # define GTEST_API_ __declspec(dllimport) # elif GTEST_CREATE_SHARED_LIBRARY # define GTEST_API_ __declspec(dllexport) # endif #endif // _MSC_VER #ifndef GTEST_API_ # define GTEST_API_ #endif #ifdef __GNUC__ // Ask the compiler to never inline a given function. # define GTEST_NO_INLINE_ __attribute__((noinline)) #else # define GTEST_NO_INLINE_ #endif namespace testing { class Message; namespace internal { class String; // The GTEST_COMPILE_ASSERT_ macro can be used to verify that a compile time // expression is true. For example, you could use it to verify the // size of a static array: // // GTEST_COMPILE_ASSERT_(ARRAYSIZE(content_type_names) == CONTENT_NUM_TYPES, // content_type_names_incorrect_size); // // or to make sure a struct is smaller than a certain size: // // GTEST_COMPILE_ASSERT_(sizeof(foo) < 128, foo_too_large); // // The second argument to the macro is the name of the variable. If // the expression is false, most compilers will issue a warning/error // containing the name of the variable. template struct CompileAssert { }; #define GTEST_COMPILE_ASSERT_(expr, msg) \ typedef ::testing::internal::CompileAssert<(bool(expr))> \ msg[bool(expr) ? 1 : -1] // Implementation details of GTEST_COMPILE_ASSERT_: // // - GTEST_COMPILE_ASSERT_ works by defining an array type that has -1 // elements (and thus is invalid) when the expression is false. // // - The simpler definition // // #define GTEST_COMPILE_ASSERT_(expr, msg) typedef char msg[(expr) ? 1 : -1] // // does not work, as gcc supports variable-length arrays whose sizes // are determined at run-time (this is gcc's extension and not part // of the C++ standard). As a result, gcc fails to reject the // following code with the simple definition: // // int foo; // GTEST_COMPILE_ASSERT_(foo, msg); // not supposed to compile as foo is // // not a compile-time constant. // // - By using the type CompileAssert<(bool(expr))>, we ensures that // expr is a compile-time constant. (Template arguments must be // determined at compile-time.) // // - The outter parentheses in CompileAssert<(bool(expr))> are necessary // to work around a bug in gcc 3.4.4 and 4.0.1. If we had written // // CompileAssert // // instead, these compilers will refuse to compile // // GTEST_COMPILE_ASSERT_(5 > 0, some_message); // // (They seem to think the ">" in "5 > 0" marks the end of the // template argument list.) // // - The array size is (bool(expr) ? 1 : -1), instead of simply // // ((expr) ? 1 : -1). // // This is to avoid running into a bug in MS VC 7.1, which // causes ((0.0) ? 1 : -1) to incorrectly evaluate to 1. // StaticAssertTypeEqHelper is used by StaticAssertTypeEq defined in gtest.h. // // This template is declared, but intentionally undefined. template struct StaticAssertTypeEqHelper; template struct StaticAssertTypeEqHelper {}; #if GTEST_HAS_GLOBAL_STRING typedef ::string string; #else typedef ::std::string string; #endif // GTEST_HAS_GLOBAL_STRING #if GTEST_HAS_GLOBAL_WSTRING typedef ::wstring wstring; #elif GTEST_HAS_STD_WSTRING typedef ::std::wstring wstring; #endif // GTEST_HAS_GLOBAL_WSTRING // A helper for suppressing warnings on constant condition. It just // returns 'condition'. GTEST_API_ bool IsTrue(bool condition); // Defines scoped_ptr. // This implementation of scoped_ptr is PARTIAL - it only contains // enough stuff to satisfy Google Test's need. template class scoped_ptr { public: typedef T element_type; explicit scoped_ptr(T* p = NULL) : ptr_(p) {} ~scoped_ptr() { reset(); } T& operator*() const { return *ptr_; } T* operator->() const { return ptr_; } T* get() const { return ptr_; } T* release() { T* const ptr = ptr_; ptr_ = NULL; return ptr; } void reset(T* p = NULL) { if (p != ptr_) { if (IsTrue(sizeof(T) > 0)) { // Makes sure T is a complete type. delete ptr_; } ptr_ = p; } } private: T* ptr_; GTEST_DISALLOW_COPY_AND_ASSIGN_(scoped_ptr); }; // Defines RE. // A simple C++ wrapper for . It uses the POSIX Extended // Regular Expression syntax. class GTEST_API_ RE { public: // A copy constructor is required by the Standard to initialize object // references from r-values. RE(const RE& other) { Init(other.pattern()); } // Constructs an RE from a string. RE(const ::std::string& regex) { Init(regex.c_str()); } // NOLINT #if GTEST_HAS_GLOBAL_STRING RE(const ::string& regex) { Init(regex.c_str()); } // NOLINT #endif // GTEST_HAS_GLOBAL_STRING RE(const char* regex) { Init(regex); } // NOLINT ~RE(); // Returns the string representation of the regex. const char* pattern() const { return pattern_; } // FullMatch(str, re) returns true iff regular expression re matches // the entire str. // PartialMatch(str, re) returns true iff regular expression re // matches a substring of str (including str itself). // // TODO(wan@google.com): make FullMatch() and PartialMatch() work // when str contains NUL characters. static bool FullMatch(const ::std::string& str, const RE& re) { return FullMatch(str.c_str(), re); } static bool PartialMatch(const ::std::string& str, const RE& re) { return PartialMatch(str.c_str(), re); } #if GTEST_HAS_GLOBAL_STRING static bool FullMatch(const ::string& str, const RE& re) { return FullMatch(str.c_str(), re); } static bool PartialMatch(const ::string& str, const RE& re) { return PartialMatch(str.c_str(), re); } #endif // GTEST_HAS_GLOBAL_STRING static bool FullMatch(const char* str, const RE& re); static bool PartialMatch(const char* str, const RE& re); private: void Init(const char* regex); // We use a const char* instead of a string, as Google Test may be used // where string is not available. We also do not use Google Test's own // String type here, in order to simplify dependencies between the // files. const char* pattern_; bool is_valid_; #if GTEST_USES_POSIX_RE regex_t full_regex_; // For FullMatch(). regex_t partial_regex_; // For PartialMatch(). #else // GTEST_USES_SIMPLE_RE const char* full_pattern_; // For FullMatch(); #endif GTEST_DISALLOW_ASSIGN_(RE); }; // Formats a source file path and a line number as they would appear // in an error message from the compiler used to compile this code. GTEST_API_ ::std::string FormatFileLocation(const char* file, int line); // Formats a file location for compiler-independent XML output. // Although this function is not platform dependent, we put it next to // FormatFileLocation in order to contrast the two functions. GTEST_API_ ::std::string FormatCompilerIndependentFileLocation(const char* file, int line); // Defines logging utilities: // GTEST_LOG_(severity) - logs messages at the specified severity level. The // message itself is streamed into the macro. // LogToStderr() - directs all log messages to stderr. // FlushInfoLog() - flushes informational log messages. enum GTestLogSeverity { GTEST_INFO, GTEST_WARNING, GTEST_ERROR, GTEST_FATAL }; // Formats log entry severity, provides a stream object for streaming the // log message, and terminates the message with a newline when going out of // scope. class GTEST_API_ GTestLog { public: GTestLog(GTestLogSeverity severity, const char* file, int line); // Flushes the buffers and, if severity is GTEST_FATAL, aborts the program. ~GTestLog(); ::std::ostream& GetStream() { return ::std::cerr; } private: const GTestLogSeverity severity_; GTEST_DISALLOW_COPY_AND_ASSIGN_(GTestLog); }; #define GTEST_LOG_(severity) \ ::testing::internal::GTestLog(::testing::internal::GTEST_##severity, \ __FILE__, __LINE__).GetStream() inline void LogToStderr() {} inline void FlushInfoLog() { fflush(NULL); } // INTERNAL IMPLEMENTATION - DO NOT USE. // // GTEST_CHECK_ is an all-mode assert. It aborts the program if the condition // is not satisfied. // Synopsys: // GTEST_CHECK_(boolean_condition); // or // GTEST_CHECK_(boolean_condition) << "Additional message"; // // This checks the condition and if the condition is not satisfied // it prints message about the condition violation, including the // condition itself, plus additional message streamed into it, if any, // and then it aborts the program. It aborts the program irrespective of // whether it is built in the debug mode or not. #define GTEST_CHECK_(condition) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ if (::testing::internal::IsTrue(condition)) \ ; \ else \ GTEST_LOG_(FATAL) << "Condition " #condition " failed. " // An all-mode assert to verify that the given POSIX-style function // call returns 0 (indicating success). Known limitation: this // doesn't expand to a balanced 'if' statement, so enclose the macro // in {} if you need to use it as the only statement in an 'if' // branch. #define GTEST_CHECK_POSIX_SUCCESS_(posix_call) \ if (const int gtest_error = (posix_call)) \ GTEST_LOG_(FATAL) << #posix_call << "failed with error " \ << gtest_error // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // Use ImplicitCast_ as a safe version of static_cast for upcasting in // the type hierarchy (e.g. casting a Foo* to a SuperclassOfFoo* or a // const Foo*). When you use ImplicitCast_, the compiler checks that // the cast is safe. Such explicit ImplicitCast_s are necessary in // surprisingly many situations where C++ demands an exact type match // instead of an argument type convertable to a target type. // // The syntax for using ImplicitCast_ is the same as for static_cast: // // ImplicitCast_(expr) // // ImplicitCast_ would have been part of the C++ standard library, // but the proposal was submitted too late. It will probably make // its way into the language in the future. // // This relatively ugly name is intentional. It prevents clashes with // similar functions users may have (e.g., implicit_cast). The internal // namespace alone is not enough because the function can be found by ADL. template inline To ImplicitCast_(To x) { return x; } // When you upcast (that is, cast a pointer from type Foo to type // SuperclassOfFoo), it's fine to use ImplicitCast_<>, since upcasts // always succeed. When you downcast (that is, cast a pointer from // type Foo to type SubclassOfFoo), static_cast<> isn't safe, because // how do you know the pointer is really of type SubclassOfFoo? It // could be a bare Foo, or of type DifferentSubclassOfFoo. Thus, // when you downcast, you should use this macro. In debug mode, we // use dynamic_cast<> to double-check the downcast is legal (we die // if it's not). In normal mode, we do the efficient static_cast<> // instead. Thus, it's important to test in debug mode to make sure // the cast is legal! // This is the only place in the code we should use dynamic_cast<>. // In particular, you SHOULDN'T be using dynamic_cast<> in order to // do RTTI (eg code like this: // if (dynamic_cast(foo)) HandleASubclass1Object(foo); // if (dynamic_cast(foo)) HandleASubclass2Object(foo); // You should design the code some other way not to need this. // // This relatively ugly name is intentional. It prevents clashes with // similar functions users may have (e.g., down_cast). The internal // namespace alone is not enough because the function can be found by ADL. template // use like this: DownCast_(foo); inline To DownCast_(From* f) { // so we only accept pointers // Ensures that To is a sub-type of From *. This test is here only // for compile-time type checking, and has no overhead in an // optimized build at run-time, as it will be optimized away // completely. if (false) { const To to = NULL; ::testing::internal::ImplicitCast_(to); } #if GTEST_HAS_RTTI // RTTI: debug mode only! GTEST_CHECK_(f == NULL || dynamic_cast(f) != NULL); #endif return static_cast(f); } // Downcasts the pointer of type Base to Derived. // Derived must be a subclass of Base. The parameter MUST // point to a class of type Derived, not any subclass of it. // When RTTI is available, the function performs a runtime // check to enforce this. template Derived* CheckedDowncastToActualType(Base* base) { #if GTEST_HAS_RTTI GTEST_CHECK_(typeid(*base) == typeid(Derived)); return dynamic_cast(base); // NOLINT #else return static_cast(base); // Poor man's downcast. #endif } #if GTEST_HAS_STREAM_REDIRECTION // Defines the stderr capturer: // CaptureStdout - starts capturing stdout. // GetCapturedStdout - stops capturing stdout and returns the captured string. // CaptureStderr - starts capturing stderr. // GetCapturedStderr - stops capturing stderr and returns the captured string. // GTEST_API_ void CaptureStdout(); GTEST_API_ String GetCapturedStdout(); GTEST_API_ void CaptureStderr(); GTEST_API_ String GetCapturedStderr(); #endif // GTEST_HAS_STREAM_REDIRECTION #if GTEST_HAS_DEATH_TEST // A copy of all command line arguments. Set by InitGoogleTest(). extern ::std::vector g_argvs; // GTEST_HAS_DEATH_TEST implies we have ::std::string. const ::std::vector& GetArgvs(); #endif // GTEST_HAS_DEATH_TEST // Defines synchronization primitives. #if GTEST_HAS_PTHREAD // Sleeps for (roughly) n milli-seconds. This function is only for // testing Google Test's own constructs. Don't use it in user tests, // either directly or indirectly. inline void SleepMilliseconds(int n) { const timespec time = { 0, // 0 seconds. n * 1000L * 1000L, // And n ms. }; nanosleep(&time, NULL); } // Allows a controller thread to pause execution of newly created // threads until notified. Instances of this class must be created // and destroyed in the controller thread. // // This class is only for testing Google Test's own constructs. Do not // use it in user tests, either directly or indirectly. class Notification { public: Notification() : notified_(false) {} // Notifies all threads created with this notification to start. Must // be called from the controller thread. void Notify() { notified_ = true; } // Blocks until the controller thread notifies. Must be called from a test // thread. void WaitForNotification() { while(!notified_) { SleepMilliseconds(10); } } private: volatile bool notified_; GTEST_DISALLOW_COPY_AND_ASSIGN_(Notification); }; // As a C-function, ThreadFuncWithCLinkage cannot be templated itself. // Consequently, it cannot select a correct instantiation of ThreadWithParam // in order to call its Run(). Introducing ThreadWithParamBase as a // non-templated base class for ThreadWithParam allows us to bypass this // problem. class ThreadWithParamBase { public: virtual ~ThreadWithParamBase() {} virtual void Run() = 0; }; // pthread_create() accepts a pointer to a function type with the C linkage. // According to the Standard (7.5/1), function types with different linkages // are different even if they are otherwise identical. Some compilers (for // example, SunStudio) treat them as different types. Since class methods // cannot be defined with C-linkage we need to define a free C-function to // pass into pthread_create(). extern "C" inline void* ThreadFuncWithCLinkage(void* thread) { static_cast(thread)->Run(); return NULL; } // Helper class for testing Google Test's multi-threading constructs. // To use it, write: // // void ThreadFunc(int param) { /* Do things with param */ } // Notification thread_can_start; // ... // // The thread_can_start parameter is optional; you can supply NULL. // ThreadWithParam thread(&ThreadFunc, 5, &thread_can_start); // thread_can_start.Notify(); // // These classes are only for testing Google Test's own constructs. Do // not use them in user tests, either directly or indirectly. template class ThreadWithParam : public ThreadWithParamBase { public: typedef void (*UserThreadFunc)(T); ThreadWithParam( UserThreadFunc func, T param, Notification* thread_can_start) : func_(func), param_(param), thread_can_start_(thread_can_start), finished_(false) { ThreadWithParamBase* const base = this; // The thread can be created only after all fields except thread_ // have been initialized. GTEST_CHECK_POSIX_SUCCESS_( pthread_create(&thread_, 0, &ThreadFuncWithCLinkage, base)); } ~ThreadWithParam() { Join(); } void Join() { if (!finished_) { GTEST_CHECK_POSIX_SUCCESS_(pthread_join(thread_, 0)); finished_ = true; } } virtual void Run() { if (thread_can_start_ != NULL) thread_can_start_->WaitForNotification(); func_(param_); } private: const UserThreadFunc func_; // User-supplied thread function. const T param_; // User-supplied parameter to the thread function. // When non-NULL, used to block execution until the controller thread // notifies. Notification* const thread_can_start_; bool finished_; // true iff we know that the thread function has finished. pthread_t thread_; // The native thread object. GTEST_DISALLOW_COPY_AND_ASSIGN_(ThreadWithParam); }; // MutexBase and Mutex implement mutex on pthreads-based platforms. They // are used in conjunction with class MutexLock: // // Mutex mutex; // ... // MutexLock lock(&mutex); // Acquires the mutex and releases it at the end // // of the current scope. // // MutexBase implements behavior for both statically and dynamically // allocated mutexes. Do not use MutexBase directly. Instead, write // the following to define a static mutex: // // GTEST_DEFINE_STATIC_MUTEX_(g_some_mutex); // // You can forward declare a static mutex like this: // // GTEST_DECLARE_STATIC_MUTEX_(g_some_mutex); // // To create a dynamic mutex, just define an object of type Mutex. class MutexBase { public: // Acquires this mutex. void Lock() { GTEST_CHECK_POSIX_SUCCESS_(pthread_mutex_lock(&mutex_)); owner_ = pthread_self(); } // Releases this mutex. void Unlock() { // We don't protect writing to owner_ here, as it's the caller's // responsibility to ensure that the current thread holds the // mutex when this is called. owner_ = 0; GTEST_CHECK_POSIX_SUCCESS_(pthread_mutex_unlock(&mutex_)); } // Does nothing if the current thread holds the mutex. Otherwise, crashes // with high probability. void AssertHeld() const { GTEST_CHECK_(owner_ == pthread_self()) << "The current thread is not holding the mutex @" << this; } // A static mutex may be used before main() is entered. It may even // be used before the dynamic initialization stage. Therefore we // must be able to initialize a static mutex object at link time. // This means MutexBase has to be a POD and its member variables // have to be public. public: pthread_mutex_t mutex_; // The underlying pthread mutex. pthread_t owner_; // The thread holding the mutex; 0 means no one holds it. }; // Forward-declares a static mutex. # define GTEST_DECLARE_STATIC_MUTEX_(mutex) \ extern ::testing::internal::MutexBase mutex // Defines and statically (i.e. at link time) initializes a static mutex. # define GTEST_DEFINE_STATIC_MUTEX_(mutex) \ ::testing::internal::MutexBase mutex = { PTHREAD_MUTEX_INITIALIZER, 0 } // The Mutex class can only be used for mutexes created at runtime. It // shares its API with MutexBase otherwise. class Mutex : public MutexBase { public: Mutex() { GTEST_CHECK_POSIX_SUCCESS_(pthread_mutex_init(&mutex_, NULL)); owner_ = 0; } ~Mutex() { GTEST_CHECK_POSIX_SUCCESS_(pthread_mutex_destroy(&mutex_)); } private: GTEST_DISALLOW_COPY_AND_ASSIGN_(Mutex); }; // We cannot name this class MutexLock as the ctor declaration would // conflict with a macro named MutexLock, which is defined on some // platforms. Hence the typedef trick below. class GTestMutexLock { public: explicit GTestMutexLock(MutexBase* mutex) : mutex_(mutex) { mutex_->Lock(); } ~GTestMutexLock() { mutex_->Unlock(); } private: MutexBase* const mutex_; GTEST_DISALLOW_COPY_AND_ASSIGN_(GTestMutexLock); }; typedef GTestMutexLock MutexLock; // Helpers for ThreadLocal. // pthread_key_create() requires DeleteThreadLocalValue() to have // C-linkage. Therefore it cannot be templatized to access // ThreadLocal. Hence the need for class // ThreadLocalValueHolderBase. class ThreadLocalValueHolderBase { public: virtual ~ThreadLocalValueHolderBase() {} }; // Called by pthread to delete thread-local data stored by // pthread_setspecific(). extern "C" inline void DeleteThreadLocalValue(void* value_holder) { delete static_cast(value_holder); } // Implements thread-local storage on pthreads-based systems. // // // Thread 1 // ThreadLocal tl(100); // 100 is the default value for each thread. // // // Thread 2 // tl.set(150); // Changes the value for thread 2 only. // EXPECT_EQ(150, tl.get()); // // // Thread 1 // EXPECT_EQ(100, tl.get()); // In thread 1, tl has the original value. // tl.set(200); // EXPECT_EQ(200, tl.get()); // // The template type argument T must have a public copy constructor. // In addition, the default ThreadLocal constructor requires T to have // a public default constructor. // // An object managed for a thread by a ThreadLocal instance is deleted // when the thread exits. Or, if the ThreadLocal instance dies in // that thread, when the ThreadLocal dies. It's the user's // responsibility to ensure that all other threads using a ThreadLocal // have exited when it dies, or the per-thread objects for those // threads will not be deleted. // // Google Test only uses global ThreadLocal objects. That means they // will die after main() has returned. Therefore, no per-thread // object managed by Google Test will be leaked as long as all threads // using Google Test have exited when main() returns. template class ThreadLocal { public: ThreadLocal() : key_(CreateKey()), default_() {} explicit ThreadLocal(const T& value) : key_(CreateKey()), default_(value) {} ~ThreadLocal() { // Destroys the managed object for the current thread, if any. DeleteThreadLocalValue(pthread_getspecific(key_)); // Releases resources associated with the key. This will *not* // delete managed objects for other threads. GTEST_CHECK_POSIX_SUCCESS_(pthread_key_delete(key_)); } T* pointer() { return GetOrCreateValue(); } const T* pointer() const { return GetOrCreateValue(); } const T& get() const { return *pointer(); } void set(const T& value) { *pointer() = value; } private: // Holds a value of type T. class ValueHolder : public ThreadLocalValueHolderBase { public: explicit ValueHolder(const T& value) : value_(value) {} T* pointer() { return &value_; } private: T value_; GTEST_DISALLOW_COPY_AND_ASSIGN_(ValueHolder); }; static pthread_key_t CreateKey() { pthread_key_t key; // When a thread exits, DeleteThreadLocalValue() will be called on // the object managed for that thread. GTEST_CHECK_POSIX_SUCCESS_( pthread_key_create(&key, &DeleteThreadLocalValue)); return key; } T* GetOrCreateValue() const { ThreadLocalValueHolderBase* const holder = static_cast(pthread_getspecific(key_)); if (holder != NULL) { return CheckedDowncastToActualType(holder)->pointer(); } ValueHolder* const new_holder = new ValueHolder(default_); ThreadLocalValueHolderBase* const holder_base = new_holder; GTEST_CHECK_POSIX_SUCCESS_(pthread_setspecific(key_, holder_base)); return new_holder->pointer(); } // A key pthreads uses for looking up per-thread values. const pthread_key_t key_; const T default_; // The default value for each thread. GTEST_DISALLOW_COPY_AND_ASSIGN_(ThreadLocal); }; # define GTEST_IS_THREADSAFE 1 #else // GTEST_HAS_PTHREAD // A dummy implementation of synchronization primitives (mutex, lock, // and thread-local variable). Necessary for compiling Google Test where // mutex is not supported - using Google Test in multiple threads is not // supported on such platforms. class Mutex { public: Mutex():owner_(0), handle_() { ::InitializeCriticalSection(&handle_); } ~Mutex() { ::DeleteCriticalSection(&handle_); } void Lock() { ::EnterCriticalSection(&handle_); owner_ = ::GetCurrentThreadId(); } void Unlock() { ::LeaveCriticalSection(&handle_); owner_ = 0; } // Does nothing if the current thread holds the mutex. Otherwise, crashes // with high probability. void AssertHeld() const { GTEST_CHECK_(owner_ == ::GetCurrentThreadId()) << "The current thread is not holding the mutex @" << this; } private: DWORD owner_; CRITICAL_SECTION handle_; }; # define GTEST_DECLARE_STATIC_MUTEX_(mutex) \ static ::testing::internal::Mutex mutex # define GTEST_DEFINE_STATIC_MUTEX_(mutex) class GTestMutexLock { public: explicit GTestMutexLock(Mutex* inMutex) : mutex_(inMutex) { mutex_->Lock(); } ~GTestMutexLock() { mutex_->Unlock(); } private: Mutex* mutex_; }; typedef GTestMutexLock MutexLock; class ThreadLocalValueHolderBase { public: virtual ~ThreadLocalValueHolderBase() {} }; extern "C" inline void DeleteThreadLocalValue(void* value_holder) { delete static_cast(value_holder); } // Implements thread-local storage on windows system. template class ThreadLocal { public: ThreadLocal() : key_(CreateKey()), default_() {} explicit ThreadLocal(const T& value) : key_(CreateKey()), default_(value) {} ~ThreadLocal() { // Destroys the managed object for the current thread, if any. DeleteThreadLocalValue(TlsGetValue(key_)); // Releases resources associated with the key. This will *not* // delete managed objects for other threads. GTEST_CHECK_(TlsFree(key_) > 0); } T* pointer() { return GetOrCreateValue(); } const T* pointer() const { return GetOrCreateValue(); } const T& get() const { return *pointer(); } void set(const T& value) { *pointer() = value; } private: // Holds a value of type T. class ValueHolder : public ThreadLocalValueHolderBase { public: explicit ValueHolder(const T& value) : value_(value) {} T* pointer() { return &value_; } private: T value_; GTEST_DISALLOW_COPY_AND_ASSIGN_(ValueHolder); }; static DWORD CreateKey() { DWORD key; // When a thread exits, DeleteThreadLocalValue() will be called on // the object managed for that thread. GTEST_CHECK_((key = TlsAlloc()) != TLS_OUT_OF_INDEXES); return key; } T* GetOrCreateValue() const { ThreadLocalValueHolderBase* const holder = static_cast(TlsGetValue(key_)); if (holder != NULL) { return CheckedDowncastToActualType(holder)->pointer(); } ValueHolder* const new_holder = new ValueHolder(default_); ThreadLocalValueHolderBase* const holder_base = new_holder; GTEST_CHECK_(TlsSetValue(key_, holder_base) != 0); return new_holder->pointer(); } // A key pthreads uses for looking up per-thread values. const DWORD key_; const T default_; // The default value for each thread. GTEST_DISALLOW_COPY_AND_ASSIGN_(ThreadLocal); }; // The above synchronization primitives have dummy implementations. // Therefore Google Test is not thread-safe. # define GTEST_IS_THREADSAFE 0 #endif // GTEST_HAS_PTHREAD // Returns the number of threads running in the process, or 0 to indicate that // we cannot detect it. GTEST_API_ size_t GetThreadCount(); // Passing non-POD classes through ellipsis (...) crashes the ARM // compiler and generates a warning in Sun Studio. The Nokia Symbian // and the IBM XL C/C++ compiler try to instantiate a copy constructor // for objects passed through ellipsis (...), failing for uncopyable // objects. We define this to ensure that only POD is passed through // ellipsis on these systems. #if defined(__SYMBIAN32__) || defined(__IBMCPP__) || defined(__SUNPRO_CC) // We lose support for NULL detection where the compiler doesn't like // passing non-POD classes through ellipsis (...). # define GTEST_ELLIPSIS_NEEDS_POD_ 1 #else # define GTEST_CAN_COMPARE_NULL 1 #endif // The Nokia Symbian and IBM XL C/C++ compilers cannot decide between // const T& and const T* in a function template. These compilers // _can_ decide between class template specializations for T and T*, // so a tr1::type_traits-like is_pointer works. #if defined(__SYMBIAN32__) || defined(__IBMCPP__) # define GTEST_NEEDS_IS_POINTER_ 1 #endif template struct bool_constant { typedef bool_constant type; static const bool value = bool_value; }; template const bool bool_constant::value; typedef bool_constant false_type; typedef bool_constant true_type; template struct is_pointer : public false_type {}; template struct is_pointer : public true_type {}; template struct IteratorTraits { typedef typename Iterator::value_type value_type; }; template struct IteratorTraits { typedef T value_type; }; template struct IteratorTraits { typedef T value_type; }; #if GTEST_OS_WINDOWS # define GTEST_PATH_SEP_ "\\" # define GTEST_HAS_ALT_PATH_SEP_ 1 // The biggest signed integer type the compiler supports. typedef __int64 BiggestInt; #else # define GTEST_PATH_SEP_ "/" # define GTEST_HAS_ALT_PATH_SEP_ 0 typedef long long BiggestInt; // NOLINT #endif // GTEST_OS_WINDOWS // Utilities for char. // isspace(int ch) and friends accept an unsigned char or EOF. char // may be signed, depending on the compiler (or compiler flags). // Therefore we need to cast a char to unsigned char before calling // isspace(), etc. inline bool IsAlpha(char ch) { return isalpha(static_cast(ch)) != 0; } inline bool IsAlNum(char ch) { return isalnum(static_cast(ch)) != 0; } inline bool IsDigit(char ch) { return isdigit(static_cast(ch)) != 0; } inline bool IsLower(char ch) { return islower(static_cast(ch)) != 0; } inline bool IsSpace(char ch) { return isspace(static_cast(ch)) != 0; } inline bool IsUpper(char ch) { return isupper(static_cast(ch)) != 0; } inline bool IsXDigit(char ch) { return isxdigit(static_cast(ch)) != 0; } inline char ToLower(char ch) { return static_cast(tolower(static_cast(ch))); } inline char ToUpper(char ch) { return static_cast(toupper(static_cast(ch))); } // The testing::internal::posix namespace holds wrappers for common // POSIX functions. These wrappers hide the differences between // Windows/MSVC and POSIX systems. Since some compilers define these // standard functions as macros, the wrapper cannot have the same name // as the wrapped function. namespace posix { // Functions with a different name on Windows. #if GTEST_OS_WINDOWS typedef struct _stat StatStruct; # ifdef __BORLANDC__ inline int IsATTY(int fd) { return isatty(fd); } inline int StrCaseCmp(const char* s1, const char* s2) { return stricmp(s1, s2); } inline char* StrDup(const char* src) { return strdup(src); } # else // !__BORLANDC__ # if GTEST_OS_WINDOWS_MOBILE inline int IsATTY(int /* fd */) { return 0; } # else inline int IsATTY(int fd) { return _isatty(fd); } # endif // GTEST_OS_WINDOWS_MOBILE inline int StrCaseCmp(const char* s1, const char* s2) { return _stricmp(s1, s2); } inline char* StrDup(const char* src) { return _strdup(src); } # endif // __BORLANDC__ # if GTEST_OS_WINDOWS_MOBILE inline int FileNo(FILE* file) { return reinterpret_cast(_fileno(file)); } // Stat(), RmDir(), and IsDir() are not needed on Windows CE at this // time and thus not defined there. # else inline int FileNo(FILE* file) { return _fileno(file); } inline int Stat(const char* path, StatStruct* buf) { return _stat(path, buf); } inline int RmDir(const char* dir) { return _rmdir(dir); } inline bool IsDir(const StatStruct& st) { return (_S_IFDIR & st.st_mode) != 0; } # endif // GTEST_OS_WINDOWS_MOBILE #else typedef struct stat StatStruct; inline int FileNo(FILE* file) { return fileno(file); } inline int IsATTY(int fd) { return isatty(fd); } inline int Stat(const char* path, StatStruct* buf) { return stat(path, buf); } inline int StrCaseCmp(const char* s1, const char* s2) { return strcasecmp(s1, s2); } inline char* StrDup(const char* src) { return strdup(src); } inline int RmDir(const char* dir) { return rmdir(dir); } inline bool IsDir(const StatStruct& st) { return S_ISDIR(st.st_mode); } #endif // GTEST_OS_WINDOWS // Functions deprecated by MSVC 8.0. #ifdef _MSC_VER // Temporarily disable warning 4996 (deprecated function). # pragma warning(push) # pragma warning(disable:4996) #endif inline const char* StrNCpy(char* dest, const char* src, size_t n) { return strncpy(dest, src, n); } // ChDir(), FReopen(), FDOpen(), Read(), Write(), Close(), and // StrError() aren't needed on Windows CE at this time and thus not // defined there. #if !GTEST_OS_WINDOWS_MOBILE inline int ChDir(const char* dir) { return chdir(dir); } #endif inline FILE* FOpen(const char* path, const char* mode) { return fopen(path, mode); } #if !GTEST_OS_WINDOWS_MOBILE inline FILE *FReopen(const char* path, const char* mode, FILE* stream) { return freopen(path, mode, stream); } inline FILE* FDOpen(int fd, const char* mode) { return fdopen(fd, mode); } #endif inline int FClose(FILE* fp) { return fclose(fp); } #if !GTEST_OS_WINDOWS_MOBILE inline int Read(int fd, void* buf, unsigned int count) { return static_cast(read(fd, buf, count)); } inline int Write(int fd, const void* buf, unsigned int count) { return static_cast(write(fd, buf, count)); } inline int Close(int fd) { return close(fd); } inline const char* StrError(int errnum) { return strerror(errnum); } #endif inline const char* GetEnv(const char* name) { #if GTEST_OS_WINDOWS_MOBILE // We are on Windows CE, which has no environment variables. return NULL; #elif defined(__BORLANDC__) || defined(__SunOS_5_8) || defined(__SunOS_5_9) // Environment variables which we programmatically clear will be set to the // empty string rather than unset (NULL). Handle that case. const char* const env = getenv(name); return (env != NULL && env[0] != '\0') ? env : NULL; #else return getenv(name); #endif } #ifdef _MSC_VER # pragma warning(pop) // Restores the warning state. #endif #if GTEST_OS_WINDOWS_MOBILE // Windows CE has no C library. The abort() function is used in // several places in Google Test. This implementation provides a reasonable // imitation of standard behaviour. void Abort(); #else inline void Abort() { abort(); } #endif // GTEST_OS_WINDOWS_MOBILE } // namespace posix // The maximum number a BiggestInt can represent. This definition // works no matter BiggestInt is represented in one's complement or // two's complement. // // We cannot rely on numeric_limits in STL, as __int64 and long long // are not part of standard C++ and numeric_limits doesn't need to be // defined for them. const BiggestInt kMaxBiggestInt = ~(static_cast(1) << (8*sizeof(BiggestInt) - 1)); // This template class serves as a compile-time function from size to // type. It maps a size in bytes to a primitive type with that // size. e.g. // // TypeWithSize<4>::UInt // // is typedef-ed to be unsigned int (unsigned integer made up of 4 // bytes). // // Such functionality should belong to STL, but I cannot find it // there. // // Google Test uses this class in the implementation of floating-point // comparison. // // For now it only handles UInt (unsigned int) as that's all Google Test // needs. Other types can be easily added in the future if need // arises. template class TypeWithSize { public: // This prevents the user from using TypeWithSize with incorrect // values of N. typedef void UInt; }; // The specialization for size 4. template <> class TypeWithSize<4> { public: // unsigned int has size 4 in both gcc and MSVC. // // As base/basictypes.h doesn't compile on Windows, we cannot use // uint32, uint64, and etc here. typedef int Int; typedef unsigned int UInt; }; // The specialization for size 8. template <> class TypeWithSize<8> { public: #if GTEST_OS_WINDOWS typedef __int64 Int; typedef unsigned __int64 UInt; #else typedef long long Int; // NOLINT typedef unsigned long long UInt; // NOLINT #endif // GTEST_OS_WINDOWS }; // Integer types of known sizes. typedef TypeWithSize<4>::Int Int32; typedef TypeWithSize<4>::UInt UInt32; typedef TypeWithSize<8>::Int Int64; typedef TypeWithSize<8>::UInt UInt64; typedef TypeWithSize<8>::Int TimeInMillis; // Represents time in milliseconds. // Utilities for command line flags and environment variables. // Macro for referencing flags. #define GTEST_FLAG(name) FLAGS_gtest_##name // Macros for declaring flags. #define GTEST_DECLARE_bool_(name) GTEST_API_ extern bool GTEST_FLAG(name) #define GTEST_DECLARE_int32_(name) \ GTEST_API_ extern ::testing::internal::Int32 GTEST_FLAG(name) #define GTEST_DECLARE_string_(name) \ GTEST_API_ extern ::testing::internal::String GTEST_FLAG(name) // Macros for defining flags. #define GTEST_DEFINE_bool_(name, default_val, doc) \ GTEST_API_ bool GTEST_FLAG(name) = (default_val) #define GTEST_DEFINE_int32_(name, default_val, doc) \ GTEST_API_ ::testing::internal::Int32 GTEST_FLAG(name) = (default_val) #define GTEST_DEFINE_string_(name, default_val, doc) \ GTEST_API_ ::testing::internal::String GTEST_FLAG(name) = (default_val) // Parses 'str' for a 32-bit signed integer. If successful, writes the result // to *value and returns true; otherwise leaves *value unchanged and returns // false. // TODO(chandlerc): Find a better way to refactor flag and environment parsing // out of both gtest-port.cc and gtest.cc to avoid exporting this utility // function. bool ParseInt32(const Message& src_text, const char* str, Int32* value); // Parses a bool/Int32/string from the environment variable // corresponding to the given Google Test flag. bool BoolFromGTestEnv(const char* flag, bool default_val); GTEST_API_ Int32 Int32FromGTestEnv(const char* flag, Int32 default_val); const char* StringFromGTestEnv(const char* flag, const char* default_val); } // namespace internal } // namespace testing #endif // GTEST_INCLUDE_GTEST_INTERNAL_GTEST_PORT_H_ #if GTEST_OS_LINUX # include # include # include # include #endif // GTEST_OS_LINUX #include #include #include #include #include // Copyright 2005, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Authors: wan@google.com (Zhanyong Wan), eefacm@gmail.com (Sean Mcafee) // // The Google C++ Testing Framework (Google Test) // // This header file declares the String class and functions used internally by // Google Test. They are subject to change without notice. They should not used // by code external to Google Test. // // This header file is #included by . // It should not be #included by other files. #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_STRING_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_STRING_H_ #ifdef __BORLANDC__ // string.h is not guaranteed to provide strcpy on C++ Builder. # include #endif #include #include namespace testing { namespace internal { // String - a UTF-8 string class. // // For historic reasons, we don't use std::string. // // TODO(wan@google.com): replace this class with std::string or // implement it in terms of the latter. // // Note that String can represent both NULL and the empty string, // while std::string cannot represent NULL. // // NULL and the empty string are considered different. NULL is less // than anything (including the empty string) except itself. // // This class only provides minimum functionality necessary for // implementing Google Test. We do not intend to implement a full-fledged // string class here. // // Since the purpose of this class is to provide a substitute for // std::string on platforms where it cannot be used, we define a copy // constructor and assignment operators such that we don't need // conditional compilation in a lot of places. // // In order to make the representation efficient, the d'tor of String // is not virtual. Therefore DO NOT INHERIT FROM String. class GTEST_API_ String { public: // Static utility methods // Returns the input enclosed in double quotes if it's not NULL; // otherwise returns "(null)". For example, "\"Hello\"" is returned // for input "Hello". // // This is useful for printing a C string in the syntax of a literal. // // Known issue: escape sequences are not handled yet. static String ShowCStringQuoted(const char* c_str); // Clones a 0-terminated C string, allocating memory using new. The // caller is responsible for deleting the return value using // delete[]. Returns the cloned string, or NULL if the input is // NULL. // // This is different from strdup() in string.h, which allocates // memory using malloc(). static const char* CloneCString(const char* c_str); #if GTEST_OS_WINDOWS_MOBILE // Windows CE does not have the 'ANSI' versions of Win32 APIs. To be // able to pass strings to Win32 APIs on CE we need to convert them // to 'Unicode', UTF-16. // Creates a UTF-16 wide string from the given ANSI string, allocating // memory using new. The caller is responsible for deleting the return // value using delete[]. Returns the wide string, or NULL if the // input is NULL. // // The wide string is created using the ANSI codepage (CP_ACP) to // match the behaviour of the ANSI versions of Win32 calls and the // C runtime. static LPCWSTR AnsiToUtf16(const char* c_str); // Creates an ANSI string from the given wide string, allocating // memory using new. The caller is responsible for deleting the return // value using delete[]. Returns the ANSI string, or NULL if the // input is NULL. // // The returned string is created using the ANSI codepage (CP_ACP) to // match the behaviour of the ANSI versions of Win32 calls and the // C runtime. static const char* Utf16ToAnsi(LPCWSTR utf16_str); #endif // Compares two C strings. Returns true iff they have the same content. // // Unlike strcmp(), this function can handle NULL argument(s). A // NULL C string is considered different to any non-NULL C string, // including the empty string. static bool CStringEquals(const char* lhs, const char* rhs); // Converts a wide C string to a String using the UTF-8 encoding. // NULL will be converted to "(null)". If an error occurred during // the conversion, "(failed to convert from wide string)" is // returned. static String ShowWideCString(const wchar_t* wide_c_str); // Similar to ShowWideCString(), except that this function encloses // the converted string in double quotes. static String ShowWideCStringQuoted(const wchar_t* wide_c_str); // Compares two wide C strings. Returns true iff they have the same // content. // // Unlike wcscmp(), this function can handle NULL argument(s). A // NULL C string is considered different to any non-NULL C string, // including the empty string. static bool WideCStringEquals(const wchar_t* lhs, const wchar_t* rhs); // Compares two C strings, ignoring case. Returns true iff they // have the same content. // // Unlike strcasecmp(), this function can handle NULL argument(s). // A NULL C string is considered different to any non-NULL C string, // including the empty string. static bool CaseInsensitiveCStringEquals(const char* lhs, const char* rhs); // Compares two wide C strings, ignoring case. Returns true iff they // have the same content. // // Unlike wcscasecmp(), this function can handle NULL argument(s). // A NULL C string is considered different to any non-NULL wide C string, // including the empty string. // NB: The implementations on different platforms slightly differ. // On windows, this method uses _wcsicmp which compares according to LC_CTYPE // environment variable. On GNU platform this method uses wcscasecmp // which compares according to LC_CTYPE category of the current locale. // On MacOS X, it uses towlower, which also uses LC_CTYPE category of the // current locale. static bool CaseInsensitiveWideCStringEquals(const wchar_t* lhs, const wchar_t* rhs); // Formats a list of arguments to a String, using the same format // spec string as for printf. // // We do not use the StringPrintf class as it is not universally // available. // // The result is limited to 4096 characters (including the tailing // 0). If 4096 characters are not enough to format the input, // "" is returned. static String Format(const char* format, ...); // C'tors // The default c'tor constructs a NULL string. String() : c_str_(NULL), length_(0) {} // Constructs a String by cloning a 0-terminated C string. String(const char* a_c_str) { // NOLINT if (a_c_str == NULL) { c_str_ = NULL; length_ = 0; } else { ConstructNonNull(a_c_str, strlen(a_c_str)); } } // Constructs a String by copying a given number of chars from a // buffer. E.g. String("hello", 3) creates the string "hel", // String("a\0bcd", 4) creates "a\0bc", String(NULL, 0) creates "", // and String(NULL, 1) results in access violation. String(const char* buffer, size_t a_length) { ConstructNonNull(buffer, a_length); } // The copy c'tor creates a new copy of the string. The two // String objects do not share content. String(const String& str) : c_str_(NULL), length_(0) { *this = str; } // D'tor. String is intended to be a final class, so the d'tor // doesn't need to be virtual. ~String() { delete[] c_str_; } // Allows a String to be implicitly converted to an ::std::string or // ::string, and vice versa. Converting a String containing a NULL // pointer to ::std::string or ::string is undefined behavior. // Converting a ::std::string or ::string containing an embedded NUL // character to a String will result in the prefix up to the first // NUL character. String(const ::std::string& str) { ConstructNonNull(str.c_str(), str.length()); } operator ::std::string() const { return ::std::string(c_str(), length()); } #if GTEST_HAS_GLOBAL_STRING String(const ::string& str) { ConstructNonNull(str.c_str(), str.length()); } operator ::string() const { return ::string(c_str(), length()); } #endif // GTEST_HAS_GLOBAL_STRING // Returns true iff this is an empty string (i.e. ""). bool empty() const { return (c_str() != NULL) && (length() == 0); } // Compares this with another String. // Returns < 0 if this is less than rhs, 0 if this is equal to rhs, or > 0 // if this is greater than rhs. int Compare(const String& rhs) const; // Returns true iff this String equals the given C string. A NULL // string and a non-NULL string are considered not equal. bool operator==(const char* a_c_str) const { return Compare(a_c_str) == 0; } // Returns true iff this String is less than the given String. A // NULL string is considered less than "". bool operator<(const String& rhs) const { return Compare(rhs) < 0; } // Returns true iff this String doesn't equal the given C string. A NULL // string and a non-NULL string are considered not equal. bool operator!=(const char* a_c_str) const { return !(*this == a_c_str); } // Returns true iff this String ends with the given suffix. *Any* // String is considered to end with a NULL or empty suffix. bool EndsWith(const char* suffix) const; // Returns true iff this String ends with the given suffix, not considering // case. Any String is considered to end with a NULL or empty suffix. bool EndsWithCaseInsensitive(const char* suffix) const; // Returns the length of the encapsulated string, or 0 if the // string is NULL. size_t length() const { return length_; } // Gets the 0-terminated C string this String object represents. // The String object still owns the string. Therefore the caller // should NOT delete the return value. const char* c_str() const { return c_str_; } // Assigns a C string to this object. Self-assignment works. const String& operator=(const char* a_c_str) { return *this = String(a_c_str); } // Assigns a String object to this object. Self-assignment works. const String& operator=(const String& rhs) { if (this != &rhs) { delete[] c_str_; if (rhs.c_str() == NULL) { c_str_ = NULL; length_ = 0; } else { ConstructNonNull(rhs.c_str(), rhs.length()); } } return *this; } private: // Constructs a non-NULL String from the given content. This // function can only be called when c_str_ has not been allocated. // ConstructNonNull(NULL, 0) results in an empty string (""). // ConstructNonNull(NULL, non_zero) is undefined behavior. void ConstructNonNull(const char* buffer, size_t a_length) { char* const str = new char[a_length + 1]; memcpy(str, buffer, a_length); str[a_length] = '\0'; c_str_ = str; length_ = a_length; } const char* c_str_; size_t length_; }; // class String // Streams a String to an ostream. Each '\0' character in the String // is replaced with "\\0". inline ::std::ostream& operator<<(::std::ostream& os, const String& str) { if (str.c_str() == NULL) { os << "(null)"; } else { const char* const c_str = str.c_str(); for (size_t i = 0; i != str.length(); i++) { if (c_str[i] == '\0') { os << "\\0"; } else { os << c_str[i]; } } } return os; } // Gets the content of the stringstream's buffer as a String. Each '\0' // character in the buffer is replaced with "\\0". GTEST_API_ String StringStreamToString(::std::stringstream* stream); // Converts a streamable value to a String. A NULL pointer is // converted to "(null)". When the input value is a ::string, // ::std::string, ::wstring, or ::std::wstring object, each NUL // character in it is replaced with "\\0". // Declared here but defined in gtest.h, so that it has access // to the definition of the Message class, required by the ARM // compiler. template String StreamableToString(const T& streamable); } // namespace internal } // namespace testing #endif // GTEST_INCLUDE_GTEST_INTERNAL_GTEST_STRING_H_ // Copyright 2008, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: keith.ray@gmail.com (Keith Ray) // // Google Test filepath utilities // // This header file declares classes and functions used internally by // Google Test. They are subject to change without notice. // // This file is #included in . // Do not include this header file separately! #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_FILEPATH_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_FILEPATH_H_ namespace testing { namespace internal { // FilePath - a class for file and directory pathname manipulation which // handles platform-specific conventions (like the pathname separator). // Used for helper functions for naming files in a directory for xml output. // Except for Set methods, all methods are const or static, which provides an // "immutable value object" -- useful for peace of mind. // A FilePath with a value ending in a path separator ("like/this/") represents // a directory, otherwise it is assumed to represent a file. In either case, // it may or may not represent an actual file or directory in the file system. // Names are NOT checked for syntax correctness -- no checking for illegal // characters, malformed paths, etc. class GTEST_API_ FilePath { public: FilePath() : pathname_("") { } FilePath(const FilePath& rhs) : pathname_(rhs.pathname_) { } explicit FilePath(const char* pathname) : pathname_(pathname) { Normalize(); } explicit FilePath(const String& pathname) : pathname_(pathname) { Normalize(); } FilePath& operator=(const FilePath& rhs) { Set(rhs); return *this; } void Set(const FilePath& rhs) { pathname_ = rhs.pathname_; } String ToString() const { return pathname_; } const char* c_str() const { return pathname_.c_str(); } // Returns the current working directory, or "" if unsuccessful. static FilePath GetCurrentDir(); // Given directory = "dir", base_name = "test", number = 0, // extension = "xml", returns "dir/test.xml". If number is greater // than zero (e.g., 12), returns "dir/test_12.xml". // On Windows platform, uses \ as the separator rather than /. static FilePath MakeFileName(const FilePath& directory, const FilePath& base_name, int number, const char* extension); // Given directory = "dir", relative_path = "test.xml", // returns "dir/test.xml". // On Windows, uses \ as the separator rather than /. static FilePath ConcatPaths(const FilePath& directory, const FilePath& relative_path); // Returns a pathname for a file that does not currently exist. The pathname // will be directory/base_name.extension or // directory/base_name_.extension if directory/base_name.extension // already exists. The number will be incremented until a pathname is found // that does not already exist. // Examples: 'dir/foo_test.xml' or 'dir/foo_test_1.xml'. // There could be a race condition if two or more processes are calling this // function at the same time -- they could both pick the same filename. static FilePath GenerateUniqueFileName(const FilePath& directory, const FilePath& base_name, const char* extension); // Returns true iff the path is NULL or "". bool IsEmpty() const { return c_str() == NULL || *c_str() == '\0'; } // If input name has a trailing separator character, removes it and returns // the name, otherwise return the name string unmodified. // On Windows platform, uses \ as the separator, other platforms use /. FilePath RemoveTrailingPathSeparator() const; // Returns a copy of the FilePath with the directory part removed. // Example: FilePath("path/to/file").RemoveDirectoryName() returns // FilePath("file"). If there is no directory part ("just_a_file"), it returns // the FilePath unmodified. If there is no file part ("just_a_dir/") it // returns an empty FilePath (""). // On Windows platform, '\' is the path separator, otherwise it is '/'. FilePath RemoveDirectoryName() const; // RemoveFileName returns the directory path with the filename removed. // Example: FilePath("path/to/file").RemoveFileName() returns "path/to/". // If the FilePath is "a_file" or "/a_file", RemoveFileName returns // FilePath("./") or, on Windows, FilePath(".\\"). If the filepath does // not have a file, like "just/a/dir/", it returns the FilePath unmodified. // On Windows platform, '\' is the path separator, otherwise it is '/'. FilePath RemoveFileName() const; // Returns a copy of the FilePath with the case-insensitive extension removed. // Example: FilePath("dir/file.exe").RemoveExtension("EXE") returns // FilePath("dir/file"). If a case-insensitive extension is not // found, returns a copy of the original FilePath. FilePath RemoveExtension(const char* extension) const; // Creates directories so that path exists. Returns true if successful or if // the directories already exist; returns false if unable to create // directories for any reason. Will also return false if the FilePath does // not represent a directory (that is, it doesn't end with a path separator). bool CreateDirectoriesRecursively() const; // Create the directory so that path exists. Returns true if successful or // if the directory already exists; returns false if unable to create the // directory for any reason, including if the parent directory does not // exist. Not named "CreateDirectory" because that's a macro on Windows. bool CreateFolder() const; // Returns true if FilePath describes something in the file-system, // either a file, directory, or whatever, and that something exists. bool FileOrDirectoryExists() const; // Returns true if pathname describes a directory in the file-system // that exists. bool DirectoryExists() const; // Returns true if FilePath ends with a path separator, which indicates that // it is intended to represent a directory. Returns false otherwise. // This does NOT check that a directory (or file) actually exists. bool IsDirectory() const; // Returns true if pathname describes a root directory. (Windows has one // root directory per disk drive.) bool IsRootDirectory() const; // Returns true if pathname describes an absolute path. bool IsAbsolutePath() const; private: // Replaces multiple consecutive separators with a single separator. // For example, "bar///foo" becomes "bar/foo". Does not eliminate other // redundancies that might be in a pathname involving "." or "..". // // A pathname with multiple consecutive separators may occur either through // user error or as a result of some scripts or APIs that generate a pathname // with a trailing separator. On other platforms the same API or script // may NOT generate a pathname with a trailing "/". Then elsewhere that // pathname may have another "/" and pathname components added to it, // without checking for the separator already being there. // The script language and operating system may allow paths like "foo//bar" // but some of the functions in FilePath will not handle that correctly. In // particular, RemoveTrailingPathSeparator() only removes one separator, and // it is called in CreateDirectoriesRecursively() assuming that it will change // a pathname from directory syntax (trailing separator) to filename syntax. // // On Windows this method also replaces the alternate path separator '/' with // the primary path separator '\\', so that for example "bar\\/\\foo" becomes // "bar\\foo". void Normalize(); // Returns a pointer to the last occurence of a valid path separator in // the FilePath. On Windows, for example, both '/' and '\' are valid path // separators. Returns NULL if no path separator was found. const char* FindLastPathSeparator() const; String pathname_; }; // class FilePath } // namespace internal } // namespace testing #endif // GTEST_INCLUDE_GTEST_INTERNAL_GTEST_FILEPATH_H_ // This file was GENERATED by command: // pump.py gtest-type-util.h.pump // DO NOT EDIT BY HAND!!! // Copyright 2008 Google Inc. // All Rights Reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan) // Type utilities needed for implementing typed and type-parameterized // tests. This file is generated by a SCRIPT. DO NOT EDIT BY HAND! // // Currently we support at most 50 types in a list, and at most 50 // type-parameterized tests in one type-parameterized test case. // Please contact googletestframework@googlegroups.com if you need // more. #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_TYPE_UTIL_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_TYPE_UTIL_H_ // #ifdef __GNUC__ is too general here. It is possible to use gcc without using // libstdc++ (which is where cxxabi.h comes from). # ifdef __GLIBCXX__ # include # elif defined(__HP_aCC) # include # endif // __GLIBCXX__ namespace testing { namespace internal { // GetTypeName() returns a human-readable name of type T. // NB: This function is also used in Google Mock, so don't move it inside of // the typed-test-only section below. template String GetTypeName() { # if GTEST_HAS_RTTI const char* const name = typeid(T).name(); # if defined(__GLIBCXX__) || defined(__HP_aCC) int status = 0; // gcc's implementation of typeid(T).name() mangles the type name, // so we have to demangle it. # ifdef __GLIBCXX__ using abi::__cxa_demangle; # endif // __GLIBCXX__ char* const readable_name = __cxa_demangle(name, 0, 0, &status); const String name_str(status == 0 ? readable_name : name); free(readable_name); return name_str; # else return name; # endif // __GLIBCXX__ || __HP_aCC # else return ""; # endif // GTEST_HAS_RTTI } #if GTEST_HAS_TYPED_TEST || GTEST_HAS_TYPED_TEST_P // AssertyTypeEq::type is defined iff T1 and T2 are the same // type. This can be used as a compile-time assertion to ensure that // two types are equal. template struct AssertTypeEq; template struct AssertTypeEq { typedef bool type; }; // A unique type used as the default value for the arguments of class // template Types. This allows us to simulate variadic templates // (e.g. Types, Type, and etc), which C++ doesn't // support directly. struct None {}; // The following family of struct and struct templates are used to // represent type lists. In particular, TypesN // represents a type list with N types (T1, T2, ..., and TN) in it. // Except for Types0, every struct in the family has two member types: // Head for the first type in the list, and Tail for the rest of the // list. // The empty type list. struct Types0 {}; // Type lists of length 1, 2, 3, and so on. template struct Types1 { typedef T1 Head; typedef Types0 Tail; }; template struct Types2 { typedef T1 Head; typedef Types1 Tail; }; template struct Types3 { typedef T1 Head; typedef Types2 Tail; }; template struct Types4 { typedef T1 Head; typedef Types3 Tail; }; template struct Types5 { typedef T1 Head; typedef Types4 Tail; }; template struct Types6 { typedef T1 Head; typedef Types5 Tail; }; template struct Types7 { typedef T1 Head; typedef Types6 Tail; }; template struct Types8 { typedef T1 Head; typedef Types7 Tail; }; template struct Types9 { typedef T1 Head; typedef Types8 Tail; }; template struct Types10 { typedef T1 Head; typedef Types9 Tail; }; template struct Types11 { typedef T1 Head; typedef Types10 Tail; }; template struct Types12 { typedef T1 Head; typedef Types11 Tail; }; template struct Types13 { typedef T1 Head; typedef Types12 Tail; }; template struct Types14 { typedef T1 Head; typedef Types13 Tail; }; template struct Types15 { typedef T1 Head; typedef Types14 Tail; }; template struct Types16 { typedef T1 Head; typedef Types15 Tail; }; template struct Types17 { typedef T1 Head; typedef Types16 Tail; }; template struct Types18 { typedef T1 Head; typedef Types17 Tail; }; template struct Types19 { typedef T1 Head; typedef Types18 Tail; }; template struct Types20 { typedef T1 Head; typedef Types19 Tail; }; template struct Types21 { typedef T1 Head; typedef Types20 Tail; }; template struct Types22 { typedef T1 Head; typedef Types21 Tail; }; template struct Types23 { typedef T1 Head; typedef Types22 Tail; }; template struct Types24 { typedef T1 Head; typedef Types23 Tail; }; template struct Types25 { typedef T1 Head; typedef Types24 Tail; }; template struct Types26 { typedef T1 Head; typedef Types25 Tail; }; template struct Types27 { typedef T1 Head; typedef Types26 Tail; }; template struct Types28 { typedef T1 Head; typedef Types27 Tail; }; template struct Types29 { typedef T1 Head; typedef Types28 Tail; }; template struct Types30 { typedef T1 Head; typedef Types29 Tail; }; template struct Types31 { typedef T1 Head; typedef Types30 Tail; }; template struct Types32 { typedef T1 Head; typedef Types31 Tail; }; template struct Types33 { typedef T1 Head; typedef Types32 Tail; }; template struct Types34 { typedef T1 Head; typedef Types33 Tail; }; template struct Types35 { typedef T1 Head; typedef Types34 Tail; }; template struct Types36 { typedef T1 Head; typedef Types35 Tail; }; template struct Types37 { typedef T1 Head; typedef Types36 Tail; }; template struct Types38 { typedef T1 Head; typedef Types37 Tail; }; template struct Types39 { typedef T1 Head; typedef Types38 Tail; }; template struct Types40 { typedef T1 Head; typedef Types39 Tail; }; template struct Types41 { typedef T1 Head; typedef Types40 Tail; }; template struct Types42 { typedef T1 Head; typedef Types41 Tail; }; template struct Types43 { typedef T1 Head; typedef Types42 Tail; }; template struct Types44 { typedef T1 Head; typedef Types43 Tail; }; template struct Types45 { typedef T1 Head; typedef Types44 Tail; }; template struct Types46 { typedef T1 Head; typedef Types45 Tail; }; template struct Types47 { typedef T1 Head; typedef Types46 Tail; }; template struct Types48 { typedef T1 Head; typedef Types47 Tail; }; template struct Types49 { typedef T1 Head; typedef Types48 Tail; }; template struct Types50 { typedef T1 Head; typedef Types49 Tail; }; } // namespace internal // We don't want to require the users to write TypesN<...> directly, // as that would require them to count the length. Types<...> is much // easier to write, but generates horrible messages when there is a // compiler error, as gcc insists on printing out each template // argument, even if it has the default value (this means Types // will appear as Types in the compiler // errors). // // Our solution is to combine the best part of the two approaches: a // user would write Types, and Google Test will translate // that to TypesN internally to make error messages // readable. The translation is done by the 'type' member of the // Types template. template struct Types { typedef internal::Types50 type; }; template <> struct Types { typedef internal::Types0 type; }; template struct Types { typedef internal::Types1 type; }; template struct Types { typedef internal::Types2 type; }; template struct Types { typedef internal::Types3 type; }; template struct Types { typedef internal::Types4 type; }; template struct Types { typedef internal::Types5 type; }; template struct Types { typedef internal::Types6 type; }; template struct Types { typedef internal::Types7 type; }; template struct Types { typedef internal::Types8 type; }; template struct Types { typedef internal::Types9 type; }; template struct Types { typedef internal::Types10 type; }; template struct Types { typedef internal::Types11 type; }; template struct Types { typedef internal::Types12 type; }; template struct Types { typedef internal::Types13 type; }; template struct Types { typedef internal::Types14 type; }; template struct Types { typedef internal::Types15 type; }; template struct Types { typedef internal::Types16 type; }; template struct Types { typedef internal::Types17 type; }; template struct Types { typedef internal::Types18 type; }; template struct Types { typedef internal::Types19 type; }; template struct Types { typedef internal::Types20 type; }; template struct Types { typedef internal::Types21 type; }; template struct Types { typedef internal::Types22 type; }; template struct Types { typedef internal::Types23 type; }; template struct Types { typedef internal::Types24 type; }; template struct Types { typedef internal::Types25 type; }; template struct Types { typedef internal::Types26 type; }; template struct Types { typedef internal::Types27 type; }; template struct Types { typedef internal::Types28 type; }; template struct Types { typedef internal::Types29 type; }; template struct Types { typedef internal::Types30 type; }; template struct Types { typedef internal::Types31 type; }; template struct Types { typedef internal::Types32 type; }; template struct Types { typedef internal::Types33 type; }; template struct Types { typedef internal::Types34 type; }; template struct Types { typedef internal::Types35 type; }; template struct Types { typedef internal::Types36 type; }; template struct Types { typedef internal::Types37 type; }; template struct Types { typedef internal::Types38 type; }; template struct Types { typedef internal::Types39 type; }; template struct Types { typedef internal::Types40 type; }; template struct Types { typedef internal::Types41 type; }; template struct Types { typedef internal::Types42 type; }; template struct Types { typedef internal::Types43 type; }; template struct Types { typedef internal::Types44 type; }; template struct Types { typedef internal::Types45 type; }; template struct Types { typedef internal::Types46 type; }; template struct Types { typedef internal::Types47 type; }; template struct Types { typedef internal::Types48 type; }; template struct Types { typedef internal::Types49 type; }; namespace internal { # define GTEST_TEMPLATE_ template class // The template "selector" struct TemplateSel is used to // represent Tmpl, which must be a class template with one type // parameter, as a type. TemplateSel::Bind::type is defined // as the type Tmpl. This allows us to actually instantiate the // template "selected" by TemplateSel. // // This trick is necessary for simulating typedef for class templates, // which C++ doesn't support directly. template struct TemplateSel { template struct Bind { typedef Tmpl type; }; }; # define GTEST_BIND_(TmplSel, T) \ TmplSel::template Bind::type // A unique struct template used as the default value for the // arguments of class template Templates. This allows us to simulate // variadic templates (e.g. Templates, Templates, // and etc), which C++ doesn't support directly. template struct NoneT {}; // The following family of struct and struct templates are used to // represent template lists. In particular, TemplatesN represents a list of N templates (T1, T2, ..., and TN). Except // for Templates0, every struct in the family has two member types: // Head for the selector of the first template in the list, and Tail // for the rest of the list. // The empty template list. struct Templates0 {}; // Template lists of length 1, 2, 3, and so on. template struct Templates1 { typedef TemplateSel Head; typedef Templates0 Tail; }; template struct Templates2 { typedef TemplateSel Head; typedef Templates1 Tail; }; template struct Templates3 { typedef TemplateSel Head; typedef Templates2 Tail; }; template struct Templates4 { typedef TemplateSel Head; typedef Templates3 Tail; }; template struct Templates5 { typedef TemplateSel Head; typedef Templates4 Tail; }; template struct Templates6 { typedef TemplateSel Head; typedef Templates5 Tail; }; template struct Templates7 { typedef TemplateSel Head; typedef Templates6 Tail; }; template struct Templates8 { typedef TemplateSel Head; typedef Templates7 Tail; }; template struct Templates9 { typedef TemplateSel Head; typedef Templates8 Tail; }; template struct Templates10 { typedef TemplateSel Head; typedef Templates9 Tail; }; template struct Templates11 { typedef TemplateSel Head; typedef Templates10 Tail; }; template struct Templates12 { typedef TemplateSel Head; typedef Templates11 Tail; }; template struct Templates13 { typedef TemplateSel Head; typedef Templates12 Tail; }; template struct Templates14 { typedef TemplateSel Head; typedef Templates13 Tail; }; template struct Templates15 { typedef TemplateSel Head; typedef Templates14 Tail; }; template struct Templates16 { typedef TemplateSel Head; typedef Templates15 Tail; }; template struct Templates17 { typedef TemplateSel Head; typedef Templates16 Tail; }; template struct Templates18 { typedef TemplateSel Head; typedef Templates17 Tail; }; template struct Templates19 { typedef TemplateSel Head; typedef Templates18 Tail; }; template struct Templates20 { typedef TemplateSel Head; typedef Templates19 Tail; }; template struct Templates21 { typedef TemplateSel Head; typedef Templates20 Tail; }; template struct Templates22 { typedef TemplateSel Head; typedef Templates21 Tail; }; template struct Templates23 { typedef TemplateSel Head; typedef Templates22 Tail; }; template struct Templates24 { typedef TemplateSel Head; typedef Templates23 Tail; }; template struct Templates25 { typedef TemplateSel Head; typedef Templates24 Tail; }; template struct Templates26 { typedef TemplateSel Head; typedef Templates25 Tail; }; template struct Templates27 { typedef TemplateSel Head; typedef Templates26 Tail; }; template struct Templates28 { typedef TemplateSel Head; typedef Templates27 Tail; }; template struct Templates29 { typedef TemplateSel Head; typedef Templates28 Tail; }; template struct Templates30 { typedef TemplateSel Head; typedef Templates29 Tail; }; template struct Templates31 { typedef TemplateSel Head; typedef Templates30 Tail; }; template struct Templates32 { typedef TemplateSel Head; typedef Templates31 Tail; }; template struct Templates33 { typedef TemplateSel Head; typedef Templates32 Tail; }; template struct Templates34 { typedef TemplateSel Head; typedef Templates33 Tail; }; template struct Templates35 { typedef TemplateSel Head; typedef Templates34 Tail; }; template struct Templates36 { typedef TemplateSel Head; typedef Templates35 Tail; }; template struct Templates37 { typedef TemplateSel Head; typedef Templates36 Tail; }; template struct Templates38 { typedef TemplateSel Head; typedef Templates37 Tail; }; template struct Templates39 { typedef TemplateSel Head; typedef Templates38 Tail; }; template struct Templates40 { typedef TemplateSel Head; typedef Templates39 Tail; }; template struct Templates41 { typedef TemplateSel Head; typedef Templates40 Tail; }; template struct Templates42 { typedef TemplateSel Head; typedef Templates41 Tail; }; template struct Templates43 { typedef TemplateSel Head; typedef Templates42 Tail; }; template struct Templates44 { typedef TemplateSel Head; typedef Templates43 Tail; }; template struct Templates45 { typedef TemplateSel Head; typedef Templates44 Tail; }; template struct Templates46 { typedef TemplateSel Head; typedef Templates45 Tail; }; template struct Templates47 { typedef TemplateSel Head; typedef Templates46 Tail; }; template struct Templates48 { typedef TemplateSel Head; typedef Templates47 Tail; }; template struct Templates49 { typedef TemplateSel Head; typedef Templates48 Tail; }; template struct Templates50 { typedef TemplateSel Head; typedef Templates49 Tail; }; // We don't want to require the users to write TemplatesN<...> directly, // as that would require them to count the length. Templates<...> is much // easier to write, but generates horrible messages when there is a // compiler error, as gcc insists on printing out each template // argument, even if it has the default value (this means Templates // will appear as Templates in the compiler // errors). // // Our solution is to combine the best part of the two approaches: a // user would write Templates, and Google Test will translate // that to TemplatesN internally to make error messages // readable. The translation is done by the 'type' member of the // Templates template. template struct Templates { typedef Templates50 type; }; template <> struct Templates { typedef Templates0 type; }; template struct Templates { typedef Templates1 type; }; template struct Templates { typedef Templates2 type; }; template struct Templates { typedef Templates3 type; }; template struct Templates { typedef Templates4 type; }; template struct Templates { typedef Templates5 type; }; template struct Templates { typedef Templates6 type; }; template struct Templates { typedef Templates7 type; }; template struct Templates { typedef Templates8 type; }; template struct Templates { typedef Templates9 type; }; template struct Templates { typedef Templates10 type; }; template struct Templates { typedef Templates11 type; }; template struct Templates { typedef Templates12 type; }; template struct Templates { typedef Templates13 type; }; template struct Templates { typedef Templates14 type; }; template struct Templates { typedef Templates15 type; }; template struct Templates { typedef Templates16 type; }; template struct Templates { typedef Templates17 type; }; template struct Templates { typedef Templates18 type; }; template struct Templates { typedef Templates19 type; }; template struct Templates { typedef Templates20 type; }; template struct Templates { typedef Templates21 type; }; template struct Templates { typedef Templates22 type; }; template struct Templates { typedef Templates23 type; }; template struct Templates { typedef Templates24 type; }; template struct Templates { typedef Templates25 type; }; template struct Templates { typedef Templates26 type; }; template struct Templates { typedef Templates27 type; }; template struct Templates { typedef Templates28 type; }; template struct Templates { typedef Templates29 type; }; template struct Templates { typedef Templates30 type; }; template struct Templates { typedef Templates31 type; }; template struct Templates { typedef Templates32 type; }; template struct Templates { typedef Templates33 type; }; template struct Templates { typedef Templates34 type; }; template struct Templates { typedef Templates35 type; }; template struct Templates { typedef Templates36 type; }; template struct Templates { typedef Templates37 type; }; template struct Templates { typedef Templates38 type; }; template struct Templates { typedef Templates39 type; }; template struct Templates { typedef Templates40 type; }; template struct Templates { typedef Templates41 type; }; template struct Templates { typedef Templates42 type; }; template struct Templates { typedef Templates43 type; }; template struct Templates { typedef Templates44 type; }; template struct Templates { typedef Templates45 type; }; template struct Templates { typedef Templates46 type; }; template struct Templates { typedef Templates47 type; }; template struct Templates { typedef Templates48 type; }; template struct Templates { typedef Templates49 type; }; // The TypeList template makes it possible to use either a single type // or a Types<...> list in TYPED_TEST_CASE() and // INSTANTIATE_TYPED_TEST_CASE_P(). template struct TypeList { typedef Types1 type; }; template struct TypeList > { typedef typename Types::type type; }; #endif // GTEST_HAS_TYPED_TEST || GTEST_HAS_TYPED_TEST_P } // namespace internal } // namespace testing #endif // GTEST_INCLUDE_GTEST_INTERNAL_GTEST_TYPE_UTIL_H_ // Due to C++ preprocessor weirdness, we need double indirection to // concatenate two tokens when one of them is __LINE__. Writing // // foo ## __LINE__ // // will result in the token foo__LINE__, instead of foo followed by // the current line number. For more details, see // http://www.parashift.com/c++-faq-lite/misc-technical-issues.html#faq-39.6 #define GTEST_CONCAT_TOKEN_(foo, bar) GTEST_CONCAT_TOKEN_IMPL_(foo, bar) #define GTEST_CONCAT_TOKEN_IMPL_(foo, bar) foo ## bar // Google Test defines the testing::Message class to allow construction of // test messages via the << operator. The idea is that anything // streamable to std::ostream can be streamed to a testing::Message. // This allows a user to use his own types in Google Test assertions by // overloading the << operator. // // util/gtl/stl_logging-inl.h overloads << for STL containers. These // overloads cannot be defined in the std namespace, as that will be // undefined behavior. Therefore, they are defined in the global // namespace instead. // // C++'s symbol lookup rule (i.e. Koenig lookup) says that these // overloads are visible in either the std namespace or the global // namespace, but not other namespaces, including the testing // namespace which Google Test's Message class is in. // // To allow STL containers (and other types that has a << operator // defined in the global namespace) to be used in Google Test assertions, // testing::Message must access the custom << operator from the global // namespace. Hence this helper function. // // Note: Jeffrey Yasskin suggested an alternative fix by "using // ::operator<<;" in the definition of Message's operator<<. That fix // doesn't require a helper function, but unfortunately doesn't // compile with MSVC. template inline void GTestStreamToHelper(std::ostream* os, const T& val) { *os << val; } class ProtocolMessage; namespace proto2 { class Message; } namespace testing { // Forward declarations. class AssertionResult; // Result of an assertion. class Message; // Represents a failure message. class Test; // Represents a test. class TestInfo; // Information about a test. class TestPartResult; // Result of a test part. class UnitTest; // A collection of test cases. template ::std::string PrintToString(const T& value); namespace internal { struct TraceInfo; // Information about a trace point. class ScopedTrace; // Implements scoped trace. class TestInfoImpl; // Opaque implementation of TestInfo class UnitTestImpl; // Opaque implementation of UnitTest // How many times InitGoogleTest() has been called. extern int g_init_gtest_count; // The text used in failure messages to indicate the start of the // stack trace. GTEST_API_ extern const char kStackTraceMarker[]; // A secret type that Google Test users don't know about. It has no // definition on purpose. Therefore it's impossible to create a // Secret object, which is what we want. class Secret; // Two overloaded helpers for checking at compile time whether an // expression is a null pointer literal (i.e. NULL or any 0-valued // compile-time integral constant). Their return values have // different sizes, so we can use sizeof() to test which version is // picked by the compiler. These helpers have no implementations, as // we only need their signatures. // // Given IsNullLiteralHelper(x), the compiler will pick the first // version if x can be implicitly converted to Secret*, and pick the // second version otherwise. Since Secret is a secret and incomplete // type, the only expression a user can write that has type Secret* is // a null pointer literal. Therefore, we know that x is a null // pointer literal if and only if the first version is picked by the // compiler. char IsNullLiteralHelper(Secret* p); char (&IsNullLiteralHelper(...))[2]; // NOLINT // A compile-time bool constant that is true if and only if x is a // null pointer literal (i.e. NULL or any 0-valued compile-time // integral constant). #ifdef GTEST_ELLIPSIS_NEEDS_POD_ // We lose support for NULL detection where the compiler doesn't like // passing non-POD classes through ellipsis (...). # define GTEST_IS_NULL_LITERAL_(x) false #else # define GTEST_IS_NULL_LITERAL_(x) \ (sizeof(::testing::internal::IsNullLiteralHelper(x)) == 1) #endif // GTEST_ELLIPSIS_NEEDS_POD_ // Appends the user-supplied message to the Google-Test-generated message. GTEST_API_ String AppendUserMessage(const String& gtest_msg, const Message& user_msg); // A helper class for creating scoped traces in user programs. class GTEST_API_ ScopedTrace { public: // The c'tor pushes the given source file location and message onto // a trace stack maintained by Google Test. ScopedTrace(const char* file, int line, const Message& message); // The d'tor pops the info pushed by the c'tor. // // Note that the d'tor is not virtual in order to be efficient. // Don't inherit from ScopedTrace! ~ScopedTrace(); private: GTEST_DISALLOW_COPY_AND_ASSIGN_(ScopedTrace); } GTEST_ATTRIBUTE_UNUSED_; // A ScopedTrace object does its job in its // c'tor and d'tor. Therefore it doesn't // need to be used otherwise. // Converts a streamable value to a String. A NULL pointer is // converted to "(null)". When the input value is a ::string, // ::std::string, ::wstring, or ::std::wstring object, each NUL // character in it is replaced with "\\0". // Declared here but defined in gtest.h, so that it has access // to the definition of the Message class, required by the ARM // compiler. template String StreamableToString(const T& streamable); // The Symbian compiler has a bug that prevents it from selecting the // correct overload of FormatForComparisonFailureMessage (see below) // unless we pass the first argument by reference. If we do that, // however, Visual Age C++ 10.1 generates a compiler error. Therefore // we only apply the work-around for Symbian. #if defined(__SYMBIAN32__) # define GTEST_CREF_WORKAROUND_ const& #else # define GTEST_CREF_WORKAROUND_ #endif // When this operand is a const char* or char*, if the other operand // is a ::std::string or ::string, we print this operand as a C string // rather than a pointer (we do the same for wide strings); otherwise // we print it as a pointer to be safe. // This internal macro is used to avoid duplicated code. #define GTEST_FORMAT_IMPL_(operand2_type, operand1_printer)\ inline String FormatForComparisonFailureMessage(\ operand2_type::value_type* GTEST_CREF_WORKAROUND_ str, \ const operand2_type& /*operand2*/) {\ return operand1_printer(str);\ }\ inline String FormatForComparisonFailureMessage(\ const operand2_type::value_type* GTEST_CREF_WORKAROUND_ str, \ const operand2_type& /*operand2*/) {\ return operand1_printer(str);\ } GTEST_FORMAT_IMPL_(::std::string, String::ShowCStringQuoted) #if GTEST_HAS_STD_WSTRING GTEST_FORMAT_IMPL_(::std::wstring, String::ShowWideCStringQuoted) #endif // GTEST_HAS_STD_WSTRING #if GTEST_HAS_GLOBAL_STRING GTEST_FORMAT_IMPL_(::string, String::ShowCStringQuoted) #endif // GTEST_HAS_GLOBAL_STRING #if GTEST_HAS_GLOBAL_WSTRING GTEST_FORMAT_IMPL_(::wstring, String::ShowWideCStringQuoted) #endif // GTEST_HAS_GLOBAL_WSTRING #undef GTEST_FORMAT_IMPL_ // The next four overloads handle the case where the operand being // printed is a char/wchar_t pointer and the other operand is not a // string/wstring object. In such cases, we just print the operand as // a pointer to be safe. #define GTEST_FORMAT_CHAR_PTR_IMPL_(CharType) \ template \ String FormatForComparisonFailureMessage(CharType* GTEST_CREF_WORKAROUND_ p, \ const T&) { \ return PrintToString(static_cast(p)); \ } GTEST_FORMAT_CHAR_PTR_IMPL_(char) GTEST_FORMAT_CHAR_PTR_IMPL_(const char) GTEST_FORMAT_CHAR_PTR_IMPL_(wchar_t) GTEST_FORMAT_CHAR_PTR_IMPL_(const wchar_t) #undef GTEST_FORMAT_CHAR_PTR_IMPL_ // Constructs and returns the message for an equality assertion // (e.g. ASSERT_EQ, EXPECT_STREQ, etc) failure. // // The first four parameters are the expressions used in the assertion // and their values, as strings. For example, for ASSERT_EQ(foo, bar) // where foo is 5 and bar is 6, we have: // // expected_expression: "foo" // actual_expression: "bar" // expected_value: "5" // actual_value: "6" // // The ignoring_case parameter is true iff the assertion is a // *_STRCASEEQ*. When it's true, the string " (ignoring case)" will // be inserted into the message. GTEST_API_ AssertionResult EqFailure(const char* expected_expression, const char* actual_expression, const String& expected_value, const String& actual_value, bool ignoring_case); // Constructs a failure message for Boolean assertions such as EXPECT_TRUE. GTEST_API_ String GetBoolAssertionFailureMessage( const AssertionResult& assertion_result, const char* expression_text, const char* actual_predicate_value, const char* expected_predicate_value); // This template class represents an IEEE floating-point number // (either single-precision or double-precision, depending on the // template parameters). // // The purpose of this class is to do more sophisticated number // comparison. (Due to round-off error, etc, it's very unlikely that // two floating-points will be equal exactly. Hence a naive // comparison by the == operation often doesn't work.) // // Format of IEEE floating-point: // // The most-significant bit being the leftmost, an IEEE // floating-point looks like // // sign_bit exponent_bits fraction_bits // // Here, sign_bit is a single bit that designates the sign of the // number. // // For float, there are 8 exponent bits and 23 fraction bits. // // For double, there are 11 exponent bits and 52 fraction bits. // // More details can be found at // http://en.wikipedia.org/wiki/IEEE_floating-point_standard. // // Template parameter: // // RawType: the raw floating-point type (either float or double) template class FloatingPoint { public: // Defines the unsigned integer type that has the same size as the // floating point number. typedef typename TypeWithSize::UInt Bits; // Constants. // # of bits in a number. static const size_t kBitCount = 8*sizeof(RawType); // # of fraction bits in a number. static const size_t kFractionBitCount = std::numeric_limits::digits - 1; // # of exponent bits in a number. static const size_t kExponentBitCount = kBitCount - 1 - kFractionBitCount; // The mask for the sign bit. static const Bits kSignBitMask = static_cast(1) << (kBitCount - 1); // The mask for the fraction bits. static const Bits kFractionBitMask = ~static_cast(0) >> (kExponentBitCount + 1); // The mask for the exponent bits. static const Bits kExponentBitMask = ~(kSignBitMask | kFractionBitMask); // How many ULP's (Units in the Last Place) we want to tolerate when // comparing two numbers. The larger the value, the more error we // allow. A 0 value means that two numbers must be exactly the same // to be considered equal. // // The maximum error of a single floating-point operation is 0.5 // units in the last place. On Intel CPU's, all floating-point // calculations are done with 80-bit precision, while double has 64 // bits. Therefore, 4 should be enough for ordinary use. // // See the following article for more details on ULP: // http://www.cygnus-software.com/papers/comparingfloats/comparingfloats.htm. static const size_t kMaxUlps = 4; // Constructs a FloatingPoint from a raw floating-point number. // // On an Intel CPU, passing a non-normalized NAN (Not a Number) // around may change its bits, although the new value is guaranteed // to be also a NAN. Therefore, don't expect this constructor to // preserve the bits in x when x is a NAN. explicit FloatingPoint(const RawType& x) { u_.value_ = x; } // Static methods // Reinterprets a bit pattern as a floating-point number. // // This function is needed to test the AlmostEquals() method. static RawType ReinterpretBits(const Bits bits) { FloatingPoint fp(0); fp.u_.bits_ = bits; return fp.u_.value_; } // Returns the floating-point number that represent positive infinity. static RawType Infinity() { return ReinterpretBits(kExponentBitMask); } // Non-static methods // Returns the bits that represents this number. const Bits &bits() const { return u_.bits_; } // Returns the exponent bits of this number. Bits exponent_bits() const { return kExponentBitMask & u_.bits_; } // Returns the fraction bits of this number. Bits fraction_bits() const { return kFractionBitMask & u_.bits_; } // Returns the sign bit of this number. Bits sign_bit() const { return kSignBitMask & u_.bits_; } // Returns true iff this is NAN (not a number). bool is_nan() const { // It's a NAN if the exponent bits are all ones and the fraction // bits are not entirely zeros. return (exponent_bits() == kExponentBitMask) && (fraction_bits() != 0); } // Returns true iff this number is at most kMaxUlps ULP's away from // rhs. In particular, this function: // // - returns false if either number is (or both are) NAN. // - treats really large numbers as almost equal to infinity. // - thinks +0.0 and -0.0 are 0 DLP's apart. bool AlmostEquals(const FloatingPoint& rhs) const { // The IEEE standard says that any comparison operation involving // a NAN must return false. if (is_nan() || rhs.is_nan()) return false; return DistanceBetweenSignAndMagnitudeNumbers(u_.bits_, rhs.u_.bits_) <= kMaxUlps; } private: // The data type used to store the actual floating-point number. union FloatingPointUnion { RawType value_; // The raw floating-point number. Bits bits_; // The bits that represent the number. }; // Converts an integer from the sign-and-magnitude representation to // the biased representation. More precisely, let N be 2 to the // power of (kBitCount - 1), an integer x is represented by the // unsigned number x + N. // // For instance, // // -N + 1 (the most negative number representable using // sign-and-magnitude) is represented by 1; // 0 is represented by N; and // N - 1 (the biggest number representable using // sign-and-magnitude) is represented by 2N - 1. // // Read http://en.wikipedia.org/wiki/Signed_number_representations // for more details on signed number representations. static Bits SignAndMagnitudeToBiased(const Bits &sam) { if (kSignBitMask & sam) { // sam represents a negative number. return ~sam + 1; } else { // sam represents a positive number. return kSignBitMask | sam; } } // Given two numbers in the sign-and-magnitude representation, // returns the distance between them as an unsigned number. static Bits DistanceBetweenSignAndMagnitudeNumbers(const Bits &sam1, const Bits &sam2) { const Bits biased1 = SignAndMagnitudeToBiased(sam1); const Bits biased2 = SignAndMagnitudeToBiased(sam2); return (biased1 >= biased2) ? (biased1 - biased2) : (biased2 - biased1); } FloatingPointUnion u_; }; // Typedefs the instances of the FloatingPoint template class that we // care to use. typedef FloatingPoint Float; typedef FloatingPoint Double; // In order to catch the mistake of putting tests that use different // test fixture classes in the same test case, we need to assign // unique IDs to fixture classes and compare them. The TypeId type is // used to hold such IDs. The user should treat TypeId as an opaque // type: the only operation allowed on TypeId values is to compare // them for equality using the == operator. typedef const void* TypeId; template class TypeIdHelper { public: // dummy_ must not have a const type. Otherwise an overly eager // compiler (e.g. MSVC 7.1 & 8.0) may try to merge // TypeIdHelper::dummy_ for different Ts as an "optimization". static bool dummy_; }; template bool TypeIdHelper::dummy_ = false; // GetTypeId() returns the ID of type T. Different values will be // returned for different types. Calling the function twice with the // same type argument is guaranteed to return the same ID. template TypeId GetTypeId() { // The compiler is required to allocate a different // TypeIdHelper::dummy_ variable for each T used to instantiate // the template. Therefore, the address of dummy_ is guaranteed to // be unique. return &(TypeIdHelper::dummy_); } // Returns the type ID of ::testing::Test. Always call this instead // of GetTypeId< ::testing::Test>() to get the type ID of // ::testing::Test, as the latter may give the wrong result due to a // suspected linker bug when compiling Google Test as a Mac OS X // framework. GTEST_API_ TypeId GetTestTypeId(); // Defines the abstract factory interface that creates instances // of a Test object. class TestFactoryBase { public: virtual ~TestFactoryBase() {} // Creates a test instance to run. The instance is both created and destroyed // within TestInfoImpl::Run() virtual Test* CreateTest() = 0; protected: TestFactoryBase() {} private: GTEST_DISALLOW_COPY_AND_ASSIGN_(TestFactoryBase); }; // This class provides implementation of TeastFactoryBase interface. // It is used in TEST and TEST_F macros. template class TestFactoryImpl : public TestFactoryBase { public: virtual Test* CreateTest() { return new TestClass; } }; #if GTEST_OS_WINDOWS // Predicate-formatters for implementing the HRESULT checking macros // {ASSERT|EXPECT}_HRESULT_{SUCCEEDED|FAILED} // We pass a long instead of HRESULT to avoid causing an // include dependency for the HRESULT type. GTEST_API_ AssertionResult IsHRESULTSuccess(const char* expr, long hr); // NOLINT GTEST_API_ AssertionResult IsHRESULTFailure(const char* expr, long hr); // NOLINT #endif // GTEST_OS_WINDOWS // Types of SetUpTestCase() and TearDownTestCase() functions. typedef void (*SetUpTestCaseFunc)(); typedef void (*TearDownTestCaseFunc)(); // Creates a new TestInfo object and registers it with Google Test; // returns the created object. // // Arguments: // // test_case_name: name of the test case // name: name of the test // type_param the name of the test's type parameter, or NULL if // this is not a typed or a type-parameterized test. // value_param text representation of the test's value parameter, // or NULL if this is not a type-parameterized test. // fixture_class_id: ID of the test fixture class // set_up_tc: pointer to the function that sets up the test case // tear_down_tc: pointer to the function that tears down the test case // factory: pointer to the factory that creates a test object. // The newly created TestInfo instance will assume // ownership of the factory object. GTEST_API_ TestInfo* MakeAndRegisterTestInfo( const char* test_case_name, const char* name, const char* type_param, const char* value_param, TypeId fixture_class_id, SetUpTestCaseFunc set_up_tc, TearDownTestCaseFunc tear_down_tc, TestFactoryBase* factory); // If *pstr starts with the given prefix, modifies *pstr to be right // past the prefix and returns true; otherwise leaves *pstr unchanged // and returns false. None of pstr, *pstr, and prefix can be NULL. GTEST_API_ bool SkipPrefix(const char* prefix, const char** pstr); #if GTEST_HAS_TYPED_TEST || GTEST_HAS_TYPED_TEST_P // State of the definition of a type-parameterized test case. class GTEST_API_ TypedTestCasePState { public: TypedTestCasePState() : registered_(false) {} // Adds the given test name to defined_test_names_ and return true // if the test case hasn't been registered; otherwise aborts the // program. bool AddTestName(const char* file, int line, const char* case_name, const char* test_name) { if (registered_) { fprintf(stderr, "%s Test %s must be defined before " "REGISTER_TYPED_TEST_CASE_P(%s, ...).\n", FormatFileLocation(file, line).c_str(), test_name, case_name); fflush(stderr); posix::Abort(); } defined_test_names_.insert(test_name); return true; } // Verifies that registered_tests match the test names in // defined_test_names_; returns registered_tests if successful, or // aborts the program otherwise. const char* VerifyRegisteredTestNames( const char* file, int line, const char* registered_tests); private: bool registered_; ::std::set defined_test_names_; }; // Skips to the first non-space char after the first comma in 'str'; // returns NULL if no comma is found in 'str'. inline const char* SkipComma(const char* str) { const char* comma = strchr(str, ','); if (comma == NULL) { return NULL; } while (IsSpace(*(++comma))) {} return comma; } // Returns the prefix of 'str' before the first comma in it; returns // the entire string if it contains no comma. inline String GetPrefixUntilComma(const char* str) { const char* comma = strchr(str, ','); return comma == NULL ? String(str) : String(str, comma - str); } // TypeParameterizedTest::Register() // registers a list of type-parameterized tests with Google Test. The // return value is insignificant - we just need to return something // such that we can call this function in a namespace scope. // // Implementation note: The GTEST_TEMPLATE_ macro declares a template // template parameter. It's defined in gtest-type-util.h. template class TypeParameterizedTest { public: // 'index' is the index of the test in the type list 'Types' // specified in INSTANTIATE_TYPED_TEST_CASE_P(Prefix, TestCase, // Types). Valid values for 'index' are [0, N - 1] where N is the // length of Types. static bool Register(const char* prefix, const char* case_name, const char* test_names, int index) { typedef typename Types::Head Type; typedef Fixture FixtureClass; typedef typename GTEST_BIND_(TestSel, Type) TestClass; // First, registers the first type-parameterized test in the type // list. MakeAndRegisterTestInfo( String::Format("%s%s%s/%d", prefix, prefix[0] == '\0' ? "" : "/", case_name, index).c_str(), GetPrefixUntilComma(test_names).c_str(), GetTypeName().c_str(), NULL, // No value parameter. GetTypeId(), TestClass::SetUpTestCase, TestClass::TearDownTestCase, new TestFactoryImpl); // Next, recurses (at compile time) with the tail of the type list. return TypeParameterizedTest ::Register(prefix, case_name, test_names, index + 1); } }; // The base case for the compile time recursion. template class TypeParameterizedTest { public: static bool Register(const char* /*prefix*/, const char* /*case_name*/, const char* /*test_names*/, int /*index*/) { return true; } }; // TypeParameterizedTestCase::Register() // registers *all combinations* of 'Tests' and 'Types' with Google // Test. The return value is insignificant - we just need to return // something such that we can call this function in a namespace scope. template class TypeParameterizedTestCase { public: static bool Register(const char* prefix, const char* case_name, const char* test_names) { typedef typename Tests::Head Head; // First, register the first test in 'Test' for each type in 'Types'. TypeParameterizedTest::Register( prefix, case_name, test_names, 0); // Next, recurses (at compile time) with the tail of the test list. return TypeParameterizedTestCase ::Register(prefix, case_name, SkipComma(test_names)); } }; // The base case for the compile time recursion. template class TypeParameterizedTestCase { public: static bool Register(const char* /*prefix*/, const char* /*case_name*/, const char* /*test_names*/) { return true; } }; #endif // GTEST_HAS_TYPED_TEST || GTEST_HAS_TYPED_TEST_P // Returns the current OS stack trace as a String. // // The maximum number of stack frames to be included is specified by // the gtest_stack_trace_depth flag. The skip_count parameter // specifies the number of top frames to be skipped, which doesn't // count against the number of frames to be included. // // For example, if Foo() calls Bar(), which in turn calls // GetCurrentOsStackTraceExceptTop(..., 1), Foo() will be included in // the trace but Bar() and GetCurrentOsStackTraceExceptTop() won't. GTEST_API_ String GetCurrentOsStackTraceExceptTop(UnitTest* unit_test, int skip_count); // Helpers for suppressing warnings on unreachable code or constant // condition. // Always returns true. GTEST_API_ bool AlwaysTrue(); // Always returns false. inline bool AlwaysFalse() { return !AlwaysTrue(); } // Helper for suppressing false warning from Clang on a const char* // variable declared in a conditional expression always being NULL in // the else branch. struct GTEST_API_ ConstCharPtr { ConstCharPtr(const char* str) : value(str) {} operator bool() const { return true; } const char* value; }; // A simple Linear Congruential Generator for generating random // numbers with a uniform distribution. Unlike rand() and srand(), it // doesn't use global state (and therefore can't interfere with user // code). Unlike rand_r(), it's portable. An LCG isn't very random, // but it's good enough for our purposes. class GTEST_API_ Random { public: static const UInt32 kMaxRange = 1u << 31; explicit Random(UInt32 seed) : state_(seed) {} void Reseed(UInt32 seed) { state_ = seed; } // Generates a random number from [0, range). Crashes if 'range' is // 0 or greater than kMaxRange. UInt32 Generate(UInt32 range); private: UInt32 state_; GTEST_DISALLOW_COPY_AND_ASSIGN_(Random); }; // Defining a variable of type CompileAssertTypesEqual will cause a // compiler error iff T1 and T2 are different types. template struct CompileAssertTypesEqual; template struct CompileAssertTypesEqual { }; // Removes the reference from a type if it is a reference type, // otherwise leaves it unchanged. This is the same as // tr1::remove_reference, which is not widely available yet. template struct RemoveReference { typedef T type; }; // NOLINT template struct RemoveReference { typedef T type; }; // NOLINT // A handy wrapper around RemoveReference that works when the argument // T depends on template parameters. #define GTEST_REMOVE_REFERENCE_(T) \ typename ::testing::internal::RemoveReference::type // Removes const from a type if it is a const type, otherwise leaves // it unchanged. This is the same as tr1::remove_const, which is not // widely available yet. template struct RemoveConst { typedef T type; }; // NOLINT template struct RemoveConst { typedef T type; }; // NOLINT // MSVC 8.0, Sun C++, and IBM XL C++ have a bug which causes the above // definition to fail to remove the const in 'const int[3]' and 'const // char[3][4]'. The following specialization works around the bug. // However, it causes trouble with GCC and thus needs to be // conditionally compiled. #if defined(_MSC_VER) || defined(__SUNPRO_CC) || defined(__IBMCPP__) template struct RemoveConst { typedef typename RemoveConst::type type[N]; }; #endif // A handy wrapper around RemoveConst that works when the argument // T depends on template parameters. #define GTEST_REMOVE_CONST_(T) \ typename ::testing::internal::RemoveConst::type // Turns const U&, U&, const U, and U all into U. #define GTEST_REMOVE_REFERENCE_AND_CONST_(T) \ GTEST_REMOVE_CONST_(GTEST_REMOVE_REFERENCE_(T)) // Adds reference to a type if it is not a reference type, // otherwise leaves it unchanged. This is the same as // tr1::add_reference, which is not widely available yet. template struct AddReference { typedef T& type; }; // NOLINT template struct AddReference { typedef T& type; }; // NOLINT // A handy wrapper around AddReference that works when the argument T // depends on template parameters. #define GTEST_ADD_REFERENCE_(T) \ typename ::testing::internal::AddReference::type // Adds a reference to const on top of T as necessary. For example, // it transforms // // char ==> const char& // const char ==> const char& // char& ==> const char& // const char& ==> const char& // // The argument T must depend on some template parameters. #define GTEST_REFERENCE_TO_CONST_(T) \ GTEST_ADD_REFERENCE_(const GTEST_REMOVE_REFERENCE_(T)) // ImplicitlyConvertible::value is a compile-time bool // constant that's true iff type From can be implicitly converted to // type To. template class ImplicitlyConvertible { private: // We need the following helper functions only for their types. // They have no implementations. // MakeFrom() is an expression whose type is From. We cannot simply // use From(), as the type From may not have a public default // constructor. static From MakeFrom(); // These two functions are overloaded. Given an expression // Helper(x), the compiler will pick the first version if x can be // implicitly converted to type To; otherwise it will pick the // second version. // // The first version returns a value of size 1, and the second // version returns a value of size 2. Therefore, by checking the // size of Helper(x), which can be done at compile time, we can tell // which version of Helper() is used, and hence whether x can be // implicitly converted to type To. static char Helper(To); static char (&Helper(...))[2]; // NOLINT // We have to put the 'public' section after the 'private' section, // or MSVC refuses to compile the code. public: // MSVC warns about implicitly converting from double to int for // possible loss of data, so we need to temporarily disable the // warning. #ifdef _MSC_VER # pragma warning(push) // Saves the current warning state. # pragma warning(disable:4244) // Temporarily disables warning 4244. static const bool value = sizeof(Helper(ImplicitlyConvertible::MakeFrom())) == 1; # pragma warning(pop) // Restores the warning state. #elif defined(__BORLANDC__) // C++Builder cannot use member overload resolution during template // instantiation. The simplest workaround is to use its C++0x type traits // functions (C++Builder 2009 and above only). static const bool value = __is_convertible(From, To); #else static const bool value = sizeof(Helper(ImplicitlyConvertible::MakeFrom())) == 1; #endif // _MSV_VER }; template const bool ImplicitlyConvertible::value; // IsAProtocolMessage::value is a compile-time bool constant that's // true iff T is type ProtocolMessage, proto2::Message, or a subclass // of those. template struct IsAProtocolMessage : public bool_constant< ImplicitlyConvertible::value || ImplicitlyConvertible::value> { }; // When the compiler sees expression IsContainerTest(0), if C is an // STL-style container class, the first overload of IsContainerTest // will be viable (since both C::iterator* and C::const_iterator* are // valid types and NULL can be implicitly converted to them). It will // be picked over the second overload as 'int' is a perfect match for // the type of argument 0. If C::iterator or C::const_iterator is not // a valid type, the first overload is not viable, and the second // overload will be picked. Therefore, we can determine whether C is // a container class by checking the type of IsContainerTest(0). // The value of the expression is insignificant. // // Note that we look for both C::iterator and C::const_iterator. The // reason is that C++ injects the name of a class as a member of the // class itself (e.g. you can refer to class iterator as either // 'iterator' or 'iterator::iterator'). If we look for C::iterator // only, for example, we would mistakenly think that a class named // iterator is an STL container. // // Also note that the simpler approach of overloading // IsContainerTest(typename C::const_iterator*) and // IsContainerTest(...) doesn't work with Visual Age C++ and Sun C++. typedef int IsContainer; template IsContainer IsContainerTest(int /* dummy */, typename C::iterator* /* it */ = NULL, typename C::const_iterator* /* const_it */ = NULL) { return 0; } typedef char IsNotContainer; template IsNotContainer IsContainerTest(long /* dummy */) { return '\0'; } // EnableIf::type is void when 'Cond' is true, and // undefined when 'Cond' is false. To use SFINAE to make a function // overload only apply when a particular expression is true, add // "typename EnableIf::type* = 0" as the last parameter. template struct EnableIf; template<> struct EnableIf { typedef void type; }; // NOLINT // Utilities for native arrays. // ArrayEq() compares two k-dimensional native arrays using the // elements' operator==, where k can be any integer >= 0. When k is // 0, ArrayEq() degenerates into comparing a single pair of values. template bool ArrayEq(const T* lhs, size_t size, const U* rhs); // This generic version is used when k is 0. template inline bool ArrayEq(const T& lhs, const U& rhs) { return lhs == rhs; } // This overload is used when k >= 1. template inline bool ArrayEq(const T(&lhs)[N], const U(&rhs)[N]) { return internal::ArrayEq(lhs, N, rhs); } // This helper reduces code bloat. If we instead put its logic inside // the previous ArrayEq() function, arrays with different sizes would // lead to different copies of the template code. template bool ArrayEq(const T* lhs, size_t size, const U* rhs) { for (size_t i = 0; i != size; i++) { if (!internal::ArrayEq(lhs[i], rhs[i])) return false; } return true; } // Finds the first element in the iterator range [begin, end) that // equals elem. Element may be a native array type itself. template Iter ArrayAwareFind(Iter begin, Iter end, const Element& elem) { for (Iter it = begin; it != end; ++it) { if (internal::ArrayEq(*it, elem)) return it; } return end; } // CopyArray() copies a k-dimensional native array using the elements' // operator=, where k can be any integer >= 0. When k is 0, // CopyArray() degenerates into copying a single value. template void CopyArray(const T* from, size_t size, U* to); // This generic version is used when k is 0. template inline void CopyArray(const T& from, U* to) { *to = from; } // This overload is used when k >= 1. template inline void CopyArray(const T(&from)[N], U(*to)[N]) { internal::CopyArray(from, N, *to); } // This helper reduces code bloat. If we instead put its logic inside // the previous CopyArray() function, arrays with different sizes // would lead to different copies of the template code. template void CopyArray(const T* from, size_t size, U* to) { for (size_t i = 0; i != size; i++) { internal::CopyArray(from[i], to + i); } } // The relation between an NativeArray object (see below) and the // native array it represents. enum RelationToSource { kReference, // The NativeArray references the native array. kCopy // The NativeArray makes a copy of the native array and // owns the copy. }; // Adapts a native array to a read-only STL-style container. Instead // of the complete STL container concept, this adaptor only implements // members useful for Google Mock's container matchers. New members // should be added as needed. To simplify the implementation, we only // support Element being a raw type (i.e. having no top-level const or // reference modifier). It's the client's responsibility to satisfy // this requirement. Element can be an array type itself (hence // multi-dimensional arrays are supported). template class NativeArray { public: // STL-style container typedefs. typedef Element value_type; typedef Element* iterator; typedef const Element* const_iterator; // Constructs from a native array. NativeArray(const Element* array, size_t count, RelationToSource relation) { Init(array, count, relation); } // Copy constructor. NativeArray(const NativeArray& rhs) { Init(rhs.array_, rhs.size_, rhs.relation_to_source_); } ~NativeArray() { // Ensures that the user doesn't instantiate NativeArray with a // const or reference type. static_cast(StaticAssertTypeEqHelper()); if (relation_to_source_ == kCopy) delete[] array_; } // STL-style container methods. size_t size() const { return size_; } const_iterator begin() const { return array_; } const_iterator end() const { return array_ + size_; } bool operator==(const NativeArray& rhs) const { return size() == rhs.size() && ArrayEq(begin(), size(), rhs.begin()); } private: // Initializes this object; makes a copy of the input array if // 'relation' is kCopy. void Init(const Element* array, size_t a_size, RelationToSource relation) { if (relation == kReference) { array_ = array; } else { Element* const copy = new Element[a_size]; CopyArray(array, a_size, copy); array_ = copy; } size_ = a_size; relation_to_source_ = relation; } const Element* array_; size_t size_; RelationToSource relation_to_source_; GTEST_DISALLOW_ASSIGN_(NativeArray); }; } // namespace internal } // namespace testing #define GTEST_MESSAGE_AT_(file, line, message, result_type) \ ::testing::internal::AssertHelper(result_type, file, line, message) \ = ::testing::Message() #define GTEST_MESSAGE_(message, result_type) \ GTEST_MESSAGE_AT_(__FILE__, __LINE__, message, result_type) #define GTEST_FATAL_FAILURE_(message) \ return GTEST_MESSAGE_(message, ::testing::TestPartResult::kFatalFailure) #define GTEST_NONFATAL_FAILURE_(message) \ GTEST_MESSAGE_(message, ::testing::TestPartResult::kNonFatalFailure) #define GTEST_SUCCESS_(message) \ GTEST_MESSAGE_(message, ::testing::TestPartResult::kSuccess) // Suppresses MSVC warnings 4072 (unreachable code) for the code following // statement if it returns or throws (or doesn't return or throw in some // situations). #define GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement) \ if (::testing::internal::AlwaysTrue()) { statement; } #define GTEST_TEST_THROW_(statement, expected_exception, fail) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ if (::testing::internal::ConstCharPtr gtest_msg = "") { \ bool gtest_caught_expected = false; \ try { \ GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement); \ } \ catch (expected_exception const&) { \ gtest_caught_expected = true; \ } \ catch (...) { \ gtest_msg.value = \ "Expected: " #statement " throws an exception of type " \ #expected_exception ".\n Actual: it throws a different type."; \ goto GTEST_CONCAT_TOKEN_(gtest_label_testthrow_, __LINE__); \ } \ if (!gtest_caught_expected) { \ gtest_msg.value = \ "Expected: " #statement " throws an exception of type " \ #expected_exception ".\n Actual: it throws nothing."; \ goto GTEST_CONCAT_TOKEN_(gtest_label_testthrow_, __LINE__); \ } \ } else \ GTEST_CONCAT_TOKEN_(gtest_label_testthrow_, __LINE__): \ fail(gtest_msg.value) #define GTEST_TEST_NO_THROW_(statement, fail) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ if (::testing::internal::AlwaysTrue()) { \ try { \ GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement); \ } \ catch (...) { \ goto GTEST_CONCAT_TOKEN_(gtest_label_testnothrow_, __LINE__); \ } \ } else \ GTEST_CONCAT_TOKEN_(gtest_label_testnothrow_, __LINE__): \ fail("Expected: " #statement " doesn't throw an exception.\n" \ " Actual: it throws.") #define GTEST_TEST_ANY_THROW_(statement, fail) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ if (::testing::internal::AlwaysTrue()) { \ bool gtest_caught_any = false; \ try { \ GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement); \ } \ catch (...) { \ gtest_caught_any = true; \ } \ if (!gtest_caught_any) { \ goto GTEST_CONCAT_TOKEN_(gtest_label_testanythrow_, __LINE__); \ } \ } else \ GTEST_CONCAT_TOKEN_(gtest_label_testanythrow_, __LINE__): \ fail("Expected: " #statement " throws an exception.\n" \ " Actual: it doesn't.") // Implements Boolean test assertions such as EXPECT_TRUE. expression can be // either a boolean expression or an AssertionResult. text is a textual // represenation of expression as it was passed into the EXPECT_TRUE. #define GTEST_TEST_BOOLEAN_(expression, text, actual, expected, fail) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ if (const ::testing::AssertionResult gtest_ar_ = \ ::testing::AssertionResult(expression)) \ ; \ else \ fail(::testing::internal::GetBoolAssertionFailureMessage(\ gtest_ar_, text, #actual, #expected).c_str()) #define GTEST_TEST_NO_FATAL_FAILURE_(statement, fail) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ if (::testing::internal::AlwaysTrue()) { \ ::testing::internal::HasNewFatalFailureHelper gtest_fatal_failure_checker; \ GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement); \ if (gtest_fatal_failure_checker.has_new_fatal_failure()) { \ goto GTEST_CONCAT_TOKEN_(gtest_label_testnofatal_, __LINE__); \ } \ } else \ GTEST_CONCAT_TOKEN_(gtest_label_testnofatal_, __LINE__): \ fail("Expected: " #statement " doesn't generate new fatal " \ "failures in the current thread.\n" \ " Actual: it does.") // Expands to the name of the class that implements the given test. #define GTEST_TEST_CLASS_NAME_(test_case_name, test_name) \ test_case_name##_##test_name##_Test // Helper macro for defining tests. #define GTEST_TEST_(test_case_name, test_name, parent_class, parent_id)\ class GTEST_TEST_CLASS_NAME_(test_case_name, test_name) : public parent_class {\ public:\ GTEST_TEST_CLASS_NAME_(test_case_name, test_name)() {}\ private:\ virtual void TestBody();\ static ::testing::TestInfo* const test_info_ GTEST_ATTRIBUTE_UNUSED_;\ GTEST_DISALLOW_COPY_AND_ASSIGN_(\ GTEST_TEST_CLASS_NAME_(test_case_name, test_name));\ };\ \ ::testing::TestInfo* const GTEST_TEST_CLASS_NAME_(test_case_name, test_name)\ ::test_info_ =\ ::testing::internal::MakeAndRegisterTestInfo(\ #test_case_name, #test_name, NULL, NULL, \ (parent_id), \ parent_class::SetUpTestCase, \ parent_class::TearDownTestCase, \ new ::testing::internal::TestFactoryImpl<\ GTEST_TEST_CLASS_NAME_(test_case_name, test_name)>);\ void GTEST_TEST_CLASS_NAME_(test_case_name, test_name)::TestBody() #endif // GTEST_INCLUDE_GTEST_INTERNAL_GTEST_INTERNAL_H_ // Copyright 2005, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan) // // The Google C++ Testing Framework (Google Test) // // This header file defines the public API for death tests. It is // #included by gtest.h so a user doesn't need to include this // directly. #ifndef GTEST_INCLUDE_GTEST_GTEST_DEATH_TEST_H_ #define GTEST_INCLUDE_GTEST_GTEST_DEATH_TEST_H_ // Copyright 2005, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Authors: wan@google.com (Zhanyong Wan), eefacm@gmail.com (Sean Mcafee) // // The Google C++ Testing Framework (Google Test) // // This header file defines internal utilities needed for implementing // death tests. They are subject to change without notice. #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_DEATH_TEST_INTERNAL_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_DEATH_TEST_INTERNAL_H_ #include namespace testing { namespace internal { GTEST_DECLARE_string_(internal_run_death_test); // Names of the flags (needed for parsing Google Test flags). const char kDeathTestStyleFlag[] = "death_test_style"; const char kDeathTestUseFork[] = "death_test_use_fork"; const char kInternalRunDeathTestFlag[] = "internal_run_death_test"; #if GTEST_HAS_DEATH_TEST // DeathTest is a class that hides much of the complexity of the // GTEST_DEATH_TEST_ macro. It is abstract; its static Create method // returns a concrete class that depends on the prevailing death test // style, as defined by the --gtest_death_test_style and/or // --gtest_internal_run_death_test flags. // In describing the results of death tests, these terms are used with // the corresponding definitions: // // exit status: The integer exit information in the format specified // by wait(2) // exit code: The integer code passed to exit(3), _exit(2), or // returned from main() class GTEST_API_ DeathTest { public: // Create returns false if there was an error determining the // appropriate action to take for the current death test; for example, // if the gtest_death_test_style flag is set to an invalid value. // The LastMessage method will return a more detailed message in that // case. Otherwise, the DeathTest pointer pointed to by the "test" // argument is set. If the death test should be skipped, the pointer // is set to NULL; otherwise, it is set to the address of a new concrete // DeathTest object that controls the execution of the current test. static bool Create(const char* statement, const RE* regex, const char* file, int line, DeathTest** test); DeathTest(); virtual ~DeathTest() { } // A helper class that aborts a death test when it's deleted. class ReturnSentinel { public: explicit ReturnSentinel(DeathTest* test) : test_(test) { } ~ReturnSentinel() { test_->Abort(TEST_ENCOUNTERED_RETURN_STATEMENT); } private: DeathTest* const test_; GTEST_DISALLOW_COPY_AND_ASSIGN_(ReturnSentinel); } GTEST_ATTRIBUTE_UNUSED_; // An enumeration of possible roles that may be taken when a death // test is encountered. EXECUTE means that the death test logic should // be executed immediately. OVERSEE means that the program should prepare // the appropriate environment for a child process to execute the death // test, then wait for it to complete. enum TestRole { OVERSEE_TEST, EXECUTE_TEST }; // An enumeration of the three reasons that a test might be aborted. enum AbortReason { TEST_ENCOUNTERED_RETURN_STATEMENT, TEST_THREW_EXCEPTION, TEST_DID_NOT_DIE }; // Assumes one of the above roles. virtual TestRole AssumeRole() = 0; // Waits for the death test to finish and returns its status. virtual int Wait() = 0; // Returns true if the death test passed; that is, the test process // exited during the test, its exit status matches a user-supplied // predicate, and its stderr output matches a user-supplied regular // expression. // The user-supplied predicate may be a macro expression rather // than a function pointer or functor, or else Wait and Passed could // be combined. virtual bool Passed(bool exit_status_ok) = 0; // Signals that the death test did not die as expected. virtual void Abort(AbortReason reason) = 0; // Returns a human-readable outcome message regarding the outcome of // the last death test. static const char* LastMessage(); static void set_last_death_test_message(const String& message); private: // A string containing a description of the outcome of the last death test. static String last_death_test_message_; GTEST_DISALLOW_COPY_AND_ASSIGN_(DeathTest); }; // Factory interface for death tests. May be mocked out for testing. class DeathTestFactory { public: virtual ~DeathTestFactory() { } virtual bool Create(const char* statement, const RE* regex, const char* file, int line, DeathTest** test) = 0; }; // A concrete DeathTestFactory implementation for normal use. class DefaultDeathTestFactory : public DeathTestFactory { public: virtual bool Create(const char* statement, const RE* regex, const char* file, int line, DeathTest** test); }; // Returns true if exit_status describes a process that was terminated // by a signal, or exited normally with a nonzero exit code. GTEST_API_ bool ExitedUnsuccessfully(int exit_status); // Traps C++ exceptions escaping statement and reports them as test // failures. Note that trapping SEH exceptions is not implemented here. # if GTEST_HAS_EXCEPTIONS # define GTEST_EXECUTE_DEATH_TEST_STATEMENT_(statement, death_test) \ try { \ GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement); \ } catch (const ::std::exception& gtest_exception) { \ fprintf(\ stderr, \ "\n%s: Caught std::exception-derived exception escaping the " \ "death test statement. Exception message: %s\n", \ ::testing::internal::FormatFileLocation(__FILE__, __LINE__).c_str(), \ gtest_exception.what()); \ fflush(stderr); \ death_test->Abort(::testing::internal::DeathTest::TEST_THREW_EXCEPTION); \ } catch (...) { \ death_test->Abort(::testing::internal::DeathTest::TEST_THREW_EXCEPTION); \ } # else # define GTEST_EXECUTE_DEATH_TEST_STATEMENT_(statement, death_test) \ GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement) # endif // This macro is for implementing ASSERT_DEATH*, EXPECT_DEATH*, // ASSERT_EXIT*, and EXPECT_EXIT*. # define GTEST_DEATH_TEST_(statement, predicate, regex, fail) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ if (::testing::internal::AlwaysTrue()) { \ const ::testing::internal::RE& gtest_regex = (regex); \ ::testing::internal::DeathTest* gtest_dt; \ if (!::testing::internal::DeathTest::Create(#statement, >est_regex, \ __FILE__, __LINE__, >est_dt)) { \ goto GTEST_CONCAT_TOKEN_(gtest_label_, __LINE__); \ } \ if (gtest_dt != NULL) { \ ::testing::internal::scoped_ptr< ::testing::internal::DeathTest> \ gtest_dt_ptr(gtest_dt); \ switch (gtest_dt->AssumeRole()) { \ case ::testing::internal::DeathTest::OVERSEE_TEST: \ if (!gtest_dt->Passed(predicate(gtest_dt->Wait()))) { \ goto GTEST_CONCAT_TOKEN_(gtest_label_, __LINE__); \ } \ break; \ case ::testing::internal::DeathTest::EXECUTE_TEST: { \ ::testing::internal::DeathTest::ReturnSentinel \ gtest_sentinel(gtest_dt); \ GTEST_EXECUTE_DEATH_TEST_STATEMENT_(statement, gtest_dt); \ gtest_dt->Abort(::testing::internal::DeathTest::TEST_DID_NOT_DIE); \ break; \ } \ default: \ break; \ } \ } \ } else \ GTEST_CONCAT_TOKEN_(gtest_label_, __LINE__): \ fail(::testing::internal::DeathTest::LastMessage()) // The symbol "fail" here expands to something into which a message // can be streamed. // A class representing the parsed contents of the // --gtest_internal_run_death_test flag, as it existed when // RUN_ALL_TESTS was called. class InternalRunDeathTestFlag { public: InternalRunDeathTestFlag(const String& a_file, int a_line, int an_index, int a_write_fd) : file_(a_file), line_(a_line), index_(an_index), write_fd_(a_write_fd) {} ~InternalRunDeathTestFlag() { if (write_fd_ >= 0) posix::Close(write_fd_); } String file() const { return file_; } int line() const { return line_; } int index() const { return index_; } int write_fd() const { return write_fd_; } private: String file_; int line_; int index_; int write_fd_; GTEST_DISALLOW_COPY_AND_ASSIGN_(InternalRunDeathTestFlag); }; // Returns a newly created InternalRunDeathTestFlag object with fields // initialized from the GTEST_FLAG(internal_run_death_test) flag if // the flag is specified; otherwise returns NULL. InternalRunDeathTestFlag* ParseInternalRunDeathTestFlag(); #else // GTEST_HAS_DEATH_TEST // This macro is used for implementing macros such as // EXPECT_DEATH_IF_SUPPORTED and ASSERT_DEATH_IF_SUPPORTED on systems where // death tests are not supported. Those macros must compile on such systems // iff EXPECT_DEATH and ASSERT_DEATH compile with the same parameters on // systems that support death tests. This allows one to write such a macro // on a system that does not support death tests and be sure that it will // compile on a death-test supporting system. // // Parameters: // statement - A statement that a macro such as EXPECT_DEATH would test // for program termination. This macro has to make sure this // statement is compiled but not executed, to ensure that // EXPECT_DEATH_IF_SUPPORTED compiles with a certain // parameter iff EXPECT_DEATH compiles with it. // regex - A regex that a macro such as EXPECT_DEATH would use to test // the output of statement. This parameter has to be // compiled but not evaluated by this macro, to ensure that // this macro only accepts expressions that a macro such as // EXPECT_DEATH would accept. // terminator - Must be an empty statement for EXPECT_DEATH_IF_SUPPORTED // and a return statement for ASSERT_DEATH_IF_SUPPORTED. // This ensures that ASSERT_DEATH_IF_SUPPORTED will not // compile inside functions where ASSERT_DEATH doesn't // compile. // // The branch that has an always false condition is used to ensure that // statement and regex are compiled (and thus syntactically correct) but // never executed. The unreachable code macro protects the terminator // statement from generating an 'unreachable code' warning in case // statement unconditionally returns or throws. The Message constructor at // the end allows the syntax of streaming additional messages into the // macro, for compilational compatibility with EXPECT_DEATH/ASSERT_DEATH. # define GTEST_UNSUPPORTED_DEATH_TEST_(statement, regex, terminator) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ if (::testing::internal::AlwaysTrue()) { \ GTEST_LOG_(WARNING) \ << "Death tests are not supported on this platform.\n" \ << "Statement '" #statement "' cannot be verified."; \ } else if (::testing::internal::AlwaysFalse()) { \ ::testing::internal::RE::PartialMatch(".*", (regex)); \ GTEST_SUPPRESS_UNREACHABLE_CODE_WARNING_BELOW_(statement); \ terminator; \ } else \ ::testing::Message() #endif // GTEST_HAS_DEATH_TEST } // namespace internal } // namespace testing #endif // GTEST_INCLUDE_GTEST_INTERNAL_GTEST_DEATH_TEST_INTERNAL_H_ namespace testing { // This flag controls the style of death tests. Valid values are "threadsafe", // meaning that the death test child process will re-execute the test binary // from the start, running only a single death test, or "fast", // meaning that the child process will execute the test logic immediately // after forking. GTEST_DECLARE_string_(death_test_style); #if GTEST_HAS_DEATH_TEST // The following macros are useful for writing death tests. // Here's what happens when an ASSERT_DEATH* or EXPECT_DEATH* is // executed: // // 1. It generates a warning if there is more than one active // thread. This is because it's safe to fork() or clone() only // when there is a single thread. // // 2. The parent process clone()s a sub-process and runs the death // test in it; the sub-process exits with code 0 at the end of the // death test, if it hasn't exited already. // // 3. The parent process waits for the sub-process to terminate. // // 4. The parent process checks the exit code and error message of // the sub-process. // // Examples: // // ASSERT_DEATH(server.SendMessage(56, "Hello"), "Invalid port number"); // for (int i = 0; i < 5; i++) { // EXPECT_DEATH(server.ProcessRequest(i), // "Invalid request .* in ProcessRequest()") // << "Failed to die on request " << i); // } // // ASSERT_EXIT(server.ExitNow(), ::testing::ExitedWithCode(0), "Exiting"); // // bool KilledBySIGHUP(int exit_code) { // return WIFSIGNALED(exit_code) && WTERMSIG(exit_code) == SIGHUP; // } // // ASSERT_EXIT(client.HangUpServer(), KilledBySIGHUP, "Hanging up!"); // // On the regular expressions used in death tests: // // On POSIX-compliant systems (*nix), we use the library, // which uses the POSIX extended regex syntax. // // On other platforms (e.g. Windows), we only support a simple regex // syntax implemented as part of Google Test. This limited // implementation should be enough most of the time when writing // death tests; though it lacks many features you can find in PCRE // or POSIX extended regex syntax. For example, we don't support // union ("x|y"), grouping ("(xy)"), brackets ("[xy]"), and // repetition count ("x{5,7}"), among others. // // Below is the syntax that we do support. We chose it to be a // subset of both PCRE and POSIX extended regex, so it's easy to // learn wherever you come from. In the following: 'A' denotes a // literal character, period (.), or a single \\ escape sequence; // 'x' and 'y' denote regular expressions; 'm' and 'n' are for // natural numbers. // // c matches any literal character c // \\d matches any decimal digit // \\D matches any character that's not a decimal digit // \\f matches \f // \\n matches \n // \\r matches \r // \\s matches any ASCII whitespace, including \n // \\S matches any character that's not a whitespace // \\t matches \t // \\v matches \v // \\w matches any letter, _, or decimal digit // \\W matches any character that \\w doesn't match // \\c matches any literal character c, which must be a punctuation // . matches any single character except \n // A? matches 0 or 1 occurrences of A // A* matches 0 or many occurrences of A // A+ matches 1 or many occurrences of A // ^ matches the beginning of a string (not that of each line) // $ matches the end of a string (not that of each line) // xy matches x followed by y // // If you accidentally use PCRE or POSIX extended regex features // not implemented by us, you will get a run-time failure. In that // case, please try to rewrite your regular expression within the // above syntax. // // This implementation is *not* meant to be as highly tuned or robust // as a compiled regex library, but should perform well enough for a // death test, which already incurs significant overhead by launching // a child process. // // Known caveats: // // A "threadsafe" style death test obtains the path to the test // program from argv[0] and re-executes it in the sub-process. For // simplicity, the current implementation doesn't search the PATH // when launching the sub-process. This means that the user must // invoke the test program via a path that contains at least one // path separator (e.g. path/to/foo_test and // /absolute/path/to/bar_test are fine, but foo_test is not). This // is rarely a problem as people usually don't put the test binary // directory in PATH. // // TODO(wan@google.com): make thread-safe death tests search the PATH. // Asserts that a given statement causes the program to exit, with an // integer exit status that satisfies predicate, and emitting error output // that matches regex. # define ASSERT_EXIT(statement, predicate, regex) \ GTEST_DEATH_TEST_(statement, predicate, regex, GTEST_FATAL_FAILURE_) // Like ASSERT_EXIT, but continues on to successive tests in the // test case, if any: # define EXPECT_EXIT(statement, predicate, regex) \ GTEST_DEATH_TEST_(statement, predicate, regex, GTEST_NONFATAL_FAILURE_) // Asserts that a given statement causes the program to exit, either by // explicitly exiting with a nonzero exit code or being killed by a // signal, and emitting error output that matches regex. # define ASSERT_DEATH(statement, regex) \ ASSERT_EXIT(statement, ::testing::internal::ExitedUnsuccessfully, regex) // Like ASSERT_DEATH, but continues on to successive tests in the // test case, if any: # define EXPECT_DEATH(statement, regex) \ EXPECT_EXIT(statement, ::testing::internal::ExitedUnsuccessfully, regex) // Two predicate classes that can be used in {ASSERT,EXPECT}_EXIT*: // Tests that an exit code describes a normal exit with a given exit code. class GTEST_API_ ExitedWithCode { public: explicit ExitedWithCode(int exit_code); bool operator()(int exit_status) const; private: // No implementation - assignment is unsupported. void operator=(const ExitedWithCode& other); const int exit_code_; }; # if !GTEST_OS_WINDOWS // Tests that an exit code describes an exit due to termination by a // given signal. class GTEST_API_ KilledBySignal { public: explicit KilledBySignal(int signum); bool operator()(int exit_status) const; private: const int signum_; }; # endif // !GTEST_OS_WINDOWS // EXPECT_DEBUG_DEATH asserts that the given statements die in debug mode. // The death testing framework causes this to have interesting semantics, // since the sideeffects of the call are only visible in opt mode, and not // in debug mode. // // In practice, this can be used to test functions that utilize the // LOG(DFATAL) macro using the following style: // // int DieInDebugOr12(int* sideeffect) { // if (sideeffect) { // *sideeffect = 12; // } // LOG(DFATAL) << "death"; // return 12; // } // // TEST(TestCase, TestDieOr12WorksInDgbAndOpt) { // int sideeffect = 0; // // Only asserts in dbg. // EXPECT_DEBUG_DEATH(DieInDebugOr12(&sideeffect), "death"); // // #ifdef NDEBUG // // opt-mode has sideeffect visible. // EXPECT_EQ(12, sideeffect); // #else // // dbg-mode no visible sideeffect. // EXPECT_EQ(0, sideeffect); // #endif // } // // This will assert that DieInDebugReturn12InOpt() crashes in debug // mode, usually due to a DCHECK or LOG(DFATAL), but returns the // appropriate fallback value (12 in this case) in opt mode. If you // need to test that a function has appropriate side-effects in opt // mode, include assertions against the side-effects. A general // pattern for this is: // // EXPECT_DEBUG_DEATH({ // // Side-effects here will have an effect after this statement in // // opt mode, but none in debug mode. // EXPECT_EQ(12, DieInDebugOr12(&sideeffect)); // }, "death"); // # ifdef NDEBUG # define EXPECT_DEBUG_DEATH(statement, regex) \ do { statement; } while (::testing::internal::AlwaysFalse()) # define ASSERT_DEBUG_DEATH(statement, regex) \ do { statement; } while (::testing::internal::AlwaysFalse()) # else # define EXPECT_DEBUG_DEATH(statement, regex) \ EXPECT_DEATH(statement, regex) # define ASSERT_DEBUG_DEATH(statement, regex) \ ASSERT_DEATH(statement, regex) # endif // NDEBUG for EXPECT_DEBUG_DEATH #endif // GTEST_HAS_DEATH_TEST // EXPECT_DEATH_IF_SUPPORTED(statement, regex) and // ASSERT_DEATH_IF_SUPPORTED(statement, regex) expand to real death tests if // death tests are supported; otherwise they just issue a warning. This is // useful when you are combining death test assertions with normal test // assertions in one test. #if GTEST_HAS_DEATH_TEST # define EXPECT_DEATH_IF_SUPPORTED(statement, regex) \ EXPECT_DEATH(statement, regex) # define ASSERT_DEATH_IF_SUPPORTED(statement, regex) \ ASSERT_DEATH(statement, regex) #else # define EXPECT_DEATH_IF_SUPPORTED(statement, regex) \ GTEST_UNSUPPORTED_DEATH_TEST_(statement, regex, ) # define ASSERT_DEATH_IF_SUPPORTED(statement, regex) \ GTEST_UNSUPPORTED_DEATH_TEST_(statement, regex, return) #endif } // namespace testing #endif // GTEST_INCLUDE_GTEST_GTEST_DEATH_TEST_H_ // Copyright 2005, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan) // // The Google C++ Testing Framework (Google Test) // // This header file defines the Message class. // // IMPORTANT NOTE: Due to limitation of the C++ language, we have to // leave some internal implementation details in this header file. // They are clearly marked by comments like this: // // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. // // Such code is NOT meant to be used by a user directly, and is subject // to CHANGE WITHOUT NOTICE. Therefore DO NOT DEPEND ON IT in a user // program! #ifndef GTEST_INCLUDE_GTEST_GTEST_MESSAGE_H_ #define GTEST_INCLUDE_GTEST_GTEST_MESSAGE_H_ #include namespace testing { // The Message class works like an ostream repeater. // // Typical usage: // // 1. You stream a bunch of values to a Message object. // It will remember the text in a stringstream. // 2. Then you stream the Message object to an ostream. // This causes the text in the Message to be streamed // to the ostream. // // For example; // // testing::Message foo; // foo << 1 << " != " << 2; // std::cout << foo; // // will print "1 != 2". // // Message is not intended to be inherited from. In particular, its // destructor is not virtual. // // Note that stringstream behaves differently in gcc and in MSVC. You // can stream a NULL char pointer to it in the former, but not in the // latter (it causes an access violation if you do). The Message // class hides this difference by treating a NULL char pointer as // "(null)". class GTEST_API_ Message { private: // The type of basic IO manipulators (endl, ends, and flush) for // narrow streams. typedef std::ostream& (*BasicNarrowIoManip)(std::ostream&); public: // Constructs an empty Message. // We allocate the stringstream separately because otherwise each use of // ASSERT/EXPECT in a procedure adds over 200 bytes to the procedure's // stack frame leading to huge stack frames in some cases; gcc does not reuse // the stack space. Message() : ss_(new ::std::stringstream) { // By default, we want there to be enough precision when printing // a double to a Message. *ss_ << std::setprecision(std::numeric_limits::digits10 + 2); } // Copy constructor. Message(const Message& msg) : ss_(new ::std::stringstream) { // NOLINT *ss_ << msg.GetString(); } // Constructs a Message from a C-string. explicit Message(const char* str) : ss_(new ::std::stringstream) { *ss_ << str; } #if GTEST_OS_SYMBIAN // Streams a value (either a pointer or not) to this object. template inline Message& operator <<(const T& value) { StreamHelper(typename internal::is_pointer::type(), value); return *this; } #else // Streams a non-pointer value to this object. template inline Message& operator <<(const T& val) { ::GTestStreamToHelper(ss_.get(), val); return *this; } // Streams a pointer value to this object. // // This function is an overload of the previous one. When you // stream a pointer to a Message, this definition will be used as it // is more specialized. (The C++ Standard, section // [temp.func.order].) If you stream a non-pointer, then the // previous definition will be used. // // The reason for this overload is that streaming a NULL pointer to // ostream is undefined behavior. Depending on the compiler, you // may get "0", "(nil)", "(null)", or an access violation. To // ensure consistent result across compilers, we always treat NULL // as "(null)". template inline Message& operator <<(T* const& pointer) { // NOLINT if (pointer == NULL) { *ss_ << "(null)"; } else { ::GTestStreamToHelper(ss_.get(), pointer); } return *this; } #endif // GTEST_OS_SYMBIAN // Since the basic IO manipulators are overloaded for both narrow // and wide streams, we have to provide this specialized definition // of operator <<, even though its body is the same as the // templatized version above. Without this definition, streaming // endl or other basic IO manipulators to Message will confuse the // compiler. Message& operator <<(BasicNarrowIoManip val) { *ss_ << val; return *this; } // Instead of 1/0, we want to see true/false for bool values. Message& operator <<(bool b) { return *this << (b ? "true" : "false"); } // These two overloads allow streaming a wide C string to a Message // using the UTF-8 encoding. Message& operator <<(const wchar_t* wide_c_str) { return *this << internal::String::ShowWideCString(wide_c_str); } Message& operator <<(wchar_t* wide_c_str) { return *this << internal::String::ShowWideCString(wide_c_str); } #if GTEST_HAS_STD_WSTRING // Converts the given wide string to a narrow string using the UTF-8 // encoding, and streams the result to this Message object. Message& operator <<(const ::std::wstring& wstr); #endif // GTEST_HAS_STD_WSTRING #if GTEST_HAS_GLOBAL_WSTRING // Converts the given wide string to a narrow string using the UTF-8 // encoding, and streams the result to this Message object. Message& operator <<(const ::wstring& wstr); #endif // GTEST_HAS_GLOBAL_WSTRING // Gets the text streamed to this object so far as a String. // Each '\0' character in the buffer is replaced with "\\0". // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. internal::String GetString() const { return internal::StringStreamToString(ss_.get()); } private: #if GTEST_OS_SYMBIAN // These are needed as the Nokia Symbian Compiler cannot decide between // const T& and const T* in a function template. The Nokia compiler _can_ // decide between class template specializations for T and T*, so a // tr1::type_traits-like is_pointer works, and we can overload on that. template inline void StreamHelper(internal::true_type /*dummy*/, T* pointer) { if (pointer == NULL) { *ss_ << "(null)"; } else { ::GTestStreamToHelper(ss_.get(), pointer); } } template inline void StreamHelper(internal::false_type /*dummy*/, const T& value) { ::GTestStreamToHelper(ss_.get(), value); } #endif // GTEST_OS_SYMBIAN // We'll hold the text streamed to this object here. const internal::scoped_ptr< ::std::stringstream> ss_; // We declare (but don't implement) this to prevent the compiler // from implementing the assignment operator. void operator=(const Message&); }; // Streams a Message to an ostream. inline std::ostream& operator <<(std::ostream& os, const Message& sb) { return os << sb.GetString(); } } // namespace testing #endif // GTEST_INCLUDE_GTEST_GTEST_MESSAGE_H_ // This file was GENERATED by command: // pump.py gtest-param-test.h.pump // DO NOT EDIT BY HAND!!! // Copyright 2008, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Authors: vladl@google.com (Vlad Losev) // // Macros and functions for implementing parameterized tests // in Google C++ Testing Framework (Google Test) // // This file is generated by a SCRIPT. DO NOT EDIT BY HAND! // #ifndef GTEST_INCLUDE_GTEST_GTEST_PARAM_TEST_H_ #define GTEST_INCLUDE_GTEST_GTEST_PARAM_TEST_H_ // Value-parameterized tests allow you to test your code with different // parameters without writing multiple copies of the same test. // // Here is how you use value-parameterized tests: #if 0 // To write value-parameterized tests, first you should define a fixture // class. It is usually derived from testing::TestWithParam (see below for // another inheritance scheme that's sometimes useful in more complicated // class hierarchies), where the type of your parameter values. // TestWithParam is itself derived from testing::Test. T can be any // copyable type. If it's a raw pointer, you are responsible for managing the // lifespan of the pointed values. class FooTest : public ::testing::TestWithParam { // You can implement all the usual class fixture members here. }; // Then, use the TEST_P macro to define as many parameterized tests // for this fixture as you want. The _P suffix is for "parameterized" // or "pattern", whichever you prefer to think. TEST_P(FooTest, DoesBlah) { // Inside a test, access the test parameter with the GetParam() method // of the TestWithParam class: EXPECT_TRUE(foo.Blah(GetParam())); ... } TEST_P(FooTest, HasBlahBlah) { ... } // Finally, you can use INSTANTIATE_TEST_CASE_P to instantiate the test // case with any set of parameters you want. Google Test defines a number // of functions for generating test parameters. They return what we call // (surprise!) parameter generators. Here is a summary of them, which // are all in the testing namespace: // // // Range(begin, end [, step]) - Yields values {begin, begin+step, // begin+step+step, ...}. The values do not // include end. step defaults to 1. // Values(v1, v2, ..., vN) - Yields values {v1, v2, ..., vN}. // ValuesIn(container) - Yields values from a C-style array, an STL // ValuesIn(begin,end) container, or an iterator range [begin, end). // Bool() - Yields sequence {false, true}. // Combine(g1, g2, ..., gN) - Yields all combinations (the Cartesian product // for the math savvy) of the values generated // by the N generators. // // For more details, see comments at the definitions of these functions below // in this file. // // The following statement will instantiate tests from the FooTest test case // each with parameter values "meeny", "miny", and "moe". INSTANTIATE_TEST_CASE_P(InstantiationName, FooTest, Values("meeny", "miny", "moe")); // To distinguish different instances of the pattern, (yes, you // can instantiate it more then once) the first argument to the // INSTANTIATE_TEST_CASE_P macro is a prefix that will be added to the // actual test case name. Remember to pick unique prefixes for different // instantiations. The tests from the instantiation above will have // these names: // // * InstantiationName/FooTest.DoesBlah/0 for "meeny" // * InstantiationName/FooTest.DoesBlah/1 for "miny" // * InstantiationName/FooTest.DoesBlah/2 for "moe" // * InstantiationName/FooTest.HasBlahBlah/0 for "meeny" // * InstantiationName/FooTest.HasBlahBlah/1 for "miny" // * InstantiationName/FooTest.HasBlahBlah/2 for "moe" // // You can use these names in --gtest_filter. // // This statement will instantiate all tests from FooTest again, each // with parameter values "cat" and "dog": const char* pets[] = {"cat", "dog"}; INSTANTIATE_TEST_CASE_P(AnotherInstantiationName, FooTest, ValuesIn(pets)); // The tests from the instantiation above will have these names: // // * AnotherInstantiationName/FooTest.DoesBlah/0 for "cat" // * AnotherInstantiationName/FooTest.DoesBlah/1 for "dog" // * AnotherInstantiationName/FooTest.HasBlahBlah/0 for "cat" // * AnotherInstantiationName/FooTest.HasBlahBlah/1 for "dog" // // Please note that INSTANTIATE_TEST_CASE_P will instantiate all tests // in the given test case, whether their definitions come before or // AFTER the INSTANTIATE_TEST_CASE_P statement. // // Please also note that generator expressions (including parameters to the // generators) are evaluated in InitGoogleTest(), after main() has started. // This allows the user on one hand, to adjust generator parameters in order // to dynamically determine a set of tests to run and on the other hand, // give the user a chance to inspect the generated tests with Google Test // reflection API before RUN_ALL_TESTS() is executed. // // You can see samples/sample7_unittest.cc and samples/sample8_unittest.cc // for more examples. // // In the future, we plan to publish the API for defining new parameter // generators. But for now this interface remains part of the internal // implementation and is subject to change. // // // A parameterized test fixture must be derived from testing::Test and from // testing::WithParamInterface, where T is the type of the parameter // values. Inheriting from TestWithParam satisfies that requirement because // TestWithParam inherits from both Test and WithParamInterface. In more // complicated hierarchies, however, it is occasionally useful to inherit // separately from Test and WithParamInterface. For example: class BaseTest : public ::testing::Test { // You can inherit all the usual members for a non-parameterized test // fixture here. }; class DerivedTest : public BaseTest, public ::testing::WithParamInterface { // The usual test fixture members go here too. }; TEST_F(BaseTest, HasFoo) { // This is an ordinary non-parameterized test. } TEST_P(DerivedTest, DoesBlah) { // GetParam works just the same here as if you inherit from TestWithParam. EXPECT_TRUE(foo.Blah(GetParam())); } #endif // 0 #if !GTEST_OS_SYMBIAN # include #endif // scripts/fuse_gtest.py depends on gtest's own header being #included // *unconditionally*. Therefore these #includes cannot be moved // inside #if GTEST_HAS_PARAM_TEST. // Copyright 2008 Google Inc. // All Rights Reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: vladl@google.com (Vlad Losev) // Type and function utilities for implementing parameterized tests. #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_PARAM_UTIL_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_PARAM_UTIL_H_ #include #include #include // scripts/fuse_gtest.py depends on gtest's own header being #included // *unconditionally*. Therefore these #includes cannot be moved // inside #if GTEST_HAS_PARAM_TEST. // Copyright 2003 Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Authors: Dan Egnor (egnor@google.com) // // A "smart" pointer type with reference tracking. Every pointer to a // particular object is kept on a circular linked list. When the last pointer // to an object is destroyed or reassigned, the object is deleted. // // Used properly, this deletes the object when the last reference goes away. // There are several caveats: // - Like all reference counting schemes, cycles lead to leaks. // - Each smart pointer is actually two pointers (8 bytes instead of 4). // - Every time a pointer is assigned, the entire list of pointers to that // object is traversed. This class is therefore NOT SUITABLE when there // will often be more than two or three pointers to a particular object. // - References are only tracked as long as linked_ptr<> objects are copied. // If a linked_ptr<> is converted to a raw pointer and back, BAD THINGS // will happen (double deletion). // // A good use of this class is storing object references in STL containers. // You can safely put linked_ptr<> in a vector<>. // Other uses may not be as good. // // Note: If you use an incomplete type with linked_ptr<>, the class // *containing* linked_ptr<> must have a constructor and destructor (even // if they do nothing!). // // Bill Gibbons suggested we use something like this. // // Thread Safety: // Unlike other linked_ptr implementations, in this implementation // a linked_ptr object is thread-safe in the sense that: // - it's safe to copy linked_ptr objects concurrently, // - it's safe to copy *from* a linked_ptr and read its underlying // raw pointer (e.g. via get()) concurrently, and // - it's safe to write to two linked_ptrs that point to the same // shared object concurrently. // TODO(wan@google.com): rename this to safe_linked_ptr to avoid // confusion with normal linked_ptr. #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_LINKED_PTR_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_LINKED_PTR_H_ #include #include namespace testing { namespace internal { // Protects copying of all linked_ptr objects. GTEST_API_ GTEST_DECLARE_STATIC_MUTEX_(g_linked_ptr_mutex); // This is used internally by all instances of linked_ptr<>. It needs to be // a non-template class because different types of linked_ptr<> can refer to // the same object (linked_ptr(obj) vs linked_ptr(obj)). // So, it needs to be possible for different types of linked_ptr to participate // in the same circular linked list, so we need a single class type here. // // DO NOT USE THIS CLASS DIRECTLY YOURSELF. Use linked_ptr. class linked_ptr_internal { public: // Create a new circle that includes only this instance. void join_new() { next_ = this; } // Many linked_ptr operations may change p.link_ for some linked_ptr // variable p in the same circle as this object. Therefore we need // to prevent two such operations from occurring concurrently. // // Note that different types of linked_ptr objects can coexist in a // circle (e.g. linked_ptr, linked_ptr, and // linked_ptr). Therefore we must use a single mutex to // protect all linked_ptr objects. This can create serious // contention in production code, but is acceptable in a testing // framework. // Join an existing circle. // L < g_linked_ptr_mutex void join(linked_ptr_internal const* ptr) { MutexLock lock(&g_linked_ptr_mutex); linked_ptr_internal const* p = ptr; while (p->next_ != ptr) p = p->next_; p->next_ = this; next_ = ptr; } // Leave whatever circle we're part of. Returns true if we were the // last member of the circle. Once this is done, you can join() another. // L < g_linked_ptr_mutex bool depart() { MutexLock lock(&g_linked_ptr_mutex); if (next_ == this) return true; linked_ptr_internal const* p = next_; while (p->next_ != this) p = p->next_; p->next_ = next_; return false; } private: mutable linked_ptr_internal const* next_; }; template class linked_ptr { public: typedef T element_type; // Take over ownership of a raw pointer. This should happen as soon as // possible after the object is created. explicit linked_ptr(T* ptr = NULL) { capture(ptr); } ~linked_ptr() { depart(); } // Copy an existing linked_ptr<>, adding ourselves to the list of references. template linked_ptr(linked_ptr const& ptr) { copy(&ptr); } linked_ptr(linked_ptr const& ptr) { // NOLINT assert(&ptr != this); copy(&ptr); } // Assignment releases the old value and acquires the new. template linked_ptr& operator=(linked_ptr const& ptr) { depart(); copy(&ptr); return *this; } linked_ptr& operator=(linked_ptr const& ptr) { if (&ptr != this) { depart(); copy(&ptr); } return *this; } // Smart pointer members. void reset(T* ptr = NULL) { depart(); capture(ptr); } T* get() const { return value_; } T* operator->() const { return value_; } T& operator*() const { return *value_; } bool operator==(T* p) const { return value_ == p; } bool operator!=(T* p) const { return value_ != p; } template bool operator==(linked_ptr const& ptr) const { return value_ == ptr.get(); } template bool operator!=(linked_ptr const& ptr) const { return value_ != ptr.get(); } private: template friend class linked_ptr; T* value_; linked_ptr_internal link_; void depart() { if (link_.depart()) delete value_; } void capture(T* ptr) { value_ = ptr; link_.join_new(); } template void copy(linked_ptr const* ptr) { value_ = ptr->get(); if (value_) link_.join(&ptr->link_); else link_.join_new(); } }; template inline bool operator==(T* ptr, const linked_ptr& x) { return ptr == x.get(); } template inline bool operator!=(T* ptr, const linked_ptr& x) { return ptr != x.get(); } // A function to convert T* into linked_ptr // Doing e.g. make_linked_ptr(new FooBarBaz(arg)) is a shorter notation // for linked_ptr >(new FooBarBaz(arg)) template linked_ptr make_linked_ptr(T* ptr) { return linked_ptr(ptr); } } // namespace internal } // namespace testing #endif // GTEST_INCLUDE_GTEST_INTERNAL_GTEST_LINKED_PTR_H_ // Copyright 2007, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan) // Google Test - The Google C++ Testing Framework // // This file implements a universal value printer that can print a // value of any type T: // // void ::testing::internal::UniversalPrinter::Print(value, ostream_ptr); // // A user can teach this function how to print a class type T by // defining either operator<<() or PrintTo() in the namespace that // defines T. More specifically, the FIRST defined function in the // following list will be used (assuming T is defined in namespace // foo): // // 1. foo::PrintTo(const T&, ostream*) // 2. operator<<(ostream&, const T&) defined in either foo or the // global namespace. // // If none of the above is defined, it will print the debug string of // the value if it is a protocol buffer, or print the raw bytes in the // value otherwise. // // To aid debugging: when T is a reference type, the address of the // value is also printed; when T is a (const) char pointer, both the // pointer value and the NUL-terminated string it points to are // printed. // // We also provide some convenient wrappers: // // // Prints a value to a string. For a (const or not) char // // pointer, the NUL-terminated string (but not the pointer) is // // printed. // std::string ::testing::PrintToString(const T& value); // // // Prints a value tersely: for a reference type, the referenced // // value (but not the address) is printed; for a (const or not) char // // pointer, the NUL-terminated string (but not the pointer) is // // printed. // void ::testing::internal::UniversalTersePrint(const T& value, ostream*); // // // Prints value using the type inferred by the compiler. The difference // // from UniversalTersePrint() is that this function prints both the // // pointer and the NUL-terminated string for a (const or not) char pointer. // void ::testing::internal::UniversalPrint(const T& value, ostream*); // // // Prints the fields of a tuple tersely to a string vector, one // // element for each field. Tuple support must be enabled in // // gtest-port.h. // std::vector UniversalTersePrintTupleFieldsToStrings( // const Tuple& value); // // Known limitation: // // The print primitives print the elements of an STL-style container // using the compiler-inferred type of *iter where iter is a // const_iterator of the container. When const_iterator is an input // iterator but not a forward iterator, this inferred type may not // match value_type, and the print output may be incorrect. In // practice, this is rarely a problem as for most containers // const_iterator is a forward iterator. We'll fix this if there's an // actual need for it. Note that this fix cannot rely on value_type // being defined as many user-defined container types don't have // value_type. #ifndef GTEST_INCLUDE_GTEST_GTEST_PRINTERS_H_ #define GTEST_INCLUDE_GTEST_GTEST_PRINTERS_H_ #include // NOLINT #include #include #include #include namespace testing { // Definitions in the 'internal' and 'internal2' name spaces are // subject to change without notice. DO NOT USE THEM IN USER CODE! namespace internal2 { // Prints the given number of bytes in the given object to the given // ostream. GTEST_API_ void PrintBytesInObjectTo(const unsigned char* obj_bytes, size_t count, ::std::ostream* os); // For selecting which printer to use when a given type has neither << // nor PrintTo(). enum TypeKind { kProtobuf, // a protobuf type kConvertibleToInteger, // a type implicitly convertible to BiggestInt // (e.g. a named or unnamed enum type) kOtherType // anything else }; // TypeWithoutFormatter::PrintValue(value, os) is called // by the universal printer to print a value of type T when neither // operator<< nor PrintTo() is defined for T, where kTypeKind is the // "kind" of T as defined by enum TypeKind. template class TypeWithoutFormatter { public: // This default version is called when kTypeKind is kOtherType. static void PrintValue(const T& value, ::std::ostream* os) { PrintBytesInObjectTo(reinterpret_cast(&value), sizeof(value), os); } }; // We print a protobuf using its ShortDebugString() when the string // doesn't exceed this many characters; otherwise we print it using // DebugString() for better readability. const size_t kProtobufOneLinerMaxLength = 50; template class TypeWithoutFormatter { public: static void PrintValue(const T& value, ::std::ostream* os) { const ::testing::internal::string short_str = value.ShortDebugString(); const ::testing::internal::string pretty_str = short_str.length() <= kProtobufOneLinerMaxLength ? short_str : ("\n" + value.DebugString()); *os << ("<" + pretty_str + ">"); } }; template class TypeWithoutFormatter { public: // Since T has no << operator or PrintTo() but can be implicitly // converted to BiggestInt, we print it as a BiggestInt. // // Most likely T is an enum type (either named or unnamed), in which // case printing it as an integer is the desired behavior. In case // T is not an enum, printing it as an integer is the best we can do // given that it has no user-defined printer. static void PrintValue(const T& value, ::std::ostream* os) { const internal::BiggestInt kBigInt = value; *os << kBigInt; } }; // Prints the given value to the given ostream. If the value is a // protocol message, its debug string is printed; if it's an enum or // of a type implicitly convertible to BiggestInt, it's printed as an // integer; otherwise the bytes in the value are printed. This is // what UniversalPrinter::Print() does when it knows nothing about // type T and T has neither << operator nor PrintTo(). // // A user can override this behavior for a class type Foo by defining // a << operator in the namespace where Foo is defined. // // We put this operator in namespace 'internal2' instead of 'internal' // to simplify the implementation, as much code in 'internal' needs to // use << in STL, which would conflict with our own << were it defined // in 'internal'. // // Note that this operator<< takes a generic std::basic_ostream type instead of the more restricted std::ostream. If // we define it to take an std::ostream instead, we'll get an // "ambiguous overloads" compiler error when trying to print a type // Foo that supports streaming to std::basic_ostream, as the compiler cannot tell whether // operator<<(std::ostream&, const T&) or // operator<<(std::basic_stream, const Foo&) is more // specific. template ::std::basic_ostream& operator<<( ::std::basic_ostream& os, const T& x) { TypeWithoutFormatter::value ? kProtobuf : internal::ImplicitlyConvertible::value ? kConvertibleToInteger : kOtherType)>::PrintValue(x, &os); return os; } } // namespace internal2 } // namespace testing // This namespace MUST NOT BE NESTED IN ::testing, or the name look-up // magic needed for implementing UniversalPrinter won't work. namespace testing_internal { // Used to print a value that is not an STL-style container when the // user doesn't define PrintTo() for it. template void DefaultPrintNonContainerTo(const T& value, ::std::ostream* os) { // With the following statement, during unqualified name lookup, // testing::internal2::operator<< appears as if it was declared in // the nearest enclosing namespace that contains both // ::testing_internal and ::testing::internal2, i.e. the global // namespace. For more details, refer to the C++ Standard section // 7.3.4-1 [namespace.udir]. This allows us to fall back onto // testing::internal2::operator<< in case T doesn't come with a << // operator. // // We cannot write 'using ::testing::internal2::operator<<;', which // gcc 3.3 fails to compile due to a compiler bug. using namespace ::testing::internal2; // NOLINT // Assuming T is defined in namespace foo, in the next statement, // the compiler will consider all of: // // 1. foo::operator<< (thanks to Koenig look-up), // 2. ::operator<< (as the current namespace is enclosed in ::), // 3. testing::internal2::operator<< (thanks to the using statement above). // // The operator<< whose type matches T best will be picked. // // We deliberately allow #2 to be a candidate, as sometimes it's // impossible to define #1 (e.g. when foo is ::std, defining // anything in it is undefined behavior unless you are a compiler // vendor.). *os << value; } } // namespace testing_internal namespace testing { namespace internal { // UniversalPrinter::Print(value, ostream_ptr) prints the given // value to the given ostream. The caller must ensure that // 'ostream_ptr' is not NULL, or the behavior is undefined. // // We define UniversalPrinter as a class template (as opposed to a // function template), as we need to partially specialize it for // reference types, which cannot be done with function templates. template class UniversalPrinter; template void UniversalPrint(const T& value, ::std::ostream* os); // Used to print an STL-style container when the user doesn't define // a PrintTo() for it. template void DefaultPrintTo(IsContainer /* dummy */, false_type /* is not a pointer */, const C& container, ::std::ostream* os) { const size_t kMaxCount = 32; // The maximum number of elements to print. *os << '{'; size_t count = 0; for (typename C::const_iterator it = container.begin(); it != container.end(); ++it, ++count) { if (count > 0) { *os << ','; if (count == kMaxCount) { // Enough has been printed. *os << " ..."; break; } } *os << ' '; // We cannot call PrintTo(*it, os) here as PrintTo() doesn't // handle *it being a native array. internal::UniversalPrint(*it, os); } if (count > 0) { *os << ' '; } *os << '}'; } // Used to print a pointer that is neither a char pointer nor a member // pointer, when the user doesn't define PrintTo() for it. (A member // variable pointer or member function pointer doesn't really point to // a location in the address space. Their representation is // implementation-defined. Therefore they will be printed as raw // bytes.) template void DefaultPrintTo(IsNotContainer /* dummy */, true_type /* is a pointer */, T* p, ::std::ostream* os) { if (p == NULL) { *os << "NULL"; } else { // C++ doesn't allow casting from a function pointer to any object // pointer. // // IsTrue() silences warnings: "Condition is always true", // "unreachable code". if (IsTrue(ImplicitlyConvertible::value)) { // T is not a function type. We just call << to print p, // relying on ADL to pick up user-defined << for their pointer // types, if any. *os << p; } else { // T is a function type, so '*os << p' doesn't do what we want // (it just prints p as bool). We want to print p as a const // void*. However, we cannot cast it to const void* directly, // even using reinterpret_cast, as earlier versions of gcc // (e.g. 3.4.5) cannot compile the cast when p is a function // pointer. Casting to uintptr_t first solves the problem. *os << reinterpret_cast( reinterpret_cast(p)); } } } // Used to print a non-container, non-pointer value when the user // doesn't define PrintTo() for it. template void DefaultPrintTo(IsNotContainer /* dummy */, false_type /* is not a pointer */, const T& value, ::std::ostream* os) { ::testing_internal::DefaultPrintNonContainerTo(value, os); } // Prints the given value using the << operator if it has one; // otherwise prints the bytes in it. This is what // UniversalPrinter::Print() does when PrintTo() is not specialized // or overloaded for type T. // // A user can override this behavior for a class type Foo by defining // an overload of PrintTo() in the namespace where Foo is defined. We // give the user this option as sometimes defining a << operator for // Foo is not desirable (e.g. the coding style may prevent doing it, // or there is already a << operator but it doesn't do what the user // wants). template void PrintTo(const T& value, ::std::ostream* os) { // DefaultPrintTo() is overloaded. The type of its first two // arguments determine which version will be picked. If T is an // STL-style container, the version for container will be called; if // T is a pointer, the pointer version will be called; otherwise the // generic version will be called. // // Note that we check for container types here, prior to we check // for protocol message types in our operator<<. The rationale is: // // For protocol messages, we want to give people a chance to // override Google Mock's format by defining a PrintTo() or // operator<<. For STL containers, other formats can be // incompatible with Google Mock's format for the container // elements; therefore we check for container types here to ensure // that our format is used. // // The second argument of DefaultPrintTo() is needed to bypass a bug // in Symbian's C++ compiler that prevents it from picking the right // overload between: // // PrintTo(const T& x, ...); // PrintTo(T* x, ...); DefaultPrintTo(IsContainerTest(0), is_pointer(), value, os); } // The following list of PrintTo() overloads tells // UniversalPrinter::Print() how to print standard types (built-in // types, strings, plain arrays, and pointers). // Overloads for various char types. GTEST_API_ void PrintTo(unsigned char c, ::std::ostream* os); GTEST_API_ void PrintTo(signed char c, ::std::ostream* os); inline void PrintTo(char c, ::std::ostream* os) { // When printing a plain char, we always treat it as unsigned. This // way, the output won't be affected by whether the compiler thinks // char is signed or not. PrintTo(static_cast(c), os); } // Overloads for other simple built-in types. inline void PrintTo(bool x, ::std::ostream* os) { *os << (x ? "true" : "false"); } // Overload for wchar_t type. // Prints a wchar_t as a symbol if it is printable or as its internal // code otherwise and also as its decimal code (except for L'\0'). // The L'\0' char is printed as "L'\\0'". The decimal code is printed // as signed integer when wchar_t is implemented by the compiler // as a signed type and is printed as an unsigned integer when wchar_t // is implemented as an unsigned type. GTEST_API_ void PrintTo(wchar_t wc, ::std::ostream* os); // Overloads for C strings. GTEST_API_ void PrintTo(const char* s, ::std::ostream* os); inline void PrintTo(char* s, ::std::ostream* os) { PrintTo(ImplicitCast_(s), os); } // signed/unsigned char is often used for representing binary data, so // we print pointers to it as void* to be safe. inline void PrintTo(const signed char* s, ::std::ostream* os) { PrintTo(ImplicitCast_(s), os); } inline void PrintTo(signed char* s, ::std::ostream* os) { PrintTo(ImplicitCast_(s), os); } inline void PrintTo(const unsigned char* s, ::std::ostream* os) { PrintTo(ImplicitCast_(s), os); } inline void PrintTo(unsigned char* s, ::std::ostream* os) { PrintTo(ImplicitCast_(s), os); } // MSVC can be configured to define wchar_t as a typedef of unsigned // short. It defines _NATIVE_WCHAR_T_DEFINED when wchar_t is a native // type. When wchar_t is a typedef, defining an overload for const // wchar_t* would cause unsigned short* be printed as a wide string, // possibly causing invalid memory accesses. #if !defined(_MSC_VER) || defined(_NATIVE_WCHAR_T_DEFINED) // Overloads for wide C strings GTEST_API_ void PrintTo(const wchar_t* s, ::std::ostream* os); inline void PrintTo(wchar_t* s, ::std::ostream* os) { PrintTo(ImplicitCast_(s), os); } #endif // Overload for C arrays. Multi-dimensional arrays are printed // properly. // Prints the given number of elements in an array, without printing // the curly braces. template void PrintRawArrayTo(const T a[], size_t count, ::std::ostream* os) { UniversalPrint(a[0], os); for (size_t i = 1; i != count; i++) { *os << ", "; UniversalPrint(a[i], os); } } // Overloads for ::string and ::std::string. #if GTEST_HAS_GLOBAL_STRING GTEST_API_ void PrintStringTo(const ::string&s, ::std::ostream* os); inline void PrintTo(const ::string& s, ::std::ostream* os) { PrintStringTo(s, os); } #endif // GTEST_HAS_GLOBAL_STRING GTEST_API_ void PrintStringTo(const ::std::string&s, ::std::ostream* os); inline void PrintTo(const ::std::string& s, ::std::ostream* os) { PrintStringTo(s, os); } // Overloads for ::wstring and ::std::wstring. #if GTEST_HAS_GLOBAL_WSTRING GTEST_API_ void PrintWideStringTo(const ::wstring&s, ::std::ostream* os); inline void PrintTo(const ::wstring& s, ::std::ostream* os) { PrintWideStringTo(s, os); } #endif // GTEST_HAS_GLOBAL_WSTRING #if GTEST_HAS_STD_WSTRING GTEST_API_ void PrintWideStringTo(const ::std::wstring&s, ::std::ostream* os); inline void PrintTo(const ::std::wstring& s, ::std::ostream* os) { PrintWideStringTo(s, os); } #endif // GTEST_HAS_STD_WSTRING #if GTEST_HAS_TR1_TUPLE // Overload for ::std::tr1::tuple. Needed for printing function arguments, // which are packed as tuples. // Helper function for printing a tuple. T must be instantiated with // a tuple type. template void PrintTupleTo(const T& t, ::std::ostream* os); // Overloaded PrintTo() for tuples of various arities. We support // tuples of up-to 10 fields. The following implementation works // regardless of whether tr1::tuple is implemented using the // non-standard variadic template feature or not. inline void PrintTo(const ::std::tr1::tuple<>& t, ::std::ostream* os) { PrintTupleTo(t, os); } template void PrintTo(const ::std::tr1::tuple& t, ::std::ostream* os) { PrintTupleTo(t, os); } template void PrintTo(const ::std::tr1::tuple& t, ::std::ostream* os) { PrintTupleTo(t, os); } template void PrintTo(const ::std::tr1::tuple& t, ::std::ostream* os) { PrintTupleTo(t, os); } template void PrintTo(const ::std::tr1::tuple& t, ::std::ostream* os) { PrintTupleTo(t, os); } template void PrintTo(const ::std::tr1::tuple& t, ::std::ostream* os) { PrintTupleTo(t, os); } template void PrintTo(const ::std::tr1::tuple& t, ::std::ostream* os) { PrintTupleTo(t, os); } template void PrintTo(const ::std::tr1::tuple& t, ::std::ostream* os) { PrintTupleTo(t, os); } template void PrintTo(const ::std::tr1::tuple& t, ::std::ostream* os) { PrintTupleTo(t, os); } template void PrintTo(const ::std::tr1::tuple& t, ::std::ostream* os) { PrintTupleTo(t, os); } template void PrintTo( const ::std::tr1::tuple& t, ::std::ostream* os) { PrintTupleTo(t, os); } #endif // GTEST_HAS_TR1_TUPLE // Overload for std::pair. template void PrintTo(const ::std::pair& value, ::std::ostream* os) { *os << '('; // We cannot use UniversalPrint(value.first, os) here, as T1 may be // a reference type. The same for printing value.second. UniversalPrinter::Print(value.first, os); *os << ", "; UniversalPrinter::Print(value.second, os); *os << ')'; } // Implements printing a non-reference type T by letting the compiler // pick the right overload of PrintTo() for T. template class UniversalPrinter { public: // MSVC warns about adding const to a function type, so we want to // disable the warning. #ifdef _MSC_VER # pragma warning(push) // Saves the current warning state. # pragma warning(disable:4180) // Temporarily disables warning 4180. #endif // _MSC_VER // Note: we deliberately don't call this PrintTo(), as that name // conflicts with ::testing::internal::PrintTo in the body of the // function. static void Print(const T& value, ::std::ostream* os) { // By default, ::testing::internal::PrintTo() is used for printing // the value. // // Thanks to Koenig look-up, if T is a class and has its own // PrintTo() function defined in its namespace, that function will // be visible here. Since it is more specific than the generic ones // in ::testing::internal, it will be picked by the compiler in the // following statement - exactly what we want. PrintTo(value, os); } #ifdef _MSC_VER # pragma warning(pop) // Restores the warning state. #endif // _MSC_VER }; // UniversalPrintArray(begin, len, os) prints an array of 'len' // elements, starting at address 'begin'. template void UniversalPrintArray(const T* begin, size_t len, ::std::ostream* os) { if (len == 0) { *os << "{}"; } else { *os << "{ "; const size_t kThreshold = 18; const size_t kChunkSize = 8; // If the array has more than kThreshold elements, we'll have to // omit some details by printing only the first and the last // kChunkSize elements. // TODO(wan@google.com): let the user control the threshold using a flag. if (len <= kThreshold) { PrintRawArrayTo(begin, len, os); } else { PrintRawArrayTo(begin, kChunkSize, os); *os << ", ..., "; PrintRawArrayTo(begin + len - kChunkSize, kChunkSize, os); } *os << " }"; } } // This overload prints a (const) char array compactly. GTEST_API_ void UniversalPrintArray(const char* begin, size_t len, ::std::ostream* os); // Implements printing an array type T[N]. template class UniversalPrinter { public: // Prints the given array, omitting some elements when there are too // many. static void Print(const T (&a)[N], ::std::ostream* os) { UniversalPrintArray(a, N, os); } }; // Implements printing a reference type T&. template class UniversalPrinter { public: // MSVC warns about adding const to a function type, so we want to // disable the warning. #ifdef _MSC_VER # pragma warning(push) // Saves the current warning state. # pragma warning(disable:4180) // Temporarily disables warning 4180. #endif // _MSC_VER static void Print(const T& value, ::std::ostream* os) { // Prints the address of the value. We use reinterpret_cast here // as static_cast doesn't compile when T is a function type. *os << "@" << reinterpret_cast(&value) << " "; // Then prints the value itself. UniversalPrint(value, os); } #ifdef _MSC_VER # pragma warning(pop) // Restores the warning state. #endif // _MSC_VER }; // Prints a value tersely: for a reference type, the referenced value // (but not the address) is printed; for a (const) char pointer, the // NUL-terminated string (but not the pointer) is printed. template void UniversalTersePrint(const T& value, ::std::ostream* os) { UniversalPrint(value, os); } inline void UniversalTersePrint(const char* str, ::std::ostream* os) { if (str == NULL) { *os << "NULL"; } else { UniversalPrint(string(str), os); } } inline void UniversalTersePrint(char* str, ::std::ostream* os) { UniversalTersePrint(static_cast(str), os); } // Prints a value using the type inferred by the compiler. The // difference between this and UniversalTersePrint() is that for a // (const) char pointer, this prints both the pointer and the // NUL-terminated string. template void UniversalPrint(const T& value, ::std::ostream* os) { UniversalPrinter::Print(value, os); } #if GTEST_HAS_TR1_TUPLE typedef ::std::vector Strings; // This helper template allows PrintTo() for tuples and // UniversalTersePrintTupleFieldsToStrings() to be defined by // induction on the number of tuple fields. The idea is that // TuplePrefixPrinter::PrintPrefixTo(t, os) prints the first N // fields in tuple t, and can be defined in terms of // TuplePrefixPrinter. // The inductive case. template struct TuplePrefixPrinter { // Prints the first N fields of a tuple. template static void PrintPrefixTo(const Tuple& t, ::std::ostream* os) { TuplePrefixPrinter::PrintPrefixTo(t, os); *os << ", "; UniversalPrinter::type> ::Print(::std::tr1::get(t), os); } // Tersely prints the first N fields of a tuple to a string vector, // one element for each field. template static void TersePrintPrefixToStrings(const Tuple& t, Strings* strings) { TuplePrefixPrinter::TersePrintPrefixToStrings(t, strings); ::std::stringstream ss; UniversalTersePrint(::std::tr1::get(t), &ss); strings->push_back(ss.str()); } }; // Base cases. template <> struct TuplePrefixPrinter<0> { template static void PrintPrefixTo(const Tuple&, ::std::ostream*) {} template static void TersePrintPrefixToStrings(const Tuple&, Strings*) {} }; // We have to specialize the entire TuplePrefixPrinter<> class // template here, even though the definition of // TersePrintPrefixToStrings() is the same as the generic version, as // Embarcadero (formerly CodeGear, formerly Borland) C++ doesn't // support specializing a method template of a class template. template <> struct TuplePrefixPrinter<1> { template static void PrintPrefixTo(const Tuple& t, ::std::ostream* os) { UniversalPrinter::type>:: Print(::std::tr1::get<0>(t), os); } template static void TersePrintPrefixToStrings(const Tuple& t, Strings* strings) { ::std::stringstream ss; UniversalTersePrint(::std::tr1::get<0>(t), &ss); strings->push_back(ss.str()); } }; // Helper function for printing a tuple. T must be instantiated with // a tuple type. template void PrintTupleTo(const T& t, ::std::ostream* os) { *os << "("; TuplePrefixPrinter< ::std::tr1::tuple_size::value>:: PrintPrefixTo(t, os); *os << ")"; } // Prints the fields of a tuple tersely to a string vector, one // element for each field. See the comment before // UniversalTersePrint() for how we define "tersely". template Strings UniversalTersePrintTupleFieldsToStrings(const Tuple& value) { Strings result; TuplePrefixPrinter< ::std::tr1::tuple_size::value>:: TersePrintPrefixToStrings(value, &result); return result; } #endif // GTEST_HAS_TR1_TUPLE } // namespace internal template ::std::string PrintToString(const T& value) { ::std::stringstream ss; internal::UniversalTersePrint(value, &ss); return ss.str(); } } // namespace testing #endif // GTEST_INCLUDE_GTEST_GTEST_PRINTERS_H_ #if GTEST_HAS_PARAM_TEST namespace testing { namespace internal { // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // Outputs a message explaining invalid registration of different // fixture class for the same test case. This may happen when // TEST_P macro is used to define two tests with the same name // but in different namespaces. GTEST_API_ void ReportInvalidTestCaseType(const char* test_case_name, const char* file, int line); template class ParamGeneratorInterface; template class ParamGenerator; // Interface for iterating over elements provided by an implementation // of ParamGeneratorInterface. template class ParamIteratorInterface { public: virtual ~ParamIteratorInterface() {} // A pointer to the base generator instance. // Used only for the purposes of iterator comparison // to make sure that two iterators belong to the same generator. virtual const ParamGeneratorInterface* BaseGenerator() const = 0; // Advances iterator to point to the next element // provided by the generator. The caller is responsible // for not calling Advance() on an iterator equal to // BaseGenerator()->End(). virtual void Advance() = 0; // Clones the iterator object. Used for implementing copy semantics // of ParamIterator. virtual ParamIteratorInterface* Clone() const = 0; // Dereferences the current iterator and provides (read-only) access // to the pointed value. It is the caller's responsibility not to call // Current() on an iterator equal to BaseGenerator()->End(). // Used for implementing ParamGenerator::operator*(). virtual const T* Current() const = 0; // Determines whether the given iterator and other point to the same // element in the sequence generated by the generator. // Used for implementing ParamGenerator::operator==(). virtual bool Equals(const ParamIteratorInterface& other) const = 0; }; // Class iterating over elements provided by an implementation of // ParamGeneratorInterface. It wraps ParamIteratorInterface // and implements the const forward iterator concept. template class ParamIterator { public: typedef T value_type; typedef const T& reference; typedef ptrdiff_t difference_type; // ParamIterator assumes ownership of the impl_ pointer. ParamIterator(const ParamIterator& other) : impl_(other.impl_->Clone()) {} ParamIterator& operator=(const ParamIterator& other) { if (this != &other) impl_.reset(other.impl_->Clone()); return *this; } const T& operator*() const { return *impl_->Current(); } const T* operator->() const { return impl_->Current(); } // Prefix version of operator++. ParamIterator& operator++() { impl_->Advance(); return *this; } // Postfix version of operator++. ParamIterator operator++(int /*unused*/) { ParamIteratorInterface* clone = impl_->Clone(); impl_->Advance(); return ParamIterator(clone); } bool operator==(const ParamIterator& other) const { return impl_.get() == other.impl_.get() || impl_->Equals(*other.impl_); } bool operator!=(const ParamIterator& other) const { return !(*this == other); } private: friend class ParamGenerator; explicit ParamIterator(ParamIteratorInterface* impl) : impl_(impl) {} scoped_ptr > impl_; }; // ParamGeneratorInterface is the binary interface to access generators // defined in other translation units. template class ParamGeneratorInterface { public: typedef T ParamType; virtual ~ParamGeneratorInterface() {} // Generator interface definition virtual ParamIteratorInterface* Begin() const = 0; virtual ParamIteratorInterface* End() const = 0; }; // Wraps ParamGeneratorInterface and provides general generator syntax // compatible with the STL Container concept. // This class implements copy initialization semantics and the contained // ParamGeneratorInterface instance is shared among all copies // of the original object. This is possible because that instance is immutable. template class ParamGenerator { public: typedef ParamIterator iterator; explicit ParamGenerator(ParamGeneratorInterface* impl) : impl_(impl) {} ParamGenerator(const ParamGenerator& other) : impl_(other.impl_) {} ParamGenerator& operator=(const ParamGenerator& other) { impl_ = other.impl_; return *this; } iterator begin() const { return iterator(impl_->Begin()); } iterator end() const { return iterator(impl_->End()); } private: linked_ptr > impl_; }; // Generates values from a range of two comparable values. Can be used to // generate sequences of user-defined types that implement operator+() and // operator<(). // This class is used in the Range() function. template class RangeGenerator : public ParamGeneratorInterface { public: RangeGenerator(T begin, T end, IncrementT step) : begin_(begin), end_(end), step_(step), end_index_(CalculateEndIndex(begin, end, step)) {} virtual ~RangeGenerator() {} virtual ParamIteratorInterface* Begin() const { return new Iterator(this, begin_, 0, step_); } virtual ParamIteratorInterface* End() const { return new Iterator(this, end_, end_index_, step_); } private: class Iterator : public ParamIteratorInterface { public: Iterator(const ParamGeneratorInterface* base, T value, int index, IncrementT step) : base_(base), value_(value), index_(index), step_(step) {} virtual ~Iterator() {} virtual const ParamGeneratorInterface* BaseGenerator() const { return base_; } virtual void Advance() { value_ = value_ + step_; index_++; } virtual ParamIteratorInterface* Clone() const { return new Iterator(*this); } virtual const T* Current() const { return &value_; } virtual bool Equals(const ParamIteratorInterface& other) const { // Having the same base generator guarantees that the other // iterator is of the same type and we can downcast. GTEST_CHECK_(BaseGenerator() == other.BaseGenerator()) << "The program attempted to compare iterators " << "from different generators." << std::endl; const int other_index = CheckedDowncastToActualType(&other)->index_; return index_ == other_index; } private: Iterator(const Iterator& other) : ParamIteratorInterface(), base_(other.base_), value_(other.value_), index_(other.index_), step_(other.step_) {} // No implementation - assignment is unsupported. void operator=(const Iterator& other); const ParamGeneratorInterface* const base_; T value_; int index_; const IncrementT step_; }; // class RangeGenerator::Iterator static int CalculateEndIndex(const T& begin, const T& end, const IncrementT& step) { int end_index = 0; for (T i = begin; i < end; i = i + step) end_index++; return end_index; } // No implementation - assignment is unsupported. void operator=(const RangeGenerator& other); const T begin_; const T end_; const IncrementT step_; // The index for the end() iterator. All the elements in the generated // sequence are indexed (0-based) to aid iterator comparison. const int end_index_; }; // class RangeGenerator // Generates values from a pair of STL-style iterators. Used in the // ValuesIn() function. The elements are copied from the source range // since the source can be located on the stack, and the generator // is likely to persist beyond that stack frame. template class ValuesInIteratorRangeGenerator : public ParamGeneratorInterface { public: template ValuesInIteratorRangeGenerator(ForwardIterator begin, ForwardIterator end) : container_(begin, end) {} virtual ~ValuesInIteratorRangeGenerator() {} virtual ParamIteratorInterface* Begin() const { return new Iterator(this, container_.begin()); } virtual ParamIteratorInterface* End() const { return new Iterator(this, container_.end()); } private: typedef typename ::std::vector ContainerType; class Iterator : public ParamIteratorInterface { public: Iterator(const ParamGeneratorInterface* base, typename ContainerType::const_iterator iterator) : base_(base), iterator_(iterator) {} virtual ~Iterator() {} virtual const ParamGeneratorInterface* BaseGenerator() const { return base_; } virtual void Advance() { ++iterator_; value_.reset(); } virtual ParamIteratorInterface* Clone() const { return new Iterator(*this); } // We need to use cached value referenced by iterator_ because *iterator_ // can return a temporary object (and of type other then T), so just // having "return &*iterator_;" doesn't work. // value_ is updated here and not in Advance() because Advance() // can advance iterator_ beyond the end of the range, and we cannot // detect that fact. The client code, on the other hand, is // responsible for not calling Current() on an out-of-range iterator. virtual const T* Current() const { if (value_.get() == NULL) value_.reset(new T(*iterator_)); return value_.get(); } virtual bool Equals(const ParamIteratorInterface& other) const { // Having the same base generator guarantees that the other // iterator is of the same type and we can downcast. GTEST_CHECK_(BaseGenerator() == other.BaseGenerator()) << "The program attempted to compare iterators " << "from different generators." << std::endl; return iterator_ == CheckedDowncastToActualType(&other)->iterator_; } private: Iterator(const Iterator& other) // The explicit constructor call suppresses a false warning // emitted by gcc when supplied with the -Wextra option. : ParamIteratorInterface(), base_(other.base_), iterator_(other.iterator_) {} const ParamGeneratorInterface* const base_; typename ContainerType::const_iterator iterator_; // A cached value of *iterator_. We keep it here to allow access by // pointer in the wrapping iterator's operator->(). // value_ needs to be mutable to be accessed in Current(). // Use of scoped_ptr helps manage cached value's lifetime, // which is bound by the lifespan of the iterator itself. mutable scoped_ptr value_; }; // class ValuesInIteratorRangeGenerator::Iterator // No implementation - assignment is unsupported. void operator=(const ValuesInIteratorRangeGenerator& other); const ContainerType container_; }; // class ValuesInIteratorRangeGenerator // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // Stores a parameter value and later creates tests parameterized with that // value. template class ParameterizedTestFactory : public TestFactoryBase { public: typedef typename TestClass::ParamType ParamType; explicit ParameterizedTestFactory(ParamType parameter) : parameter_(parameter) {} virtual Test* CreateTest() { TestClass::SetParam(¶meter_); return new TestClass(); } private: const ParamType parameter_; GTEST_DISALLOW_COPY_AND_ASSIGN_(ParameterizedTestFactory); }; // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // TestMetaFactoryBase is a base class for meta-factories that create // test factories for passing into MakeAndRegisterTestInfo function. template class TestMetaFactoryBase { public: virtual ~TestMetaFactoryBase() {} virtual TestFactoryBase* CreateTestFactory(ParamType parameter) = 0; }; // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // TestMetaFactory creates test factories for passing into // MakeAndRegisterTestInfo function. Since MakeAndRegisterTestInfo receives // ownership of test factory pointer, same factory object cannot be passed // into that method twice. But ParameterizedTestCaseInfo is going to call // it for each Test/Parameter value combination. Thus it needs meta factory // creator class. template class TestMetaFactory : public TestMetaFactoryBase { public: typedef typename TestCase::ParamType ParamType; TestMetaFactory() {} virtual TestFactoryBase* CreateTestFactory(ParamType parameter) { return new ParameterizedTestFactory(parameter); } private: GTEST_DISALLOW_COPY_AND_ASSIGN_(TestMetaFactory); }; // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // ParameterizedTestCaseInfoBase is a generic interface // to ParameterizedTestCaseInfo classes. ParameterizedTestCaseInfoBase // accumulates test information provided by TEST_P macro invocations // and generators provided by INSTANTIATE_TEST_CASE_P macro invocations // and uses that information to register all resulting test instances // in RegisterTests method. The ParameterizeTestCaseRegistry class holds // a collection of pointers to the ParameterizedTestCaseInfo objects // and calls RegisterTests() on each of them when asked. class ParameterizedTestCaseInfoBase { public: virtual ~ParameterizedTestCaseInfoBase() {} // Base part of test case name for display purposes. virtual const string& GetTestCaseName() const = 0; // Test case id to verify identity. virtual TypeId GetTestCaseTypeId() const = 0; // UnitTest class invokes this method to register tests in this // test case right before running them in RUN_ALL_TESTS macro. // This method should not be called more then once on any single // instance of a ParameterizedTestCaseInfoBase derived class. virtual void RegisterTests() = 0; protected: ParameterizedTestCaseInfoBase() {} private: GTEST_DISALLOW_COPY_AND_ASSIGN_(ParameterizedTestCaseInfoBase); }; // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // ParameterizedTestCaseInfo accumulates tests obtained from TEST_P // macro invocations for a particular test case and generators // obtained from INSTANTIATE_TEST_CASE_P macro invocations for that // test case. It registers tests with all values generated by all // generators when asked. template class ParameterizedTestCaseInfo : public ParameterizedTestCaseInfoBase { public: // ParamType and GeneratorCreationFunc are private types but are required // for declarations of public methods AddTestPattern() and // AddTestCaseInstantiation(). typedef typename TestCase::ParamType ParamType; // A function that returns an instance of appropriate generator type. typedef ParamGenerator(GeneratorCreationFunc)(); explicit ParameterizedTestCaseInfo(const char* name) : test_case_name_(name) {} // Test case base name for display purposes. virtual const string& GetTestCaseName() const { return test_case_name_; } // Test case id to verify identity. virtual TypeId GetTestCaseTypeId() const { return GetTypeId(); } // TEST_P macro uses AddTestPattern() to record information // about a single test in a LocalTestInfo structure. // test_case_name is the base name of the test case (without invocation // prefix). test_base_name is the name of an individual test without // parameter index. For the test SequenceA/FooTest.DoBar/1 FooTest is // test case base name and DoBar is test base name. void AddTestPattern(const char* test_case_name, const char* test_base_name, TestMetaFactoryBase* meta_factory) { tests_.push_back(linked_ptr(new TestInfo(test_case_name, test_base_name, meta_factory))); } // INSTANTIATE_TEST_CASE_P macro uses AddGenerator() to record information // about a generator. int AddTestCaseInstantiation(const string& instantiation_name, GeneratorCreationFunc* func, const char* /* file */, int /* line */) { instantiations_.push_back(::std::make_pair(instantiation_name, func)); return 0; // Return value used only to run this method in namespace scope. } // UnitTest class invokes this method to register tests in this test case // test cases right before running tests in RUN_ALL_TESTS macro. // This method should not be called more then once on any single // instance of a ParameterizedTestCaseInfoBase derived class. // UnitTest has a guard to prevent from calling this method more then once. virtual void RegisterTests() { for (typename TestInfoContainer::iterator test_it = tests_.begin(); test_it != tests_.end(); ++test_it) { linked_ptr test_info = *test_it; for (typename InstantiationContainer::iterator gen_it = instantiations_.begin(); gen_it != instantiations_.end(); ++gen_it) { const string& instantiation_name = gen_it->first; ParamGenerator generator((*gen_it->second)()); Message test_case_name_stream; if ( !instantiation_name.empty() ) test_case_name_stream << instantiation_name << "/"; test_case_name_stream << test_info->test_case_base_name; int i = 0; for (typename ParamGenerator::iterator param_it = generator.begin(); param_it != generator.end(); ++param_it, ++i) { Message test_name_stream; test_name_stream << test_info->test_base_name << "/" << i; MakeAndRegisterTestInfo( test_case_name_stream.GetString().c_str(), test_name_stream.GetString().c_str(), NULL, // No type parameter. PrintToString(*param_it).c_str(), GetTestCaseTypeId(), TestCase::SetUpTestCase, TestCase::TearDownTestCase, test_info->test_meta_factory->CreateTestFactory(*param_it)); } // for param_it } // for gen_it } // for test_it } // RegisterTests private: // LocalTestInfo structure keeps information about a single test registered // with TEST_P macro. struct TestInfo { TestInfo(const char* a_test_case_base_name, const char* a_test_base_name, TestMetaFactoryBase* a_test_meta_factory) : test_case_base_name(a_test_case_base_name), test_base_name(a_test_base_name), test_meta_factory(a_test_meta_factory) {} const string test_case_base_name; const string test_base_name; const scoped_ptr > test_meta_factory; }; typedef ::std::vector > TestInfoContainer; // Keeps pairs of // received from INSTANTIATE_TEST_CASE_P macros. typedef ::std::vector > InstantiationContainer; const string test_case_name_; TestInfoContainer tests_; InstantiationContainer instantiations_; GTEST_DISALLOW_COPY_AND_ASSIGN_(ParameterizedTestCaseInfo); }; // class ParameterizedTestCaseInfo // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // ParameterizedTestCaseRegistry contains a map of ParameterizedTestCaseInfoBase // classes accessed by test case names. TEST_P and INSTANTIATE_TEST_CASE_P // macros use it to locate their corresponding ParameterizedTestCaseInfo // descriptors. class ParameterizedTestCaseRegistry { public: ParameterizedTestCaseRegistry() {} ~ParameterizedTestCaseRegistry() { for (TestCaseInfoContainer::iterator it = test_case_infos_.begin(); it != test_case_infos_.end(); ++it) { delete *it; } } // Looks up or creates and returns a structure containing information about // tests and instantiations of a particular test case. template ParameterizedTestCaseInfo* GetTestCasePatternHolder( const char* test_case_name, const char* file, int line) { ParameterizedTestCaseInfo* typed_test_info = NULL; for (TestCaseInfoContainer::iterator it = test_case_infos_.begin(); it != test_case_infos_.end(); ++it) { if ((*it)->GetTestCaseName() == test_case_name) { if ((*it)->GetTestCaseTypeId() != GetTypeId()) { // Complain about incorrect usage of Google Test facilities // and terminate the program since we cannot guaranty correct // test case setup and tear-down in this case. ReportInvalidTestCaseType(test_case_name, file, line); posix::Abort(); } else { // At this point we are sure that the object we found is of the same // type we are looking for, so we downcast it to that type // without further checks. typed_test_info = CheckedDowncastToActualType< ParameterizedTestCaseInfo >(*it); } break; } } if (typed_test_info == NULL) { typed_test_info = new ParameterizedTestCaseInfo(test_case_name); test_case_infos_.push_back(typed_test_info); } return typed_test_info; } void RegisterTests() { for (TestCaseInfoContainer::iterator it = test_case_infos_.begin(); it != test_case_infos_.end(); ++it) { (*it)->RegisterTests(); } } private: typedef ::std::vector TestCaseInfoContainer; TestCaseInfoContainer test_case_infos_; GTEST_DISALLOW_COPY_AND_ASSIGN_(ParameterizedTestCaseRegistry); }; } // namespace internal } // namespace testing #endif // GTEST_HAS_PARAM_TEST #endif // GTEST_INCLUDE_GTEST_INTERNAL_GTEST_PARAM_UTIL_H_ // This file was GENERATED by command: // pump.py gtest-param-util-generated.h.pump // DO NOT EDIT BY HAND!!! // Copyright 2008 Google Inc. // All Rights Reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: vladl@google.com (Vlad Losev) // Type and function utilities for implementing parameterized tests. // This file is generated by a SCRIPT. DO NOT EDIT BY HAND! // // Currently Google Test supports at most 50 arguments in Values, // and at most 10 arguments in Combine. Please contact // googletestframework@googlegroups.com if you need more. // Please note that the number of arguments to Combine is limited // by the maximum arity of the implementation of tr1::tuple which is // currently set at 10. #ifndef GTEST_INCLUDE_GTEST_INTERNAL_GTEST_PARAM_UTIL_GENERATED_H_ #define GTEST_INCLUDE_GTEST_INTERNAL_GTEST_PARAM_UTIL_GENERATED_H_ // scripts/fuse_gtest.py depends on gtest's own header being #included // *unconditionally*. Therefore these #includes cannot be moved // inside #if GTEST_HAS_PARAM_TEST. #if GTEST_HAS_PARAM_TEST namespace testing { // Forward declarations of ValuesIn(), which is implemented in // include/gtest/gtest-param-test.h. template internal::ParamGenerator< typename ::testing::internal::IteratorTraits::value_type> ValuesIn(ForwardIterator begin, ForwardIterator end); template internal::ParamGenerator ValuesIn(const T (&array)[N]); template internal::ParamGenerator ValuesIn( const Container& container); namespace internal { // Used in the Values() function to provide polymorphic capabilities. template class ValueArray1 { public: explicit ValueArray1(T1 v1) : v1_(v1) {} template operator ParamGenerator() const { return ValuesIn(&v1_, &v1_ + 1); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray1& other); const T1 v1_; }; template class ValueArray2 { public: ValueArray2(T1 v1, T2 v2) : v1_(v1), v2_(v2) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray2& other); const T1 v1_; const T2 v2_; }; template class ValueArray3 { public: ValueArray3(T1 v1, T2 v2, T3 v3) : v1_(v1), v2_(v2), v3_(v3) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray3& other); const T1 v1_; const T2 v2_; const T3 v3_; }; template class ValueArray4 { public: ValueArray4(T1 v1, T2 v2, T3 v3, T4 v4) : v1_(v1), v2_(v2), v3_(v3), v4_(v4) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray4& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; }; template class ValueArray5 { public: ValueArray5(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray5& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; }; template class ValueArray6 { public: ValueArray6(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray6& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; }; template class ValueArray7 { public: ValueArray7(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray7& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; }; template class ValueArray8 { public: ValueArray8(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray8& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; }; template class ValueArray9 { public: ValueArray9(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray9& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; }; template class ValueArray10 { public: ValueArray10(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray10& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; }; template class ValueArray11 { public: ValueArray11(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray11& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; }; template class ValueArray12 { public: ValueArray12(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray12& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; }; template class ValueArray13 { public: ValueArray13(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray13& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; }; template class ValueArray14 { public: ValueArray14(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray14& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; }; template class ValueArray15 { public: ValueArray15(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray15& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; }; template class ValueArray16 { public: ValueArray16(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray16& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; }; template class ValueArray17 { public: ValueArray17(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray17& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; }; template class ValueArray18 { public: ValueArray18(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray18& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; }; template class ValueArray19 { public: ValueArray19(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray19& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; }; template class ValueArray20 { public: ValueArray20(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray20& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; }; template class ValueArray21 { public: ValueArray21(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray21& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; }; template class ValueArray22 { public: ValueArray22(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray22& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; }; template class ValueArray23 { public: ValueArray23(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray23& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; }; template class ValueArray24 { public: ValueArray24(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray24& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; }; template class ValueArray25 { public: ValueArray25(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray25& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; }; template class ValueArray26 { public: ValueArray26(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray26& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; }; template class ValueArray27 { public: ValueArray27(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray27& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; }; template class ValueArray28 { public: ValueArray28(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray28& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; }; template class ValueArray29 { public: ValueArray29(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray29& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; }; template class ValueArray30 { public: ValueArray30(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray30& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; }; template class ValueArray31 { public: ValueArray31(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray31& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; }; template class ValueArray32 { public: ValueArray32(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray32& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; }; template class ValueArray33 { public: ValueArray33(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray33& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; }; template class ValueArray34 { public: ValueArray34(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray34& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; }; template class ValueArray35 { public: ValueArray35(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray35& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; }; template class ValueArray36 { public: ValueArray36(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray36& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; }; template class ValueArray37 { public: ValueArray37(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray37& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; }; template class ValueArray38 { public: ValueArray38(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37), v38_(v38) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_, v38_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray38& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; const T38 v38_; }; template class ValueArray39 { public: ValueArray39(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37), v38_(v38), v39_(v39) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_, v38_, v39_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray39& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; const T38 v38_; const T39 v39_; }; template class ValueArray40 { public: ValueArray40(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37), v38_(v38), v39_(v39), v40_(v40) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_, v38_, v39_, v40_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray40& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; const T38 v38_; const T39 v39_; const T40 v40_; }; template class ValueArray41 { public: ValueArray41(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37), v38_(v38), v39_(v39), v40_(v40), v41_(v41) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_, v38_, v39_, v40_, v41_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray41& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; const T38 v38_; const T39 v39_; const T40 v40_; const T41 v41_; }; template class ValueArray42 { public: ValueArray42(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37), v38_(v38), v39_(v39), v40_(v40), v41_(v41), v42_(v42) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_, v38_, v39_, v40_, v41_, v42_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray42& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; const T38 v38_; const T39 v39_; const T40 v40_; const T41 v41_; const T42 v42_; }; template class ValueArray43 { public: ValueArray43(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37), v38_(v38), v39_(v39), v40_(v40), v41_(v41), v42_(v42), v43_(v43) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_, v38_, v39_, v40_, v41_, v42_, v43_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray43& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; const T38 v38_; const T39 v39_; const T40 v40_; const T41 v41_; const T42 v42_; const T43 v43_; }; template class ValueArray44 { public: ValueArray44(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37), v38_(v38), v39_(v39), v40_(v40), v41_(v41), v42_(v42), v43_(v43), v44_(v44) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_, v38_, v39_, v40_, v41_, v42_, v43_, v44_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray44& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; const T38 v38_; const T39 v39_; const T40 v40_; const T41 v41_; const T42 v42_; const T43 v43_; const T44 v44_; }; template class ValueArray45 { public: ValueArray45(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44, T45 v45) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37), v38_(v38), v39_(v39), v40_(v40), v41_(v41), v42_(v42), v43_(v43), v44_(v44), v45_(v45) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_, v38_, v39_, v40_, v41_, v42_, v43_, v44_, v45_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray45& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; const T38 v38_; const T39 v39_; const T40 v40_; const T41 v41_; const T42 v42_; const T43 v43_; const T44 v44_; const T45 v45_; }; template class ValueArray46 { public: ValueArray46(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44, T45 v45, T46 v46) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37), v38_(v38), v39_(v39), v40_(v40), v41_(v41), v42_(v42), v43_(v43), v44_(v44), v45_(v45), v46_(v46) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_, v38_, v39_, v40_, v41_, v42_, v43_, v44_, v45_, v46_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray46& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; const T38 v38_; const T39 v39_; const T40 v40_; const T41 v41_; const T42 v42_; const T43 v43_; const T44 v44_; const T45 v45_; const T46 v46_; }; template class ValueArray47 { public: ValueArray47(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44, T45 v45, T46 v46, T47 v47) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37), v38_(v38), v39_(v39), v40_(v40), v41_(v41), v42_(v42), v43_(v43), v44_(v44), v45_(v45), v46_(v46), v47_(v47) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_, v38_, v39_, v40_, v41_, v42_, v43_, v44_, v45_, v46_, v47_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray47& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; const T38 v38_; const T39 v39_; const T40 v40_; const T41 v41_; const T42 v42_; const T43 v43_; const T44 v44_; const T45 v45_; const T46 v46_; const T47 v47_; }; template class ValueArray48 { public: ValueArray48(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44, T45 v45, T46 v46, T47 v47, T48 v48) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37), v38_(v38), v39_(v39), v40_(v40), v41_(v41), v42_(v42), v43_(v43), v44_(v44), v45_(v45), v46_(v46), v47_(v47), v48_(v48) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_, v38_, v39_, v40_, v41_, v42_, v43_, v44_, v45_, v46_, v47_, v48_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray48& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; const T38 v38_; const T39 v39_; const T40 v40_; const T41 v41_; const T42 v42_; const T43 v43_; const T44 v44_; const T45 v45_; const T46 v46_; const T47 v47_; const T48 v48_; }; template class ValueArray49 { public: ValueArray49(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44, T45 v45, T46 v46, T47 v47, T48 v48, T49 v49) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37), v38_(v38), v39_(v39), v40_(v40), v41_(v41), v42_(v42), v43_(v43), v44_(v44), v45_(v45), v46_(v46), v47_(v47), v48_(v48), v49_(v49) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_, v38_, v39_, v40_, v41_, v42_, v43_, v44_, v45_, v46_, v47_, v48_, v49_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray49& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; const T38 v38_; const T39 v39_; const T40 v40_; const T41 v41_; const T42 v42_; const T43 v43_; const T44 v44_; const T45 v45_; const T46 v46_; const T47 v47_; const T48 v48_; const T49 v49_; }; template class ValueArray50 { public: ValueArray50(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44, T45 v45, T46 v46, T47 v47, T48 v48, T49 v49, T50 v50) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12), v13_(v13), v14_(v14), v15_(v15), v16_(v16), v17_(v17), v18_(v18), v19_(v19), v20_(v20), v21_(v21), v22_(v22), v23_(v23), v24_(v24), v25_(v25), v26_(v26), v27_(v27), v28_(v28), v29_(v29), v30_(v30), v31_(v31), v32_(v32), v33_(v33), v34_(v34), v35_(v35), v36_(v36), v37_(v37), v38_(v38), v39_(v39), v40_(v40), v41_(v41), v42_(v42), v43_(v43), v44_(v44), v45_(v45), v46_(v46), v47_(v47), v48_(v48), v49_(v49), v50_(v50) {} template operator ParamGenerator() const { const T array[] = {v1_, v2_, v3_, v4_, v5_, v6_, v7_, v8_, v9_, v10_, v11_, v12_, v13_, v14_, v15_, v16_, v17_, v18_, v19_, v20_, v21_, v22_, v23_, v24_, v25_, v26_, v27_, v28_, v29_, v30_, v31_, v32_, v33_, v34_, v35_, v36_, v37_, v38_, v39_, v40_, v41_, v42_, v43_, v44_, v45_, v46_, v47_, v48_, v49_, v50_}; return ValuesIn(array); } private: // No implementation - assignment is unsupported. void operator=(const ValueArray50& other); const T1 v1_; const T2 v2_; const T3 v3_; const T4 v4_; const T5 v5_; const T6 v6_; const T7 v7_; const T8 v8_; const T9 v9_; const T10 v10_; const T11 v11_; const T12 v12_; const T13 v13_; const T14 v14_; const T15 v15_; const T16 v16_; const T17 v17_; const T18 v18_; const T19 v19_; const T20 v20_; const T21 v21_; const T22 v22_; const T23 v23_; const T24 v24_; const T25 v25_; const T26 v26_; const T27 v27_; const T28 v28_; const T29 v29_; const T30 v30_; const T31 v31_; const T32 v32_; const T33 v33_; const T34 v34_; const T35 v35_; const T36 v36_; const T37 v37_; const T38 v38_; const T39 v39_; const T40 v40_; const T41 v41_; const T42 v42_; const T43 v43_; const T44 v44_; const T45 v45_; const T46 v46_; const T47 v47_; const T48 v48_; const T49 v49_; const T50 v50_; }; # if GTEST_HAS_COMBINE // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // Generates values from the Cartesian product of values produced // by the argument generators. // template class CartesianProductGenerator2 : public ParamGeneratorInterface< ::std::tr1::tuple > { public: typedef ::std::tr1::tuple ParamType; CartesianProductGenerator2(const ParamGenerator& g1, const ParamGenerator& g2) : g1_(g1), g2_(g2) {} virtual ~CartesianProductGenerator2() {} virtual ParamIteratorInterface* Begin() const { return new Iterator(this, g1_, g1_.begin(), g2_, g2_.begin()); } virtual ParamIteratorInterface* End() const { return new Iterator(this, g1_, g1_.end(), g2_, g2_.end()); } private: class Iterator : public ParamIteratorInterface { public: Iterator(const ParamGeneratorInterface* base, const ParamGenerator& g1, const typename ParamGenerator::iterator& current1, const ParamGenerator& g2, const typename ParamGenerator::iterator& current2) : base_(base), begin1_(g1.begin()), end1_(g1.end()), current1_(current1), begin2_(g2.begin()), end2_(g2.end()), current2_(current2) { ComputeCurrentValue(); } virtual ~Iterator() {} virtual const ParamGeneratorInterface* BaseGenerator() const { return base_; } // Advance should not be called on beyond-of-range iterators // so no component iterators must be beyond end of range, either. virtual void Advance() { assert(!AtEnd()); ++current2_; if (current2_ == end2_) { current2_ = begin2_; ++current1_; } ComputeCurrentValue(); } virtual ParamIteratorInterface* Clone() const { return new Iterator(*this); } virtual const ParamType* Current() const { return ¤t_value_; } virtual bool Equals(const ParamIteratorInterface& other) const { // Having the same base generator guarantees that the other // iterator is of the same type and we can downcast. GTEST_CHECK_(BaseGenerator() == other.BaseGenerator()) << "The program attempted to compare iterators " << "from different generators." << std::endl; const Iterator* typed_other = CheckedDowncastToActualType(&other); // We must report iterators equal if they both point beyond their // respective ranges. That can happen in a variety of fashions, // so we have to consult AtEnd(). return (AtEnd() && typed_other->AtEnd()) || ( current1_ == typed_other->current1_ && current2_ == typed_other->current2_); } private: Iterator(const Iterator& other) : base_(other.base_), begin1_(other.begin1_), end1_(other.end1_), current1_(other.current1_), begin2_(other.begin2_), end2_(other.end2_), current2_(other.current2_) { ComputeCurrentValue(); } void ComputeCurrentValue() { if (!AtEnd()) current_value_ = ParamType(*current1_, *current2_); } bool AtEnd() const { // We must report iterator past the end of the range when either of the // component iterators has reached the end of its range. return current1_ == end1_ || current2_ == end2_; } // No implementation - assignment is unsupported. void operator=(const Iterator& other); const ParamGeneratorInterface* const base_; // begin[i]_ and end[i]_ define the i-th range that Iterator traverses. // current[i]_ is the actual traversing iterator. const typename ParamGenerator::iterator begin1_; const typename ParamGenerator::iterator end1_; typename ParamGenerator::iterator current1_; const typename ParamGenerator::iterator begin2_; const typename ParamGenerator::iterator end2_; typename ParamGenerator::iterator current2_; ParamType current_value_; }; // class CartesianProductGenerator2::Iterator // No implementation - assignment is unsupported. void operator=(const CartesianProductGenerator2& other); const ParamGenerator g1_; const ParamGenerator g2_; }; // class CartesianProductGenerator2 template class CartesianProductGenerator3 : public ParamGeneratorInterface< ::std::tr1::tuple > { public: typedef ::std::tr1::tuple ParamType; CartesianProductGenerator3(const ParamGenerator& g1, const ParamGenerator& g2, const ParamGenerator& g3) : g1_(g1), g2_(g2), g3_(g3) {} virtual ~CartesianProductGenerator3() {} virtual ParamIteratorInterface* Begin() const { return new Iterator(this, g1_, g1_.begin(), g2_, g2_.begin(), g3_, g3_.begin()); } virtual ParamIteratorInterface* End() const { return new Iterator(this, g1_, g1_.end(), g2_, g2_.end(), g3_, g3_.end()); } private: class Iterator : public ParamIteratorInterface { public: Iterator(const ParamGeneratorInterface* base, const ParamGenerator& g1, const typename ParamGenerator::iterator& current1, const ParamGenerator& g2, const typename ParamGenerator::iterator& current2, const ParamGenerator& g3, const typename ParamGenerator::iterator& current3) : base_(base), begin1_(g1.begin()), end1_(g1.end()), current1_(current1), begin2_(g2.begin()), end2_(g2.end()), current2_(current2), begin3_(g3.begin()), end3_(g3.end()), current3_(current3) { ComputeCurrentValue(); } virtual ~Iterator() {} virtual const ParamGeneratorInterface* BaseGenerator() const { return base_; } // Advance should not be called on beyond-of-range iterators // so no component iterators must be beyond end of range, either. virtual void Advance() { assert(!AtEnd()); ++current3_; if (current3_ == end3_) { current3_ = begin3_; ++current2_; } if (current2_ == end2_) { current2_ = begin2_; ++current1_; } ComputeCurrentValue(); } virtual ParamIteratorInterface* Clone() const { return new Iterator(*this); } virtual const ParamType* Current() const { return ¤t_value_; } virtual bool Equals(const ParamIteratorInterface& other) const { // Having the same base generator guarantees that the other // iterator is of the same type and we can downcast. GTEST_CHECK_(BaseGenerator() == other.BaseGenerator()) << "The program attempted to compare iterators " << "from different generators." << std::endl; const Iterator* typed_other = CheckedDowncastToActualType(&other); // We must report iterators equal if they both point beyond their // respective ranges. That can happen in a variety of fashions, // so we have to consult AtEnd(). return (AtEnd() && typed_other->AtEnd()) || ( current1_ == typed_other->current1_ && current2_ == typed_other->current2_ && current3_ == typed_other->current3_); } private: Iterator(const Iterator& other) : base_(other.base_), begin1_(other.begin1_), end1_(other.end1_), current1_(other.current1_), begin2_(other.begin2_), end2_(other.end2_), current2_(other.current2_), begin3_(other.begin3_), end3_(other.end3_), current3_(other.current3_) { ComputeCurrentValue(); } void ComputeCurrentValue() { if (!AtEnd()) current_value_ = ParamType(*current1_, *current2_, *current3_); } bool AtEnd() const { // We must report iterator past the end of the range when either of the // component iterators has reached the end of its range. return current1_ == end1_ || current2_ == end2_ || current3_ == end3_; } // No implementation - assignment is unsupported. void operator=(const Iterator& other); const ParamGeneratorInterface* const base_; // begin[i]_ and end[i]_ define the i-th range that Iterator traverses. // current[i]_ is the actual traversing iterator. const typename ParamGenerator::iterator begin1_; const typename ParamGenerator::iterator end1_; typename ParamGenerator::iterator current1_; const typename ParamGenerator::iterator begin2_; const typename ParamGenerator::iterator end2_; typename ParamGenerator::iterator current2_; const typename ParamGenerator::iterator begin3_; const typename ParamGenerator::iterator end3_; typename ParamGenerator::iterator current3_; ParamType current_value_; }; // class CartesianProductGenerator3::Iterator // No implementation - assignment is unsupported. void operator=(const CartesianProductGenerator3& other); const ParamGenerator g1_; const ParamGenerator g2_; const ParamGenerator g3_; }; // class CartesianProductGenerator3 template class CartesianProductGenerator4 : public ParamGeneratorInterface< ::std::tr1::tuple > { public: typedef ::std::tr1::tuple ParamType; CartesianProductGenerator4(const ParamGenerator& g1, const ParamGenerator& g2, const ParamGenerator& g3, const ParamGenerator& g4) : g1_(g1), g2_(g2), g3_(g3), g4_(g4) {} virtual ~CartesianProductGenerator4() {} virtual ParamIteratorInterface* Begin() const { return new Iterator(this, g1_, g1_.begin(), g2_, g2_.begin(), g3_, g3_.begin(), g4_, g4_.begin()); } virtual ParamIteratorInterface* End() const { return new Iterator(this, g1_, g1_.end(), g2_, g2_.end(), g3_, g3_.end(), g4_, g4_.end()); } private: class Iterator : public ParamIteratorInterface { public: Iterator(const ParamGeneratorInterface* base, const ParamGenerator& g1, const typename ParamGenerator::iterator& current1, const ParamGenerator& g2, const typename ParamGenerator::iterator& current2, const ParamGenerator& g3, const typename ParamGenerator::iterator& current3, const ParamGenerator& g4, const typename ParamGenerator::iterator& current4) : base_(base), begin1_(g1.begin()), end1_(g1.end()), current1_(current1), begin2_(g2.begin()), end2_(g2.end()), current2_(current2), begin3_(g3.begin()), end3_(g3.end()), current3_(current3), begin4_(g4.begin()), end4_(g4.end()), current4_(current4) { ComputeCurrentValue(); } virtual ~Iterator() {} virtual const ParamGeneratorInterface* BaseGenerator() const { return base_; } // Advance should not be called on beyond-of-range iterators // so no component iterators must be beyond end of range, either. virtual void Advance() { assert(!AtEnd()); ++current4_; if (current4_ == end4_) { current4_ = begin4_; ++current3_; } if (current3_ == end3_) { current3_ = begin3_; ++current2_; } if (current2_ == end2_) { current2_ = begin2_; ++current1_; } ComputeCurrentValue(); } virtual ParamIteratorInterface* Clone() const { return new Iterator(*this); } virtual const ParamType* Current() const { return ¤t_value_; } virtual bool Equals(const ParamIteratorInterface& other) const { // Having the same base generator guarantees that the other // iterator is of the same type and we can downcast. GTEST_CHECK_(BaseGenerator() == other.BaseGenerator()) << "The program attempted to compare iterators " << "from different generators." << std::endl; const Iterator* typed_other = CheckedDowncastToActualType(&other); // We must report iterators equal if they both point beyond their // respective ranges. That can happen in a variety of fashions, // so we have to consult AtEnd(). return (AtEnd() && typed_other->AtEnd()) || ( current1_ == typed_other->current1_ && current2_ == typed_other->current2_ && current3_ == typed_other->current3_ && current4_ == typed_other->current4_); } private: Iterator(const Iterator& other) : base_(other.base_), begin1_(other.begin1_), end1_(other.end1_), current1_(other.current1_), begin2_(other.begin2_), end2_(other.end2_), current2_(other.current2_), begin3_(other.begin3_), end3_(other.end3_), current3_(other.current3_), begin4_(other.begin4_), end4_(other.end4_), current4_(other.current4_) { ComputeCurrentValue(); } void ComputeCurrentValue() { if (!AtEnd()) current_value_ = ParamType(*current1_, *current2_, *current3_, *current4_); } bool AtEnd() const { // We must report iterator past the end of the range when either of the // component iterators has reached the end of its range. return current1_ == end1_ || current2_ == end2_ || current3_ == end3_ || current4_ == end4_; } // No implementation - assignment is unsupported. void operator=(const Iterator& other); const ParamGeneratorInterface* const base_; // begin[i]_ and end[i]_ define the i-th range that Iterator traverses. // current[i]_ is the actual traversing iterator. const typename ParamGenerator::iterator begin1_; const typename ParamGenerator::iterator end1_; typename ParamGenerator::iterator current1_; const typename ParamGenerator::iterator begin2_; const typename ParamGenerator::iterator end2_; typename ParamGenerator::iterator current2_; const typename ParamGenerator::iterator begin3_; const typename ParamGenerator::iterator end3_; typename ParamGenerator::iterator current3_; const typename ParamGenerator::iterator begin4_; const typename ParamGenerator::iterator end4_; typename ParamGenerator::iterator current4_; ParamType current_value_; }; // class CartesianProductGenerator4::Iterator // No implementation - assignment is unsupported. void operator=(const CartesianProductGenerator4& other); const ParamGenerator g1_; const ParamGenerator g2_; const ParamGenerator g3_; const ParamGenerator g4_; }; // class CartesianProductGenerator4 template class CartesianProductGenerator5 : public ParamGeneratorInterface< ::std::tr1::tuple > { public: typedef ::std::tr1::tuple ParamType; CartesianProductGenerator5(const ParamGenerator& g1, const ParamGenerator& g2, const ParamGenerator& g3, const ParamGenerator& g4, const ParamGenerator& g5) : g1_(g1), g2_(g2), g3_(g3), g4_(g4), g5_(g5) {} virtual ~CartesianProductGenerator5() {} virtual ParamIteratorInterface* Begin() const { return new Iterator(this, g1_, g1_.begin(), g2_, g2_.begin(), g3_, g3_.begin(), g4_, g4_.begin(), g5_, g5_.begin()); } virtual ParamIteratorInterface* End() const { return new Iterator(this, g1_, g1_.end(), g2_, g2_.end(), g3_, g3_.end(), g4_, g4_.end(), g5_, g5_.end()); } private: class Iterator : public ParamIteratorInterface { public: Iterator(const ParamGeneratorInterface* base, const ParamGenerator& g1, const typename ParamGenerator::iterator& current1, const ParamGenerator& g2, const typename ParamGenerator::iterator& current2, const ParamGenerator& g3, const typename ParamGenerator::iterator& current3, const ParamGenerator& g4, const typename ParamGenerator::iterator& current4, const ParamGenerator& g5, const typename ParamGenerator::iterator& current5) : base_(base), begin1_(g1.begin()), end1_(g1.end()), current1_(current1), begin2_(g2.begin()), end2_(g2.end()), current2_(current2), begin3_(g3.begin()), end3_(g3.end()), current3_(current3), begin4_(g4.begin()), end4_(g4.end()), current4_(current4), begin5_(g5.begin()), end5_(g5.end()), current5_(current5) { ComputeCurrentValue(); } virtual ~Iterator() {} virtual const ParamGeneratorInterface* BaseGenerator() const { return base_; } // Advance should not be called on beyond-of-range iterators // so no component iterators must be beyond end of range, either. virtual void Advance() { assert(!AtEnd()); ++current5_; if (current5_ == end5_) { current5_ = begin5_; ++current4_; } if (current4_ == end4_) { current4_ = begin4_; ++current3_; } if (current3_ == end3_) { current3_ = begin3_; ++current2_; } if (current2_ == end2_) { current2_ = begin2_; ++current1_; } ComputeCurrentValue(); } virtual ParamIteratorInterface* Clone() const { return new Iterator(*this); } virtual const ParamType* Current() const { return ¤t_value_; } virtual bool Equals(const ParamIteratorInterface& other) const { // Having the same base generator guarantees that the other // iterator is of the same type and we can downcast. GTEST_CHECK_(BaseGenerator() == other.BaseGenerator()) << "The program attempted to compare iterators " << "from different generators." << std::endl; const Iterator* typed_other = CheckedDowncastToActualType(&other); // We must report iterators equal if they both point beyond their // respective ranges. That can happen in a variety of fashions, // so we have to consult AtEnd(). return (AtEnd() && typed_other->AtEnd()) || ( current1_ == typed_other->current1_ && current2_ == typed_other->current2_ && current3_ == typed_other->current3_ && current4_ == typed_other->current4_ && current5_ == typed_other->current5_); } private: Iterator(const Iterator& other) : base_(other.base_), begin1_(other.begin1_), end1_(other.end1_), current1_(other.current1_), begin2_(other.begin2_), end2_(other.end2_), current2_(other.current2_), begin3_(other.begin3_), end3_(other.end3_), current3_(other.current3_), begin4_(other.begin4_), end4_(other.end4_), current4_(other.current4_), begin5_(other.begin5_), end5_(other.end5_), current5_(other.current5_) { ComputeCurrentValue(); } void ComputeCurrentValue() { if (!AtEnd()) current_value_ = ParamType(*current1_, *current2_, *current3_, *current4_, *current5_); } bool AtEnd() const { // We must report iterator past the end of the range when either of the // component iterators has reached the end of its range. return current1_ == end1_ || current2_ == end2_ || current3_ == end3_ || current4_ == end4_ || current5_ == end5_; } // No implementation - assignment is unsupported. void operator=(const Iterator& other); const ParamGeneratorInterface* const base_; // begin[i]_ and end[i]_ define the i-th range that Iterator traverses. // current[i]_ is the actual traversing iterator. const typename ParamGenerator::iterator begin1_; const typename ParamGenerator::iterator end1_; typename ParamGenerator::iterator current1_; const typename ParamGenerator::iterator begin2_; const typename ParamGenerator::iterator end2_; typename ParamGenerator::iterator current2_; const typename ParamGenerator::iterator begin3_; const typename ParamGenerator::iterator end3_; typename ParamGenerator::iterator current3_; const typename ParamGenerator::iterator begin4_; const typename ParamGenerator::iterator end4_; typename ParamGenerator::iterator current4_; const typename ParamGenerator::iterator begin5_; const typename ParamGenerator::iterator end5_; typename ParamGenerator::iterator current5_; ParamType current_value_; }; // class CartesianProductGenerator5::Iterator // No implementation - assignment is unsupported. void operator=(const CartesianProductGenerator5& other); const ParamGenerator g1_; const ParamGenerator g2_; const ParamGenerator g3_; const ParamGenerator g4_; const ParamGenerator g5_; }; // class CartesianProductGenerator5 template class CartesianProductGenerator6 : public ParamGeneratorInterface< ::std::tr1::tuple > { public: typedef ::std::tr1::tuple ParamType; CartesianProductGenerator6(const ParamGenerator& g1, const ParamGenerator& g2, const ParamGenerator& g3, const ParamGenerator& g4, const ParamGenerator& g5, const ParamGenerator& g6) : g1_(g1), g2_(g2), g3_(g3), g4_(g4), g5_(g5), g6_(g6) {} virtual ~CartesianProductGenerator6() {} virtual ParamIteratorInterface* Begin() const { return new Iterator(this, g1_, g1_.begin(), g2_, g2_.begin(), g3_, g3_.begin(), g4_, g4_.begin(), g5_, g5_.begin(), g6_, g6_.begin()); } virtual ParamIteratorInterface* End() const { return new Iterator(this, g1_, g1_.end(), g2_, g2_.end(), g3_, g3_.end(), g4_, g4_.end(), g5_, g5_.end(), g6_, g6_.end()); } private: class Iterator : public ParamIteratorInterface { public: Iterator(const ParamGeneratorInterface* base, const ParamGenerator& g1, const typename ParamGenerator::iterator& current1, const ParamGenerator& g2, const typename ParamGenerator::iterator& current2, const ParamGenerator& g3, const typename ParamGenerator::iterator& current3, const ParamGenerator& g4, const typename ParamGenerator::iterator& current4, const ParamGenerator& g5, const typename ParamGenerator::iterator& current5, const ParamGenerator& g6, const typename ParamGenerator::iterator& current6) : base_(base), begin1_(g1.begin()), end1_(g1.end()), current1_(current1), begin2_(g2.begin()), end2_(g2.end()), current2_(current2), begin3_(g3.begin()), end3_(g3.end()), current3_(current3), begin4_(g4.begin()), end4_(g4.end()), current4_(current4), begin5_(g5.begin()), end5_(g5.end()), current5_(current5), begin6_(g6.begin()), end6_(g6.end()), current6_(current6) { ComputeCurrentValue(); } virtual ~Iterator() {} virtual const ParamGeneratorInterface* BaseGenerator() const { return base_; } // Advance should not be called on beyond-of-range iterators // so no component iterators must be beyond end of range, either. virtual void Advance() { assert(!AtEnd()); ++current6_; if (current6_ == end6_) { current6_ = begin6_; ++current5_; } if (current5_ == end5_) { current5_ = begin5_; ++current4_; } if (current4_ == end4_) { current4_ = begin4_; ++current3_; } if (current3_ == end3_) { current3_ = begin3_; ++current2_; } if (current2_ == end2_) { current2_ = begin2_; ++current1_; } ComputeCurrentValue(); } virtual ParamIteratorInterface* Clone() const { return new Iterator(*this); } virtual const ParamType* Current() const { return ¤t_value_; } virtual bool Equals(const ParamIteratorInterface& other) const { // Having the same base generator guarantees that the other // iterator is of the same type and we can downcast. GTEST_CHECK_(BaseGenerator() == other.BaseGenerator()) << "The program attempted to compare iterators " << "from different generators." << std::endl; const Iterator* typed_other = CheckedDowncastToActualType(&other); // We must report iterators equal if they both point beyond their // respective ranges. That can happen in a variety of fashions, // so we have to consult AtEnd(). return (AtEnd() && typed_other->AtEnd()) || ( current1_ == typed_other->current1_ && current2_ == typed_other->current2_ && current3_ == typed_other->current3_ && current4_ == typed_other->current4_ && current5_ == typed_other->current5_ && current6_ == typed_other->current6_); } private: Iterator(const Iterator& other) : base_(other.base_), begin1_(other.begin1_), end1_(other.end1_), current1_(other.current1_), begin2_(other.begin2_), end2_(other.end2_), current2_(other.current2_), begin3_(other.begin3_), end3_(other.end3_), current3_(other.current3_), begin4_(other.begin4_), end4_(other.end4_), current4_(other.current4_), begin5_(other.begin5_), end5_(other.end5_), current5_(other.current5_), begin6_(other.begin6_), end6_(other.end6_), current6_(other.current6_) { ComputeCurrentValue(); } void ComputeCurrentValue() { if (!AtEnd()) current_value_ = ParamType(*current1_, *current2_, *current3_, *current4_, *current5_, *current6_); } bool AtEnd() const { // We must report iterator past the end of the range when either of the // component iterators has reached the end of its range. return current1_ == end1_ || current2_ == end2_ || current3_ == end3_ || current4_ == end4_ || current5_ == end5_ || current6_ == end6_; } // No implementation - assignment is unsupported. void operator=(const Iterator& other); const ParamGeneratorInterface* const base_; // begin[i]_ and end[i]_ define the i-th range that Iterator traverses. // current[i]_ is the actual traversing iterator. const typename ParamGenerator::iterator begin1_; const typename ParamGenerator::iterator end1_; typename ParamGenerator::iterator current1_; const typename ParamGenerator::iterator begin2_; const typename ParamGenerator::iterator end2_; typename ParamGenerator::iterator current2_; const typename ParamGenerator::iterator begin3_; const typename ParamGenerator::iterator end3_; typename ParamGenerator::iterator current3_; const typename ParamGenerator::iterator begin4_; const typename ParamGenerator::iterator end4_; typename ParamGenerator::iterator current4_; const typename ParamGenerator::iterator begin5_; const typename ParamGenerator::iterator end5_; typename ParamGenerator::iterator current5_; const typename ParamGenerator::iterator begin6_; const typename ParamGenerator::iterator end6_; typename ParamGenerator::iterator current6_; ParamType current_value_; }; // class CartesianProductGenerator6::Iterator // No implementation - assignment is unsupported. void operator=(const CartesianProductGenerator6& other); const ParamGenerator g1_; const ParamGenerator g2_; const ParamGenerator g3_; const ParamGenerator g4_; const ParamGenerator g5_; const ParamGenerator g6_; }; // class CartesianProductGenerator6 template class CartesianProductGenerator7 : public ParamGeneratorInterface< ::std::tr1::tuple > { public: typedef ::std::tr1::tuple ParamType; CartesianProductGenerator7(const ParamGenerator& g1, const ParamGenerator& g2, const ParamGenerator& g3, const ParamGenerator& g4, const ParamGenerator& g5, const ParamGenerator& g6, const ParamGenerator& g7) : g1_(g1), g2_(g2), g3_(g3), g4_(g4), g5_(g5), g6_(g6), g7_(g7) {} virtual ~CartesianProductGenerator7() {} virtual ParamIteratorInterface* Begin() const { return new Iterator(this, g1_, g1_.begin(), g2_, g2_.begin(), g3_, g3_.begin(), g4_, g4_.begin(), g5_, g5_.begin(), g6_, g6_.begin(), g7_, g7_.begin()); } virtual ParamIteratorInterface* End() const { return new Iterator(this, g1_, g1_.end(), g2_, g2_.end(), g3_, g3_.end(), g4_, g4_.end(), g5_, g5_.end(), g6_, g6_.end(), g7_, g7_.end()); } private: class Iterator : public ParamIteratorInterface { public: Iterator(const ParamGeneratorInterface* base, const ParamGenerator& g1, const typename ParamGenerator::iterator& current1, const ParamGenerator& g2, const typename ParamGenerator::iterator& current2, const ParamGenerator& g3, const typename ParamGenerator::iterator& current3, const ParamGenerator& g4, const typename ParamGenerator::iterator& current4, const ParamGenerator& g5, const typename ParamGenerator::iterator& current5, const ParamGenerator& g6, const typename ParamGenerator::iterator& current6, const ParamGenerator& g7, const typename ParamGenerator::iterator& current7) : base_(base), begin1_(g1.begin()), end1_(g1.end()), current1_(current1), begin2_(g2.begin()), end2_(g2.end()), current2_(current2), begin3_(g3.begin()), end3_(g3.end()), current3_(current3), begin4_(g4.begin()), end4_(g4.end()), current4_(current4), begin5_(g5.begin()), end5_(g5.end()), current5_(current5), begin6_(g6.begin()), end6_(g6.end()), current6_(current6), begin7_(g7.begin()), end7_(g7.end()), current7_(current7) { ComputeCurrentValue(); } virtual ~Iterator() {} virtual const ParamGeneratorInterface* BaseGenerator() const { return base_; } // Advance should not be called on beyond-of-range iterators // so no component iterators must be beyond end of range, either. virtual void Advance() { assert(!AtEnd()); ++current7_; if (current7_ == end7_) { current7_ = begin7_; ++current6_; } if (current6_ == end6_) { current6_ = begin6_; ++current5_; } if (current5_ == end5_) { current5_ = begin5_; ++current4_; } if (current4_ == end4_) { current4_ = begin4_; ++current3_; } if (current3_ == end3_) { current3_ = begin3_; ++current2_; } if (current2_ == end2_) { current2_ = begin2_; ++current1_; } ComputeCurrentValue(); } virtual ParamIteratorInterface* Clone() const { return new Iterator(*this); } virtual const ParamType* Current() const { return ¤t_value_; } virtual bool Equals(const ParamIteratorInterface& other) const { // Having the same base generator guarantees that the other // iterator is of the same type and we can downcast. GTEST_CHECK_(BaseGenerator() == other.BaseGenerator()) << "The program attempted to compare iterators " << "from different generators." << std::endl; const Iterator* typed_other = CheckedDowncastToActualType(&other); // We must report iterators equal if they both point beyond their // respective ranges. That can happen in a variety of fashions, // so we have to consult AtEnd(). return (AtEnd() && typed_other->AtEnd()) || ( current1_ == typed_other->current1_ && current2_ == typed_other->current2_ && current3_ == typed_other->current3_ && current4_ == typed_other->current4_ && current5_ == typed_other->current5_ && current6_ == typed_other->current6_ && current7_ == typed_other->current7_); } private: Iterator(const Iterator& other) : base_(other.base_), begin1_(other.begin1_), end1_(other.end1_), current1_(other.current1_), begin2_(other.begin2_), end2_(other.end2_), current2_(other.current2_), begin3_(other.begin3_), end3_(other.end3_), current3_(other.current3_), begin4_(other.begin4_), end4_(other.end4_), current4_(other.current4_), begin5_(other.begin5_), end5_(other.end5_), current5_(other.current5_), begin6_(other.begin6_), end6_(other.end6_), current6_(other.current6_), begin7_(other.begin7_), end7_(other.end7_), current7_(other.current7_) { ComputeCurrentValue(); } void ComputeCurrentValue() { if (!AtEnd()) current_value_ = ParamType(*current1_, *current2_, *current3_, *current4_, *current5_, *current6_, *current7_); } bool AtEnd() const { // We must report iterator past the end of the range when either of the // component iterators has reached the end of its range. return current1_ == end1_ || current2_ == end2_ || current3_ == end3_ || current4_ == end4_ || current5_ == end5_ || current6_ == end6_ || current7_ == end7_; } // No implementation - assignment is unsupported. void operator=(const Iterator& other); const ParamGeneratorInterface* const base_; // begin[i]_ and end[i]_ define the i-th range that Iterator traverses. // current[i]_ is the actual traversing iterator. const typename ParamGenerator::iterator begin1_; const typename ParamGenerator::iterator end1_; typename ParamGenerator::iterator current1_; const typename ParamGenerator::iterator begin2_; const typename ParamGenerator::iterator end2_; typename ParamGenerator::iterator current2_; const typename ParamGenerator::iterator begin3_; const typename ParamGenerator::iterator end3_; typename ParamGenerator::iterator current3_; const typename ParamGenerator::iterator begin4_; const typename ParamGenerator::iterator end4_; typename ParamGenerator::iterator current4_; const typename ParamGenerator::iterator begin5_; const typename ParamGenerator::iterator end5_; typename ParamGenerator::iterator current5_; const typename ParamGenerator::iterator begin6_; const typename ParamGenerator::iterator end6_; typename ParamGenerator::iterator current6_; const typename ParamGenerator::iterator begin7_; const typename ParamGenerator::iterator end7_; typename ParamGenerator::iterator current7_; ParamType current_value_; }; // class CartesianProductGenerator7::Iterator // No implementation - assignment is unsupported. void operator=(const CartesianProductGenerator7& other); const ParamGenerator g1_; const ParamGenerator g2_; const ParamGenerator g3_; const ParamGenerator g4_; const ParamGenerator g5_; const ParamGenerator g6_; const ParamGenerator g7_; }; // class CartesianProductGenerator7 template class CartesianProductGenerator8 : public ParamGeneratorInterface< ::std::tr1::tuple > { public: typedef ::std::tr1::tuple ParamType; CartesianProductGenerator8(const ParamGenerator& g1, const ParamGenerator& g2, const ParamGenerator& g3, const ParamGenerator& g4, const ParamGenerator& g5, const ParamGenerator& g6, const ParamGenerator& g7, const ParamGenerator& g8) : g1_(g1), g2_(g2), g3_(g3), g4_(g4), g5_(g5), g6_(g6), g7_(g7), g8_(g8) {} virtual ~CartesianProductGenerator8() {} virtual ParamIteratorInterface* Begin() const { return new Iterator(this, g1_, g1_.begin(), g2_, g2_.begin(), g3_, g3_.begin(), g4_, g4_.begin(), g5_, g5_.begin(), g6_, g6_.begin(), g7_, g7_.begin(), g8_, g8_.begin()); } virtual ParamIteratorInterface* End() const { return new Iterator(this, g1_, g1_.end(), g2_, g2_.end(), g3_, g3_.end(), g4_, g4_.end(), g5_, g5_.end(), g6_, g6_.end(), g7_, g7_.end(), g8_, g8_.end()); } private: class Iterator : public ParamIteratorInterface { public: Iterator(const ParamGeneratorInterface* base, const ParamGenerator& g1, const typename ParamGenerator::iterator& current1, const ParamGenerator& g2, const typename ParamGenerator::iterator& current2, const ParamGenerator& g3, const typename ParamGenerator::iterator& current3, const ParamGenerator& g4, const typename ParamGenerator::iterator& current4, const ParamGenerator& g5, const typename ParamGenerator::iterator& current5, const ParamGenerator& g6, const typename ParamGenerator::iterator& current6, const ParamGenerator& g7, const typename ParamGenerator::iterator& current7, const ParamGenerator& g8, const typename ParamGenerator::iterator& current8) : base_(base), begin1_(g1.begin()), end1_(g1.end()), current1_(current1), begin2_(g2.begin()), end2_(g2.end()), current2_(current2), begin3_(g3.begin()), end3_(g3.end()), current3_(current3), begin4_(g4.begin()), end4_(g4.end()), current4_(current4), begin5_(g5.begin()), end5_(g5.end()), current5_(current5), begin6_(g6.begin()), end6_(g6.end()), current6_(current6), begin7_(g7.begin()), end7_(g7.end()), current7_(current7), begin8_(g8.begin()), end8_(g8.end()), current8_(current8) { ComputeCurrentValue(); } virtual ~Iterator() {} virtual const ParamGeneratorInterface* BaseGenerator() const { return base_; } // Advance should not be called on beyond-of-range iterators // so no component iterators must be beyond end of range, either. virtual void Advance() { assert(!AtEnd()); ++current8_; if (current8_ == end8_) { current8_ = begin8_; ++current7_; } if (current7_ == end7_) { current7_ = begin7_; ++current6_; } if (current6_ == end6_) { current6_ = begin6_; ++current5_; } if (current5_ == end5_) { current5_ = begin5_; ++current4_; } if (current4_ == end4_) { current4_ = begin4_; ++current3_; } if (current3_ == end3_) { current3_ = begin3_; ++current2_; } if (current2_ == end2_) { current2_ = begin2_; ++current1_; } ComputeCurrentValue(); } virtual ParamIteratorInterface* Clone() const { return new Iterator(*this); } virtual const ParamType* Current() const { return ¤t_value_; } virtual bool Equals(const ParamIteratorInterface& other) const { // Having the same base generator guarantees that the other // iterator is of the same type and we can downcast. GTEST_CHECK_(BaseGenerator() == other.BaseGenerator()) << "The program attempted to compare iterators " << "from different generators." << std::endl; const Iterator* typed_other = CheckedDowncastToActualType(&other); // We must report iterators equal if they both point beyond their // respective ranges. That can happen in a variety of fashions, // so we have to consult AtEnd(). return (AtEnd() && typed_other->AtEnd()) || ( current1_ == typed_other->current1_ && current2_ == typed_other->current2_ && current3_ == typed_other->current3_ && current4_ == typed_other->current4_ && current5_ == typed_other->current5_ && current6_ == typed_other->current6_ && current7_ == typed_other->current7_ && current8_ == typed_other->current8_); } private: Iterator(const Iterator& other) : base_(other.base_), begin1_(other.begin1_), end1_(other.end1_), current1_(other.current1_), begin2_(other.begin2_), end2_(other.end2_), current2_(other.current2_), begin3_(other.begin3_), end3_(other.end3_), current3_(other.current3_), begin4_(other.begin4_), end4_(other.end4_), current4_(other.current4_), begin5_(other.begin5_), end5_(other.end5_), current5_(other.current5_), begin6_(other.begin6_), end6_(other.end6_), current6_(other.current6_), begin7_(other.begin7_), end7_(other.end7_), current7_(other.current7_), begin8_(other.begin8_), end8_(other.end8_), current8_(other.current8_) { ComputeCurrentValue(); } void ComputeCurrentValue() { if (!AtEnd()) current_value_ = ParamType(*current1_, *current2_, *current3_, *current4_, *current5_, *current6_, *current7_, *current8_); } bool AtEnd() const { // We must report iterator past the end of the range when either of the // component iterators has reached the end of its range. return current1_ == end1_ || current2_ == end2_ || current3_ == end3_ || current4_ == end4_ || current5_ == end5_ || current6_ == end6_ || current7_ == end7_ || current8_ == end8_; } // No implementation - assignment is unsupported. void operator=(const Iterator& other); const ParamGeneratorInterface* const base_; // begin[i]_ and end[i]_ define the i-th range that Iterator traverses. // current[i]_ is the actual traversing iterator. const typename ParamGenerator::iterator begin1_; const typename ParamGenerator::iterator end1_; typename ParamGenerator::iterator current1_; const typename ParamGenerator::iterator begin2_; const typename ParamGenerator::iterator end2_; typename ParamGenerator::iterator current2_; const typename ParamGenerator::iterator begin3_; const typename ParamGenerator::iterator end3_; typename ParamGenerator::iterator current3_; const typename ParamGenerator::iterator begin4_; const typename ParamGenerator::iterator end4_; typename ParamGenerator::iterator current4_; const typename ParamGenerator::iterator begin5_; const typename ParamGenerator::iterator end5_; typename ParamGenerator::iterator current5_; const typename ParamGenerator::iterator begin6_; const typename ParamGenerator::iterator end6_; typename ParamGenerator::iterator current6_; const typename ParamGenerator::iterator begin7_; const typename ParamGenerator::iterator end7_; typename ParamGenerator::iterator current7_; const typename ParamGenerator::iterator begin8_; const typename ParamGenerator::iterator end8_; typename ParamGenerator::iterator current8_; ParamType current_value_; }; // class CartesianProductGenerator8::Iterator // No implementation - assignment is unsupported. void operator=(const CartesianProductGenerator8& other); const ParamGenerator g1_; const ParamGenerator g2_; const ParamGenerator g3_; const ParamGenerator g4_; const ParamGenerator g5_; const ParamGenerator g6_; const ParamGenerator g7_; const ParamGenerator g8_; }; // class CartesianProductGenerator8 template class CartesianProductGenerator9 : public ParamGeneratorInterface< ::std::tr1::tuple > { public: typedef ::std::tr1::tuple ParamType; CartesianProductGenerator9(const ParamGenerator& g1, const ParamGenerator& g2, const ParamGenerator& g3, const ParamGenerator& g4, const ParamGenerator& g5, const ParamGenerator& g6, const ParamGenerator& g7, const ParamGenerator& g8, const ParamGenerator& g9) : g1_(g1), g2_(g2), g3_(g3), g4_(g4), g5_(g5), g6_(g6), g7_(g7), g8_(g8), g9_(g9) {} virtual ~CartesianProductGenerator9() {} virtual ParamIteratorInterface* Begin() const { return new Iterator(this, g1_, g1_.begin(), g2_, g2_.begin(), g3_, g3_.begin(), g4_, g4_.begin(), g5_, g5_.begin(), g6_, g6_.begin(), g7_, g7_.begin(), g8_, g8_.begin(), g9_, g9_.begin()); } virtual ParamIteratorInterface* End() const { return new Iterator(this, g1_, g1_.end(), g2_, g2_.end(), g3_, g3_.end(), g4_, g4_.end(), g5_, g5_.end(), g6_, g6_.end(), g7_, g7_.end(), g8_, g8_.end(), g9_, g9_.end()); } private: class Iterator : public ParamIteratorInterface { public: Iterator(const ParamGeneratorInterface* base, const ParamGenerator& g1, const typename ParamGenerator::iterator& current1, const ParamGenerator& g2, const typename ParamGenerator::iterator& current2, const ParamGenerator& g3, const typename ParamGenerator::iterator& current3, const ParamGenerator& g4, const typename ParamGenerator::iterator& current4, const ParamGenerator& g5, const typename ParamGenerator::iterator& current5, const ParamGenerator& g6, const typename ParamGenerator::iterator& current6, const ParamGenerator& g7, const typename ParamGenerator::iterator& current7, const ParamGenerator& g8, const typename ParamGenerator::iterator& current8, const ParamGenerator& g9, const typename ParamGenerator::iterator& current9) : base_(base), begin1_(g1.begin()), end1_(g1.end()), current1_(current1), begin2_(g2.begin()), end2_(g2.end()), current2_(current2), begin3_(g3.begin()), end3_(g3.end()), current3_(current3), begin4_(g4.begin()), end4_(g4.end()), current4_(current4), begin5_(g5.begin()), end5_(g5.end()), current5_(current5), begin6_(g6.begin()), end6_(g6.end()), current6_(current6), begin7_(g7.begin()), end7_(g7.end()), current7_(current7), begin8_(g8.begin()), end8_(g8.end()), current8_(current8), begin9_(g9.begin()), end9_(g9.end()), current9_(current9) { ComputeCurrentValue(); } virtual ~Iterator() {} virtual const ParamGeneratorInterface* BaseGenerator() const { return base_; } // Advance should not be called on beyond-of-range iterators // so no component iterators must be beyond end of range, either. virtual void Advance() { assert(!AtEnd()); ++current9_; if (current9_ == end9_) { current9_ = begin9_; ++current8_; } if (current8_ == end8_) { current8_ = begin8_; ++current7_; } if (current7_ == end7_) { current7_ = begin7_; ++current6_; } if (current6_ == end6_) { current6_ = begin6_; ++current5_; } if (current5_ == end5_) { current5_ = begin5_; ++current4_; } if (current4_ == end4_) { current4_ = begin4_; ++current3_; } if (current3_ == end3_) { current3_ = begin3_; ++current2_; } if (current2_ == end2_) { current2_ = begin2_; ++current1_; } ComputeCurrentValue(); } virtual ParamIteratorInterface* Clone() const { return new Iterator(*this); } virtual const ParamType* Current() const { return ¤t_value_; } virtual bool Equals(const ParamIteratorInterface& other) const { // Having the same base generator guarantees that the other // iterator is of the same type and we can downcast. GTEST_CHECK_(BaseGenerator() == other.BaseGenerator()) << "The program attempted to compare iterators " << "from different generators." << std::endl; const Iterator* typed_other = CheckedDowncastToActualType(&other); // We must report iterators equal if they both point beyond their // respective ranges. That can happen in a variety of fashions, // so we have to consult AtEnd(). return (AtEnd() && typed_other->AtEnd()) || ( current1_ == typed_other->current1_ && current2_ == typed_other->current2_ && current3_ == typed_other->current3_ && current4_ == typed_other->current4_ && current5_ == typed_other->current5_ && current6_ == typed_other->current6_ && current7_ == typed_other->current7_ && current8_ == typed_other->current8_ && current9_ == typed_other->current9_); } private: Iterator(const Iterator& other) : base_(other.base_), begin1_(other.begin1_), end1_(other.end1_), current1_(other.current1_), begin2_(other.begin2_), end2_(other.end2_), current2_(other.current2_), begin3_(other.begin3_), end3_(other.end3_), current3_(other.current3_), begin4_(other.begin4_), end4_(other.end4_), current4_(other.current4_), begin5_(other.begin5_), end5_(other.end5_), current5_(other.current5_), begin6_(other.begin6_), end6_(other.end6_), current6_(other.current6_), begin7_(other.begin7_), end7_(other.end7_), current7_(other.current7_), begin8_(other.begin8_), end8_(other.end8_), current8_(other.current8_), begin9_(other.begin9_), end9_(other.end9_), current9_(other.current9_) { ComputeCurrentValue(); } void ComputeCurrentValue() { if (!AtEnd()) current_value_ = ParamType(*current1_, *current2_, *current3_, *current4_, *current5_, *current6_, *current7_, *current8_, *current9_); } bool AtEnd() const { // We must report iterator past the end of the range when either of the // component iterators has reached the end of its range. return current1_ == end1_ || current2_ == end2_ || current3_ == end3_ || current4_ == end4_ || current5_ == end5_ || current6_ == end6_ || current7_ == end7_ || current8_ == end8_ || current9_ == end9_; } // No implementation - assignment is unsupported. void operator=(const Iterator& other); const ParamGeneratorInterface* const base_; // begin[i]_ and end[i]_ define the i-th range that Iterator traverses. // current[i]_ is the actual traversing iterator. const typename ParamGenerator::iterator begin1_; const typename ParamGenerator::iterator end1_; typename ParamGenerator::iterator current1_; const typename ParamGenerator::iterator begin2_; const typename ParamGenerator::iterator end2_; typename ParamGenerator::iterator current2_; const typename ParamGenerator::iterator begin3_; const typename ParamGenerator::iterator end3_; typename ParamGenerator::iterator current3_; const typename ParamGenerator::iterator begin4_; const typename ParamGenerator::iterator end4_; typename ParamGenerator::iterator current4_; const typename ParamGenerator::iterator begin5_; const typename ParamGenerator::iterator end5_; typename ParamGenerator::iterator current5_; const typename ParamGenerator::iterator begin6_; const typename ParamGenerator::iterator end6_; typename ParamGenerator::iterator current6_; const typename ParamGenerator::iterator begin7_; const typename ParamGenerator::iterator end7_; typename ParamGenerator::iterator current7_; const typename ParamGenerator::iterator begin8_; const typename ParamGenerator::iterator end8_; typename ParamGenerator::iterator current8_; const typename ParamGenerator::iterator begin9_; const typename ParamGenerator::iterator end9_; typename ParamGenerator::iterator current9_; ParamType current_value_; }; // class CartesianProductGenerator9::Iterator // No implementation - assignment is unsupported. void operator=(const CartesianProductGenerator9& other); const ParamGenerator g1_; const ParamGenerator g2_; const ParamGenerator g3_; const ParamGenerator g4_; const ParamGenerator g5_; const ParamGenerator g6_; const ParamGenerator g7_; const ParamGenerator g8_; const ParamGenerator g9_; }; // class CartesianProductGenerator9 template class CartesianProductGenerator10 : public ParamGeneratorInterface< ::std::tr1::tuple > { public: typedef ::std::tr1::tuple ParamType; CartesianProductGenerator10(const ParamGenerator& g1, const ParamGenerator& g2, const ParamGenerator& g3, const ParamGenerator& g4, const ParamGenerator& g5, const ParamGenerator& g6, const ParamGenerator& g7, const ParamGenerator& g8, const ParamGenerator& g9, const ParamGenerator& g10) : g1_(g1), g2_(g2), g3_(g3), g4_(g4), g5_(g5), g6_(g6), g7_(g7), g8_(g8), g9_(g9), g10_(g10) {} virtual ~CartesianProductGenerator10() {} virtual ParamIteratorInterface* Begin() const { return new Iterator(this, g1_, g1_.begin(), g2_, g2_.begin(), g3_, g3_.begin(), g4_, g4_.begin(), g5_, g5_.begin(), g6_, g6_.begin(), g7_, g7_.begin(), g8_, g8_.begin(), g9_, g9_.begin(), g10_, g10_.begin()); } virtual ParamIteratorInterface* End() const { return new Iterator(this, g1_, g1_.end(), g2_, g2_.end(), g3_, g3_.end(), g4_, g4_.end(), g5_, g5_.end(), g6_, g6_.end(), g7_, g7_.end(), g8_, g8_.end(), g9_, g9_.end(), g10_, g10_.end()); } private: class Iterator : public ParamIteratorInterface { public: Iterator(const ParamGeneratorInterface* base, const ParamGenerator& g1, const typename ParamGenerator::iterator& current1, const ParamGenerator& g2, const typename ParamGenerator::iterator& current2, const ParamGenerator& g3, const typename ParamGenerator::iterator& current3, const ParamGenerator& g4, const typename ParamGenerator::iterator& current4, const ParamGenerator& g5, const typename ParamGenerator::iterator& current5, const ParamGenerator& g6, const typename ParamGenerator::iterator& current6, const ParamGenerator& g7, const typename ParamGenerator::iterator& current7, const ParamGenerator& g8, const typename ParamGenerator::iterator& current8, const ParamGenerator& g9, const typename ParamGenerator::iterator& current9, const ParamGenerator& g10, const typename ParamGenerator::iterator& current10) : base_(base), begin1_(g1.begin()), end1_(g1.end()), current1_(current1), begin2_(g2.begin()), end2_(g2.end()), current2_(current2), begin3_(g3.begin()), end3_(g3.end()), current3_(current3), begin4_(g4.begin()), end4_(g4.end()), current4_(current4), begin5_(g5.begin()), end5_(g5.end()), current5_(current5), begin6_(g6.begin()), end6_(g6.end()), current6_(current6), begin7_(g7.begin()), end7_(g7.end()), current7_(current7), begin8_(g8.begin()), end8_(g8.end()), current8_(current8), begin9_(g9.begin()), end9_(g9.end()), current9_(current9), begin10_(g10.begin()), end10_(g10.end()), current10_(current10) { ComputeCurrentValue(); } virtual ~Iterator() {} virtual const ParamGeneratorInterface* BaseGenerator() const { return base_; } // Advance should not be called on beyond-of-range iterators // so no component iterators must be beyond end of range, either. virtual void Advance() { assert(!AtEnd()); ++current10_; if (current10_ == end10_) { current10_ = begin10_; ++current9_; } if (current9_ == end9_) { current9_ = begin9_; ++current8_; } if (current8_ == end8_) { current8_ = begin8_; ++current7_; } if (current7_ == end7_) { current7_ = begin7_; ++current6_; } if (current6_ == end6_) { current6_ = begin6_; ++current5_; } if (current5_ == end5_) { current5_ = begin5_; ++current4_; } if (current4_ == end4_) { current4_ = begin4_; ++current3_; } if (current3_ == end3_) { current3_ = begin3_; ++current2_; } if (current2_ == end2_) { current2_ = begin2_; ++current1_; } ComputeCurrentValue(); } virtual ParamIteratorInterface* Clone() const { return new Iterator(*this); } virtual const ParamType* Current() const { return ¤t_value_; } virtual bool Equals(const ParamIteratorInterface& other) const { // Having the same base generator guarantees that the other // iterator is of the same type and we can downcast. GTEST_CHECK_(BaseGenerator() == other.BaseGenerator()) << "The program attempted to compare iterators " << "from different generators." << std::endl; const Iterator* typed_other = CheckedDowncastToActualType(&other); // We must report iterators equal if they both point beyond their // respective ranges. That can happen in a variety of fashions, // so we have to consult AtEnd(). return (AtEnd() && typed_other->AtEnd()) || ( current1_ == typed_other->current1_ && current2_ == typed_other->current2_ && current3_ == typed_other->current3_ && current4_ == typed_other->current4_ && current5_ == typed_other->current5_ && current6_ == typed_other->current6_ && current7_ == typed_other->current7_ && current8_ == typed_other->current8_ && current9_ == typed_other->current9_ && current10_ == typed_other->current10_); } private: Iterator(const Iterator& other) : base_(other.base_), begin1_(other.begin1_), end1_(other.end1_), current1_(other.current1_), begin2_(other.begin2_), end2_(other.end2_), current2_(other.current2_), begin3_(other.begin3_), end3_(other.end3_), current3_(other.current3_), begin4_(other.begin4_), end4_(other.end4_), current4_(other.current4_), begin5_(other.begin5_), end5_(other.end5_), current5_(other.current5_), begin6_(other.begin6_), end6_(other.end6_), current6_(other.current6_), begin7_(other.begin7_), end7_(other.end7_), current7_(other.current7_), begin8_(other.begin8_), end8_(other.end8_), current8_(other.current8_), begin9_(other.begin9_), end9_(other.end9_), current9_(other.current9_), begin10_(other.begin10_), end10_(other.end10_), current10_(other.current10_) { ComputeCurrentValue(); } void ComputeCurrentValue() { if (!AtEnd()) current_value_ = ParamType(*current1_, *current2_, *current3_, *current4_, *current5_, *current6_, *current7_, *current8_, *current9_, *current10_); } bool AtEnd() const { // We must report iterator past the end of the range when either of the // component iterators has reached the end of its range. return current1_ == end1_ || current2_ == end2_ || current3_ == end3_ || current4_ == end4_ || current5_ == end5_ || current6_ == end6_ || current7_ == end7_ || current8_ == end8_ || current9_ == end9_ || current10_ == end10_; } // No implementation - assignment is unsupported. void operator=(const Iterator& other); const ParamGeneratorInterface* const base_; // begin[i]_ and end[i]_ define the i-th range that Iterator traverses. // current[i]_ is the actual traversing iterator. const typename ParamGenerator::iterator begin1_; const typename ParamGenerator::iterator end1_; typename ParamGenerator::iterator current1_; const typename ParamGenerator::iterator begin2_; const typename ParamGenerator::iterator end2_; typename ParamGenerator::iterator current2_; const typename ParamGenerator::iterator begin3_; const typename ParamGenerator::iterator end3_; typename ParamGenerator::iterator current3_; const typename ParamGenerator::iterator begin4_; const typename ParamGenerator::iterator end4_; typename ParamGenerator::iterator current4_; const typename ParamGenerator::iterator begin5_; const typename ParamGenerator::iterator end5_; typename ParamGenerator::iterator current5_; const typename ParamGenerator::iterator begin6_; const typename ParamGenerator::iterator end6_; typename ParamGenerator::iterator current6_; const typename ParamGenerator::iterator begin7_; const typename ParamGenerator::iterator end7_; typename ParamGenerator::iterator current7_; const typename ParamGenerator::iterator begin8_; const typename ParamGenerator::iterator end8_; typename ParamGenerator::iterator current8_; const typename ParamGenerator::iterator begin9_; const typename ParamGenerator::iterator end9_; typename ParamGenerator::iterator current9_; const typename ParamGenerator::iterator begin10_; const typename ParamGenerator::iterator end10_; typename ParamGenerator::iterator current10_; ParamType current_value_; }; // class CartesianProductGenerator10::Iterator // No implementation - assignment is unsupported. void operator=(const CartesianProductGenerator10& other); const ParamGenerator g1_; const ParamGenerator g2_; const ParamGenerator g3_; const ParamGenerator g4_; const ParamGenerator g5_; const ParamGenerator g6_; const ParamGenerator g7_; const ParamGenerator g8_; const ParamGenerator g9_; const ParamGenerator g10_; }; // class CartesianProductGenerator10 // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // Helper classes providing Combine() with polymorphic features. They allow // casting CartesianProductGeneratorN to ParamGenerator if T is // convertible to U. // template class CartesianProductHolder2 { public: CartesianProductHolder2(const Generator1& g1, const Generator2& g2) : g1_(g1), g2_(g2) {} template operator ParamGenerator< ::std::tr1::tuple >() const { return ParamGenerator< ::std::tr1::tuple >( new CartesianProductGenerator2( static_cast >(g1_), static_cast >(g2_))); } private: // No implementation - assignment is unsupported. void operator=(const CartesianProductHolder2& other); const Generator1 g1_; const Generator2 g2_; }; // class CartesianProductHolder2 template class CartesianProductHolder3 { public: CartesianProductHolder3(const Generator1& g1, const Generator2& g2, const Generator3& g3) : g1_(g1), g2_(g2), g3_(g3) {} template operator ParamGenerator< ::std::tr1::tuple >() const { return ParamGenerator< ::std::tr1::tuple >( new CartesianProductGenerator3( static_cast >(g1_), static_cast >(g2_), static_cast >(g3_))); } private: // No implementation - assignment is unsupported. void operator=(const CartesianProductHolder3& other); const Generator1 g1_; const Generator2 g2_; const Generator3 g3_; }; // class CartesianProductHolder3 template class CartesianProductHolder4 { public: CartesianProductHolder4(const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4) : g1_(g1), g2_(g2), g3_(g3), g4_(g4) {} template operator ParamGenerator< ::std::tr1::tuple >() const { return ParamGenerator< ::std::tr1::tuple >( new CartesianProductGenerator4( static_cast >(g1_), static_cast >(g2_), static_cast >(g3_), static_cast >(g4_))); } private: // No implementation - assignment is unsupported. void operator=(const CartesianProductHolder4& other); const Generator1 g1_; const Generator2 g2_; const Generator3 g3_; const Generator4 g4_; }; // class CartesianProductHolder4 template class CartesianProductHolder5 { public: CartesianProductHolder5(const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4, const Generator5& g5) : g1_(g1), g2_(g2), g3_(g3), g4_(g4), g5_(g5) {} template operator ParamGenerator< ::std::tr1::tuple >() const { return ParamGenerator< ::std::tr1::tuple >( new CartesianProductGenerator5( static_cast >(g1_), static_cast >(g2_), static_cast >(g3_), static_cast >(g4_), static_cast >(g5_))); } private: // No implementation - assignment is unsupported. void operator=(const CartesianProductHolder5& other); const Generator1 g1_; const Generator2 g2_; const Generator3 g3_; const Generator4 g4_; const Generator5 g5_; }; // class CartesianProductHolder5 template class CartesianProductHolder6 { public: CartesianProductHolder6(const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4, const Generator5& g5, const Generator6& g6) : g1_(g1), g2_(g2), g3_(g3), g4_(g4), g5_(g5), g6_(g6) {} template operator ParamGenerator< ::std::tr1::tuple >() const { return ParamGenerator< ::std::tr1::tuple >( new CartesianProductGenerator6( static_cast >(g1_), static_cast >(g2_), static_cast >(g3_), static_cast >(g4_), static_cast >(g5_), static_cast >(g6_))); } private: // No implementation - assignment is unsupported. void operator=(const CartesianProductHolder6& other); const Generator1 g1_; const Generator2 g2_; const Generator3 g3_; const Generator4 g4_; const Generator5 g5_; const Generator6 g6_; }; // class CartesianProductHolder6 template class CartesianProductHolder7 { public: CartesianProductHolder7(const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4, const Generator5& g5, const Generator6& g6, const Generator7& g7) : g1_(g1), g2_(g2), g3_(g3), g4_(g4), g5_(g5), g6_(g6), g7_(g7) {} template operator ParamGenerator< ::std::tr1::tuple >() const { return ParamGenerator< ::std::tr1::tuple >( new CartesianProductGenerator7( static_cast >(g1_), static_cast >(g2_), static_cast >(g3_), static_cast >(g4_), static_cast >(g5_), static_cast >(g6_), static_cast >(g7_))); } private: // No implementation - assignment is unsupported. void operator=(const CartesianProductHolder7& other); const Generator1 g1_; const Generator2 g2_; const Generator3 g3_; const Generator4 g4_; const Generator5 g5_; const Generator6 g6_; const Generator7 g7_; }; // class CartesianProductHolder7 template class CartesianProductHolder8 { public: CartesianProductHolder8(const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4, const Generator5& g5, const Generator6& g6, const Generator7& g7, const Generator8& g8) : g1_(g1), g2_(g2), g3_(g3), g4_(g4), g5_(g5), g6_(g6), g7_(g7), g8_(g8) {} template operator ParamGenerator< ::std::tr1::tuple >() const { return ParamGenerator< ::std::tr1::tuple >( new CartesianProductGenerator8( static_cast >(g1_), static_cast >(g2_), static_cast >(g3_), static_cast >(g4_), static_cast >(g5_), static_cast >(g6_), static_cast >(g7_), static_cast >(g8_))); } private: // No implementation - assignment is unsupported. void operator=(const CartesianProductHolder8& other); const Generator1 g1_; const Generator2 g2_; const Generator3 g3_; const Generator4 g4_; const Generator5 g5_; const Generator6 g6_; const Generator7 g7_; const Generator8 g8_; }; // class CartesianProductHolder8 template class CartesianProductHolder9 { public: CartesianProductHolder9(const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4, const Generator5& g5, const Generator6& g6, const Generator7& g7, const Generator8& g8, const Generator9& g9) : g1_(g1), g2_(g2), g3_(g3), g4_(g4), g5_(g5), g6_(g6), g7_(g7), g8_(g8), g9_(g9) {} template operator ParamGenerator< ::std::tr1::tuple >() const { return ParamGenerator< ::std::tr1::tuple >( new CartesianProductGenerator9( static_cast >(g1_), static_cast >(g2_), static_cast >(g3_), static_cast >(g4_), static_cast >(g5_), static_cast >(g6_), static_cast >(g7_), static_cast >(g8_), static_cast >(g9_))); } private: // No implementation - assignment is unsupported. void operator=(const CartesianProductHolder9& other); const Generator1 g1_; const Generator2 g2_; const Generator3 g3_; const Generator4 g4_; const Generator5 g5_; const Generator6 g6_; const Generator7 g7_; const Generator8 g8_; const Generator9 g9_; }; // class CartesianProductHolder9 template class CartesianProductHolder10 { public: CartesianProductHolder10(const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4, const Generator5& g5, const Generator6& g6, const Generator7& g7, const Generator8& g8, const Generator9& g9, const Generator10& g10) : g1_(g1), g2_(g2), g3_(g3), g4_(g4), g5_(g5), g6_(g6), g7_(g7), g8_(g8), g9_(g9), g10_(g10) {} template operator ParamGenerator< ::std::tr1::tuple >() const { return ParamGenerator< ::std::tr1::tuple >( new CartesianProductGenerator10( static_cast >(g1_), static_cast >(g2_), static_cast >(g3_), static_cast >(g4_), static_cast >(g5_), static_cast >(g6_), static_cast >(g7_), static_cast >(g8_), static_cast >(g9_), static_cast >(g10_))); } private: // No implementation - assignment is unsupported. void operator=(const CartesianProductHolder10& other); const Generator1 g1_; const Generator2 g2_; const Generator3 g3_; const Generator4 g4_; const Generator5 g5_; const Generator6 g6_; const Generator7 g7_; const Generator8 g8_; const Generator9 g9_; const Generator10 g10_; }; // class CartesianProductHolder10 # endif // GTEST_HAS_COMBINE } // namespace internal } // namespace testing #endif // GTEST_HAS_PARAM_TEST #endif // GTEST_INCLUDE_GTEST_INTERNAL_GTEST_PARAM_UTIL_GENERATED_H_ #if GTEST_HAS_PARAM_TEST namespace testing { // Functions producing parameter generators. // // Google Test uses these generators to produce parameters for value- // parameterized tests. When a parameterized test case is instantiated // with a particular generator, Google Test creates and runs tests // for each element in the sequence produced by the generator. // // In the following sample, tests from test case FooTest are instantiated // each three times with parameter values 3, 5, and 8: // // class FooTest : public TestWithParam { ... }; // // TEST_P(FooTest, TestThis) { // } // TEST_P(FooTest, TestThat) { // } // INSTANTIATE_TEST_CASE_P(TestSequence, FooTest, Values(3, 5, 8)); // // Range() returns generators providing sequences of values in a range. // // Synopsis: // Range(start, end) // - returns a generator producing a sequence of values {start, start+1, // start+2, ..., }. // Range(start, end, step) // - returns a generator producing a sequence of values {start, start+step, // start+step+step, ..., }. // Notes: // * The generated sequences never include end. For example, Range(1, 5) // returns a generator producing a sequence {1, 2, 3, 4}. Range(1, 9, 2) // returns a generator producing {1, 3, 5, 7}. // * start and end must have the same type. That type may be any integral or // floating-point type or a user defined type satisfying these conditions: // * It must be assignable (have operator=() defined). // * It must have operator+() (operator+(int-compatible type) for // two-operand version). // * It must have operator<() defined. // Elements in the resulting sequences will also have that type. // * Condition start < end must be satisfied in order for resulting sequences // to contain any elements. // template internal::ParamGenerator Range(T start, T end, IncrementT step) { return internal::ParamGenerator( new internal::RangeGenerator(start, end, step)); } template internal::ParamGenerator Range(T start, T end) { return Range(start, end, 1); } // ValuesIn() function allows generation of tests with parameters coming from // a container. // // Synopsis: // ValuesIn(const T (&array)[N]) // - returns a generator producing sequences with elements from // a C-style array. // ValuesIn(const Container& container) // - returns a generator producing sequences with elements from // an STL-style container. // ValuesIn(Iterator begin, Iterator end) // - returns a generator producing sequences with elements from // a range [begin, end) defined by a pair of STL-style iterators. These // iterators can also be plain C pointers. // // Please note that ValuesIn copies the values from the containers // passed in and keeps them to generate tests in RUN_ALL_TESTS(). // // Examples: // // This instantiates tests from test case StringTest // each with C-string values of "foo", "bar", and "baz": // // const char* strings[] = {"foo", "bar", "baz"}; // INSTANTIATE_TEST_CASE_P(StringSequence, SrtingTest, ValuesIn(strings)); // // This instantiates tests from test case StlStringTest // each with STL strings with values "a" and "b": // // ::std::vector< ::std::string> GetParameterStrings() { // ::std::vector< ::std::string> v; // v.push_back("a"); // v.push_back("b"); // return v; // } // // INSTANTIATE_TEST_CASE_P(CharSequence, // StlStringTest, // ValuesIn(GetParameterStrings())); // // // This will also instantiate tests from CharTest // each with parameter values 'a' and 'b': // // ::std::list GetParameterChars() { // ::std::list list; // list.push_back('a'); // list.push_back('b'); // return list; // } // ::std::list l = GetParameterChars(); // INSTANTIATE_TEST_CASE_P(CharSequence2, // CharTest, // ValuesIn(l.begin(), l.end())); // template internal::ParamGenerator< typename ::testing::internal::IteratorTraits::value_type> ValuesIn(ForwardIterator begin, ForwardIterator end) { typedef typename ::testing::internal::IteratorTraits ::value_type ParamType; return internal::ParamGenerator( new internal::ValuesInIteratorRangeGenerator(begin, end)); } template internal::ParamGenerator ValuesIn(const T (&array)[N]) { return ValuesIn(array, array + N); } template internal::ParamGenerator ValuesIn( const Container& container) { return ValuesIn(container.begin(), container.end()); } // Values() allows generating tests from explicitly specified list of // parameters. // // Synopsis: // Values(T v1, T v2, ..., T vN) // - returns a generator producing sequences with elements v1, v2, ..., vN. // // For example, this instantiates tests from test case BarTest each // with values "one", "two", and "three": // // INSTANTIATE_TEST_CASE_P(NumSequence, BarTest, Values("one", "two", "three")); // // This instantiates tests from test case BazTest each with values 1, 2, 3.5. // The exact type of values will depend on the type of parameter in BazTest. // // INSTANTIATE_TEST_CASE_P(FloatingNumbers, BazTest, Values(1, 2, 3.5)); // // Currently, Values() supports from 1 to 50 parameters. // template internal::ValueArray1 Values(T1 v1) { return internal::ValueArray1(v1); } template internal::ValueArray2 Values(T1 v1, T2 v2) { return internal::ValueArray2(v1, v2); } template internal::ValueArray3 Values(T1 v1, T2 v2, T3 v3) { return internal::ValueArray3(v1, v2, v3); } template internal::ValueArray4 Values(T1 v1, T2 v2, T3 v3, T4 v4) { return internal::ValueArray4(v1, v2, v3, v4); } template internal::ValueArray5 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5) { return internal::ValueArray5(v1, v2, v3, v4, v5); } template internal::ValueArray6 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6) { return internal::ValueArray6(v1, v2, v3, v4, v5, v6); } template internal::ValueArray7 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7) { return internal::ValueArray7(v1, v2, v3, v4, v5, v6, v7); } template internal::ValueArray8 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8) { return internal::ValueArray8(v1, v2, v3, v4, v5, v6, v7, v8); } template internal::ValueArray9 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9) { return internal::ValueArray9(v1, v2, v3, v4, v5, v6, v7, v8, v9); } template internal::ValueArray10 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10) { return internal::ValueArray10(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10); } template internal::ValueArray11 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11) { return internal::ValueArray11(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11); } template internal::ValueArray12 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12) { return internal::ValueArray12(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12); } template internal::ValueArray13 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13) { return internal::ValueArray13(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13); } template internal::ValueArray14 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14) { return internal::ValueArray14(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14); } template internal::ValueArray15 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15) { return internal::ValueArray15(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15); } template internal::ValueArray16 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16) { return internal::ValueArray16(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16); } template internal::ValueArray17 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17) { return internal::ValueArray17(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17); } template internal::ValueArray18 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18) { return internal::ValueArray18(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18); } template internal::ValueArray19 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19) { return internal::ValueArray19(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19); } template internal::ValueArray20 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20) { return internal::ValueArray20(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20); } template internal::ValueArray21 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21) { return internal::ValueArray21(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21); } template internal::ValueArray22 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22) { return internal::ValueArray22(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22); } template internal::ValueArray23 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23) { return internal::ValueArray23(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23); } template internal::ValueArray24 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24) { return internal::ValueArray24(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24); } template internal::ValueArray25 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25) { return internal::ValueArray25(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25); } template internal::ValueArray26 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26) { return internal::ValueArray26(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26); } template internal::ValueArray27 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27) { return internal::ValueArray27(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27); } template internal::ValueArray28 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28) { return internal::ValueArray28(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28); } template internal::ValueArray29 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29) { return internal::ValueArray29(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29); } template internal::ValueArray30 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30) { return internal::ValueArray30(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30); } template internal::ValueArray31 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31) { return internal::ValueArray31(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31); } template internal::ValueArray32 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32) { return internal::ValueArray32(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32); } template internal::ValueArray33 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33) { return internal::ValueArray33(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33); } template internal::ValueArray34 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34) { return internal::ValueArray34(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34); } template internal::ValueArray35 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35) { return internal::ValueArray35(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35); } template internal::ValueArray36 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36) { return internal::ValueArray36(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36); } template internal::ValueArray37 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37) { return internal::ValueArray37(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37); } template internal::ValueArray38 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38) { return internal::ValueArray38(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38); } template internal::ValueArray39 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39) { return internal::ValueArray39(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39); } template internal::ValueArray40 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40) { return internal::ValueArray40(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40); } template internal::ValueArray41 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41) { return internal::ValueArray41(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41); } template internal::ValueArray42 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42) { return internal::ValueArray42(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42); } template internal::ValueArray43 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43) { return internal::ValueArray43(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43); } template internal::ValueArray44 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44) { return internal::ValueArray44(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44); } template internal::ValueArray45 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44, T45 v45) { return internal::ValueArray45(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45); } template internal::ValueArray46 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44, T45 v45, T46 v46) { return internal::ValueArray46(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46); } template internal::ValueArray47 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44, T45 v45, T46 v46, T47 v47) { return internal::ValueArray47(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47); } template internal::ValueArray48 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44, T45 v45, T46 v46, T47 v47, T48 v48) { return internal::ValueArray48(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48); } template internal::ValueArray49 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44, T45 v45, T46 v46, T47 v47, T48 v48, T49 v49) { return internal::ValueArray49(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49); } template internal::ValueArray50 Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10, T11 v11, T12 v12, T13 v13, T14 v14, T15 v15, T16 v16, T17 v17, T18 v18, T19 v19, T20 v20, T21 v21, T22 v22, T23 v23, T24 v24, T25 v25, T26 v26, T27 v27, T28 v28, T29 v29, T30 v30, T31 v31, T32 v32, T33 v33, T34 v34, T35 v35, T36 v36, T37 v37, T38 v38, T39 v39, T40 v40, T41 v41, T42 v42, T43 v43, T44 v44, T45 v45, T46 v46, T47 v47, T48 v48, T49 v49, T50 v50) { return internal::ValueArray50(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50); } // Bool() allows generating tests with parameters in a set of (false, true). // // Synopsis: // Bool() // - returns a generator producing sequences with elements {false, true}. // // It is useful when testing code that depends on Boolean flags. Combinations // of multiple flags can be tested when several Bool()'s are combined using // Combine() function. // // In the following example all tests in the test case FlagDependentTest // will be instantiated twice with parameters false and true. // // class FlagDependentTest : public testing::TestWithParam { // virtual void SetUp() { // external_flag = GetParam(); // } // } // INSTANTIATE_TEST_CASE_P(BoolSequence, FlagDependentTest, Bool()); // inline internal::ParamGenerator Bool() { return Values(false, true); } # if GTEST_HAS_COMBINE // Combine() allows the user to combine two or more sequences to produce // values of a Cartesian product of those sequences' elements. // // Synopsis: // Combine(gen1, gen2, ..., genN) // - returns a generator producing sequences with elements coming from // the Cartesian product of elements from the sequences generated by // gen1, gen2, ..., genN. The sequence elements will have a type of // tuple where T1, T2, ..., TN are the types // of elements from sequences produces by gen1, gen2, ..., genN. // // Combine can have up to 10 arguments. This number is currently limited // by the maximum number of elements in the tuple implementation used by Google // Test. // // Example: // // This will instantiate tests in test case AnimalTest each one with // the parameter values tuple("cat", BLACK), tuple("cat", WHITE), // tuple("dog", BLACK), and tuple("dog", WHITE): // // enum Color { BLACK, GRAY, WHITE }; // class AnimalTest // : public testing::TestWithParam > {...}; // // TEST_P(AnimalTest, AnimalLooksNice) {...} // // INSTANTIATE_TEST_CASE_P(AnimalVariations, AnimalTest, // Combine(Values("cat", "dog"), // Values(BLACK, WHITE))); // // This will instantiate tests in FlagDependentTest with all variations of two // Boolean flags: // // class FlagDependentTest // : public testing::TestWithParam > { // virtual void SetUp() { // // Assigns external_flag_1 and external_flag_2 values from the tuple. // tie(external_flag_1, external_flag_2) = GetParam(); // } // }; // // TEST_P(FlagDependentTest, TestFeature1) { // // Test your code using external_flag_1 and external_flag_2 here. // } // INSTANTIATE_TEST_CASE_P(TwoBoolSequence, FlagDependentTest, // Combine(Bool(), Bool())); // template internal::CartesianProductHolder2 Combine( const Generator1& g1, const Generator2& g2) { return internal::CartesianProductHolder2( g1, g2); } template internal::CartesianProductHolder3 Combine( const Generator1& g1, const Generator2& g2, const Generator3& g3) { return internal::CartesianProductHolder3( g1, g2, g3); } template internal::CartesianProductHolder4 Combine( const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4) { return internal::CartesianProductHolder4( g1, g2, g3, g4); } template internal::CartesianProductHolder5 Combine( const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4, const Generator5& g5) { return internal::CartesianProductHolder5( g1, g2, g3, g4, g5); } template internal::CartesianProductHolder6 Combine( const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4, const Generator5& g5, const Generator6& g6) { return internal::CartesianProductHolder6( g1, g2, g3, g4, g5, g6); } template internal::CartesianProductHolder7 Combine( const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4, const Generator5& g5, const Generator6& g6, const Generator7& g7) { return internal::CartesianProductHolder7( g1, g2, g3, g4, g5, g6, g7); } template internal::CartesianProductHolder8 Combine( const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4, const Generator5& g5, const Generator6& g6, const Generator7& g7, const Generator8& g8) { return internal::CartesianProductHolder8( g1, g2, g3, g4, g5, g6, g7, g8); } template internal::CartesianProductHolder9 Combine( const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4, const Generator5& g5, const Generator6& g6, const Generator7& g7, const Generator8& g8, const Generator9& g9) { return internal::CartesianProductHolder9( g1, g2, g3, g4, g5, g6, g7, g8, g9); } template internal::CartesianProductHolder10 Combine( const Generator1& g1, const Generator2& g2, const Generator3& g3, const Generator4& g4, const Generator5& g5, const Generator6& g6, const Generator7& g7, const Generator8& g8, const Generator9& g9, const Generator10& g10) { return internal::CartesianProductHolder10( g1, g2, g3, g4, g5, g6, g7, g8, g9, g10); } # endif // GTEST_HAS_COMBINE # define TEST_P(test_case_name, test_name) \ class GTEST_TEST_CLASS_NAME_(test_case_name, test_name) \ : public test_case_name { \ public: \ GTEST_TEST_CLASS_NAME_(test_case_name, test_name)() {} \ virtual void TestBody(); \ private: \ static int AddToRegistry() { \ ::testing::UnitTest::GetInstance()->parameterized_test_registry(). \ GetTestCasePatternHolder(\ #test_case_name, __FILE__, __LINE__)->AddTestPattern(\ #test_case_name, \ #test_name, \ new ::testing::internal::TestMetaFactory< \ GTEST_TEST_CLASS_NAME_(test_case_name, test_name)>()); \ return 0; \ } \ static int gtest_registering_dummy_; \ GTEST_DISALLOW_COPY_AND_ASSIGN_(\ GTEST_TEST_CLASS_NAME_(test_case_name, test_name)); \ }; \ int GTEST_TEST_CLASS_NAME_(test_case_name, \ test_name)::gtest_registering_dummy_ = \ GTEST_TEST_CLASS_NAME_(test_case_name, test_name)::AddToRegistry(); \ void GTEST_TEST_CLASS_NAME_(test_case_name, test_name)::TestBody() # define INSTANTIATE_TEST_CASE_P(prefix, test_case_name, generator) \ ::testing::internal::ParamGenerator \ gtest_##prefix##test_case_name##_EvalGenerator_() { return generator; } \ int gtest_##prefix##test_case_name##_dummy_ = \ ::testing::UnitTest::GetInstance()->parameterized_test_registry(). \ GetTestCasePatternHolder(\ #test_case_name, __FILE__, __LINE__)->AddTestCaseInstantiation(\ #prefix, \ >est_##prefix##test_case_name##_EvalGenerator_, \ __FILE__, __LINE__) } // namespace testing #endif // GTEST_HAS_PARAM_TEST #endif // GTEST_INCLUDE_GTEST_GTEST_PARAM_TEST_H_ // Copyright 2006, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan) // // Google C++ Testing Framework definitions useful in production code. #ifndef GTEST_INCLUDE_GTEST_GTEST_PROD_H_ #define GTEST_INCLUDE_GTEST_GTEST_PROD_H_ // When you need to test the private or protected members of a class, // use the FRIEND_TEST macro to declare your tests as friends of the // class. For example: // // class MyClass { // private: // void MyMethod(); // FRIEND_TEST(MyClassTest, MyMethod); // }; // // class MyClassTest : public testing::Test { // // ... // }; // // TEST_F(MyClassTest, MyMethod) { // // Can call MyClass::MyMethod() here. // } #define FRIEND_TEST(test_case_name, test_name)\ friend class test_case_name##_##test_name##_Test #endif // GTEST_INCLUDE_GTEST_GTEST_PROD_H_ // Copyright 2008, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: mheule@google.com (Markus Heule) // #ifndef GTEST_INCLUDE_GTEST_GTEST_TEST_PART_H_ #define GTEST_INCLUDE_GTEST_GTEST_TEST_PART_H_ #include #include namespace testing { // A copyable object representing the result of a test part (i.e. an // assertion or an explicit FAIL(), ADD_FAILURE(), or SUCCESS()). // // Don't inherit from TestPartResult as its destructor is not virtual. class GTEST_API_ TestPartResult { public: // The possible outcomes of a test part (i.e. an assertion or an // explicit SUCCEED(), FAIL(), or ADD_FAILURE()). enum Type { kSuccess, // Succeeded. kNonFatalFailure, // Failed but the test can continue. kFatalFailure // Failed and the test should be terminated. }; // C'tor. TestPartResult does NOT have a default constructor. // Always use this constructor (with parameters) to create a // TestPartResult object. TestPartResult(Type a_type, const char* a_file_name, int a_line_number, const char* a_message) : type_(a_type), file_name_(a_file_name), line_number_(a_line_number), summary_(ExtractSummary(a_message)), message_(a_message) { } // Gets the outcome of the test part. Type type() const { return type_; } // Gets the name of the source file where the test part took place, or // NULL if it's unknown. const char* file_name() const { return file_name_.c_str(); } // Gets the line in the source file where the test part took place, // or -1 if it's unknown. int line_number() const { return line_number_; } // Gets the summary of the failure message. const char* summary() const { return summary_.c_str(); } // Gets the message associated with the test part. const char* message() const { return message_.c_str(); } // Returns true iff the test part passed. bool passed() const { return type_ == kSuccess; } // Returns true iff the test part failed. bool failed() const { return type_ != kSuccess; } // Returns true iff the test part non-fatally failed. bool nonfatally_failed() const { return type_ == kNonFatalFailure; } // Returns true iff the test part fatally failed. bool fatally_failed() const { return type_ == kFatalFailure; } private: Type type_; // Gets the summary of the failure message by omitting the stack // trace in it. static internal::String ExtractSummary(const char* message); // The name of the source file where the test part took place, or // NULL if the source file is unknown. internal::String file_name_; // The line in the source file where the test part took place, or -1 // if the line number is unknown. int line_number_; internal::String summary_; // The test failure summary. internal::String message_; // The test failure message. }; // Prints a TestPartResult object. std::ostream& operator<<(std::ostream& os, const TestPartResult& result); // An array of TestPartResult objects. // // Don't inherit from TestPartResultArray as its destructor is not // virtual. class GTEST_API_ TestPartResultArray { public: TestPartResultArray() {} // Appends the given TestPartResult to the array. void Append(const TestPartResult& result); // Returns the TestPartResult at the given index (0-based). const TestPartResult& GetTestPartResult(int index) const; // Returns the number of TestPartResult objects in the array. int size() const; private: std::vector array_; GTEST_DISALLOW_COPY_AND_ASSIGN_(TestPartResultArray); }; // This interface knows how to report a test part result. class TestPartResultReporterInterface { public: virtual ~TestPartResultReporterInterface() {} virtual void ReportTestPartResult(const TestPartResult& result) = 0; }; namespace internal { // This helper class is used by {ASSERT|EXPECT}_NO_FATAL_FAILURE to check if a // statement generates new fatal failures. To do so it registers itself as the // current test part result reporter. Besides checking if fatal failures were // reported, it only delegates the reporting to the former result reporter. // The original result reporter is restored in the destructor. // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. class GTEST_API_ HasNewFatalFailureHelper : public TestPartResultReporterInterface { public: HasNewFatalFailureHelper(); virtual ~HasNewFatalFailureHelper(); virtual void ReportTestPartResult(const TestPartResult& result); bool has_new_fatal_failure() const { return has_new_fatal_failure_; } private: bool has_new_fatal_failure_; TestPartResultReporterInterface* original_reporter_; GTEST_DISALLOW_COPY_AND_ASSIGN_(HasNewFatalFailureHelper); }; } // namespace internal } // namespace testing #endif // GTEST_INCLUDE_GTEST_GTEST_TEST_PART_H_ // Copyright 2008 Google Inc. // All Rights Reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Author: wan@google.com (Zhanyong Wan) #ifndef GTEST_INCLUDE_GTEST_GTEST_TYPED_TEST_H_ #define GTEST_INCLUDE_GTEST_GTEST_TYPED_TEST_H_ // This header implements typed tests and type-parameterized tests. // Typed (aka type-driven) tests repeat the same test for types in a // list. You must know which types you want to test with when writing // typed tests. Here's how you do it: #if 0 // First, define a fixture class template. It should be parameterized // by a type. Remember to derive it from testing::Test. template class FooTest : public testing::Test { public: ... typedef std::list List; static T shared_; T value_; }; // Next, associate a list of types with the test case, which will be // repeated for each type in the list. The typedef is necessary for // the macro to parse correctly. typedef testing::Types MyTypes; TYPED_TEST_CASE(FooTest, MyTypes); // If the type list contains only one type, you can write that type // directly without Types<...>: // TYPED_TEST_CASE(FooTest, int); // Then, use TYPED_TEST() instead of TEST_F() to define as many typed // tests for this test case as you want. TYPED_TEST(FooTest, DoesBlah) { // Inside a test, refer to TypeParam to get the type parameter. // Since we are inside a derived class template, C++ requires use to // visit the members of FooTest via 'this'. TypeParam n = this->value_; // To visit static members of the fixture, add the TestFixture:: // prefix. n += TestFixture::shared_; // To refer to typedefs in the fixture, add the "typename // TestFixture::" prefix. typename TestFixture::List values; values.push_back(n); ... } TYPED_TEST(FooTest, HasPropertyA) { ... } #endif // 0 // Type-parameterized tests are abstract test patterns parameterized // by a type. Compared with typed tests, type-parameterized tests // allow you to define the test pattern without knowing what the type // parameters are. The defined pattern can be instantiated with // different types any number of times, in any number of translation // units. // // If you are designing an interface or concept, you can define a // suite of type-parameterized tests to verify properties that any // valid implementation of the interface/concept should have. Then, // each implementation can easily instantiate the test suite to verify // that it conforms to the requirements, without having to write // similar tests repeatedly. Here's an example: #if 0 // First, define a fixture class template. It should be parameterized // by a type. Remember to derive it from testing::Test. template class FooTest : public testing::Test { ... }; // Next, declare that you will define a type-parameterized test case // (the _P suffix is for "parameterized" or "pattern", whichever you // prefer): TYPED_TEST_CASE_P(FooTest); // Then, use TYPED_TEST_P() to define as many type-parameterized tests // for this type-parameterized test case as you want. TYPED_TEST_P(FooTest, DoesBlah) { // Inside a test, refer to TypeParam to get the type parameter. TypeParam n = 0; ... } TYPED_TEST_P(FooTest, HasPropertyA) { ... } // Now the tricky part: you need to register all test patterns before // you can instantiate them. The first argument of the macro is the // test case name; the rest are the names of the tests in this test // case. REGISTER_TYPED_TEST_CASE_P(FooTest, DoesBlah, HasPropertyA); // Finally, you are free to instantiate the pattern with the types you // want. If you put the above code in a header file, you can #include // it in multiple C++ source files and instantiate it multiple times. // // To distinguish different instances of the pattern, the first // argument to the INSTANTIATE_* macro is a prefix that will be added // to the actual test case name. Remember to pick unique prefixes for // different instances. typedef testing::Types MyTypes; INSTANTIATE_TYPED_TEST_CASE_P(My, FooTest, MyTypes); // If the type list contains only one type, you can write that type // directly without Types<...>: // INSTANTIATE_TYPED_TEST_CASE_P(My, FooTest, int); #endif // 0 // Implements typed tests. #if GTEST_HAS_TYPED_TEST // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // Expands to the name of the typedef for the type parameters of the // given test case. # define GTEST_TYPE_PARAMS_(TestCaseName) gtest_type_params_##TestCaseName##_ // The 'Types' template argument below must have spaces around it // since some compilers may choke on '>>' when passing a template // instance (e.g. Types) # define TYPED_TEST_CASE(CaseName, Types) \ typedef ::testing::internal::TypeList< Types >::type \ GTEST_TYPE_PARAMS_(CaseName) # define TYPED_TEST(CaseName, TestName) \ template \ class GTEST_TEST_CLASS_NAME_(CaseName, TestName) \ : public CaseName { \ private: \ typedef CaseName TestFixture; \ typedef gtest_TypeParam_ TypeParam; \ virtual void TestBody(); \ }; \ bool gtest_##CaseName##_##TestName##_registered_ GTEST_ATTRIBUTE_UNUSED_ = \ ::testing::internal::TypeParameterizedTest< \ CaseName, \ ::testing::internal::TemplateSel< \ GTEST_TEST_CLASS_NAME_(CaseName, TestName)>, \ GTEST_TYPE_PARAMS_(CaseName)>::Register(\ "", #CaseName, #TestName, 0); \ template \ void GTEST_TEST_CLASS_NAME_(CaseName, TestName)::TestBody() #endif // GTEST_HAS_TYPED_TEST // Implements type-parameterized tests. #if GTEST_HAS_TYPED_TEST_P // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // Expands to the namespace name that the type-parameterized tests for // the given type-parameterized test case are defined in. The exact // name of the namespace is subject to change without notice. # define GTEST_CASE_NAMESPACE_(TestCaseName) \ gtest_case_##TestCaseName##_ // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // // Expands to the name of the variable used to remember the names of // the defined tests in the given test case. # define GTEST_TYPED_TEST_CASE_P_STATE_(TestCaseName) \ gtest_typed_test_case_p_state_##TestCaseName##_ // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE DIRECTLY. // // Expands to the name of the variable used to remember the names of // the registered tests in the given test case. # define GTEST_REGISTERED_TEST_NAMES_(TestCaseName) \ gtest_registered_test_names_##TestCaseName##_ // The variables defined in the type-parameterized test macros are // static as typically these macros are used in a .h file that can be // #included in multiple translation units linked together. # define TYPED_TEST_CASE_P(CaseName) \ static ::testing::internal::TypedTestCasePState \ GTEST_TYPED_TEST_CASE_P_STATE_(CaseName) # define TYPED_TEST_P(CaseName, TestName) \ namespace GTEST_CASE_NAMESPACE_(CaseName) { \ template \ class TestName : public CaseName { \ private: \ typedef CaseName TestFixture; \ typedef gtest_TypeParam_ TypeParam; \ virtual void TestBody(); \ }; \ static bool gtest_##TestName##_defined_ GTEST_ATTRIBUTE_UNUSED_ = \ GTEST_TYPED_TEST_CASE_P_STATE_(CaseName).AddTestName(\ __FILE__, __LINE__, #CaseName, #TestName); \ } \ template \ void GTEST_CASE_NAMESPACE_(CaseName)::TestName::TestBody() # define REGISTER_TYPED_TEST_CASE_P(CaseName, ...) \ namespace GTEST_CASE_NAMESPACE_(CaseName) { \ typedef ::testing::internal::Templates<__VA_ARGS__>::type gtest_AllTests_; \ } \ static const char* const GTEST_REGISTERED_TEST_NAMES_(CaseName) = \ GTEST_TYPED_TEST_CASE_P_STATE_(CaseName).VerifyRegisteredTestNames(\ __FILE__, __LINE__, #__VA_ARGS__) // The 'Types' template argument below must have spaces around it // since some compilers may choke on '>>' when passing a template // instance (e.g. Types) # define INSTANTIATE_TYPED_TEST_CASE_P(Prefix, CaseName, Types) \ bool gtest_##Prefix##_##CaseName GTEST_ATTRIBUTE_UNUSED_ = \ ::testing::internal::TypeParameterizedTestCase::type>::Register(\ #Prefix, #CaseName, GTEST_REGISTERED_TEST_NAMES_(CaseName)) #endif // GTEST_HAS_TYPED_TEST_P #endif // GTEST_INCLUDE_GTEST_GTEST_TYPED_TEST_H_ // Depending on the platform, different string classes are available. // On Linux, in addition to ::std::string, Google also makes use of // class ::string, which has the same interface as ::std::string, but // has a different implementation. // // The user can define GTEST_HAS_GLOBAL_STRING to 1 to indicate that // ::string is available AND is a distinct type to ::std::string, or // define it to 0 to indicate otherwise. // // If the user's ::std::string and ::string are the same class due to // aliasing, he should define GTEST_HAS_GLOBAL_STRING to 0. // // If the user doesn't define GTEST_HAS_GLOBAL_STRING, it is defined // heuristically. namespace testing { // Declares the flags. // This flag temporary enables the disabled tests. GTEST_DECLARE_bool_(also_run_disabled_tests); // This flag brings the debugger on an assertion failure. GTEST_DECLARE_bool_(break_on_failure); // This flag controls whether Google Test catches all test-thrown exceptions // and logs them as failures. GTEST_DECLARE_bool_(catch_exceptions); // This flag enables using colors in terminal output. Available values are // "yes" to enable colors, "no" (disable colors), or "auto" (the default) // to let Google Test decide. GTEST_DECLARE_string_(color); // This flag sets up the filter to select by name using a glob pattern // the tests to run. If the filter is not given all tests are executed. GTEST_DECLARE_string_(filter); // This flag causes the Google Test to list tests. None of the tests listed // are actually run if the flag is provided. GTEST_DECLARE_bool_(list_tests); // This flag controls whether Google Test emits a detailed XML report to a file // in addition to its normal textual output. GTEST_DECLARE_string_(output); // This flags control whether Google Test prints the elapsed time for each // test. GTEST_DECLARE_bool_(print_time); // This flag specifies the random number seed. GTEST_DECLARE_int32_(random_seed); // This flag sets how many times the tests are repeated. The default value // is 1. If the value is -1 the tests are repeating forever. GTEST_DECLARE_int32_(repeat); // This flag controls whether Google Test includes Google Test internal // stack frames in failure stack traces. GTEST_DECLARE_bool_(show_internal_stack_frames); // When this flag is specified, tests' order is randomized on every iteration. GTEST_DECLARE_bool_(shuffle); // This flag specifies the maximum number of stack frames to be // printed in a failure message. GTEST_DECLARE_int32_(stack_trace_depth); // When this flag is specified, a failed assertion will throw an // exception if exceptions are enabled, or exit the program with a // non-zero code otherwise. GTEST_DECLARE_bool_(throw_on_failure); // When this flag is set with a "host:port" string, on supported // platforms test results are streamed to the specified port on // the specified host machine. GTEST_DECLARE_string_(stream_result_to); // The upper limit for valid stack trace depths. const int kMaxStackTraceDepth = 100; namespace internal { class AssertHelper; class DefaultGlobalTestPartResultReporter; class ExecDeathTest; class NoExecDeathTest; class FinalSuccessChecker; class GTestFlagSaver; class TestResultAccessor; class TestEventListenersAccessor; class TestEventRepeater; class WindowsDeathTest; class UnitTestImpl* GetUnitTestImpl(); void ReportFailureInUnknownLocation(TestPartResult::Type result_type, const String& message); // Converts a streamable value to a String. A NULL pointer is // converted to "(null)". When the input value is a ::string, // ::std::string, ::wstring, or ::std::wstring object, each NUL // character in it is replaced with "\\0". // Declared in gtest-internal.h but defined here, so that it has access // to the definition of the Message class, required by the ARM // compiler. template String StreamableToString(const T& streamable) { return (Message() << streamable).GetString(); } } // namespace internal // The friend relationship of some of these classes is cyclic. // If we don't forward declare them the compiler might confuse the classes // in friendship clauses with same named classes on the scope. class Test; class TestCase; class TestInfo; class UnitTest; // A class for indicating whether an assertion was successful. When // the assertion wasn't successful, the AssertionResult object // remembers a non-empty message that describes how it failed. // // To create an instance of this class, use one of the factory functions // (AssertionSuccess() and AssertionFailure()). // // This class is useful for two purposes: // 1. Defining predicate functions to be used with Boolean test assertions // EXPECT_TRUE/EXPECT_FALSE and their ASSERT_ counterparts // 2. Defining predicate-format functions to be // used with predicate assertions (ASSERT_PRED_FORMAT*, etc). // // For example, if you define IsEven predicate: // // testing::AssertionResult IsEven(int n) { // if ((n % 2) == 0) // return testing::AssertionSuccess(); // else // return testing::AssertionFailure() << n << " is odd"; // } // // Then the failed expectation EXPECT_TRUE(IsEven(Fib(5))) // will print the message // // Value of: IsEven(Fib(5)) // Actual: false (5 is odd) // Expected: true // // instead of a more opaque // // Value of: IsEven(Fib(5)) // Actual: false // Expected: true // // in case IsEven is a simple Boolean predicate. // // If you expect your predicate to be reused and want to support informative // messages in EXPECT_FALSE and ASSERT_FALSE (negative assertions show up // about half as often as positive ones in our tests), supply messages for // both success and failure cases: // // testing::AssertionResult IsEven(int n) { // if ((n % 2) == 0) // return testing::AssertionSuccess() << n << " is even"; // else // return testing::AssertionFailure() << n << " is odd"; // } // // Then a statement EXPECT_FALSE(IsEven(Fib(6))) will print // // Value of: IsEven(Fib(6)) // Actual: true (8 is even) // Expected: false // // NB: Predicates that support negative Boolean assertions have reduced // performance in positive ones so be careful not to use them in tests // that have lots (tens of thousands) of positive Boolean assertions. // // To use this class with EXPECT_PRED_FORMAT assertions such as: // // // Verifies that Foo() returns an even number. // EXPECT_PRED_FORMAT1(IsEven, Foo()); // // you need to define: // // testing::AssertionResult IsEven(const char* expr, int n) { // if ((n % 2) == 0) // return testing::AssertionSuccess(); // else // return testing::AssertionFailure() // << "Expected: " << expr << " is even\n Actual: it's " << n; // } // // If Foo() returns 5, you will see the following message: // // Expected: Foo() is even // Actual: it's 5 // class GTEST_API_ AssertionResult { public: // Copy constructor. // Used in EXPECT_TRUE/FALSE(assertion_result). AssertionResult(const AssertionResult& other); // Used in the EXPECT_TRUE/FALSE(bool_expression). explicit AssertionResult(bool success) : success_(success) {} // Returns true iff the assertion succeeded. operator bool() const { return success_; } // NOLINT // Returns the assertion's negation. Used with EXPECT/ASSERT_FALSE. AssertionResult operator!() const; // Returns the text streamed into this AssertionResult. Test assertions // use it when they fail (i.e., the predicate's outcome doesn't match the // assertion's expectation). When nothing has been streamed into the // object, returns an empty string. const char* message() const { return message_.get() != NULL ? message_->c_str() : ""; } // TODO(vladl@google.com): Remove this after making sure no clients use it. // Deprecated; please use message() instead. const char* failure_message() const { return message(); } // Streams a custom failure message into this object. template AssertionResult& operator<<(const T& value) { AppendMessage(Message() << value); return *this; } // Allows streaming basic output manipulators such as endl or flush into // this object. AssertionResult& operator<<( ::std::ostream& (*basic_manipulator)(::std::ostream& stream)) { AppendMessage(Message() << basic_manipulator); return *this; } private: // Appends the contents of message to message_. void AppendMessage(const Message& a_message) { if (message_.get() == NULL) message_.reset(new ::std::string); message_->append(a_message.GetString().c_str()); } // Stores result of the assertion predicate. bool success_; // Stores the message describing the condition in case the expectation // construct is not satisfied with the predicate's outcome. // Referenced via a pointer to avoid taking too much stack frame space // with test assertions. internal::scoped_ptr< ::std::string> message_; GTEST_DISALLOW_ASSIGN_(AssertionResult); }; // Makes a successful assertion result. GTEST_API_ AssertionResult AssertionSuccess(); // Makes a failed assertion result. GTEST_API_ AssertionResult AssertionFailure(); // Makes a failed assertion result with the given failure message. // Deprecated; use AssertionFailure() << msg. GTEST_API_ AssertionResult AssertionFailure(const Message& msg); // The abstract class that all tests inherit from. // // In Google Test, a unit test program contains one or many TestCases, and // each TestCase contains one or many Tests. // // When you define a test using the TEST macro, you don't need to // explicitly derive from Test - the TEST macro automatically does // this for you. // // The only time you derive from Test is when defining a test fixture // to be used a TEST_F. For example: // // class FooTest : public testing::Test { // protected: // virtual void SetUp() { ... } // virtual void TearDown() { ... } // ... // }; // // TEST_F(FooTest, Bar) { ... } // TEST_F(FooTest, Baz) { ... } // // Test is not copyable. class GTEST_API_ Test { public: friend class TestInfo; // Defines types for pointers to functions that set up and tear down // a test case. typedef internal::SetUpTestCaseFunc SetUpTestCaseFunc; typedef internal::TearDownTestCaseFunc TearDownTestCaseFunc; // The d'tor is virtual as we intend to inherit from Test. virtual ~Test(); // Sets up the stuff shared by all tests in this test case. // // Google Test will call Foo::SetUpTestCase() before running the first // test in test case Foo. Hence a sub-class can define its own // SetUpTestCase() method to shadow the one defined in the super // class. static void SetUpTestCase() {} // Tears down the stuff shared by all tests in this test case. // // Google Test will call Foo::TearDownTestCase() after running the last // test in test case Foo. Hence a sub-class can define its own // TearDownTestCase() method to shadow the one defined in the super // class. static void TearDownTestCase() {} // Returns true iff the current test has a fatal failure. static bool HasFatalFailure(); // Returns true iff the current test has a non-fatal failure. static bool HasNonfatalFailure(); // Returns true iff the current test has a (either fatal or // non-fatal) failure. static bool HasFailure() { return HasFatalFailure() || HasNonfatalFailure(); } // Logs a property for the current test. Only the last value for a given // key is remembered. // These are public static so they can be called from utility functions // that are not members of the test fixture. // The arguments are const char* instead strings, as Google Test is used // on platforms where string doesn't compile. // // Note that a driving consideration for these RecordProperty methods // was to produce xml output suited to the Greenspan charting utility, // which at present will only chart values that fit in a 32-bit int. It // is the user's responsibility to restrict their values to 32-bit ints // if they intend them to be used with Greenspan. static void RecordProperty(const char* key, const char* value); static void RecordProperty(const char* key, int value); protected: // Creates a Test object. Test(); // Sets up the test fixture. virtual void SetUp(); // Tears down the test fixture. virtual void TearDown(); private: // Returns true iff the current test has the same fixture class as // the first test in the current test case. static bool HasSameFixtureClass(); // Runs the test after the test fixture has been set up. // // A sub-class must implement this to define the test logic. // // DO NOT OVERRIDE THIS FUNCTION DIRECTLY IN A USER PROGRAM. // Instead, use the TEST or TEST_F macro. virtual void TestBody() = 0; // Sets up, executes, and tears down the test. void Run(); // Deletes self. We deliberately pick an unusual name for this // internal method to avoid clashing with names used in user TESTs. void DeleteSelf_() { delete this; } // Uses a GTestFlagSaver to save and restore all Google Test flags. const internal::GTestFlagSaver* const gtest_flag_saver_; // Often a user mis-spells SetUp() as Setup() and spends a long time // wondering why it is never called by Google Test. The declaration of // the following method is solely for catching such an error at // compile time: // // - The return type is deliberately chosen to be not void, so it // will be a conflict if a user declares void Setup() in his test // fixture. // // - This method is private, so it will be another compiler error // if a user calls it from his test fixture. // // DO NOT OVERRIDE THIS FUNCTION. // // If you see an error about overriding the following function or // about it being private, you have mis-spelled SetUp() as Setup(). struct Setup_should_be_spelled_SetUp {}; virtual Setup_should_be_spelled_SetUp* Setup() { return NULL; } // We disallow copying Tests. GTEST_DISALLOW_COPY_AND_ASSIGN_(Test); }; typedef internal::TimeInMillis TimeInMillis; // A copyable object representing a user specified test property which can be // output as a key/value string pair. // // Don't inherit from TestProperty as its destructor is not virtual. class TestProperty { public: // C'tor. TestProperty does NOT have a default constructor. // Always use this constructor (with parameters) to create a // TestProperty object. TestProperty(const char* a_key, const char* a_value) : key_(a_key), value_(a_value) { } // Gets the user supplied key. const char* key() const { return key_.c_str(); } // Gets the user supplied value. const char* value() const { return value_.c_str(); } // Sets a new value, overriding the one supplied in the constructor. void SetValue(const char* new_value) { value_ = new_value; } private: // The key supplied by the user. internal::String key_; // The value supplied by the user. internal::String value_; }; // The result of a single Test. This includes a list of // TestPartResults, a list of TestProperties, a count of how many // death tests there are in the Test, and how much time it took to run // the Test. // // TestResult is not copyable. class GTEST_API_ TestResult { public: // Creates an empty TestResult. TestResult(); // D'tor. Do not inherit from TestResult. ~TestResult(); // Gets the number of all test parts. This is the sum of the number // of successful test parts and the number of failed test parts. int total_part_count() const; // Returns the number of the test properties. int test_property_count() const; // Returns true iff the test passed (i.e. no test part failed). bool Passed() const { return !Failed(); } // Returns true iff the test failed. bool Failed() const; // Returns true iff the test fatally failed. bool HasFatalFailure() const; // Returns true iff the test has a non-fatal failure. bool HasNonfatalFailure() const; // Returns the elapsed time, in milliseconds. TimeInMillis elapsed_time() const { return elapsed_time_; } // Returns the i-th test part result among all the results. i can range // from 0 to test_property_count() - 1. If i is not in that range, aborts // the program. const TestPartResult& GetTestPartResult(int i) const; // Returns the i-th test property. i can range from 0 to // test_property_count() - 1. If i is not in that range, aborts the // program. const TestProperty& GetTestProperty(int i) const; private: friend class TestInfo; friend class UnitTest; friend class internal::DefaultGlobalTestPartResultReporter; friend class internal::ExecDeathTest; friend class internal::TestResultAccessor; friend class internal::UnitTestImpl; friend class internal::WindowsDeathTest; // Gets the vector of TestPartResults. const std::vector& test_part_results() const { return test_part_results_; } // Gets the vector of TestProperties. const std::vector& test_properties() const { return test_properties_; } // Sets the elapsed time. void set_elapsed_time(TimeInMillis elapsed) { elapsed_time_ = elapsed; } // Adds a test property to the list. The property is validated and may add // a non-fatal failure if invalid (e.g., if it conflicts with reserved // key names). If a property is already recorded for the same key, the // value will be updated, rather than storing multiple values for the same // key. void RecordProperty(const TestProperty& test_property); // Adds a failure if the key is a reserved attribute of Google Test // testcase tags. Returns true if the property is valid. // TODO(russr): Validate attribute names are legal and human readable. static bool ValidateTestProperty(const TestProperty& test_property); // Adds a test part result to the list. void AddTestPartResult(const TestPartResult& test_part_result); // Returns the death test count. int death_test_count() const { return death_test_count_; } // Increments the death test count, returning the new count. int increment_death_test_count() { return ++death_test_count_; } // Clears the test part results. void ClearTestPartResults(); // Clears the object. void Clear(); // Protects mutable state of the property vector and of owned // properties, whose values may be updated. internal::Mutex test_properites_mutex_; // The vector of TestPartResults std::vector test_part_results_; // The vector of TestProperties std::vector test_properties_; // Running count of death tests. int death_test_count_; // The elapsed time, in milliseconds. TimeInMillis elapsed_time_; // We disallow copying TestResult. GTEST_DISALLOW_COPY_AND_ASSIGN_(TestResult); }; // class TestResult // A TestInfo object stores the following information about a test: // // Test case name // Test name // Whether the test should be run // A function pointer that creates the test object when invoked // Test result // // The constructor of TestInfo registers itself with the UnitTest // singleton such that the RUN_ALL_TESTS() macro knows which tests to // run. class GTEST_API_ TestInfo { public: // Destructs a TestInfo object. This function is not virtual, so // don't inherit from TestInfo. ~TestInfo(); // Returns the test case name. const char* test_case_name() const { return test_case_name_.c_str(); } // Returns the test name. const char* name() const { return name_.c_str(); } // Returns the name of the parameter type, or NULL if this is not a typed // or a type-parameterized test. const char* type_param() const { if (type_param_.get() != NULL) return type_param_->c_str(); return NULL; } // Returns the text representation of the value parameter, or NULL if this // is not a value-parameterized test. const char* value_param() const { if (value_param_.get() != NULL) return value_param_->c_str(); return NULL; } // Returns true if this test should run, that is if the test is not disabled // (or it is disabled but the also_run_disabled_tests flag has been specified) // and its full name matches the user-specified filter. // // Google Test allows the user to filter the tests by their full names. // The full name of a test Bar in test case Foo is defined as // "Foo.Bar". Only the tests that match the filter will run. // // A filter is a colon-separated list of glob (not regex) patterns, // optionally followed by a '-' and a colon-separated list of // negative patterns (tests to exclude). A test is run if it // matches one of the positive patterns and does not match any of // the negative patterns. // // For example, *A*:Foo.* is a filter that matches any string that // contains the character 'A' or starts with "Foo.". bool should_run() const { return should_run_; } // Returns the result of the test. const TestResult* result() const { return &result_; } private: #if GTEST_HAS_DEATH_TEST friend class internal::DefaultDeathTestFactory; #endif // GTEST_HAS_DEATH_TEST friend class Test; friend class TestCase; friend class internal::UnitTestImpl; friend TestInfo* internal::MakeAndRegisterTestInfo( const char* test_case_name, const char* name, const char* type_param, const char* value_param, internal::TypeId fixture_class_id, Test::SetUpTestCaseFunc set_up_tc, Test::TearDownTestCaseFunc tear_down_tc, internal::TestFactoryBase* factory); // Constructs a TestInfo object. The newly constructed instance assumes // ownership of the factory object. TestInfo(const char* test_case_name, const char* name, const char* a_type_param, const char* a_value_param, internal::TypeId fixture_class_id, internal::TestFactoryBase* factory); // Increments the number of death tests encountered in this test so // far. int increment_death_test_count() { return result_.increment_death_test_count(); } // Creates the test object, runs it, records its result, and then // deletes it. void Run(); static void ClearTestResult(TestInfo* test_info) { test_info->result_.Clear(); } // These fields are immutable properties of the test. const std::string test_case_name_; // Test case name const std::string name_; // Test name // Name of the parameter type, or NULL if this is not a typed or a // type-parameterized test. const internal::scoped_ptr type_param_; // Text representation of the value parameter, or NULL if this is not a // value-parameterized test. const internal::scoped_ptr value_param_; const internal::TypeId fixture_class_id_; // ID of the test fixture class bool should_run_; // True iff this test should run bool is_disabled_; // True iff this test is disabled bool matches_filter_; // True if this test matches the // user-specified filter. internal::TestFactoryBase* const factory_; // The factory that creates // the test object // This field is mutable and needs to be reset before running the // test for the second time. TestResult result_; GTEST_DISALLOW_COPY_AND_ASSIGN_(TestInfo); }; // A test case, which consists of a vector of TestInfos. // // TestCase is not copyable. class GTEST_API_ TestCase { public: // Creates a TestCase with the given name. // // TestCase does NOT have a default constructor. Always use this // constructor to create a TestCase object. // // Arguments: // // name: name of the test case // a_type_param: the name of the test's type parameter, or NULL if // this is not a type-parameterized test. // set_up_tc: pointer to the function that sets up the test case // tear_down_tc: pointer to the function that tears down the test case TestCase(const char* name, const char* a_type_param, Test::SetUpTestCaseFunc set_up_tc, Test::TearDownTestCaseFunc tear_down_tc); // Destructor of TestCase. virtual ~TestCase(); // Gets the name of the TestCase. const char* name() const { return name_.c_str(); } // Returns the name of the parameter type, or NULL if this is not a // type-parameterized test case. const char* type_param() const { if (type_param_.get() != NULL) return type_param_->c_str(); return NULL; } // Returns true if any test in this test case should run. bool should_run() const { return should_run_; } // Gets the number of successful tests in this test case. int successful_test_count() const; // Gets the number of failed tests in this test case. int failed_test_count() const; // Gets the number of disabled tests in this test case. int disabled_test_count() const; // Get the number of tests in this test case that should run. int test_to_run_count() const; // Gets the number of all tests in this test case. int total_test_count() const; // Returns true iff the test case passed. bool Passed() const { return !Failed(); } // Returns true iff the test case failed. bool Failed() const { return failed_test_count() > 0; } // Returns the elapsed time, in milliseconds. TimeInMillis elapsed_time() const { return elapsed_time_; } // Returns the i-th test among all the tests. i can range from 0 to // total_test_count() - 1. If i is not in that range, returns NULL. const TestInfo* GetTestInfo(int i) const; private: friend class Test; friend class internal::UnitTestImpl; // Gets the (mutable) vector of TestInfos in this TestCase. std::vector& test_info_list() { return test_info_list_; } // Gets the (immutable) vector of TestInfos in this TestCase. const std::vector& test_info_list() const { return test_info_list_; } // Returns the i-th test among all the tests. i can range from 0 to // total_test_count() - 1. If i is not in that range, returns NULL. TestInfo* GetMutableTestInfo(int i); // Sets the should_run member. void set_should_run(bool should) { should_run_ = should; } // Adds a TestInfo to this test case. Will delete the TestInfo upon // destruction of the TestCase object. void AddTestInfo(TestInfo * test_info); // Clears the results of all tests in this test case. void ClearResult(); // Clears the results of all tests in the given test case. static void ClearTestCaseResult(TestCase* test_case) { test_case->ClearResult(); } // Runs every test in this TestCase. void Run(); // Runs SetUpTestCase() for this TestCase. This wrapper is needed // for catching exceptions thrown from SetUpTestCase(). void RunSetUpTestCase() { (*set_up_tc_)(); } // Runs TearDownTestCase() for this TestCase. This wrapper is // needed for catching exceptions thrown from TearDownTestCase(). void RunTearDownTestCase() { (*tear_down_tc_)(); } // Returns true iff test passed. static bool TestPassed(const TestInfo* test_info) { return test_info->should_run() && test_info->result()->Passed(); } // Returns true iff test failed. static bool TestFailed(const TestInfo* test_info) { return test_info->should_run() && test_info->result()->Failed(); } // Returns true iff test is disabled. static bool TestDisabled(const TestInfo* test_info) { return test_info->is_disabled_; } // Returns true if the given test should run. static bool ShouldRunTest(const TestInfo* test_info) { return test_info->should_run(); } // Shuffles the tests in this test case. void ShuffleTests(internal::Random* random); // Restores the test order to before the first shuffle. void UnshuffleTests(); // Name of the test case. internal::String name_; // Name of the parameter type, or NULL if this is not a typed or a // type-parameterized test. const internal::scoped_ptr type_param_; // The vector of TestInfos in their original order. It owns the // elements in the vector. std::vector test_info_list_; // Provides a level of indirection for the test list to allow easy // shuffling and restoring the test order. The i-th element in this // vector is the index of the i-th test in the shuffled test list. std::vector test_indices_; // Pointer to the function that sets up the test case. Test::SetUpTestCaseFunc set_up_tc_; // Pointer to the function that tears down the test case. Test::TearDownTestCaseFunc tear_down_tc_; // True iff any test in this test case should run. bool should_run_; // Elapsed time, in milliseconds. TimeInMillis elapsed_time_; // We disallow copying TestCases. GTEST_DISALLOW_COPY_AND_ASSIGN_(TestCase); }; // An Environment object is capable of setting up and tearing down an // environment. The user should subclass this to define his own // environment(s). // // An Environment object does the set-up and tear-down in virtual // methods SetUp() and TearDown() instead of the constructor and the // destructor, as: // // 1. You cannot safely throw from a destructor. This is a problem // as in some cases Google Test is used where exceptions are enabled, and // we may want to implement ASSERT_* using exceptions where they are // available. // 2. You cannot use ASSERT_* directly in a constructor or // destructor. class Environment { public: // The d'tor is virtual as we need to subclass Environment. virtual ~Environment() {} // Override this to define how to set up the environment. virtual void SetUp() {} // Override this to define how to tear down the environment. virtual void TearDown() {} private: // If you see an error about overriding the following function or // about it being private, you have mis-spelled SetUp() as Setup(). struct Setup_should_be_spelled_SetUp {}; virtual Setup_should_be_spelled_SetUp* Setup() { return NULL; } }; // The interface for tracing execution of tests. The methods are organized in // the order the corresponding events are fired. class TestEventListener { public: virtual ~TestEventListener() {} // Fired before any test activity starts. virtual void OnTestProgramStart(const UnitTest& unit_test) = 0; // Fired before each iteration of tests starts. There may be more than // one iteration if GTEST_FLAG(repeat) is set. iteration is the iteration // index, starting from 0. virtual void OnTestIterationStart(const UnitTest& unit_test, int iteration) = 0; // Fired before environment set-up for each iteration of tests starts. virtual void OnEnvironmentsSetUpStart(const UnitTest& unit_test) = 0; // Fired after environment set-up for each iteration of tests ends. virtual void OnEnvironmentsSetUpEnd(const UnitTest& unit_test) = 0; // Fired before the test case starts. virtual void OnTestCaseStart(const TestCase& test_case) = 0; // Fired before the test starts. virtual void OnTestStart(const TestInfo& test_info) = 0; // Fired after a failed assertion or a SUCCEED() invocation. virtual void OnTestPartResult(const TestPartResult& test_part_result) = 0; // Fired after the test ends. virtual void OnTestEnd(const TestInfo& test_info) = 0; // Fired after the test case ends. virtual void OnTestCaseEnd(const TestCase& test_case) = 0; // Fired before environment tear-down for each iteration of tests starts. virtual void OnEnvironmentsTearDownStart(const UnitTest& unit_test) = 0; // Fired after environment tear-down for each iteration of tests ends. virtual void OnEnvironmentsTearDownEnd(const UnitTest& unit_test) = 0; // Fired after each iteration of tests finishes. virtual void OnTestIterationEnd(const UnitTest& unit_test, int iteration) = 0; // Fired after all test activities have ended. virtual void OnTestProgramEnd(const UnitTest& unit_test) = 0; }; // The convenience class for users who need to override just one or two // methods and are not concerned that a possible change to a signature of // the methods they override will not be caught during the build. For // comments about each method please see the definition of TestEventListener // above. class EmptyTestEventListener : public TestEventListener { public: virtual void OnTestProgramStart(const UnitTest& /*unit_test*/) {} virtual void OnTestIterationStart(const UnitTest& /*unit_test*/, int /*iteration*/) {} virtual void OnEnvironmentsSetUpStart(const UnitTest& /*unit_test*/) {} virtual void OnEnvironmentsSetUpEnd(const UnitTest& /*unit_test*/) {} virtual void OnTestCaseStart(const TestCase& /*test_case*/) {} virtual void OnTestStart(const TestInfo& /*test_info*/) {} virtual void OnTestPartResult(const TestPartResult& /*test_part_result*/) {} virtual void OnTestEnd(const TestInfo& /*test_info*/) {} virtual void OnTestCaseEnd(const TestCase& /*test_case*/) {} virtual void OnEnvironmentsTearDownStart(const UnitTest& /*unit_test*/) {} virtual void OnEnvironmentsTearDownEnd(const UnitTest& /*unit_test*/) {} virtual void OnTestIterationEnd(const UnitTest& /*unit_test*/, int /*iteration*/) {} virtual void OnTestProgramEnd(const UnitTest& /*unit_test*/) {} }; // TestEventListeners lets users add listeners to track events in Google Test. class GTEST_API_ TestEventListeners { public: TestEventListeners(); ~TestEventListeners(); // Appends an event listener to the end of the list. Google Test assumes // the ownership of the listener (i.e. it will delete the listener when // the test program finishes). void Append(TestEventListener* listener); // Removes the given event listener from the list and returns it. It then // becomes the caller's responsibility to delete the listener. Returns // NULL if the listener is not found in the list. TestEventListener* Release(TestEventListener* listener); // Returns the standard listener responsible for the default console // output. Can be removed from the listeners list to shut down default // console output. Note that removing this object from the listener list // with Release transfers its ownership to the caller and makes this // function return NULL the next time. TestEventListener* default_result_printer() const { return default_result_printer_; } // Returns the standard listener responsible for the default XML output // controlled by the --gtest_output=xml flag. Can be removed from the // listeners list by users who want to shut down the default XML output // controlled by this flag and substitute it with custom one. Note that // removing this object from the listener list with Release transfers its // ownership to the caller and makes this function return NULL the next // time. TestEventListener* default_xml_generator() const { return default_xml_generator_; } private: friend class TestCase; friend class TestInfo; friend class internal::DefaultGlobalTestPartResultReporter; friend class internal::NoExecDeathTest; friend class internal::TestEventListenersAccessor; friend class internal::UnitTestImpl; // Returns repeater that broadcasts the TestEventListener events to all // subscribers. TestEventListener* repeater(); // Sets the default_result_printer attribute to the provided listener. // The listener is also added to the listener list and previous // default_result_printer is removed from it and deleted. The listener can // also be NULL in which case it will not be added to the list. Does // nothing if the previous and the current listener objects are the same. void SetDefaultResultPrinter(TestEventListener* listener); // Sets the default_xml_generator attribute to the provided listener. The // listener is also added to the listener list and previous // default_xml_generator is removed from it and deleted. The listener can // also be NULL in which case it will not be added to the list. Does // nothing if the previous and the current listener objects are the same. void SetDefaultXmlGenerator(TestEventListener* listener); // Controls whether events will be forwarded by the repeater to the // listeners in the list. bool EventForwardingEnabled() const; void SuppressEventForwarding(); // The actual list of listeners. internal::TestEventRepeater* repeater_; // Listener responsible for the standard result output. TestEventListener* default_result_printer_; // Listener responsible for the creation of the XML output file. TestEventListener* default_xml_generator_; // We disallow copying TestEventListeners. GTEST_DISALLOW_COPY_AND_ASSIGN_(TestEventListeners); }; // A UnitTest consists of a vector of TestCases. // // This is a singleton class. The only instance of UnitTest is // created when UnitTest::GetInstance() is first called. This // instance is never deleted. // // UnitTest is not copyable. // // This class is thread-safe as long as the methods are called // according to their specification. class GTEST_API_ UnitTest { public: // Gets the singleton UnitTest object. The first time this method // is called, a UnitTest object is constructed and returned. // Consecutive calls will return the same object. static UnitTest* GetInstance(); // Runs all tests in this UnitTest object and prints the result. // Returns 0 if successful, or 1 otherwise. // // This method can only be called from the main thread. // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. int Run() GTEST_MUST_USE_RESULT_; // Returns the working directory when the first TEST() or TEST_F() // was executed. The UnitTest object owns the string. const char* original_working_dir() const; // Returns the TestCase object for the test that's currently running, // or NULL if no test is running. const TestCase* current_test_case() const; // Returns the TestInfo object for the test that's currently running, // or NULL if no test is running. const TestInfo* current_test_info() const; // Returns the random seed used at the start of the current test run. int random_seed() const; #if GTEST_HAS_PARAM_TEST // Returns the ParameterizedTestCaseRegistry object used to keep track of // value-parameterized tests and instantiate and register them. // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. internal::ParameterizedTestCaseRegistry& parameterized_test_registry(); #endif // GTEST_HAS_PARAM_TEST // Gets the number of successful test cases. int successful_test_case_count() const; // Gets the number of failed test cases. int failed_test_case_count() const; // Gets the number of all test cases. int total_test_case_count() const; // Gets the number of all test cases that contain at least one test // that should run. int test_case_to_run_count() const; // Gets the number of successful tests. int successful_test_count() const; // Gets the number of failed tests. int failed_test_count() const; // Gets the number of disabled tests. int disabled_test_count() const; // Gets the number of all tests. int total_test_count() const; // Gets the number of tests that should run. int test_to_run_count() const; // Gets the elapsed time, in milliseconds. TimeInMillis elapsed_time() const; // Returns true iff the unit test passed (i.e. all test cases passed). bool Passed() const; // Returns true iff the unit test failed (i.e. some test case failed // or something outside of all tests failed). bool Failed() const; // Gets the i-th test case among all the test cases. i can range from 0 to // total_test_case_count() - 1. If i is not in that range, returns NULL. const TestCase* GetTestCase(int i) const; // Returns the list of event listeners that can be used to track events // inside Google Test. TestEventListeners& listeners(); private: // Registers and returns a global test environment. When a test // program is run, all global test environments will be set-up in // the order they were registered. After all tests in the program // have finished, all global test environments will be torn-down in // the *reverse* order they were registered. // // The UnitTest object takes ownership of the given environment. // // This method can only be called from the main thread. Environment* AddEnvironment(Environment* env); // Adds a TestPartResult to the current TestResult object. All // Google Test assertion macros (e.g. ASSERT_TRUE, EXPECT_EQ, etc) // eventually call this to report their results. The user code // should use the assertion macros instead of calling this directly. void AddTestPartResult(TestPartResult::Type result_type, const char* file_name, int line_number, const internal::String& message, const internal::String& os_stack_trace); // Adds a TestProperty to the current TestResult object. If the result already // contains a property with the same key, the value will be updated. void RecordPropertyForCurrentTest(const char* key, const char* value); // Gets the i-th test case among all the test cases. i can range from 0 to // total_test_case_count() - 1. If i is not in that range, returns NULL. TestCase* GetMutableTestCase(int i); // Accessors for the implementation object. internal::UnitTestImpl* impl() { return impl_; } const internal::UnitTestImpl* impl() const { return impl_; } // These classes and funcions are friends as they need to access private // members of UnitTest. friend class Test; friend class internal::AssertHelper; friend class internal::ScopedTrace; friend Environment* AddGlobalTestEnvironment(Environment* env); friend internal::UnitTestImpl* internal::GetUnitTestImpl(); friend void internal::ReportFailureInUnknownLocation( TestPartResult::Type result_type, const internal::String& message); // Creates an empty UnitTest. UnitTest(); // D'tor virtual ~UnitTest(); // Pushes a trace defined by SCOPED_TRACE() on to the per-thread // Google Test trace stack. void PushGTestTrace(const internal::TraceInfo& trace); // Pops a trace from the per-thread Google Test trace stack. void PopGTestTrace(); // Protects mutable state in *impl_. This is mutable as some const // methods need to lock it too. mutable internal::Mutex mutex_; // Opaque implementation object. This field is never changed once // the object is constructed. We don't mark it as const here, as // doing so will cause a warning in the constructor of UnitTest. // Mutable state in *impl_ is protected by mutex_. internal::UnitTestImpl* impl_; // We disallow copying UnitTest. GTEST_DISALLOW_COPY_AND_ASSIGN_(UnitTest); }; // A convenient wrapper for adding an environment for the test // program. // // You should call this before RUN_ALL_TESTS() is called, probably in // main(). If you use gtest_main, you need to call this before main() // starts for it to take effect. For example, you can define a global // variable like this: // // testing::Environment* const foo_env = // testing::AddGlobalTestEnvironment(new FooEnvironment); // // However, we strongly recommend you to write your own main() and // call AddGlobalTestEnvironment() there, as relying on initialization // of global variables makes the code harder to read and may cause // problems when you register multiple environments from different // translation units and the environments have dependencies among them // (remember that the compiler doesn't guarantee the order in which // global variables from different translation units are initialized). inline Environment* AddGlobalTestEnvironment(Environment* env) { return UnitTest::GetInstance()->AddEnvironment(env); } // Initializes Google Test. This must be called before calling // RUN_ALL_TESTS(). In particular, it parses a command line for the // flags that Google Test recognizes. Whenever a Google Test flag is // seen, it is removed from argv, and *argc is decremented. // // No value is returned. Instead, the Google Test flag variables are // updated. // // Calling the function for the second time has no user-visible effect. GTEST_API_ void InitGoogleTest(int* argc, char** argv); // This overloaded version can be used in Windows programs compiled in // UNICODE mode. GTEST_API_ void InitGoogleTest(int* argc, wchar_t** argv); namespace internal { // Formats a comparison assertion (e.g. ASSERT_EQ, EXPECT_LT, and etc) // operand to be used in a failure message. The type (but not value) // of the other operand may affect the format. This allows us to // print a char* as a raw pointer when it is compared against another // char*, and print it as a C string when it is compared against an // std::string object, for example. // // The default implementation ignores the type of the other operand. // Some specialized versions are used to handle formatting wide or // narrow C strings. // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. template String FormatForComparisonFailureMessage(const T1& value, const T2& /* other_operand */) { // C++Builder compiles this incorrectly if the namespace isn't explicitly // given. return ::testing::PrintToString(value); } // The helper function for {ASSERT|EXPECT}_EQ. template AssertionResult CmpHelperEQ(const char* expected_expression, const char* actual_expression, const T1& expected, const T2& actual) { #ifdef _MSC_VER # pragma warning(push) // Saves the current warning state. # pragma warning(disable:4389) // Temporarily disables warning on // signed/unsigned mismatch. #endif if (expected == actual) { return AssertionSuccess(); } #ifdef _MSC_VER # pragma warning(pop) // Restores the warning state. #endif return EqFailure(expected_expression, actual_expression, FormatForComparisonFailureMessage(expected, actual), FormatForComparisonFailureMessage(actual, expected), false); } // With this overloaded version, we allow anonymous enums to be used // in {ASSERT|EXPECT}_EQ when compiled with gcc 4, as anonymous enums // can be implicitly cast to BiggestInt. GTEST_API_ AssertionResult CmpHelperEQ(const char* expected_expression, const char* actual_expression, BiggestInt expected, BiggestInt actual); // The helper class for {ASSERT|EXPECT}_EQ. The template argument // lhs_is_null_literal is true iff the first argument to ASSERT_EQ() // is a null pointer literal. The following default implementation is // for lhs_is_null_literal being false. template class EqHelper { public: // This templatized version is for the general case. template static AssertionResult Compare(const char* expected_expression, const char* actual_expression, const T1& expected, const T2& actual) { return CmpHelperEQ(expected_expression, actual_expression, expected, actual); } // With this overloaded version, we allow anonymous enums to be used // in {ASSERT|EXPECT}_EQ when compiled with gcc 4, as anonymous // enums can be implicitly cast to BiggestInt. // // Even though its body looks the same as the above version, we // cannot merge the two, as it will make anonymous enums unhappy. static AssertionResult Compare(const char* expected_expression, const char* actual_expression, BiggestInt expected, BiggestInt actual) { return CmpHelperEQ(expected_expression, actual_expression, expected, actual); } }; // This specialization is used when the first argument to ASSERT_EQ() // is a null pointer literal, like NULL, false, or 0. template <> class EqHelper { public: // We define two overloaded versions of Compare(). The first // version will be picked when the second argument to ASSERT_EQ() is // NOT a pointer, e.g. ASSERT_EQ(0, AnIntFunction()) or // EXPECT_EQ(false, a_bool). template static AssertionResult Compare( const char* expected_expression, const char* actual_expression, const T1& expected, const T2& actual, // The following line prevents this overload from being considered if T2 // is not a pointer type. We need this because ASSERT_EQ(NULL, my_ptr) // expands to Compare("", "", NULL, my_ptr), which requires a conversion // to match the Secret* in the other overload, which would otherwise make // this template match better. typename EnableIf::value>::type* = 0) { return CmpHelperEQ(expected_expression, actual_expression, expected, actual); } // This version will be picked when the second argument to ASSERT_EQ() is a // pointer, e.g. ASSERT_EQ(NULL, a_pointer). template static AssertionResult Compare( const char* expected_expression, const char* actual_expression, // We used to have a second template parameter instead of Secret*. That // template parameter would deduce to 'long', making this a better match // than the first overload even without the first overload's EnableIf. // Unfortunately, gcc with -Wconversion-null warns when "passing NULL to // non-pointer argument" (even a deduced integral argument), so the old // implementation caused warnings in user code. Secret* /* expected (NULL) */, T* actual) { // We already know that 'expected' is a null pointer. return CmpHelperEQ(expected_expression, actual_expression, static_cast(NULL), actual); } }; // A macro for implementing the helper functions needed to implement // ASSERT_?? and EXPECT_??. It is here just to avoid copy-and-paste // of similar code. // // For each templatized helper function, we also define an overloaded // version for BiggestInt in order to reduce code bloat and allow // anonymous enums to be used with {ASSERT|EXPECT}_?? when compiled // with gcc 4. // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. #define GTEST_IMPL_CMP_HELPER_(op_name, op)\ template \ AssertionResult CmpHelper##op_name(const char* expr1, const char* expr2, \ const T1& val1, const T2& val2) {\ if (val1 op val2) {\ return AssertionSuccess();\ } else {\ return AssertionFailure() \ << "Expected: (" << expr1 << ") " #op " (" << expr2\ << "), actual: " << FormatForComparisonFailureMessage(val1, val2)\ << " vs " << FormatForComparisonFailureMessage(val2, val1);\ }\ }\ GTEST_API_ AssertionResult CmpHelper##op_name(\ const char* expr1, const char* expr2, BiggestInt val1, BiggestInt val2) // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. // Implements the helper function for {ASSERT|EXPECT}_NE GTEST_IMPL_CMP_HELPER_(NE, !=); // Implements the helper function for {ASSERT|EXPECT}_LE GTEST_IMPL_CMP_HELPER_(LE, <=); // Implements the helper function for {ASSERT|EXPECT}_LT GTEST_IMPL_CMP_HELPER_(LT, < ); // Implements the helper function for {ASSERT|EXPECT}_GE GTEST_IMPL_CMP_HELPER_(GE, >=); // Implements the helper function for {ASSERT|EXPECT}_GT GTEST_IMPL_CMP_HELPER_(GT, > ); #undef GTEST_IMPL_CMP_HELPER_ // The helper function for {ASSERT|EXPECT}_STREQ. // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. GTEST_API_ AssertionResult CmpHelperSTREQ(const char* expected_expression, const char* actual_expression, const char* expected, const char* actual); // The helper function for {ASSERT|EXPECT}_STRCASEEQ. // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. GTEST_API_ AssertionResult CmpHelperSTRCASEEQ(const char* expected_expression, const char* actual_expression, const char* expected, const char* actual); // The helper function for {ASSERT|EXPECT}_STRNE. // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. GTEST_API_ AssertionResult CmpHelperSTRNE(const char* s1_expression, const char* s2_expression, const char* s1, const char* s2); // The helper function for {ASSERT|EXPECT}_STRCASENE. // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. GTEST_API_ AssertionResult CmpHelperSTRCASENE(const char* s1_expression, const char* s2_expression, const char* s1, const char* s2); // Helper function for *_STREQ on wide strings. // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. GTEST_API_ AssertionResult CmpHelperSTREQ(const char* expected_expression, const char* actual_expression, const wchar_t* expected, const wchar_t* actual); // Helper function for *_STRNE on wide strings. // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. GTEST_API_ AssertionResult CmpHelperSTRNE(const char* s1_expression, const char* s2_expression, const wchar_t* s1, const wchar_t* s2); } // namespace internal // IsSubstring() and IsNotSubstring() are intended to be used as the // first argument to {EXPECT,ASSERT}_PRED_FORMAT2(), not by // themselves. They check whether needle is a substring of haystack // (NULL is considered a substring of itself only), and return an // appropriate error message when they fail. // // The {needle,haystack}_expr arguments are the stringified // expressions that generated the two real arguments. GTEST_API_ AssertionResult IsSubstring( const char* needle_expr, const char* haystack_expr, const char* needle, const char* haystack); GTEST_API_ AssertionResult IsSubstring( const char* needle_expr, const char* haystack_expr, const wchar_t* needle, const wchar_t* haystack); GTEST_API_ AssertionResult IsNotSubstring( const char* needle_expr, const char* haystack_expr, const char* needle, const char* haystack); GTEST_API_ AssertionResult IsNotSubstring( const char* needle_expr, const char* haystack_expr, const wchar_t* needle, const wchar_t* haystack); GTEST_API_ AssertionResult IsSubstring( const char* needle_expr, const char* haystack_expr, const ::std::string& needle, const ::std::string& haystack); GTEST_API_ AssertionResult IsNotSubstring( const char* needle_expr, const char* haystack_expr, const ::std::string& needle, const ::std::string& haystack); #if GTEST_HAS_STD_WSTRING GTEST_API_ AssertionResult IsSubstring( const char* needle_expr, const char* haystack_expr, const ::std::wstring& needle, const ::std::wstring& haystack); GTEST_API_ AssertionResult IsNotSubstring( const char* needle_expr, const char* haystack_expr, const ::std::wstring& needle, const ::std::wstring& haystack); #endif // GTEST_HAS_STD_WSTRING namespace internal { // Helper template function for comparing floating-points. // // Template parameter: // // RawType: the raw floating-point type (either float or double) // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. template AssertionResult CmpHelperFloatingPointEQ(const char* expected_expression, const char* actual_expression, RawType expected, RawType actual) { const FloatingPoint lhs(expected), rhs(actual); if (lhs.AlmostEquals(rhs)) { return AssertionSuccess(); } ::std::stringstream expected_ss; expected_ss << std::setprecision(std::numeric_limits::digits10 + 2) << expected; ::std::stringstream actual_ss; actual_ss << std::setprecision(std::numeric_limits::digits10 + 2) << actual; return EqFailure(expected_expression, actual_expression, StringStreamToString(&expected_ss), StringStreamToString(&actual_ss), false); } // Helper function for implementing ASSERT_NEAR. // // INTERNAL IMPLEMENTATION - DO NOT USE IN A USER PROGRAM. GTEST_API_ AssertionResult DoubleNearPredFormat(const char* expr1, const char* expr2, const char* abs_error_expr, double val1, double val2, double abs_error); // INTERNAL IMPLEMENTATION - DO NOT USE IN USER CODE. // A class that enables one to stream messages to assertion macros class GTEST_API_ AssertHelper { public: // Constructor. AssertHelper(TestPartResult::Type type, const char* file, int line, const char* message); ~AssertHelper(); // Message assignment is a semantic trick to enable assertion // streaming; see the GTEST_MESSAGE_ macro below. void operator=(const Message& message) const; private: // We put our data in a struct so that the size of the AssertHelper class can // be as small as possible. This is important because gcc is incapable of // re-using stack space even for temporary variables, so every EXPECT_EQ // reserves stack space for another AssertHelper. struct AssertHelperData { AssertHelperData(TestPartResult::Type t, const char* srcfile, int line_num, const char* msg) : type(t), file(srcfile), line(line_num), message(msg) { } TestPartResult::Type const type; const char* const file; int const line; String const message; private: GTEST_DISALLOW_COPY_AND_ASSIGN_(AssertHelperData); }; AssertHelperData* const data_; GTEST_DISALLOW_COPY_AND_ASSIGN_(AssertHelper); }; } // namespace internal #if GTEST_HAS_PARAM_TEST // The pure interface class that all value-parameterized tests inherit from. // A value-parameterized class must inherit from both ::testing::Test and // ::testing::WithParamInterface. In most cases that just means inheriting // from ::testing::TestWithParam, but more complicated test hierarchies // may need to inherit from Test and WithParamInterface at different levels. // // This interface has support for accessing the test parameter value via // the GetParam() method. // // Use it with one of the parameter generator defining functions, like Range(), // Values(), ValuesIn(), Bool(), and Combine(). // // class FooTest : public ::testing::TestWithParam { // protected: // FooTest() { // // Can use GetParam() here. // } // virtual ~FooTest() { // // Can use GetParam() here. // } // virtual void SetUp() { // // Can use GetParam() here. // } // virtual void TearDown { // // Can use GetParam() here. // } // }; // TEST_P(FooTest, DoesBar) { // // Can use GetParam() method here. // Foo foo; // ASSERT_TRUE(foo.DoesBar(GetParam())); // } // INSTANTIATE_TEST_CASE_P(OneToTenRange, FooTest, ::testing::Range(1, 10)); template class WithParamInterface { public: typedef T ParamType; virtual ~WithParamInterface() {} // The current parameter value. Is also available in the test fixture's // constructor. This member function is non-static, even though it only // references static data, to reduce the opportunity for incorrect uses // like writing 'WithParamInterface::GetParam()' for a test that // uses a fixture whose parameter type is int. const ParamType& GetParam() const { return *parameter_; } private: // Sets parameter value. The caller is responsible for making sure the value // remains alive and unchanged throughout the current test. static void SetParam(const ParamType* parameter) { parameter_ = parameter; } // Static value used for accessing parameter during a test lifetime. static const ParamType* parameter_; // TestClass must be a subclass of WithParamInterface and Test. template friend class internal::ParameterizedTestFactory; }; template const T* WithParamInterface::parameter_ = NULL; // Most value-parameterized classes can ignore the existence of // WithParamInterface, and can just inherit from ::testing::TestWithParam. template class TestWithParam : public Test, public WithParamInterface { }; #endif // GTEST_HAS_PARAM_TEST // Macros for indicating success/failure in test code. // ADD_FAILURE unconditionally adds a failure to the current test. // SUCCEED generates a success - it doesn't automatically make the // current test successful, as a test is only successful when it has // no failure. // // EXPECT_* verifies that a certain condition is satisfied. If not, // it behaves like ADD_FAILURE. In particular: // // EXPECT_TRUE verifies that a Boolean condition is true. // EXPECT_FALSE verifies that a Boolean condition is false. // // FAIL and ASSERT_* are similar to ADD_FAILURE and EXPECT_*, except // that they will also abort the current function on failure. People // usually want the fail-fast behavior of FAIL and ASSERT_*, but those // writing data-driven tests often find themselves using ADD_FAILURE // and EXPECT_* more. // // Examples: // // EXPECT_TRUE(server.StatusIsOK()); // ASSERT_FALSE(server.HasPendingRequest(port)) // << "There are still pending requests " << "on port " << port; // Generates a nonfatal failure with a generic message. #define ADD_FAILURE() GTEST_NONFATAL_FAILURE_("Failed") // Generates a nonfatal failure at the given source file location with // a generic message. #define ADD_FAILURE_AT(file, line) \ GTEST_MESSAGE_AT_(file, line, "Failed", \ ::testing::TestPartResult::kNonFatalFailure) // Generates a fatal failure with a generic message. #define GTEST_FAIL() GTEST_FATAL_FAILURE_("Failed") // Define this macro to 1 to omit the definition of FAIL(), which is a // generic name and clashes with some other libraries. #if !GTEST_DONT_DEFINE_FAIL # define FAIL() GTEST_FAIL() #endif // Generates a success with a generic message. #define GTEST_SUCCEED() GTEST_SUCCESS_("Succeeded") // Define this macro to 1 to omit the definition of SUCCEED(), which // is a generic name and clashes with some other libraries. #if !GTEST_DONT_DEFINE_SUCCEED # define SUCCEED() GTEST_SUCCEED() #endif // Macros for testing exceptions. // // * {ASSERT|EXPECT}_THROW(statement, expected_exception): // Tests that the statement throws the expected exception. // * {ASSERT|EXPECT}_NO_THROW(statement): // Tests that the statement doesn't throw any exception. // * {ASSERT|EXPECT}_ANY_THROW(statement): // Tests that the statement throws an exception. #define EXPECT_THROW(statement, expected_exception) \ GTEST_TEST_THROW_(statement, expected_exception, GTEST_NONFATAL_FAILURE_) #define EXPECT_NO_THROW(statement) \ GTEST_TEST_NO_THROW_(statement, GTEST_NONFATAL_FAILURE_) #define EXPECT_ANY_THROW(statement) \ GTEST_TEST_ANY_THROW_(statement, GTEST_NONFATAL_FAILURE_) #define ASSERT_THROW(statement, expected_exception) \ GTEST_TEST_THROW_(statement, expected_exception, GTEST_FATAL_FAILURE_) #define ASSERT_NO_THROW(statement) \ GTEST_TEST_NO_THROW_(statement, GTEST_FATAL_FAILURE_) #define ASSERT_ANY_THROW(statement) \ GTEST_TEST_ANY_THROW_(statement, GTEST_FATAL_FAILURE_) // Boolean assertions. Condition can be either a Boolean expression or an // AssertionResult. For more information on how to use AssertionResult with // these macros see comments on that class. #define EXPECT_TRUE(condition) \ GTEST_TEST_BOOLEAN_(condition, #condition, false, true, \ GTEST_NONFATAL_FAILURE_) #define EXPECT_FALSE(condition) \ GTEST_TEST_BOOLEAN_(!(condition), #condition, true, false, \ GTEST_NONFATAL_FAILURE_) #define ASSERT_TRUE(condition) \ GTEST_TEST_BOOLEAN_(condition, #condition, false, true, \ GTEST_FATAL_FAILURE_) #define ASSERT_FALSE(condition) \ GTEST_TEST_BOOLEAN_(!(condition), #condition, true, false, \ GTEST_FATAL_FAILURE_) // Includes the auto-generated header that implements a family of // generic predicate assertion macros. // Copyright 2006, Google Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google Inc. nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // This file is AUTOMATICALLY GENERATED on 09/24/2010 by command // 'gen_gtest_pred_impl.py 5'. DO NOT EDIT BY HAND! // // Implements a family of generic predicate assertion macros. #ifndef GTEST_INCLUDE_GTEST_GTEST_PRED_IMPL_H_ #define GTEST_INCLUDE_GTEST_GTEST_PRED_IMPL_H_ // Makes sure this header is not included before gtest.h. #ifndef GTEST_INCLUDE_GTEST_GTEST_H_ # error Do not include gtest_pred_impl.h directly. Include gtest.h instead. #endif // GTEST_INCLUDE_GTEST_GTEST_H_ // This header implements a family of generic predicate assertion // macros: // // ASSERT_PRED_FORMAT1(pred_format, v1) // ASSERT_PRED_FORMAT2(pred_format, v1, v2) // ... // // where pred_format is a function or functor that takes n (in the // case of ASSERT_PRED_FORMATn) values and their source expression // text, and returns a testing::AssertionResult. See the definition // of ASSERT_EQ in gtest.h for an example. // // If you don't care about formatting, you can use the more // restrictive version: // // ASSERT_PRED1(pred, v1) // ASSERT_PRED2(pred, v1, v2) // ... // // where pred is an n-ary function or functor that returns bool, // and the values v1, v2, ..., must support the << operator for // streaming to std::ostream. // // We also define the EXPECT_* variations. // // For now we only support predicates whose arity is at most 5. // Please email googletestframework@googlegroups.com if you need // support for higher arities. // GTEST_ASSERT_ is the basic statement to which all of the assertions // in this file reduce. Don't use this in your code. #define GTEST_ASSERT_(expression, on_failure) \ GTEST_AMBIGUOUS_ELSE_BLOCKER_ \ if (const ::testing::AssertionResult gtest_ar = (expression)) \ ; \ else \ on_failure(gtest_ar.failure_message()) // Helper function for implementing {EXPECT|ASSERT}_PRED1. Don't use // this in your code. template AssertionResult AssertPred1Helper(const char* pred_text, const char* e1, Pred pred, const T1& v1) { if (pred(v1)) return AssertionSuccess(); return AssertionFailure() << pred_text << "(" << e1 << ") evaluates to false, where" << "\n" << e1 << " evaluates to " << v1; } // Internal macro for implementing {EXPECT|ASSERT}_PRED_FORMAT1. // Don't use this in your code. #define GTEST_PRED_FORMAT1_(pred_format, v1, on_failure)\ GTEST_ASSERT_(pred_format(#v1, v1),\ on_failure) // Internal macro for implementing {EXPECT|ASSERT}_PRED1. Don't use // this in your code. #define GTEST_PRED1_(pred, v1, on_failure)\ GTEST_ASSERT_(::testing::AssertPred1Helper(#pred, \ #v1, \ pred, \ v1), on_failure) // Unary predicate assertion macros. #define EXPECT_PRED_FORMAT1(pred_format, v1) \ GTEST_PRED_FORMAT1_(pred_format, v1, GTEST_NONFATAL_FAILURE_) #define EXPECT_PRED1(pred, v1) \ GTEST_PRED1_(pred, v1, GTEST_NONFATAL_FAILURE_) #define ASSERT_PRED_FORMAT1(pred_format, v1) \ GTEST_PRED_FORMAT1_(pred_format, v1, GTEST_FATAL_FAILURE_) #define ASSERT_PRED1(pred, v1) \ GTEST_PRED1_(pred, v1, GTEST_FATAL_FAILURE_) // Helper function for implementing {EXPECT|ASSERT}_PRED2. Don't use // this in your code. template AssertionResult AssertPred2Helper(const char* pred_text, const char* e1, const char* e2, Pred pred, const T1& v1, const T2& v2) { if (pred(v1, v2)) return AssertionSuccess(); return AssertionFailure() << pred_text << "(" << e1 << ", " << e2 << ") evaluates to false, where" << "\n" << e1 << " evaluates to " << v1 << "\n" << e2 << " evaluates to " << v2; } // Internal macro for implementing {EXPECT|ASSERT}_PRED_FORMAT2. // Don't use this in your code. #define GTEST_PRED_FORMAT2_(pred_format, v1, v2, on_failure)\ GTEST_ASSERT_(pred_format(#v1, #v2, v1, v2),\ on_failure) // Internal macro for implementing {EXPECT|ASSERT}_PRED2. Don't use // this in your code. #define GTEST_PRED2_(pred, v1, v2, on_failure)\ GTEST_ASSERT_(::testing::AssertPred2Helper(#pred, \ #v1, \ #v2, \ pred, \ v1, \ v2), on_failure) // Binary predicate assertion macros. #define EXPECT_PRED_FORMAT2(pred_format, v1, v2) \ GTEST_PRED_FORMAT2_(pred_format, v1, v2, GTEST_NONFATAL_FAILURE_) #define EXPECT_PRED2(pred, v1, v2) \ GTEST_PRED2_(pred, v1, v2, GTEST_NONFATAL_FAILURE_) #define ASSERT_PRED_FORMAT2(pred_format, v1, v2) \ GTEST_PRED_FORMAT2_(pred_format, v1, v2, GTEST_FATAL_FAILURE_) #define ASSERT_PRED2(pred, v1, v2) \ GTEST_PRED2_(pred, v1, v2, GTEST_FATAL_FAILURE_) // Helper function for implementing {EXPECT|ASSERT}_PRED3. Don't use // this in your code. template AssertionResult AssertPred3Helper(const char* pred_text, const char* e1, const char* e2, const char* e3, Pred pred, const T1& v1, const T2& v2, const T3& v3) { if (pred(v1, v2, v3)) return AssertionSuccess(); return AssertionFailure() << pred_text << "(" << e1 << ", " << e2 << ", " << e3 << ") evaluates to false, where" << "\n" << e1 << " evaluates to " << v1 << "\n" << e2 << " evaluates to " << v2 << "\n" << e3 << " evaluates to " << v3; } // Internal macro for implementing {EXPECT|ASSERT}_PRED_FORMAT3. // Don't use this in your code. #define GTEST_PRED_FORMAT3_(pred_format, v1, v2, v3, on_failure)\ GTEST_ASSERT_(pred_format(#v1, #v2, #v3, v1, v2, v3),\ on_failure) // Internal macro for implementing {EXPECT|ASSERT}_PRED3. Don't use // this in your code. #define GTEST_PRED3_(pred, v1, v2, v3, on_failure)\ GTEST_ASSERT_(::testing::AssertPred3Helper(#pred, \ #v1, \ #v2, \ #v3, \ pred, \ v1, \ v2, \ v3), on_failure) // Ternary predicate assertion macros. #define EXPECT_PRED_FORMAT3(pred_format, v1, v2, v3) \ GTEST_PRED_FORMAT3_(pred_format, v1, v2, v3, GTEST_NONFATAL_FAILURE_) #define EXPECT_PRED3(pred, v1, v2, v3) \ GTEST_PRED3_(pred, v1, v2, v3, GTEST_NONFATAL_FAILURE_) #define ASSERT_PRED_FORMAT3(pred_format, v1, v2, v3) \ GTEST_PRED_FORMAT3_(pred_format, v1, v2, v3, GTEST_FATAL_FAILURE_) #define ASSERT_PRED3(pred, v1, v2, v3) \ GTEST_PRED3_(pred, v1, v2, v3, GTEST_FATAL_FAILURE_) // Helper function for implementing {EXPECT|ASSERT}_PRED4. Don't use // this in your code. template AssertionResult AssertPred4Helper(const char* pred_text, const char* e1, const char* e2, const char* e3, const char* e4, Pred pred, const T1& v1, const T2& v2, const T3& v3, const T4& v4) { if (pred(v1, v2, v3, v4)) return AssertionSuccess(); return AssertionFailure() << pred_text << "(" << e1 << ", " << e2 << ", " << e3 << ", " << e4 << ") evaluates to false, where" << "\n" << e1 << " evaluates to " << v1 << "\n" << e2 << " evaluates to " << v2 << "\n" << e3 << " evaluates to " << v3 << "\n" << e4 << " evaluates to " << v4; } // Internal macro for implementing {EXPECT|ASSERT}_PRED_FORMAT4. // Don't use this in your code. #define GTEST_PRED_FORMAT4_(pred_format, v1, v2, v3, v4, on_failure)\ GTEST_ASSERT_(pred_format(#v1, #v2, #v3, #v4, v1, v2, v3, v4),\ on_failure) // Internal macro for implementing {EXPECT|ASSERT}_PRED4. Don't use // this in your code. #define GTEST_PRED4_(pred, v1, v2, v3, v4, on_failure)\ GTEST_ASSERT_(::testing::AssertPred4Helper(#pred, \ #v1, \ #v2, \ #v3, \ #v4, \ pred, \ v1, \ v2, \ v3, \ v4), on_failure) // 4-ary predicate assertion macros. #define EXPECT_PRED_FORMAT4(pred_format, v1, v2, v3, v4) \ GTEST_PRED_FORMAT4_(pred_format, v1, v2, v3, v4, GTEST_NONFATAL_FAILURE_) #define EXPECT_PRED4(pred, v1, v2, v3, v4) \ GTEST_PRED4_(pred, v1, v2, v3, v4, GTEST_NONFATAL_FAILURE_) #define ASSERT_PRED_FORMAT4(pred_format, v1, v2, v3, v4) \ GTEST_PRED_FORMAT4_(pred_format, v1, v2, v3, v4, GTEST_FATAL_FAILURE_) #define ASSERT_PRED4(pred, v1, v2, v3, v4) \ GTEST_PRED4_(pred, v1, v2, v3, v4, GTEST_FATAL_FAILURE_) // Helper function for implementing {EXPECT|ASSERT}_PRED5. Don't use // this in your code. template AssertionResult AssertPred5Helper(const char* pred_text, const char* e1, const char* e2, const char* e3, const char* e4, const char* e5, Pred pred, const T1& v1, const T2& v2, const T3& v3, const T4& v4, const T5& v5) { if (pred(v1, v2, v3, v4, v5)) return AssertionSuccess(); return AssertionFailure() << pred_text << "(" << e1 << ", " << e2 << ", " << e3 << ", " << e4 << ", " << e5 << ") evaluates to false, where" << "\n" << e1 << " evaluates to " << v1 << "\n" << e2 << " evaluates to " << v2 << "\n" << e3 << " evaluates to " << v3 << "\n" << e4 << " evaluates to " << v4 << "\n" << e5 << " evaluates to " << v5; } // Internal macro for implementing {EXPECT|ASSERT}_PRED_FORMAT5. // Don't use this in your code. #define GTEST_PRED_FORMAT5_(pred_format, v1, v2, v3, v4, v5, on_failure)\ GTEST_ASSERT_(pred_format(#v1, #v2, #v3, #v4, #v5, v1, v2, v3, v4, v5),\ on_failure) // Internal macro for implementing {EXPECT|ASSERT}_PRED5. Don't use // this in your code. #define GTEST_PRED5_(pred, v1, v2, v3, v4, v5, on_failure)\ GTEST_ASSERT_(::testing::AssertPred5Helper(#pred, \ #v1, \ #v2, \ #v3, \ #v4, \ #v5, \ pred, \ v1, \ v2, \ v3, \ v4, \ v5), on_failure) // 5-ary predicate assertion macros. #define EXPECT_PRED_FORMAT5(pred_format, v1, v2, v3, v4, v5) \ GTEST_PRED_FORMAT5_(pred_format, v1, v2, v3, v4, v5, GTEST_NONFATAL_FAILURE_) #define EXPECT_PRED5(pred, v1, v2, v3, v4, v5) \ GTEST_PRED5_(pred, v1, v2, v3, v4, v5, GTEST_NONFATAL_FAILURE_) #define ASSERT_PRED_FORMAT5(pred_format, v1, v2, v3, v4, v5) \ GTEST_PRED_FORMAT5_(pred_format, v1, v2, v3, v4, v5, GTEST_FATAL_FAILURE_) #define ASSERT_PRED5(pred, v1, v2, v3, v4, v5) \ GTEST_PRED5_(pred, v1, v2, v3, v4, v5, GTEST_FATAL_FAILURE_) #endif // GTEST_INCLUDE_GTEST_GTEST_PRED_IMPL_H_ // Macros for testing equalities and inequalities. // // * {ASSERT|EXPECT}_EQ(expected, actual): Tests that expected == actual // * {ASSERT|EXPECT}_NE(v1, v2): Tests that v1 != v2 // * {ASSERT|EXPECT}_LT(v1, v2): Tests that v1 < v2 // * {ASSERT|EXPECT}_LE(v1, v2): Tests that v1 <= v2 // * {ASSERT|EXPECT}_GT(v1, v2): Tests that v1 > v2 // * {ASSERT|EXPECT}_GE(v1, v2): Tests that v1 >= v2 // // When they are not, Google Test prints both the tested expressions and // their actual values. The values must be compatible built-in types, // or you will get a compiler error. By "compatible" we mean that the // values can be compared by the respective operator. // // Note: // // 1. It is possible to make a user-defined type work with // {ASSERT|EXPECT}_??(), but that requires overloading the // comparison operators and is thus discouraged by the Google C++ // Usage Guide. Therefore, you are advised to use the // {ASSERT|EXPECT}_TRUE() macro to assert that two objects are // equal. // // 2. The {ASSERT|EXPECT}_??() macros do pointer comparisons on // pointers (in particular, C strings). Therefore, if you use it // with two C strings, you are testing how their locations in memory // are related, not how their content is related. To compare two C // strings by content, use {ASSERT|EXPECT}_STR*(). // // 3. {ASSERT|EXPECT}_EQ(expected, actual) is preferred to // {ASSERT|EXPECT}_TRUE(expected == actual), as the former tells you // what the actual value is when it fails, and similarly for the // other comparisons. // // 4. Do not depend on the order in which {ASSERT|EXPECT}_??() // evaluate their arguments, which is undefined. // // 5. These macros evaluate their arguments exactly once. // // Examples: // // EXPECT_NE(5, Foo()); // EXPECT_EQ(NULL, a_pointer); // ASSERT_LT(i, array_size); // ASSERT_GT(records.size(), 0) << "There is no record left."; #define EXPECT_EQ(expected, actual) \ EXPECT_PRED_FORMAT2(::testing::internal:: \ EqHelper::Compare, \ expected, actual) #define EXPECT_NE(expected, actual) \ EXPECT_PRED_FORMAT2(::testing::internal::CmpHelperNE, expected, actual) #define EXPECT_LE(val1, val2) \ EXPECT_PRED_FORMAT2(::testing::internal::CmpHelperLE, val1, val2) #define EXPECT_LT(val1, val2) \ EXPECT_PRED_FORMAT2(::testing::internal::CmpHelperLT, val1, val2) #define EXPECT_GE(val1, val2) \ EXPECT_PRED_FORMAT2(::testing::internal::CmpHelperGE, val1, val2) #define EXPECT_GT(val1, val2) \ EXPECT_PRED_FORMAT2(::testing::internal::CmpHelperGT, val1, val2) #define GTEST_ASSERT_EQ(expected, actual) \ ASSERT_PRED_FORMAT2(::testing::internal:: \ EqHelper::Compare, \ expected, actual) #define GTEST_ASSERT_NE(val1, val2) \ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperNE, val1, val2) #define GTEST_ASSERT_LE(val1, val2) \ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperLE, val1, val2) #define GTEST_ASSERT_LT(val1, val2) \ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperLT, val1, val2) #define GTEST_ASSERT_GE(val1, val2) \ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperGE, val1, val2) #define GTEST_ASSERT_GT(val1, val2) \ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperGT, val1, val2) // Define macro GTEST_DONT_DEFINE_ASSERT_XY to 1 to omit the definition of // ASSERT_XY(), which clashes with some users' own code. #if !GTEST_DONT_DEFINE_ASSERT_EQ # define ASSERT_EQ(val1, val2) GTEST_ASSERT_EQ(val1, val2) #endif #if !GTEST_DONT_DEFINE_ASSERT_NE # define ASSERT_NE(val1, val2) GTEST_ASSERT_NE(val1, val2) #endif #if !GTEST_DONT_DEFINE_ASSERT_LE # define ASSERT_LE(val1, val2) GTEST_ASSERT_LE(val1, val2) #endif #if !GTEST_DONT_DEFINE_ASSERT_LT # define ASSERT_LT(val1, val2) GTEST_ASSERT_LT(val1, val2) #endif #if !GTEST_DONT_DEFINE_ASSERT_GE # define ASSERT_GE(val1, val2) GTEST_ASSERT_GE(val1, val2) #endif #if !GTEST_DONT_DEFINE_ASSERT_GT # define ASSERT_GT(val1, val2) GTEST_ASSERT_GT(val1, val2) #endif // C String Comparisons. All tests treat NULL and any non-NULL string // as different. Two NULLs are equal. // // * {ASSERT|EXPECT}_STREQ(s1, s2): Tests that s1 == s2 // * {ASSERT|EXPECT}_STRNE(s1, s2): Tests that s1 != s2 // * {ASSERT|EXPECT}_STRCASEEQ(s1, s2): Tests that s1 == s2, ignoring case // * {ASSERT|EXPECT}_STRCASENE(s1, s2): Tests that s1 != s2, ignoring case // // For wide or narrow string objects, you can use the // {ASSERT|EXPECT}_??() macros. // // Don't depend on the order in which the arguments are evaluated, // which is undefined. // // These macros evaluate their arguments exactly once. #define EXPECT_STREQ(expected, actual) \ EXPECT_PRED_FORMAT2(::testing::internal::CmpHelperSTREQ, expected, actual) #define EXPECT_STRNE(s1, s2) \ EXPECT_PRED_FORMAT2(::testing::internal::CmpHelperSTRNE, s1, s2) #define EXPECT_STRCASEEQ(expected, actual) \ EXPECT_PRED_FORMAT2(::testing::internal::CmpHelperSTRCASEEQ, expected, actual) #define EXPECT_STRCASENE(s1, s2)\ EXPECT_PRED_FORMAT2(::testing::internal::CmpHelperSTRCASENE, s1, s2) #define ASSERT_STREQ(expected, actual) \ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperSTREQ, expected, actual) #define ASSERT_STRNE(s1, s2) \ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperSTRNE, s1, s2) #define ASSERT_STRCASEEQ(expected, actual) \ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperSTRCASEEQ, expected, actual) #define ASSERT_STRCASENE(s1, s2)\ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperSTRCASENE, s1, s2) // Macros for comparing floating-point numbers. // // * {ASSERT|EXPECT}_FLOAT_EQ(expected, actual): // Tests that two float values are almost equal. // * {ASSERT|EXPECT}_DOUBLE_EQ(expected, actual): // Tests that two double values are almost equal. // * {ASSERT|EXPECT}_NEAR(v1, v2, abs_error): // Tests that v1 and v2 are within the given distance to each other. // // Google Test uses ULP-based comparison to automatically pick a default // error bound that is appropriate for the operands. See the // FloatingPoint template class in gtest-internal.h if you are // interested in the implementation details. #define EXPECT_FLOAT_EQ(expected, actual)\ EXPECT_PRED_FORMAT2(::testing::internal::CmpHelperFloatingPointEQ, \ expected, actual) #define EXPECT_DOUBLE_EQ(expected, actual)\ EXPECT_PRED_FORMAT2(::testing::internal::CmpHelperFloatingPointEQ, \ expected, actual) #define ASSERT_FLOAT_EQ(expected, actual)\ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperFloatingPointEQ, \ expected, actual) #define ASSERT_DOUBLE_EQ(expected, actual)\ ASSERT_PRED_FORMAT2(::testing::internal::CmpHelperFloatingPointEQ, \ expected, actual) #define EXPECT_NEAR(val1, val2, abs_error)\ EXPECT_PRED_FORMAT3(::testing::internal::DoubleNearPredFormat, \ val1, val2, abs_error) #define ASSERT_NEAR(val1, val2, abs_error)\ ASSERT_PRED_FORMAT3(::testing::internal::DoubleNearPredFormat, \ val1, val2, abs_error) // These predicate format functions work on floating-point values, and // can be used in {ASSERT|EXPECT}_PRED_FORMAT2*(), e.g. // // EXPECT_PRED_FORMAT2(testing::DoubleLE, Foo(), 5.0); // Asserts that val1 is less than, or almost equal to, val2. Fails // otherwise. In particular, it fails if either val1 or val2 is NaN. GTEST_API_ AssertionResult FloatLE(const char* expr1, const char* expr2, float val1, float val2); GTEST_API_ AssertionResult DoubleLE(const char* expr1, const char* expr2, double val1, double val2); #if GTEST_OS_WINDOWS // Macros that test for HRESULT failure and success, these are only useful // on Windows, and rely on Windows SDK macros and APIs to compile. // // * {ASSERT|EXPECT}_HRESULT_{SUCCEEDED|FAILED}(expr) // // When expr unexpectedly fails or succeeds, Google Test prints the // expected result and the actual result with both a human-readable // string representation of the error, if available, as well as the // hex result code. # define EXPECT_HRESULT_SUCCEEDED(expr) \ EXPECT_PRED_FORMAT1(::testing::internal::IsHRESULTSuccess, (expr)) # define ASSERT_HRESULT_SUCCEEDED(expr) \ ASSERT_PRED_FORMAT1(::testing::internal::IsHRESULTSuccess, (expr)) # define EXPECT_HRESULT_FAILED(expr) \ EXPECT_PRED_FORMAT1(::testing::internal::IsHRESULTFailure, (expr)) # define ASSERT_HRESULT_FAILED(expr) \ ASSERT_PRED_FORMAT1(::testing::internal::IsHRESULTFailure, (expr)) #endif // GTEST_OS_WINDOWS // Macros that execute statement and check that it doesn't generate new fatal // failures in the current thread. // // * {ASSERT|EXPECT}_NO_FATAL_FAILURE(statement); // // Examples: // // EXPECT_NO_FATAL_FAILURE(Process()); // ASSERT_NO_FATAL_FAILURE(Process()) << "Process() failed"; // #define ASSERT_NO_FATAL_FAILURE(statement) \ GTEST_TEST_NO_FATAL_FAILURE_(statement, GTEST_FATAL_FAILURE_) #define EXPECT_NO_FATAL_FAILURE(statement) \ GTEST_TEST_NO_FATAL_FAILURE_(statement, GTEST_NONFATAL_FAILURE_) // Causes a trace (including the source file path, the current line // number, and the given message) to be included in every test failure // message generated by code in the current scope. The effect is // undone when the control leaves the current scope. // // The message argument can be anything streamable to std::ostream. // // In the implementation, we include the current line number as part // of the dummy variable name, thus allowing multiple SCOPED_TRACE()s // to appear in the same block - as long as they are on different // lines. #define SCOPED_TRACE(message) \ ::testing::internal::ScopedTrace GTEST_CONCAT_TOKEN_(gtest_trace_, __LINE__)(\ __FILE__, __LINE__, ::testing::Message() << (message)) // Compile-time assertion for type equality. // StaticAssertTypeEq() compiles iff type1 and type2 are // the same type. The value it returns is not interesting. // // Instead of making StaticAssertTypeEq a class template, we make it a // function template that invokes a helper class template. This // prevents a user from misusing StaticAssertTypeEq by // defining objects of that type. // // CAVEAT: // // When used inside a method of a class template, // StaticAssertTypeEq() is effective ONLY IF the method is // instantiated. For example, given: // // template class Foo { // public: // void Bar() { testing::StaticAssertTypeEq(); } // }; // // the code: // // void Test1() { Foo foo; } // // will NOT generate a compiler error, as Foo::Bar() is never // actually instantiated. Instead, you need: // // void Test2() { Foo foo; foo.Bar(); } // // to cause a compiler error. template bool StaticAssertTypeEq() { (void)internal::StaticAssertTypeEqHelper(); return true; } // Defines a test. // // The first parameter is the name of the test case, and the second // parameter is the name of the test within the test case. // // The convention is to end the test case name with "Test". For // example, a test case for the Foo class can be named FooTest. // // The user should put his test code between braces after using this // macro. Example: // // TEST(FooTest, InitializesCorrectly) { // Foo foo; // EXPECT_TRUE(foo.StatusIsOK()); // } // Note that we call GetTestTypeId() instead of GetTypeId< // ::testing::Test>() here to get the type ID of testing::Test. This // is to work around a suspected linker bug when using Google Test as // a framework on Mac OS X. The bug causes GetTypeId< // ::testing::Test>() to return different values depending on whether // the call is from the Google Test framework itself or from user test // code. GetTestTypeId() is guaranteed to always return the same // value, as it always calls GetTypeId<>() from the Google Test // framework. #define GTEST_TEST(test_case_name, test_name)\ GTEST_TEST_(test_case_name, test_name, \ ::testing::Test, ::testing::internal::GetTestTypeId()) // Define this macro to 1 to omit the definition of TEST(), which // is a generic name and clashes with some other libraries. #if !GTEST_DONT_DEFINE_TEST # define TEST(test_case_name, test_name) GTEST_TEST(test_case_name, test_name) #endif // Defines a test that uses a test fixture. // // The first parameter is the name of the test fixture class, which // also doubles as the test case name. The second parameter is the // name of the test within the test case. // // A test fixture class must be declared earlier. The user should put // his test code between braces after using this macro. Example: // // class FooTest : public testing::Test { // protected: // virtual void SetUp() { b_.AddElement(3); } // // Foo a_; // Foo b_; // }; // // TEST_F(FooTest, InitializesCorrectly) { // EXPECT_TRUE(a_.StatusIsOK()); // } // // TEST_F(FooTest, ReturnsElementCountCorrectly) { // EXPECT_EQ(0, a_.size()); // EXPECT_EQ(1, b_.size()); // } #define TEST_F(test_fixture, test_name)\ GTEST_TEST_(test_fixture, test_name, test_fixture, \ ::testing::internal::GetTypeId()) // Use this macro in main() to run all tests. It returns 0 if all // tests are successful, or 1 otherwise. // // RUN_ALL_TESTS() should be invoked after the command line has been // parsed by InitGoogleTest(). #define RUN_ALL_TESTS()\ (::testing::UnitTest::GetInstance()->Run()) } // namespace testing #endif // GTEST_INCLUDE_GTEST_GTEST_H_ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/include/000077500000000000000000000000001446477712600224705ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/include/amdp2ptest.h000066400000000000000000000044131446477712600247260ustar00rootroot00000000000000/* * Copyright (C) 2015-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef AMDP2PTEST_H_ #define AMDP2PTEST_H_ #include #define AMDP2PTEST_IOCTL_MAGIC 'A' #define AMDP2PTEST_DEVICE_NAME "amdp2ptest" #define AMDP2PTEST_DEVICE_PATH "/dev/amdp2ptest" struct AMDRDMA_IOCTL_GET_PAGE_SIZE_PARAM { /* Input parameters */ uint64_t addr; uint64_t length; /* Output parameters */ uint64_t page_size; }; struct AMDRDMA_IOCTL_GET_PAGES_PARAM { /* Input parameters */ uint64_t addr; uint64_t length; }; struct AMDRDMA_IOCTL_PUT_PAGES_PARAM { /* Input parameters */ uint64_t addr; uint64_t length; }; struct AMDRDMA_IOCTL_IS_GPU_ADDRESS_PARAM { /* Input parameters */ uint64_t addr; uint64_t ret_value; }; #define AMD2P2PTEST_IOCTL_GET_PAGE_SIZE \ _IOWR(AMDP2PTEST_IOCTL_MAGIC, 1, struct AMDRDMA_IOCTL_GET_PAGE_SIZE_PARAM *) #define AMD2P2PTEST_IOCTL_GET_PAGES \ _IOWR(AMDP2PTEST_IOCTL_MAGIC, 2, struct AMDRDMA_IOCTL_GET_PAGES_PARAM *) #define AMD2P2PTEST_IOCTL_PUT_PAGES \ _IOW(AMDP2PTEST_IOCTL_MAGIC, 3, struct AMDRDMA_IOCTL_PUT_PAGES_PARAM *) #define AMD2P2PTEST_IOCTL_IS_GPU_ADDRESS \ _IOW(AMDP2PTEST_IOCTL_MAGIC, 4, struct AMDRDMA_IOCTL_IS_GPU_ADDRESS *) #endif /* AMDP2PTEST_H */ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/include/asic_reg/000077500000000000000000000000001446477712600242445ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/include/asic_reg/gfx_7_2_d.h000066400000000000000000006573461446477712600262000ustar00rootroot00000000000000/* * Copyright (C) 2014 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef GFX_7_2_D_H #define GFX_7_2_D_H #define mmCB_BLEND_RED 0xa105 #define mmCB_BLEND_GREEN 0xa106 #define mmCB_BLEND_BLUE 0xa107 #define mmCB_BLEND_ALPHA 0xa108 #define mmCB_COLOR_CONTROL 0xa202 #define mmCB_BLEND0_CONTROL 0xa1e0 #define mmCB_BLEND1_CONTROL 0xa1e1 #define mmCB_BLEND2_CONTROL 0xa1e2 #define mmCB_BLEND3_CONTROL 0xa1e3 #define mmCB_BLEND4_CONTROL 0xa1e4 #define mmCB_BLEND5_CONTROL 0xa1e5 #define mmCB_BLEND6_CONTROL 0xa1e6 #define mmCB_BLEND7_CONTROL 0xa1e7 #define mmCB_COLOR0_BASE 0xa318 #define mmCB_COLOR1_BASE 0xa327 #define mmCB_COLOR2_BASE 0xa336 #define mmCB_COLOR3_BASE 0xa345 #define mmCB_COLOR4_BASE 0xa354 #define mmCB_COLOR5_BASE 0xa363 #define mmCB_COLOR6_BASE 0xa372 #define mmCB_COLOR7_BASE 0xa381 #define mmCB_COLOR0_PITCH 0xa319 #define mmCB_COLOR1_PITCH 0xa328 #define mmCB_COLOR2_PITCH 0xa337 #define mmCB_COLOR3_PITCH 0xa346 #define mmCB_COLOR4_PITCH 0xa355 #define mmCB_COLOR5_PITCH 0xa364 #define mmCB_COLOR6_PITCH 0xa373 #define mmCB_COLOR7_PITCH 0xa382 #define mmCB_COLOR0_SLICE 0xa31a #define mmCB_COLOR1_SLICE 0xa329 #define mmCB_COLOR2_SLICE 0xa338 #define mmCB_COLOR3_SLICE 0xa347 #define mmCB_COLOR4_SLICE 0xa356 #define mmCB_COLOR5_SLICE 0xa365 #define mmCB_COLOR6_SLICE 0xa374 #define mmCB_COLOR7_SLICE 0xa383 #define mmCB_COLOR0_VIEW 0xa31b #define mmCB_COLOR1_VIEW 0xa32a #define mmCB_COLOR2_VIEW 0xa339 #define mmCB_COLOR3_VIEW 0xa348 #define mmCB_COLOR4_VIEW 0xa357 #define mmCB_COLOR5_VIEW 0xa366 #define mmCB_COLOR6_VIEW 0xa375 #define mmCB_COLOR7_VIEW 0xa384 #define mmCB_COLOR0_INFO 0xa31c #define mmCB_COLOR1_INFO 0xa32b #define mmCB_COLOR2_INFO 0xa33a #define mmCB_COLOR3_INFO 0xa349 #define mmCB_COLOR4_INFO 0xa358 #define mmCB_COLOR5_INFO 0xa367 #define mmCB_COLOR6_INFO 0xa376 #define mmCB_COLOR7_INFO 0xa385 #define mmCB_COLOR0_ATTRIB 0xa31d #define mmCB_COLOR1_ATTRIB 0xa32c #define mmCB_COLOR2_ATTRIB 0xa33b #define mmCB_COLOR3_ATTRIB 0xa34a #define mmCB_COLOR4_ATTRIB 0xa359 #define mmCB_COLOR5_ATTRIB 0xa368 #define mmCB_COLOR6_ATTRIB 0xa377 #define mmCB_COLOR7_ATTRIB 0xa386 #define mmCB_COLOR0_CMASK 0xa31f #define mmCB_COLOR1_CMASK 0xa32e #define mmCB_COLOR2_CMASK 0xa33d #define mmCB_COLOR3_CMASK 0xa34c #define mmCB_COLOR4_CMASK 0xa35b #define mmCB_COLOR5_CMASK 0xa36a #define mmCB_COLOR6_CMASK 0xa379 #define mmCB_COLOR7_CMASK 0xa388 #define mmCB_COLOR0_CMASK_SLICE 0xa320 #define mmCB_COLOR1_CMASK_SLICE 0xa32f #define mmCB_COLOR2_CMASK_SLICE 0xa33e #define mmCB_COLOR3_CMASK_SLICE 0xa34d #define mmCB_COLOR4_CMASK_SLICE 0xa35c #define mmCB_COLOR5_CMASK_SLICE 0xa36b #define mmCB_COLOR6_CMASK_SLICE 0xa37a #define mmCB_COLOR7_CMASK_SLICE 0xa389 #define mmCB_COLOR0_FMASK 0xa321 #define mmCB_COLOR1_FMASK 0xa330 #define mmCB_COLOR2_FMASK 0xa33f #define mmCB_COLOR3_FMASK 0xa34e #define mmCB_COLOR4_FMASK 0xa35d #define mmCB_COLOR5_FMASK 0xa36c #define mmCB_COLOR6_FMASK 0xa37b #define mmCB_COLOR7_FMASK 0xa38a #define mmCB_COLOR0_FMASK_SLICE 0xa322 #define mmCB_COLOR1_FMASK_SLICE 0xa331 #define mmCB_COLOR2_FMASK_SLICE 0xa340 #define mmCB_COLOR3_FMASK_SLICE 0xa34f #define mmCB_COLOR4_FMASK_SLICE 0xa35e #define mmCB_COLOR5_FMASK_SLICE 0xa36d #define mmCB_COLOR6_FMASK_SLICE 0xa37c #define mmCB_COLOR7_FMASK_SLICE 0xa38b #define mmCB_COLOR0_CLEAR_WORD0 0xa323 #define mmCB_COLOR1_CLEAR_WORD0 0xa332 #define mmCB_COLOR2_CLEAR_WORD0 0xa341 #define mmCB_COLOR3_CLEAR_WORD0 0xa350 #define mmCB_COLOR4_CLEAR_WORD0 0xa35f #define mmCB_COLOR5_CLEAR_WORD0 0xa36e #define mmCB_COLOR6_CLEAR_WORD0 0xa37d #define mmCB_COLOR7_CLEAR_WORD0 0xa38c #define mmCB_COLOR0_CLEAR_WORD1 0xa324 #define mmCB_COLOR1_CLEAR_WORD1 0xa333 #define mmCB_COLOR2_CLEAR_WORD1 0xa342 #define mmCB_COLOR3_CLEAR_WORD1 0xa351 #define mmCB_COLOR4_CLEAR_WORD1 0xa360 #define mmCB_COLOR5_CLEAR_WORD1 0xa36f #define mmCB_COLOR6_CLEAR_WORD1 0xa37e #define mmCB_COLOR7_CLEAR_WORD1 0xa38d #define mmCB_TARGET_MASK 0xa08e #define mmCB_SHADER_MASK 0xa08f #define mmCB_HW_CONTROL 0x2684 #define mmCB_HW_CONTROL_1 0x2685 #define mmCB_HW_CONTROL_2 0x2686 #define mmCB_HW_CONTROL_3 0x2683 #define mmCB_PERFCOUNTER_FILTER 0xdc00 #define mmCB_PERFCOUNTER0_SELECT 0xdc01 #define mmCB_PERFCOUNTER0_SELECT1 0xdc02 #define mmCB_PERFCOUNTER1_SELECT 0xdc03 #define mmCB_PERFCOUNTER2_SELECT 0xdc04 #define mmCB_PERFCOUNTER3_SELECT 0xdc05 #define mmCB_PERFCOUNTER0_LO 0xd406 #define mmCB_PERFCOUNTER1_LO 0xd408 #define mmCB_PERFCOUNTER2_LO 0xd40a #define mmCB_PERFCOUNTER3_LO 0xd40c #define mmCB_PERFCOUNTER0_HI 0xd407 #define mmCB_PERFCOUNTER1_HI 0xd409 #define mmCB_PERFCOUNTER2_HI 0xd40b #define mmCB_PERFCOUNTER3_HI 0xd40d #define mmCB_CGTT_SCLK_CTRL 0xf0a8 #define mmCB_DEBUG_BUS_1 0x2699 #define mmCB_DEBUG_BUS_2 0x269a #define mmCB_DEBUG_BUS_3 0x269b #define mmCB_DEBUG_BUS_4 0x269c #define mmCB_DEBUG_BUS_5 0x269d #define mmCB_DEBUG_BUS_6 0x269e #define mmCB_DEBUG_BUS_7 0x269f #define mmCB_DEBUG_BUS_8 0x26a0 #define mmCB_DEBUG_BUS_9 0x26a1 #define mmCB_DEBUG_BUS_10 0x26a2 #define mmCB_DEBUG_BUS_11 0x26a3 #define mmCB_DEBUG_BUS_12 0x26a4 #define mmCB_DEBUG_BUS_13 0x26a5 #define mmCB_DEBUG_BUS_14 0x26a6 #define mmCB_DEBUG_BUS_15 0x26a7 #define mmCB_DEBUG_BUS_16 0x26a8 #define mmCB_DEBUG_BUS_17 0x26a9 #define mmCB_DEBUG_BUS_18 0x26aa #define mmCP_DFY_CNTL 0x3020 #define mmCP_DFY_STAT 0x3021 #define mmCP_DFY_ADDR_HI 0x3022 #define mmCP_DFY_ADDR_LO 0x3023 #define mmCP_DFY_DATA_0 0x3024 #define mmCP_DFY_DATA_1 0x3025 #define mmCP_DFY_DATA_2 0x3026 #define mmCP_DFY_DATA_3 0x3027 #define mmCP_DFY_DATA_4 0x3028 #define mmCP_DFY_DATA_5 0x3029 #define mmCP_DFY_DATA_6 0x302a #define mmCP_DFY_DATA_7 0x302b #define mmCP_DFY_DATA_8 0x302c #define mmCP_DFY_DATA_9 0x302d #define mmCP_DFY_DATA_10 0x302e #define mmCP_DFY_DATA_11 0x302f #define mmCP_DFY_DATA_12 0x3030 #define mmCP_DFY_DATA_13 0x3031 #define mmCP_DFY_DATA_14 0x3032 #define mmCP_DFY_DATA_15 0x3033 #define mmCP_RB0_BASE 0x3040 #define mmCP_RB0_BASE_HI 0x30b1 #define mmCP_RB_BASE 0x3040 #define mmCP_RB1_BASE 0x3060 #define mmCP_RB1_BASE_HI 0x30b2 #define mmCP_RB2_BASE 0x3065 #define mmCP_RB0_CNTL 0x3041 #define mmCP_RB_CNTL 0x3041 #define mmCP_RB1_CNTL 0x3061 #define mmCP_RB2_CNTL 0x3066 #define mmCP_RB_RPTR_WR 0x3042 #define mmCP_RB0_RPTR_ADDR 0x3043 #define mmCP_RB_RPTR_ADDR 0x3043 #define mmCP_RB1_RPTR_ADDR 0x3062 #define mmCP_RB2_RPTR_ADDR 0x3067 #define mmCP_RB0_RPTR_ADDR_HI 0x3044 #define mmCP_RB_RPTR_ADDR_HI 0x3044 #define mmCP_RB1_RPTR_ADDR_HI 0x3063 #define mmCP_RB2_RPTR_ADDR_HI 0x3068 #define mmCP_RB0_WPTR 0x3045 #define mmCP_RB_WPTR 0x3045 #define mmCP_RB1_WPTR 0x3064 #define mmCP_RB2_WPTR 0x3069 #define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 #define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 #define mmGC_PRIV_MODE 0x3048 #define mmCP_INT_CNTL 0x3049 #define mmCP_INT_CNTL_RING0 0x306a #define mmCP_INT_CNTL_RING1 0x306b #define mmCP_INT_CNTL_RING2 0x306c #define mmCP_INT_STATUS 0x304a #define mmCP_INT_STATUS_RING0 0x306d #define mmCP_INT_STATUS_RING1 0x306e #define mmCP_INT_STATUS_RING2 0x306f #define mmCP_DEVICE_ID 0x304b #define mmCP_RING_PRIORITY_CNTS 0x304c #define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304c #define mmCP_RING0_PRIORITY 0x304d #define mmCP_ME0_PIPE0_PRIORITY 0x304d #define mmCP_RING1_PRIORITY 0x304e #define mmCP_ME0_PIPE1_PRIORITY 0x304e #define mmCP_RING2_PRIORITY 0x304f #define mmCP_ME0_PIPE2_PRIORITY 0x304f #define mmCP_ENDIAN_SWAP 0x3050 #define mmCP_RB_VMID 0x3051 #define mmCP_ME0_PIPE0_VMID 0x3052 #define mmCP_ME0_PIPE1_VMID 0x3053 #define mmCP_PFP_UCODE_ADDR 0x3054 #define mmCP_PFP_UCODE_DATA 0x3055 #define mmCP_ME_RAM_RADDR 0x3056 #define mmCP_ME_RAM_WADDR 0x3057 #define mmCP_ME_RAM_DATA 0x3058 #define mmCGTT_CPC_CLK_CTRL 0xf0b2 #define mmCGTT_CPF_CLK_CTRL 0xf0b1 #define mmCGTT_CP_CLK_CTRL 0xf0b0 #define mmCP_CE_UCODE_ADDR 0x305a #define mmCP_CE_UCODE_DATA 0x305b #define mmCP_MEC_ME1_UCODE_ADDR 0x305c #define mmCP_MEC_ME1_UCODE_DATA 0x305d #define mmCP_MEC_ME2_UCODE_ADDR 0x305e #define mmCP_MEC_ME2_UCODE_DATA 0x305f #define mmCP_PWR_CNTL 0x3078 #define mmCP_MEM_SLP_CNTL 0x3079 #define mmCP_ECC_FIRSTOCCURRENCE 0x307a #define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307b #define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307c #define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307d #define mmCP_CPF_DEBUG 0x3080 #define mmCP_FETCHER_SOURCE 0x3082 #define mmCP_PQ_WPTR_POLL_CNTL 0x3083 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 #define mmCPC_INT_CNTL 0x30b4 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085 #define mmCP_ME1_PIPE1_INT_CNTL 0x3086 #define mmCP_ME1_PIPE2_INT_CNTL 0x3087 #define mmCP_ME1_PIPE3_INT_CNTL 0x3088 #define mmCP_ME2_PIPE0_INT_CNTL 0x3089 #define mmCP_ME2_PIPE1_INT_CNTL 0x308a #define mmCP_ME2_PIPE2_INT_CNTL 0x308b #define mmCP_ME2_PIPE3_INT_CNTL 0x308c #define mmCPC_INT_STATUS 0x30b5 #define mmCP_ME1_PIPE0_INT_STATUS 0x308d #define mmCP_ME1_PIPE1_INT_STATUS 0x308e #define mmCP_ME1_PIPE2_INT_STATUS 0x308f #define mmCP_ME1_PIPE3_INT_STATUS 0x3090 #define mmCP_ME2_PIPE0_INT_STATUS 0x3091 #define mmCP_ME2_PIPE1_INT_STATUS 0x3092 #define mmCP_ME2_PIPE2_INT_STATUS 0x3093 #define mmCP_ME2_PIPE3_INT_STATUS 0x3094 #define mmCP_ME1_INT_STAT_DEBUG 0x3095 #define mmCP_ME2_INT_STAT_DEBUG 0x3096 #define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099 #define mmCP_ME1_PIPE0_PRIORITY 0x309a #define mmCP_ME1_PIPE1_PRIORITY 0x309b #define mmCP_ME1_PIPE2_PRIORITY 0x309c #define mmCP_ME1_PIPE3_PRIORITY 0x309d #define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309e #define mmCP_ME2_PIPE0_PRIORITY 0x309f #define mmCP_ME2_PIPE1_PRIORITY 0x30a0 #define mmCP_ME2_PIPE2_PRIORITY 0x30a1 #define mmCP_ME2_PIPE3_PRIORITY 0x30a2 #define mmCP_CE_PRGRM_CNTR_START 0x30a3 #define mmCP_PFP_PRGRM_CNTR_START 0x30a4 #define mmCP_ME_PRGRM_CNTR_START 0x30a5 #define mmCP_MEC1_PRGRM_CNTR_START 0x30a6 #define mmCP_MEC2_PRGRM_CNTR_START 0x30a7 #define mmCP_CE_INTR_ROUTINE_START 0x30a8 #define mmCP_PFP_INTR_ROUTINE_START 0x30a9 #define mmCP_ME_INTR_ROUTINE_START 0x30aa #define mmCP_MEC1_INTR_ROUTINE_START 0x30ab #define mmCP_MEC2_INTR_ROUTINE_START 0x30ac #define mmCP_CONTEXT_CNTL 0x30ad #define mmCP_MAX_CONTEXT 0x30ae #define mmCP_IQ_WAIT_TIME1 0x30af #define mmCP_IQ_WAIT_TIME2 0x30b0 #define mmCP_VMID_RESET 0x30b3 #define mmCP_VMID_PREEMPT 0x30b6 #define mmCPC_INT_CNTX_ID 0x30b7 #define mmCP_PQ_STATUS 0x30b8 #define mmCP_CPC_STATUS 0x2084 #define mmCP_CPC_BUSY_STAT 0x2085 #define mmCP_CPC_STALLED_STAT1 0x2086 #define mmCP_CPF_STATUS 0x2087 #define mmCP_CPF_BUSY_STAT 0x2088 #define mmCP_CPF_STALLED_STAT1 0x2089 #define mmCP_CPC_MC_CNTL 0x208a #define mmCP_CPC_GRBM_FREE_COUNT 0x208b #define mmCP_MEC_CNTL 0x208d #define mmCP_MEC_ME1_HEADER_DUMP 0x208e #define mmCP_MEC_ME2_HEADER_DUMP 0x208f #define mmCP_CPC_SCRATCH_INDEX 0x2090 #define mmCP_CPC_SCRATCH_DATA 0x2091 #define mmCPG_PERFCOUNTER1_SELECT 0xd800 #define mmCPG_PERFCOUNTER1_LO 0xd000 #define mmCPG_PERFCOUNTER1_HI 0xd001 #define mmCPG_PERFCOUNTER0_SELECT1 0xd801 #define mmCPG_PERFCOUNTER0_SELECT 0xd802 #define mmCPG_PERFCOUNTER0_LO 0xd002 #define mmCPG_PERFCOUNTER0_HI 0xd003 #define mmCPC_PERFCOUNTER1_SELECT 0xd803 #define mmCPC_PERFCOUNTER1_LO 0xd004 #define mmCPC_PERFCOUNTER1_HI 0xd005 #define mmCPC_PERFCOUNTER0_SELECT1 0xd804 #define mmCPC_PERFCOUNTER0_SELECT 0xd809 #define mmCPC_PERFCOUNTER0_LO 0xd006 #define mmCPC_PERFCOUNTER0_HI 0xd007 #define mmCPF_PERFCOUNTER1_SELECT 0xd805 #define mmCPF_PERFCOUNTER1_LO 0xd008 #define mmCPF_PERFCOUNTER1_HI 0xd009 #define mmCPF_PERFCOUNTER0_SELECT1 0xd806 #define mmCPF_PERFCOUNTER0_SELECT 0xd807 #define mmCPF_PERFCOUNTER0_LO 0xd00a #define mmCPF_PERFCOUNTER0_HI 0xd00b #define mmCP_CPC_HALT_HYST_COUNT 0x20a7 #define mmCP_DRAW_OBJECT 0xd810 #define mmCP_DRAW_OBJECT_COUNTER 0xd811 #define mmCP_DRAW_WINDOW_MASK_HI 0xd812 #define mmCP_DRAW_WINDOW_HI 0xd813 #define mmCP_DRAW_WINDOW_LO 0xd814 #define mmCP_DRAW_WINDOW_CNTL 0xd815 #define mmCP_PRT_LOD_STATS_CNTL0 0x20ad #define mmCP_PRT_LOD_STATS_CNTL1 0x20ae #define mmCP_PRT_LOD_STATS_CNTL2 0x20af #define mmCP_CE_COMPARE_COUNT 0x20c0 #define mmCP_CE_DE_COUNT 0x20c1 #define mmCP_DE_CE_COUNT 0x20c2 #define mmCP_DE_LAST_INVAL_COUNT 0x20c3 #define mmCP_DE_DE_COUNT 0x20c4 #define mmCP_EOP_DONE_EVENT_CNTL 0xc0d5 #define mmCP_EOP_DONE_DATA_CNTL 0xc0d6 #define mmCP_EOP_DONE_ADDR_LO 0xc000 #define mmCP_EOP_DONE_ADDR_HI 0xc001 #define mmCP_EOP_DONE_DATA_LO 0xc002 #define mmCP_EOP_DONE_DATA_HI 0xc003 #define mmCP_EOP_LAST_FENCE_LO 0xc004 #define mmCP_EOP_LAST_FENCE_HI 0xc005 #define mmCP_STREAM_OUT_ADDR_LO 0xc006 #define mmCP_STREAM_OUT_ADDR_HI 0xc007 #define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xc008 #define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xc009 #define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xc00a #define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xc00b #define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xc00c #define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xc00d #define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xc00e #define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xc00f #define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xc010 #define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xc011 #define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xc012 #define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xc013 #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xc014 #define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xc015 #define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xc016 #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xc017 #define mmCP_PIPE_STATS_ADDR_LO 0xc018 #define mmCP_PIPE_STATS_ADDR_HI 0xc019 #define mmCP_VGT_IAVERT_COUNT_LO 0xc01a #define mmCP_VGT_IAVERT_COUNT_HI 0xc01b #define mmCP_VGT_IAPRIM_COUNT_LO 0xc01c #define mmCP_VGT_IAPRIM_COUNT_HI 0xc01d #define mmCP_VGT_GSPRIM_COUNT_LO 0xc01e #define mmCP_VGT_GSPRIM_COUNT_HI 0xc01f #define mmCP_VGT_VSINVOC_COUNT_LO 0xc020 #define mmCP_VGT_VSINVOC_COUNT_HI 0xc021 #define mmCP_VGT_GSINVOC_COUNT_LO 0xc022 #define mmCP_VGT_GSINVOC_COUNT_HI 0xc023 #define mmCP_VGT_HSINVOC_COUNT_LO 0xc024 #define mmCP_VGT_HSINVOC_COUNT_HI 0xc025 #define mmCP_VGT_DSINVOC_COUNT_LO 0xc026 #define mmCP_VGT_DSINVOC_COUNT_HI 0xc027 #define mmCP_PA_CINVOC_COUNT_LO 0xc028 #define mmCP_PA_CINVOC_COUNT_HI 0xc029 #define mmCP_PA_CPRIM_COUNT_LO 0xc02a #define mmCP_PA_CPRIM_COUNT_HI 0xc02b #define mmCP_SC_PSINVOC_COUNT0_LO 0xc02c #define mmCP_SC_PSINVOC_COUNT0_HI 0xc02d #define mmCP_SC_PSINVOC_COUNT1_LO 0xc02e #define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f #define mmCP_VGT_CSINVOC_COUNT_LO 0xc030 #define mmCP_VGT_CSINVOC_COUNT_HI 0xc031 #define mmCP_STRMOUT_CNTL 0xc03f #define mmSCRATCH_REG0 0xc040 #define mmSCRATCH_REG1 0xc041 #define mmSCRATCH_REG2 0xc042 #define mmSCRATCH_REG3 0xc043 #define mmSCRATCH_REG4 0xc044 #define mmSCRATCH_REG5 0xc045 #define mmSCRATCH_REG6 0xc046 #define mmSCRATCH_REG7 0xc047 #define mmSCRATCH_UMSK 0xc050 #define mmSCRATCH_ADDR 0xc051 #define mmCP_PFP_ATOMIC_PREOP_LO 0xc052 #define mmCP_PFP_ATOMIC_PREOP_HI 0xc053 #define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xc054 #define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xc055 #define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xc056 #define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xc057 #define mmCP_APPEND_ADDR_LO 0xc058 #define mmCP_APPEND_ADDR_HI 0xc059 #define mmCP_APPEND_DATA 0xc05a #define mmCP_APPEND_LAST_CS_FENCE 0xc05b #define mmCP_APPEND_LAST_PS_FENCE 0xc05c #define mmCP_ATOMIC_PREOP_LO 0xc05d #define mmCP_ME_ATOMIC_PREOP_LO 0xc05d #define mmCP_ATOMIC_PREOP_HI 0xc05e #define mmCP_ME_ATOMIC_PREOP_HI 0xc05e #define mmCP_GDS_ATOMIC0_PREOP_LO 0xc05f #define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xc05f #define mmCP_GDS_ATOMIC0_PREOP_HI 0xc060 #define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xc060 #define mmCP_GDS_ATOMIC1_PREOP_LO 0xc061 #define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xc061 #define mmCP_GDS_ATOMIC1_PREOP_HI 0xc062 #define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xc062 #define mmCP_ME_MC_WADDR_LO 0xc069 #define mmCP_ME_MC_WADDR_HI 0xc06a #define mmCP_ME_MC_WDATA_LO 0xc06b #define mmCP_ME_MC_WDATA_HI 0xc06c #define mmCP_ME_MC_RADDR_LO 0xc06d #define mmCP_ME_MC_RADDR_HI 0xc06e #define mmCP_SEM_WAIT_TIMER 0xc06f #define mmCP_SIG_SEM_ADDR_LO 0xc070 #define mmCP_SIG_SEM_ADDR_HI 0xc071 #define mmCP_WAIT_SEM_ADDR_LO 0xc075 #define mmCP_WAIT_SEM_ADDR_HI 0xc076 #define mmCP_WAIT_REG_MEM_TIMEOUT 0xc074 #define mmCP_COHER_START_DELAY 0xc07b #define mmCP_COHER_CNTL 0xc07c #define mmCP_COHER_SIZE 0xc07d #define mmCP_COHER_SIZE_HI 0xc08c #define mmCP_COHER_BASE 0xc07e #define mmCP_COHER_BASE_HI 0xc079 #define mmCP_COHER_STATUS 0xc07f #define mmCOHER_DEST_BASE_0 0xa092 #define mmCOHER_DEST_BASE_1 0xa093 #define mmCOHER_DEST_BASE_2 0xa07e #define mmCOHER_DEST_BASE_3 0xa07f #define mmCOHER_DEST_BASE_HI_0 0xa07a #define mmCOHER_DEST_BASE_HI_1 0xa07b #define mmCOHER_DEST_BASE_HI_2 0xa07c #define mmCOHER_DEST_BASE_HI_3 0xa07d #define mmCP_DMA_ME_SRC_ADDR 0xc080 #define mmCP_DMA_ME_SRC_ADDR_HI 0xc081 #define mmCP_DMA_ME_DST_ADDR 0xc082 #define mmCP_DMA_ME_DST_ADDR_HI 0xc083 #define mmCP_DMA_ME_CONTROL 0xc078 #define mmCP_DMA_ME_COMMAND 0xc084 #define mmCP_DMA_PFP_SRC_ADDR 0xc085 #define mmCP_DMA_PFP_SRC_ADDR_HI 0xc086 #define mmCP_DMA_PFP_DST_ADDR 0xc087 #define mmCP_DMA_PFP_DST_ADDR_HI 0xc088 #define mmCP_DMA_PFP_CONTROL 0xc077 #define mmCP_DMA_PFP_COMMAND 0xc089 #define mmCP_DMA_CNTL 0xc08a #define mmCP_DMA_READ_TAGS 0xc08b #define mmCP_PFP_IB_CONTROL 0xc08d #define mmCP_PFP_LOAD_CONTROL 0xc08e #define mmCP_SCRATCH_INDEX 0xc08f #define mmCP_SCRATCH_DATA 0xc090 #define mmCP_RB_OFFSET 0xc091 #define mmCP_IB1_OFFSET 0xc092 #define mmCP_IB2_OFFSET 0xc093 #define mmCP_IB1_PREAMBLE_BEGIN 0xc094 #define mmCP_IB1_PREAMBLE_END 0xc095 #define mmCP_IB2_PREAMBLE_BEGIN 0xc096 #define mmCP_IB2_PREAMBLE_END 0xc097 #define mmCP_CE_IB1_OFFSET 0xc098 #define mmCP_CE_IB2_OFFSET 0xc099 #define mmCP_CE_COUNTER 0xc09a #define mmCP_STALLED_STAT1 0x219d #define mmCP_STALLED_STAT2 0x219e #define mmCP_STALLED_STAT3 0x219c #define mmCP_BUSY_STAT 0x219f #define mmCP_STAT 0x21a0 #define mmCP_ME_HEADER_DUMP 0x21a1 #define mmCP_PFP_HEADER_DUMP 0x21a2 #define mmCP_GRBM_FREE_COUNT 0x21a3 #define mmCP_CE_HEADER_DUMP 0x21a4 #define mmCP_MC_PACK_DELAY_CNT 0x21a7 #define mmCP_MC_TAG_CNTL 0x21a8 #define mmCP_MC_TAG_DATA 0x21a9 #define mmCP_CSF_STAT 0x21b4 #define mmCP_CSF_CNTL 0x21b5 #define mmCP_ME_CNTL 0x21b6 #define mmCP_CNTX_STAT 0x21b8 #define mmCP_ME_PREEMPTION 0x21b9 #define mmCP_RB0_RPTR 0x21c0 #define mmCP_RB_RPTR 0x21c0 #define mmCP_RB1_RPTR 0x21bf #define mmCP_RB2_RPTR 0x21be #define mmCP_RB_WPTR_DELAY 0x21c1 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 #define mmCP_CE_INIT_BASE_LO 0xc0c3 #define mmCP_CE_INIT_BASE_HI 0xc0c4 #define mmCP_CE_INIT_BUFSZ 0xc0c5 #define mmCP_CE_IB1_BASE_LO 0xc0c6 #define mmCP_CE_IB1_BASE_HI 0xc0c7 #define mmCP_CE_IB1_BUFSZ 0xc0c8 #define mmCP_CE_IB2_BASE_LO 0xc0c9 #define mmCP_CE_IB2_BASE_HI 0xc0ca #define mmCP_CE_IB2_BUFSZ 0xc0cb #define mmCP_IB1_BASE_LO 0xc0cc #define mmCP_IB1_BASE_HI 0xc0cd #define mmCP_IB1_BUFSZ 0xc0ce #define mmCP_IB2_BASE_LO 0xc0cf #define mmCP_IB2_BASE_HI 0xc0d0 #define mmCP_IB2_BUFSZ 0xc0d1 #define mmCP_ST_BASE_LO 0xc0d2 #define mmCP_ST_BASE_HI 0xc0d3 #define mmCP_ST_BUFSZ 0xc0d4 #define mmCP_ROQ_THRESHOLDS 0x21bc #define mmCP_MEQ_STQ_THRESHOLD 0x21bd #define mmCP_ROQ1_THRESHOLDS 0x21d5 #define mmCP_ROQ2_THRESHOLDS 0x21d6 #define mmCP_STQ_THRESHOLDS 0x21d7 #define mmCP_QUEUE_THRESHOLDS 0x21d8 #define mmCP_MEQ_THRESHOLDS 0x21d9 #define mmCP_ROQ_AVAIL 0x21da #define mmCP_STQ_AVAIL 0x21db #define mmCP_ROQ2_AVAIL 0x21dc #define mmCP_MEQ_AVAIL 0x21dd #define mmCP_CMD_INDEX 0x21de #define mmCP_CMD_DATA 0x21df #define mmCP_ROQ_RB_STAT 0x21e0 #define mmCP_ROQ_IB1_STAT 0x21e1 #define mmCP_ROQ_IB2_STAT 0x21e2 #define mmCP_STQ_STAT 0x21e3 #define mmCP_STQ_WR_STAT 0x21e4 #define mmCP_MEQ_STAT 0x21e5 #define mmCP_CEQ1_AVAIL 0x21e6 #define mmCP_CEQ2_AVAIL 0x21e7 #define mmCP_CE_ROQ_RB_STAT 0x21e8 #define mmCP_CE_ROQ_IB1_STAT 0x21e9 #define mmCP_CE_ROQ_IB2_STAT 0x21ea #define mmCP_INT_STAT_DEBUG 0x21f7 #define mmCP_PERFMON_CNTL 0xd808 #define mmCP_PERFMON_CNTX_CNTL 0xa0d8 #define mmCP_RINGID 0xa0d9 #define mmCP_PIPEID 0xa0d9 #define mmCP_VMID 0xa0da #define mmCP_HPD_ROQ_OFFSETS 0x3240 #define mmCP_HPD_EOP_BASE_ADDR 0x3241 #define mmCP_HPD_EOP_BASE_ADDR_HI 0x3242 #define mmCP_HPD_EOP_VMID 0x3243 #define mmCP_HPD_EOP_CONTROL 0x3244 #define mmCP_MQD_BASE_ADDR 0x3245 #define mmCP_MQD_BASE_ADDR_HI 0x3246 #define mmCP_HQD_ACTIVE 0x3247 #define mmCP_HQD_VMID 0x3248 #define mmCP_HQD_PERSISTENT_STATE 0x3249 #define mmCP_HQD_PIPE_PRIORITY 0x324a #define mmCP_HQD_QUEUE_PRIORITY 0x324b #define mmCP_HQD_QUANTUM 0x324c #define mmCP_HQD_PQ_BASE 0x324d #define mmCP_HQD_PQ_BASE_HI 0x324e #define mmCP_HQD_PQ_RPTR 0x324f #define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251 #define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 #define mmCP_HQD_PQ_WPTR 0x3255 #define mmCP_HQD_PQ_CONTROL 0x3256 #define mmCP_HQD_IB_BASE_ADDR 0x3257 #define mmCP_HQD_IB_BASE_ADDR_HI 0x3258 #define mmCP_HQD_IB_RPTR 0x3259 #define mmCP_HQD_IB_CONTROL 0x325a #define mmCP_HQD_IQ_TIMER 0x325b #define mmCP_HQD_IQ_RPTR 0x325c #define mmCP_HQD_DEQUEUE_REQUEST 0x325d #define mmCP_HQD_DMA_OFFLOAD 0x325e #define mmCP_HQD_SEMA_CMD 0x325f #define mmCP_HQD_MSG_TYPE 0x3260 #define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261 #define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262 #define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263 #define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264 #define mmCP_HQD_HQ_SCHEDULER0 0x3265 #define mmCP_HQD_HQ_SCHEDULER1 0x3266 #define mmCP_MQD_CONTROL 0x3267 #define mmDB_Z_READ_BASE 0xa012 #define mmDB_STENCIL_READ_BASE 0xa013 #define mmDB_Z_WRITE_BASE 0xa014 #define mmDB_STENCIL_WRITE_BASE 0xa015 #define mmDB_DEPTH_INFO 0xa00f #define mmDB_Z_INFO 0xa010 #define mmDB_STENCIL_INFO 0xa011 #define mmDB_DEPTH_SIZE 0xa016 #define mmDB_DEPTH_SLICE 0xa017 #define mmDB_DEPTH_VIEW 0xa002 #define mmDB_RENDER_CONTROL 0xa000 #define mmDB_COUNT_CONTROL 0xa001 #define mmDB_RENDER_OVERRIDE 0xa003 #define mmDB_RENDER_OVERRIDE2 0xa004 #define mmDB_EQAA 0xa201 #define mmDB_SHADER_CONTROL 0xa203 #define mmDB_DEPTH_BOUNDS_MIN 0xa008 #define mmDB_DEPTH_BOUNDS_MAX 0xa009 #define mmDB_STENCIL_CLEAR 0xa00a #define mmDB_DEPTH_CLEAR 0xa00b #define mmDB_HTILE_DATA_BASE 0xa005 #define mmDB_HTILE_SURFACE 0xa2af #define mmDB_PRELOAD_CONTROL 0xa2b2 #define mmDB_STENCILREFMASK 0xa10c #define mmDB_STENCILREFMASK_BF 0xa10d #define mmDB_SRESULTS_COMPARE_STATE0 0xa2b0 #define mmDB_SRESULTS_COMPARE_STATE1 0xa2b1 #define mmDB_DEPTH_CONTROL 0xa200 #define mmDB_STENCIL_CONTROL 0xa10b #define mmDB_ALPHA_TO_MASK 0xa2dc #define mmDB_PERFCOUNTER0_SELECT 0xdc40 #define mmDB_PERFCOUNTER1_SELECT 0xdc42 #define mmDB_PERFCOUNTER2_SELECT 0xdc44 #define mmDB_PERFCOUNTER3_SELECT 0xdc46 #define mmDB_PERFCOUNTER0_SELECT1 0xdc41 #define mmDB_PERFCOUNTER1_SELECT1 0xdc43 #define mmDB_PERFCOUNTER0_LO 0xd440 #define mmDB_PERFCOUNTER1_LO 0xd442 #define mmDB_PERFCOUNTER2_LO 0xd444 #define mmDB_PERFCOUNTER3_LO 0xd446 #define mmDB_PERFCOUNTER0_HI 0xd441 #define mmDB_PERFCOUNTER1_HI 0xd443 #define mmDB_PERFCOUNTER2_HI 0xd445 #define mmDB_PERFCOUNTER3_HI 0xd447 #define mmDB_DEBUG 0x260c #define mmDB_DEBUG2 0x260d #define mmDB_DEBUG3 0x260e #define mmDB_DEBUG4 0x260f #define mmDB_CREDIT_LIMIT 0x2614 #define mmDB_WATERMARKS 0x2615 #define mmDB_SUBTILE_CONTROL 0x2616 #define mmDB_FREE_CACHELINES 0x2617 #define mmDB_FIFO_DEPTH1 0x2618 #define mmDB_FIFO_DEPTH2 0x2619 #define mmDB_CGTT_CLK_CTRL_0 0xf0a4 #define mmDB_ZPASS_COUNT_LOW 0xc3fe #define mmDB_ZPASS_COUNT_HI 0xc3ff #define mmDB_RING_CONTROL 0x261b #define mmDB_READ_DEBUG_0 0x2620 #define mmDB_READ_DEBUG_1 0x2621 #define mmDB_READ_DEBUG_2 0x2622 #define mmDB_READ_DEBUG_3 0x2623 #define mmDB_READ_DEBUG_4 0x2624 #define mmDB_READ_DEBUG_5 0x2625 #define mmDB_READ_DEBUG_6 0x2626 #define mmDB_READ_DEBUG_7 0x2627 #define mmDB_READ_DEBUG_8 0x2628 #define mmDB_READ_DEBUG_9 0x2629 #define mmDB_READ_DEBUG_A 0x262a #define mmDB_READ_DEBUG_B 0x262b #define mmDB_READ_DEBUG_C 0x262c #define mmDB_READ_DEBUG_D 0x262d #define mmDB_READ_DEBUG_E 0x262e #define mmDB_READ_DEBUG_F 0x262f #define mmDB_OCCLUSION_COUNT0_LOW 0xc3c0 #define mmDB_OCCLUSION_COUNT0_HI 0xc3c1 #define mmDB_OCCLUSION_COUNT1_LOW 0xc3c2 #define mmDB_OCCLUSION_COUNT1_HI 0xc3c3 #define mmDB_OCCLUSION_COUNT2_LOW 0xc3c4 #define mmDB_OCCLUSION_COUNT2_HI 0xc3c5 #define mmDB_OCCLUSION_COUNT3_LOW 0xc3c6 #define mmDB_OCCLUSION_COUNT3_HI 0xc3c7 #define mmCC_RB_REDUNDANCY 0x263c #define mmCC_RB_BACKEND_DISABLE 0x263d #define mmGC_USER_RB_REDUNDANCY 0x26de #define mmGC_USER_RB_BACKEND_DISABLE 0x26df #define mmGB_ADDR_CONFIG 0x263e #define mmGB_BACKEND_MAP 0x263f #define mmGB_GPU_ID 0x2640 #define mmCC_RB_DAISY_CHAIN 0x2641 #define mmGB_TILE_MODE0 0x2644 #define mmGB_TILE_MODE1 0x2645 #define mmGB_TILE_MODE2 0x2646 #define mmGB_TILE_MODE3 0x2647 #define mmGB_TILE_MODE4 0x2648 #define mmGB_TILE_MODE5 0x2649 #define mmGB_TILE_MODE6 0x264a #define mmGB_TILE_MODE7 0x264b #define mmGB_TILE_MODE8 0x264c #define mmGB_TILE_MODE9 0x264d #define mmGB_TILE_MODE10 0x264e #define mmGB_TILE_MODE11 0x264f #define mmGB_TILE_MODE12 0x2650 #define mmGB_TILE_MODE13 0x2651 #define mmGB_TILE_MODE14 0x2652 #define mmGB_TILE_MODE15 0x2653 #define mmGB_TILE_MODE16 0x2654 #define mmGB_TILE_MODE17 0x2655 #define mmGB_TILE_MODE18 0x2656 #define mmGB_TILE_MODE19 0x2657 #define mmGB_TILE_MODE20 0x2658 #define mmGB_TILE_MODE21 0x2659 #define mmGB_TILE_MODE22 0x265a #define mmGB_TILE_MODE23 0x265b #define mmGB_TILE_MODE24 0x265c #define mmGB_TILE_MODE25 0x265d #define mmGB_TILE_MODE26 0x265e #define mmGB_TILE_MODE27 0x265f #define mmGB_TILE_MODE28 0x2660 #define mmGB_TILE_MODE29 0x2661 #define mmGB_TILE_MODE30 0x2662 #define mmGB_TILE_MODE31 0x2663 #define mmGB_MACROTILE_MODE0 0x2664 #define mmGB_MACROTILE_MODE1 0x2665 #define mmGB_MACROTILE_MODE2 0x2666 #define mmGB_MACROTILE_MODE3 0x2667 #define mmGB_MACROTILE_MODE4 0x2668 #define mmGB_MACROTILE_MODE5 0x2669 #define mmGB_MACROTILE_MODE6 0x266a #define mmGB_MACROTILE_MODE7 0x266b #define mmGB_MACROTILE_MODE8 0x266c #define mmGB_MACROTILE_MODE9 0x266d #define mmGB_MACROTILE_MODE10 0x266e #define mmGB_MACROTILE_MODE11 0x266f #define mmGB_MACROTILE_MODE12 0x2670 #define mmGB_MACROTILE_MODE13 0x2671 #define mmGB_MACROTILE_MODE14 0x2672 #define mmGB_MACROTILE_MODE15 0x2673 #define mmGB_EDC_MODE 0x307e #define mmCC_GC_EDC_CONFIG 0x3098 #define mmRAS_SIGNATURE_CONTROL 0x3380 #define mmRAS_SIGNATURE_MASK 0x3381 #define mmRAS_SX_SIGNATURE0 0x3382 #define mmRAS_SX_SIGNATURE1 0x3383 #define mmRAS_SX_SIGNATURE2 0x3384 #define mmRAS_SX_SIGNATURE3 0x3385 #define mmRAS_DB_SIGNATURE0 0x338b #define mmRAS_PA_SIGNATURE0 0x338c #define mmRAS_VGT_SIGNATURE0 0x338d #define mmRAS_SQ_SIGNATURE0 0x338e #define mmRAS_SC_SIGNATURE0 0x338f #define mmRAS_SC_SIGNATURE1 0x3390 #define mmRAS_SC_SIGNATURE2 0x3391 #define mmRAS_SC_SIGNATURE3 0x3392 #define mmRAS_SC_SIGNATURE4 0x3393 #define mmRAS_SC_SIGNATURE5 0x3394 #define mmRAS_SC_SIGNATURE6 0x3395 #define mmRAS_SC_SIGNATURE7 0x3396 #define mmRAS_IA_SIGNATURE0 0x3397 #define mmRAS_IA_SIGNATURE1 0x3398 #define mmRAS_SPI_SIGNATURE0 0x3399 #define mmRAS_SPI_SIGNATURE1 0x339a #define mmRAS_TA_SIGNATURE0 0x339b #define mmRAS_TD_SIGNATURE0 0x339c #define mmRAS_CB_SIGNATURE0 0x339d #define mmRAS_BCI_SIGNATURE0 0x339e #define mmRAS_BCI_SIGNATURE1 0x339f #define mmGRBM_CAM_INDEX 0x3000 #define mmGRBM_CAM_DATA 0x3001 #define mmGRBM_CNTL 0x2000 #define mmGRBM_SKEW_CNTL 0x2001 #define mmGRBM_PWR_CNTL 0x2003 #define mmGRBM_STATUS 0x2004 #define mmGRBM_STATUS2 0x2002 #define mmGRBM_STATUS_SE0 0x2005 #define mmGRBM_STATUS_SE1 0x2006 #define mmGRBM_STATUS_SE2 0x200e #define mmGRBM_STATUS_SE3 0x200f #define mmGRBM_SOFT_RESET 0x2008 #define mmGRBM_DEBUG_CNTL 0x2009 #define mmGRBM_DEBUG_DATA 0x200a #define mmGRBM_GFX_INDEX 0xc200 #define mmGRBM_GFX_CLKEN_CNTL 0x200c #define mmGRBM_WAIT_IDLE_CLOCKS 0x200d #define mmGRBM_DEBUG 0x2014 #define mmGRBM_DEBUG_SNAPSHOT 0x2015 #define mmGRBM_READ_ERROR 0x2016 #define mmGRBM_READ_ERROR2 0x2017 #define mmGRBM_INT_CNTL 0x2018 #define mmGRBM_PERFCOUNTER0_SELECT 0xd840 #define mmGRBM_PERFCOUNTER1_SELECT 0xd841 #define mmGRBM_SE0_PERFCOUNTER_SELECT 0xd842 #define mmGRBM_SE1_PERFCOUNTER_SELECT 0xd843 #define mmGRBM_SE2_PERFCOUNTER_SELECT 0xd844 #define mmGRBM_SE3_PERFCOUNTER_SELECT 0xd845 #define mmGRBM_PERFCOUNTER0_LO 0xd040 #define mmGRBM_PERFCOUNTER0_HI 0xd041 #define mmGRBM_PERFCOUNTER1_LO 0xd043 #define mmGRBM_PERFCOUNTER1_HI 0xd044 #define mmGRBM_SE0_PERFCOUNTER_LO 0xd045 #define mmGRBM_SE0_PERFCOUNTER_HI 0xd046 #define mmGRBM_SE1_PERFCOUNTER_LO 0xd047 #define mmGRBM_SE1_PERFCOUNTER_HI 0xd048 #define mmGRBM_SE2_PERFCOUNTER_LO 0xd049 #define mmGRBM_SE2_PERFCOUNTER_HI 0xd04a #define mmGRBM_SE3_PERFCOUNTER_LO 0xd04b #define mmGRBM_SE3_PERFCOUNTER_HI 0xd04c #define mmGRBM_SCRATCH_REG0 0x2040 #define mmGRBM_SCRATCH_REG1 0x2041 #define mmGRBM_SCRATCH_REG2 0x2042 #define mmGRBM_SCRATCH_REG3 0x2043 #define mmGRBM_SCRATCH_REG4 0x2044 #define mmGRBM_SCRATCH_REG5 0x2045 #define mmGRBM_SCRATCH_REG6 0x2046 #define mmGRBM_SCRATCH_REG7 0x2047 #define mmDEBUG_INDEX 0x203c #define mmDEBUG_DATA 0x203d #define mmGRBM_NOWHERE 0x203f #define mmPA_CL_VPORT_XSCALE 0xa10f #define mmPA_CL_VPORT_XOFFSET 0xa110 #define mmPA_CL_VPORT_YSCALE 0xa111 #define mmPA_CL_VPORT_YOFFSET 0xa112 #define mmPA_CL_VPORT_ZSCALE 0xa113 #define mmPA_CL_VPORT_ZOFFSET 0xa114 #define mmPA_CL_VPORT_XSCALE_1 0xa115 #define mmPA_CL_VPORT_XSCALE_2 0xa11b #define mmPA_CL_VPORT_XSCALE_3 0xa121 #define mmPA_CL_VPORT_XSCALE_4 0xa127 #define mmPA_CL_VPORT_XSCALE_5 0xa12d #define mmPA_CL_VPORT_XSCALE_6 0xa133 #define mmPA_CL_VPORT_XSCALE_7 0xa139 #define mmPA_CL_VPORT_XSCALE_8 0xa13f #define mmPA_CL_VPORT_XSCALE_9 0xa145 #define mmPA_CL_VPORT_XSCALE_10 0xa14b #define mmPA_CL_VPORT_XSCALE_11 0xa151 #define mmPA_CL_VPORT_XSCALE_12 0xa157 #define mmPA_CL_VPORT_XSCALE_13 0xa15d #define mmPA_CL_VPORT_XSCALE_14 0xa163 #define mmPA_CL_VPORT_XSCALE_15 0xa169 #define mmPA_CL_VPORT_XOFFSET_1 0xa116 #define mmPA_CL_VPORT_XOFFSET_2 0xa11c #define mmPA_CL_VPORT_XOFFSET_3 0xa122 #define mmPA_CL_VPORT_XOFFSET_4 0xa128 #define mmPA_CL_VPORT_XOFFSET_5 0xa12e #define mmPA_CL_VPORT_XOFFSET_6 0xa134 #define mmPA_CL_VPORT_XOFFSET_7 0xa13a #define mmPA_CL_VPORT_XOFFSET_8 0xa140 #define mmPA_CL_VPORT_XOFFSET_9 0xa146 #define mmPA_CL_VPORT_XOFFSET_10 0xa14c #define mmPA_CL_VPORT_XOFFSET_11 0xa152 #define mmPA_CL_VPORT_XOFFSET_12 0xa158 #define mmPA_CL_VPORT_XOFFSET_13 0xa15e #define mmPA_CL_VPORT_XOFFSET_14 0xa164 #define mmPA_CL_VPORT_XOFFSET_15 0xa16a #define mmPA_CL_VPORT_YSCALE_1 0xa117 #define mmPA_CL_VPORT_YSCALE_2 0xa11d #define mmPA_CL_VPORT_YSCALE_3 0xa123 #define mmPA_CL_VPORT_YSCALE_4 0xa129 #define mmPA_CL_VPORT_YSCALE_5 0xa12f #define mmPA_CL_VPORT_YSCALE_6 0xa135 #define mmPA_CL_VPORT_YSCALE_7 0xa13b #define mmPA_CL_VPORT_YSCALE_8 0xa141 #define mmPA_CL_VPORT_YSCALE_9 0xa147 #define mmPA_CL_VPORT_YSCALE_10 0xa14d #define mmPA_CL_VPORT_YSCALE_11 0xa153 #define mmPA_CL_VPORT_YSCALE_12 0xa159 #define mmPA_CL_VPORT_YSCALE_13 0xa15f #define mmPA_CL_VPORT_YSCALE_14 0xa165 #define mmPA_CL_VPORT_YSCALE_15 0xa16b #define mmPA_CL_VPORT_YOFFSET_1 0xa118 #define mmPA_CL_VPORT_YOFFSET_2 0xa11e #define mmPA_CL_VPORT_YOFFSET_3 0xa124 #define mmPA_CL_VPORT_YOFFSET_4 0xa12a #define mmPA_CL_VPORT_YOFFSET_5 0xa130 #define mmPA_CL_VPORT_YOFFSET_6 0xa136 #define mmPA_CL_VPORT_YOFFSET_7 0xa13c #define mmPA_CL_VPORT_YOFFSET_8 0xa142 #define mmPA_CL_VPORT_YOFFSET_9 0xa148 #define mmPA_CL_VPORT_YOFFSET_10 0xa14e #define mmPA_CL_VPORT_YOFFSET_11 0xa154 #define mmPA_CL_VPORT_YOFFSET_12 0xa15a #define mmPA_CL_VPORT_YOFFSET_13 0xa160 #define mmPA_CL_VPORT_YOFFSET_14 0xa166 #define mmPA_CL_VPORT_YOFFSET_15 0xa16c #define mmPA_CL_VPORT_ZSCALE_1 0xa119 #define mmPA_CL_VPORT_ZSCALE_2 0xa11f #define mmPA_CL_VPORT_ZSCALE_3 0xa125 #define mmPA_CL_VPORT_ZSCALE_4 0xa12b #define mmPA_CL_VPORT_ZSCALE_5 0xa131 #define mmPA_CL_VPORT_ZSCALE_6 0xa137 #define mmPA_CL_VPORT_ZSCALE_7 0xa13d #define mmPA_CL_VPORT_ZSCALE_8 0xa143 #define mmPA_CL_VPORT_ZSCALE_9 0xa149 #define mmPA_CL_VPORT_ZSCALE_10 0xa14f #define mmPA_CL_VPORT_ZSCALE_11 0xa155 #define mmPA_CL_VPORT_ZSCALE_12 0xa15b #define mmPA_CL_VPORT_ZSCALE_13 0xa161 #define mmPA_CL_VPORT_ZSCALE_14 0xa167 #define mmPA_CL_VPORT_ZSCALE_15 0xa16d #define mmPA_CL_VPORT_ZOFFSET_1 0xa11a #define mmPA_CL_VPORT_ZOFFSET_2 0xa120 #define mmPA_CL_VPORT_ZOFFSET_3 0xa126 #define mmPA_CL_VPORT_ZOFFSET_4 0xa12c #define mmPA_CL_VPORT_ZOFFSET_5 0xa132 #define mmPA_CL_VPORT_ZOFFSET_6 0xa138 #define mmPA_CL_VPORT_ZOFFSET_7 0xa13e #define mmPA_CL_VPORT_ZOFFSET_8 0xa144 #define mmPA_CL_VPORT_ZOFFSET_9 0xa14a #define mmPA_CL_VPORT_ZOFFSET_10 0xa150 #define mmPA_CL_VPORT_ZOFFSET_11 0xa156 #define mmPA_CL_VPORT_ZOFFSET_12 0xa15c #define mmPA_CL_VPORT_ZOFFSET_13 0xa162 #define mmPA_CL_VPORT_ZOFFSET_14 0xa168 #define mmPA_CL_VPORT_ZOFFSET_15 0xa16e #define mmPA_CL_VTE_CNTL 0xa206 #define mmPA_CL_VS_OUT_CNTL 0xa207 #define mmPA_CL_NANINF_CNTL 0xa208 #define mmPA_CL_CLIP_CNTL 0xa204 #define mmPA_CL_GB_VERT_CLIP_ADJ 0xa2fa #define mmPA_CL_GB_VERT_DISC_ADJ 0xa2fb #define mmPA_CL_GB_HORZ_CLIP_ADJ 0xa2fc #define mmPA_CL_GB_HORZ_DISC_ADJ 0xa2fd #define mmPA_CL_UCP_0_X 0xa16f #define mmPA_CL_UCP_0_Y 0xa170 #define mmPA_CL_UCP_0_Z 0xa171 #define mmPA_CL_UCP_0_W 0xa172 #define mmPA_CL_UCP_1_X 0xa173 #define mmPA_CL_UCP_1_Y 0xa174 #define mmPA_CL_UCP_1_Z 0xa175 #define mmPA_CL_UCP_1_W 0xa176 #define mmPA_CL_UCP_2_X 0xa177 #define mmPA_CL_UCP_2_Y 0xa178 #define mmPA_CL_UCP_2_Z 0xa179 #define mmPA_CL_UCP_2_W 0xa17a #define mmPA_CL_UCP_3_X 0xa17b #define mmPA_CL_UCP_3_Y 0xa17c #define mmPA_CL_UCP_3_Z 0xa17d #define mmPA_CL_UCP_3_W 0xa17e #define mmPA_CL_UCP_4_X 0xa17f #define mmPA_CL_UCP_4_Y 0xa180 #define mmPA_CL_UCP_4_Z 0xa181 #define mmPA_CL_UCP_4_W 0xa182 #define mmPA_CL_UCP_5_X 0xa183 #define mmPA_CL_UCP_5_Y 0xa184 #define mmPA_CL_UCP_5_Z 0xa185 #define mmPA_CL_UCP_5_W 0xa186 #define mmPA_CL_POINT_X_RAD 0xa1f5 #define mmPA_CL_POINT_Y_RAD 0xa1f6 #define mmPA_CL_POINT_SIZE 0xa1f7 #define mmPA_CL_POINT_CULL_RAD 0xa1f8 #define mmPA_CL_ENHANCE 0x2285 #define mmPA_CL_RESET_DEBUG 0x2286 #define mmPA_SU_VTX_CNTL 0xa2f9 #define mmPA_SU_POINT_SIZE 0xa280 #define mmPA_SU_POINT_MINMAX 0xa281 #define mmPA_SU_LINE_CNTL 0xa282 #define mmPA_SU_LINE_STIPPLE_CNTL 0xa209 #define mmPA_SU_LINE_STIPPLE_SCALE 0xa20a #define mmPA_SU_PRIM_FILTER_CNTL 0xa20b #define mmPA_SU_SC_MODE_CNTL 0xa205 #define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xa2de #define mmPA_SU_POLY_OFFSET_CLAMP 0xa2df #define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xa2e0 #define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xa2e1 #define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xa2e2 #define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xa2e3 #define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xa08d #define mmPA_SU_LINE_STIPPLE_VALUE 0xc280 #define mmPA_SU_PERFCOUNTER0_SELECT 0xd900 #define mmPA_SU_PERFCOUNTER0_SELECT1 0xd901 #define mmPA_SU_PERFCOUNTER1_SELECT 0xd902 #define mmPA_SU_PERFCOUNTER1_SELECT1 0xd903 #define mmPA_SU_PERFCOUNTER2_SELECT 0xd904 #define mmPA_SU_PERFCOUNTER3_SELECT 0xd905 #define mmPA_SU_PERFCOUNTER0_LO 0xd100 #define mmPA_SU_PERFCOUNTER0_HI 0xd101 #define mmPA_SU_PERFCOUNTER1_LO 0xd102 #define mmPA_SU_PERFCOUNTER1_HI 0xd103 #define mmPA_SU_PERFCOUNTER2_LO 0xd104 #define mmPA_SU_PERFCOUNTER2_HI 0xd105 #define mmPA_SU_PERFCOUNTER3_LO 0xd106 #define mmPA_SU_PERFCOUNTER3_HI 0xd107 #define mmPA_SC_AA_CONFIG 0xa2f8 #define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xa30e #define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xa30f #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xa2fe #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xa2ff #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xa300 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xa301 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xa302 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xa303 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xa304 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xa305 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xa306 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xa307 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xa308 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xa309 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xa30a #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xa30b #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xa30c #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xa30d #define mmPA_SC_CENTROID_PRIORITY_0 0xa2f5 #define mmPA_SC_CENTROID_PRIORITY_1 0xa2f6 #define mmPA_SC_CLIPRECT_0_TL 0xa084 #define mmPA_SC_CLIPRECT_0_BR 0xa085 #define mmPA_SC_CLIPRECT_1_TL 0xa086 #define mmPA_SC_CLIPRECT_1_BR 0xa087 #define mmPA_SC_CLIPRECT_2_TL 0xa088 #define mmPA_SC_CLIPRECT_2_BR 0xa089 #define mmPA_SC_CLIPRECT_3_TL 0xa08a #define mmPA_SC_CLIPRECT_3_BR 0xa08b #define mmPA_SC_CLIPRECT_RULE 0xa083 #define mmPA_SC_EDGERULE 0xa08c #define mmPA_SC_LINE_CNTL 0xa2f7 #define mmPA_SC_LINE_STIPPLE 0xa283 #define mmPA_SC_MODE_CNTL_0 0xa292 #define mmPA_SC_MODE_CNTL_1 0xa293 #define mmPA_SC_RASTER_CONFIG 0xa0d4 #define mmPA_SC_RASTER_CONFIG_1 0xa0d5 #define mmPA_SC_SCREEN_EXTENT_CONTROL 0xa0d6 #define mmPA_SC_GENERIC_SCISSOR_TL 0xa090 #define mmPA_SC_GENERIC_SCISSOR_BR 0xa091 #define mmPA_SC_SCREEN_SCISSOR_TL 0xa00c #define mmPA_SC_SCREEN_SCISSOR_BR 0xa00d #define mmPA_SC_WINDOW_OFFSET 0xa080 #define mmPA_SC_WINDOW_SCISSOR_TL 0xa081 #define mmPA_SC_WINDOW_SCISSOR_BR 0xa082 #define mmPA_SC_VPORT_SCISSOR_0_TL 0xa094 #define mmPA_SC_VPORT_SCISSOR_1_TL 0xa096 #define mmPA_SC_VPORT_SCISSOR_2_TL 0xa098 #define mmPA_SC_VPORT_SCISSOR_3_TL 0xa09a #define mmPA_SC_VPORT_SCISSOR_4_TL 0xa09c #define mmPA_SC_VPORT_SCISSOR_5_TL 0xa09e #define mmPA_SC_VPORT_SCISSOR_6_TL 0xa0a0 #define mmPA_SC_VPORT_SCISSOR_7_TL 0xa0a2 #define mmPA_SC_VPORT_SCISSOR_8_TL 0xa0a4 #define mmPA_SC_VPORT_SCISSOR_9_TL 0xa0a6 #define mmPA_SC_VPORT_SCISSOR_10_TL 0xa0a8 #define mmPA_SC_VPORT_SCISSOR_11_TL 0xa0aa #define mmPA_SC_VPORT_SCISSOR_12_TL 0xa0ac #define mmPA_SC_VPORT_SCISSOR_13_TL 0xa0ae #define mmPA_SC_VPORT_SCISSOR_14_TL 0xa0b0 #define mmPA_SC_VPORT_SCISSOR_15_TL 0xa0b2 #define mmPA_SC_VPORT_SCISSOR_0_BR 0xa095 #define mmPA_SC_VPORT_SCISSOR_1_BR 0xa097 #define mmPA_SC_VPORT_SCISSOR_2_BR 0xa099 #define mmPA_SC_VPORT_SCISSOR_3_BR 0xa09b #define mmPA_SC_VPORT_SCISSOR_4_BR 0xa09d #define mmPA_SC_VPORT_SCISSOR_5_BR 0xa09f #define mmPA_SC_VPORT_SCISSOR_6_BR 0xa0a1 #define mmPA_SC_VPORT_SCISSOR_7_BR 0xa0a3 #define mmPA_SC_VPORT_SCISSOR_8_BR 0xa0a5 #define mmPA_SC_VPORT_SCISSOR_9_BR 0xa0a7 #define mmPA_SC_VPORT_SCISSOR_10_BR 0xa0a9 #define mmPA_SC_VPORT_SCISSOR_11_BR 0xa0ab #define mmPA_SC_VPORT_SCISSOR_12_BR 0xa0ad #define mmPA_SC_VPORT_SCISSOR_13_BR 0xa0af #define mmPA_SC_VPORT_SCISSOR_14_BR 0xa0b1 #define mmPA_SC_VPORT_SCISSOR_15_BR 0xa0b3 #define mmPA_SC_VPORT_ZMIN_0 0xa0b4 #define mmPA_SC_VPORT_ZMIN_1 0xa0b6 #define mmPA_SC_VPORT_ZMIN_2 0xa0b8 #define mmPA_SC_VPORT_ZMIN_3 0xa0ba #define mmPA_SC_VPORT_ZMIN_4 0xa0bc #define mmPA_SC_VPORT_ZMIN_5 0xa0be #define mmPA_SC_VPORT_ZMIN_6 0xa0c0 #define mmPA_SC_VPORT_ZMIN_7 0xa0c2 #define mmPA_SC_VPORT_ZMIN_8 0xa0c4 #define mmPA_SC_VPORT_ZMIN_9 0xa0c6 #define mmPA_SC_VPORT_ZMIN_10 0xa0c8 #define mmPA_SC_VPORT_ZMIN_11 0xa0ca #define mmPA_SC_VPORT_ZMIN_12 0xa0cc #define mmPA_SC_VPORT_ZMIN_13 0xa0ce #define mmPA_SC_VPORT_ZMIN_14 0xa0d0 #define mmPA_SC_VPORT_ZMIN_15 0xa0d2 #define mmPA_SC_VPORT_ZMAX_0 0xa0b5 #define mmPA_SC_VPORT_ZMAX_1 0xa0b7 #define mmPA_SC_VPORT_ZMAX_2 0xa0b9 #define mmPA_SC_VPORT_ZMAX_3 0xa0bb #define mmPA_SC_VPORT_ZMAX_4 0xa0bd #define mmPA_SC_VPORT_ZMAX_5 0xa0bf #define mmPA_SC_VPORT_ZMAX_6 0xa0c1 #define mmPA_SC_VPORT_ZMAX_7 0xa0c3 #define mmPA_SC_VPORT_ZMAX_8 0xa0c5 #define mmPA_SC_VPORT_ZMAX_9 0xa0c7 #define mmPA_SC_VPORT_ZMAX_10 0xa0c9 #define mmPA_SC_VPORT_ZMAX_11 0xa0cb #define mmPA_SC_VPORT_ZMAX_12 0xa0cd #define mmPA_SC_VPORT_ZMAX_13 0xa0cf #define mmPA_SC_VPORT_ZMAX_14 0xa0d1 #define mmPA_SC_VPORT_ZMAX_15 0xa0d3 #define mmPA_SC_ENHANCE 0x22fc #define mmPA_SC_FIFO_SIZE 0x22f3 #define mmPA_SC_IF_FIFO_SIZE 0x22f5 #define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22c9 #define mmPA_SC_LINE_STIPPLE_STATE 0xc281 #define mmPA_SC_SCREEN_EXTENT_MIN_0 0xc284 #define mmPA_SC_SCREEN_EXTENT_MAX_0 0xc285 #define mmPA_SC_SCREEN_EXTENT_MIN_1 0xc286 #define mmPA_SC_SCREEN_EXTENT_MAX_1 0xc28b #define mmPA_SC_PERFCOUNTER0_SELECT 0xd940 #define mmPA_SC_PERFCOUNTER0_SELECT1 0xd941 #define mmPA_SC_PERFCOUNTER1_SELECT 0xd942 #define mmPA_SC_PERFCOUNTER2_SELECT 0xd943 #define mmPA_SC_PERFCOUNTER3_SELECT 0xd944 #define mmPA_SC_PERFCOUNTER4_SELECT 0xd945 #define mmPA_SC_PERFCOUNTER5_SELECT 0xd946 #define mmPA_SC_PERFCOUNTER6_SELECT 0xd947 #define mmPA_SC_PERFCOUNTER7_SELECT 0xd948 #define mmPA_SC_PERFCOUNTER0_LO 0xd140 #define mmPA_SC_PERFCOUNTER0_HI 0xd141 #define mmPA_SC_PERFCOUNTER1_LO 0xd142 #define mmPA_SC_PERFCOUNTER1_HI 0xd143 #define mmPA_SC_PERFCOUNTER2_LO 0xd144 #define mmPA_SC_PERFCOUNTER2_HI 0xd145 #define mmPA_SC_PERFCOUNTER3_LO 0xd146 #define mmPA_SC_PERFCOUNTER3_HI 0xd147 #define mmPA_SC_PERFCOUNTER4_LO 0xd148 #define mmPA_SC_PERFCOUNTER4_HI 0xd149 #define mmPA_SC_PERFCOUNTER5_LO 0xd14a #define mmPA_SC_PERFCOUNTER5_HI 0xd14b #define mmPA_SC_PERFCOUNTER6_LO 0xd14c #define mmPA_SC_PERFCOUNTER6_HI 0xd14d #define mmPA_SC_PERFCOUNTER7_LO 0xd14e #define mmPA_SC_PERFCOUNTER7_HI 0xd14f #define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xc2a0 #define mmPA_SC_P3D_TRAP_SCREEN_H 0xc2a1 #define mmPA_SC_P3D_TRAP_SCREEN_V 0xc2a2 #define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xc2a3 #define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xc2a4 #define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xc2a8 #define mmPA_SC_HP3D_TRAP_SCREEN_H 0xc2a9 #define mmPA_SC_HP3D_TRAP_SCREEN_V 0xc2aa #define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xc2ab #define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xc2ac #define mmPA_SC_TRAP_SCREEN_HV_EN 0xc2b0 #define mmPA_SC_TRAP_SCREEN_H 0xc2b1 #define mmPA_SC_TRAP_SCREEN_V 0xc2b2 #define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xc2b3 #define mmPA_SC_TRAP_SCREEN_COUNT 0xc2b4 #define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22c0 #define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22c1 #define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22c2 #define mmPA_CL_CNTL_STATUS 0x2284 #define mmPA_SU_CNTL_STATUS 0x2294 #define mmPA_SC_FIFO_DEPTH_CNTL 0x2295 #define mmCGTT_PA_CLK_CTRL 0xf088 #define mmCGTT_SC_CLK_CTRL 0xf089 #define mmPA_SU_DEBUG_CNTL 0x2280 #define mmPA_SU_DEBUG_DATA 0x2281 #define mmPA_SC_DEBUG_CNTL 0x22f6 #define mmPA_SC_DEBUG_DATA 0x22f7 #define ixCLIPPER_DEBUG_REG00 0x0 #define ixCLIPPER_DEBUG_REG01 0x1 #define ixCLIPPER_DEBUG_REG02 0x2 #define ixCLIPPER_DEBUG_REG03 0x3 #define ixCLIPPER_DEBUG_REG04 0x4 #define ixCLIPPER_DEBUG_REG05 0x5 #define ixCLIPPER_DEBUG_REG06 0x6 #define ixCLIPPER_DEBUG_REG07 0x7 #define ixCLIPPER_DEBUG_REG08 0x8 #define ixCLIPPER_DEBUG_REG09 0x9 #define ixCLIPPER_DEBUG_REG10 0xa #define ixCLIPPER_DEBUG_REG11 0xb #define ixCLIPPER_DEBUG_REG12 0xc #define ixCLIPPER_DEBUG_REG13 0xd #define ixCLIPPER_DEBUG_REG14 0xe #define ixCLIPPER_DEBUG_REG15 0xf #define ixCLIPPER_DEBUG_REG16 0x10 #define ixCLIPPER_DEBUG_REG17 0x11 #define ixCLIPPER_DEBUG_REG18 0x12 #define ixCLIPPER_DEBUG_REG19 0x13 #define ixSXIFCCG_DEBUG_REG0 0x14 #define ixSXIFCCG_DEBUG_REG1 0x15 #define ixSXIFCCG_DEBUG_REG2 0x16 #define ixSXIFCCG_DEBUG_REG3 0x17 #define ixSETUP_DEBUG_REG0 0x18 #define ixSETUP_DEBUG_REG1 0x19 #define ixSETUP_DEBUG_REG2 0x1a #define ixSETUP_DEBUG_REG3 0x1b #define ixSETUP_DEBUG_REG4 0x1c #define ixSETUP_DEBUG_REG5 0x1d #define ixPA_SC_DEBUG_REG0 0x0 #define ixPA_SC_DEBUG_REG1 0x1 #define mmCOMPUTE_DISPATCH_INITIATOR 0x2e00 #define mmCOMPUTE_DIM_X 0x2e01 #define mmCOMPUTE_DIM_Y 0x2e02 #define mmCOMPUTE_DIM_Z 0x2e03 #define mmCOMPUTE_START_X 0x2e04 #define mmCOMPUTE_START_Y 0x2e05 #define mmCOMPUTE_START_Z 0x2e06 #define mmCOMPUTE_NUM_THREAD_X 0x2e07 #define mmCOMPUTE_NUM_THREAD_Y 0x2e08 #define mmCOMPUTE_NUM_THREAD_Z 0x2e09 #define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2e0a #define mmCOMPUTE_PERFCOUNT_ENABLE 0x2e0b #define mmCOMPUTE_PGM_LO 0x2e0c #define mmCOMPUTE_PGM_HI 0x2e0d #define mmCOMPUTE_TBA_LO 0x2e0e #define mmCOMPUTE_TBA_HI 0x2e0f #define mmCOMPUTE_TMA_LO 0x2e10 #define mmCOMPUTE_TMA_HI 0x2e11 #define mmCOMPUTE_PGM_RSRC1 0x2e12 #define mmCOMPUTE_PGM_RSRC2 0x2e13 #define mmCOMPUTE_VMID 0x2e14 #define mmCOMPUTE_RESOURCE_LIMITS 0x2e15 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2e16 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2e17 #define mmCOMPUTE_TMPRING_SIZE 0x2e18 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2e19 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2e1a #define mmCOMPUTE_RESTART_X 0x2e1b #define mmCOMPUTE_RESTART_Y 0x2e1c #define mmCOMPUTE_RESTART_Z 0x2e1d #define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2e1e #define mmCOMPUTE_MISC_RESERVED 0x2e1f #define mmCOMPUTE_USER_DATA_0 0x2e40 #define mmCOMPUTE_USER_DATA_1 0x2e41 #define mmCOMPUTE_USER_DATA_2 0x2e42 #define mmCOMPUTE_USER_DATA_3 0x2e43 #define mmCOMPUTE_USER_DATA_4 0x2e44 #define mmCOMPUTE_USER_DATA_5 0x2e45 #define mmCOMPUTE_USER_DATA_6 0x2e46 #define mmCOMPUTE_USER_DATA_7 0x2e47 #define mmCOMPUTE_USER_DATA_8 0x2e48 #define mmCOMPUTE_USER_DATA_9 0x2e49 #define mmCOMPUTE_USER_DATA_10 0x2e4a #define mmCOMPUTE_USER_DATA_11 0x2e4b #define mmCOMPUTE_USER_DATA_12 0x2e4c #define mmCOMPUTE_USER_DATA_13 0x2e4d #define mmCOMPUTE_USER_DATA_14 0x2e4e #define mmCOMPUTE_USER_DATA_15 0x2e4f #define mmCSPRIV_CONNECT 0x0 #define mmCSPRIV_THREAD_TRACE_TG0 0x1e #define mmCSPRIV_THREAD_TRACE_TG1 0x1e #define mmCSPRIV_THREAD_TRACE_TG2 0x1e #define mmCSPRIV_THREAD_TRACE_TG3 0x1e #define mmCSPRIV_THREAD_TRACE_EVENT 0x1f #define mmRLC_CNTL 0x30c0 #define mmRLC_DEBUG_SELECT 0x30c1 #define mmRLC_DEBUG 0x30c2 #define mmRLC_MC_CNTL 0x30c3 #define mmRLC_STAT 0x30c4 #define mmRLC_SAFE_MODE 0x313a #define mmRLC_SOFT_RESET_GPU 0x30c5 #define mmRLC_MEM_SLP_CNTL 0x30c6 #define mmRLC_PERFMON_CNTL 0xdcc0 #define mmRLC_PERFCOUNTER0_SELECT 0xdcc1 #define mmRLC_PERFCOUNTER1_SELECT 0xdcc2 #define mmRLC_PERFCOUNTER0_LO 0xd480 #define mmRLC_PERFCOUNTER1_LO 0xd482 #define mmRLC_PERFCOUNTER0_HI 0xd481 #define mmRLC_PERFCOUNTER1_HI 0xd483 #define mmCGTT_RLC_CLK_CTRL 0xf0b8 #define mmRLC_LB_CNTL 0x30d9 #define mmRLC_LB_CNTR_MAX 0x30d2 #define mmRLC_LB_CNTR_INIT 0x30db #define mmRLC_LOAD_BALANCE_CNTR 0x30dc #define mmRLC_SAVE_AND_RESTORE_BASE 0x30dd #define mmRLC_JUMP_TABLE_RESTORE 0x30de #define mmRLC_DRIVER_CPDMA_STATUS 0x30de #define mmRLC_PG_DELAY_2 0x30df #define mmRLC_GPM_DEBUG_SELECT 0x30e0 #define mmRLC_GPM_DEBUG 0x30e1 #define mmRLC_GPM_UCODE_ADDR 0x30e2 #define mmRLC_GPM_UCODE_DATA 0x30e3 #define mmRLC_GPU_CLOCK_COUNT_LSB 0x30e4 #define mmRLC_GPU_CLOCK_COUNT_MSB 0x30e5 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x30e6 #define mmRLC_UCODE_CNTL 0x30e7 #define mmRLC_GPM_STAT 0x3100 #define mmRLC_GPU_CLOCK_32_RES_SEL 0x3101 #define mmRLC_GPU_CLOCK_32 0x3102 #define mmRLC_PG_CNTL 0x3103 #define mmRLC_GPM_THREAD_PRIORITY 0x3104 #define mmRLC_GPM_THREAD_ENABLE 0x3105 #define mmRLC_GPM_VMID_THREAD0 0x3106 #define mmRLC_GPM_VMID_THREAD1 0x3107 #define mmRLC_CGTT_MGCG_OVERRIDE 0x3108 #define mmRLC_CGCG_CGLS_CTRL 0x3109 #define mmRLC_CGCG_RAMP_CTRL 0x310a #define mmRLC_DYN_PG_STATUS 0x310b #define mmRLC_DYN_PG_REQUEST 0x310c #define mmRLC_PG_DELAY 0x310d #define mmRLC_CU_STATUS 0x310e #define mmRLC_LB_INIT_CU_MASK 0x310f #define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x3110 #define mmRLC_LB_PARAMS 0x3111 #define mmRLC_THREAD1_DELAY 0x3112 #define mmRLC_PG_ALWAYS_ON_CU_MASK 0x3113 #define mmRLC_MAX_PG_CU 0x3114 #define mmRLC_AUTO_PG_CTRL 0x3115 #define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x3116 #define mmRLC_SMU_PG_CTRL 0x3117 #define mmRLC_SMU_PG_WAKE_UP_CTRL 0x3118 #define mmRLC_SERDES_RD_MASTER_INDEX 0x3119 #define mmRLC_SERDES_RD_DATA_0 0x311a #define mmRLC_SERDES_RD_DATA_1 0x311b #define mmRLC_SERDES_RD_DATA_2 0x311c #define mmRLC_SERDES_WR_CU_MASTER_MASK 0x311d #define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x311e #define mmRLC_SERDES_WR_CTRL 0x311f #define mmRLC_SERDES_WR_DATA 0x3120 #define mmRLC_SERDES_CU_MASTER_BUSY 0x3121 #define mmRLC_SERDES_NONCU_MASTER_BUSY 0x3122 #define mmRLC_GPM_GENERAL_0 0x3123 #define mmRLC_GPM_GENERAL_1 0x3124 #define mmRLC_GPM_GENERAL_2 0x3125 #define mmRLC_GPM_GENERAL_3 0x3126 #define mmRLC_GPM_GENERAL_4 0x3127 #define mmRLC_GPM_GENERAL_5 0x3128 #define mmRLC_GPM_GENERAL_6 0x3129 #define mmRLC_GPM_GENERAL_7 0x312a #define mmRLC_GPM_CU_PD_TIMEOUT 0x312b #define mmRLC_GPM_SCRATCH_ADDR 0x312c #define mmRLC_GPM_SCRATCH_DATA 0x312d #define mmRLC_STATIC_PG_STATUS 0x312e #define mmRLC_GPM_PERF_COUNT_0 0x312f #define mmRLC_GPM_PERF_COUNT_1 0x3130 #define mmRLC_GPR_REG1 0x3139 #define mmRLC_GPR_REG2 0x313a #define mmRLC_SPM_VMID 0x3131 #define mmRLC_SPM_INT_CNTL 0x3132 #define mmRLC_SPM_INT_STATUS 0x3133 #define mmRLC_SPM_DEBUG_SELECT 0x3134 #define mmRLC_SPM_DEBUG 0x3135 #define mmRLC_GPM_LOG_ADDR 0x3136 #define mmRLC_GPM_LOG_SIZE 0x3137 #define mmRLC_GPM_LOG_CONT 0x3138 #define mmRLC_SPM_PERFMON_CNTL 0xdc80 #define mmRLC_SPM_PERFMON_RING_BASE_LO 0xdc81 #define mmRLC_SPM_PERFMON_RING_BASE_HI 0xdc82 #define mmRLC_SPM_PERFMON_RING_SIZE 0xdc83 #define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xdc84 #define mmRLC_SPM_SE_MUXSEL_ADDR 0xdc85 #define mmRLC_SPM_SE_MUXSEL_DATA 0xdc86 #define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xdc87 #define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xdc88 #define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xdc89 #define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xdc8a #define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xdc8b #define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xdc8c #define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xdc8d #define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xdc8e #define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xdc90 #define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xdc91 #define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xdc92 #define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xdc93 #define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xdc94 #define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xdc95 #define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xdc96 #define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xdc97 #define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xdc98 #define mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY 0xdc99 #define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xdc9a #define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xdc9b #define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xdc9c #define mmRLC_SPM_RING_RDPTR 0xdc9d #define mmRLC_SPM_SEGMENT_THRESHOLD 0xdc9e #define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY 0xdc9f #define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY 0xdca0 #define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY 0xdca1 #define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY 0xdca2 #define mmSPI_PS_INPUT_CNTL_0 0xa191 #define mmSPI_PS_INPUT_CNTL_1 0xa192 #define mmSPI_PS_INPUT_CNTL_2 0xa193 #define mmSPI_PS_INPUT_CNTL_3 0xa194 #define mmSPI_PS_INPUT_CNTL_4 0xa195 #define mmSPI_PS_INPUT_CNTL_5 0xa196 #define mmSPI_PS_INPUT_CNTL_6 0xa197 #define mmSPI_PS_INPUT_CNTL_7 0xa198 #define mmSPI_PS_INPUT_CNTL_8 0xa199 #define mmSPI_PS_INPUT_CNTL_9 0xa19a #define mmSPI_PS_INPUT_CNTL_10 0xa19b #define mmSPI_PS_INPUT_CNTL_11 0xa19c #define mmSPI_PS_INPUT_CNTL_12 0xa19d #define mmSPI_PS_INPUT_CNTL_13 0xa19e #define mmSPI_PS_INPUT_CNTL_14 0xa19f #define mmSPI_PS_INPUT_CNTL_15 0xa1a0 #define mmSPI_PS_INPUT_CNTL_16 0xa1a1 #define mmSPI_PS_INPUT_CNTL_17 0xa1a2 #define mmSPI_PS_INPUT_CNTL_18 0xa1a3 #define mmSPI_PS_INPUT_CNTL_19 0xa1a4 #define mmSPI_PS_INPUT_CNTL_20 0xa1a5 #define mmSPI_PS_INPUT_CNTL_21 0xa1a6 #define mmSPI_PS_INPUT_CNTL_22 0xa1a7 #define mmSPI_PS_INPUT_CNTL_23 0xa1a8 #define mmSPI_PS_INPUT_CNTL_24 0xa1a9 #define mmSPI_PS_INPUT_CNTL_25 0xa1aa #define mmSPI_PS_INPUT_CNTL_26 0xa1ab #define mmSPI_PS_INPUT_CNTL_27 0xa1ac #define mmSPI_PS_INPUT_CNTL_28 0xa1ad #define mmSPI_PS_INPUT_CNTL_29 0xa1ae #define mmSPI_PS_INPUT_CNTL_30 0xa1af #define mmSPI_PS_INPUT_CNTL_31 0xa1b0 #define mmSPI_VS_OUT_CONFIG 0xa1b1 #define mmSPI_PS_INPUT_ENA 0xa1b3 #define mmSPI_PS_INPUT_ADDR 0xa1b4 #define mmSPI_INTERP_CONTROL_0 0xa1b5 #define mmSPI_PS_IN_CONTROL 0xa1b6 #define mmSPI_BARYC_CNTL 0xa1b8 #define mmSPI_TMPRING_SIZE 0xa1ba #define mmSPI_SHADER_POS_FORMAT 0xa1c3 #define mmSPI_SHADER_Z_FORMAT 0xa1c4 #define mmSPI_SHADER_COL_FORMAT 0xa1c5 #define mmSPI_ARB_PRIORITY 0x31c0 #define mmSPI_ARB_CYCLES_0 0x31c1 #define mmSPI_ARB_CYCLES_1 0x31c2 #define mmSPI_CDBG_SYS_GFX 0x31c3 #define mmSPI_CDBG_SYS_HP3D 0x31c4 #define mmSPI_CDBG_SYS_CS0 0x31c5 #define mmSPI_CDBG_SYS_CS1 0x31c6 #define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7 #define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31c8 #define mmSPI_WCL_PIPE_PERCENT_CS0 0x31c9 #define mmSPI_WCL_PIPE_PERCENT_CS1 0x31ca #define mmSPI_WCL_PIPE_PERCENT_CS2 0x31cb #define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc #define mmSPI_WCL_PIPE_PERCENT_CS4 0x31cd #define mmSPI_WCL_PIPE_PERCENT_CS5 0x31ce #define mmSPI_WCL_PIPE_PERCENT_CS6 0x31cf #define mmSPI_WCL_PIPE_PERCENT_CS7 0x31d0 #define mmSPI_GDBG_WAVE_CNTL 0x31d1 #define mmSPI_GDBG_TRAP_CONFIG 0x31d2 #define mmSPI_GDBG_TRAP_MASK 0x31d3 #define mmSPI_GDBG_TBA_LO 0x31d4 #define mmSPI_GDBG_TBA_HI 0x31d5 #define mmSPI_GDBG_TMA_LO 0x31d6 #define mmSPI_GDBG_TMA_HI 0x31d7 #define mmSPI_GDBG_TRAP_DATA0 0x31d8 #define mmSPI_GDBG_TRAP_DATA1 0x31d9 #define mmSPI_RESET_DEBUG 0x31da #define mmSPI_COMPUTE_QUEUE_RESET 0x31db #define mmSPI_RESOURCE_RESERVE_CU_0 0x31dc #define mmSPI_RESOURCE_RESERVE_CU_1 0x31dd #define mmSPI_RESOURCE_RESERVE_CU_2 0x31de #define mmSPI_RESOURCE_RESERVE_CU_3 0x31df #define mmSPI_RESOURCE_RESERVE_CU_4 0x31e0 #define mmSPI_RESOURCE_RESERVE_CU_5 0x31e1 #define mmSPI_RESOURCE_RESERVE_CU_6 0x31e2 #define mmSPI_RESOURCE_RESERVE_CU_7 0x31e3 #define mmSPI_RESOURCE_RESERVE_CU_8 0x31e4 #define mmSPI_RESOURCE_RESERVE_CU_9 0x31e5 #define mmSPI_RESOURCE_RESERVE_CU_10 0x31f0 #define mmSPI_RESOURCE_RESERVE_CU_11 0x31f1 #define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31e6 #define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31e7 #define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31e8 #define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31e9 #define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31ea #define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31eb #define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31ec #define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ed #define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31ee #define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31ef #define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x31f2 #define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x31f3 #define mmSPI_PS_MAX_WAVE_ID 0x243a #define mmSPI_CONFIG_CNTL 0x2440 #define mmSPI_DEBUG_CNTL 0x2441 #define mmSPI_DEBUG_READ 0x2442 #define mmSPI_PERFCOUNTER0_SELECT 0xd980 #define mmSPI_PERFCOUNTER1_SELECT 0xd981 #define mmSPI_PERFCOUNTER2_SELECT 0xd982 #define mmSPI_PERFCOUNTER3_SELECT 0xd983 #define mmSPI_PERFCOUNTER0_SELECT1 0xd984 #define mmSPI_PERFCOUNTER1_SELECT1 0xd985 #define mmSPI_PERFCOUNTER2_SELECT1 0xd986 #define mmSPI_PERFCOUNTER3_SELECT1 0xd987 #define mmSPI_PERFCOUNTER4_SELECT 0xd988 #define mmSPI_PERFCOUNTER5_SELECT 0xd989 #define mmSPI_PERFCOUNTER_BINS 0xd98a #define mmSPI_PERFCOUNTER0_HI 0xd180 #define mmSPI_PERFCOUNTER0_LO 0xd181 #define mmSPI_PERFCOUNTER1_HI 0xd182 #define mmSPI_PERFCOUNTER1_LO 0xd183 #define mmSPI_PERFCOUNTER2_HI 0xd184 #define mmSPI_PERFCOUNTER2_LO 0xd185 #define mmSPI_PERFCOUNTER3_HI 0xd186 #define mmSPI_PERFCOUNTER3_LO 0xd187 #define mmSPI_PERFCOUNTER4_HI 0xd188 #define mmSPI_PERFCOUNTER4_LO 0xd189 #define mmSPI_PERFCOUNTER5_HI 0xd18a #define mmSPI_PERFCOUNTER5_LO 0xd18b #define mmSPI_CONFIG_CNTL_1 0x244f #define mmSPI_DEBUG_BUSY 0x2450 #define mmCGTS_SM_CTRL_REG 0xf000 #define mmCGTS_RD_CTRL_REG 0xf001 #define mmCGTS_RD_REG 0xf002 #define mmCGTS_TCC_DISABLE 0xf003 #define mmCGTS_USER_TCC_DISABLE 0xf004 #define mmCGTS_CU0_SP0_CTRL_REG 0xf008 #define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xf009 #define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a #define mmCGTS_CU0_SP1_CTRL_REG 0xf00b #define mmCGTS_CU0_TD_TCP_CTRL_REG 0xf00c #define mmCGTS_CU1_SP0_CTRL_REG 0xf00d #define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xf00e #define mmCGTS_CU1_TA_CTRL_REG 0xf00f #define mmCGTS_CU1_SP1_CTRL_REG 0xf010 #define mmCGTS_CU1_TD_TCP_CTRL_REG 0xf011 #define mmCGTS_CU2_SP0_CTRL_REG 0xf012 #define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xf013 #define mmCGTS_CU2_TA_CTRL_REG 0xf014 #define mmCGTS_CU2_SP1_CTRL_REG 0xf015 #define mmCGTS_CU2_TD_TCP_CTRL_REG 0xf016 #define mmCGTS_CU3_SP0_CTRL_REG 0xf017 #define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xf018 #define mmCGTS_CU3_TA_CTRL_REG 0xf019 #define mmCGTS_CU3_SP1_CTRL_REG 0xf01a #define mmCGTS_CU3_TD_TCP_CTRL_REG 0xf01b #define mmCGTS_CU4_SP0_CTRL_REG 0xf01c #define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xf01d #define mmCGTS_CU4_TA_SQC_CTRL_REG 0xf01e #define mmCGTS_CU4_SP1_CTRL_REG 0xf01f #define mmCGTS_CU4_TD_TCP_CTRL_REG 0xf020 #define mmCGTS_CU5_SP0_CTRL_REG 0xf021 #define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xf022 #define mmCGTS_CU5_TA_CTRL_REG 0xf023 #define mmCGTS_CU5_SP1_CTRL_REG 0xf024 #define mmCGTS_CU5_TD_TCP_CTRL_REG 0xf025 #define mmCGTS_CU6_SP0_CTRL_REG 0xf026 #define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xf027 #define mmCGTS_CU6_TA_CTRL_REG 0xf028 #define mmCGTS_CU6_SP1_CTRL_REG 0xf029 #define mmCGTS_CU6_TD_TCP_CTRL_REG 0xf02a #define mmCGTS_CU7_SP0_CTRL_REG 0xf02b #define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xf02c #define mmCGTS_CU7_TA_CTRL_REG 0xf02d #define mmCGTS_CU7_SP1_CTRL_REG 0xf02e #define mmCGTS_CU7_TD_TCP_CTRL_REG 0xf02f #define mmCGTS_CU8_SP0_CTRL_REG 0xf030 #define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xf031 #define mmCGTS_CU8_TA_SQC_CTRL_REG 0xf032 #define mmCGTS_CU8_SP1_CTRL_REG 0xf033 #define mmCGTS_CU8_TD_TCP_CTRL_REG 0xf034 #define mmCGTS_CU9_SP0_CTRL_REG 0xf035 #define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xf036 #define mmCGTS_CU9_TA_CTRL_REG 0xf037 #define mmCGTS_CU9_SP1_CTRL_REG 0xf038 #define mmCGTS_CU9_TD_TCP_CTRL_REG 0xf039 #define mmCGTS_CU10_SP0_CTRL_REG 0xf03a #define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xf03b #define mmCGTS_CU10_TA_CTRL_REG 0xf03c #define mmCGTS_CU10_SP1_CTRL_REG 0xf03d #define mmCGTS_CU10_TD_TCP_CTRL_REG 0xf03e #define mmCGTS_CU11_SP0_CTRL_REG 0xf03f #define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xf040 #define mmCGTS_CU11_TA_CTRL_REG 0xf041 #define mmCGTS_CU11_SP1_CTRL_REG 0xf042 #define mmCGTS_CU11_TD_TCP_CTRL_REG 0xf043 #define mmCGTS_CU12_SP0_CTRL_REG 0xf044 #define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xf045 #define mmCGTS_CU12_TA_SQC_CTRL_REG 0xf046 #define mmCGTS_CU12_SP1_CTRL_REG 0xf047 #define mmCGTS_CU12_TD_TCP_CTRL_REG 0xf048 #define mmCGTS_CU13_SP0_CTRL_REG 0xf049 #define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xf04a #define mmCGTS_CU13_TA_CTRL_REG 0xf04b #define mmCGTS_CU13_SP1_CTRL_REG 0xf04c #define mmCGTS_CU13_TD_TCP_CTRL_REG 0xf04d #define mmCGTS_CU14_SP0_CTRL_REG 0xf04e #define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xf04f #define mmCGTS_CU14_TA_CTRL_REG 0xf050 #define mmCGTS_CU14_SP1_CTRL_REG 0xf051 #define mmCGTS_CU14_TD_TCP_CTRL_REG 0xf052 #define mmCGTS_CU15_SP0_CTRL_REG 0xf053 #define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054 #define mmCGTS_CU15_TA_CTRL_REG 0xf055 #define mmCGTS_CU15_SP1_CTRL_REG 0xf056 #define mmCGTS_CU15_TD_TCP_CTRL_REG 0xf057 #define mmCGTT_SPI_CLK_CTRL 0xf080 #define mmCGTT_PC_CLK_CTRL 0xf081 #define mmCGTT_BCI_CLK_CTRL 0xf082 #define mmSPI_WF_LIFETIME_CNTL 0x24aa #define mmSPI_WF_LIFETIME_LIMIT_0 0x24ab #define mmSPI_WF_LIFETIME_LIMIT_1 0x24ac #define mmSPI_WF_LIFETIME_LIMIT_2 0x24ad #define mmSPI_WF_LIFETIME_LIMIT_3 0x24ae #define mmSPI_WF_LIFETIME_LIMIT_4 0x24af #define mmSPI_WF_LIFETIME_LIMIT_5 0x24b0 #define mmSPI_WF_LIFETIME_LIMIT_6 0x24b1 #define mmSPI_WF_LIFETIME_LIMIT_7 0x24b2 #define mmSPI_WF_LIFETIME_LIMIT_8 0x24b3 #define mmSPI_WF_LIFETIME_LIMIT_9 0x24b4 #define mmSPI_WF_LIFETIME_STATUS_0 0x24b5 #define mmSPI_WF_LIFETIME_STATUS_1 0x24b6 #define mmSPI_WF_LIFETIME_STATUS_2 0x24b7 #define mmSPI_WF_LIFETIME_STATUS_3 0x24b8 #define mmSPI_WF_LIFETIME_STATUS_4 0x24b9 #define mmSPI_WF_LIFETIME_STATUS_5 0x24ba #define mmSPI_WF_LIFETIME_STATUS_6 0x24bb #define mmSPI_WF_LIFETIME_STATUS_7 0x24bc #define mmSPI_WF_LIFETIME_STATUS_8 0x24bd #define mmSPI_WF_LIFETIME_STATUS_9 0x24be #define mmSPI_WF_LIFETIME_STATUS_10 0x24bf #define mmSPI_WF_LIFETIME_STATUS_11 0x24c0 #define mmSPI_WF_LIFETIME_STATUS_12 0x24c1 #define mmSPI_WF_LIFETIME_STATUS_13 0x24c2 #define mmSPI_WF_LIFETIME_STATUS_14 0x24c3 #define mmSPI_WF_LIFETIME_STATUS_15 0x24c4 #define mmSPI_WF_LIFETIME_STATUS_16 0x24c5 #define mmSPI_WF_LIFETIME_STATUS_17 0x24c6 #define mmSPI_WF_LIFETIME_STATUS_18 0x24c7 #define mmSPI_WF_LIFETIME_STATUS_19 0x24c8 #define mmSPI_WF_LIFETIME_STATUS_20 0x24c9 #define mmSPI_WF_LIFETIME_DEBUG 0x24ca #define mmSPI_SLAVE_DEBUG_BUSY 0x24d3 #define mmSPI_LB_CTR_CTRL 0x24d4 #define mmSPI_LB_CU_MASK 0x24d5 #define mmSPI_LB_DATA_REG 0x24d6 #define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24d7 #define mmSPI_GDS_CREDITS 0x24d8 #define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24d9 #define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24da #define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24db #define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24dc #define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24dd #define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24de #define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24df #define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24e0 #define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24e1 #define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24e2 #define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24e3 #define mmBCI_DEBUG_READ 0x24eb #define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24ec #define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ed #define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24ee #define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24ef #define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24f0 #define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24f1 #define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24f2 #define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24f3 #define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24f4 #define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24f5 #define mmSPI_SHADER_TBA_LO_PS 0x2c00 #define mmSPI_SHADER_TBA_HI_PS 0x2c01 #define mmSPI_SHADER_TMA_LO_PS 0x2c02 #define mmSPI_SHADER_TMA_HI_PS 0x2c03 #define mmSPI_SHADER_PGM_LO_PS 0x2c08 #define mmSPI_SHADER_PGM_HI_PS 0x2c09 #define mmSPI_SHADER_PGM_RSRC1_PS 0x2c0a #define mmSPI_SHADER_PGM_RSRC2_PS 0x2c0b #define mmSPI_SHADER_PGM_RSRC3_PS 0x2c07 #define mmSPI_SHADER_USER_DATA_PS_0 0x2c0c #define mmSPI_SHADER_USER_DATA_PS_1 0x2c0d #define mmSPI_SHADER_USER_DATA_PS_2 0x2c0e #define mmSPI_SHADER_USER_DATA_PS_3 0x2c0f #define mmSPI_SHADER_USER_DATA_PS_4 0x2c10 #define mmSPI_SHADER_USER_DATA_PS_5 0x2c11 #define mmSPI_SHADER_USER_DATA_PS_6 0x2c12 #define mmSPI_SHADER_USER_DATA_PS_7 0x2c13 #define mmSPI_SHADER_USER_DATA_PS_8 0x2c14 #define mmSPI_SHADER_USER_DATA_PS_9 0x2c15 #define mmSPI_SHADER_USER_DATA_PS_10 0x2c16 #define mmSPI_SHADER_USER_DATA_PS_11 0x2c17 #define mmSPI_SHADER_USER_DATA_PS_12 0x2c18 #define mmSPI_SHADER_USER_DATA_PS_13 0x2c19 #define mmSPI_SHADER_USER_DATA_PS_14 0x2c1a #define mmSPI_SHADER_USER_DATA_PS_15 0x2c1b #define mmSPI_SHADER_TBA_LO_VS 0x2c40 #define mmSPI_SHADER_TBA_HI_VS 0x2c41 #define mmSPI_SHADER_TMA_LO_VS 0x2c42 #define mmSPI_SHADER_TMA_HI_VS 0x2c43 #define mmSPI_SHADER_PGM_LO_VS 0x2c48 #define mmSPI_SHADER_PGM_HI_VS 0x2c49 #define mmSPI_SHADER_PGM_RSRC1_VS 0x2c4a #define mmSPI_SHADER_PGM_RSRC2_VS 0x2c4b #define mmSPI_SHADER_PGM_RSRC3_VS 0x2c46 #define mmSPI_SHADER_LATE_ALLOC_VS 0x2c47 #define mmSPI_SHADER_USER_DATA_VS_0 0x2c4c #define mmSPI_SHADER_USER_DATA_VS_1 0x2c4d #define mmSPI_SHADER_USER_DATA_VS_2 0x2c4e #define mmSPI_SHADER_USER_DATA_VS_3 0x2c4f #define mmSPI_SHADER_USER_DATA_VS_4 0x2c50 #define mmSPI_SHADER_USER_DATA_VS_5 0x2c51 #define mmSPI_SHADER_USER_DATA_VS_6 0x2c52 #define mmSPI_SHADER_USER_DATA_VS_7 0x2c53 #define mmSPI_SHADER_USER_DATA_VS_8 0x2c54 #define mmSPI_SHADER_USER_DATA_VS_9 0x2c55 #define mmSPI_SHADER_USER_DATA_VS_10 0x2c56 #define mmSPI_SHADER_USER_DATA_VS_11 0x2c57 #define mmSPI_SHADER_USER_DATA_VS_12 0x2c58 #define mmSPI_SHADER_USER_DATA_VS_13 0x2c59 #define mmSPI_SHADER_USER_DATA_VS_14 0x2c5a #define mmSPI_SHADER_USER_DATA_VS_15 0x2c5b #define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x2c7c #define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x2c7d #define mmSPI_SHADER_TBA_LO_GS 0x2c80 #define mmSPI_SHADER_TBA_HI_GS 0x2c81 #define mmSPI_SHADER_TMA_LO_GS 0x2c82 #define mmSPI_SHADER_TMA_HI_GS 0x2c83 #define mmSPI_SHADER_PGM_LO_GS 0x2c88 #define mmSPI_SHADER_PGM_HI_GS 0x2c89 #define mmSPI_SHADER_PGM_RSRC1_GS 0x2c8a #define mmSPI_SHADER_PGM_RSRC2_GS 0x2c8b #define mmSPI_SHADER_PGM_RSRC3_GS 0x2c87 #define mmSPI_SHADER_USER_DATA_GS_0 0x2c8c #define mmSPI_SHADER_USER_DATA_GS_1 0x2c8d #define mmSPI_SHADER_USER_DATA_GS_2 0x2c8e #define mmSPI_SHADER_USER_DATA_GS_3 0x2c8f #define mmSPI_SHADER_USER_DATA_GS_4 0x2c90 #define mmSPI_SHADER_USER_DATA_GS_5 0x2c91 #define mmSPI_SHADER_USER_DATA_GS_6 0x2c92 #define mmSPI_SHADER_USER_DATA_GS_7 0x2c93 #define mmSPI_SHADER_USER_DATA_GS_8 0x2c94 #define mmSPI_SHADER_USER_DATA_GS_9 0x2c95 #define mmSPI_SHADER_USER_DATA_GS_10 0x2c96 #define mmSPI_SHADER_USER_DATA_GS_11 0x2c97 #define mmSPI_SHADER_USER_DATA_GS_12 0x2c98 #define mmSPI_SHADER_USER_DATA_GS_13 0x2c99 #define mmSPI_SHADER_USER_DATA_GS_14 0x2c9a #define mmSPI_SHADER_USER_DATA_GS_15 0x2c9b #define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x2cbc #define mmSPI_SHADER_TBA_LO_ES 0x2cc0 #define mmSPI_SHADER_TBA_HI_ES 0x2cc1 #define mmSPI_SHADER_TMA_LO_ES 0x2cc2 #define mmSPI_SHADER_TMA_HI_ES 0x2cc3 #define mmSPI_SHADER_PGM_LO_ES 0x2cc8 #define mmSPI_SHADER_PGM_HI_ES 0x2cc9 #define mmSPI_SHADER_PGM_RSRC1_ES 0x2cca #define mmSPI_SHADER_PGM_RSRC2_ES 0x2ccb #define mmSPI_SHADER_PGM_RSRC3_ES 0x2cc7 #define mmSPI_SHADER_USER_DATA_ES_0 0x2ccc #define mmSPI_SHADER_USER_DATA_ES_1 0x2ccd #define mmSPI_SHADER_USER_DATA_ES_2 0x2cce #define mmSPI_SHADER_USER_DATA_ES_3 0x2ccf #define mmSPI_SHADER_USER_DATA_ES_4 0x2cd0 #define mmSPI_SHADER_USER_DATA_ES_5 0x2cd1 #define mmSPI_SHADER_USER_DATA_ES_6 0x2cd2 #define mmSPI_SHADER_USER_DATA_ES_7 0x2cd3 #define mmSPI_SHADER_USER_DATA_ES_8 0x2cd4 #define mmSPI_SHADER_USER_DATA_ES_9 0x2cd5 #define mmSPI_SHADER_USER_DATA_ES_10 0x2cd6 #define mmSPI_SHADER_USER_DATA_ES_11 0x2cd7 #define mmSPI_SHADER_USER_DATA_ES_12 0x2cd8 #define mmSPI_SHADER_USER_DATA_ES_13 0x2cd9 #define mmSPI_SHADER_USER_DATA_ES_14 0x2cda #define mmSPI_SHADER_USER_DATA_ES_15 0x2cdb #define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x2cfd #define mmSPI_SHADER_TBA_LO_HS 0x2d00 #define mmSPI_SHADER_TBA_HI_HS 0x2d01 #define mmSPI_SHADER_TMA_LO_HS 0x2d02 #define mmSPI_SHADER_TMA_HI_HS 0x2d03 #define mmSPI_SHADER_PGM_LO_HS 0x2d08 #define mmSPI_SHADER_PGM_HI_HS 0x2d09 #define mmSPI_SHADER_PGM_RSRC1_HS 0x2d0a #define mmSPI_SHADER_PGM_RSRC2_HS 0x2d0b #define mmSPI_SHADER_PGM_RSRC3_HS 0x2d07 #define mmSPI_SHADER_USER_DATA_HS_0 0x2d0c #define mmSPI_SHADER_USER_DATA_HS_1 0x2d0d #define mmSPI_SHADER_USER_DATA_HS_2 0x2d0e #define mmSPI_SHADER_USER_DATA_HS_3 0x2d0f #define mmSPI_SHADER_USER_DATA_HS_4 0x2d10 #define mmSPI_SHADER_USER_DATA_HS_5 0x2d11 #define mmSPI_SHADER_USER_DATA_HS_6 0x2d12 #define mmSPI_SHADER_USER_DATA_HS_7 0x2d13 #define mmSPI_SHADER_USER_DATA_HS_8 0x2d14 #define mmSPI_SHADER_USER_DATA_HS_9 0x2d15 #define mmSPI_SHADER_USER_DATA_HS_10 0x2d16 #define mmSPI_SHADER_USER_DATA_HS_11 0x2d17 #define mmSPI_SHADER_USER_DATA_HS_12 0x2d18 #define mmSPI_SHADER_USER_DATA_HS_13 0x2d19 #define mmSPI_SHADER_USER_DATA_HS_14 0x2d1a #define mmSPI_SHADER_USER_DATA_HS_15 0x2d1b #define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x2d3d #define mmSPI_SHADER_TBA_LO_LS 0x2d40 #define mmSPI_SHADER_TBA_HI_LS 0x2d41 #define mmSPI_SHADER_TMA_LO_LS 0x2d42 #define mmSPI_SHADER_TMA_HI_LS 0x2d43 #define mmSPI_SHADER_PGM_LO_LS 0x2d48 #define mmSPI_SHADER_PGM_HI_LS 0x2d49 #define mmSPI_SHADER_PGM_RSRC1_LS 0x2d4a #define mmSPI_SHADER_PGM_RSRC2_LS 0x2d4b #define mmSPI_SHADER_PGM_RSRC3_LS 0x2d47 #define mmSPI_SHADER_USER_DATA_LS_0 0x2d4c #define mmSPI_SHADER_USER_DATA_LS_1 0x2d4d #define mmSPI_SHADER_USER_DATA_LS_2 0x2d4e #define mmSPI_SHADER_USER_DATA_LS_3 0x2d4f #define mmSPI_SHADER_USER_DATA_LS_4 0x2d50 #define mmSPI_SHADER_USER_DATA_LS_5 0x2d51 #define mmSPI_SHADER_USER_DATA_LS_6 0x2d52 #define mmSPI_SHADER_USER_DATA_LS_7 0x2d53 #define mmSPI_SHADER_USER_DATA_LS_8 0x2d54 #define mmSPI_SHADER_USER_DATA_LS_9 0x2d55 #define mmSPI_SHADER_USER_DATA_LS_10 0x2d56 #define mmSPI_SHADER_USER_DATA_LS_11 0x2d57 #define mmSPI_SHADER_USER_DATA_LS_12 0x2d58 #define mmSPI_SHADER_USER_DATA_LS_13 0x2d59 #define mmSPI_SHADER_USER_DATA_LS_14 0x2d5a #define mmSPI_SHADER_USER_DATA_LS_15 0x2d5b #define mmSQ_CONFIG 0x2300 #define mmSQC_CONFIG 0x2301 #define mmSQC_CACHES 0xc348 #define mmSQ_RANDOM_WAVE_PRI 0x2303 #define mmSQ_REG_CREDITS 0x2304 #define mmSQ_FIFO_SIZES 0x2305 #define mmSQ_INTERRUPT_AUTO_MASK 0x2314 #define mmSQ_INTERRUPT_MSG_CTRL 0x2315 #define mmSQ_PERFCOUNTER_CTRL 0xd9e0 #define mmSQ_PERFCOUNTER_MASK 0xd9e1 #define mmSQ_PERFCOUNTER_CTRL2 0xd9e2 #define mmCC_SQC_BANK_DISABLE 0x2307 #define mmUSER_SQC_BANK_DISABLE 0x2308 #define mmSQ_PERFCOUNTER0_LO 0xd1c0 #define mmSQ_PERFCOUNTER1_LO 0xd1c2 #define mmSQ_PERFCOUNTER2_LO 0xd1c4 #define mmSQ_PERFCOUNTER3_LO 0xd1c6 #define mmSQ_PERFCOUNTER4_LO 0xd1c8 #define mmSQ_PERFCOUNTER5_LO 0xd1ca #define mmSQ_PERFCOUNTER6_LO 0xd1cc #define mmSQ_PERFCOUNTER7_LO 0xd1ce #define mmSQ_PERFCOUNTER8_LO 0xd1d0 #define mmSQ_PERFCOUNTER9_LO 0xd1d2 #define mmSQ_PERFCOUNTER10_LO 0xd1d4 #define mmSQ_PERFCOUNTER11_LO 0xd1d6 #define mmSQ_PERFCOUNTER12_LO 0xd1d8 #define mmSQ_PERFCOUNTER13_LO 0xd1da #define mmSQ_PERFCOUNTER14_LO 0xd1dc #define mmSQ_PERFCOUNTER15_LO 0xd1de #define mmSQ_PERFCOUNTER0_HI 0xd1c1 #define mmSQ_PERFCOUNTER1_HI 0xd1c3 #define mmSQ_PERFCOUNTER2_HI 0xd1c5 #define mmSQ_PERFCOUNTER3_HI 0xd1c7 #define mmSQ_PERFCOUNTER4_HI 0xd1c9 #define mmSQ_PERFCOUNTER5_HI 0xd1cb #define mmSQ_PERFCOUNTER6_HI 0xd1cd #define mmSQ_PERFCOUNTER7_HI 0xd1cf #define mmSQ_PERFCOUNTER8_HI 0xd1d1 #define mmSQ_PERFCOUNTER9_HI 0xd1d3 #define mmSQ_PERFCOUNTER10_HI 0xd1d5 #define mmSQ_PERFCOUNTER11_HI 0xd1d7 #define mmSQ_PERFCOUNTER12_HI 0xd1d9 #define mmSQ_PERFCOUNTER13_HI 0xd1db #define mmSQ_PERFCOUNTER14_HI 0xd1dd #define mmSQ_PERFCOUNTER15_HI 0xd1df #define mmSQ_PERFCOUNTER0_SELECT 0xd9c0 #define mmSQ_PERFCOUNTER1_SELECT 0xd9c1 #define mmSQ_PERFCOUNTER2_SELECT 0xd9c2 #define mmSQ_PERFCOUNTER3_SELECT 0xd9c3 #define mmSQ_PERFCOUNTER4_SELECT 0xd9c4 #define mmSQ_PERFCOUNTER5_SELECT 0xd9c5 #define mmSQ_PERFCOUNTER6_SELECT 0xd9c6 #define mmSQ_PERFCOUNTER7_SELECT 0xd9c7 #define mmSQ_PERFCOUNTER8_SELECT 0xd9c8 #define mmSQ_PERFCOUNTER9_SELECT 0xd9c9 #define mmSQ_PERFCOUNTER10_SELECT 0xd9ca #define mmSQ_PERFCOUNTER11_SELECT 0xd9cb #define mmSQ_PERFCOUNTER12_SELECT 0xd9cc #define mmSQ_PERFCOUNTER13_SELECT 0xd9cd #define mmSQ_PERFCOUNTER14_SELECT 0xd9ce #define mmSQ_PERFCOUNTER15_SELECT 0xd9cf #define mmCGTT_SQ_CLK_CTRL 0xf08c #define mmCGTT_SQG_CLK_CTRL 0xf08d #define mmSQ_ALU_CLK_CTRL 0xf08e #define mmSQ_TEX_CLK_CTRL 0xf08f #define mmSQ_LDS_CLK_CTRL 0xf090 #define mmSQ_POWER_THROTTLE 0xf091 #define mmSQ_POWER_THROTTLE2 0xf092 #define mmSQ_TIME_HI 0x237c #define mmSQ_TIME_LO 0x237d #define mmSQ_THREAD_TRACE_BASE 0x2380 #define mmSQ_THREAD_TRACE_BASE2 0x2385 #define mmSQ_THREAD_TRACE_SIZE 0x2381 #define mmSQ_THREAD_TRACE_MASK 0x2382 #define mmSQ_THREAD_TRACE_USERDATA_0 0xc340 #define mmSQ_THREAD_TRACE_USERDATA_1 0xc341 #define mmSQ_THREAD_TRACE_USERDATA_2 0xc342 #define mmSQ_THREAD_TRACE_USERDATA_3 0xc343 #define mmSQ_THREAD_TRACE_MODE 0x238e #define mmSQ_THREAD_TRACE_CTRL 0x238f #define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2383 #define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2386 #define mmSQ_THREAD_TRACE_PERF_MASK 0x2384 #define mmSQ_THREAD_TRACE_WPTR 0x238c #define mmSQ_THREAD_TRACE_STATUS 0x238d #define mmSQ_THREAD_TRACE_CNTR 0x2390 #define mmSQ_THREAD_TRACE_HIWATER 0x2392 #define mmSQ_LB_CTR_CTRL 0x2398 #define mmSQ_LB_DATA_ALU_CYCLES 0x2399 #define mmSQ_LB_DATA_TEX_CYCLES 0x239a #define mmSQ_LB_DATA_ALU_STALLS 0x239b #define mmSQ_LB_DATA_TEX_STALLS 0x239c #define mmSQC_SECDED_CNT 0x23a0 #define mmSQ_SEC_CNT 0x23a1 #define mmSQ_DED_CNT 0x23a2 #define mmSQ_DED_INFO 0x23a3 #define mmSQ_BUF_RSRC_WORD0 0x23c0 #define mmSQ_BUF_RSRC_WORD1 0x23c1 #define mmSQ_BUF_RSRC_WORD2 0x23c2 #define mmSQ_BUF_RSRC_WORD3 0x23c3 #define mmSQ_IMG_RSRC_WORD0 0x23c4 #define mmSQ_IMG_RSRC_WORD1 0x23c5 #define mmSQ_IMG_RSRC_WORD2 0x23c6 #define mmSQ_IMG_RSRC_WORD3 0x23c7 #define mmSQ_IMG_RSRC_WORD4 0x23c8 #define mmSQ_IMG_RSRC_WORD5 0x23c9 #define mmSQ_IMG_RSRC_WORD6 0x23ca #define mmSQ_IMG_RSRC_WORD7 0x23cb #define mmSQ_IMG_SAMP_WORD0 0x23cc #define mmSQ_IMG_SAMP_WORD1 0x23cd #define mmSQ_IMG_SAMP_WORD2 0x23ce #define mmSQ_IMG_SAMP_WORD3 0x23cf #define mmSQ_FLAT_SCRATCH_WORD0 0x23d0 #define mmSQ_FLAT_SCRATCH_WORD1 0x23d1 #define mmSQ_IND_INDEX 0x2378 #define mmSQ_IND_CMD 0x237a #define mmSQ_CMD 0x237b #define mmSQ_IND_DATA 0x2379 #define mmSQ_REG_TIMESTAMP 0x2374 #define mmSQ_CMD_TIMESTAMP 0x2375 #define mmSQ_HV_VMID_CTRL 0xf840 #define ixSQ_WAVE_INST_DW0 0x1a #define ixSQ_WAVE_INST_DW1 0x1b #define ixSQ_WAVE_PC_LO 0x18 #define ixSQ_WAVE_PC_HI 0x19 #define ixSQ_WAVE_IB_DBG0 0x1c #define ixSQ_WAVE_EXEC_LO 0x27e #define ixSQ_WAVE_EXEC_HI 0x27f #define ixSQ_WAVE_STATUS 0x12 #define ixSQ_WAVE_MODE 0x11 #define ixSQ_WAVE_TRAPSTS 0x13 #define ixSQ_WAVE_HW_ID 0x14 #define ixSQ_WAVE_GPR_ALLOC 0x15 #define ixSQ_WAVE_LDS_ALLOC 0x16 #define ixSQ_WAVE_IB_STS 0x17 #define ixSQ_WAVE_M0 0x27c #define ixSQ_WAVE_TBA_LO 0x26c #define ixSQ_WAVE_TBA_HI 0x26d #define ixSQ_WAVE_TMA_LO 0x26e #define ixSQ_WAVE_TMA_HI 0x26f #define ixSQ_WAVE_TTMP0 0x270 #define ixSQ_WAVE_TTMP1 0x271 #define ixSQ_WAVE_TTMP2 0x272 #define ixSQ_WAVE_TTMP3 0x273 #define ixSQ_WAVE_TTMP4 0x274 #define ixSQ_WAVE_TTMP5 0x275 #define ixSQ_WAVE_TTMP6 0x276 #define ixSQ_WAVE_TTMP7 0x277 #define ixSQ_WAVE_TTMP8 0x278 #define ixSQ_WAVE_TTMP9 0x279 #define ixSQ_WAVE_TTMP10 0x27a #define ixSQ_WAVE_TTMP11 0x27b #define mmSQ_DEBUG_STS_GLOBAL 0x2309 #define mmSQ_DEBUG_STS_GLOBAL2 0x2310 #define mmSQ_DEBUG_STS_GLOBAL3 0x2311 #define ixSQ_DEBUG_STS_LOCAL 0x8 #define ixSQ_DEBUG_CTRL_LOCAL 0x9 #define mmSH_MEM_BASES 0x230a #define mmSH_MEM_APE1_BASE 0x230b #define mmSH_MEM_APE1_LIMIT 0x230c #define mmSH_MEM_CONFIG 0x230d #define mmSQC_POLICY 0x230e #define mmSQC_VOLATILE 0x230f #define mmSQ_THREAD_TRACE_WORD_CMN 0x23b0 #define mmSQ_THREAD_TRACE_WORD_INST 0x23b0 #define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23b0 #define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23b1 #define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23b0 #define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23b1 #define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23b0 #define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23b1 #define mmSQ_THREAD_TRACE_WORD_WAVE 0x23b0 #define mmSQ_THREAD_TRACE_WORD_MISC 0x23b0 #define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23b0 #define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23b0 #define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23b0 #define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23b0 #define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23b0 #define mmSQ_THREAD_TRACE_WORD_EVENT 0x23b0 #define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23b0 #define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23b0 #define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23b1 #define ixSQ_INTERRUPT_WORD_CMN 0x20c0 #define ixSQ_INTERRUPT_WORD_AUTO 0x20c0 #define ixSQ_INTERRUPT_WORD_WAVE 0x20c0 #define mmSQ_SOP2 0x237f #define mmSQ_VOP1 0x237f #define mmSQ_MTBUF_1 0x237f #define mmSQ_EXP_1 0x237f #define mmSQ_MUBUF_1 0x237f #define mmSQ_INST 0x237f #define mmSQ_EXP_0 0x237f #define mmSQ_MUBUF_0 0x237f #define mmSQ_VOP3_0 0x237f #define mmSQ_VOP2 0x237f #define mmSQ_MTBUF_0 0x237f #define mmSQ_SOPP 0x237f #define mmSQ_FLAT_0 0x237f #define mmSQ_VOP3_0_SDST_ENC 0x237f #define mmSQ_MIMG_1 0x237f #define mmSQ_SMRD 0x237f #define mmSQ_SOP1 0x237f #define mmSQ_SOPC 0x237f #define mmSQ_FLAT_1 0x237f #define mmSQ_DS_1 0x237f #define mmSQ_VOP3_1 0x237f #define mmSQ_MIMG_0 0x237f #define mmSQ_SOPK 0x237f #define mmSQ_DS_0 0x237f #define mmSQ_VOPC 0x237f #define mmSQ_VINTRP 0x237f #define mmCGTT_SX_CLK_CTRL0 0xf094 #define mmCGTT_SX_CLK_CTRL1 0xf095 #define mmCGTT_SX_CLK_CTRL2 0xf096 #define mmCGTT_SX_CLK_CTRL3 0xf097 #define mmCGTT_SX_CLK_CTRL4 0xf098 #define mmSX_DEBUG_BUSY 0x2414 #define mmSX_DEBUG_BUSY_2 0x2415 #define mmSX_DEBUG_BUSY_3 0x2416 #define mmSX_DEBUG_BUSY_4 0x2417 #define mmSX_DEBUG_1 0x2418 #define mmSX_PERFCOUNTER0_SELECT 0xda40 #define mmSX_PERFCOUNTER1_SELECT 0xda41 #define mmSX_PERFCOUNTER2_SELECT 0xda42 #define mmSX_PERFCOUNTER3_SELECT 0xda43 #define mmSX_PERFCOUNTER0_SELECT1 0xda44 #define mmSX_PERFCOUNTER1_SELECT1 0xda45 #define mmSX_PERFCOUNTER0_LO 0xd240 #define mmSX_PERFCOUNTER0_HI 0xd241 #define mmSX_PERFCOUNTER1_LO 0xd242 #define mmSX_PERFCOUNTER1_HI 0xd243 #define mmSX_PERFCOUNTER2_LO 0xd244 #define mmSX_PERFCOUNTER2_HI 0xd245 #define mmSX_PERFCOUNTER3_LO 0xd246 #define mmSX_PERFCOUNTER3_HI 0xd247 #define mmTCC_CTRL 0x2b80 #define mmTCC_EDC_COUNTER 0x2b82 #define mmTCC_REDUNDANCY 0x2b83 #define mmTCC_CGTT_SCLK_CTRL 0xf0ac #define mmTCA_CGTT_SCLK_CTRL 0xf0ad #define mmTCS_CGTT_SCLK_CTRL 0xf0ae #define mmTCC_PERFCOUNTER0_SELECT 0xdb80 #define mmTCC_PERFCOUNTER1_SELECT 0xdb82 #define mmTCC_PERFCOUNTER0_SELECT1 0xdb81 #define mmTCC_PERFCOUNTER1_SELECT1 0xdb83 #define mmTCC_PERFCOUNTER2_SELECT 0xdb84 #define mmTCC_PERFCOUNTER3_SELECT 0xdb85 #define mmTCC_PERFCOUNTER0_LO 0xd380 #define mmTCC_PERFCOUNTER1_LO 0xd382 #define mmTCC_PERFCOUNTER2_LO 0xd384 #define mmTCC_PERFCOUNTER3_LO 0xd386 #define mmTCC_PERFCOUNTER0_HI 0xd381 #define mmTCC_PERFCOUNTER1_HI 0xd383 #define mmTCC_PERFCOUNTER2_HI 0xd385 #define mmTCC_PERFCOUNTER3_HI 0xd387 #define mmTCA_CTRL 0x2bc0 #define mmTCA_PERFCOUNTER0_SELECT 0xdb90 #define mmTCA_PERFCOUNTER1_SELECT 0xdb92 #define mmTCA_PERFCOUNTER0_SELECT1 0xdb91 #define mmTCA_PERFCOUNTER1_SELECT1 0xdb93 #define mmTCA_PERFCOUNTER2_SELECT 0xdb94 #define mmTCA_PERFCOUNTER3_SELECT 0xdb95 #define mmTCA_PERFCOUNTER0_LO 0xd390 #define mmTCA_PERFCOUNTER1_LO 0xd392 #define mmTCA_PERFCOUNTER2_LO 0xd394 #define mmTCA_PERFCOUNTER3_LO 0xd396 #define mmTCA_PERFCOUNTER0_HI 0xd391 #define mmTCA_PERFCOUNTER1_HI 0xd393 #define mmTCA_PERFCOUNTER2_HI 0xd395 #define mmTCA_PERFCOUNTER3_HI 0xd397 #define mmTCS_CTRL 0x2be0 #define mmTCS_PERFCOUNTER0_SELECT 0xdba0 #define mmTCS_PERFCOUNTER0_SELECT1 0xdba1 #define mmTCS_PERFCOUNTER1_SELECT 0xdba2 #define mmTCS_PERFCOUNTER2_SELECT 0xdba3 #define mmTCS_PERFCOUNTER3_SELECT 0xdba4 #define mmTCS_PERFCOUNTER0_LO 0xd3a0 #define mmTCS_PERFCOUNTER1_LO 0xd3a2 #define mmTCS_PERFCOUNTER2_LO 0xd3a4 #define mmTCS_PERFCOUNTER3_LO 0xd3a6 #define mmTCS_PERFCOUNTER0_HI 0xd3a1 #define mmTCS_PERFCOUNTER1_HI 0xd3a3 #define mmTCS_PERFCOUNTER2_HI 0xd3a5 #define mmTCS_PERFCOUNTER3_HI 0xd3a7 #define mmTA_BC_BASE_ADDR 0xa020 #define mmTA_BC_BASE_ADDR_HI 0xa021 #define mmTD_CNTL 0x2525 #define mmTD_STATUS 0x2526 #define mmTD_DEBUG_INDEX 0x2528 #define mmTD_DEBUG_DATA 0x2529 #define mmTD_PERFCOUNTER0_SELECT 0xdb00 #define mmTD_PERFCOUNTER1_SELECT 0xdb02 #define mmTD_PERFCOUNTER0_SELECT1 0xdb01 #define mmTD_PERFCOUNTER0_LO 0xd300 #define mmTD_PERFCOUNTER1_LO 0xd302 #define mmTD_PERFCOUNTER0_HI 0xd301 #define mmTD_PERFCOUNTER1_HI 0xd303 #define mmTD_SCRATCH 0x2533 #define mmTA_CNTL 0x2541 #define mmTA_CNTL_AUX 0x2542 #define mmTA_RESERVED_010C 0x2543 #define mmTA_CS_BC_BASE_ADDR 0xc380 #define mmTA_CS_BC_BASE_ADDR_HI 0xc381 #define mmTA_STATUS 0x2548 #define mmTA_DEBUG_INDEX 0x254c #define mmTA_DEBUG_DATA 0x254d #define mmTA_PERFCOUNTER0_SELECT 0xdac0 #define mmTA_PERFCOUNTER1_SELECT 0xdac2 #define mmTA_PERFCOUNTER0_SELECT1 0xdac1 #define mmTA_PERFCOUNTER0_LO 0xd2c0 #define mmTA_PERFCOUNTER1_LO 0xd2c2 #define mmTA_PERFCOUNTER0_HI 0xd2c1 #define mmTA_PERFCOUNTER1_HI 0xd2c3 #define mmTA_SCRATCH 0x2564 #define mmSH_HIDDEN_PRIVATE_BASE_VMID 0x2580 #define mmSH_STATIC_MEM_CONFIG 0x2581 #define mmTCP_INVALIDATE 0x2b00 #define mmTCP_STATUS 0x2b01 #define mmTCP_CNTL 0x2b02 #define mmTCP_CHAN_STEER_LO 0x2b03 #define mmTCP_CHAN_STEER_HI 0x2b04 #define mmTCP_ADDR_CONFIG 0x2b05 #define mmTCP_CREDIT 0x2b06 #define mmTCP_PERFCOUNTER0_SELECT 0xdb40 #define mmTCP_PERFCOUNTER1_SELECT 0xdb42 #define mmTCP_PERFCOUNTER0_SELECT1 0xdb41 #define mmTCP_PERFCOUNTER1_SELECT1 0xdb43 #define mmTCP_PERFCOUNTER2_SELECT 0xdb44 #define mmTCP_PERFCOUNTER3_SELECT 0xdb45 #define mmTCP_PERFCOUNTER0_LO 0xd340 #define mmTCP_PERFCOUNTER1_LO 0xd342 #define mmTCP_PERFCOUNTER2_LO 0xd344 #define mmTCP_PERFCOUNTER3_LO 0xd346 #define mmTCP_PERFCOUNTER0_HI 0xd341 #define mmTCP_PERFCOUNTER1_HI 0xd343 #define mmTCP_PERFCOUNTER2_HI 0xd345 #define mmTCP_PERFCOUNTER3_HI 0xd347 #define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2b16 #define mmTCP_EDC_COUNTER 0x2b17 #define mmTC_CFG_L1_LOAD_POLICY0 0x2b1a #define mmTC_CFG_L1_LOAD_POLICY1 0x2b1b #define mmTC_CFG_L1_STORE_POLICY 0x2b1c #define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d #define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e #define mmTC_CFG_L2_STORE_POLICY0 0x2b1f #define mmTC_CFG_L2_STORE_POLICY1 0x2b20 #define mmTC_CFG_L2_ATOMIC_POLICY 0x2b21 #define mmTC_CFG_L1_VOLATILE 0x2b22 #define mmTC_CFG_L2_VOLATILE 0x2b23 #define mmTCP_WATCH0_ADDR_H 0x32a0 #define mmTCP_WATCH1_ADDR_H 0x32a3 #define mmTCP_WATCH2_ADDR_H 0x32a6 #define mmTCP_WATCH3_ADDR_H 0x32a9 #define mmTCP_WATCH0_ADDR_L 0x32a1 #define mmTCP_WATCH1_ADDR_L 0x32a4 #define mmTCP_WATCH2_ADDR_L 0x32a7 #define mmTCP_WATCH3_ADDR_L 0x32aa #define mmTCP_WATCH0_CNTL 0x32a2 #define mmTCP_WATCH1_CNTL 0x32a5 #define mmTCP_WATCH2_CNTL 0x32a8 #define mmTCP_WATCH3_CNTL 0x32ab #define mmTD_CGTT_CTRL 0xf09c #define mmTA_CGTT_CTRL 0xf09d #define mmCGTT_TCP_CLK_CTRL 0xf09e #define mmCGTT_TCI_CLK_CTRL 0xf09f #define mmTCI_STATUS 0x2b61 #define mmTCI_CNTL_1 0x2b62 #define mmTCI_CNTL_2 0x2b63 #define mmGDS_CONFIG 0x25c0 #define mmGDS_CNTL_STATUS 0x25c1 #define mmGDS_ENHANCE2 0x25c2 #define mmGDS_PROTECTION_FAULT 0x25c3 #define mmGDS_VM_PROTECTION_FAULT 0x25c4 #define mmGDS_SECDED_CNT 0x25c5 #define mmGDS_GRBM_SECDED_CNT 0x25c6 #define mmGDS_OA_DED 0x25c7 #define mmGDS_DEBUG_CNTL 0x25c8 #define mmGDS_DEBUG_DATA 0x25c9 #define mmCGTT_GDS_CLK_CTRL 0xf0a0 #define mmGDS_RD_ADDR 0xc400 #define mmGDS_RD_DATA 0xc401 #define mmGDS_RD_BURST_ADDR 0xc402 #define mmGDS_RD_BURST_COUNT 0xc403 #define mmGDS_RD_BURST_DATA 0xc404 #define mmGDS_WR_ADDR 0xc405 #define mmGDS_WR_DATA 0xc406 #define mmGDS_WR_BURST_ADDR 0xc407 #define mmGDS_WR_BURST_DATA 0xc408 #define mmGDS_WRITE_COMPLETE 0xc409 #define mmGDS_ATOM_CNTL 0xc40a #define mmGDS_ATOM_COMPLETE 0xc40b #define mmGDS_ATOM_BASE 0xc40c #define mmGDS_ATOM_SIZE 0xc40d #define mmGDS_ATOM_OFFSET0 0xc40e #define mmGDS_ATOM_OFFSET1 0xc40f #define mmGDS_ATOM_DST 0xc410 #define mmGDS_ATOM_OP 0xc411 #define mmGDS_ATOM_SRC0 0xc412 #define mmGDS_ATOM_SRC0_U 0xc413 #define mmGDS_ATOM_SRC1 0xc414 #define mmGDS_ATOM_SRC1_U 0xc415 #define mmGDS_ATOM_READ0 0xc416 #define mmGDS_ATOM_READ0_U 0xc417 #define mmGDS_ATOM_READ1 0xc418 #define mmGDS_ATOM_READ1_U 0xc419 #define mmGDS_GWS_RESOURCE_CNTL 0xc41a #define mmGDS_GWS_RESOURCE 0xc41b #define mmGDS_GWS_RESOURCE_CNT 0xc41c #define mmGDS_OA_CNTL 0xc41d #define mmGDS_OA_COUNTER 0xc41e #define mmGDS_OA_ADDRESS 0xc41f #define mmGDS_OA_INCDEC 0xc420 #define mmGDS_OA_RING_SIZE 0xc421 #define ixGDS_DEBUG_REG0 0x0 #define ixGDS_DEBUG_REG1 0x1 #define ixGDS_DEBUG_REG2 0x2 #define ixGDS_DEBUG_REG3 0x3 #define ixGDS_DEBUG_REG4 0x4 #define ixGDS_DEBUG_REG5 0x5 #define ixGDS_DEBUG_REG6 0x6 #define mmGDS_PERFCOUNTER0_SELECT 0xda80 #define mmGDS_PERFCOUNTER1_SELECT 0xda81 #define mmGDS_PERFCOUNTER2_SELECT 0xda82 #define mmGDS_PERFCOUNTER3_SELECT 0xda83 #define mmGDS_PERFCOUNTER0_LO 0xd280 #define mmGDS_PERFCOUNTER1_LO 0xd282 #define mmGDS_PERFCOUNTER2_LO 0xd284 #define mmGDS_PERFCOUNTER3_LO 0xd286 #define mmGDS_PERFCOUNTER0_HI 0xd281 #define mmGDS_PERFCOUNTER1_HI 0xd283 #define mmGDS_PERFCOUNTER2_HI 0xd285 #define mmGDS_PERFCOUNTER3_HI 0xd287 #define mmGDS_PERFCOUNTER0_SELECT1 0xda84 #define mmGDS_VMID0_BASE 0x3300 #define mmGDS_VMID1_BASE 0x3302 #define mmGDS_VMID2_BASE 0x3304 #define mmGDS_VMID3_BASE 0x3306 #define mmGDS_VMID4_BASE 0x3308 #define mmGDS_VMID5_BASE 0x330a #define mmGDS_VMID6_BASE 0x330c #define mmGDS_VMID7_BASE 0x330e #define mmGDS_VMID8_BASE 0x3310 #define mmGDS_VMID9_BASE 0x3312 #define mmGDS_VMID10_BASE 0x3314 #define mmGDS_VMID11_BASE 0x3316 #define mmGDS_VMID12_BASE 0x3318 #define mmGDS_VMID13_BASE 0x331a #define mmGDS_VMID14_BASE 0x331c #define mmGDS_VMID15_BASE 0x331e #define mmGDS_VMID0_SIZE 0x3301 #define mmGDS_VMID1_SIZE 0x3303 #define mmGDS_VMID2_SIZE 0x3305 #define mmGDS_VMID3_SIZE 0x3307 #define mmGDS_VMID4_SIZE 0x3309 #define mmGDS_VMID5_SIZE 0x330b #define mmGDS_VMID6_SIZE 0x330d #define mmGDS_VMID7_SIZE 0x330f #define mmGDS_VMID8_SIZE 0x3311 #define mmGDS_VMID9_SIZE 0x3313 #define mmGDS_VMID10_SIZE 0x3315 #define mmGDS_VMID11_SIZE 0x3317 #define mmGDS_VMID12_SIZE 0x3319 #define mmGDS_VMID13_SIZE 0x331b #define mmGDS_VMID14_SIZE 0x331d #define mmGDS_VMID15_SIZE 0x331f #define mmGDS_GWS_VMID0 0x3320 #define mmGDS_GWS_VMID1 0x3321 #define mmGDS_GWS_VMID2 0x3322 #define mmGDS_GWS_VMID3 0x3323 #define mmGDS_GWS_VMID4 0x3324 #define mmGDS_GWS_VMID5 0x3325 #define mmGDS_GWS_VMID6 0x3326 #define mmGDS_GWS_VMID7 0x3327 #define mmGDS_GWS_VMID8 0x3328 #define mmGDS_GWS_VMID9 0x3329 #define mmGDS_GWS_VMID10 0x332a #define mmGDS_GWS_VMID11 0x332b #define mmGDS_GWS_VMID12 0x332c #define mmGDS_GWS_VMID13 0x332d #define mmGDS_GWS_VMID14 0x332e #define mmGDS_GWS_VMID15 0x332f #define mmGDS_OA_VMID0 0x3330 #define mmGDS_OA_VMID1 0x3331 #define mmGDS_OA_VMID2 0x3332 #define mmGDS_OA_VMID3 0x3333 #define mmGDS_OA_VMID4 0x3334 #define mmGDS_OA_VMID5 0x3335 #define mmGDS_OA_VMID6 0x3336 #define mmGDS_OA_VMID7 0x3337 #define mmGDS_OA_VMID8 0x3338 #define mmGDS_OA_VMID9 0x3339 #define mmGDS_OA_VMID10 0x333a #define mmGDS_OA_VMID11 0x333b #define mmGDS_OA_VMID12 0x333c #define mmGDS_OA_VMID13 0x333d #define mmGDS_OA_VMID14 0x333e #define mmGDS_OA_VMID15 0x333f #define mmGDS_GWS_RESET0 0x3344 #define mmGDS_GWS_RESET1 0x3345 #define mmGDS_GWS_RESOURCE_RESET 0x3346 #define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348 #define mmGDS_OA_RESET_MASK 0x3349 #define mmGDS_OA_RESET 0x334a #define mmGDS_ENHANCE 0x334b #define mmGDS_OA_CGPG_RESTORE 0x334c #define mmCS_COPY_STATE 0xa1f3 #define mmGFX_COPY_STATE 0xa1f4 #define mmVGT_DRAW_INITIATOR 0xa1fc #define mmVGT_EVENT_INITIATOR 0xa2a4 #define mmVGT_EVENT_ADDRESS_REG 0xa1fe #define mmVGT_DMA_BASE_HI 0xa1f9 #define mmVGT_DMA_BASE 0xa1fa #define mmVGT_DMA_INDEX_TYPE 0xa29f #define mmVGT_DMA_NUM_INSTANCES 0xa2a2 #define mmIA_ENHANCE 0xa29c #define mmVGT_DMA_SIZE 0xa29d #define mmVGT_DMA_MAX_SIZE 0xa29e #define mmVGT_DMA_PRIMITIVE_TYPE 0x2271 #define mmVGT_DMA_CONTROL 0x2272 #define mmVGT_IMMED_DATA 0xa1fd #define mmVGT_INDEX_TYPE 0xc243 #define mmVGT_NUM_INDICES 0xc24c #define mmVGT_NUM_INSTANCES 0xc24d #define mmVGT_PRIMITIVE_TYPE 0xc242 #define mmVGT_PRIMITIVEID_EN 0xa2a1 #define mmVGT_PRIMITIVEID_RESET 0xa2a3 #define mmVGT_VTX_CNT_EN 0xa2ae #define mmVGT_REUSE_OFF 0xa2ad #define mmVGT_INSTANCE_STEP_RATE_0 0xa2a8 #define mmVGT_INSTANCE_STEP_RATE_1 0xa2a9 #define mmVGT_MAX_VTX_INDX 0xa100 #define mmVGT_MIN_VTX_INDX 0xa101 #define mmVGT_INDX_OFFSET 0xa102 #define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xa316 #define mmVGT_OUT_DEALLOC_CNTL 0xa317 #define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xa103 #define mmVGT_MULTI_PRIM_IB_RESET_EN 0xa2a5 #define mmVGT_ENHANCE 0xa294 #define mmVGT_OUTPUT_PATH_CNTL 0xa284 #define mmVGT_HOS_CNTL 0xa285 #define mmVGT_HOS_MAX_TESS_LEVEL 0xa286 #define mmVGT_HOS_MIN_TESS_LEVEL 0xa287 #define mmVGT_HOS_REUSE_DEPTH 0xa288 #define mmVGT_GROUP_PRIM_TYPE 0xa289 #define mmVGT_GROUP_FIRST_DECR 0xa28a #define mmVGT_GROUP_DECR 0xa28b #define mmVGT_GROUP_VECT_0_CNTL 0xa28c #define mmVGT_GROUP_VECT_1_CNTL 0xa28d #define mmVGT_GROUP_VECT_0_FMT_CNTL 0xa28e #define mmVGT_GROUP_VECT_1_FMT_CNTL 0xa28f #define mmVGT_VTX_VECT_EJECT_REG 0x222c #define mmVGT_DMA_DATA_FIFO_DEPTH 0x222d #define mmVGT_DMA_REQ_FIFO_DEPTH 0x222e #define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222f #define mmVGT_LAST_COPY_STATE 0x2230 #define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 #define mmVGT_GS_MODE 0xa290 #define mmVGT_GS_ONCHIP_CNTL 0xa291 #define mmVGT_GS_OUT_PRIM_TYPE 0xa29b #define mmVGT_CACHE_INVALIDATION 0x2231 #define mmVGT_RESET_DEBUG 0x2232 #define mmVGT_STRMOUT_DELAY 0x2233 #define mmVGT_FIFO_DEPTHS 0x2234 #define mmVGT_GS_PER_ES 0xa295 #define mmVGT_ES_PER_GS 0xa296 #define mmVGT_GS_PER_VS 0xa297 #define mmVGT_GS_VERTEX_REUSE 0x2235 #define mmVGT_MC_LAT_CNTL 0x2236 #define mmIA_CNTL_STATUS 0x2237 #define mmVGT_STRMOUT_CONFIG 0xa2e5 #define mmVGT_STRMOUT_BUFFER_SIZE_0 0xa2b4 #define mmVGT_STRMOUT_BUFFER_SIZE_1 0xa2b8 #define mmVGT_STRMOUT_BUFFER_SIZE_2 0xa2bc #define mmVGT_STRMOUT_BUFFER_SIZE_3 0xa2c0 #define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xa2b7 #define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xa2bb #define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xa2bf #define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xa2c3 #define mmVGT_STRMOUT_VTX_STRIDE_0 0xa2b5 #define mmVGT_STRMOUT_VTX_STRIDE_1 0xa2b9 #define mmVGT_STRMOUT_VTX_STRIDE_2 0xa2bd #define mmVGT_STRMOUT_VTX_STRIDE_3 0xa2c1 #define mmVGT_STRMOUT_BUFFER_CONFIG 0xa2e6 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xc244 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xc245 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xc246 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xc247 #define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xa2ca #define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xa2cb #define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xa2cc #define mmVGT_GS_MAX_VERT_OUT 0xa2ce #define mmIA_VMID_OVERRIDE 0x2260 #define mmVGT_SHADER_STAGES_EN 0xa2d5 #define mmVGT_DISPATCH_DRAW_INDEX 0xa2dd #define mmVGT_LS_HS_CONFIG 0xa2d6 #define mmVGT_DMA_LS_HS_CONFIG 0x2273 #define mmVGT_TF_PARAM 0xa2db #define mmVGT_TF_RING_SIZE 0xc24e #define mmVGT_SYS_CONFIG 0x2263 #define mmVGT_HS_OFFCHIP_PARAM 0xc24f #define mmVGT_TF_MEMORY_BASE 0xc250 #define mmVGT_GS_INSTANCE_CNT 0xa2e4 #define mmIA_MULTI_VGT_PARAM 0xa2aa #define mmVGT_VS_MAX_WAVE_ID 0x2268 #define mmVGT_ESGS_RING_SIZE 0xc240 #define mmVGT_GSVS_RING_SIZE 0xc241 #define mmVGT_GSVS_RING_OFFSET_1 0xa298 #define mmVGT_GSVS_RING_OFFSET_2 0xa299 #define mmVGT_GSVS_RING_OFFSET_3 0xa29a #define mmVGT_ESGS_RING_ITEMSIZE 0xa2ab #define mmVGT_GSVS_RING_ITEMSIZE 0xa2ac #define mmVGT_GS_VERT_ITEMSIZE 0xa2d7 #define mmVGT_GS_VERT_ITEMSIZE_1 0xa2d8 #define mmVGT_GS_VERT_ITEMSIZE_2 0xa2d9 #define mmVGT_GS_VERT_ITEMSIZE_3 0xa2da #define mmWD_CNTL_STATUS 0x223f #define mmWD_ENHANCE 0xa2a0 #define mmGFX_PIPE_CONTROL 0x226d #define mmGFX_PIPE_PRIORITY 0xf87f #define mmCGTT_VGT_CLK_CTRL 0xf084 #define mmCGTT_IA_CLK_CTRL 0xf085 #define mmCGTT_WD_CLK_CTRL 0xf086 #define mmVGT_DEBUG_CNTL 0x2238 #define mmVGT_DEBUG_DATA 0x2239 #define mmIA_DEBUG_CNTL 0x223a #define mmIA_DEBUG_DATA 0x223b #define mmVGT_CNTL_STATUS 0x223c #define mmWD_DEBUG_CNTL 0x223d #define mmWD_DEBUG_DATA 0x223e #define mmCC_GC_PRIM_CONFIG 0x2240 #define mmGC_USER_PRIM_CONFIG 0x2241 #define ixWD_DEBUG_REG0 0x0 #define ixWD_DEBUG_REG1 0x1 #define ixWD_DEBUG_REG2 0x2 #define ixWD_DEBUG_REG3 0x3 #define ixWD_DEBUG_REG4 0x4 #define ixWD_DEBUG_REG5 0x5 #define ixIA_DEBUG_REG0 0x0 #define ixIA_DEBUG_REG1 0x1 #define ixIA_DEBUG_REG2 0x2 #define ixIA_DEBUG_REG3 0x3 #define ixIA_DEBUG_REG4 0x4 #define ixIA_DEBUG_REG5 0x5 #define ixIA_DEBUG_REG6 0x6 #define ixIA_DEBUG_REG7 0x7 #define ixIA_DEBUG_REG8 0x8 #define ixIA_DEBUG_REG9 0x9 #define ixVGT_DEBUG_REG0 0x0 #define ixVGT_DEBUG_REG1 0x1 #define ixVGT_DEBUG_REG2 0x1e #define ixVGT_DEBUG_REG3 0x1f #define ixVGT_DEBUG_REG4 0x20 #define ixVGT_DEBUG_REG5 0x21 #define ixVGT_DEBUG_REG6 0x22 #define ixVGT_DEBUG_REG7 0x23 #define ixVGT_DEBUG_REG8 0x8 #define ixVGT_DEBUG_REG9 0x9 #define ixVGT_DEBUG_REG10 0xa #define ixVGT_DEBUG_REG11 0xb #define ixVGT_DEBUG_REG12 0xc #define ixVGT_DEBUG_REG13 0xd #define ixVGT_DEBUG_REG14 0xe #define ixVGT_DEBUG_REG15 0xf #define ixVGT_DEBUG_REG16 0x10 #define ixVGT_DEBUG_REG17 0x11 #define ixVGT_DEBUG_REG18 0x7 #define ixVGT_DEBUG_REG19 0x13 #define ixVGT_DEBUG_REG20 0x14 #define ixVGT_DEBUG_REG21 0x15 #define ixVGT_DEBUG_REG22 0x16 #define ixVGT_DEBUG_REG23 0x17 #define ixVGT_DEBUG_REG24 0x18 #define ixVGT_DEBUG_REG25 0x19 #define ixVGT_DEBUG_REG26 0x24 #define ixVGT_DEBUG_REG27 0x1b #define ixVGT_DEBUG_REG28 0x1c #define ixVGT_DEBUG_REG29 0x1d #define ixVGT_DEBUG_REG30 0x25 #define ixVGT_DEBUG_REG31 0x26 #define ixVGT_DEBUG_REG32 0x27 #define ixVGT_DEBUG_REG33 0x28 #define ixVGT_DEBUG_REG34 0x29 #define ixVGT_DEBUG_REG35 0x2a #define mmVGT_PERFCOUNTER_SEID_MASK 0xd894 #define mmVGT_PERFCOUNTER0_SELECT 0xd88c #define mmVGT_PERFCOUNTER1_SELECT 0xd88d #define mmVGT_PERFCOUNTER2_SELECT 0xd88e #define mmVGT_PERFCOUNTER3_SELECT 0xd88f #define mmVGT_PERFCOUNTER0_SELECT1 0xd890 #define mmVGT_PERFCOUNTER1_SELECT1 0xd891 #define mmVGT_PERFCOUNTER0_LO 0xd090 #define mmVGT_PERFCOUNTER1_LO 0xd092 #define mmVGT_PERFCOUNTER2_LO 0xd094 #define mmVGT_PERFCOUNTER3_LO 0xd096 #define mmVGT_PERFCOUNTER0_HI 0xd091 #define mmVGT_PERFCOUNTER1_HI 0xd093 #define mmVGT_PERFCOUNTER2_HI 0xd095 #define mmVGT_PERFCOUNTER3_HI 0xd097 #define mmIA_PERFCOUNTER0_SELECT 0xd884 #define mmIA_PERFCOUNTER1_SELECT 0xd885 #define mmIA_PERFCOUNTER2_SELECT 0xd886 #define mmIA_PERFCOUNTER3_SELECT 0xd887 #define mmIA_PERFCOUNTER0_SELECT1 0xd888 #define mmIA_PERFCOUNTER0_LO 0xd088 #define mmIA_PERFCOUNTER1_LO 0xd08a #define mmIA_PERFCOUNTER2_LO 0xd08c #define mmIA_PERFCOUNTER3_LO 0xd08e #define mmIA_PERFCOUNTER0_HI 0xd089 #define mmIA_PERFCOUNTER1_HI 0xd08b #define mmIA_PERFCOUNTER2_HI 0xd08d #define mmIA_PERFCOUNTER3_HI 0xd08f #define mmWD_PERFCOUNTER0_SELECT 0xd880 #define mmWD_PERFCOUNTER1_SELECT 0xd881 #define mmWD_PERFCOUNTER2_SELECT 0xd882 #define mmWD_PERFCOUNTER3_SELECT 0xd883 #define mmWD_PERFCOUNTER0_LO 0xd080 #define mmWD_PERFCOUNTER1_LO 0xd082 #define mmWD_PERFCOUNTER2_LO 0xd084 #define mmWD_PERFCOUNTER3_LO 0xd086 #define mmWD_PERFCOUNTER0_HI 0xd081 #define mmWD_PERFCOUNTER1_HI 0xd083 #define mmWD_PERFCOUNTER2_HI 0xd085 #define mmWD_PERFCOUNTER3_HI 0xd087 #define mmDIDT_IND_INDEX 0x3280 #define mmDIDT_IND_DATA 0x3281 #define ixDIDT_SQ_CTRL0 0x0 #define ixDIDT_SQ_CTRL1 0x1 #define ixDIDT_SQ_CTRL2 0x2 #define ixDIDT_SQ_WEIGHT0_3 0x10 #define ixDIDT_SQ_WEIGHT4_7 0x11 #define ixDIDT_SQ_WEIGHT8_11 0x12 #define ixDIDT_DB_CTRL0 0x20 #define ixDIDT_DB_CTRL1 0x21 #define ixDIDT_DB_CTRL2 0x22 #define ixDIDT_DB_WEIGHT0_3 0x30 #define ixDIDT_DB_WEIGHT4_7 0x31 #define ixDIDT_DB_WEIGHT8_11 0x32 #define ixDIDT_TD_CTRL0 0x40 #define ixDIDT_TD_CTRL1 0x41 #define ixDIDT_TD_CTRL2 0x42 #define ixDIDT_TD_WEIGHT0_3 0x50 #define ixDIDT_TD_WEIGHT4_7 0x51 #define ixDIDT_TD_WEIGHT8_11 0x52 #define ixDIDT_TCP_CTRL0 0x60 #define ixDIDT_TCP_CTRL1 0x61 #define ixDIDT_TCP_CTRL2 0x62 #define ixDIDT_TCP_WEIGHT0_3 0x70 #define ixDIDT_TCP_WEIGHT4_7 0x71 #define ixDIDT_TCP_WEIGHT8_11 0x72 #endif /* GFX_7_2_D_H */ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/include/asic_reg/gfx_7_2_enum.h000066400000000000000000012360311446477712600267020ustar00rootroot00000000000000/* * Copyright (C) 2014 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef GFX_7_2_ENUM_H #define GFX_7_2_ENUM_H typedef enum SurfaceNumber { NUMBER_UNORM = 0x0, NUMBER_SNORM = 0x1, NUMBER_USCALED = 0x2, NUMBER_SSCALED = 0x3, NUMBER_UINT = 0x4, NUMBER_SINT = 0x5, NUMBER_SRGB = 0x6, NUMBER_FLOAT = 0x7, } SurfaceNumber; typedef enum SurfaceSwap { SWAP_STD = 0x0, SWAP_ALT = 0x1, SWAP_STD_REV = 0x2, SWAP_ALT_REV = 0x3, } SurfaceSwap; typedef enum CBMode { CB_DISABLE = 0x0, CB_NORMAL = 0x1, CB_ELIMINATE_FAST_CLEAR = 0x2, CB_RESOLVE = 0x3, CB_DECOMPRESS = 0x4, CB_FMASK_DECOMPRESS = 0x5, } CBMode; typedef enum RoundMode { ROUND_BY_HALF = 0x0, ROUND_TRUNCATE = 0x1, } RoundMode; typedef enum SourceFormat { EXPORT_4C_32BPC = 0x0, EXPORT_4C_16BPC = 0x1, EXPORT_2C_32BPC_GR = 0x2, EXPORT_2C_32BPC_AR = 0x3, } SourceFormat; typedef enum BlendOp { BLEND_ZERO = 0x0, BLEND_ONE = 0x1, BLEND_SRC_COLOR = 0x2, BLEND_ONE_MINUS_SRC_COLOR = 0x3, BLEND_SRC_ALPHA = 0x4, BLEND_ONE_MINUS_SRC_ALPHA = 0x5, BLEND_DST_ALPHA = 0x6, BLEND_ONE_MINUS_DST_ALPHA = 0x7, BLEND_DST_COLOR = 0x8, BLEND_ONE_MINUS_DST_COLOR = 0x9, BLEND_SRC_ALPHA_SATURATE = 0xa, BLEND_BOTH_SRC_ALPHA = 0xb, BLEND_BOTH_INV_SRC_ALPHA = 0xc, BLEND_CONSTANT_COLOR = 0xd, BLEND_ONE_MINUS_CONSTANT_COLOR = 0xe, BLEND_SRC1_COLOR = 0xf, BLEND_INV_SRC1_COLOR = 0x10, BLEND_SRC1_ALPHA = 0x11, BLEND_INV_SRC1_ALPHA = 0x12, BLEND_CONSTANT_ALPHA = 0x13, BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, } BlendOp; typedef enum CombFunc { COMB_DST_PLUS_SRC = 0x0, COMB_SRC_MINUS_DST = 0x1, COMB_MIN_DST_SRC = 0x2, COMB_MAX_DST_SRC = 0x3, COMB_DST_MINUS_SRC = 0x4, } CombFunc; typedef enum BlendOpt { FORCE_OPT_AUTO = 0x0, FORCE_OPT_DISABLE = 0x1, FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x2, FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x3, FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x4, FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x5, FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x6, FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x7, } BlendOpt; typedef enum CmaskCode { CMASK_CLR00_F0 = 0x0, CMASK_CLR00_F1 = 0x1, CMASK_CLR00_F2 = 0x2, CMASK_CLR00_FX = 0x3, CMASK_CLR01_F0 = 0x4, CMASK_CLR01_F1 = 0x5, CMASK_CLR01_F2 = 0x6, CMASK_CLR01_FX = 0x7, CMASK_CLR10_F0 = 0x8, CMASK_CLR10_F1 = 0x9, CMASK_CLR10_F2 = 0xa, CMASK_CLR10_FX = 0xb, CMASK_CLR11_F0 = 0xc, CMASK_CLR11_F1 = 0xd, CMASK_CLR11_F2 = 0xe, CMASK_CLR11_FX = 0xf, } CmaskCode; typedef enum CBPerfSel { CB_PERF_SEL_NONE = 0x0, CB_PERF_SEL_BUSY = 0x1, CB_PERF_SEL_CORE_SCLK_VLD = 0x2, CB_PERF_SEL_REG_SCLK0_VLD = 0x3, CB_PERF_SEL_REG_SCLK1_VLD = 0x4, CB_PERF_SEL_DRAWN_QUAD = 0x5, CB_PERF_SEL_DRAWN_PIXEL = 0x6, CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x7, CB_PERF_SEL_DRAWN_TILE = 0x8, CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x9, CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa, CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0xb, CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0xc, CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0xd, CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0xe, CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0xf, CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x10, CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x11, CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x12, CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x13, CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x14, CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x15, CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x16, CB_PERF_SEL_LQUAD_NO_TILE = 0x17, CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x18, CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x19, CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x1a, CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x1b, CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x1c, CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d, CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e, CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x1f, CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x20, CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21, CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x22, CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x23, CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x24, CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x25, CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x26, CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x27, CB_PERF_SEL_FOP_IN_VALID_READY = 0x28, CB_PERF_SEL_FOP_IN_VALID_READYB = 0x29, CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x2a, CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x2b, CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x2c, CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x2d, CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x2e, CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x2f, CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x30, CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x31, CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x32, CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x33, CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x34, CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x35, CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x36, CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x37, CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x38, CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x39, CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x3a, CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x3b, CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x3c, CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x3d, CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x3e, CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x3f, CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x40, CB_PERF_SEL_CM_CACHE_HIT = 0x41, CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x42, CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x43, CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x44, CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45, CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46, CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47, CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x48, CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x49, CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x4a, CB_PERF_SEL_CM_CACHE_STALL = 0x4b, CB_PERF_SEL_CM_CACHE_FLUSH = 0x4c, CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x4d, CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x4e, CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x4f, CB_PERF_SEL_FC_CACHE_HIT = 0x50, CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x51, CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x52, CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x53, CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54, CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55, CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56, CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x57, CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x58, CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x59, CB_PERF_SEL_FC_CACHE_STALL = 0x5a, CB_PERF_SEL_FC_CACHE_FLUSH = 0x5b, CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x5c, CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x5d, CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x5e, CB_PERF_SEL_CC_CACHE_HIT = 0x5f, CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x60, CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x61, CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x62, CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63, CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64, CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65, CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x66, CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x67, CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x68, CB_PERF_SEL_CC_CACHE_STALL = 0x69, CB_PERF_SEL_CC_CACHE_FLUSH = 0x6a, CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x6b, CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x6c, CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x6d, CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x6e, CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x6f, CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x70, CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x71, CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x72, CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x73, CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x74, CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x75, CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x76, CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x77, CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x78, CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x79, CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x7a, CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x7b, CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x7c, CB_PERF_SEL_CM_MC_READ_REQUEST = 0x7d, CB_PERF_SEL_FC_MC_READ_REQUEST = 0x7e, CB_PERF_SEL_CC_MC_READ_REQUEST = 0x7f, CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x80, CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x81, CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x82, CB_PERF_SEL_CM_TQ_FULL = 0x83, CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x84, CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x85, CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x86, CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x87, CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x88, CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x89, CB_PERF_SEL_CC_SF_FULL = 0x8a, CB_PERF_SEL_CC_RB_FULL = 0x8b, CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x8c, CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x8d, CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x8e, CB_PERF_SEL_EVENT = 0x8f, CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x90, CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x91, CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x92, CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x93, CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x94, CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x95, CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x96, CB_PERF_SEL_CC_SURFACE_SYNC = 0x97, CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x98, CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x99, CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x9a, CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x9b, CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x9c, CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x9d, CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x9e, CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0x9f, CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0xa0, CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0xa1, CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0xa2, CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0xa3, CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0xa4, CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0xa5, CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0xa6, CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0xa7, CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0xa8, CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0xa9, CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0xaa, CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0xab, CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0xac, CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0xad, CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0xae, CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0xaf, CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0xb0, CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0xb1, CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0xb2, CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0xb3, CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0xb4, CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0xb5, CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0xb6, CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0xb7, CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0xb8, CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0xb9, CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0xba, CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0xbb, CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0xbc, CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0xbd, CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0xbe, CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0xbf, CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0xc0, CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0xc1, CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0xc2, CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0xc3, CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0xc4, CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0xc5, CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0xc6, CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0xc7, CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0xc8, CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0xc9, CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0xca, CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0xcb, CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0xcc, CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0xcd, CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0xce, CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0xcf, CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0xd0, CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0xd1, CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0xd2, CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0xd3, CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd4, CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd5, CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0xd6, CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0xd7, CB_PERF_SEL_DRAWN_BUSY = 0xd8, CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0xd9, CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0xda, CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0xdb, CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0xdc, CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xdd, CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0xde, CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0xdf, CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0xe0, CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe1, } CBPerfSel; typedef enum CBPerfOpFilterSel { CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x0, CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x1, CB_PERF_OP_FILTER_SEL_RESOLVE = 0x2, CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x3, CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x4, CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x5, } CBPerfOpFilterSel; typedef enum CBPerfClearFilterSel { CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x0, CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x1, } CBPerfClearFilterSel; typedef enum CP_RING_ID { RINGID0 = 0x0, RINGID1 = 0x1, RINGID2 = 0x2, RINGID3 = 0x3, } CP_RING_ID; typedef enum CP_PIPE_ID { PIPE_ID0 = 0x0, PIPE_ID1 = 0x1, PIPE_ID2 = 0x2, PIPE_ID3 = 0x3, } CP_PIPE_ID; typedef enum CP_ME_ID { ME_ID0 = 0x0, ME_ID1 = 0x1, ME_ID2 = 0x2, ME_ID3 = 0x3, } CP_ME_ID; typedef enum SPM_PERFMON_STATE { STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x0, STRM_PERFMON_STATE_START_COUNTING = 0x1, STRM_PERFMON_STATE_STOP_COUNTING = 0x2, STRM_PERFMON_STATE_RESERVED_3 = 0x3, STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4, STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5, } SPM_PERFMON_STATE; typedef enum CP_PERFMON_STATE { CP_PERFMON_STATE_DISABLE_AND_RESET = 0x0, CP_PERFMON_STATE_START_COUNTING = 0x1, CP_PERFMON_STATE_STOP_COUNTING = 0x2, CP_PERFMON_STATE_RESERVED_3 = 0x3, CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4, CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5, } CP_PERFMON_STATE; typedef enum CP_PERFMON_ENABLE_MODE { CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x0, CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x1, CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x2, CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x3, } CP_PERFMON_ENABLE_MODE; typedef enum CPG_PERFCOUNT_SEL { CPG_PERF_SEL_ALWAYS_COUNT = 0x0, CPG_PERF_SEL_RBIU_FIFO_FULL = 0x1, CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x2, CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x3, CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x4, CPG_PERF_SEL_ME_PARSER_BUSY = 0x5, CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x6, CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x7, CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x8, CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x9, CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa, CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0xb, CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0xc, CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0xd, CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0xe, CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0xf, CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x10, CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x11, CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x12, CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x13, CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x14, CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x15, CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x16, CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x17, CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x18, CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x19, CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x1a, CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x1b, CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x1c, CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x1d, CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x1e, CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x1f, CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x20, CPG_PERF_SEL_REGISTER_CLK_VALID = 0x21, CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x22, CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x23, CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x24, CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x25, CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x26, CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x27, CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x28, CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x29, CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x2a, CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x2b, CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x2c, CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x2d, } CPG_PERFCOUNT_SEL; typedef enum CPF_PERFCOUNT_SEL { CPF_PERF_SEL_ALWAYS_COUNT = 0x0, CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x1, CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x2, CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x3, CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x4, CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x5, CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x6, CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x7, CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x8, CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x9, CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa, CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0xb, CPF_PERF_SEL_GRBM_DWORDS_SENT = 0xc, CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0xd, CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0xe, CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0xf, CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x10, } CPF_PERFCOUNT_SEL; typedef enum CPC_PERFCOUNT_SEL { CPC_PERF_SEL_ALWAYS_COUNT = 0x0, CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x1, CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x2, CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x3, CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x4, CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x5, CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x6, CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x7, CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x8, CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x9, CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa, CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0xb, CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0xc, CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0xd, CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0xe, CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0xf, CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x10, CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x11, CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x12, CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x13, CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x14, CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x15, } CPC_PERFCOUNT_SEL; typedef enum CP_ALPHA_TAG_RAM_SEL { CPG_TAG_RAM = 0x0, CPC_TAG_RAM = 0x1, CPF_TAG_RAM = 0x2, RSV_TAG_RAM = 0x3, } CP_ALPHA_TAG_RAM_SEL; #define SEM_ECC_ERROR 0x0 #define SEM_RESERVED 0x1 #define SEM_FAILED 0x2 #define SEM_PASSED 0x3 #define IQ_QUEUE_SLEEP 0x0 #define IQ_OFFLOAD_RETRY 0x1 #define IQ_SCH_WAVE_MSG 0x2 #define IQ_SEM_REARM 0x3 #define IQ_DEQUEUE_RETRY 0x4 #define IQ_INTR_TYPE_PQ 0x0 #define IQ_INTR_TYPE_IB 0x1 #define IQ_INTR_TYPE_MQD 0x2 #define VMID_SZ 0x4 #define CONFIG_SPACE_START 0x2000 #define CONFIG_SPACE_END 0x9fff #define CONFIG_SPACE1_START 0x2000 #define CONFIG_SPACE1_END 0x2bff #define CONFIG_SPACE2_START 0x3000 #define CONFIG_SPACE2_END 0x9fff #define UCONFIG_SPACE_START 0xc000 #define UCONFIG_SPACE_END 0xffff #define PERSISTENT_SPACE_START 0x2c00 #define PERSISTENT_SPACE_END 0x2fff #define CONTEXT_SPACE_START 0xa000 #define CONTEXT_SPACE_END 0xbfff typedef enum ForceControl { FORCE_OFF = 0x0, FORCE_ENABLE = 0x1, FORCE_DISABLE = 0x2, FORCE_RESERVED = 0x3, } ForceControl; typedef enum ZSamplePosition { Z_SAMPLE_CENTER = 0x0, Z_SAMPLE_CENTROID = 0x1, } ZSamplePosition; typedef enum ZOrder { LATE_Z = 0x0, EARLY_Z_THEN_LATE_Z = 0x1, RE_Z = 0x2, EARLY_Z_THEN_RE_Z = 0x3, } ZOrder; typedef enum ZpassControl { ZPASS_DISABLE = 0x0, ZPASS_SAMPLES = 0x1, ZPASS_PIXELS = 0x2, } ZpassControl; typedef enum ZModeForce { NO_FORCE = 0x0, FORCE_EARLY_Z = 0x1, FORCE_LATE_Z = 0x2, FORCE_RE_Z = 0x3, } ZModeForce; typedef enum ZLimitSumm { FORCE_SUMM_OFF = 0x0, FORCE_SUMM_MINZ = 0x1, FORCE_SUMM_MAXZ = 0x2, FORCE_SUMM_BOTH = 0x3, } ZLimitSumm; typedef enum CompareFrag { FRAG_NEVER = 0x0, FRAG_LESS = 0x1, FRAG_EQUAL = 0x2, FRAG_LEQUAL = 0x3, FRAG_GREATER = 0x4, FRAG_NOTEQUAL = 0x5, FRAG_GEQUAL = 0x6, FRAG_ALWAYS = 0x7, } CompareFrag; typedef enum StencilOp { STENCIL_KEEP = 0x0, STENCIL_ZERO = 0x1, STENCIL_ONES = 0x2, STENCIL_REPLACE_TEST = 0x3, STENCIL_REPLACE_OP = 0x4, STENCIL_ADD_CLAMP = 0x5, STENCIL_SUB_CLAMP = 0x6, STENCIL_INVERT = 0x7, STENCIL_ADD_WRAP = 0x8, STENCIL_SUB_WRAP = 0x9, STENCIL_AND = 0xa, STENCIL_OR = 0xb, STENCIL_XOR = 0xc, STENCIL_NAND = 0xd, STENCIL_NOR = 0xe, STENCIL_XNOR = 0xf, } StencilOp; typedef enum ConservativeZExport { EXPORT_ANY_Z = 0x0, EXPORT_LESS_THAN_Z = 0x1, EXPORT_GREATER_THAN_Z = 0x2, EXPORT_RESERVED = 0x3, } ConservativeZExport; typedef enum DbPSLControl { PSLC_AUTO = 0x0, PSLC_ON_HANG_ONLY = 0x1, PSLC_ASAP = 0x2, PSLC_COUNTDOWN = 0x3, } DbPSLControl; typedef enum PerfCounter_Vals { DB_PERF_SEL_SC_DB_tile_sends = 0x0, DB_PERF_SEL_SC_DB_tile_busy = 0x1, DB_PERF_SEL_SC_DB_tile_stalls = 0x2, DB_PERF_SEL_SC_DB_tile_events = 0x3, DB_PERF_SEL_SC_DB_tile_tiles = 0x4, DB_PERF_SEL_SC_DB_tile_covered = 0x5, DB_PERF_SEL_hiz_tc_read_starved = 0x6, DB_PERF_SEL_hiz_tc_write_stall = 0x7, DB_PERF_SEL_hiz_qtiles_culled = 0x8, DB_PERF_SEL_his_qtiles_culled = 0x9, DB_PERF_SEL_DB_SC_tile_sends = 0xa, DB_PERF_SEL_DB_SC_tile_busy = 0xb, DB_PERF_SEL_DB_SC_tile_stalls = 0xc, DB_PERF_SEL_DB_SC_tile_df_stalls = 0xd, DB_PERF_SEL_DB_SC_tile_tiles = 0xe, DB_PERF_SEL_DB_SC_tile_culled = 0xf, DB_PERF_SEL_DB_SC_tile_hier_kill = 0x10, DB_PERF_SEL_DB_SC_tile_fast_ops = 0x11, DB_PERF_SEL_DB_SC_tile_no_ops = 0x12, DB_PERF_SEL_DB_SC_tile_tile_rate = 0x13, DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x14, DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x15, DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x16, DB_PERF_SEL_SC_DB_quad_sends = 0x17, DB_PERF_SEL_SC_DB_quad_busy = 0x18, DB_PERF_SEL_SC_DB_quad_squads = 0x19, DB_PERF_SEL_SC_DB_quad_tiles = 0x1a, DB_PERF_SEL_SC_DB_quad_pixels = 0x1b, DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x1c, DB_PERF_SEL_DB_SC_quad_sends = 0x1d, DB_PERF_SEL_DB_SC_quad_busy = 0x1e, DB_PERF_SEL_DB_SC_quad_stalls = 0x1f, DB_PERF_SEL_DB_SC_quad_tiles = 0x20, DB_PERF_SEL_DB_SC_quad_lit_quad = 0x21, DB_PERF_SEL_DB_CB_tile_sends = 0x22, DB_PERF_SEL_DB_CB_tile_busy = 0x23, DB_PERF_SEL_DB_CB_tile_stalls = 0x24, DB_PERF_SEL_SX_DB_quad_sends = 0x25, DB_PERF_SEL_SX_DB_quad_busy = 0x26, DB_PERF_SEL_SX_DB_quad_stalls = 0x27, DB_PERF_SEL_SX_DB_quad_quads = 0x28, DB_PERF_SEL_SX_DB_quad_pixels = 0x29, DB_PERF_SEL_SX_DB_quad_exports = 0x2a, DB_PERF_SEL_SH_quads_outstanding_sum = 0x2b, DB_PERF_SEL_DB_CB_lquad_sends = 0x2c, DB_PERF_SEL_DB_CB_lquad_busy = 0x2d, DB_PERF_SEL_DB_CB_lquad_stalls = 0x2e, DB_PERF_SEL_DB_CB_lquad_quads = 0x2f, DB_PERF_SEL_tile_rd_sends = 0x30, DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x31, DB_PERF_SEL_quad_rd_sends = 0x32, DB_PERF_SEL_quad_rd_busy = 0x33, DB_PERF_SEL_quad_rd_mi_stall = 0x34, DB_PERF_SEL_quad_rd_rw_collision = 0x35, DB_PERF_SEL_quad_rd_tag_stall = 0x36, DB_PERF_SEL_quad_rd_32byte_reqs = 0x37, DB_PERF_SEL_quad_rd_panic = 0x38, DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x39, DB_PERF_SEL_quad_rdret_sends = 0x3a, DB_PERF_SEL_quad_rdret_busy = 0x3b, DB_PERF_SEL_tile_wr_sends = 0x3c, DB_PERF_SEL_tile_wr_acks = 0x3d, DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x3e, DB_PERF_SEL_quad_wr_sends = 0x3f, DB_PERF_SEL_quad_wr_busy = 0x40, DB_PERF_SEL_quad_wr_mi_stall = 0x41, DB_PERF_SEL_quad_wr_coherency_stall = 0x42, DB_PERF_SEL_quad_wr_acks = 0x43, DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x44, DB_PERF_SEL_Tile_Cache_misses = 0x45, DB_PERF_SEL_Tile_Cache_hits = 0x46, DB_PERF_SEL_Tile_Cache_flushes = 0x47, DB_PERF_SEL_Tile_Cache_surface_stall = 0x48, DB_PERF_SEL_Tile_Cache_starves = 0x49, DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x4a, DB_PERF_SEL_tcp_dispatcher_reads = 0x4b, DB_PERF_SEL_tcp_prefetcher_reads = 0x4c, DB_PERF_SEL_tcp_preloader_reads = 0x4d, DB_PERF_SEL_tcp_dispatcher_flushes = 0x4e, DB_PERF_SEL_tcp_prefetcher_flushes = 0x4f, DB_PERF_SEL_tcp_preloader_flushes = 0x50, DB_PERF_SEL_Depth_Tile_Cache_sends = 0x51, DB_PERF_SEL_Depth_Tile_Cache_busy = 0x52, DB_PERF_SEL_Depth_Tile_Cache_starves = 0x53, DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x54, DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x55, DB_PERF_SEL_Depth_Tile_Cache_misses = 0x56, DB_PERF_SEL_Depth_Tile_Cache_hits = 0x57, DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x58, DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x59, DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x5a, DB_PERF_SEL_Depth_Tile_Cache_event = 0x5b, DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x5c, DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x5d, DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x5e, DB_PERF_SEL_Stencil_Cache_misses = 0x5f, DB_PERF_SEL_Stencil_Cache_hits = 0x60, DB_PERF_SEL_Stencil_Cache_flushes = 0x61, DB_PERF_SEL_Stencil_Cache_starves = 0x62, DB_PERF_SEL_Stencil_Cache_frees = 0x63, DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x64, DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x65, DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x66, DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x67, DB_PERF_SEL_Z_Cache_pmask_misses = 0x68, DB_PERF_SEL_Z_Cache_pmask_hits = 0x69, DB_PERF_SEL_Z_Cache_pmask_flushes = 0x6a, DB_PERF_SEL_Z_Cache_pmask_starves = 0x6b, DB_PERF_SEL_Z_Cache_frees = 0x6c, DB_PERF_SEL_Plane_Cache_misses = 0x6d, DB_PERF_SEL_Plane_Cache_hits = 0x6e, DB_PERF_SEL_Plane_Cache_flushes = 0x6f, DB_PERF_SEL_Plane_Cache_starves = 0x70, DB_PERF_SEL_Plane_Cache_frees = 0x71, DB_PERF_SEL_flush_expanded_stencil = 0x72, DB_PERF_SEL_flush_compressed_stencil = 0x73, DB_PERF_SEL_flush_single_stencil = 0x74, DB_PERF_SEL_planes_flushed = 0x75, DB_PERF_SEL_flush_1plane = 0x76, DB_PERF_SEL_flush_2plane = 0x77, DB_PERF_SEL_flush_3plane = 0x78, DB_PERF_SEL_flush_4plane = 0x79, DB_PERF_SEL_flush_5plane = 0x7a, DB_PERF_SEL_flush_6plane = 0x7b, DB_PERF_SEL_flush_7plane = 0x7c, DB_PERF_SEL_flush_8plane = 0x7d, DB_PERF_SEL_flush_9plane = 0x7e, DB_PERF_SEL_flush_10plane = 0x7f, DB_PERF_SEL_flush_11plane = 0x80, DB_PERF_SEL_flush_12plane = 0x81, DB_PERF_SEL_flush_13plane = 0x82, DB_PERF_SEL_flush_14plane = 0x83, DB_PERF_SEL_flush_15plane = 0x84, DB_PERF_SEL_flush_16plane = 0x85, DB_PERF_SEL_flush_expanded_z = 0x86, DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x87, DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x88, DB_PERF_SEL_dk_tile_sends = 0x89, DB_PERF_SEL_dk_tile_busy = 0x8a, DB_PERF_SEL_dk_tile_quad_starves = 0x8b, DB_PERF_SEL_dk_tile_stalls = 0x8c, DB_PERF_SEL_dk_squad_sends = 0x8d, DB_PERF_SEL_dk_squad_busy = 0x8e, DB_PERF_SEL_dk_squad_stalls = 0x8f, DB_PERF_SEL_Op_Pipe_Busy = 0x90, DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x91, DB_PERF_SEL_qc_busy = 0x92, DB_PERF_SEL_qc_xfc = 0x93, DB_PERF_SEL_qc_conflicts = 0x94, DB_PERF_SEL_qc_full_stall = 0x95, DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x96, DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x97, DB_PERF_SEL_tsc_insert_summarize_stall = 0x98, DB_PERF_SEL_tl_busy = 0x99, DB_PERF_SEL_tl_dtc_read_starved = 0x9a, DB_PERF_SEL_tl_z_fetch_stall = 0x9b, DB_PERF_SEL_tl_stencil_stall = 0x9c, DB_PERF_SEL_tl_z_decompress_stall = 0x9d, DB_PERF_SEL_tl_stencil_locked_stall = 0x9e, DB_PERF_SEL_tl_events = 0x9f, DB_PERF_SEL_tl_summarize_squads = 0xa0, DB_PERF_SEL_tl_flush_expand_squads = 0xa1, DB_PERF_SEL_tl_expand_squads = 0xa2, DB_PERF_SEL_tl_preZ_squads = 0xa3, DB_PERF_SEL_tl_postZ_squads = 0xa4, DB_PERF_SEL_tl_preZ_noop_squads = 0xa5, DB_PERF_SEL_tl_postZ_noop_squads = 0xa6, DB_PERF_SEL_tl_tile_ops = 0xa7, DB_PERF_SEL_tl_in_xfc = 0xa8, DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0xa9, DB_PERF_SEL_tl_in_fast_z_stall = 0xaa, DB_PERF_SEL_tl_out_xfc = 0xab, DB_PERF_SEL_tl_out_squads = 0xac, DB_PERF_SEL_zf_plane_multicycle = 0xad, DB_PERF_SEL_PostZ_Samples_passing_Z = 0xae, DB_PERF_SEL_PostZ_Samples_failing_Z = 0xaf, DB_PERF_SEL_PostZ_Samples_failing_S = 0xb0, DB_PERF_SEL_PreZ_Samples_passing_Z = 0xb1, DB_PERF_SEL_PreZ_Samples_failing_Z = 0xb2, DB_PERF_SEL_PreZ_Samples_failing_S = 0xb3, DB_PERF_SEL_ts_tc_update_stall = 0xb4, DB_PERF_SEL_sc_kick_start = 0xb5, DB_PERF_SEL_sc_kick_end = 0xb6, DB_PERF_SEL_clock_reg_active = 0xb7, DB_PERF_SEL_clock_main_active = 0xb8, DB_PERF_SEL_clock_mem_export_active = 0xb9, DB_PERF_SEL_esr_ps_out_busy = 0xba, DB_PERF_SEL_esr_ps_lqf_busy = 0xbb, DB_PERF_SEL_esr_ps_lqf_stall = 0xbc, DB_PERF_SEL_etr_out_send = 0xbd, DB_PERF_SEL_etr_out_busy = 0xbe, DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0xbf, DB_PERF_SEL_etr_out_cb_tile_stall = 0xc0, DB_PERF_SEL_etr_out_esr_stall = 0xc1, DB_PERF_SEL_esr_ps_sqq_busy = 0xc2, DB_PERF_SEL_esr_ps_sqq_stall = 0xc3, DB_PERF_SEL_esr_eot_fwd_busy = 0xc4, DB_PERF_SEL_esr_eot_fwd_holding_squad = 0xc5, DB_PERF_SEL_esr_eot_fwd_forward = 0xc6, DB_PERF_SEL_esr_sqq_zi_busy = 0xc7, DB_PERF_SEL_esr_sqq_zi_stall = 0xc8, DB_PERF_SEL_postzl_sq_pt_busy = 0xc9, DB_PERF_SEL_postzl_sq_pt_stall = 0xca, DB_PERF_SEL_postzl_se_busy = 0xcb, DB_PERF_SEL_postzl_se_stall = 0xcc, DB_PERF_SEL_postzl_partial_launch = 0xcd, DB_PERF_SEL_postzl_full_launch = 0xce, DB_PERF_SEL_postzl_partial_waiting = 0xcf, DB_PERF_SEL_postzl_tile_mem_stall = 0xd0, DB_PERF_SEL_postzl_tile_init_stall = 0xd1, DB_PEFF_SEL_prezl_tile_mem_stall = 0xd2, DB_PERF_SEL_prezl_tile_init_stall = 0xd3, DB_PERF_SEL_dtt_sm_clash_stall = 0xd4, DB_PERF_SEL_dtt_sm_slot_stall = 0xd5, DB_PERF_SEL_dtt_sm_miss_stall = 0xd6, DB_PERF_SEL_mi_rdreq_busy = 0xd7, DB_PERF_SEL_mi_rdreq_stall = 0xd8, DB_PERF_SEL_mi_wrreq_busy = 0xd9, DB_PERF_SEL_mi_wrreq_stall = 0xda, DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0xdb, DB_PERF_SEL_dkg_tile_rate_tile = 0xdc, DB_PERF_SEL_prezl_src_in_sends = 0xdd, DB_PERF_SEL_prezl_src_in_stall = 0xde, DB_PERF_SEL_prezl_src_in_squads = 0xdf, DB_PERF_SEL_prezl_src_in_squads_unrolled = 0xe0, DB_PERF_SEL_prezl_src_in_tile_rate = 0xe1, DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0xe2, DB_PERF_SEL_prezl_src_out_stall = 0xe3, DB_PERF_SEL_postzl_src_in_sends = 0xe4, DB_PERF_SEL_postzl_src_in_stall = 0xe5, DB_PERF_SEL_postzl_src_in_squads = 0xe6, DB_PERF_SEL_postzl_src_in_squads_unrolled = 0xe7, DB_PERF_SEL_postzl_src_in_tile_rate = 0xe8, DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0xe9, DB_PERF_SEL_postzl_src_out_stall = 0xea, DB_PERF_SEL_esr_ps_src_in_sends = 0xeb, DB_PERF_SEL_esr_ps_src_in_stall = 0xec, DB_PERF_SEL_esr_ps_src_in_squads = 0xed, DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0xee, DB_PERF_SEL_esr_ps_src_in_tile_rate = 0xef, DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0xf0, DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1, DB_PERF_SEL_esr_ps_src_out_stall = 0xf2, DB_PERF_SEL_depth_bounds_qtiles_culled = 0xf3, DB_PERF_SEL_PreZ_Samples_failing_DB = 0xf4, DB_PERF_SEL_PostZ_Samples_failing_DB = 0xf5, DB_PERF_SEL_flush_compressed = 0xf6, DB_PERF_SEL_flush_plane_le4 = 0xf7, DB_PERF_SEL_tiles_z_fully_summarized = 0xf8, DB_PERF_SEL_tiles_stencil_fully_summarized = 0xf9, DB_PERF_SEL_tiles_z_clear_on_expclear = 0xfa, DB_PERF_SEL_tiles_s_clear_on_expclear = 0xfb, DB_PERF_SEL_tiles_decomp_on_expclear = 0xfc, DB_PERF_SEL_tiles_compressed_to_decompressed = 0xfd, DB_PERF_SEL_Op_Pipe_Prez_Busy = 0xfe, DB_PERF_SEL_Op_Pipe_Postz_Busy = 0xff, DB_PERF_SEL_di_dt_stall = 0x100, } PerfCounter_Vals; typedef enum RingCounterControl { COUNTER_RING_SPLIT = 0x0, COUNTER_RING_0 = 0x1, COUNTER_RING_1 = 0x2, } RingCounterControl; typedef enum PixelPipeCounterId { PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x0, PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x1, PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x2, PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x3, PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x4, PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x5, PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x6, PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x7, } PixelPipeCounterId; typedef enum PixelPipeStride { PIXEL_PIPE_STRIDE_32_BITS = 0x0, PIXEL_PIPE_STRIDE_64_BITS = 0x1, PIXEL_PIPE_STRIDE_128_BITS = 0x2, PIXEL_PIPE_STRIDE_256_BITS = 0x3, } PixelPipeStride; typedef enum GB_EDC_DED_MODE { GB_EDC_DED_MODE_LOG = 0x0, GB_EDC_DED_MODE_HALT = 0x1, GB_EDC_DED_MODE_INT_HALT = 0x2, } GB_EDC_DED_MODE; #define GB_TILING_CONFIG_TABLE_SIZE 0x20 #define GB_TILING_CONFIG_MACROTABLE_SIZE 0x10 typedef enum GRBM_PERF_SEL { GRBM_PERF_SEL_COUNT = 0x0, GRBM_PERF_SEL_USER_DEFINED = 0x1, GRBM_PERF_SEL_GUI_ACTIVE = 0x2, GRBM_PERF_SEL_CP_BUSY = 0x3, GRBM_PERF_SEL_CP_COHER_BUSY = 0x4, GRBM_PERF_SEL_CP_DMA_BUSY = 0x5, GRBM_PERF_SEL_CB_BUSY = 0x6, GRBM_PERF_SEL_DB_BUSY = 0x7, GRBM_PERF_SEL_PA_BUSY = 0x8, GRBM_PERF_SEL_SC_BUSY = 0x9, GRBM_PERF_SEL_RESERVED_6 = 0xa, GRBM_PERF_SEL_SPI_BUSY = 0xb, GRBM_PERF_SEL_SX_BUSY = 0xc, GRBM_PERF_SEL_TA_BUSY = 0xd, GRBM_PERF_SEL_CB_CLEAN = 0xe, GRBM_PERF_SEL_DB_CLEAN = 0xf, GRBM_PERF_SEL_RESERVED_5 = 0x10, GRBM_PERF_SEL_VGT_BUSY = 0x11, GRBM_PERF_SEL_RESERVED_4 = 0x12, GRBM_PERF_SEL_RESERVED_3 = 0x13, GRBM_PERF_SEL_RESERVED_2 = 0x14, GRBM_PERF_SEL_RESERVED_1 = 0x15, GRBM_PERF_SEL_RESERVED_0 = 0x16, GRBM_PERF_SEL_IA_BUSY = 0x17, GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x18, GRBM_PERF_SEL_GDS_BUSY = 0x19, GRBM_PERF_SEL_BCI_BUSY = 0x1a, GRBM_PERF_SEL_RLC_BUSY = 0x1b, GRBM_PERF_SEL_TC_BUSY = 0x1c, GRBM_PERF_SEL_CPG_BUSY = 0x1d, GRBM_PERF_SEL_CPC_BUSY = 0x1e, GRBM_PERF_SEL_CPF_BUSY = 0x1f, GRBM_PERF_SEL_WD_BUSY = 0x20, GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x21, } GRBM_PERF_SEL; typedef enum GRBM_SE0_PERF_SEL { GRBM_SE0_PERF_SEL_COUNT = 0x0, GRBM_SE0_PERF_SEL_USER_DEFINED = 0x1, GRBM_SE0_PERF_SEL_CB_BUSY = 0x2, GRBM_SE0_PERF_SEL_DB_BUSY = 0x3, GRBM_SE0_PERF_SEL_SC_BUSY = 0x4, GRBM_SE0_PERF_SEL_RESERVED_1 = 0x5, GRBM_SE0_PERF_SEL_SPI_BUSY = 0x6, GRBM_SE0_PERF_SEL_SX_BUSY = 0x7, GRBM_SE0_PERF_SEL_TA_BUSY = 0x8, GRBM_SE0_PERF_SEL_CB_CLEAN = 0x9, GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa, GRBM_SE0_PERF_SEL_RESERVED_0 = 0xb, GRBM_SE0_PERF_SEL_PA_BUSY = 0xc, GRBM_SE0_PERF_SEL_VGT_BUSY = 0xd, GRBM_SE0_PERF_SEL_BCI_BUSY = 0xe, } GRBM_SE0_PERF_SEL; typedef enum GRBM_SE1_PERF_SEL { GRBM_SE1_PERF_SEL_COUNT = 0x0, GRBM_SE1_PERF_SEL_USER_DEFINED = 0x1, GRBM_SE1_PERF_SEL_CB_BUSY = 0x2, GRBM_SE1_PERF_SEL_DB_BUSY = 0x3, GRBM_SE1_PERF_SEL_SC_BUSY = 0x4, GRBM_SE1_PERF_SEL_RESERVED_1 = 0x5, GRBM_SE1_PERF_SEL_SPI_BUSY = 0x6, GRBM_SE1_PERF_SEL_SX_BUSY = 0x7, GRBM_SE1_PERF_SEL_TA_BUSY = 0x8, GRBM_SE1_PERF_SEL_CB_CLEAN = 0x9, GRBM_SE1_PERF_SEL_DB_CLEAN = 0xa, GRBM_SE1_PERF_SEL_RESERVED_0 = 0xb, GRBM_SE1_PERF_SEL_PA_BUSY = 0xc, GRBM_SE1_PERF_SEL_VGT_BUSY = 0xd, GRBM_SE1_PERF_SEL_BCI_BUSY = 0xe, } GRBM_SE1_PERF_SEL; typedef enum GRBM_SE2_PERF_SEL { GRBM_SE2_PERF_SEL_COUNT = 0x0, GRBM_SE2_PERF_SEL_USER_DEFINED = 0x1, GRBM_SE2_PERF_SEL_CB_BUSY = 0x2, GRBM_SE2_PERF_SEL_DB_BUSY = 0x3, GRBM_SE2_PERF_SEL_SC_BUSY = 0x4, GRBM_SE2_PERF_SEL_RESERVED_1 = 0x5, GRBM_SE2_PERF_SEL_SPI_BUSY = 0x6, GRBM_SE2_PERF_SEL_SX_BUSY = 0x7, GRBM_SE2_PERF_SEL_TA_BUSY = 0x8, GRBM_SE2_PERF_SEL_CB_CLEAN = 0x9, GRBM_SE2_PERF_SEL_DB_CLEAN = 0xa, GRBM_SE2_PERF_SEL_RESERVED_0 = 0xb, GRBM_SE2_PERF_SEL_PA_BUSY = 0xc, GRBM_SE2_PERF_SEL_VGT_BUSY = 0xd, GRBM_SE2_PERF_SEL_BCI_BUSY = 0xe, } GRBM_SE2_PERF_SEL; typedef enum GRBM_SE3_PERF_SEL { GRBM_SE3_PERF_SEL_COUNT = 0x0, GRBM_SE3_PERF_SEL_USER_DEFINED = 0x1, GRBM_SE3_PERF_SEL_CB_BUSY = 0x2, GRBM_SE3_PERF_SEL_DB_BUSY = 0x3, GRBM_SE3_PERF_SEL_SC_BUSY = 0x4, GRBM_SE3_PERF_SEL_RESERVED_1 = 0x5, GRBM_SE3_PERF_SEL_SPI_BUSY = 0x6, GRBM_SE3_PERF_SEL_SX_BUSY = 0x7, GRBM_SE3_PERF_SEL_TA_BUSY = 0x8, GRBM_SE3_PERF_SEL_CB_CLEAN = 0x9, GRBM_SE3_PERF_SEL_DB_CLEAN = 0xa, GRBM_SE3_PERF_SEL_RESERVED_0 = 0xb, GRBM_SE3_PERF_SEL_PA_BUSY = 0xc, GRBM_SE3_PERF_SEL_VGT_BUSY = 0xd, GRBM_SE3_PERF_SEL_BCI_BUSY = 0xe, } GRBM_SE3_PERF_SEL; typedef enum SU_PERFCNT_SEL { PERF_PAPC_PASX_REQ = 0x0, PERF_PAPC_PASX_DISABLE_PIPE = 0x1, PERF_PAPC_PASX_FIRST_VECTOR = 0x2, PERF_PAPC_PASX_SECOND_VECTOR = 0x3, PERF_PAPC_PASX_FIRST_DEAD = 0x4, PERF_PAPC_PASX_SECOND_DEAD = 0x5, PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x6, PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x7, PERF_PAPC_PA_INPUT_PRIM = 0x8, PERF_PAPC_PA_INPUT_NULL_PRIM = 0x9, PERF_PAPC_PA_INPUT_EVENT_FLAG = 0xa, PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0xb, PERF_PAPC_PA_INPUT_END_OF_PACKET = 0xc, PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0xd, PERF_PAPC_CLPR_CULL_PRIM = 0xe, PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0xf, PERF_PAPC_CLPR_VV_CULL_PRIM = 0x10, PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x11, PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x12, PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x13, PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x14, PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x15, PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x16, PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x17, PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x18, PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x19, PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x1a, PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x1b, PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x1c, PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x1d, PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x1e, PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x1f, PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x20, PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x21, PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x22, PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x23, PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x24, PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x25, PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x26, PERF_PAPC_CLSM_NULL_PRIM = 0x27, PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x28, PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x29, PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x2a, PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x2b, PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x2c, PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x2d, PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x2e, PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x2f, PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x30, PERF_PAPC_SU_INPUT_PRIM = 0x31, PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x32, PERF_PAPC_SU_INPUT_NULL_PRIM = 0x33, PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x34, PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x35, PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x36, PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x37, PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x38, PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x39, PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x3a, PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x3b, PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x3c, PERF_PAPC_SU_OUTPUT_PRIM = 0x3d, PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x3e, PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x3f, PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x40, PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x41, PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x42, PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x43, PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x44, PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x45, PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x46, PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x47, PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x48, PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x49, PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x4a, PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x4b, PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x4c, PERF_PAPC_PASX_REQ_IDLE = 0x4d, PERF_PAPC_PASX_REQ_BUSY = 0x4e, PERF_PAPC_PASX_REQ_STALLED = 0x4f, PERF_PAPC_PASX_REC_IDLE = 0x50, PERF_PAPC_PASX_REC_BUSY = 0x51, PERF_PAPC_PASX_REC_STARVED_SX = 0x52, PERF_PAPC_PASX_REC_STALLED = 0x53, PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x54, PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x55, PERF_PAPC_CCGSM_IDLE = 0x56, PERF_PAPC_CCGSM_BUSY = 0x57, PERF_PAPC_CCGSM_STALLED = 0x58, PERF_PAPC_CLPRIM_IDLE = 0x59, PERF_PAPC_CLPRIM_BUSY = 0x5a, PERF_PAPC_CLPRIM_STALLED = 0x5b, PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x5c, PERF_PAPC_CLIPSM_IDLE = 0x5d, PERF_PAPC_CLIPSM_BUSY = 0x5e, PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x5f, PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x60, PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x61, PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x62, PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x63, PERF_PAPC_CLIPGA_IDLE = 0x64, PERF_PAPC_CLIPGA_BUSY = 0x65, PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x66, PERF_PAPC_CLIPGA_STALLED = 0x67, PERF_PAPC_CLIP_IDLE = 0x68, PERF_PAPC_CLIP_BUSY = 0x69, PERF_PAPC_SU_IDLE = 0x6a, PERF_PAPC_SU_BUSY = 0x6b, PERF_PAPC_SU_STARVED_CLIP = 0x6c, PERF_PAPC_SU_STALLED_SC = 0x6d, PERF_PAPC_CL_DYN_SCLK_VLD = 0x6e, PERF_PAPC_SU_DYN_SCLK_VLD = 0x6f, PERF_PAPC_PA_REG_SCLK_VLD = 0x70, PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x71, PERF_PAPC_PASX_SE0_REQ = 0x72, PERF_PAPC_PASX_SE1_REQ = 0x73, PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x74, PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x75, PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x76, PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x77, PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x78, PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x79, PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x7a, PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x7b, PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x7c, PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x7d, PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x7e, PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x7f, PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x80, PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x81, PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x82, PERF_PAPC_SU_SE0_STALLED_SC = 0x83, PERF_PAPC_SU_SE1_STALLED_SC = 0x84, PERF_PAPC_SU_SE01_STALLED_SC = 0x85, PERF_PAPC_CLSM_CLIPPING_PRIM = 0x86, PERF_PAPC_SU_CULLED_PRIM = 0x87, PERF_PAPC_SU_OUTPUT_EOPG = 0x88, PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x89, PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x8a, PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x8b, PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x8c, PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x8d, PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x8e, PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x8f, PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x90, PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x91, PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x92, PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x93, PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x94, PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x95, PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x96, PERF_PAPC_SU_SE2_STALLED_SC = 0x97, PERF_PAPC_SU_SE3_STALLED_SC = 0x98, } SU_PERFCNT_SEL; typedef enum SC_PERFCNT_SEL { SC_SRPS_WINDOW_VALID = 0x0, SC_PSSW_WINDOW_VALID = 0x1, SC_TPQZ_WINDOW_VALID = 0x2, SC_QZQP_WINDOW_VALID = 0x3, SC_TRPK_WINDOW_VALID = 0x4, SC_SRPS_WINDOW_VALID_BUSY = 0x5, SC_PSSW_WINDOW_VALID_BUSY = 0x6, SC_TPQZ_WINDOW_VALID_BUSY = 0x7, SC_QZQP_WINDOW_VALID_BUSY = 0x8, SC_TRPK_WINDOW_VALID_BUSY = 0x9, SC_STARVED_BY_PA = 0xa, SC_STALLED_BY_PRIMFIFO = 0xb, SC_STALLED_BY_DB_TILE = 0xc, SC_STARVED_BY_DB_TILE = 0xd, SC_STALLED_BY_TILEORDERFIFO = 0xe, SC_STALLED_BY_TILEFIFO = 0xf, SC_STALLED_BY_DB_QUAD = 0x10, SC_STARVED_BY_DB_QUAD = 0x11, SC_STALLED_BY_QUADFIFO = 0x12, SC_STALLED_BY_BCI = 0x13, SC_STALLED_BY_SPI = 0x14, SC_SCISSOR_DISCARD = 0x15, SC_BB_DISCARD = 0x16, SC_SUPERTILE_COUNT = 0x17, SC_SUPERTILE_PER_PRIM_H0 = 0x18, SC_SUPERTILE_PER_PRIM_H1 = 0x19, SC_SUPERTILE_PER_PRIM_H2 = 0x1a, SC_SUPERTILE_PER_PRIM_H3 = 0x1b, SC_SUPERTILE_PER_PRIM_H4 = 0x1c, SC_SUPERTILE_PER_PRIM_H5 = 0x1d, SC_SUPERTILE_PER_PRIM_H6 = 0x1e, SC_SUPERTILE_PER_PRIM_H7 = 0x1f, SC_SUPERTILE_PER_PRIM_H8 = 0x20, SC_SUPERTILE_PER_PRIM_H9 = 0x21, SC_SUPERTILE_PER_PRIM_H10 = 0x22, SC_SUPERTILE_PER_PRIM_H11 = 0x23, SC_SUPERTILE_PER_PRIM_H12 = 0x24, SC_SUPERTILE_PER_PRIM_H13 = 0x25, SC_SUPERTILE_PER_PRIM_H14 = 0x26, SC_SUPERTILE_PER_PRIM_H15 = 0x27, SC_SUPERTILE_PER_PRIM_H16 = 0x28, SC_TILE_PER_PRIM_H0 = 0x29, SC_TILE_PER_PRIM_H1 = 0x2a, SC_TILE_PER_PRIM_H2 = 0x2b, SC_TILE_PER_PRIM_H3 = 0x2c, SC_TILE_PER_PRIM_H4 = 0x2d, SC_TILE_PER_PRIM_H5 = 0x2e, SC_TILE_PER_PRIM_H6 = 0x2f, SC_TILE_PER_PRIM_H7 = 0x30, SC_TILE_PER_PRIM_H8 = 0x31, SC_TILE_PER_PRIM_H9 = 0x32, SC_TILE_PER_PRIM_H10 = 0x33, SC_TILE_PER_PRIM_H11 = 0x34, SC_TILE_PER_PRIM_H12 = 0x35, SC_TILE_PER_PRIM_H13 = 0x36, SC_TILE_PER_PRIM_H14 = 0x37, SC_TILE_PER_PRIM_H15 = 0x38, SC_TILE_PER_PRIM_H16 = 0x39, SC_TILE_PER_SUPERTILE_H0 = 0x3a, SC_TILE_PER_SUPERTILE_H1 = 0x3b, SC_TILE_PER_SUPERTILE_H2 = 0x3c, SC_TILE_PER_SUPERTILE_H3 = 0x3d, SC_TILE_PER_SUPERTILE_H4 = 0x3e, SC_TILE_PER_SUPERTILE_H5 = 0x3f, SC_TILE_PER_SUPERTILE_H6 = 0x40, SC_TILE_PER_SUPERTILE_H7 = 0x41, SC_TILE_PER_SUPERTILE_H8 = 0x42, SC_TILE_PER_SUPERTILE_H9 = 0x43, SC_TILE_PER_SUPERTILE_H10 = 0x44, SC_TILE_PER_SUPERTILE_H11 = 0x45, SC_TILE_PER_SUPERTILE_H12 = 0x46, SC_TILE_PER_SUPERTILE_H13 = 0x47, SC_TILE_PER_SUPERTILE_H14 = 0x48, SC_TILE_PER_SUPERTILE_H15 = 0x49, SC_TILE_PER_SUPERTILE_H16 = 0x4a, SC_TILE_PICKED_H1 = 0x4b, SC_TILE_PICKED_H2 = 0x4c, SC_TILE_PICKED_H3 = 0x4d, SC_TILE_PICKED_H4 = 0x4e, SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x4f, SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x50, SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x51, SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x52, SC_QZ0_TILE_COUNT = 0x53, SC_QZ1_TILE_COUNT = 0x54, SC_QZ2_TILE_COUNT = 0x55, SC_QZ3_TILE_COUNT = 0x56, SC_QZ0_TILE_COVERED_COUNT = 0x57, SC_QZ1_TILE_COVERED_COUNT = 0x58, SC_QZ2_TILE_COVERED_COUNT = 0x59, SC_QZ3_TILE_COVERED_COUNT = 0x5a, SC_QZ0_TILE_NOT_COVERED_COUNT = 0x5b, SC_QZ1_TILE_NOT_COVERED_COUNT = 0x5c, SC_QZ2_TILE_NOT_COVERED_COUNT = 0x5d, SC_QZ3_TILE_NOT_COVERED_COUNT = 0x5e, SC_QZ0_QUAD_PER_TILE_H0 = 0x5f, SC_QZ0_QUAD_PER_TILE_H1 = 0x60, SC_QZ0_QUAD_PER_TILE_H2 = 0x61, SC_QZ0_QUAD_PER_TILE_H3 = 0x62, SC_QZ0_QUAD_PER_TILE_H4 = 0x63, SC_QZ0_QUAD_PER_TILE_H5 = 0x64, SC_QZ0_QUAD_PER_TILE_H6 = 0x65, SC_QZ0_QUAD_PER_TILE_H7 = 0x66, SC_QZ0_QUAD_PER_TILE_H8 = 0x67, SC_QZ0_QUAD_PER_TILE_H9 = 0x68, SC_QZ0_QUAD_PER_TILE_H10 = 0x69, SC_QZ0_QUAD_PER_TILE_H11 = 0x6a, SC_QZ0_QUAD_PER_TILE_H12 = 0x6b, SC_QZ0_QUAD_PER_TILE_H13 = 0x6c, SC_QZ0_QUAD_PER_TILE_H14 = 0x6d, SC_QZ0_QUAD_PER_TILE_H15 = 0x6e, SC_QZ0_QUAD_PER_TILE_H16 = 0x6f, SC_QZ1_QUAD_PER_TILE_H0 = 0x70, SC_QZ1_QUAD_PER_TILE_H1 = 0x71, SC_QZ1_QUAD_PER_TILE_H2 = 0x72, SC_QZ1_QUAD_PER_TILE_H3 = 0x73, SC_QZ1_QUAD_PER_TILE_H4 = 0x74, SC_QZ1_QUAD_PER_TILE_H5 = 0x75, SC_QZ1_QUAD_PER_TILE_H6 = 0x76, SC_QZ1_QUAD_PER_TILE_H7 = 0x77, SC_QZ1_QUAD_PER_TILE_H8 = 0x78, SC_QZ1_QUAD_PER_TILE_H9 = 0x79, SC_QZ1_QUAD_PER_TILE_H10 = 0x7a, SC_QZ1_QUAD_PER_TILE_H11 = 0x7b, SC_QZ1_QUAD_PER_TILE_H12 = 0x7c, SC_QZ1_QUAD_PER_TILE_H13 = 0x7d, SC_QZ1_QUAD_PER_TILE_H14 = 0x7e, SC_QZ1_QUAD_PER_TILE_H15 = 0x7f, SC_QZ1_QUAD_PER_TILE_H16 = 0x80, SC_QZ2_QUAD_PER_TILE_H0 = 0x81, SC_QZ2_QUAD_PER_TILE_H1 = 0x82, SC_QZ2_QUAD_PER_TILE_H2 = 0x83, SC_QZ2_QUAD_PER_TILE_H3 = 0x84, SC_QZ2_QUAD_PER_TILE_H4 = 0x85, SC_QZ2_QUAD_PER_TILE_H5 = 0x86, SC_QZ2_QUAD_PER_TILE_H6 = 0x87, SC_QZ2_QUAD_PER_TILE_H7 = 0x88, SC_QZ2_QUAD_PER_TILE_H8 = 0x89, SC_QZ2_QUAD_PER_TILE_H9 = 0x8a, SC_QZ2_QUAD_PER_TILE_H10 = 0x8b, SC_QZ2_QUAD_PER_TILE_H11 = 0x8c, SC_QZ2_QUAD_PER_TILE_H12 = 0x8d, SC_QZ2_QUAD_PER_TILE_H13 = 0x8e, SC_QZ2_QUAD_PER_TILE_H14 = 0x8f, SC_QZ2_QUAD_PER_TILE_H15 = 0x90, SC_QZ2_QUAD_PER_TILE_H16 = 0x91, SC_QZ3_QUAD_PER_TILE_H0 = 0x92, SC_QZ3_QUAD_PER_TILE_H1 = 0x93, SC_QZ3_QUAD_PER_TILE_H2 = 0x94, SC_QZ3_QUAD_PER_TILE_H3 = 0x95, SC_QZ3_QUAD_PER_TILE_H4 = 0x96, SC_QZ3_QUAD_PER_TILE_H5 = 0x97, SC_QZ3_QUAD_PER_TILE_H6 = 0x98, SC_QZ3_QUAD_PER_TILE_H7 = 0x99, SC_QZ3_QUAD_PER_TILE_H8 = 0x9a, SC_QZ3_QUAD_PER_TILE_H9 = 0x9b, SC_QZ3_QUAD_PER_TILE_H10 = 0x9c, SC_QZ3_QUAD_PER_TILE_H11 = 0x9d, SC_QZ3_QUAD_PER_TILE_H12 = 0x9e, SC_QZ3_QUAD_PER_TILE_H13 = 0x9f, SC_QZ3_QUAD_PER_TILE_H14 = 0xa0, SC_QZ3_QUAD_PER_TILE_H15 = 0xa1, SC_QZ3_QUAD_PER_TILE_H16 = 0xa2, SC_QZ0_QUAD_COUNT = 0xa3, SC_QZ1_QUAD_COUNT = 0xa4, SC_QZ2_QUAD_COUNT = 0xa5, SC_QZ3_QUAD_COUNT = 0xa6, SC_P0_HIZ_TILE_COUNT = 0xa7, SC_P1_HIZ_TILE_COUNT = 0xa8, SC_P2_HIZ_TILE_COUNT = 0xa9, SC_P3_HIZ_TILE_COUNT = 0xaa, SC_P0_HIZ_QUAD_PER_TILE_H0 = 0xab, SC_P0_HIZ_QUAD_PER_TILE_H1 = 0xac, SC_P0_HIZ_QUAD_PER_TILE_H2 = 0xad, SC_P0_HIZ_QUAD_PER_TILE_H3 = 0xae, SC_P0_HIZ_QUAD_PER_TILE_H4 = 0xaf, SC_P0_HIZ_QUAD_PER_TILE_H5 = 0xb0, SC_P0_HIZ_QUAD_PER_TILE_H6 = 0xb1, SC_P0_HIZ_QUAD_PER_TILE_H7 = 0xb2, SC_P0_HIZ_QUAD_PER_TILE_H8 = 0xb3, SC_P0_HIZ_QUAD_PER_TILE_H9 = 0xb4, SC_P0_HIZ_QUAD_PER_TILE_H10 = 0xb5, SC_P0_HIZ_QUAD_PER_TILE_H11 = 0xb6, SC_P0_HIZ_QUAD_PER_TILE_H12 = 0xb7, SC_P0_HIZ_QUAD_PER_TILE_H13 = 0xb8, SC_P0_HIZ_QUAD_PER_TILE_H14 = 0xb9, SC_P0_HIZ_QUAD_PER_TILE_H15 = 0xba, SC_P0_HIZ_QUAD_PER_TILE_H16 = 0xbb, SC_P1_HIZ_QUAD_PER_TILE_H0 = 0xbc, SC_P1_HIZ_QUAD_PER_TILE_H1 = 0xbd, SC_P1_HIZ_QUAD_PER_TILE_H2 = 0xbe, SC_P1_HIZ_QUAD_PER_TILE_H3 = 0xbf, SC_P1_HIZ_QUAD_PER_TILE_H4 = 0xc0, SC_P1_HIZ_QUAD_PER_TILE_H5 = 0xc1, SC_P1_HIZ_QUAD_PER_TILE_H6 = 0xc2, SC_P1_HIZ_QUAD_PER_TILE_H7 = 0xc3, SC_P1_HIZ_QUAD_PER_TILE_H8 = 0xc4, SC_P1_HIZ_QUAD_PER_TILE_H9 = 0xc5, SC_P1_HIZ_QUAD_PER_TILE_H10 = 0xc6, SC_P1_HIZ_QUAD_PER_TILE_H11 = 0xc7, SC_P1_HIZ_QUAD_PER_TILE_H12 = 0xc8, SC_P1_HIZ_QUAD_PER_TILE_H13 = 0xc9, SC_P1_HIZ_QUAD_PER_TILE_H14 = 0xca, SC_P1_HIZ_QUAD_PER_TILE_H15 = 0xcb, SC_P1_HIZ_QUAD_PER_TILE_H16 = 0xcc, SC_P2_HIZ_QUAD_PER_TILE_H0 = 0xcd, SC_P2_HIZ_QUAD_PER_TILE_H1 = 0xce, SC_P2_HIZ_QUAD_PER_TILE_H2 = 0xcf, SC_P2_HIZ_QUAD_PER_TILE_H3 = 0xd0, SC_P2_HIZ_QUAD_PER_TILE_H4 = 0xd1, SC_P2_HIZ_QUAD_PER_TILE_H5 = 0xd2, SC_P2_HIZ_QUAD_PER_TILE_H6 = 0xd3, SC_P2_HIZ_QUAD_PER_TILE_H7 = 0xd4, SC_P2_HIZ_QUAD_PER_TILE_H8 = 0xd5, SC_P2_HIZ_QUAD_PER_TILE_H9 = 0xd6, SC_P2_HIZ_QUAD_PER_TILE_H10 = 0xd7, SC_P2_HIZ_QUAD_PER_TILE_H11 = 0xd8, SC_P2_HIZ_QUAD_PER_TILE_H12 = 0xd9, SC_P2_HIZ_QUAD_PER_TILE_H13 = 0xda, SC_P2_HIZ_QUAD_PER_TILE_H14 = 0xdb, SC_P2_HIZ_QUAD_PER_TILE_H15 = 0xdc, SC_P2_HIZ_QUAD_PER_TILE_H16 = 0xdd, SC_P3_HIZ_QUAD_PER_TILE_H0 = 0xde, SC_P3_HIZ_QUAD_PER_TILE_H1 = 0xdf, SC_P3_HIZ_QUAD_PER_TILE_H2 = 0xe0, SC_P3_HIZ_QUAD_PER_TILE_H3 = 0xe1, SC_P3_HIZ_QUAD_PER_TILE_H4 = 0xe2, SC_P3_HIZ_QUAD_PER_TILE_H5 = 0xe3, SC_P3_HIZ_QUAD_PER_TILE_H6 = 0xe4, SC_P3_HIZ_QUAD_PER_TILE_H7 = 0xe5, SC_P3_HIZ_QUAD_PER_TILE_H8 = 0xe6, SC_P3_HIZ_QUAD_PER_TILE_H9 = 0xe7, SC_P3_HIZ_QUAD_PER_TILE_H10 = 0xe8, SC_P3_HIZ_QUAD_PER_TILE_H11 = 0xe9, SC_P3_HIZ_QUAD_PER_TILE_H12 = 0xea, SC_P3_HIZ_QUAD_PER_TILE_H13 = 0xeb, SC_P3_HIZ_QUAD_PER_TILE_H14 = 0xec, SC_P3_HIZ_QUAD_PER_TILE_H15 = 0xed, SC_P3_HIZ_QUAD_PER_TILE_H16 = 0xee, SC_P0_HIZ_QUAD_COUNT = 0xef, SC_P1_HIZ_QUAD_COUNT = 0xf0, SC_P2_HIZ_QUAD_COUNT = 0xf1, SC_P3_HIZ_QUAD_COUNT = 0xf2, SC_P0_DETAIL_QUAD_COUNT = 0xf3, SC_P1_DETAIL_QUAD_COUNT = 0xf4, SC_P2_DETAIL_QUAD_COUNT = 0xf5, SC_P3_DETAIL_QUAD_COUNT = 0xf6, SC_P0_DETAIL_QUAD_WITH_1_PIX = 0xf7, SC_P0_DETAIL_QUAD_WITH_2_PIX = 0xf8, SC_P0_DETAIL_QUAD_WITH_3_PIX = 0xf9, SC_P0_DETAIL_QUAD_WITH_4_PIX = 0xfa, SC_P1_DETAIL_QUAD_WITH_1_PIX = 0xfb, SC_P1_DETAIL_QUAD_WITH_2_PIX = 0xfc, SC_P1_DETAIL_QUAD_WITH_3_PIX = 0xfd, SC_P1_DETAIL_QUAD_WITH_4_PIX = 0xfe, SC_P2_DETAIL_QUAD_WITH_1_PIX = 0xff, SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x100, SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x101, SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x102, SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x103, SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x104, SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x105, SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x106, SC_EARLYZ_QUAD_COUNT = 0x107, SC_EARLYZ_QUAD_WITH_1_PIX = 0x108, SC_EARLYZ_QUAD_WITH_2_PIX = 0x109, SC_EARLYZ_QUAD_WITH_3_PIX = 0x10a, SC_EARLYZ_QUAD_WITH_4_PIX = 0x10b, SC_PKR_QUAD_PER_ROW_H1 = 0x10c, SC_PKR_QUAD_PER_ROW_H2 = 0x10d, SC_PKR_QUAD_PER_ROW_H3 = 0x10e, SC_PKR_QUAD_PER_ROW_H4 = 0x10f, SC_PKR_END_OF_VECTOR = 0x110, SC_PKR_CONTROL_XFER = 0x111, SC_PKR_DBHANG_FORCE_EOV = 0x112, SC_REG_SCLK_BUSY = 0x113, SC_GRP0_DYN_SCLK_BUSY = 0x114, SC_GRP1_DYN_SCLK_BUSY = 0x115, SC_GRP2_DYN_SCLK_BUSY = 0x116, SC_GRP3_DYN_SCLK_BUSY = 0x117, SC_GRP4_DYN_SCLK_BUSY = 0x118, SC_PA0_SC_DATA_FIFO_RD = 0x119, SC_PA0_SC_DATA_FIFO_WE = 0x11a, SC_PA1_SC_DATA_FIFO_RD = 0x11b, SC_PA1_SC_DATA_FIFO_WE = 0x11c, SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x11d, SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x11e, SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x11f, SC_PS_ARB_STALLED_FROM_BELOW = 0x120, SC_PS_ARB_STARVED_FROM_ABOVE = 0x121, SC_PS_ARB_SC_BUSY = 0x122, SC_PS_ARB_PA_SC_BUSY = 0x123, SC_PA2_SC_DATA_FIFO_RD = 0x124, SC_PA2_SC_DATA_FIFO_WE = 0x125, SC_PA3_SC_DATA_FIFO_RD = 0x126, SC_PA3_SC_DATA_FIFO_WE = 0x127, SC_PA_SC_DEALLOC_0_0_WE = 0x128, SC_PA_SC_DEALLOC_0_1_WE = 0x129, SC_PA_SC_DEALLOC_1_0_WE = 0x12a, SC_PA_SC_DEALLOC_1_1_WE = 0x12b, SC_PA_SC_DEALLOC_2_0_WE = 0x12c, SC_PA_SC_DEALLOC_2_1_WE = 0x12d, SC_PA_SC_DEALLOC_3_0_WE = 0x12e, SC_PA_SC_DEALLOC_3_1_WE = 0x12f, SC_PA0_SC_EOP_WE = 0x130, SC_PA0_SC_EOPG_WE = 0x131, SC_PA0_SC_EVENT_WE = 0x132, SC_PA1_SC_EOP_WE = 0x133, SC_PA1_SC_EOPG_WE = 0x134, SC_PA1_SC_EVENT_WE = 0x135, SC_PA2_SC_EOP_WE = 0x136, SC_PA2_SC_EOPG_WE = 0x137, SC_PA2_SC_EVENT_WE = 0x138, SC_PA3_SC_EOP_WE = 0x139, SC_PA3_SC_EOPG_WE = 0x13a, SC_PA3_SC_EVENT_WE = 0x13b, SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x13c, SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x13d, SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x13e, SC_PS_ARB_EOP_POP_SYNC_POP = 0x13f, SC_PS_ARB_EVENT_SYNC_POP = 0x140, SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x141, SC_PA0_SC_FPOV_WE = 0x142, SC_PA1_SC_FPOV_WE = 0x143, SC_PA2_SC_FPOV_WE = 0x144, SC_PA3_SC_FPOV_WE = 0x145, SC_PA0_SC_LPOV_WE = 0x146, SC_PA1_SC_LPOV_WE = 0x147, SC_PA2_SC_LPOV_WE = 0x148, SC_PA3_SC_LPOV_WE = 0x149, SC_SC_SPI_DEALLOC_0_0 = 0x14a, SC_SC_SPI_DEALLOC_0_1 = 0x14b, SC_SC_SPI_DEALLOC_0_2 = 0x14c, SC_SC_SPI_DEALLOC_1_0 = 0x14d, SC_SC_SPI_DEALLOC_1_1 = 0x14e, SC_SC_SPI_DEALLOC_1_2 = 0x14f, SC_SC_SPI_DEALLOC_2_0 = 0x150, SC_SC_SPI_DEALLOC_2_1 = 0x151, SC_SC_SPI_DEALLOC_2_2 = 0x152, SC_SC_SPI_DEALLOC_3_0 = 0x153, SC_SC_SPI_DEALLOC_3_1 = 0x154, SC_SC_SPI_DEALLOC_3_2 = 0x155, SC_SC_SPI_FPOV_0 = 0x156, SC_SC_SPI_FPOV_1 = 0x157, SC_SC_SPI_FPOV_2 = 0x158, SC_SC_SPI_FPOV_3 = 0x159, SC_SC_SPI_EVENT = 0x15a, SC_PS_TS_EVENT_FIFO_PUSH = 0x15b, SC_PS_TS_EVENT_FIFO_POP = 0x15c, SC_PS_CTX_DONE_FIFO_PUSH = 0x15d, SC_PS_CTX_DONE_FIFO_POP = 0x15e, SC_MULTICYCLE_BUBBLE_FREEZE = 0x15f, SC_EOP_SYNC_WINDOW = 0x160, SC_PA0_SC_NULL_WE = 0x161, SC_PA0_SC_NULL_DEALLOC_WE = 0x162, SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x163, SC_PA0_SC_DATA_FIFO_EOP_RD = 0x164, SC_PA0_SC_DEALLOC_0_RD = 0x165, SC_PA0_SC_DEALLOC_1_RD = 0x166, SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x167, SC_PA1_SC_DATA_FIFO_EOP_RD = 0x168, SC_PA1_SC_DEALLOC_0_RD = 0x169, SC_PA1_SC_DEALLOC_1_RD = 0x16a, SC_PA1_SC_NULL_WE = 0x16b, SC_PA1_SC_NULL_DEALLOC_WE = 0x16c, SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x16d, SC_PA2_SC_DATA_FIFO_EOP_RD = 0x16e, SC_PA2_SC_DEALLOC_0_RD = 0x16f, SC_PA2_SC_DEALLOC_1_RD = 0x170, SC_PA2_SC_NULL_WE = 0x171, SC_PA2_SC_NULL_DEALLOC_WE = 0x172, SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x173, SC_PA3_SC_DATA_FIFO_EOP_RD = 0x174, SC_PA3_SC_DEALLOC_0_RD = 0x175, SC_PA3_SC_DEALLOC_1_RD = 0x176, SC_PA3_SC_NULL_WE = 0x177, SC_PA3_SC_NULL_DEALLOC_WE = 0x178, SC_PS_PA0_SC_FIFO_EMPTY = 0x179, SC_PS_PA0_SC_FIFO_FULL = 0x17a, SC_PA0_PS_DATA_SEND = 0x17b, SC_PS_PA1_SC_FIFO_EMPTY = 0x17c, SC_PS_PA1_SC_FIFO_FULL = 0x17d, SC_PA1_PS_DATA_SEND = 0x17e, SC_PS_PA2_SC_FIFO_EMPTY = 0x17f, SC_PS_PA2_SC_FIFO_FULL = 0x180, SC_PA2_PS_DATA_SEND = 0x181, SC_PS_PA3_SC_FIFO_EMPTY = 0x182, SC_PS_PA3_SC_FIFO_FULL = 0x183, SC_PA3_PS_DATA_SEND = 0x184, SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x185, SC_BUSY_CNT_NOT_ZERO = 0x186, SC_BM_BUSY = 0x187, SC_BACKEND_BUSY = 0x188, SC_SCF_SCB_INTERFACE_BUSY = 0x189, SC_SCB_BUSY = 0x18a, } SC_PERFCNT_SEL; typedef enum SePairXsel { RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x0, RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x1, RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x2, RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x3, } SePairXsel; typedef enum SePairYsel { RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x0, RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x1, RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x2, RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x3, } SePairYsel; typedef enum SePairMap { RASTER_CONFIG_SE_PAIR_MAP_0 = 0x0, RASTER_CONFIG_SE_PAIR_MAP_1 = 0x1, RASTER_CONFIG_SE_PAIR_MAP_2 = 0x2, RASTER_CONFIG_SE_PAIR_MAP_3 = 0x3, } SePairMap; typedef enum SeXsel { RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x0, RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x1, RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x2, RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x3, } SeXsel; typedef enum SeYsel { RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x0, RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x1, RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x2, RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x3, } SeYsel; typedef enum SeMap { RASTER_CONFIG_SE_MAP_0 = 0x0, RASTER_CONFIG_SE_MAP_1 = 0x1, RASTER_CONFIG_SE_MAP_2 = 0x2, RASTER_CONFIG_SE_MAP_3 = 0x3, } SeMap; typedef enum ScXsel { RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x0, RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x1, RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x2, RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x3, } ScXsel; typedef enum ScYsel { RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x0, RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x1, RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x2, RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x3, } ScYsel; typedef enum ScMap { RASTER_CONFIG_SC_MAP_0 = 0x0, RASTER_CONFIG_SC_MAP_1 = 0x1, RASTER_CONFIG_SC_MAP_2 = 0x2, RASTER_CONFIG_SC_MAP_3 = 0x3, } ScMap; typedef enum PkrXsel2 { RASTER_CONFIG_PKR_XSEL2_0 = 0x0, RASTER_CONFIG_PKR_XSEL2_1 = 0x1, RASTER_CONFIG_PKR_XSEL2_2 = 0x2, RASTER_CONFIG_PKR_XSEL2_3 = 0x3, } PkrXsel2; typedef enum PkrXsel { RASTER_CONFIG_PKR_XSEL_0 = 0x0, RASTER_CONFIG_PKR_XSEL_1 = 0x1, RASTER_CONFIG_PKR_XSEL_2 = 0x2, RASTER_CONFIG_PKR_XSEL_3 = 0x3, } PkrXsel; typedef enum PkrYsel { RASTER_CONFIG_PKR_YSEL_0 = 0x0, RASTER_CONFIG_PKR_YSEL_1 = 0x1, RASTER_CONFIG_PKR_YSEL_2 = 0x2, RASTER_CONFIG_PKR_YSEL_3 = 0x3, } PkrYsel; typedef enum PkrMap { RASTER_CONFIG_PKR_MAP_0 = 0x0, RASTER_CONFIG_PKR_MAP_1 = 0x1, RASTER_CONFIG_PKR_MAP_2 = 0x2, RASTER_CONFIG_PKR_MAP_3 = 0x3, } PkrMap; typedef enum RbXsel { RASTER_CONFIG_RB_XSEL_0 = 0x0, RASTER_CONFIG_RB_XSEL_1 = 0x1, } RbXsel; typedef enum RbYsel { RASTER_CONFIG_RB_YSEL_0 = 0x0, RASTER_CONFIG_RB_YSEL_1 = 0x1, } RbYsel; typedef enum RbXsel2 { RASTER_CONFIG_RB_XSEL2_0 = 0x0, RASTER_CONFIG_RB_XSEL2_1 = 0x1, RASTER_CONFIG_RB_XSEL2_2 = 0x2, RASTER_CONFIG_RB_XSEL2_3 = 0x3, } RbXsel2; typedef enum RbMap { RASTER_CONFIG_RB_MAP_0 = 0x0, RASTER_CONFIG_RB_MAP_1 = 0x1, RASTER_CONFIG_RB_MAP_2 = 0x2, RASTER_CONFIG_RB_MAP_3 = 0x3, } RbMap; typedef enum CSDATA_TYPE { CSDATA_TYPE_TG = 0x0, CSDATA_TYPE_STATE = 0x1, CSDATA_TYPE_EVENT = 0x2, CSDATA_TYPE_PRIVATE = 0x3, } CSDATA_TYPE; #define CSDATA_TYPE_WIDTH 0x2 #define CSDATA_ADDR_WIDTH 0x7 #define CSDATA_DATA_WIDTH 0x20 typedef enum SPI_SAMPLE_CNTL { CENTROIDS_ONLY = 0x0, CENTERS_ONLY = 0x1, CENTROIDS_AND_CENTERS = 0x2, UNDEF = 0x3, } SPI_SAMPLE_CNTL; typedef enum SPI_FOG_MODE { SPI_FOG_NONE = 0x0, SPI_FOG_EXP = 0x1, SPI_FOG_EXP2 = 0x2, SPI_FOG_LINEAR = 0x3, } SPI_FOG_MODE; typedef enum SPI_PNT_SPRITE_OVERRIDE { SPI_PNT_SPRITE_SEL_0 = 0x0, SPI_PNT_SPRITE_SEL_1 = 0x1, SPI_PNT_SPRITE_SEL_S = 0x2, SPI_PNT_SPRITE_SEL_T = 0x3, SPI_PNT_SPRITE_SEL_NONE = 0x4, } SPI_PNT_SPRITE_OVERRIDE; typedef enum SPI_PERFCNT_SEL { SPI_PERF_VS_WINDOW_VALID = 0x0, SPI_PERF_VS_BUSY = 0x1, SPI_PERF_VS_FIRST_WAVE = 0x2, SPI_PERF_VS_LAST_WAVE = 0x3, SPI_PERF_VS_LSHS_DEALLOC = 0x4, SPI_PERF_VS_PC_STALL = 0x5, SPI_PERF_VS_POS0_STALL = 0x6, SPI_PERF_VS_POS1_STALL = 0x7, SPI_PERF_VS_CRAWLER_STALL = 0x8, SPI_PERF_VS_EVENT_WAVE = 0x9, SPI_PERF_VS_WAVE = 0xa, SPI_PERF_VS_PERS_UPD_FULL0 = 0xb, SPI_PERF_VS_PERS_UPD_FULL1 = 0xc, SPI_PERF_VS_LATE_ALLOC_FULL = 0xd, SPI_PERF_VS_FIRST_SUBGRP = 0xe, SPI_PERF_VS_LAST_SUBGRP = 0xf, SPI_PERF_GS_WINDOW_VALID = 0x10, SPI_PERF_GS_BUSY = 0x11, SPI_PERF_GS_CRAWLER_STALL = 0x12, SPI_PERF_GS_EVENT_WAVE = 0x13, SPI_PERF_GS_WAVE = 0x14, SPI_PERF_GS_PERS_UPD_FULL0 = 0x15, SPI_PERF_GS_PERS_UPD_FULL1 = 0x16, SPI_PERF_GS_FIRST_SUBGRP = 0x17, SPI_PERF_GS_LAST_SUBGRP = 0x18, SPI_PERF_ES_WINDOW_VALID = 0x19, SPI_PERF_ES_BUSY = 0x1a, SPI_PERF_ES_CRAWLER_STALL = 0x1b, SPI_PERF_ES_FIRST_WAVE = 0x1c, SPI_PERF_ES_LAST_WAVE = 0x1d, SPI_PERF_ES_LSHS_DEALLOC = 0x1e, SPI_PERF_ES_EVENT_WAVE = 0x1f, SPI_PERF_ES_WAVE = 0x20, SPI_PERF_ES_PERS_UPD_FULL0 = 0x21, SPI_PERF_ES_PERS_UPD_FULL1 = 0x22, SPI_PERF_ES_FIRST_SUBGRP = 0x23, SPI_PERF_ES_LAST_SUBGRP = 0x24, SPI_PERF_HS_WINDOW_VALID = 0x25, SPI_PERF_HS_BUSY = 0x26, SPI_PERF_HS_CRAWLER_STALL = 0x27, SPI_PERF_HS_FIRST_WAVE = 0x28, SPI_PERF_HS_LAST_WAVE = 0x29, SPI_PERF_HS_LSHS_DEALLOC = 0x2a, SPI_PERF_HS_EVENT_WAVE = 0x2b, SPI_PERF_HS_WAVE = 0x2c, SPI_PERF_HS_PERS_UPD_FULL0 = 0x2d, SPI_PERF_HS_PERS_UPD_FULL1 = 0x2e, SPI_PERF_LS_WINDOW_VALID = 0x2f, SPI_PERF_LS_BUSY = 0x30, SPI_PERF_LS_CRAWLER_STALL = 0x31, SPI_PERF_LS_FIRST_WAVE = 0x32, SPI_PERF_LS_LAST_WAVE = 0x33, SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x34, SPI_PERF_LS_EVENT_WAVE = 0x35, SPI_PERF_LS_WAVE = 0x36, SPI_PERF_LS_PERS_UPD_FULL0 = 0x37, SPI_PERF_LS_PERS_UPD_FULL1 = 0x38, SPI_PERF_CSG_WINDOW_VALID = 0x39, SPI_PERF_CSG_BUSY = 0x3a, SPI_PERF_CSG_NUM_THREADGROUPS = 0x3b, SPI_PERF_CSG_CRAWLER_STALL = 0x3c, SPI_PERF_CSG_EVENT_WAVE = 0x3d, SPI_PERF_CSG_WAVE = 0x3e, SPI_PERF_CSN_WINDOW_VALID = 0x3f, SPI_PERF_CSN_BUSY = 0x40, SPI_PERF_CSN_NUM_THREADGROUPS = 0x41, SPI_PERF_CSN_CRAWLER_STALL = 0x42, SPI_PERF_CSN_EVENT_WAVE = 0x43, SPI_PERF_CSN_WAVE = 0x44, SPI_PERF_PS_CTL_WINDOW_VALID = 0x45, SPI_PERF_PS_CTL_BUSY = 0x46, SPI_PERF_PS_CTL_ACTIVE = 0x47, SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x48, SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x49, SPI_PERF_PS_CTL_EVENT_WAVE = 0x4a, SPI_PERF_PS_CTL_WAVE = 0x4b, SPI_PERF_PS_CTL_OPT_WAVE = 0x4c, SPI_PERF_PS_CTL_PASS_BIN0 = 0x4d, SPI_PERF_PS_CTL_PASS_BIN1 = 0x4e, SPI_PERF_PS_CTL_FPOS_BIN2 = 0x4f, SPI_PERF_PS_CTL_PRIM_BIN0 = 0x50, SPI_PERF_PS_CTL_PRIM_BIN1 = 0x51, SPI_PERF_PS_CTL_CNF_BIN2 = 0x52, SPI_PERF_PS_CTL_CNF_BIN3 = 0x53, SPI_PERF_PS_CTL_CRAWLER_STALL = 0x54, SPI_PERF_PS_CTL_LDS_RES_FULL = 0x55, SPI_PERF_PS_PERS_UPD_FULL0 = 0x56, SPI_PERF_PS_PERS_UPD_FULL1 = 0x57, SPI_PERF_PIX_ALLOC_PEND_CNT = 0x58, SPI_PERF_PIX_ALLOC_SCB_STALL = 0x59, SPI_PERF_PIX_ALLOC_DB0_STALL = 0x5a, SPI_PERF_PIX_ALLOC_DB1_STALL = 0x5b, SPI_PERF_PIX_ALLOC_DB2_STALL = 0x5c, SPI_PERF_PIX_ALLOC_DB3_STALL = 0x5d, SPI_PERF_LDS0_PC_VALID = 0x5e, SPI_PERF_LDS1_PC_VALID = 0x5f, SPI_PERF_RA_PIPE_REQ_BIN2 = 0x60, SPI_PERF_RA_TASK_REQ_BIN3 = 0x61, SPI_PERF_RA_WR_CTL_FULL = 0x62, SPI_PERF_RA_REQ_NO_ALLOC = 0x63, SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x64, SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x65, SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x66, SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x67, SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x68, SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x69, SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x6a, SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x6b, SPI_PERF_RA_RES_STALL_PS = 0x6c, SPI_PERF_RA_RES_STALL_VS = 0x6d, SPI_PERF_RA_RES_STALL_GS = 0x6e, SPI_PERF_RA_RES_STALL_ES = 0x6f, SPI_PERF_RA_RES_STALL_HS = 0x70, SPI_PERF_RA_RES_STALL_LS = 0x71, SPI_PERF_RA_RES_STALL_CSG = 0x72, SPI_PERF_RA_RES_STALL_CSN = 0x73, SPI_PERF_RA_TMP_STALL_PS = 0x74, SPI_PERF_RA_TMP_STALL_VS = 0x75, SPI_PERF_RA_TMP_STALL_GS = 0x76, SPI_PERF_RA_TMP_STALL_ES = 0x77, SPI_PERF_RA_TMP_STALL_HS = 0x78, SPI_PERF_RA_TMP_STALL_LS = 0x79, SPI_PERF_RA_TMP_STALL_CSG = 0x7a, SPI_PERF_RA_TMP_STALL_CSN = 0x7b, SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x7c, SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x7d, SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x7e, SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x7f, SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x80, SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x81, SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x82, SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x83, SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x84, SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x85, SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x86, SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x87, SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x88, SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x89, SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x8a, SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x8b, SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x8c, SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x8d, SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x8e, SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x8f, SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x90, SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x91, SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x92, SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x93, SPI_PERF_RA_LDS_CU_FULL_PS = 0x94, SPI_PERF_RA_LDS_CU_FULL_LS = 0x95, SPI_PERF_RA_LDS_CU_FULL_ES = 0x96, SPI_PERF_RA_LDS_CU_FULL_CSG = 0x97, SPI_PERF_RA_LDS_CU_FULL_CSN = 0x98, SPI_PERF_RA_BAR_CU_FULL_HS = 0x99, SPI_PERF_RA_BAR_CU_FULL_CSG = 0x9a, SPI_PERF_RA_BAR_CU_FULL_CSN = 0x9b, SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x9c, SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x9d, SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x9e, SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x9f, SPI_PERF_RA_WVLIM_STALL_PS = 0xa0, SPI_PERF_RA_WVLIM_STALL_VS = 0xa1, SPI_PERF_RA_WVLIM_STALL_GS = 0xa2, SPI_PERF_RA_WVLIM_STALL_ES = 0xa3, SPI_PERF_RA_WVLIM_STALL_HS = 0xa4, SPI_PERF_RA_WVLIM_STALL_LS = 0xa5, SPI_PERF_RA_WVLIM_STALL_CSG = 0xa6, SPI_PERF_RA_WVLIM_STALL_CSN = 0xa7, SPI_PERF_RA_PS_LOCK = 0xa8, SPI_PERF_RA_VS_LOCK = 0xa9, SPI_PERF_RA_GS_LOCK = 0xaa, SPI_PERF_RA_ES_LOCK = 0xab, SPI_PERF_RA_HS_LOCK = 0xac, SPI_PERF_RA_LS_LOCK = 0xad, SPI_PERF_RA_CSG_LOCK = 0xae, SPI_PERF_RA_CSN_LOCK = 0xaf, SPI_PERF_RA_RSV_UPD = 0xb0, SPI_PERF_EXP_ARB_COL_CNT = 0xb1, SPI_PERF_EXP_ARB_PAR_CNT = 0xb2, SPI_PERF_EXP_ARB_POS_CNT = 0xb3, SPI_PERF_EXP_ARB_GDS_CNT = 0xb4, SPI_PERF_CLKGATE_BUSY_STALL = 0xb5, SPI_PERF_CLKGATE_ACTIVE_STALL = 0xb6, SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0xb7, SPI_PERF_CLKGATE_CGTT_DYN_ON = 0xb8, SPI_PERF_CLKGATE_CGTT_REG_ON = 0xb9, } SPI_PERFCNT_SEL; typedef enum SPI_SHADER_FORMAT { SPI_SHADER_NONE = 0x0, SPI_SHADER_1COMP = 0x1, SPI_SHADER_2COMP = 0x2, SPI_SHADER_4COMPRESS = 0x3, SPI_SHADER_4COMP = 0x4, } SPI_SHADER_FORMAT; typedef enum SPI_SHADER_EX_FORMAT { SPI_SHADER_ZERO = 0x0, SPI_SHADER_32_R = 0x1, SPI_SHADER_32_GR = 0x2, SPI_SHADER_32_AR = 0x3, SPI_SHADER_FP16_ABGR = 0x4, SPI_SHADER_UNORM16_ABGR = 0x5, SPI_SHADER_SNORM16_ABGR = 0x6, SPI_SHADER_UINT16_ABGR = 0x7, SPI_SHADER_SINT16_ABGR = 0x8, SPI_SHADER_32_ABGR = 0x9, } SPI_SHADER_EX_FORMAT; typedef enum CLKGATE_SM_MODE { ON_SEQ = 0x0, OFF_SEQ = 0x1, PROG_SEQ = 0x2, READ_SEQ = 0x3, SM_MODE_RESERVED = 0x4, } CLKGATE_SM_MODE; typedef enum CLKGATE_BASE_MODE { MULT_8 = 0x0, MULT_16 = 0x1, } CLKGATE_BASE_MODE; typedef enum SQ_TEX_CLAMP { SQ_TEX_WRAP = 0x0, SQ_TEX_MIRROR = 0x1, SQ_TEX_CLAMP_LAST_TEXEL = 0x2, SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x3, SQ_TEX_CLAMP_HALF_BORDER = 0x4, SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x5, SQ_TEX_CLAMP_BORDER = 0x6, SQ_TEX_MIRROR_ONCE_BORDER = 0x7, } SQ_TEX_CLAMP; typedef enum SQ_TEX_XY_FILTER { SQ_TEX_XY_FILTER_POINT = 0x0, SQ_TEX_XY_FILTER_BILINEAR = 0x1, SQ_TEX_XY_FILTER_ANISO_POINT = 0x2, SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x3, } SQ_TEX_XY_FILTER; typedef enum SQ_TEX_Z_FILTER { SQ_TEX_Z_FILTER_NONE = 0x0, SQ_TEX_Z_FILTER_POINT = 0x1, SQ_TEX_Z_FILTER_LINEAR = 0x2, } SQ_TEX_Z_FILTER; typedef enum SQ_TEX_MIP_FILTER { SQ_TEX_MIP_FILTER_NONE = 0x0, SQ_TEX_MIP_FILTER_POINT = 0x1, SQ_TEX_MIP_FILTER_LINEAR = 0x2, } SQ_TEX_MIP_FILTER; typedef enum SQ_TEX_ANISO_RATIO { SQ_TEX_ANISO_RATIO_1 = 0x0, SQ_TEX_ANISO_RATIO_2 = 0x1, SQ_TEX_ANISO_RATIO_4 = 0x2, SQ_TEX_ANISO_RATIO_8 = 0x3, SQ_TEX_ANISO_RATIO_16 = 0x4, } SQ_TEX_ANISO_RATIO; typedef enum SQ_TEX_DEPTH_COMPARE { SQ_TEX_DEPTH_COMPARE_NEVER = 0x0, SQ_TEX_DEPTH_COMPARE_LESS = 0x1, SQ_TEX_DEPTH_COMPARE_EQUAL = 0x2, SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x3, SQ_TEX_DEPTH_COMPARE_GREATER = 0x4, SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x5, SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x6, SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x7, } SQ_TEX_DEPTH_COMPARE; typedef enum SQ_TEX_BORDER_COLOR { SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x0, SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x1, SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x2, SQ_TEX_BORDER_COLOR_REGISTER = 0x3, } SQ_TEX_BORDER_COLOR; typedef enum SQ_RSRC_BUF_TYPE { SQ_RSRC_BUF = 0x0, SQ_RSRC_BUF_RSVD_1 = 0x1, SQ_RSRC_BUF_RSVD_2 = 0x2, SQ_RSRC_BUF_RSVD_3 = 0x3, } SQ_RSRC_BUF_TYPE; typedef enum SQ_RSRC_IMG_TYPE { SQ_RSRC_IMG_RSVD_0 = 0x0, SQ_RSRC_IMG_RSVD_1 = 0x1, SQ_RSRC_IMG_RSVD_2 = 0x2, SQ_RSRC_IMG_RSVD_3 = 0x3, SQ_RSRC_IMG_RSVD_4 = 0x4, SQ_RSRC_IMG_RSVD_5 = 0x5, SQ_RSRC_IMG_RSVD_6 = 0x6, SQ_RSRC_IMG_RSVD_7 = 0x7, SQ_RSRC_IMG_1D = 0x8, SQ_RSRC_IMG_2D = 0x9, SQ_RSRC_IMG_3D = 0xa, SQ_RSRC_IMG_CUBE = 0xb, SQ_RSRC_IMG_1D_ARRAY = 0xc, SQ_RSRC_IMG_2D_ARRAY = 0xd, SQ_RSRC_IMG_2D_MSAA = 0xe, SQ_RSRC_IMG_2D_MSAA_ARRAY = 0xf, } SQ_RSRC_IMG_TYPE; typedef enum SQ_RSRC_FLAT_TYPE { SQ_RSRC_FLAT_RSVD_0 = 0x0, SQ_RSRC_FLAT = 0x1, SQ_RSRC_FLAT_RSVD_2 = 0x2, SQ_RSRC_FLAT_RSVD_3 = 0x3, } SQ_RSRC_FLAT_TYPE; typedef enum SQ_IMG_FILTER_TYPE { SQ_IMG_FILTER_MODE_BLEND = 0x0, SQ_IMG_FILTER_MODE_MIN = 0x1, SQ_IMG_FILTER_MODE_MAX = 0x2, } SQ_IMG_FILTER_TYPE; typedef enum SQ_SEL_XYZW01 { SQ_SEL_0 = 0x0, SQ_SEL_1 = 0x1, SQ_SEL_RESERVED_0 = 0x2, SQ_SEL_RESERVED_1 = 0x3, SQ_SEL_X = 0x4, SQ_SEL_Y = 0x5, SQ_SEL_Z = 0x6, SQ_SEL_W = 0x7, } SQ_SEL_XYZW01; typedef enum SQ_WAVE_TYPE { SQ_WAVE_TYPE_PS = 0x0, SQ_WAVE_TYPE_VS = 0x1, SQ_WAVE_TYPE_GS = 0x2, SQ_WAVE_TYPE_ES = 0x3, SQ_WAVE_TYPE_HS = 0x4, SQ_WAVE_TYPE_LS = 0x5, SQ_WAVE_TYPE_CS = 0x6, SQ_WAVE_TYPE_PS1 = 0x7, } SQ_WAVE_TYPE; typedef enum SQ_THREAD_TRACE_TOKEN_TYPE { SQ_THREAD_TRACE_TOKEN_MISC = 0x0, SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x1, SQ_THREAD_TRACE_TOKEN_REG = 0x2, SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x3, SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x4, SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x5, SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x6, SQ_THREAD_TRACE_TOKEN_EVENT = 0x7, SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x8, SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x9, SQ_THREAD_TRACE_TOKEN_INST = 0xa, SQ_THREAD_TRACE_TOKEN_INST_PC = 0xb, SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0xc, SQ_THREAD_TRACE_TOKEN_ISSUE = 0xd, SQ_THREAD_TRACE_TOKEN_PERF = 0xe, SQ_THREAD_TRACE_TOKEN_REG_CS = 0xf, } SQ_THREAD_TRACE_TOKEN_TYPE; typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE { SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x0, SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x1, SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x2, SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x3, SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x4, SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x5, } SQ_THREAD_TRACE_MISC_TOKEN_TYPE; typedef enum SQ_THREAD_TRACE_INST_TYPE { SQ_THREAD_TRACE_INST_TYPE_SMEM = 0x0, SQ_THREAD_TRACE_INST_TYPE_SALU = 0x1, SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x2, SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x3, SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x4, SQ_THREAD_TRACE_INST_TYPE_VALU = 0x5, SQ_THREAD_TRACE_INST_TYPE_LDS = 0x6, SQ_THREAD_TRACE_INST_TYPE_PC = 0x7, SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x8, SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x9, SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0xa, SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0xb, SQ_THREAD_TRACE_INST_TYPE_JUMP = 0xc, SQ_THREAD_TRACE_INST_TYPE_NEXT = 0xd, SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0xe, SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0xf, } SQ_THREAD_TRACE_INST_TYPE; typedef enum SQ_THREAD_TRACE_REG_TYPE { SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x0, SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x1, SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x2, SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x3, SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x4, SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x5, SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x6, SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x7, } SQ_THREAD_TRACE_REG_TYPE; typedef enum SQ_THREAD_TRACE_REG_OP { SQ_THREAD_TRACE_REG_OP_READ = 0x0, SQ_THREAD_TRACE_REG_OP_WRITE = 0x1, } SQ_THREAD_TRACE_REG_OP; typedef enum SQ_THREAD_TRACE_MODE_SEL { SQ_THREAD_TRACE_MODE_OFF = 0x0, SQ_THREAD_TRACE_MODE_ON = 0x1, SQ_THREAD_TRACE_MODE_RANDOM = 0x2, } SQ_THREAD_TRACE_MODE_SEL; typedef enum SQ_THREAD_TRACE_CAPTURE_MODE { SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x0, SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x1, SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x2, } SQ_THREAD_TRACE_CAPTURE_MODE; typedef enum SQ_THREAD_TRACE_VM_ID_MASK { SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x0, SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x1, SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x2, } SQ_THREAD_TRACE_VM_ID_MASK; typedef enum SQ_THREAD_TRACE_WAVE_MASK { SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x0, SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x1, SQ_THREAD_TRACE_WAVE_MASK_1_2 = 0x2, SQ_THREAD_TRACE_WAVE_MASK_1_4 = 0x3, SQ_THREAD_TRACE_WAVE_MASK_1_8 = 0x4, SQ_THREAD_TRACE_WAVE_MASK_1_16 = 0x5, SQ_THREAD_TRACE_WAVE_MASK_1_32 = 0x6, SQ_THREAD_TRACE_WAVE_MASK_1_64 = 0x7, } SQ_THREAD_TRACE_WAVE_MASK; typedef enum SQ_THREAD_TRACE_ISSUE { SQ_THREAD_TRACE_ISSUE_NULL = 0x0, SQ_THREAD_TRACE_ISSUE_STALL = 0x1, SQ_THREAD_TRACE_ISSUE_INST = 0x2, SQ_THREAD_TRACE_ISSUE_IMMED = 0x3, } SQ_THREAD_TRACE_ISSUE; typedef enum SQ_THREAD_TRACE_ISSUE_MASK { SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x0, SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x1, SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x2, SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x3, } SQ_THREAD_TRACE_ISSUE_MASK; typedef enum SQ_PERF_SEL { SQ_PERF_SEL_NONE = 0x0, SQ_PERF_SEL_ACCUM_PREV = 0x1, SQ_PERF_SEL_CYCLES = 0x2, SQ_PERF_SEL_BUSY_CYCLES = 0x3, SQ_PERF_SEL_WAVES = 0x4, SQ_PERF_SEL_LEVEL_WAVES = 0x5, SQ_PERF_SEL_WAVES_EQ_64 = 0x6, SQ_PERF_SEL_WAVES_LT_64 = 0x7, SQ_PERF_SEL_WAVES_LT_48 = 0x8, SQ_PERF_SEL_WAVES_LT_32 = 0x9, SQ_PERF_SEL_WAVES_LT_16 = 0xa, SQ_PERF_SEL_WAVES_CU = 0xb, SQ_PERF_SEL_LEVEL_WAVES_CU = 0xc, SQ_PERF_SEL_BUSY_CU_CYCLES = 0xd, SQ_PERF_SEL_ITEMS = 0xe, SQ_PERF_SEL_QUADS = 0xf, SQ_PERF_SEL_EVENTS = 0x10, SQ_PERF_SEL_SURF_SYNCS = 0x11, SQ_PERF_SEL_TTRACE_REQS = 0x12, SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x13, SQ_PERF_SEL_TTRACE_STALL = 0x14, SQ_PERF_SEL_MSG_CNTR = 0x15, SQ_PERF_SEL_MSG_PERF = 0x16, SQ_PERF_SEL_MSG_GSCNT = 0x17, SQ_PERF_SEL_MSG_INTERRUPT = 0x18, SQ_PERF_SEL_INSTS = 0x19, SQ_PERF_SEL_INSTS_VALU = 0x1a, SQ_PERF_SEL_INSTS_VMEM_WR = 0x1b, SQ_PERF_SEL_INSTS_VMEM_RD = 0x1c, SQ_PERF_SEL_INSTS_VMEM = 0x1d, SQ_PERF_SEL_INSTS_SALU = 0x1e, SQ_PERF_SEL_INSTS_SMEM = 0x1f, SQ_PERF_SEL_INSTS_FLAT = 0x20, SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x21, SQ_PERF_SEL_INSTS_LDS = 0x22, SQ_PERF_SEL_INSTS_GDS = 0x23, SQ_PERF_SEL_INSTS_EXP = 0x24, SQ_PERF_SEL_INSTS_EXP_GDS = 0x25, SQ_PERF_SEL_INSTS_BRANCH = 0x26, SQ_PERF_SEL_INSTS_SENDMSG = 0x27, SQ_PERF_SEL_INSTS_VSKIPPED = 0x28, SQ_PERF_SEL_INST_LEVEL_VMEM = 0x29, SQ_PERF_SEL_INST_LEVEL_SMEM = 0x2a, SQ_PERF_SEL_INST_LEVEL_LDS = 0x2b, SQ_PERF_SEL_INST_LEVEL_GDS = 0x2c, SQ_PERF_SEL_INST_LEVEL_EXP = 0x2d, SQ_PERF_SEL_WAVE_CYCLES = 0x2e, SQ_PERF_SEL_WAVE_READY = 0x2f, SQ_PERF_SEL_WAIT_CNT_VM = 0x30, SQ_PERF_SEL_WAIT_CNT_LGKM = 0x31, SQ_PERF_SEL_WAIT_CNT_EXP = 0x32, SQ_PERF_SEL_WAIT_CNT_ANY = 0x33, SQ_PERF_SEL_WAIT_BARRIER = 0x34, SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x35, SQ_PERF_SEL_WAIT_SLEEP = 0x36, SQ_PERF_SEL_WAIT_OTHER = 0x37, SQ_PERF_SEL_WAIT_ANY = 0x38, SQ_PERF_SEL_WAIT_TTRACE = 0x39, SQ_PERF_SEL_WAIT_IFETCH = 0x3a, SQ_PERF_SEL_WAIT_INST_VMEM = 0x3b, SQ_PERF_SEL_WAIT_INST_SCA = 0x3c, SQ_PERF_SEL_WAIT_INST_LDS = 0x3d, SQ_PERF_SEL_WAIT_INST_VALU = 0x3e, SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x3f, SQ_PERF_SEL_WAIT_INST_MISC = 0x40, SQ_PERF_SEL_WAIT_INST_FLAT = 0x41, SQ_PERF_SEL_ACTIVE_INST_ANY = 0x42, SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x43, SQ_PERF_SEL_ACTIVE_INST_LDS = 0x44, SQ_PERF_SEL_ACTIVE_INST_VALU = 0x45, SQ_PERF_SEL_ACTIVE_INST_SCA = 0x46, SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x47, SQ_PERF_SEL_ACTIVE_INST_MISC = 0x48, SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x49, SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x4a, SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x4b, SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x4c, SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x4d, SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x4e, SQ_PERF_SEL_INST_CYCLES_VMEM = 0x4f, SQ_PERF_SEL_INST_CYCLES_LDS = 0x50, SQ_PERF_SEL_INST_CYCLES_VALU = 0x51, SQ_PERF_SEL_INST_CYCLES_EXP = 0x52, SQ_PERF_SEL_INST_CYCLES_GDS = 0x53, SQ_PERF_SEL_INST_CYCLES_SCA = 0x54, SQ_PERF_SEL_INST_CYCLES_SMEM = 0x55, SQ_PERF_SEL_INST_CYCLES_SALU = 0x56, SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x57, SQ_PERF_SEL_INST_CYCLES_MISC = 0x58, SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x59, SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x5a, SQ_PERF_SEL_IFETCH = 0x5b, SQ_PERF_SEL_IFETCH_LEVEL = 0x5c, SQ_PERF_SEL_CBRANCH_FORK = 0x5d, SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x5e, SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x5f, SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x60, SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x61, SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x62, SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x63, SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x64, SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x65, SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x66, SQ_PERF_SEL_VALU_DEP_STALL = 0x67, SQ_PERF_SEL_VALU_STARVE = 0x68, SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x69, SQ_PERF_SEL_LDS_BACK2BACK_STALL = 0x6a, SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x6b, SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x6c, SQ_PERF_SEL_VMEM_BACK2BACK_STALL = 0x6d, SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x6e, SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x6f, SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x70, SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL = 0x71, SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x72, SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x73, SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x74, SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x75, SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x76, SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x77, SQ_PERF_SEL_SRC_CD_BUSY = 0x78, SQ_PERF_SEL_PT_POWER_STALL = 0x79, SQ_PERF_SEL_USER0 = 0x7a, SQ_PERF_SEL_USER1 = 0x7b, SQ_PERF_SEL_USER2 = 0x7c, SQ_PERF_SEL_USER3 = 0x7d, SQ_PERF_SEL_USER4 = 0x7e, SQ_PERF_SEL_USER5 = 0x7f, SQ_PERF_SEL_USER6 = 0x80, SQ_PERF_SEL_USER7 = 0x81, SQ_PERF_SEL_USER8 = 0x82, SQ_PERF_SEL_USER9 = 0x83, SQ_PERF_SEL_USER10 = 0x84, SQ_PERF_SEL_USER11 = 0x85, SQ_PERF_SEL_USER12 = 0x86, SQ_PERF_SEL_USER13 = 0x87, SQ_PERF_SEL_USER14 = 0x88, SQ_PERF_SEL_USER15 = 0x89, SQ_PERF_SEL_USER_LEVEL0 = 0x8a, SQ_PERF_SEL_USER_LEVEL1 = 0x8b, SQ_PERF_SEL_USER_LEVEL2 = 0x8c, SQ_PERF_SEL_USER_LEVEL3 = 0x8d, SQ_PERF_SEL_USER_LEVEL4 = 0x8e, SQ_PERF_SEL_USER_LEVEL5 = 0x8f, SQ_PERF_SEL_USER_LEVEL6 = 0x90, SQ_PERF_SEL_USER_LEVEL7 = 0x91, SQ_PERF_SEL_USER_LEVEL8 = 0x92, SQ_PERF_SEL_USER_LEVEL9 = 0x93, SQ_PERF_SEL_USER_LEVEL10 = 0x94, SQ_PERF_SEL_USER_LEVEL11 = 0x95, SQ_PERF_SEL_USER_LEVEL12 = 0x96, SQ_PERF_SEL_USER_LEVEL13 = 0x97, SQ_PERF_SEL_USER_LEVEL14 = 0x98, SQ_PERF_SEL_USER_LEVEL15 = 0x99, SQ_PERF_SEL_POWER_VALU = 0x9a, SQ_PERF_SEL_POWER_VALU0 = 0x9b, SQ_PERF_SEL_POWER_VALU1 = 0x9c, SQ_PERF_SEL_POWER_VALU2 = 0x9d, SQ_PERF_SEL_POWER_GPR_RD = 0x9e, SQ_PERF_SEL_POWER_GPR_WR = 0x9f, SQ_PERF_SEL_POWER_LDS_BUSY = 0xa0, SQ_PERF_SEL_POWER_ALU_BUSY = 0xa1, SQ_PERF_SEL_POWER_TEX_BUSY = 0xa2, SQ_PERF_SEL_ACCUM_PREV_HIRES = 0xa3, SQ_PERF_SEL_DUMMY_LAST = 0xa7, SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0xa8, SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0xa9, SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0xaa, SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0xab, SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0xac, SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0xad, SQC_PERF_SEL_TC_REQ = 0xae, SQC_PERF_SEL_TC_INST_REQ = 0xaf, SQC_PERF_SEL_TC_DATA_REQ = 0xb0, SQC_PERF_SEL_TC_STALL = 0xb1, SQC_PERF_SEL_TC_STARVE = 0xb2, SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0xb3, SQC_PERF_SEL_ICACHE_REQ = 0xb4, SQC_PERF_SEL_ICACHE_HITS = 0xb5, SQC_PERF_SEL_ICACHE_MISSES = 0xb6, SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0xb7, SQC_PERF_SEL_ICACHE_UNCACHED = 0xb8, SQC_PERF_SEL_ICACHE_VOLATILE = 0xb9, SQC_PERF_SEL_ICACHE_INVAL_INST = 0xba, SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0xbb, SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_INST = 0xbc, SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_ASYNC = 0xbd, SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0xbe, SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0xbf, SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0xc0, SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xc1, SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0xc2, SQC_PERF_SEL_ICACHE_CACHE_STALL_VOLATILE_MISMATCH= 0xc3, SQC_PERF_SEL_ICACHE_CACHE_STALL_UNCACHED_HIT = 0xc4, SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0xc5, SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc6, SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xc7, SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0xc8, SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xc9, SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0xca, SQC_PERF_SEL_DCACHE_REQ = 0xcb, SQC_PERF_SEL_DCACHE_HITS = 0xcc, SQC_PERF_SEL_DCACHE_MISSES = 0xcd, SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0xce, SQC_PERF_SEL_DCACHE_UNCACHED = 0xcf, SQC_PERF_SEL_DCACHE_VOLATILE = 0xd0, SQC_PERF_SEL_DCACHE_INVAL_INST = 0xd1, SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0xd2, SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0xd3, SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0xd4, SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0xd5, SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0xd6, SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0xd7, SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xd8, SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0xd9, SQC_PERF_SEL_DCACHE_CACHE_STALL_VOLATILE_MISMATCH= 0xda, SQC_PERF_SEL_DCACHE_CACHE_STALL_UNCACHED_HIT = 0xdb, SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0xdc, SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xdd, SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xde, SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0xdf, SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xe0, SQC_PERF_SEL_DCACHE_REQ_1 = 0xe1, SQC_PERF_SEL_DCACHE_REQ_2 = 0xe2, SQC_PERF_SEL_DCACHE_REQ_4 = 0xe3, SQC_PERF_SEL_DCACHE_REQ_8 = 0xe4, SQC_PERF_SEL_DCACHE_REQ_16 = 0xe5, SQC_PERF_SEL_DCACHE_REQ_TIME = 0xe6, SQC_PERF_SEL_SQ_DCACHE_REQS = 0xe7, SQC_PERF_SEL_DCACHE_FLAT_REQ = 0xe8, SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0xe9, SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0xea, SQC_PERF_SEL_ICACHE_PRE_CC_LEVEL = 0xeb, SQC_PERF_SEL_ICACHE_POST_CC_LEVEL = 0xec, SQC_PERF_SEL_ICACHE_POST_CC_HIT_LEVEL = 0xed, SQC_PERF_SEL_ICACHE_POST_CC_MISS_LEVEL = 0xee, SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0xef, SQC_PERF_SEL_DCACHE_PRE_CC_LEVEL = 0xf0, SQC_PERF_SEL_DCACHE_POST_CC_LEVEL = 0xf1, SQC_PERF_SEL_DCACHE_POST_CC_HIT_LEVEL = 0xf2, SQC_PERF_SEL_DCACHE_POST_CC_MISS_LEVEL = 0xf3, SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0xf4, SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0xf5, SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0xf6, SQC_PERF_SEL_ERR_DCACHE_REQ_2_GPR_ADDR_UNALIGNED = 0xf7, SQC_PERF_SEL_ERR_DCACHE_REQ_4_GPR_ADDR_UNALIGNED = 0xf8, SQC_PERF_SEL_ERR_DCACHE_REQ_8_GPR_ADDR_UNALIGNED = 0xf9, SQC_PERF_SEL_ERR_DCACHE_REQ_16_GPR_ADDR_UNALIGNED= 0xfa, SQC_PERF_SEL_DUMMY_LAST = 0xfb, } SQ_PERF_SEL; typedef enum SQC_DATA_CACHE_POLICIES { SQC_DATA_CACHE_POLICY_HIT_LRU = 0x0, SQC_DATA_CACHE_POLICY_MISS_EVICT = 0x1, } SQC_DATA_CACHE_POLICIES; typedef enum SQ_CAC_POWER_SEL { SQ_CAC_POWER_VALU = 0x0, SQ_CAC_POWER_VALU0 = 0x1, SQ_CAC_POWER_VALU1 = 0x2, SQ_CAC_POWER_VALU2 = 0x3, SQ_CAC_POWER_GPR_RD = 0x4, SQ_CAC_POWER_GPR_WR = 0x5, SQ_CAC_POWER_LDS_BUSY = 0x6, SQ_CAC_POWER_ALU_BUSY = 0x7, SQ_CAC_POWER_TEX_BUSY = 0x8, } SQ_CAC_POWER_SEL; typedef enum SQ_IND_CMD_CMD { SQ_IND_CMD_CMD_NULL = 0x0, SQ_IND_CMD_CMD_HALT = 0x1, SQ_IND_CMD_CMD_RESUME = 0x2, SQ_IND_CMD_CMD_KILL = 0x3, SQ_IND_CMD_CMD_DEBUG = 0x4, SQ_IND_CMD_CMD_TRAP = 0x5, } SQ_IND_CMD_CMD; typedef enum SQ_IND_CMD_MODE { SQ_IND_CMD_MODE_SINGLE = 0x0, SQ_IND_CMD_MODE_BROADCAST = 0x1, SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x2, SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x3, SQ_IND_CMD_MODE_BROADCAST_ME = 0x4, } SQ_IND_CMD_MODE; typedef enum SQ_DED_INFO_SOURCE { SQ_DED_INFO_SOURCE_INVALID = 0x0, SQ_DED_INFO_SOURCE_INST = 0x1, SQ_DED_INFO_SOURCE_SGPR = 0x2, SQ_DED_INFO_SOURCE_VGPR = 0x3, SQ_DED_INFO_SOURCE_LDS = 0x4, SQ_DED_INFO_SOURCE_GDS = 0x5, SQ_DED_INFO_SOURCE_TA = 0x6, } SQ_DED_INFO_SOURCE; typedef enum SQ_ROUND_MODE { SQ_ROUND_NEAREST_EVEN = 0x0, SQ_ROUND_PLUS_INFINITY = 0x1, SQ_ROUND_MINUS_INFINITY = 0x2, SQ_ROUND_TO_ZERO = 0x3, } SQ_ROUND_MODE; typedef enum SQ_INTERRUPT_WORD_ENCODING { SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, SQ_INTERRUPT_WORD_ENCODING_INST = 0x1, SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x2, } SQ_INTERRUPT_WORD_ENCODING; typedef enum ENUM_SQ_EXPORT_RAT_INST { SQ_EXPORT_RAT_INST_NOP = 0x0, SQ_EXPORT_RAT_INST_STORE_TYPED = 0x1, SQ_EXPORT_RAT_INST_STORE_RAW = 0x2, SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x3, SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x4, SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x5, SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x6, SQ_EXPORT_RAT_INST_ADD = 0x7, SQ_EXPORT_RAT_INST_SUB = 0x8, SQ_EXPORT_RAT_INST_RSUB = 0x9, SQ_EXPORT_RAT_INST_MIN_INT = 0xa, SQ_EXPORT_RAT_INST_MIN_UINT = 0xb, SQ_EXPORT_RAT_INST_MAX_INT = 0xc, SQ_EXPORT_RAT_INST_MAX_UINT = 0xd, SQ_EXPORT_RAT_INST_AND = 0xe, SQ_EXPORT_RAT_INST_OR = 0xf, SQ_EXPORT_RAT_INST_XOR = 0x10, SQ_EXPORT_RAT_INST_MSKOR = 0x11, SQ_EXPORT_RAT_INST_INC_UINT = 0x12, SQ_EXPORT_RAT_INST_DEC_UINT = 0x13, SQ_EXPORT_RAT_INST_STORE_DWORD = 0x14, SQ_EXPORT_RAT_INST_STORE_SHORT = 0x15, SQ_EXPORT_RAT_INST_STORE_BYTE = 0x16, SQ_EXPORT_RAT_INST_NOP_RTN = 0x20, SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22, SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23, SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24, SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25, SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26, SQ_EXPORT_RAT_INST_ADD_RTN = 0x27, SQ_EXPORT_RAT_INST_SUB_RTN = 0x28, SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29, SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a, SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b, SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c, SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d, SQ_EXPORT_RAT_INST_AND_RTN = 0x2e, SQ_EXPORT_RAT_INST_OR_RTN = 0x2f, SQ_EXPORT_RAT_INST_XOR_RTN = 0x30, SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31, SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32, SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33, } ENUM_SQ_EXPORT_RAT_INST; typedef enum SQ_IBUF_ST { SQ_IBUF_IB_IDLE = 0x0, SQ_IBUF_IB_INI_WAIT_GNT = 0x1, SQ_IBUF_IB_INI_WAIT_DRET = 0x2, SQ_IBUF_IB_LE_4DW = 0x3, SQ_IBUF_IB_WAIT_DRET = 0x4, SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x5, SQ_IBUF_IB_DRET = 0x6, SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x7, } SQ_IBUF_ST; typedef enum SQ_INST_STR_ST { SQ_INST_STR_IB_WAVE_NORML = 0x0, SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x1, SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x2, SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x3, SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x4, SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x5, SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x6, SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x7, } SQ_INST_STR_ST; typedef enum SQ_WAVE_IB_ECC_ST { SQ_WAVE_IB_ECC_CLEAN = 0x0, SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x1, SQ_WAVE_IB_ECC_ERR_HALT = 0x2, SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x3, } SQ_WAVE_IB_ECC_ST; typedef enum SH_MEM_ALIGNMENT_MODE { SH_MEM_ALIGNMENT_MODE_DWORD = 0x0, SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x1, SH_MEM_ALIGNMENT_MODE_STRICT = 0x2, SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x3, } SH_MEM_ALIGNMENT_MODE; #define SQ_WAVE_TYPE_PS0 0x0 #define SQ_THREAD_TRACE_LFSR_PS 0x8016 #define SQ_THREAD_TRACE_LFSR_VS 0x801c #define SQ_THREAD_TRACE_LFSR_GS 0x801f #define SQ_THREAD_TRACE_LFSR_ES 0x8029 #define SQ_THREAD_TRACE_LFSR_HS 0x805e #define SQ_THREAD_TRACE_LFSR_LS 0x806b #define SQ_THREAD_TRACE_LFSR_CS 0x8097 #define SQIND_GLOBAL_REGS_OFFSET 0x0 #define SQIND_GLOBAL_REGS_SIZE 0x8 #define SQIND_LOCAL_REGS_OFFSET 0x8 #define SQIND_LOCAL_REGS_SIZE 0x8 #define SQIND_WAVE_HWREGS_OFFSET 0x10 #define SQIND_WAVE_HWREGS_SIZE 0x1f0 #define SQIND_WAVE_SGPRS_OFFSET 0x200 #define SQIND_WAVE_SGPRS_SIZE 0x200 #define SQ_GFXDEC_BEGIN 0xa000 #define SQ_GFXDEC_END 0xc000 #define SQ_GFXDEC_STATE_ID_SHIFT 0xa #define SQDEC_BEGIN 0x2300 #define SQDEC_END 0x23ff #define SQPERFSDEC_BEGIN 0xd9c0 #define SQPERFSDEC_END 0xda40 #define SQPERFDDEC_BEGIN 0xd1c0 #define SQPERFDDEC_END 0xd240 #define SQGFXUDEC_BEGIN 0xc340 #define SQGFXUDEC_END 0xc380 #define SQPWRDEC_BEGIN 0xf08c #define SQPWRDEC_END 0xf094 #define SQ_DISPATCHER_GFX_MIN 0x10 #define SQ_DISPATCHER_GFX_CNT_PER_RING 0x8 #define SQ_MAX_PGM_SGPRS 0x68 #define SQ_MAX_PGM_VGPRS 0x100 #define SQ_THREAD_TRACE_TIME_UNIT 0x4 #define SQ_INTERRUPT_ID 0xef #define SQ_EX_MODE_EXCP_VALU_BASE 0x0 #define SQ_EX_MODE_EXCP_VALU_SIZE 0x7 #define SQ_EX_MODE_EXCP_INVALID 0x0 #define SQ_EX_MODE_EXCP_INPUT_DENORM 0x1 #define SQ_EX_MODE_EXCP_DIV0 0x2 #define SQ_EX_MODE_EXCP_OVERFLOW 0x3 #define SQ_EX_MODE_EXCP_UNDERFLOW 0x4 #define SQ_EX_MODE_EXCP_INEXACT 0x5 #define SQ_EX_MODE_EXCP_INT_DIV0 0x6 #define SQ_EX_MODE_EXCP_ADDR_WATCH 0x7 #define SQ_EX_MODE_EXCP_MEM_VIOL 0x8 #define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0 #define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1 #define INST_ID_HW_TRAP 0xfffffff2 #define INST_ID_KILL_SEQ 0xfffffff3 #define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe #define SQ_ENC_SOP1_BITS 0xbe800000 #define SQ_ENC_SOP1_MASK 0xff800000 #define SQ_ENC_SOP1_FIELD 0x17d #define SQ_ENC_SOPC_BITS 0xbf000000 #define SQ_ENC_SOPC_MASK 0xff800000 #define SQ_ENC_SOPC_FIELD 0x17e #define SQ_ENC_SOPP_BITS 0xbf800000 #define SQ_ENC_SOPP_MASK 0xff800000 #define SQ_ENC_SOPP_FIELD 0x17f #define SQ_ENC_SOPK_BITS 0xb0000000 #define SQ_ENC_SOPK_MASK 0xf0000000 #define SQ_ENC_SOPK_FIELD 0xb #define SQ_ENC_SOP2_BITS 0x80000000 #define SQ_ENC_SOP2_MASK 0xc0000000 #define SQ_ENC_SOP2_FIELD 0x2 #define SQ_ENC_SMRD_BITS 0xc0000000 #define SQ_ENC_SMRD_MASK 0xf8000000 #define SQ_ENC_SMRD_FIELD 0x18 #define SQ_ENC_VOP1_BITS 0x7e000000 #define SQ_ENC_VOP1_MASK 0xfe000000 #define SQ_ENC_VOP1_FIELD 0x3f #define SQ_ENC_VOPC_BITS 0x7c000000 #define SQ_ENC_VOPC_MASK 0xfe000000 #define SQ_ENC_VOPC_FIELD 0x3e #define SQ_ENC_VOP2_BITS 0x0 #define SQ_ENC_VOP2_MASK 0x80000000 #define SQ_ENC_VOP2_FIELD 0x0 #define SQ_ENC_VINTRP_BITS 0xc8000000 #define SQ_ENC_VINTRP_MASK 0xfc000000 #define SQ_ENC_VINTRP_FIELD 0x32 #define SQ_ENC_VOP3_BITS 0xd0000000 #define SQ_ENC_VOP3_MASK 0xfc000000 #define SQ_ENC_VOP3_FIELD 0x34 #define SQ_ENC_DS_BITS 0xd8000000 #define SQ_ENC_DS_MASK 0xfc000000 #define SQ_ENC_DS_FIELD 0x36 #define SQ_ENC_MUBUF_BITS 0xe0000000 #define SQ_ENC_MUBUF_MASK 0xfc000000 #define SQ_ENC_MUBUF_FIELD 0x38 #define SQ_ENC_MTBUF_BITS 0xe8000000 #define SQ_ENC_MTBUF_MASK 0xfc000000 #define SQ_ENC_MTBUF_FIELD 0x3a #define SQ_ENC_MIMG_BITS 0xf0000000 #define SQ_ENC_MIMG_MASK 0xfc000000 #define SQ_ENC_MIMG_FIELD 0x3c #define SQ_ENC_EXP_BITS 0xf8000000 #define SQ_ENC_EXP_MASK 0xfc000000 #define SQ_ENC_EXP_FIELD 0x3e #define SQ_ENC_FLAT_BITS 0xdc000000 #define SQ_ENC_FLAT_MASK 0xfc000000 #define SQ_ENC_FLAT_FIELD 0x37 #define SQ_WAITCNT_VM_SHIFT 0x0 #define SQ_SENDMSG_STREAMID_SIZE 0x2 #define SQ_V_OPC_COUNT 0x100 #define SQ_HWREG_OFFSET_SIZE 0x5 #define SQ_HWREG_OFFSET_SHIFT 0x6 #define SQ_NUM_ATTR 0x21 #define SQ_NUM_VGPR 0x100 #define SQ_SENDMSG_MSG_SIZE 0x4 #define SQ_NUM_TTMP 0xc #define SQ_HWREG_ID_SIZE 0x6 #define SQ_SENDMSG_GSOP_SIZE 0x2 #define SQ_NUM_SGPR 0x68 #define SQ_EXP_NUM_MRT 0x8 #define SQ_SENDMSG_SYSTEM_SIZE 0x3 #define SQ_WAITCNT_LGKM_SHIFT 0x8 #define SQ_WAITCNT_EXP_SIZE 0x3 #define SQ_SENDMSG_SYSTEM_SHIFT 0x4 #define SQ_HWREG_SIZE_SHIFT 0xb #define SQ_EXP_NUM_GDS 0x5 #define SQ_SENDMSG_MSG_SHIFT 0x0 #define SQ_WAITCNT_EXP_SHIFT 0x4 #define SQ_WAITCNT_VM_SIZE 0x4 #define SQ_SENDMSG_GSOP_SHIFT 0x4 #define SQ_SRC_VGPR_BIT 0x100 #define SQ_V_OP2_COUNT 0x40 #define SQ_EXP_NUM_PARAM 0x20 #define SQ_SENDMSG_STREAMID_SHIFT 0x8 #define SQ_V_OP1_COUNT 0x80 #define SQ_WAITCNT_LGKM_SIZE 0x5 #define SQ_EXP_NUM_POS 0x4 #define SQ_HWREG_SIZE_SIZE 0x5 #define SQ_HWREG_ID_SHIFT 0x0 #define SQ_S_MOV_B32 0x3 #define SQ_S_MOV_B64 0x4 #define SQ_S_CMOV_B32 0x5 #define SQ_S_CMOV_B64 0x6 #define SQ_S_NOT_B32 0x7 #define SQ_S_NOT_B64 0x8 #define SQ_S_WQM_B32 0x9 #define SQ_S_WQM_B64 0xa #define SQ_S_BREV_B32 0xb #define SQ_S_BREV_B64 0xc #define SQ_S_BCNT0_I32_B32 0xd #define SQ_S_BCNT0_I32_B64 0xe #define SQ_S_BCNT1_I32_B32 0xf #define SQ_S_BCNT1_I32_B64 0x10 #define SQ_S_FF0_I32_B32 0x11 #define SQ_S_FF0_I32_B64 0x12 #define SQ_S_FF1_I32_B32 0x13 #define SQ_S_FF1_I32_B64 0x14 #define SQ_S_FLBIT_I32_B32 0x15 #define SQ_S_FLBIT_I32_B64 0x16 #define SQ_S_FLBIT_I32 0x17 #define SQ_S_FLBIT_I32_I64 0x18 #define SQ_S_SEXT_I32_I8 0x19 #define SQ_S_SEXT_I32_I16 0x1a #define SQ_S_BITSET0_B32 0x1b #define SQ_S_BITSET0_B64 0x1c #define SQ_S_BITSET1_B32 0x1d #define SQ_S_BITSET1_B64 0x1e #define SQ_S_GETPC_B64 0x1f #define SQ_S_SETPC_B64 0x20 #define SQ_S_SWAPPC_B64 0x21 #define SQ_S_RFE_B64 0x22 #define SQ_S_AND_SAVEEXEC_B64 0x24 #define SQ_S_OR_SAVEEXEC_B64 0x25 #define SQ_S_XOR_SAVEEXEC_B64 0x26 #define SQ_S_ANDN2_SAVEEXEC_B64 0x27 #define SQ_S_ORN2_SAVEEXEC_B64 0x28 #define SQ_S_NAND_SAVEEXEC_B64 0x29 #define SQ_S_NOR_SAVEEXEC_B64 0x2a #define SQ_S_XNOR_SAVEEXEC_B64 0x2b #define SQ_S_QUADMASK_B32 0x2c #define SQ_S_QUADMASK_B64 0x2d #define SQ_S_MOVRELS_B32 0x2e #define SQ_S_MOVRELS_B64 0x2f #define SQ_S_MOVRELD_B32 0x30 #define SQ_S_MOVRELD_B64 0x31 #define SQ_S_CBRANCH_JOIN 0x32 #define SQ_S_MOV_REGRD_B32 0x33 #define SQ_S_ABS_I32 0x34 #define SQ_S_MOV_FED_B32 0x35 #define SQ_ATTR0 0x0 #define SQ_S_MOVK_I32 0x0 #define SQ_S_CMOVK_I32 0x2 #define SQ_S_CMPK_EQ_I32 0x3 #define SQ_S_CMPK_LG_I32 0x4 #define SQ_S_CMPK_GT_I32 0x5 #define SQ_S_CMPK_GE_I32 0x6 #define SQ_S_CMPK_LT_I32 0x7 #define SQ_S_CMPK_LE_I32 0x8 #define SQ_S_CMPK_EQ_U32 0x9 #define SQ_S_CMPK_LG_U32 0xa #define SQ_S_CMPK_GT_U32 0xb #define SQ_S_CMPK_GE_U32 0xc #define SQ_S_CMPK_LT_U32 0xd #define SQ_S_CMPK_LE_U32 0xe #define SQ_S_ADDK_I32 0xf #define SQ_S_MULK_I32 0x10 #define SQ_S_CBRANCH_I_FORK 0x11 #define SQ_S_GETREG_B32 0x12 #define SQ_S_SETREG_B32 0x13 #define SQ_S_GETREG_REGRD_B32 0x14 #define SQ_S_SETREG_IMM32_B32 0x15 #define SQ_TBA_LO 0x6c #define SQ_TBA_HI 0x6d #define SQ_TMA_LO 0x6e #define SQ_TMA_HI 0x6f #define SQ_TTMP0 0x70 #define SQ_TTMP1 0x71 #define SQ_TTMP2 0x72 #define SQ_TTMP3 0x73 #define SQ_TTMP4 0x74 #define SQ_TTMP5 0x75 #define SQ_TTMP6 0x76 #define SQ_TTMP7 0x77 #define SQ_TTMP8 0x78 #define SQ_TTMP9 0x79 #define SQ_TTMP10 0x7a #define SQ_TTMP11 0x7b #define SQ_VGPR0 0x0 #define SQ_EXP 0x0 #define SQ_EXP_MRT0 0x0 #define SQ_EXP_MRTZ 0x8 #define SQ_EXP_NULL 0x9 #define SQ_EXP_POS0 0xc #define SQ_EXP_PARAM0 0x20 #define SQ_CNT1 0x0 #define SQ_CNT2 0x1 #define SQ_CNT3 0x2 #define SQ_CNT4 0x3 #define SQ_F 0x0 #define SQ_LT 0x1 #define SQ_EQ 0x2 #define SQ_LE 0x3 #define SQ_GT 0x4 #define SQ_LG 0x5 #define SQ_GE 0x6 #define SQ_O 0x7 #define SQ_U 0x8 #define SQ_NGE 0x9 #define SQ_NLG 0xa #define SQ_NGT 0xb #define SQ_NLE 0xc #define SQ_NEQ 0xd #define SQ_NLT 0xe #define SQ_TRU 0xf #define SQ_V_CMP_F_F32 0x0 #define SQ_V_CMP_LT_F32 0x1 #define SQ_V_CMP_EQ_F32 0x2 #define SQ_V_CMP_LE_F32 0x3 #define SQ_V_CMP_GT_F32 0x4 #define SQ_V_CMP_LG_F32 0x5 #define SQ_V_CMP_GE_F32 0x6 #define SQ_V_CMP_O_F32 0x7 #define SQ_V_CMP_U_F32 0x8 #define SQ_V_CMP_NGE_F32 0x9 #define SQ_V_CMP_NLG_F32 0xa #define SQ_V_CMP_NGT_F32 0xb #define SQ_V_CMP_NLE_F32 0xc #define SQ_V_CMP_NEQ_F32 0xd #define SQ_V_CMP_NLT_F32 0xe #define SQ_V_CMP_TRU_F32 0xf #define SQ_V_CMPX_F_F32 0x10 #define SQ_V_CMPX_LT_F32 0x11 #define SQ_V_CMPX_EQ_F32 0x12 #define SQ_V_CMPX_LE_F32 0x13 #define SQ_V_CMPX_GT_F32 0x14 #define SQ_V_CMPX_LG_F32 0x15 #define SQ_V_CMPX_GE_F32 0x16 #define SQ_V_CMPX_O_F32 0x17 #define SQ_V_CMPX_U_F32 0x18 #define SQ_V_CMPX_NGE_F32 0x19 #define SQ_V_CMPX_NLG_F32 0x1a #define SQ_V_CMPX_NGT_F32 0x1b #define SQ_V_CMPX_NLE_F32 0x1c #define SQ_V_CMPX_NEQ_F32 0x1d #define SQ_V_CMPX_NLT_F32 0x1e #define SQ_V_CMPX_TRU_F32 0x1f #define SQ_V_CMP_F_F64 0x20 #define SQ_V_CMP_LT_F64 0x21 #define SQ_V_CMP_EQ_F64 0x22 #define SQ_V_CMP_LE_F64 0x23 #define SQ_V_CMP_GT_F64 0x24 #define SQ_V_CMP_LG_F64 0x25 #define SQ_V_CMP_GE_F64 0x26 #define SQ_V_CMP_O_F64 0x27 #define SQ_V_CMP_U_F64 0x28 #define SQ_V_CMP_NGE_F64 0x29 #define SQ_V_CMP_NLG_F64 0x2a #define SQ_V_CMP_NGT_F64 0x2b #define SQ_V_CMP_NLE_F64 0x2c #define SQ_V_CMP_NEQ_F64 0x2d #define SQ_V_CMP_NLT_F64 0x2e #define SQ_V_CMP_TRU_F64 0x2f #define SQ_V_CMPX_F_F64 0x30 #define SQ_V_CMPX_LT_F64 0x31 #define SQ_V_CMPX_EQ_F64 0x32 #define SQ_V_CMPX_LE_F64 0x33 #define SQ_V_CMPX_GT_F64 0x34 #define SQ_V_CMPX_LG_F64 0x35 #define SQ_V_CMPX_GE_F64 0x36 #define SQ_V_CMPX_O_F64 0x37 #define SQ_V_CMPX_U_F64 0x38 #define SQ_V_CMPX_NGE_F64 0x39 #define SQ_V_CMPX_NLG_F64 0x3a #define SQ_V_CMPX_NGT_F64 0x3b #define SQ_V_CMPX_NLE_F64 0x3c #define SQ_V_CMPX_NEQ_F64 0x3d #define SQ_V_CMPX_NLT_F64 0x3e #define SQ_V_CMPX_TRU_F64 0x3f #define SQ_V_CMPS_F_F32 0x40 #define SQ_V_CMPS_LT_F32 0x41 #define SQ_V_CMPS_EQ_F32 0x42 #define SQ_V_CMPS_LE_F32 0x43 #define SQ_V_CMPS_GT_F32 0x44 #define SQ_V_CMPS_LG_F32 0x45 #define SQ_V_CMPS_GE_F32 0x46 #define SQ_V_CMPS_O_F32 0x47 #define SQ_V_CMPS_U_F32 0x48 #define SQ_V_CMPS_NGE_F32 0x49 #define SQ_V_CMPS_NLG_F32 0x4a #define SQ_V_CMPS_NGT_F32 0x4b #define SQ_V_CMPS_NLE_F32 0x4c #define SQ_V_CMPS_NEQ_F32 0x4d #define SQ_V_CMPS_NLT_F32 0x4e #define SQ_V_CMPS_TRU_F32 0x4f #define SQ_V_CMPSX_F_F32 0x50 #define SQ_V_CMPSX_LT_F32 0x51 #define SQ_V_CMPSX_EQ_F32 0x52 #define SQ_V_CMPSX_LE_F32 0x53 #define SQ_V_CMPSX_GT_F32 0x54 #define SQ_V_CMPSX_LG_F32 0x55 #define SQ_V_CMPSX_GE_F32 0x56 #define SQ_V_CMPSX_O_F32 0x57 #define SQ_V_CMPSX_U_F32 0x58 #define SQ_V_CMPSX_NGE_F32 0x59 #define SQ_V_CMPSX_NLG_F32 0x5a #define SQ_V_CMPSX_NGT_F32 0x5b #define SQ_V_CMPSX_NLE_F32 0x5c #define SQ_V_CMPSX_NEQ_F32 0x5d #define SQ_V_CMPSX_NLT_F32 0x5e #define SQ_V_CMPSX_TRU_F32 0x5f #define SQ_V_CMPS_F_F64 0x60 #define SQ_V_CMPS_LT_F64 0x61 #define SQ_V_CMPS_EQ_F64 0x62 #define SQ_V_CMPS_LE_F64 0x63 #define SQ_V_CMPS_GT_F64 0x64 #define SQ_V_CMPS_LG_F64 0x65 #define SQ_V_CMPS_GE_F64 0x66 #define SQ_V_CMPS_O_F64 0x67 #define SQ_V_CMPS_U_F64 0x68 #define SQ_V_CMPS_NGE_F64 0x69 #define SQ_V_CMPS_NLG_F64 0x6a #define SQ_V_CMPS_NGT_F64 0x6b #define SQ_V_CMPS_NLE_F64 0x6c #define SQ_V_CMPS_NEQ_F64 0x6d #define SQ_V_CMPS_NLT_F64 0x6e #define SQ_V_CMPS_TRU_F64 0x6f #define SQ_V_CMPSX_F_F64 0x70 #define SQ_V_CMPSX_LT_F64 0x71 #define SQ_V_CMPSX_EQ_F64 0x72 #define SQ_V_CMPSX_LE_F64 0x73 #define SQ_V_CMPSX_GT_F64 0x74 #define SQ_V_CMPSX_LG_F64 0x75 #define SQ_V_CMPSX_GE_F64 0x76 #define SQ_V_CMPSX_O_F64 0x77 #define SQ_V_CMPSX_U_F64 0x78 #define SQ_V_CMPSX_NGE_F64 0x79 #define SQ_V_CMPSX_NLG_F64 0x7a #define SQ_V_CMPSX_NGT_F64 0x7b #define SQ_V_CMPSX_NLE_F64 0x7c #define SQ_V_CMPSX_NEQ_F64 0x7d #define SQ_V_CMPSX_NLT_F64 0x7e #define SQ_V_CMPSX_TRU_F64 0x7f #define SQ_V_CMP_F_I32 0x80 #define SQ_V_CMP_LT_I32 0x81 #define SQ_V_CMP_EQ_I32 0x82 #define SQ_V_CMP_LE_I32 0x83 #define SQ_V_CMP_GT_I32 0x84 #define SQ_V_CMP_NE_I32 0x85 #define SQ_V_CMP_GE_I32 0x86 #define SQ_V_CMP_T_I32 0x87 #define SQ_V_CMPX_F_I32 0x90 #define SQ_V_CMPX_LT_I32 0x91 #define SQ_V_CMPX_EQ_I32 0x92 #define SQ_V_CMPX_LE_I32 0x93 #define SQ_V_CMPX_GT_I32 0x94 #define SQ_V_CMPX_NE_I32 0x95 #define SQ_V_CMPX_GE_I32 0x96 #define SQ_V_CMPX_T_I32 0x97 #define SQ_V_CMP_F_I64 0xa0 #define SQ_V_CMP_LT_I64 0xa1 #define SQ_V_CMP_EQ_I64 0xa2 #define SQ_V_CMP_LE_I64 0xa3 #define SQ_V_CMP_GT_I64 0xa4 #define SQ_V_CMP_NE_I64 0xa5 #define SQ_V_CMP_GE_I64 0xa6 #define SQ_V_CMP_T_I64 0xa7 #define SQ_V_CMPX_F_I64 0xb0 #define SQ_V_CMPX_LT_I64 0xb1 #define SQ_V_CMPX_EQ_I64 0xb2 #define SQ_V_CMPX_LE_I64 0xb3 #define SQ_V_CMPX_GT_I64 0xb4 #define SQ_V_CMPX_NE_I64 0xb5 #define SQ_V_CMPX_GE_I64 0xb6 #define SQ_V_CMPX_T_I64 0xb7 #define SQ_V_CMP_F_U32 0xc0 #define SQ_V_CMP_LT_U32 0xc1 #define SQ_V_CMP_EQ_U32 0xc2 #define SQ_V_CMP_LE_U32 0xc3 #define SQ_V_CMP_GT_U32 0xc4 #define SQ_V_CMP_NE_U32 0xc5 #define SQ_V_CMP_GE_U32 0xc6 #define SQ_V_CMP_T_U32 0xc7 #define SQ_V_CMPX_F_U32 0xd0 #define SQ_V_CMPX_LT_U32 0xd1 #define SQ_V_CMPX_EQ_U32 0xd2 #define SQ_V_CMPX_LE_U32 0xd3 #define SQ_V_CMPX_GT_U32 0xd4 #define SQ_V_CMPX_NE_U32 0xd5 #define SQ_V_CMPX_GE_U32 0xd6 #define SQ_V_CMPX_T_U32 0xd7 #define SQ_V_CMP_F_U64 0xe0 #define SQ_V_CMP_LT_U64 0xe1 #define SQ_V_CMP_EQ_U64 0xe2 #define SQ_V_CMP_LE_U64 0xe3 #define SQ_V_CMP_GT_U64 0xe4 #define SQ_V_CMP_NE_U64 0xe5 #define SQ_V_CMP_GE_U64 0xe6 #define SQ_V_CMP_T_U64 0xe7 #define SQ_V_CMPX_F_U64 0xf0 #define SQ_V_CMPX_LT_U64 0xf1 #define SQ_V_CMPX_EQ_U64 0xf2 #define SQ_V_CMPX_LE_U64 0xf3 #define SQ_V_CMPX_GT_U64 0xf4 #define SQ_V_CMPX_NE_U64 0xf5 #define SQ_V_CMPX_GE_U64 0xf6 #define SQ_V_CMPX_T_U64 0xf7 #define SQ_V_CMP_CLASS_F32 0x88 #define SQ_V_CMPX_CLASS_F32 0x98 #define SQ_V_CMP_CLASS_F64 0xa8 #define SQ_V_CMPX_CLASS_F64 0xb8 #define SQ_SGPR0 0x0 #define SQ_F 0x0 #define SQ_LT 0x1 #define SQ_EQ 0x2 #define SQ_LE 0x3 #define SQ_GT 0x4 #define SQ_NE 0x5 #define SQ_GE 0x6 #define SQ_T 0x7 #define SQ_SRC_64_INT 0xc0 #define SQ_SRC_M_1_INT 0xc1 #define SQ_SRC_M_2_INT 0xc2 #define SQ_SRC_M_3_INT 0xc3 #define SQ_SRC_M_4_INT 0xc4 #define SQ_SRC_M_5_INT 0xc5 #define SQ_SRC_M_6_INT 0xc6 #define SQ_SRC_M_7_INT 0xc7 #define SQ_SRC_M_8_INT 0xc8 #define SQ_SRC_M_9_INT 0xc9 #define SQ_SRC_M_10_INT 0xca #define SQ_SRC_M_11_INT 0xcb #define SQ_SRC_M_12_INT 0xcc #define SQ_SRC_M_13_INT 0xcd #define SQ_SRC_M_14_INT 0xce #define SQ_SRC_M_15_INT 0xcf #define SQ_SRC_M_16_INT 0xd0 #define SQ_SRC_0_5 0xf0 #define SQ_SRC_M_0_5 0xf1 #define SQ_SRC_1 0xf2 #define SQ_SRC_M_1 0xf3 #define SQ_SRC_2 0xf4 #define SQ_SRC_M_2 0xf5 #define SQ_SRC_4 0xf6 #define SQ_SRC_M_4 0xf7 #define SQ_SRC_0 0x80 #define SQ_SRC_1_INT 0x81 #define SQ_SRC_2_INT 0x82 #define SQ_SRC_3_INT 0x83 #define SQ_SRC_4_INT 0x84 #define SQ_SRC_5_INT 0x85 #define SQ_SRC_6_INT 0x86 #define SQ_SRC_7_INT 0x87 #define SQ_SRC_8_INT 0x88 #define SQ_SRC_9_INT 0x89 #define SQ_SRC_10_INT 0x8a #define SQ_SRC_11_INT 0x8b #define SQ_SRC_12_INT 0x8c #define SQ_SRC_13_INT 0x8d #define SQ_SRC_14_INT 0x8e #define SQ_SRC_15_INT 0x8f #define SQ_SRC_16_INT 0x90 #define SQ_SRC_17_INT 0x91 #define SQ_SRC_18_INT 0x92 #define SQ_SRC_19_INT 0x93 #define SQ_SRC_20_INT 0x94 #define SQ_SRC_21_INT 0x95 #define SQ_SRC_22_INT 0x96 #define SQ_SRC_23_INT 0x97 #define SQ_SRC_24_INT 0x98 #define SQ_SRC_25_INT 0x99 #define SQ_SRC_26_INT 0x9a #define SQ_SRC_27_INT 0x9b #define SQ_SRC_28_INT 0x9c #define SQ_SRC_29_INT 0x9d #define SQ_SRC_30_INT 0x9e #define SQ_SRC_31_INT 0x9f #define SQ_SRC_32_INT 0xa0 #define SQ_SRC_33_INT 0xa1 #define SQ_SRC_34_INT 0xa2 #define SQ_SRC_35_INT 0xa3 #define SQ_SRC_36_INT 0xa4 #define SQ_SRC_37_INT 0xa5 #define SQ_SRC_38_INT 0xa6 #define SQ_SRC_39_INT 0xa7 #define SQ_SRC_40_INT 0xa8 #define SQ_SRC_41_INT 0xa9 #define SQ_SRC_42_INT 0xaa #define SQ_SRC_43_INT 0xab #define SQ_SRC_44_INT 0xac #define SQ_SRC_45_INT 0xad #define SQ_SRC_46_INT 0xae #define SQ_SRC_47_INT 0xaf #define SQ_SRC_48_INT 0xb0 #define SQ_SRC_49_INT 0xb1 #define SQ_SRC_50_INT 0xb2 #define SQ_SRC_51_INT 0xb3 #define SQ_SRC_52_INT 0xb4 #define SQ_SRC_53_INT 0xb5 #define SQ_SRC_54_INT 0xb6 #define SQ_SRC_55_INT 0xb7 #define SQ_SRC_56_INT 0xb8 #define SQ_SRC_57_INT 0xb9 #define SQ_SRC_58_INT 0xba #define SQ_SRC_59_INT 0xbb #define SQ_SRC_60_INT 0xbc #define SQ_SRC_61_INT 0xbd #define SQ_SRC_62_INT 0xbe #define SQ_SRC_63_INT 0xbf #define SQ_BUFFER_LOAD_FORMAT_X 0x0 #define SQ_BUFFER_LOAD_FORMAT_XY 0x1 #define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2 #define SQ_BUFFER_LOAD_FORMAT_XYZW 0x3 #define SQ_BUFFER_STORE_FORMAT_X 0x4 #define SQ_BUFFER_STORE_FORMAT_XY 0x5 #define SQ_BUFFER_STORE_FORMAT_XYZ 0x6 #define SQ_BUFFER_STORE_FORMAT_XYZW 0x7 #define SQ_BUFFER_LOAD_UBYTE 0x8 #define SQ_BUFFER_LOAD_SBYTE 0x9 #define SQ_BUFFER_LOAD_USHORT 0xa #define SQ_BUFFER_LOAD_SSHORT 0xb #define SQ_BUFFER_LOAD_DWORD 0xc #define SQ_BUFFER_LOAD_DWORDX2 0xd #define SQ_BUFFER_LOAD_DWORDX4 0xe #define SQ_BUFFER_LOAD_DWORDX3 0xf #define SQ_BUFFER_STORE_BYTE 0x18 #define SQ_BUFFER_STORE_SHORT 0x1a #define SQ_BUFFER_STORE_DWORD 0x1c #define SQ_BUFFER_STORE_DWORDX2 0x1d #define SQ_BUFFER_STORE_DWORDX4 0x1e #define SQ_BUFFER_STORE_DWORDX3 0x1f #define SQ_BUFFER_ATOMIC_SWAP 0x30 #define SQ_BUFFER_ATOMIC_CMPSWAP 0x31 #define SQ_BUFFER_ATOMIC_ADD 0x32 #define SQ_BUFFER_ATOMIC_SUB 0x33 #define SQ_BUFFER_ATOMIC_SMIN 0x35 #define SQ_BUFFER_ATOMIC_UMIN 0x36 #define SQ_BUFFER_ATOMIC_SMAX 0x37 #define SQ_BUFFER_ATOMIC_UMAX 0x38 #define SQ_BUFFER_ATOMIC_AND 0x39 #define SQ_BUFFER_ATOMIC_OR 0x3a #define SQ_BUFFER_ATOMIC_XOR 0x3b #define SQ_BUFFER_ATOMIC_INC 0x3c #define SQ_BUFFER_ATOMIC_DEC 0x3d #define SQ_BUFFER_ATOMIC_FCMPSWAP 0x3e #define SQ_BUFFER_ATOMIC_FMIN 0x3f #define SQ_BUFFER_ATOMIC_FMAX 0x40 #define SQ_BUFFER_ATOMIC_SWAP_X2 0x50 #define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x51 #define SQ_BUFFER_ATOMIC_ADD_X2 0x52 #define SQ_BUFFER_ATOMIC_SUB_X2 0x53 #define SQ_BUFFER_ATOMIC_SMIN_X2 0x55 #define SQ_BUFFER_ATOMIC_UMIN_X2 0x56 #define SQ_BUFFER_ATOMIC_SMAX_X2 0x57 #define SQ_BUFFER_ATOMIC_UMAX_X2 0x58 #define SQ_BUFFER_ATOMIC_AND_X2 0x59 #define SQ_BUFFER_ATOMIC_OR_X2 0x5a #define SQ_BUFFER_ATOMIC_XOR_X2 0x5b #define SQ_BUFFER_ATOMIC_INC_X2 0x5c #define SQ_BUFFER_ATOMIC_DEC_X2 0x5d #define SQ_BUFFER_ATOMIC_FCMPSWAP_X2 0x5e #define SQ_BUFFER_ATOMIC_FMIN_X2 0x5f #define SQ_BUFFER_ATOMIC_FMAX_X2 0x60 #define SQ_BUFFER_WBINVL1_VOL 0x70 #define SQ_BUFFER_WBINVL1 0x71 #define SQ_DS_ADD_U32 0x0 #define SQ_DS_SUB_U32 0x1 #define SQ_DS_RSUB_U32 0x2 #define SQ_DS_INC_U32 0x3 #define SQ_DS_DEC_U32 0x4 #define SQ_DS_MIN_I32 0x5 #define SQ_DS_MAX_I32 0x6 #define SQ_DS_MIN_U32 0x7 #define SQ_DS_MAX_U32 0x8 #define SQ_DS_AND_B32 0x9 #define SQ_DS_OR_B32 0xa #define SQ_DS_XOR_B32 0xb #define SQ_DS_MSKOR_B32 0xc #define SQ_DS_WRITE_B32 0xd #define SQ_DS_WRITE2_B32 0xe #define SQ_DS_WRITE2ST64_B32 0xf #define SQ_DS_CMPST_B32 0x10 #define SQ_DS_CMPST_F32 0x11 #define SQ_DS_MIN_F32 0x12 #define SQ_DS_MAX_F32 0x13 #define SQ_DS_NOP 0x14 #define SQ_DS_GWS_SEMA_RELEASE_ALL 0x18 #define SQ_DS_GWS_INIT 0x19 #define SQ_DS_GWS_SEMA_V 0x1a #define SQ_DS_GWS_SEMA_BR 0x1b #define SQ_DS_GWS_SEMA_P 0x1c #define SQ_DS_GWS_BARRIER 0x1d #define SQ_DS_WRITE_B8 0x1e #define SQ_DS_WRITE_B16 0x1f #define SQ_DS_ADD_RTN_U32 0x20 #define SQ_DS_SUB_RTN_U32 0x21 #define SQ_DS_RSUB_RTN_U32 0x22 #define SQ_DS_INC_RTN_U32 0x23 #define SQ_DS_DEC_RTN_U32 0x24 #define SQ_DS_MIN_RTN_I32 0x25 #define SQ_DS_MAX_RTN_I32 0x26 #define SQ_DS_MIN_RTN_U32 0x27 #define SQ_DS_MAX_RTN_U32 0x28 #define SQ_DS_AND_RTN_B32 0x29 #define SQ_DS_OR_RTN_B32 0x2a #define SQ_DS_XOR_RTN_B32 0x2b #define SQ_DS_MSKOR_RTN_B32 0x2c #define SQ_DS_WRXCHG_RTN_B32 0x2d #define SQ_DS_WRXCHG2_RTN_B32 0x2e #define SQ_DS_WRXCHG2ST64_RTN_B32 0x2f #define SQ_DS_CMPST_RTN_B32 0x30 #define SQ_DS_CMPST_RTN_F32 0x31 #define SQ_DS_MIN_RTN_F32 0x32 #define SQ_DS_MAX_RTN_F32 0x33 #define SQ_DS_WRAP_RTN_B32 0x34 #define SQ_DS_SWIZZLE_B32 0x35 #define SQ_DS_READ_B32 0x36 #define SQ_DS_READ2_B32 0x37 #define SQ_DS_READ2ST64_B32 0x38 #define SQ_DS_READ_I8 0x39 #define SQ_DS_READ_U8 0x3a #define SQ_DS_READ_I16 0x3b #define SQ_DS_READ_U16 0x3c #define SQ_DS_CONSUME 0x3d #define SQ_DS_APPEND 0x3e #define SQ_DS_ORDERED_COUNT 0x3f #define SQ_DS_ADD_U64 0x40 #define SQ_DS_SUB_U64 0x41 #define SQ_DS_RSUB_U64 0x42 #define SQ_DS_INC_U64 0x43 #define SQ_DS_DEC_U64 0x44 #define SQ_DS_MIN_I64 0x45 #define SQ_DS_MAX_I64 0x46 #define SQ_DS_MIN_U64 0x47 #define SQ_DS_MAX_U64 0x48 #define SQ_DS_AND_B64 0x49 #define SQ_DS_OR_B64 0x4a #define SQ_DS_XOR_B64 0x4b #define SQ_DS_MSKOR_B64 0x4c #define SQ_DS_WRITE_B64 0x4d #define SQ_DS_WRITE2_B64 0x4e #define SQ_DS_WRITE2ST64_B64 0x4f #define SQ_DS_CMPST_B64 0x50 #define SQ_DS_CMPST_F64 0x51 #define SQ_DS_MIN_F64 0x52 #define SQ_DS_MAX_F64 0x53 #define SQ_DS_ADD_RTN_U64 0x60 #define SQ_DS_SUB_RTN_U64 0x61 #define SQ_DS_RSUB_RTN_U64 0x62 #define SQ_DS_INC_RTN_U64 0x63 #define SQ_DS_DEC_RTN_U64 0x64 #define SQ_DS_MIN_RTN_I64 0x65 #define SQ_DS_MAX_RTN_I64 0x66 #define SQ_DS_MIN_RTN_U64 0x67 #define SQ_DS_MAX_RTN_U64 0x68 #define SQ_DS_AND_RTN_B64 0x69 #define SQ_DS_OR_RTN_B64 0x6a #define SQ_DS_XOR_RTN_B64 0x6b #define SQ_DS_MSKOR_RTN_B64 0x6c #define SQ_DS_WRXCHG_RTN_B64 0x6d #define SQ_DS_WRXCHG2_RTN_B64 0x6e #define SQ_DS_WRXCHG2ST64_RTN_B64 0x6f #define SQ_DS_CMPST_RTN_B64 0x70 #define SQ_DS_CMPST_RTN_F64 0x71 #define SQ_DS_MIN_RTN_F64 0x72 #define SQ_DS_MAX_RTN_F64 0x73 #define SQ_DS_READ_B64 0x76 #define SQ_DS_READ2_B64 0x77 #define SQ_DS_READ2ST64_B64 0x78 #define SQ_DS_CONDXCHG32_RTN_B64 0x7e #define SQ_DS_ADD_SRC2_U32 0x80 #define SQ_DS_SUB_SRC2_U32 0x81 #define SQ_DS_RSUB_SRC2_U32 0x82 #define SQ_DS_INC_SRC2_U32 0x83 #define SQ_DS_DEC_SRC2_U32 0x84 #define SQ_DS_MIN_SRC2_I32 0x85 #define SQ_DS_MAX_SRC2_I32 0x86 #define SQ_DS_MIN_SRC2_U32 0x87 #define SQ_DS_MAX_SRC2_U32 0x88 #define SQ_DS_AND_SRC2_B32 0x89 #define SQ_DS_OR_SRC2_B32 0x8a #define SQ_DS_XOR_SRC2_B32 0x8b #define SQ_DS_WRITE_SRC2_B32 0x8d #define SQ_DS_MIN_SRC2_F32 0x92 #define SQ_DS_MAX_SRC2_F32 0x93 #define SQ_DS_ADD_SRC2_U64 0xc0 #define SQ_DS_SUB_SRC2_U64 0xc1 #define SQ_DS_RSUB_SRC2_U64 0xc2 #define SQ_DS_INC_SRC2_U64 0xc3 #define SQ_DS_DEC_SRC2_U64 0xc4 #define SQ_DS_MIN_SRC2_I64 0xc5 #define SQ_DS_MAX_SRC2_I64 0xc6 #define SQ_DS_MIN_SRC2_U64 0xc7 #define SQ_DS_MAX_SRC2_U64 0xc8 #define SQ_DS_AND_SRC2_B64 0xc9 #define SQ_DS_OR_SRC2_B64 0xca #define SQ_DS_XOR_SRC2_B64 0xcb #define SQ_DS_WRITE_SRC2_B64 0xcd #define SQ_DS_MIN_SRC2_F64 0xd2 #define SQ_DS_MAX_SRC2_F64 0xd3 #define SQ_DS_WRITE_B96 0xde #define SQ_DS_WRITE_B128 0xdf #define SQ_DS_CONDXCHG32_RTN_B128 0xfd #define SQ_DS_READ_B96 0xfe #define SQ_DS_READ_B128 0xff #define SQ_SRC_SCC 0xfd #define SQ_OMOD_OFF 0x0 #define SQ_OMOD_M2 0x1 #define SQ_OMOD_M4 0x2 #define SQ_OMOD_D2 0x3 #define SQ_EXP_GDS0 0x18 #define SQ_GS_OP_NOP 0x0 #define SQ_GS_OP_CUT 0x1 #define SQ_GS_OP_EMIT 0x2 #define SQ_GS_OP_EMIT_CUT 0x3 #define SQ_IMAGE_LOAD 0x0 #define SQ_IMAGE_LOAD_MIP 0x1 #define SQ_IMAGE_LOAD_PCK 0x2 #define SQ_IMAGE_LOAD_PCK_SGN 0x3 #define SQ_IMAGE_LOAD_MIP_PCK 0x4 #define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x5 #define SQ_IMAGE_STORE 0x8 #define SQ_IMAGE_STORE_MIP 0x9 #define SQ_IMAGE_STORE_PCK 0xa #define SQ_IMAGE_STORE_MIP_PCK 0xb #define SQ_IMAGE_GET_RESINFO 0xe #define SQ_IMAGE_ATOMIC_SWAP 0xf #define SQ_IMAGE_ATOMIC_CMPSWAP 0x10 #define SQ_IMAGE_ATOMIC_ADD 0x11 #define SQ_IMAGE_ATOMIC_SUB 0x12 #define SQ_IMAGE_ATOMIC_SMIN 0x14 #define SQ_IMAGE_ATOMIC_UMIN 0x15 #define SQ_IMAGE_ATOMIC_SMAX 0x16 #define SQ_IMAGE_ATOMIC_UMAX 0x17 #define SQ_IMAGE_ATOMIC_AND 0x18 #define SQ_IMAGE_ATOMIC_OR 0x19 #define SQ_IMAGE_ATOMIC_XOR 0x1a #define SQ_IMAGE_ATOMIC_INC 0x1b #define SQ_IMAGE_ATOMIC_DEC 0x1c #define SQ_IMAGE_ATOMIC_FCMPSWAP 0x1d #define SQ_IMAGE_ATOMIC_FMIN 0x1e #define SQ_IMAGE_ATOMIC_FMAX 0x1f #define SQ_IMAGE_SAMPLE 0x20 #define SQ_IMAGE_SAMPLE_CL 0x21 #define SQ_IMAGE_SAMPLE_D 0x22 #define SQ_IMAGE_SAMPLE_D_CL 0x23 #define SQ_IMAGE_SAMPLE_L 0x24 #define SQ_IMAGE_SAMPLE_B 0x25 #define SQ_IMAGE_SAMPLE_B_CL 0x26 #define SQ_IMAGE_SAMPLE_LZ 0x27 #define SQ_IMAGE_SAMPLE_C 0x28 #define SQ_IMAGE_SAMPLE_C_CL 0x29 #define SQ_IMAGE_SAMPLE_C_D 0x2a #define SQ_IMAGE_SAMPLE_C_D_CL 0x2b #define SQ_IMAGE_SAMPLE_C_L 0x2c #define SQ_IMAGE_SAMPLE_C_B 0x2d #define SQ_IMAGE_SAMPLE_C_B_CL 0x2e #define SQ_IMAGE_SAMPLE_C_LZ 0x2f #define SQ_IMAGE_SAMPLE_O 0x30 #define SQ_IMAGE_SAMPLE_CL_O 0x31 #define SQ_IMAGE_SAMPLE_D_O 0x32 #define SQ_IMAGE_SAMPLE_D_CL_O 0x33 #define SQ_IMAGE_SAMPLE_L_O 0x34 #define SQ_IMAGE_SAMPLE_B_O 0x35 #define SQ_IMAGE_SAMPLE_B_CL_O 0x36 #define SQ_IMAGE_SAMPLE_LZ_O 0x37 #define SQ_IMAGE_SAMPLE_C_O 0x38 #define SQ_IMAGE_SAMPLE_C_CL_O 0x39 #define SQ_IMAGE_SAMPLE_C_D_O 0x3a #define SQ_IMAGE_SAMPLE_C_D_CL_O 0x3b #define SQ_IMAGE_SAMPLE_C_L_O 0x3c #define SQ_IMAGE_SAMPLE_C_B_O 0x3d #define SQ_IMAGE_SAMPLE_C_B_CL_O 0x3e #define SQ_IMAGE_SAMPLE_C_LZ_O 0x3f #define SQ_IMAGE_GATHER4 0x40 #define SQ_IMAGE_GATHER4_CL 0x41 #define SQ_IMAGE_GATHER4_L 0x44 #define SQ_IMAGE_GATHER4_B 0x45 #define SQ_IMAGE_GATHER4_B_CL 0x46 #define SQ_IMAGE_GATHER4_LZ 0x47 #define SQ_IMAGE_GATHER4_C 0x48 #define SQ_IMAGE_GATHER4_C_CL 0x49 #define SQ_IMAGE_GATHER4_C_L 0x4c #define SQ_IMAGE_GATHER4_C_B 0x4d #define SQ_IMAGE_GATHER4_C_B_CL 0x4e #define SQ_IMAGE_GATHER4_C_LZ 0x4f #define SQ_IMAGE_GATHER4_O 0x50 #define SQ_IMAGE_GATHER4_CL_O 0x51 #define SQ_IMAGE_GATHER4_L_O 0x54 #define SQ_IMAGE_GATHER4_B_O 0x55 #define SQ_IMAGE_GATHER4_B_CL_O 0x56 #define SQ_IMAGE_GATHER4_LZ_O 0x57 #define SQ_IMAGE_GATHER4_C_O 0x58 #define SQ_IMAGE_GATHER4_C_CL_O 0x59 #define SQ_IMAGE_GATHER4_C_L_O 0x5c #define SQ_IMAGE_GATHER4_C_B_O 0x5d #define SQ_IMAGE_GATHER4_C_B_CL_O 0x5e #define SQ_IMAGE_GATHER4_C_LZ_O 0x5f #define SQ_IMAGE_GET_LOD 0x60 #define SQ_IMAGE_SAMPLE_CD 0x68 #define SQ_IMAGE_SAMPLE_CD_CL 0x69 #define SQ_IMAGE_SAMPLE_C_CD 0x6a #define SQ_IMAGE_SAMPLE_C_CD_CL 0x6b #define SQ_IMAGE_SAMPLE_CD_O 0x6c #define SQ_IMAGE_SAMPLE_CD_CL_O 0x6d #define SQ_IMAGE_SAMPLE_C_CD_O 0x6e #define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6f #define SQ_IMAGE_RSRC256 0x7e #define SQ_IMAGE_SAMPLER 0x7f #define SQ_SRC_VCCZ 0xfb #define SQ_SRC_VGPR0 0x100 #define SQ_DFMT_INVALID 0x0 #define SQ_DFMT_8 0x1 #define SQ_DFMT_16 0x2 #define SQ_DFMT_8_8 0x3 #define SQ_DFMT_32 0x4 #define SQ_DFMT_16_16 0x5 #define SQ_DFMT_10_11_11 0x6 #define SQ_DFMT_11_11_10 0x7 #define SQ_DFMT_10_10_10_2 0x8 #define SQ_DFMT_2_10_10_10 0x9 #define SQ_DFMT_8_8_8_8 0xa #define SQ_DFMT_32_32 0xb #define SQ_DFMT_16_16_16_16 0xc #define SQ_DFMT_32_32_32 0xd #define SQ_DFMT_32_32_32_32 0xe #define SQ_TBUFFER_LOAD_FORMAT_X 0x0 #define SQ_TBUFFER_LOAD_FORMAT_XY 0x1 #define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2 #define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x3 #define SQ_TBUFFER_STORE_FORMAT_X 0x4 #define SQ_TBUFFER_STORE_FORMAT_XY 0x5 #define SQ_TBUFFER_STORE_FORMAT_XYZ 0x6 #define SQ_TBUFFER_STORE_FORMAT_XYZW 0x7 #define SQ_CHAN_X 0x0 #define SQ_CHAN_Y 0x1 #define SQ_CHAN_Z 0x2 #define SQ_CHAN_W 0x3 #define SQ_EXEC_LO 0x7e #define SQ_EXEC_HI 0x7f #define SQ_S_LOAD_DWORD 0x0 #define SQ_S_LOAD_DWORDX2 0x1 #define SQ_S_LOAD_DWORDX4 0x2 #define SQ_S_LOAD_DWORDX8 0x3 #define SQ_S_LOAD_DWORDX16 0x4 #define SQ_S_BUFFER_LOAD_DWORD 0x8 #define SQ_S_BUFFER_LOAD_DWORDX2 0x9 #define SQ_S_BUFFER_LOAD_DWORDX4 0xa #define SQ_S_BUFFER_LOAD_DWORDX8 0xb #define SQ_S_BUFFER_LOAD_DWORDX16 0xc #define SQ_S_DCACHE_INV_VOL 0x1d #define SQ_S_MEMTIME 0x1e #define SQ_S_DCACHE_INV 0x1f #define SQ_V_NOP 0x0 #define SQ_V_MOV_B32 0x1 #define SQ_V_READFIRSTLANE_B32 0x2 #define SQ_V_CVT_I32_F64 0x3 #define SQ_V_CVT_F64_I32 0x4 #define SQ_V_CVT_F32_I32 0x5 #define SQ_V_CVT_F32_U32 0x6 #define SQ_V_CVT_U32_F32 0x7 #define SQ_V_CVT_I32_F32 0x8 #define SQ_V_MOV_FED_B32 0x9 #define SQ_V_CVT_F16_F32 0xa #define SQ_V_CVT_F32_F16 0xb #define SQ_V_CVT_RPI_I32_F32 0xc #define SQ_V_CVT_FLR_I32_F32 0xd #define SQ_V_CVT_OFF_F32_I4 0xe #define SQ_V_CVT_F32_F64 0xf #define SQ_V_CVT_F64_F32 0x10 #define SQ_V_CVT_F32_UBYTE0 0x11 #define SQ_V_CVT_F32_UBYTE1 0x12 #define SQ_V_CVT_F32_UBYTE2 0x13 #define SQ_V_CVT_F32_UBYTE3 0x14 #define SQ_V_CVT_U32_F64 0x15 #define SQ_V_CVT_F64_U32 0x16 #define SQ_V_TRUNC_F64 0x17 #define SQ_V_CEIL_F64 0x18 #define SQ_V_RNDNE_F64 0x19 #define SQ_V_FLOOR_F64 0x1a #define SQ_V_FRACT_F32 0x20 #define SQ_V_TRUNC_F32 0x21 #define SQ_V_CEIL_F32 0x22 #define SQ_V_RNDNE_F32 0x23 #define SQ_V_FLOOR_F32 0x24 #define SQ_V_EXP_F32 0x25 #define SQ_V_LOG_CLAMP_F32 0x26 #define SQ_V_LOG_F32 0x27 #define SQ_V_RCP_CLAMP_F32 0x28 #define SQ_V_RCP_LEGACY_F32 0x29 #define SQ_V_RCP_F32 0x2a #define SQ_V_RCP_IFLAG_F32 0x2b #define SQ_V_RSQ_CLAMP_F32 0x2c #define SQ_V_RSQ_LEGACY_F32 0x2d #define SQ_V_RSQ_F32 0x2e #define SQ_V_RCP_F64 0x2f #define SQ_V_RCP_CLAMP_F64 0x30 #define SQ_V_RSQ_F64 0x31 #define SQ_V_RSQ_CLAMP_F64 0x32 #define SQ_V_SQRT_F32 0x33 #define SQ_V_SQRT_F64 0x34 #define SQ_V_SIN_F32 0x35 #define SQ_V_COS_F32 0x36 #define SQ_V_NOT_B32 0x37 #define SQ_V_BFREV_B32 0x38 #define SQ_V_FFBH_U32 0x39 #define SQ_V_FFBL_B32 0x3a #define SQ_V_FFBH_I32 0x3b #define SQ_V_FREXP_EXP_I32_F64 0x3c #define SQ_V_FREXP_MANT_F64 0x3d #define SQ_V_FRACT_F64 0x3e #define SQ_V_FREXP_EXP_I32_F32 0x3f #define SQ_V_FREXP_MANT_F32 0x40 #define SQ_V_CLREXCP 0x41 #define SQ_V_MOVRELD_B32 0x42 #define SQ_V_MOVRELS_B32 0x43 #define SQ_V_MOVRELSD_B32 0x44 #define SQ_V_LOG_LEGACY_F32 0x45 #define SQ_V_EXP_LEGACY_F32 0x46 #define SQ_NFMT_UNORM 0x0 #define SQ_NFMT_SNORM 0x1 #define SQ_NFMT_USCALED 0x2 #define SQ_NFMT_SSCALED 0x3 #define SQ_NFMT_UINT 0x4 #define SQ_NFMT_SINT 0x5 #define SQ_NFMT_SNORM_OGL 0x6 #define SQ_NFMT_FLOAT 0x7 #define SQ_V_OP1_OFFSET 0x180 #define SQ_V_OP2_OFFSET 0x100 #define SQ_V_OPC_OFFSET 0x0 #define SQ_V_INTERP_P1_F32 0x0 #define SQ_V_INTERP_P2_F32 0x1 #define SQ_V_INTERP_MOV_F32 0x2 #define SQ_S_NOP 0x0 #define SQ_S_ENDPGM 0x1 #define SQ_S_BRANCH 0x2 #define SQ_S_CBRANCH_SCC0 0x4 #define SQ_S_CBRANCH_SCC1 0x5 #define SQ_S_CBRANCH_VCCZ 0x6 #define SQ_S_CBRANCH_VCCNZ 0x7 #define SQ_S_CBRANCH_EXECZ 0x8 #define SQ_S_CBRANCH_EXECNZ 0x9 #define SQ_S_BARRIER 0xa #define SQ_S_SETKILL 0xb #define SQ_S_WAITCNT 0xc #define SQ_S_SETHALT 0xd #define SQ_S_SLEEP 0xe #define SQ_S_SETPRIO 0xf #define SQ_S_SENDMSG 0x10 #define SQ_S_SENDMSGHALT 0x11 #define SQ_S_TRAP 0x12 #define SQ_S_ICACHE_INV 0x13 #define SQ_S_INCPERFLEVEL 0x14 #define SQ_S_DECPERFLEVEL 0x15 #define SQ_S_TTRACEDATA 0x16 #define SQ_S_CBRANCH_CDBGSYS 0x17 #define SQ_S_CBRANCH_CDBGUSER 0x18 #define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19 #define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1a #define SQ_SRC_LITERAL 0xff #define SQ_VCC_LO 0x6a #define SQ_VCC_HI 0x6b #define SQ_PARAM_P10 0x0 #define SQ_PARAM_P20 0x1 #define SQ_PARAM_P0 0x2 #define SQ_SRC_LDS_DIRECT 0xfe #define SQ_FLAT_SCRATCH_LO 0x68 #define SQ_FLAT_SCRATCH_HI 0x69 #define SQ_V_CNDMASK_B32 0x0 #define SQ_V_READLANE_B32 0x1 #define SQ_V_WRITELANE_B32 0x2 #define SQ_V_ADD_F32 0x3 #define SQ_V_SUB_F32 0x4 #define SQ_V_SUBREV_F32 0x5 #define SQ_V_MAC_LEGACY_F32 0x6 #define SQ_V_MUL_LEGACY_F32 0x7 #define SQ_V_MUL_F32 0x8 #define SQ_V_MUL_I32_I24 0x9 #define SQ_V_MUL_HI_I32_I24 0xa #define SQ_V_MUL_U32_U24 0xb #define SQ_V_MUL_HI_U32_U24 0xc #define SQ_V_MIN_LEGACY_F32 0xd #define SQ_V_MAX_LEGACY_F32 0xe #define SQ_V_MIN_F32 0xf #define SQ_V_MAX_F32 0x10 #define SQ_V_MIN_I32 0x11 #define SQ_V_MAX_I32 0x12 #define SQ_V_MIN_U32 0x13 #define SQ_V_MAX_U32 0x14 #define SQ_V_LSHR_B32 0x15 #define SQ_V_LSHRREV_B32 0x16 #define SQ_V_ASHR_I32 0x17 #define SQ_V_ASHRREV_I32 0x18 #define SQ_V_LSHL_B32 0x19 #define SQ_V_LSHLREV_B32 0x1a #define SQ_V_AND_B32 0x1b #define SQ_V_OR_B32 0x1c #define SQ_V_XOR_B32 0x1d #define SQ_V_BFM_B32 0x1e #define SQ_V_MAC_F32 0x1f #define SQ_V_MADMK_F32 0x20 #define SQ_V_MADAK_F32 0x21 #define SQ_V_BCNT_U32_B32 0x22 #define SQ_V_MBCNT_LO_U32_B32 0x23 #define SQ_V_MBCNT_HI_U32_B32 0x24 #define SQ_V_ADD_I32 0x25 #define SQ_V_SUB_I32 0x26 #define SQ_V_SUBREV_I32 0x27 #define SQ_V_ADDC_U32 0x28 #define SQ_V_SUBB_U32 0x29 #define SQ_V_SUBBREV_U32 0x2a #define SQ_V_LDEXP_F32 0x2b #define SQ_V_CVT_PKACCUM_U8_F32 0x2c #define SQ_V_CVT_PKNORM_I16_F32 0x2d #define SQ_V_CVT_PKNORM_U16_F32 0x2e #define SQ_V_CVT_PKRTZ_F16_F32 0x2f #define SQ_V_CVT_PK_U16_U32 0x30 #define SQ_V_CVT_PK_I16_I32 0x31 #define SQ_FLAT_LOAD_UBYTE 0x8 #define SQ_FLAT_LOAD_SBYTE 0x9 #define SQ_FLAT_LOAD_USHORT 0xa #define SQ_FLAT_LOAD_SSHORT 0xb #define SQ_FLAT_LOAD_DWORD 0xc #define SQ_FLAT_LOAD_DWORDX2 0xd #define SQ_FLAT_LOAD_DWORDX4 0xe #define SQ_FLAT_LOAD_DWORDX3 0xf #define SQ_FLAT_STORE_BYTE 0x18 #define SQ_FLAT_STORE_SHORT 0x1a #define SQ_FLAT_STORE_DWORD 0x1c #define SQ_FLAT_STORE_DWORDX2 0x1d #define SQ_FLAT_STORE_DWORDX4 0x1e #define SQ_FLAT_STORE_DWORDX3 0x1f #define SQ_FLAT_ATOMIC_SWAP 0x30 #define SQ_FLAT_ATOMIC_CMPSWAP 0x31 #define SQ_FLAT_ATOMIC_ADD 0x32 #define SQ_FLAT_ATOMIC_SUB 0x33 #define SQ_FLAT_ATOMIC_SMIN 0x35 #define SQ_FLAT_ATOMIC_UMIN 0x36 #define SQ_FLAT_ATOMIC_SMAX 0x37 #define SQ_FLAT_ATOMIC_UMAX 0x38 #define SQ_FLAT_ATOMIC_AND 0x39 #define SQ_FLAT_ATOMIC_OR 0x3a #define SQ_FLAT_ATOMIC_XOR 0x3b #define SQ_FLAT_ATOMIC_INC 0x3c #define SQ_FLAT_ATOMIC_DEC 0x3d #define SQ_FLAT_ATOMIC_FCMPSWAP 0x3e #define SQ_FLAT_ATOMIC_FMIN 0x3f #define SQ_FLAT_ATOMIC_FMAX 0x40 #define SQ_FLAT_ATOMIC_SWAP_X2 0x50 #define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x51 #define SQ_FLAT_ATOMIC_ADD_X2 0x52 #define SQ_FLAT_ATOMIC_SUB_X2 0x53 #define SQ_FLAT_ATOMIC_SMIN_X2 0x55 #define SQ_FLAT_ATOMIC_UMIN_X2 0x56 #define SQ_FLAT_ATOMIC_SMAX_X2 0x57 #define SQ_FLAT_ATOMIC_UMAX_X2 0x58 #define SQ_FLAT_ATOMIC_AND_X2 0x59 #define SQ_FLAT_ATOMIC_OR_X2 0x5a #define SQ_FLAT_ATOMIC_XOR_X2 0x5b #define SQ_FLAT_ATOMIC_INC_X2 0x5c #define SQ_FLAT_ATOMIC_DEC_X2 0x5d #define SQ_FLAT_ATOMIC_FCMPSWAP_X2 0x5e #define SQ_FLAT_ATOMIC_FMIN_X2 0x5f #define SQ_FLAT_ATOMIC_FMAX_X2 0x60 #define SQ_S_CMP_EQ_I32 0x0 #define SQ_S_CMP_LG_I32 0x1 #define SQ_S_CMP_GT_I32 0x2 #define SQ_S_CMP_GE_I32 0x3 #define SQ_S_CMP_LT_I32 0x4 #define SQ_S_CMP_LE_I32 0x5 #define SQ_S_CMP_EQ_U32 0x6 #define SQ_S_CMP_LG_U32 0x7 #define SQ_S_CMP_GT_U32 0x8 #define SQ_S_CMP_GE_U32 0x9 #define SQ_S_CMP_LT_U32 0xa #define SQ_S_CMP_LE_U32 0xb #define SQ_S_BITCMP0_B32 0xc #define SQ_S_BITCMP1_B32 0xd #define SQ_S_BITCMP0_B64 0xe #define SQ_S_BITCMP1_B64 0xf #define SQ_S_SETVSKIP 0x10 #define SQ_M0 0x7c #define SQ_V_MAD_LEGACY_F32 0x140 #define SQ_V_MAD_F32 0x141 #define SQ_V_MAD_I32_I24 0x142 #define SQ_V_MAD_U32_U24 0x143 #define SQ_V_CUBEID_F32 0x144 #define SQ_V_CUBESC_F32 0x145 #define SQ_V_CUBETC_F32 0x146 #define SQ_V_CUBEMA_F32 0x147 #define SQ_V_BFE_U32 0x148 #define SQ_V_BFE_I32 0x149 #define SQ_V_BFI_B32 0x14a #define SQ_V_FMA_F32 0x14b #define SQ_V_FMA_F64 0x14c #define SQ_V_LERP_U8 0x14d #define SQ_V_ALIGNBIT_B32 0x14e #define SQ_V_ALIGNBYTE_B32 0x14f #define SQ_V_MULLIT_F32 0x150 #define SQ_V_MIN3_F32 0x151 #define SQ_V_MIN3_I32 0x152 #define SQ_V_MIN3_U32 0x153 #define SQ_V_MAX3_F32 0x154 #define SQ_V_MAX3_I32 0x155 #define SQ_V_MAX3_U32 0x156 #define SQ_V_MED3_F32 0x157 #define SQ_V_MED3_I32 0x158 #define SQ_V_MED3_U32 0x159 #define SQ_V_SAD_U8 0x15a #define SQ_V_SAD_HI_U8 0x15b #define SQ_V_SAD_U16 0x15c #define SQ_V_SAD_U32 0x15d #define SQ_V_CVT_PK_U8_F32 0x15e #define SQ_V_DIV_FIXUP_F32 0x15f #define SQ_V_DIV_FIXUP_F64 0x160 #define SQ_V_LSHL_B64 0x161 #define SQ_V_LSHR_B64 0x162 #define SQ_V_ASHR_I64 0x163 #define SQ_V_ADD_F64 0x164 #define SQ_V_MUL_F64 0x165 #define SQ_V_MIN_F64 0x166 #define SQ_V_MAX_F64 0x167 #define SQ_V_LDEXP_F64 0x168 #define SQ_V_MUL_LO_U32 0x169 #define SQ_V_MUL_HI_U32 0x16a #define SQ_V_MUL_LO_I32 0x16b #define SQ_V_MUL_HI_I32 0x16c #define SQ_V_DIV_SCALE_F32 0x16d #define SQ_V_DIV_SCALE_F64 0x16e #define SQ_V_DIV_FMAS_F32 0x16f #define SQ_V_DIV_FMAS_F64 0x170 #define SQ_V_MSAD_U8 0x171 #define SQ_V_QSAD_PK_U16_U8 0x172 #define SQ_V_MQSAD_PK_U16_U8 0x173 #define SQ_V_TRIG_PREOP_F64 0x174 #define SQ_V_MQSAD_U32_U8 0x175 #define SQ_V_MAD_U64_U32 0x176 #define SQ_V_MAD_I64_I32 0x177 #define SQ_VCC_ALL 0x0 #define SQ_SRC_EXECZ 0xfc #define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x1 #define SQ_SYSMSG_OP_REG_RD 0x2 #define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x3 #define SQ_SYSMSG_OP_TTRACE_PC 0x4 #define SQ_HW_REG_MODE 0x1 #define SQ_HW_REG_STATUS 0x2 #define SQ_HW_REG_TRAPSTS 0x3 #define SQ_HW_REG_HW_ID 0x4 #define SQ_HW_REG_GPR_ALLOC 0x5 #define SQ_HW_REG_LDS_ALLOC 0x6 #define SQ_HW_REG_IB_STS 0x7 #define SQ_HW_REG_PC_LO 0x8 #define SQ_HW_REG_PC_HI 0x9 #define SQ_HW_REG_INST_DW0 0xa #define SQ_HW_REG_INST_DW1 0xb #define SQ_HW_REG_IB_DBG0 0xc #define SQ_S_ADD_U32 0x0 #define SQ_S_SUB_U32 0x1 #define SQ_S_ADD_I32 0x2 #define SQ_S_SUB_I32 0x3 #define SQ_S_ADDC_U32 0x4 #define SQ_S_SUBB_U32 0x5 #define SQ_S_MIN_I32 0x6 #define SQ_S_MIN_U32 0x7 #define SQ_S_MAX_I32 0x8 #define SQ_S_MAX_U32 0x9 #define SQ_S_CSELECT_B32 0xa #define SQ_S_CSELECT_B64 0xb #define SQ_S_AND_B32 0xe #define SQ_S_AND_B64 0xf #define SQ_S_OR_B32 0x10 #define SQ_S_OR_B64 0x11 #define SQ_S_XOR_B32 0x12 #define SQ_S_XOR_B64 0x13 #define SQ_S_ANDN2_B32 0x14 #define SQ_S_ANDN2_B64 0x15 #define SQ_S_ORN2_B32 0x16 #define SQ_S_ORN2_B64 0x17 #define SQ_S_NAND_B32 0x18 #define SQ_S_NAND_B64 0x19 #define SQ_S_NOR_B32 0x1a #define SQ_S_NOR_B64 0x1b #define SQ_S_XNOR_B32 0x1c #define SQ_S_XNOR_B64 0x1d #define SQ_S_LSHL_B32 0x1e #define SQ_S_LSHL_B64 0x1f #define SQ_S_LSHR_B32 0x20 #define SQ_S_LSHR_B64 0x21 #define SQ_S_ASHR_I32 0x22 #define SQ_S_ASHR_I64 0x23 #define SQ_S_BFM_B32 0x24 #define SQ_S_BFM_B64 0x25 #define SQ_S_MUL_I32 0x26 #define SQ_S_BFE_U32 0x27 #define SQ_S_BFE_I32 0x28 #define SQ_S_BFE_U64 0x29 #define SQ_S_BFE_I64 0x2a #define SQ_S_CBRANCH_G_FORK 0x2b #define SQ_S_ABSDIFF_I32 0x2c #define SQ_MSG_INTERRUPT 0x1 #define SQ_MSG_GS 0x2 #define SQ_MSG_GS_DONE 0x3 #define SQ_MSG_SYSMSG 0xf typedef enum TEX_BORDER_COLOR_TYPE { TEX_BorderColor_TransparentBlack = 0x0, TEX_BorderColor_OpaqueBlack = 0x1, TEX_BorderColor_OpaqueWhite = 0x2, TEX_BorderColor_Register = 0x3, } TEX_BORDER_COLOR_TYPE; typedef enum TEX_CHROMA_KEY { TEX_ChromaKey_Disabled = 0x0, TEX_ChromaKey_Kill = 0x1, TEX_ChromaKey_Blend = 0x2, TEX_ChromaKey_RESERVED_3 = 0x3, } TEX_CHROMA_KEY; typedef enum TEX_CLAMP { TEX_Clamp_Repeat = 0x0, TEX_Clamp_Mirror = 0x1, TEX_Clamp_ClampToLast = 0x2, TEX_Clamp_MirrorOnceToLast = 0x3, TEX_Clamp_ClampHalfToBorder = 0x4, TEX_Clamp_MirrorOnceHalfToBorder = 0x5, TEX_Clamp_ClampToBorder = 0x6, TEX_Clamp_MirrorOnceToBorder = 0x7, } TEX_CLAMP; typedef enum TEX_COORD_TYPE { TEX_CoordType_Unnormalized = 0x0, TEX_CoordType_Normalized = 0x1, } TEX_COORD_TYPE; typedef enum TEX_DEPTH_COMPARE_FUNCTION { TEX_DepthCompareFunction_Never = 0x0, TEX_DepthCompareFunction_Less = 0x1, TEX_DepthCompareFunction_Equal = 0x2, TEX_DepthCompareFunction_LessEqual = 0x3, TEX_DepthCompareFunction_Greater = 0x4, TEX_DepthCompareFunction_NotEqual = 0x5, TEX_DepthCompareFunction_GreaterEqual = 0x6, TEX_DepthCompareFunction_Always = 0x7, } TEX_DEPTH_COMPARE_FUNCTION; typedef enum TEX_DIM { TEX_Dim_1D = 0x0, TEX_Dim_2D = 0x1, TEX_Dim_3D = 0x2, TEX_Dim_CubeMap = 0x3, TEX_Dim_1DArray = 0x4, TEX_Dim_2DArray = 0x5, TEX_Dim_2D_MSAA = 0x6, TEX_Dim_2DArray_MSAA = 0x7, } TEX_DIM; typedef enum TEX_FORMAT_COMP { TEX_FormatComp_Unsigned = 0x0, TEX_FormatComp_Signed = 0x1, TEX_FormatComp_UnsignedBiased = 0x2, TEX_FormatComp_RESERVED_3 = 0x3, } TEX_FORMAT_COMP; typedef enum TEX_MAX_ANISO_RATIO { TEX_MaxAnisoRatio_1to1 = 0x0, TEX_MaxAnisoRatio_2to1 = 0x1, TEX_MaxAnisoRatio_4to1 = 0x2, TEX_MaxAnisoRatio_8to1 = 0x3, TEX_MaxAnisoRatio_16to1 = 0x4, TEX_MaxAnisoRatio_RESERVED_5 = 0x5, TEX_MaxAnisoRatio_RESERVED_6 = 0x6, TEX_MaxAnisoRatio_RESERVED_7 = 0x7, } TEX_MAX_ANISO_RATIO; typedef enum TEX_MIP_FILTER { TEX_MipFilter_None = 0x0, TEX_MipFilter_Point = 0x1, TEX_MipFilter_Linear = 0x2, TEX_MipFilter_RESERVED_3 = 0x3, } TEX_MIP_FILTER; typedef enum TEX_REQUEST_SIZE { TEX_RequestSize_32B = 0x0, TEX_RequestSize_64B = 0x1, TEX_RequestSize_128B = 0x2, TEX_RequestSize_2X64B = 0x3, } TEX_REQUEST_SIZE; typedef enum TEX_SAMPLER_TYPE { TEX_SamplerType_Invalid = 0x0, TEX_SamplerType_Valid = 0x1, } TEX_SAMPLER_TYPE; typedef enum TEX_XY_FILTER { TEX_XYFilter_Point = 0x0, TEX_XYFilter_Linear = 0x1, TEX_XYFilter_AnisoPoint = 0x2, TEX_XYFilter_AnisoLinear = 0x3, } TEX_XY_FILTER; typedef enum TEX_Z_FILTER { TEX_ZFilter_None = 0x0, TEX_ZFilter_Point = 0x1, TEX_ZFilter_Linear = 0x2, TEX_ZFilter_RESERVED_3 = 0x3, } TEX_Z_FILTER; typedef enum VTX_CLAMP { VTX_Clamp_ClampToZero = 0x0, VTX_Clamp_ClampToNAN = 0x1, } VTX_CLAMP; typedef enum VTX_FETCH_TYPE { VTX_FetchType_VertexData = 0x0, VTX_FetchType_InstanceData = 0x1, VTX_FetchType_NoIndexOffset = 0x2, VTX_FetchType_RESERVED_3 = 0x3, } VTX_FETCH_TYPE; typedef enum VTX_FORMAT_COMP_ALL { VTX_FormatCompAll_Unsigned = 0x0, VTX_FormatCompAll_Signed = 0x1, } VTX_FORMAT_COMP_ALL; typedef enum VTX_MEM_REQUEST_SIZE { VTX_MemRequestSize_32B = 0x0, VTX_MemRequestSize_64B = 0x1, } VTX_MEM_REQUEST_SIZE; typedef enum TVX_DATA_FORMAT { TVX_FMT_INVALID = 0x0, TVX_FMT_8 = 0x1, TVX_FMT_4_4 = 0x2, TVX_FMT_3_3_2 = 0x3, TVX_FMT_RESERVED_4 = 0x4, TVX_FMT_16 = 0x5, TVX_FMT_16_FLOAT = 0x6, TVX_FMT_8_8 = 0x7, TVX_FMT_5_6_5 = 0x8, TVX_FMT_6_5_5 = 0x9, TVX_FMT_1_5_5_5 = 0xa, TVX_FMT_4_4_4_4 = 0xb, TVX_FMT_5_5_5_1 = 0xc, TVX_FMT_32 = 0xd, TVX_FMT_32_FLOAT = 0xe, TVX_FMT_16_16 = 0xf, TVX_FMT_16_16_FLOAT = 0x10, TVX_FMT_8_24 = 0x11, TVX_FMT_8_24_FLOAT = 0x12, TVX_FMT_24_8 = 0x13, TVX_FMT_24_8_FLOAT = 0x14, TVX_FMT_10_11_11 = 0x15, TVX_FMT_10_11_11_FLOAT = 0x16, TVX_FMT_11_11_10 = 0x17, TVX_FMT_11_11_10_FLOAT = 0x18, TVX_FMT_2_10_10_10 = 0x19, TVX_FMT_8_8_8_8 = 0x1a, TVX_FMT_10_10_10_2 = 0x1b, TVX_FMT_X24_8_32_FLOAT = 0x1c, TVX_FMT_32_32 = 0x1d, TVX_FMT_32_32_FLOAT = 0x1e, TVX_FMT_16_16_16_16 = 0x1f, TVX_FMT_16_16_16_16_FLOAT = 0x20, TVX_FMT_RESERVED_33 = 0x21, TVX_FMT_32_32_32_32 = 0x22, TVX_FMT_32_32_32_32_FLOAT = 0x23, TVX_FMT_RESERVED_36 = 0x24, TVX_FMT_1 = 0x25, TVX_FMT_1_REVERSED = 0x26, TVX_FMT_GB_GR = 0x27, TVX_FMT_BG_RG = 0x28, TVX_FMT_32_AS_8 = 0x29, TVX_FMT_32_AS_8_8 = 0x2a, TVX_FMT_5_9_9_9_SHAREDEXP = 0x2b, TVX_FMT_8_8_8 = 0x2c, TVX_FMT_16_16_16 = 0x2d, TVX_FMT_16_16_16_FLOAT = 0x2e, TVX_FMT_32_32_32 = 0x2f, TVX_FMT_32_32_32_FLOAT = 0x30, TVX_FMT_BC1 = 0x31, TVX_FMT_BC2 = 0x32, TVX_FMT_BC3 = 0x33, TVX_FMT_BC4 = 0x34, TVX_FMT_BC5 = 0x35, TVX_FMT_APC0 = 0x36, TVX_FMT_APC1 = 0x37, TVX_FMT_APC2 = 0x38, TVX_FMT_APC3 = 0x39, TVX_FMT_APC4 = 0x3a, TVX_FMT_APC5 = 0x3b, TVX_FMT_APC6 = 0x3c, TVX_FMT_APC7 = 0x3d, TVX_FMT_CTX1 = 0x3e, TVX_FMT_RESERVED_63 = 0x3f, } TVX_DATA_FORMAT; typedef enum TVX_DST_SEL { TVX_DstSel_X = 0x0, TVX_DstSel_Y = 0x1, TVX_DstSel_Z = 0x2, TVX_DstSel_W = 0x3, TVX_DstSel_0f = 0x4, TVX_DstSel_1f = 0x5, TVX_DstSel_RESERVED_6 = 0x6, TVX_DstSel_Mask = 0x7, } TVX_DST_SEL; typedef enum TVX_ENDIAN_SWAP { TVX_EndianSwap_None = 0x0, TVX_EndianSwap_8in16 = 0x1, TVX_EndianSwap_8in32 = 0x2, TVX_EndianSwap_8in64 = 0x3, } TVX_ENDIAN_SWAP; typedef enum TVX_INST { TVX_Inst_NormalVertexFetch = 0x0, TVX_Inst_SemanticVertexFetch = 0x1, TVX_Inst_RESERVED_2 = 0x2, TVX_Inst_LD = 0x3, TVX_Inst_GetTextureResInfo = 0x4, TVX_Inst_GetNumberOfSamples = 0x5, TVX_Inst_GetLOD = 0x6, TVX_Inst_GetGradientsH = 0x7, TVX_Inst_GetGradientsV = 0x8, TVX_Inst_SetTextureOffsets = 0x9, TVX_Inst_KeepGradients = 0xa, TVX_Inst_SetGradientsH = 0xb, TVX_Inst_SetGradientsV = 0xc, TVX_Inst_Pass = 0xd, TVX_Inst_GetBufferResInfo = 0xe, TVX_Inst_RESERVED_15 = 0xf, TVX_Inst_Sample = 0x10, TVX_Inst_Sample_L = 0x11, TVX_Inst_Sample_LB = 0x12, TVX_Inst_Sample_LZ = 0x13, TVX_Inst_Sample_G = 0x14, TVX_Inst_Gather4 = 0x15, TVX_Inst_Sample_G_LB = 0x16, TVX_Inst_Gather4_O = 0x17, TVX_Inst_Sample_C = 0x18, TVX_Inst_Sample_C_L = 0x19, TVX_Inst_Sample_C_LB = 0x1a, TVX_Inst_Sample_C_LZ = 0x1b, TVX_Inst_Sample_C_G = 0x1c, TVX_Inst_Gather4_C = 0x1d, TVX_Inst_Sample_C_G_LB = 0x1e, TVX_Inst_Gather4_C_O = 0x1f, } TVX_INST; typedef enum TVX_NUM_FORMAT_ALL { TVX_NumFormatAll_Norm = 0x0, TVX_NumFormatAll_Int = 0x1, TVX_NumFormatAll_Scaled = 0x2, TVX_NumFormatAll_RESERVED_3 = 0x3, } TVX_NUM_FORMAT_ALL; typedef enum TVX_SRC_SEL { TVX_SrcSel_X = 0x0, TVX_SrcSel_Y = 0x1, TVX_SrcSel_Z = 0x2, TVX_SrcSel_W = 0x3, TVX_SrcSel_0f = 0x4, TVX_SrcSel_1f = 0x5, } TVX_SRC_SEL; typedef enum TVX_SRF_MODE_ALL { TVX_SRFModeAll_ZCMO = 0x0, TVX_SRFModeAll_NZ = 0x1, } TVX_SRF_MODE_ALL; typedef enum TVX_TYPE { TVX_Type_InvalidTextureResource = 0x0, TVX_Type_InvalidVertexBuffer = 0x1, TVX_Type_ValidTextureResource = 0x2, TVX_Type_ValidVertexBuffer = 0x3, } TVX_TYPE; typedef enum TC_OP_MASKS { TC_OP_MASK_FLUSH_DENROM = 0x8, TC_OP_MASK_64 = 0x20, TC_OP_MASK_NO_RTN = 0x40, } TC_OP_MASKS; typedef enum TC_OP { TC_OP_READ = 0x0, TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x1, TC_OP_ATOMIC_FMIN_RTN_32 = 0x2, TC_OP_ATOMIC_FMAX_RTN_32 = 0x3, TC_OP_RESERVED_FOP_RTN_32_0 = 0x4, TC_OP_RESERVED_FOP_RTN_32_1 = 0x5, TC_OP_RESERVED_FOP_RTN_32_2 = 0x6, TC_OP_ATOMIC_SWAP_RTN_32 = 0x7, TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x8, TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x9, TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0xa, TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0xb, TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0 = 0xc, TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0xd, TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0xe, TC_OP_ATOMIC_ADD_RTN_32 = 0xf, TC_OP_ATOMIC_SUB_RTN_32 = 0x10, TC_OP_ATOMIC_SMIN_RTN_32 = 0x11, TC_OP_ATOMIC_UMIN_RTN_32 = 0x12, TC_OP_ATOMIC_SMAX_RTN_32 = 0x13, TC_OP_ATOMIC_UMAX_RTN_32 = 0x14, TC_OP_ATOMIC_AND_RTN_32 = 0x15, TC_OP_ATOMIC_OR_RTN_32 = 0x16, TC_OP_ATOMIC_XOR_RTN_32 = 0x17, TC_OP_ATOMIC_INC_RTN_32 = 0x18, TC_OP_ATOMIC_DEC_RTN_32 = 0x19, TC_OP_WBINVL1_VOL = 0x1a, TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x1b, TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x1c, TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x1d, TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x1e, TC_OP_RESERVED_NON_FLOAT_RTN_32_4 = 0x1f, TC_OP_WRITE = 0x20, TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x21, TC_OP_ATOMIC_FMIN_RTN_64 = 0x22, TC_OP_ATOMIC_FMAX_RTN_64 = 0x23, TC_OP_RESERVED_FOP_RTN_64_0 = 0x24, TC_OP_RESERVED_FOP_RTN_64_1 = 0x25, TC_OP_RESERVED_FOP_RTN_64_2 = 0x26, TC_OP_ATOMIC_SWAP_RTN_64 = 0x27, TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x28, TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x29, TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x2a, TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x2b, TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x2c, TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x2d, TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_2 = 0x2e, TC_OP_ATOMIC_ADD_RTN_64 = 0x2f, TC_OP_ATOMIC_SUB_RTN_64 = 0x30, TC_OP_ATOMIC_SMIN_RTN_64 = 0x31, TC_OP_ATOMIC_UMIN_RTN_64 = 0x32, TC_OP_ATOMIC_SMAX_RTN_64 = 0x33, TC_OP_ATOMIC_UMAX_RTN_64 = 0x34, TC_OP_ATOMIC_AND_RTN_64 = 0x35, TC_OP_ATOMIC_OR_RTN_64 = 0x36, TC_OP_ATOMIC_XOR_RTN_64 = 0x37, TC_OP_ATOMIC_INC_RTN_64 = 0x38, TC_OP_ATOMIC_DEC_RTN_64 = 0x39, TC_OP_WBL2_VOL = 0x3a, TC_OP_RESERVED_NON_FLOAT_RTN_64_0 = 0x3b, TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x3c, TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x3d, TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x3e, TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x3f, TC_OP_WBINVL1 = 0x40, TC_OP_ATOMIC_FCMPSWAP_32 = 0x41, TC_OP_ATOMIC_FMIN_32 = 0x42, TC_OP_ATOMIC_FMAX_32 = 0x43, TC_OP_RESERVED_FOP_32_0 = 0x44, TC_OP_RESERVED_FOP_32_1 = 0x45, TC_OP_RESERVED_FOP_32_2 = 0x46, TC_OP_ATOMIC_SWAP_32 = 0x47, TC_OP_ATOMIC_CMPSWAP_32 = 0x48, TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x49, TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x4a, TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x4b, TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0 = 0x4c, TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x4d, TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x4e, TC_OP_ATOMIC_ADD_32 = 0x4f, TC_OP_ATOMIC_SUB_32 = 0x50, TC_OP_ATOMIC_SMIN_32 = 0x51, TC_OP_ATOMIC_UMIN_32 = 0x52, TC_OP_ATOMIC_SMAX_32 = 0x53, TC_OP_ATOMIC_UMAX_32 = 0x54, TC_OP_ATOMIC_AND_32 = 0x55, TC_OP_ATOMIC_OR_32 = 0x56, TC_OP_ATOMIC_XOR_32 = 0x57, TC_OP_ATOMIC_INC_32 = 0x58, TC_OP_ATOMIC_DEC_32 = 0x59, TC_OP_INVL2_VOL = 0x5a, TC_OP_RESERVED_NON_FLOAT_32_0 = 0x5b, TC_OP_RESERVED_NON_FLOAT_32_1 = 0x5c, TC_OP_RESERVED_NON_FLOAT_32_2 = 0x5d, TC_OP_RESERVED_NON_FLOAT_32_3 = 0x5e, TC_OP_RESERVED_NON_FLOAT_32_4 = 0x5f, TC_OP_WBINVL2 = 0x60, TC_OP_ATOMIC_FCMPSWAP_64 = 0x61, TC_OP_ATOMIC_FMIN_64 = 0x62, TC_OP_ATOMIC_FMAX_64 = 0x63, TC_OP_RESERVED_FOP_64_0 = 0x64, TC_OP_RESERVED_FOP_64_1 = 0x65, TC_OP_RESERVED_FOP_64_2 = 0x66, TC_OP_ATOMIC_SWAP_64 = 0x67, TC_OP_ATOMIC_CMPSWAP_64 = 0x68, TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x69, TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x6a, TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x6b, TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x6c, TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x6d, TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x6e, TC_OP_ATOMIC_ADD_64 = 0x6f, TC_OP_ATOMIC_SUB_64 = 0x70, TC_OP_ATOMIC_SMIN_64 = 0x71, TC_OP_ATOMIC_UMIN_64 = 0x72, TC_OP_ATOMIC_SMAX_64 = 0x73, TC_OP_ATOMIC_UMAX_64 = 0x74, TC_OP_ATOMIC_AND_64 = 0x75, TC_OP_ATOMIC_OR_64 = 0x76, TC_OP_ATOMIC_XOR_64 = 0x77, TC_OP_ATOMIC_INC_64 = 0x78, TC_OP_ATOMIC_DEC_64 = 0x79, TC_OP_INVL1L2_VOL = 0x7a, TC_OP_RESERVED_NON_FLOAT_64_0 = 0x7b, TC_OP_RESERVED_NON_FLOAT_64_1 = 0x7c, TC_OP_RESERVED_NON_FLOAT_64_2 = 0x7d, TC_OP_RESERVED_NON_FLOAT_64_3 = 0x7e, TC_OP_RESERVED_NON_FLOAT_64_4 = 0x7f, } TC_OP; typedef enum TC_CHUB_REQ_CREDITS_ENUM { TC_CHUB_REQ_CREDITS = 0x10, } TC_CHUB_REQ_CREDITS_ENUM; typedef enum CHUB_TC_RET_CREDITS_ENUM { CHUB_TC_RET_CREDITS = 0x20, } CHUB_TC_RET_CREDITS_ENUM; typedef enum TC_NACKS { TC_NACK_NO_FAULT = 0x0, TC_NACK_PAGE_FAULT = 0x1, TC_NACK_PROTECTION_FAULT = 0x2, TC_NACK_DATA_ERROR = 0x3, } TC_NACKS; typedef enum TCC_PERF_SEL { TCC_PERF_SEL_NONE = 0x0, TCC_PERF_SEL_CYCLE = 0x1, TCC_PERF_SEL_BUSY = 0x2, TCC_PERF_SEL_REQ = 0x3, TCC_PERF_SEL_STREAMING_REQ = 0x4, TCC_PERF_SEL_READ = 0x5, TCC_PERF_SEL_WRITE = 0x6, TCC_PERF_SEL_ATOMIC = 0x7, TCC_PERF_SEL_WBINVL2 = 0x8, TCC_PERF_SEL_WBINVL2_CYCLE = 0x9, TCC_PERF_SEL_HIT = 0xa, TCC_PERF_SEL_MISS = 0xb, TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0xc, TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0xd, TCC_PERF_SEL_WRITEBACK = 0xe, TCC_PERF_SEL_LATENCY_FIFO_FULL = 0xf, TCC_PERF_SEL_SRC_FIFO_FULL = 0x10, TCC_PERF_SEL_HOLE_FIFO_FULL = 0x11, TCC_PERF_SEL_MC_WRREQ = 0x12, TCC_PERF_SEL_MC_WRREQ_STALL = 0x13, TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL = 0x14, TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL = 0x15, TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL = 0x16, TCC_PERF_SEL_MC_WRREQ_LEVEL = 0x17, TCC_PERF_SEL_MC_RDREQ = 0x18, TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL = 0x19, TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL = 0x1a, TCC_PERF_SEL_MC_RDREQ_LEVEL = 0x1b, TCC_PERF_SEL_TAG_STALL = 0x1c, TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL = 0x1d, TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x1e, TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x1f, TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x20, TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x21, TCC_PERF_SEL_BUBBLE = 0x22, TCC_PERF_SEL_RETURN_ACK = 0x23, TCC_PERF_SEL_RETURN_DATA = 0x24, TCC_PERF_SEL_RETURN_HOLE = 0x25, TCC_PERF_SEL_RETURN_ACK_HOLE = 0x26, TCC_PERF_SEL_IB_STALL = 0x27, TCC_PERF_SEL_TCA_LEVEL = 0x28, TCC_PERF_SEL_HOLE_LEVEL = 0x29, TCC_PERF_SEL_MC_RDRET_NACK = 0x2a, TCC_PERF_SEL_MC_WRRET_NACK = 0x2b, TCC_PERF_SEL_EXE_REQ = 0x2c, TCC_PERF_SEL_CLIENT0_REQ = 0x40, TCC_PERF_SEL_CLIENT1_REQ = 0x41, TCC_PERF_SEL_CLIENT2_REQ = 0x42, TCC_PERF_SEL_CLIENT3_REQ = 0x43, TCC_PERF_SEL_CLIENT4_REQ = 0x44, TCC_PERF_SEL_CLIENT5_REQ = 0x45, TCC_PERF_SEL_CLIENT6_REQ = 0x46, TCC_PERF_SEL_CLIENT7_REQ = 0x47, TCC_PERF_SEL_CLIENT8_REQ = 0x48, TCC_PERF_SEL_CLIENT9_REQ = 0x49, TCC_PERF_SEL_CLIENT10_REQ = 0x4a, TCC_PERF_SEL_CLIENT11_REQ = 0x4b, TCC_PERF_SEL_CLIENT12_REQ = 0x4c, TCC_PERF_SEL_CLIENT13_REQ = 0x4d, TCC_PERF_SEL_CLIENT14_REQ = 0x4e, TCC_PERF_SEL_CLIENT15_REQ = 0x4f, TCC_PERF_SEL_CLIENT16_REQ = 0x50, TCC_PERF_SEL_CLIENT17_REQ = 0x51, TCC_PERF_SEL_CLIENT18_REQ = 0x52, TCC_PERF_SEL_CLIENT19_REQ = 0x53, TCC_PERF_SEL_CLIENT20_REQ = 0x54, TCC_PERF_SEL_CLIENT21_REQ = 0x55, TCC_PERF_SEL_CLIENT22_REQ = 0x56, TCC_PERF_SEL_CLIENT23_REQ = 0x57, TCC_PERF_SEL_CLIENT24_REQ = 0x58, TCC_PERF_SEL_CLIENT25_REQ = 0x59, TCC_PERF_SEL_CLIENT26_REQ = 0x5a, TCC_PERF_SEL_CLIENT27_REQ = 0x5b, TCC_PERF_SEL_CLIENT28_REQ = 0x5c, TCC_PERF_SEL_CLIENT29_REQ = 0x5d, TCC_PERF_SEL_CLIENT30_REQ = 0x5e, TCC_PERF_SEL_CLIENT31_REQ = 0x5f, TCC_PERF_SEL_CLIENT32_REQ = 0x60, TCC_PERF_SEL_CLIENT33_REQ = 0x61, TCC_PERF_SEL_CLIENT34_REQ = 0x62, TCC_PERF_SEL_CLIENT35_REQ = 0x63, TCC_PERF_SEL_CLIENT36_REQ = 0x64, TCC_PERF_SEL_CLIENT37_REQ = 0x65, TCC_PERF_SEL_CLIENT38_REQ = 0x66, TCC_PERF_SEL_CLIENT39_REQ = 0x67, TCC_PERF_SEL_CLIENT40_REQ = 0x68, TCC_PERF_SEL_CLIENT41_REQ = 0x69, TCC_PERF_SEL_CLIENT42_REQ = 0x6a, TCC_PERF_SEL_CLIENT43_REQ = 0x6b, TCC_PERF_SEL_CLIENT44_REQ = 0x6c, TCC_PERF_SEL_CLIENT45_REQ = 0x6d, TCC_PERF_SEL_CLIENT46_REQ = 0x6e, TCC_PERF_SEL_CLIENT47_REQ = 0x6f, TCC_PERF_SEL_CLIENT48_REQ = 0x70, TCC_PERF_SEL_CLIENT49_REQ = 0x71, TCC_PERF_SEL_CLIENT50_REQ = 0x72, TCC_PERF_SEL_CLIENT51_REQ = 0x73, TCC_PERF_SEL_CLIENT52_REQ = 0x74, TCC_PERF_SEL_CLIENT53_REQ = 0x75, TCC_PERF_SEL_CLIENT54_REQ = 0x76, TCC_PERF_SEL_CLIENT55_REQ = 0x77, TCC_PERF_SEL_CLIENT56_REQ = 0x78, TCC_PERF_SEL_CLIENT57_REQ = 0x79, TCC_PERF_SEL_CLIENT58_REQ = 0x7a, TCC_PERF_SEL_CLIENT59_REQ = 0x7b, TCC_PERF_SEL_CLIENT60_REQ = 0x7c, TCC_PERF_SEL_CLIENT61_REQ = 0x7d, TCC_PERF_SEL_CLIENT62_REQ = 0x7e, TCC_PERF_SEL_CLIENT63_REQ = 0x7f, TCC_PERF_SEL_NORMAL_WRITEBACK = 0x80, TCC_PERF_SEL_TC_OP_WBL2_VOL_WRITEBACK = 0x81, TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x82, TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x83, TCC_PERF_SEL_NORMAL_EVICT = 0x84, TCC_PERF_SEL_TC_OP_INVL2_VOL_EVICT = 0x85, TCC_PERF_SEL_TC_OP_INVL1L2_VOL_EVICT = 0x86, TCC_PERF_SEL_TC_OP_WBL2_VOL_EVICT = 0x87, TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x88, TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x89, TCC_PERF_SEL_ALL_TC_OP_INV_VOL_EVICT = 0x8a, TCC_PERF_SEL_TC_OP_WBL2_VOL_CYCLE = 0x8b, TCC_PERF_SEL_TC_OP_INVL2_VOL_CYCLE = 0x8c, TCC_PERF_SEL_TC_OP_INVL1L2_VOL_CYCLE = 0x8d, TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x8e, TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x8f, TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_CYCLE = 0x90, TCC_PERF_SEL_TC_OP_WBL2_VOL_START = 0x91, TCC_PERF_SEL_TC_OP_INVL2_VOL_START = 0x92, TCC_PERF_SEL_TC_OP_INVL1L2_VOL_START = 0x93, TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x94, TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x95, TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 0x96, TCC_PERF_SEL_TC_OP_WBL2_VOL_FINISH = 0x97, TCC_PERF_SEL_TC_OP_INVL2_VOL_FINISH = 0x98, TCC_PERF_SEL_TC_OP_INVL1L2_VOL_FINISH = 0x99, TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x9a, TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x9b, TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_FINISH = 0x9c, TCC_PERF_SEL_VOL_MC_WRREQ = 0x9d, TCC_PERF_SEL_VOL_MC_RDREQ = 0x9e, TCC_PERF_SEL_VOL_REQ = 0x9f, } TCC_PERF_SEL; typedef enum TCA_PERF_SEL { TCA_PERF_SEL_NONE = 0x0, TCA_PERF_SEL_CYCLE = 0x1, TCA_PERF_SEL_BUSY = 0x2, TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x3, TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x4, TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x5, TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x6, TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x7, TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x8, TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x9, TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0xa, TCA_PERF_SEL_REQ_TCC0 = 0xb, TCA_PERF_SEL_REQ_TCC1 = 0xc, TCA_PERF_SEL_REQ_TCC2 = 0xd, TCA_PERF_SEL_REQ_TCC3 = 0xe, TCA_PERF_SEL_REQ_TCC4 = 0xf, TCA_PERF_SEL_REQ_TCC5 = 0x10, TCA_PERF_SEL_REQ_TCC6 = 0x11, TCA_PERF_SEL_REQ_TCC7 = 0x12, TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x13, TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x14, TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x15, TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x16, TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x17, TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x18, TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x19, TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x1a, TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x1b, TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x1c, TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x1d, TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x1e, TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x1f, TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x20, TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x21, TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x22, TCA_PERF_SEL_FORCED_HOLE_TCS = 0x23, TCA_PERF_SEL_REQ_TCS = 0x24, TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCS = 0x25, TCA_PERF_SEL_CROSSBAR_STALL_TCS = 0x26, } TCA_PERF_SEL; typedef enum TCS_PERF_SEL { TCS_PERF_SEL_NONE = 0x0, TCS_PERF_SEL_CYCLE = 0x1, TCS_PERF_SEL_BUSY = 0x2, TCS_PERF_SEL_REQ = 0x3, TCS_PERF_SEL_READ = 0x4, TCS_PERF_SEL_WRITE = 0x5, TCS_PERF_SEL_ATOMIC = 0x6, TCS_PERF_SEL_HOLE_FIFO_FULL = 0x7, TCS_PERF_SEL_REQ_FIFO_FULL = 0x8, TCS_PERF_SEL_REQ_CREDIT_STALL = 0x9, TCS_PERF_SEL_REQ_NO_SRC_DATA_STALL = 0xa, TCS_PERF_SEL_REQ_STALL = 0xb, TCS_PERF_SEL_TCS_CHUB_REQ_SEND = 0xc, TCS_PERF_SEL_CHUB_TCS_RET_SEND = 0xd, TCS_PERF_SEL_RETURN_ACK = 0xe, TCS_PERF_SEL_RETURN_DATA = 0xf, TCS_PERF_SEL_IB_TOTAL_REQUESTS_STALL = 0x10, TCS_PERF_SEL_IB_STALL = 0x11, TCS_PERF_SEL_TCA_LEVEL = 0x12, TCS_PERF_SEL_HOLE_LEVEL = 0x13, TCS_PERF_SEL_CHUB_LEVEL = 0x14, TCS_PERF_SEL_CLIENT0_REQ = 0x40, TCS_PERF_SEL_CLIENT1_REQ = 0x41, TCS_PERF_SEL_CLIENT2_REQ = 0x42, TCS_PERF_SEL_CLIENT3_REQ = 0x43, TCS_PERF_SEL_CLIENT4_REQ = 0x44, TCS_PERF_SEL_CLIENT5_REQ = 0x45, TCS_PERF_SEL_CLIENT6_REQ = 0x46, TCS_PERF_SEL_CLIENT7_REQ = 0x47, TCS_PERF_SEL_CLIENT8_REQ = 0x48, TCS_PERF_SEL_CLIENT9_REQ = 0x49, TCS_PERF_SEL_CLIENT10_REQ = 0x4a, TCS_PERF_SEL_CLIENT11_REQ = 0x4b, TCS_PERF_SEL_CLIENT12_REQ = 0x4c, TCS_PERF_SEL_CLIENT13_REQ = 0x4d, TCS_PERF_SEL_CLIENT14_REQ = 0x4e, TCS_PERF_SEL_CLIENT15_REQ = 0x4f, TCS_PERF_SEL_CLIENT16_REQ = 0x50, TCS_PERF_SEL_CLIENT17_REQ = 0x51, TCS_PERF_SEL_CLIENT18_REQ = 0x52, TCS_PERF_SEL_CLIENT19_REQ = 0x53, TCS_PERF_SEL_CLIENT20_REQ = 0x54, TCS_PERF_SEL_CLIENT21_REQ = 0x55, TCS_PERF_SEL_CLIENT22_REQ = 0x56, TCS_PERF_SEL_CLIENT23_REQ = 0x57, TCS_PERF_SEL_CLIENT24_REQ = 0x58, TCS_PERF_SEL_CLIENT25_REQ = 0x59, TCS_PERF_SEL_CLIENT26_REQ = 0x5a, TCS_PERF_SEL_CLIENT27_REQ = 0x5b, TCS_PERF_SEL_CLIENT28_REQ = 0x5c, TCS_PERF_SEL_CLIENT29_REQ = 0x5d, TCS_PERF_SEL_CLIENT30_REQ = 0x5e, TCS_PERF_SEL_CLIENT31_REQ = 0x5f, TCS_PERF_SEL_CLIENT32_REQ = 0x60, TCS_PERF_SEL_CLIENT33_REQ = 0x61, TCS_PERF_SEL_CLIENT34_REQ = 0x62, TCS_PERF_SEL_CLIENT35_REQ = 0x63, TCS_PERF_SEL_CLIENT36_REQ = 0x64, TCS_PERF_SEL_CLIENT37_REQ = 0x65, TCS_PERF_SEL_CLIENT38_REQ = 0x66, TCS_PERF_SEL_CLIENT39_REQ = 0x67, TCS_PERF_SEL_CLIENT40_REQ = 0x68, TCS_PERF_SEL_CLIENT41_REQ = 0x69, TCS_PERF_SEL_CLIENT42_REQ = 0x6a, TCS_PERF_SEL_CLIENT43_REQ = 0x6b, TCS_PERF_SEL_CLIENT44_REQ = 0x6c, TCS_PERF_SEL_CLIENT45_REQ = 0x6d, TCS_PERF_SEL_CLIENT46_REQ = 0x6e, TCS_PERF_SEL_CLIENT47_REQ = 0x6f, TCS_PERF_SEL_CLIENT48_REQ = 0x70, TCS_PERF_SEL_CLIENT49_REQ = 0x71, TCS_PERF_SEL_CLIENT50_REQ = 0x72, TCS_PERF_SEL_CLIENT51_REQ = 0x73, TCS_PERF_SEL_CLIENT52_REQ = 0x74, TCS_PERF_SEL_CLIENT53_REQ = 0x75, TCS_PERF_SEL_CLIENT54_REQ = 0x76, TCS_PERF_SEL_CLIENT55_REQ = 0x77, TCS_PERF_SEL_CLIENT56_REQ = 0x78, TCS_PERF_SEL_CLIENT57_REQ = 0x79, TCS_PERF_SEL_CLIENT58_REQ = 0x7a, TCS_PERF_SEL_CLIENT59_REQ = 0x7b, TCS_PERF_SEL_CLIENT60_REQ = 0x7c, TCS_PERF_SEL_CLIENT61_REQ = 0x7d, TCS_PERF_SEL_CLIENT62_REQ = 0x7e, TCS_PERF_SEL_CLIENT63_REQ = 0x7f, } TCS_PERF_SEL; typedef enum TA_TC_ADDR_MODES { TA_TC_ADDR_MODE_DEFAULT = 0x0, TA_TC_ADDR_MODE_COMP0 = 0x1, TA_TC_ADDR_MODE_COMP1 = 0x2, TA_TC_ADDR_MODE_COMP2 = 0x3, TA_TC_ADDR_MODE_COMP3 = 0x4, TA_TC_ADDR_MODE_UNALIGNED = 0x5, TA_TC_ADDR_MODE_BORDER_COLOR = 0x6, } TA_TC_ADDR_MODES; typedef enum TA_PERFCOUNT_SEL { TA_PERF_SEL_ta_busy = 0x0, TA_PERF_SEL_sh_fifo_busy = 0x1, TA_PERF_SEL_sh_fifo_cmd_busy = 0x2, TA_PERF_SEL_sh_fifo_addr_busy = 0x3, TA_PERF_SEL_sh_fifo_data_busy = 0x4, TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x5, TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x6, TA_PERF_SEL_gradient_busy = 0x7, TA_PERF_SEL_gradient_fifo_busy = 0x8, TA_PERF_SEL_lod_busy = 0x9, TA_PERF_SEL_lod_fifo_busy = 0xa, TA_PERF_SEL_addresser_busy = 0xb, TA_PERF_SEL_addresser_fifo_busy = 0xc, TA_PERF_SEL_aligner_busy = 0xd, TA_PERF_SEL_write_path_busy = 0xe, TA_PERF_SEL_RESERVED_15 = 0xf, TA_PERF_SEL_sq_ta_cmd_cycles = 0x10, TA_PERF_SEL_sp_ta_addr_cycles = 0x11, TA_PERF_SEL_sp_ta_data_cycles = 0x12, TA_PERF_SEL_ta_fa_data_state_cycles = 0x13, TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x14, TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x15, TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16, TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17, TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18, TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19, TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a, TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b, TA_PERF_SEL_RESERVED_28 = 0x1c, TA_PERF_SEL_RESERVED_29 = 0x1d, TA_PERF_SEL_sh_fifo_addr_cycles = 0x1e, TA_PERF_SEL_sh_fifo_data_cycles = 0x1f, TA_PERF_SEL_total_wavefronts = 0x20, TA_PERF_SEL_gradient_cycles = 0x21, TA_PERF_SEL_walker_cycles = 0x22, TA_PERF_SEL_aligner_cycles = 0x23, TA_PERF_SEL_image_wavefronts = 0x24, TA_PERF_SEL_image_read_wavefronts = 0x25, TA_PERF_SEL_image_write_wavefronts = 0x26, TA_PERF_SEL_image_atomic_wavefronts = 0x27, TA_PERF_SEL_image_total_cycles = 0x28, TA_PERF_SEL_RESERVED_41 = 0x29, TA_PERF_SEL_RESERVED_42 = 0x2a, TA_PERF_SEL_RESERVED_43 = 0x2b, TA_PERF_SEL_buffer_wavefronts = 0x2c, TA_PERF_SEL_buffer_read_wavefronts = 0x2d, TA_PERF_SEL_buffer_write_wavefronts = 0x2e, TA_PERF_SEL_buffer_atomic_wavefronts = 0x2f, TA_PERF_SEL_buffer_coalescable_wavefronts = 0x30, TA_PERF_SEL_buffer_total_cycles = 0x31, TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32, TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33, TA_PERF_SEL_buffer_coalesced_read_cycles = 0x34, TA_PERF_SEL_buffer_coalesced_write_cycles = 0x35, TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x36, TA_PERF_SEL_addr_stalled_by_td_cycles = 0x37, TA_PERF_SEL_data_stalled_by_tc_cycles = 0x38, TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39, TA_PERF_SEL_addresser_stalled_cycles = 0x3a, TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b, TA_PERF_SEL_aniso_stalled_cycles = 0x3c, TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x3d, TA_PERF_SEL_deriv_stalled_cycles = 0x3e, TA_PERF_SEL_aniso_gt1_cycle_quads = 0x3f, TA_PERF_SEL_color_1_cycle_pixels = 0x40, TA_PERF_SEL_color_2_cycle_pixels = 0x41, TA_PERF_SEL_color_3_cycle_pixels = 0x42, TA_PERF_SEL_color_4_cycle_pixels = 0x43, TA_PERF_SEL_mip_1_cycle_pixels = 0x44, TA_PERF_SEL_mip_2_cycle_pixels = 0x45, TA_PERF_SEL_vol_1_cycle_pixels = 0x46, TA_PERF_SEL_vol_2_cycle_pixels = 0x47, TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x48, TA_PERF_SEL_mipmap_lod_0_samples = 0x49, TA_PERF_SEL_mipmap_lod_1_samples = 0x4a, TA_PERF_SEL_mipmap_lod_2_samples = 0x4b, TA_PERF_SEL_mipmap_lod_3_samples = 0x4c, TA_PERF_SEL_mipmap_lod_4_samples = 0x4d, TA_PERF_SEL_mipmap_lod_5_samples = 0x4e, TA_PERF_SEL_mipmap_lod_6_samples = 0x4f, TA_PERF_SEL_mipmap_lod_7_samples = 0x50, TA_PERF_SEL_mipmap_lod_8_samples = 0x51, TA_PERF_SEL_mipmap_lod_9_samples = 0x52, TA_PERF_SEL_mipmap_lod_10_samples = 0x53, TA_PERF_SEL_mipmap_lod_11_samples = 0x54, TA_PERF_SEL_mipmap_lod_12_samples = 0x55, TA_PERF_SEL_mipmap_lod_13_samples = 0x56, TA_PERF_SEL_mipmap_lod_14_samples = 0x57, TA_PERF_SEL_mipmap_invalid_samples = 0x58, TA_PERF_SEL_aniso_1_cycle_quads = 0x59, TA_PERF_SEL_aniso_2_cycle_quads = 0x5a, TA_PERF_SEL_aniso_4_cycle_quads = 0x5b, TA_PERF_SEL_aniso_6_cycle_quads = 0x5c, TA_PERF_SEL_aniso_8_cycle_quads = 0x5d, TA_PERF_SEL_aniso_10_cycle_quads = 0x5e, TA_PERF_SEL_aniso_12_cycle_quads = 0x5f, TA_PERF_SEL_aniso_14_cycle_quads = 0x60, TA_PERF_SEL_aniso_16_cycle_quads = 0x61, TA_PERF_SEL_write_path_input_cycles = 0x62, TA_PERF_SEL_write_path_output_cycles = 0x63, TA_PERF_SEL_flat_wavefronts = 0x64, TA_PERF_SEL_flat_read_wavefronts = 0x65, TA_PERF_SEL_flat_write_wavefronts = 0x66, TA_PERF_SEL_flat_atomic_wavefronts = 0x67, TA_PERF_SEL_flat_coalesceable_wavefronts = 0x68, TA_PERF_SEL_reg_sclk_vld = 0x69, TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6a, TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x6b, TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x6c, TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x6d, TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x6e, } TA_PERFCOUNT_SEL; typedef enum TD_PERFCOUNT_SEL { TD_PERF_SEL_td_busy = 0x0, TD_PERF_SEL_input_busy = 0x1, TD_PERF_SEL_output_busy = 0x2, TD_PERF_SEL_lerp_busy = 0x3, TD_PERF_SEL_RESERVED_4 = 0x4, TD_PERF_SEL_reg_sclk_vld = 0x5, TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6, TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x7, TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x8, TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x9, TD_PERF_SEL_tc_td_fifo_full = 0xa, TD_PERF_SEL_constant_state_full = 0xb, TD_PERF_SEL_sample_state_full = 0xc, TD_PERF_SEL_output_fifo_full = 0xd, TD_PERF_SEL_RESERVED_14 = 0xe, TD_PERF_SEL_tc_stall = 0xf, TD_PERF_SEL_pc_stall = 0x10, TD_PERF_SEL_gds_stall = 0x11, TD_PERF_SEL_RESERVED_18 = 0x12, TD_PERF_SEL_RESERVED_19 = 0x13, TD_PERF_SEL_gather4_wavefront = 0x14, TD_PERF_SEL_sample_c_wavefront = 0x15, TD_PERF_SEL_load_wavefront = 0x16, TD_PERF_SEL_atomic_wavefront = 0x17, TD_PERF_SEL_store_wavefront = 0x18, TD_PERF_SEL_ldfptr_wavefront = 0x19, TD_PERF_SEL_RESERVED_26 = 0x1a, TD_PERF_SEL_RESERVED_27 = 0x1b, TD_PERF_SEL_RESERVED_28 = 0x1c, TD_PERF_SEL_RESERVED_29 = 0x1d, TD_PERF_SEL_bypass_filter_wavefront = 0x1e, TD_PERF_SEL_min_max_filter_wavefront = 0x1f, TD_PERF_SEL_coalescable_wavefront = 0x20, TD_PERF_SEL_coalesced_phase = 0x21, TD_PERF_SEL_four_phase_wavefront = 0x22, TD_PERF_SEL_eight_phase_wavefront = 0x23, TD_PERF_SEL_sixteen_phase_wavefront = 0x24, TD_PERF_SEL_four_phase_forward_wavefront = 0x25, TD_PERF_SEL_write_ack_wavefront = 0x26, TD_PERF_SEL_RESERVED_39 = 0x27, TD_PERF_SEL_user_defined_border = 0x28, TD_PERF_SEL_white_border = 0x29, TD_PERF_SEL_opaque_black_border = 0x2a, TD_PERF_SEL_RESERVED_43 = 0x2b, TD_PERF_SEL_RESERVED_44 = 0x2c, TD_PERF_SEL_nack = 0x2d, TD_PERF_SEL_td_sp_traffic = 0x2e, TD_PERF_SEL_consume_gds_traffic = 0x2f, TD_PERF_SEL_addresscmd_poison = 0x30, TD_PERF_SEL_data_poison = 0x31, TD_PERF_SEL_start_cycle_0 = 0x32, TD_PERF_SEL_start_cycle_1 = 0x33, TD_PERF_SEL_start_cycle_2 = 0x34, TD_PERF_SEL_start_cycle_3 = 0x35, TD_PERF_SEL_null_cycle_output = 0x36, } TD_PERFCOUNT_SEL; typedef enum TCP_PERFCOUNT_SELECT { TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x0, TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x1, TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x2, TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x3, TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x4, TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x5, TCP_PERF_SEL_LOD_STALL_CYCLES = 0x6, TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x7, TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x8, TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x9, TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0xa, TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0xb, TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0xc, TCP_PERF_SEL_TCR_RDRET_STALL = 0xd, TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0xe, TCP_PERF_SEL_HOLE_READ_STALL = 0xf, TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x10, TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x11, TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x12, TCP_PERF_SEL_TCP_LATENCY = 0x13, TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x14, TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x15, TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x16, TCP_PERF_SEL_TCC_READ_REQ = 0x17, TCP_PERF_SEL_TCC_WRITE_REQ = 0x18, TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x19, TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x1a, TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x1b, TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x1c, TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x1d, TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x1e, TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x1f, TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x20, TCP_PERF_SEL_TOTAL_WBINVL1 = 0x21, TCP_PERF_SEL_IMG_READ_FMT_1 = 0x22, TCP_PERF_SEL_IMG_READ_FMT_8 = 0x23, TCP_PERF_SEL_IMG_READ_FMT_16 = 0x24, TCP_PERF_SEL_IMG_READ_FMT_32 = 0x25, TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x26, TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x27, TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x28, TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x29, TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x2a, TCP_PERF_SEL_IMG_READ_FMT_96 = 0x2b, TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x2c, TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x2d, TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x2e, TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x2f, TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x30, TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x31, TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x32, TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x33, TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x34, TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x35, TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x36, TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x37, TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x38, TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x39, TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x3a, TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x3b, TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x3c, TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x3d, TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x3e, TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x3f, TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x40, TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x41, TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x42, TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x43, TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x44, TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x45, TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x46, TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x47, TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x48, TCP_PERF_SEL_BUF_READ_FMT_8 = 0x49, TCP_PERF_SEL_BUF_READ_FMT_16 = 0x4a, TCP_PERF_SEL_BUF_READ_FMT_32 = 0x4b, TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x4c, TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x4d, TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x4e, TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x4f, TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x50, TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x51, TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x52, TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x53, TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x54, TCP_PERF_SEL_ARR_1D_THIN1 = 0x55, TCP_PERF_SEL_ARR_1D_THICK = 0x56, TCP_PERF_SEL_ARR_2D_THIN1 = 0x57, TCP_PERF_SEL_ARR_2D_THICK = 0x58, TCP_PERF_SEL_ARR_2D_XTHICK = 0x59, TCP_PERF_SEL_ARR_3D_THIN1 = 0x5a, TCP_PERF_SEL_ARR_3D_THICK = 0x5b, TCP_PERF_SEL_ARR_3D_XTHICK = 0x5c, TCP_PERF_SEL_DIM_1D = 0x5d, TCP_PERF_SEL_DIM_2D = 0x5e, TCP_PERF_SEL_DIM_3D = 0x5f, TCP_PERF_SEL_DIM_1D_ARRAY = 0x60, TCP_PERF_SEL_DIM_2D_ARRAY = 0x61, TCP_PERF_SEL_DIM_2D_MSAA = 0x62, TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x63, TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x64, TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x65, TCP_PERF_SEL_TA_TCP_STATE_READ = 0x66, TCP_PERF_SEL_TAGRAM0_REQ = 0x67, TCP_PERF_SEL_TAGRAM1_REQ = 0x68, TCP_PERF_SEL_TAGRAM2_REQ = 0x69, TCP_PERF_SEL_TAGRAM3_REQ = 0x6a, TCP_PERF_SEL_GATE_EN1 = 0x6b, TCP_PERF_SEL_GATE_EN2 = 0x6c, TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x6d, TCP_PERF_SEL_TCC_REQ = 0x6e, TCP_PERF_SEL_TCC_NON_READ_REQ = 0x6f, TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x70, TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x71, TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x72, TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x73, TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x74, TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x75, TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x76, TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x77, TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x78, TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x79, TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x7a, TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x7b, TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x7c, TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x7d, TCP_PERF_SEL_TOTAL_ACCESSES = 0x7e, TCP_PERF_SEL_TOTAL_READ = 0x7f, TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x80, TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x81, TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x82, TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x83, TCP_PERF_SEL_TOTAL_NON_READ = 0x84, TCP_PERF_SEL_TOTAL_WRITE = 0x85, TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x86, TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x87, TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x88, TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x89, TCP_PERF_SEL_DISPLAY_MICROTILING = 0x8a, TCP_PERF_SEL_THIN_MICROTILING = 0x8b, TCP_PERF_SEL_DEPTH_MICROTILING = 0x8c, TCP_PERF_SEL_ARR_PRT_THIN1 = 0x8d, TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x8e, TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x8f, TCP_PERF_SEL_ARR_PRT_THICK = 0x90, TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x91, TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x92, TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x93, TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x94, TCP_PERF_SEL_UNALIGNED = 0x95, TCP_PERF_SEL_ROTATED_MICROTILING = 0x96, TCP_PERF_SEL_THICK_MICROTILING = 0x97, TCP_PERF_SEL_ATC = 0x98, TCP_PERF_SEL_POWER_STALL = 0x99, } TCP_PERFCOUNT_SELECT; typedef enum TCP_CACHE_POLICIES { TCP_CACHE_POLICY_MISS_LRU = 0x0, TCP_CACHE_POLICY_MISS_EVICT = 0x1, TCP_CACHE_POLICY_HIT_LRU = 0x2, TCP_CACHE_POLICY_HIT_EVICT = 0x3, } TCP_CACHE_POLICIES; typedef enum TCP_CACHE_STORE_POLICIES { TCP_CACHE_STORE_POLICY_MISS_LRU = 0x0, TCP_CACHE_STORE_POLICY_MISS_EVICT = 0x1, } TCP_CACHE_STORE_POLICIES; typedef enum TCP_WATCH_MODES { TCP_WATCH_MODE_READ = 0x0, TCP_WATCH_MODE_NONREAD = 0x1, TCP_WATCH_MODE_ATOMIC = 0x2, TCP_WATCH_MODE_ALL = 0x3, } TCP_WATCH_MODES; typedef enum VGT_OUT_PRIM_TYPE { VGT_OUT_POINT = 0x0, VGT_OUT_LINE = 0x1, VGT_OUT_TRI = 0x2, VGT_OUT_RECT_V0 = 0x3, VGT_OUT_RECT_V1 = 0x4, VGT_OUT_RECT_V2 = 0x5, VGT_OUT_RECT_V3 = 0x6, VGT_OUT_RESERVED = 0x7, VGT_TE_QUAD = 0x8, VGT_TE_PRIM_INDEX_LINE = 0x9, VGT_TE_PRIM_INDEX_TRI = 0xa, VGT_TE_PRIM_INDEX_QUAD = 0xb, VGT_OUT_LINE_ADJ = 0xc, VGT_OUT_TRI_ADJ = 0xd, VGT_OUT_PATCH = 0xe, } VGT_OUT_PRIM_TYPE; typedef enum VGT_DI_PRIM_TYPE { DI_PT_NONE = 0x0, DI_PT_POINTLIST = 0x1, DI_PT_LINELIST = 0x2, DI_PT_LINESTRIP = 0x3, DI_PT_TRILIST = 0x4, DI_PT_TRIFAN = 0x5, DI_PT_TRISTRIP = 0x6, DI_PT_UNUSED_0 = 0x7, DI_PT_UNUSED_1 = 0x8, DI_PT_PATCH = 0x9, DI_PT_LINELIST_ADJ = 0xa, DI_PT_LINESTRIP_ADJ = 0xb, DI_PT_TRILIST_ADJ = 0xc, DI_PT_TRISTRIP_ADJ = 0xd, DI_PT_UNUSED_3 = 0xe, DI_PT_UNUSED_4 = 0xf, DI_PT_TRI_WITH_WFLAGS = 0x10, DI_PT_RECTLIST = 0x11, DI_PT_LINELOOP = 0x12, DI_PT_QUADLIST = 0x13, DI_PT_QUADSTRIP = 0x14, DI_PT_POLYGON = 0x15, DI_PT_2D_COPY_RECT_LIST_V0 = 0x16, DI_PT_2D_COPY_RECT_LIST_V1 = 0x17, DI_PT_2D_COPY_RECT_LIST_V2 = 0x18, DI_PT_2D_COPY_RECT_LIST_V3 = 0x19, DI_PT_2D_FILL_RECT_LIST = 0x1a, DI_PT_2D_LINE_STRIP = 0x1b, DI_PT_2D_TRI_STRIP = 0x1c, } VGT_DI_PRIM_TYPE; typedef enum VGT_DI_SOURCE_SELECT { DI_SRC_SEL_DMA = 0x0, DI_SRC_SEL_IMMEDIATE = 0x1, DI_SRC_SEL_AUTO_INDEX = 0x2, DI_SRC_SEL_RESERVED = 0x3, } VGT_DI_SOURCE_SELECT; typedef enum VGT_DI_MAJOR_MODE_SELECT { DI_MAJOR_MODE_0 = 0x0, DI_MAJOR_MODE_1 = 0x1, } VGT_DI_MAJOR_MODE_SELECT; typedef enum VGT_DI_INDEX_SIZE { DI_INDEX_SIZE_16_BIT = 0x0, DI_INDEX_SIZE_32_BIT = 0x1, } VGT_DI_INDEX_SIZE; typedef enum VGT_EVENT_TYPE { Reserved_0x00 = 0x0, SAMPLE_STREAMOUTSTATS1 = 0x1, SAMPLE_STREAMOUTSTATS2 = 0x2, SAMPLE_STREAMOUTSTATS3 = 0x3, CACHE_FLUSH_TS = 0x4, CONTEXT_DONE = 0x5, CACHE_FLUSH = 0x6, CS_PARTIAL_FLUSH = 0x7, VGT_STREAMOUT_SYNC = 0x8, Reserved_0x09 = 0x9, VGT_STREAMOUT_RESET = 0xa, END_OF_PIPE_INCR_DE = 0xb, END_OF_PIPE_IB_END = 0xc, RST_PIX_CNT = 0xd, Reserved_0x0E = 0xe, VS_PARTIAL_FLUSH = 0xf, PS_PARTIAL_FLUSH = 0x10, FLUSH_HS_OUTPUT = 0x11, FLUSH_LS_OUTPUT = 0x12, Reserved_0x13 = 0x13, CACHE_FLUSH_AND_INV_TS_EVENT = 0x14, ZPASS_DONE = 0x15, CACHE_FLUSH_AND_INV_EVENT = 0x16, PERFCOUNTER_START = 0x17, PERFCOUNTER_STOP = 0x18, PIPELINESTAT_START = 0x19, PIPELINESTAT_STOP = 0x1a, PERFCOUNTER_SAMPLE = 0x1b, FLUSH_ES_OUTPUT = 0x1c, FLUSH_GS_OUTPUT = 0x1d, SAMPLE_PIPELINESTAT = 0x1e, SO_VGTSTREAMOUT_FLUSH = 0x1f, SAMPLE_STREAMOUTSTATS = 0x20, RESET_VTX_CNT = 0x21, BLOCK_CONTEXT_DONE = 0x22, CS_CONTEXT_DONE = 0x23, VGT_FLUSH = 0x24, Reserved_0x25 = 0x25, SQ_NON_EVENT = 0x26, SC_SEND_DB_VPZ = 0x27, BOTTOM_OF_PIPE_TS = 0x28, FLUSH_SX_TS = 0x29, DB_CACHE_FLUSH_AND_INV = 0x2a, FLUSH_AND_INV_DB_DATA_TS = 0x2b, FLUSH_AND_INV_DB_META = 0x2c, FLUSH_AND_INV_CB_DATA_TS = 0x2d, FLUSH_AND_INV_CB_META = 0x2e, CS_DONE = 0x2f, PS_DONE = 0x30, FLUSH_AND_INV_CB_PIXEL_DATA = 0x31, SX_CB_RAT_ACK_REQUEST = 0x32, THREAD_TRACE_START = 0x33, THREAD_TRACE_STOP = 0x34, THREAD_TRACE_MARKER = 0x35, THREAD_TRACE_FLUSH = 0x36, THREAD_TRACE_FINISH = 0x37, PIXEL_PIPE_STAT_CONTROL = 0x38, PIXEL_PIPE_STAT_DUMP = 0x39, PIXEL_PIPE_STAT_RESET = 0x3a, CONTEXT_SUSPEND = 0x3b, } VGT_EVENT_TYPE; typedef enum VGT_DMA_SWAP_MODE { VGT_DMA_SWAP_NONE = 0x0, VGT_DMA_SWAP_16_BIT = 0x1, VGT_DMA_SWAP_32_BIT = 0x2, VGT_DMA_SWAP_WORD = 0x3, } VGT_DMA_SWAP_MODE; typedef enum VGT_INDEX_TYPE_MODE { VGT_INDEX_16 = 0x0, VGT_INDEX_32 = 0x1, } VGT_INDEX_TYPE_MODE; typedef enum VGT_DMA_BUF_TYPE { VGT_DMA_BUF_MEM = 0x0, VGT_DMA_BUF_RING = 0x1, VGT_DMA_BUF_SETUP = 0x2, } VGT_DMA_BUF_TYPE; typedef enum VGT_OUTPATH_SELECT { VGT_OUTPATH_VTX_REUSE = 0x0, VGT_OUTPATH_TESS_EN = 0x1, VGT_OUTPATH_PASSTHRU = 0x2, VGT_OUTPATH_GS_BLOCK = 0x3, VGT_OUTPATH_HS_BLOCK = 0x4, } VGT_OUTPATH_SELECT; typedef enum VGT_GRP_PRIM_TYPE { VGT_GRP_3D_POINT = 0x0, VGT_GRP_3D_LINE = 0x1, VGT_GRP_3D_TRI = 0x2, VGT_GRP_3D_RECT = 0x3, VGT_GRP_3D_QUAD = 0x4, VGT_GRP_2D_COPY_RECT_V0 = 0x5, VGT_GRP_2D_COPY_RECT_V1 = 0x6, VGT_GRP_2D_COPY_RECT_V2 = 0x7, VGT_GRP_2D_COPY_RECT_V3 = 0x8, VGT_GRP_2D_FILL_RECT = 0x9, VGT_GRP_2D_LINE = 0xa, VGT_GRP_2D_TRI = 0xb, VGT_GRP_PRIM_INDEX_LINE = 0xc, VGT_GRP_PRIM_INDEX_TRI = 0xd, VGT_GRP_PRIM_INDEX_QUAD = 0xe, VGT_GRP_3D_LINE_ADJ = 0xf, VGT_GRP_3D_TRI_ADJ = 0x10, VGT_GRP_3D_PATCH = 0x11, } VGT_GRP_PRIM_TYPE; typedef enum VGT_GRP_PRIM_ORDER { VGT_GRP_LIST = 0x0, VGT_GRP_STRIP = 0x1, VGT_GRP_FAN = 0x2, VGT_GRP_LOOP = 0x3, VGT_GRP_POLYGON = 0x4, } VGT_GRP_PRIM_ORDER; typedef enum VGT_GROUP_CONV_SEL { VGT_GRP_INDEX_16 = 0x0, VGT_GRP_INDEX_32 = 0x1, VGT_GRP_UINT_16 = 0x2, VGT_GRP_UINT_32 = 0x3, VGT_GRP_SINT_16 = 0x4, VGT_GRP_SINT_32 = 0x5, VGT_GRP_FLOAT_32 = 0x6, VGT_GRP_AUTO_PRIM = 0x7, VGT_GRP_FIX_1_23_TO_FLOAT = 0x8, } VGT_GROUP_CONV_SEL; typedef enum VGT_GS_MODE_TYPE { GS_OFF = 0x0, GS_SCENARIO_A = 0x1, GS_SCENARIO_B = 0x2, GS_SCENARIO_G = 0x3, GS_SCENARIO_C = 0x4, SPRITE_EN = 0x5, } VGT_GS_MODE_TYPE; typedef enum VGT_GS_CUT_MODE { GS_CUT_1024 = 0x0, GS_CUT_512 = 0x1, GS_CUT_256 = 0x2, GS_CUT_128 = 0x3, } VGT_GS_CUT_MODE; typedef enum VGT_GS_OUTPRIM_TYPE { POINTLIST = 0x0, LINESTRIP = 0x1, TRISTRIP = 0x2, } VGT_GS_OUTPRIM_TYPE; typedef enum VGT_CACHE_INVALID_MODE { VC_ONLY = 0x0, TC_ONLY = 0x1, VC_AND_TC = 0x2, } VGT_CACHE_INVALID_MODE; typedef enum VGT_TESS_TYPE { TESS_ISOLINE = 0x0, TESS_TRIANGLE = 0x1, TESS_QUAD = 0x2, } VGT_TESS_TYPE; typedef enum VGT_TESS_PARTITION { PART_INTEGER = 0x0, PART_POW2 = 0x1, PART_FRAC_ODD = 0x2, PART_FRAC_EVEN = 0x3, } VGT_TESS_PARTITION; typedef enum VGT_TESS_TOPOLOGY { OUTPUT_POINT = 0x0, OUTPUT_LINE = 0x1, OUTPUT_TRIANGLE_CW = 0x2, OUTPUT_TRIANGLE_CCW = 0x3, } VGT_TESS_TOPOLOGY; typedef enum VGT_RDREQ_POLICY { VGT_POLICY_LRU = 0x0, VGT_POLICY_STREAM = 0x1, VGT_POLICY_BYPASS = 0x2, VGT_POLICY_RESERVED = 0x3, } VGT_RDREQ_POLICY; typedef enum VGT_STAGES_LS_EN { LS_STAGE_OFF = 0x0, LS_STAGE_ON = 0x1, CS_STAGE_ON = 0x2, RESERVED_LS = 0x3, } VGT_STAGES_LS_EN; typedef enum VGT_STAGES_HS_EN { HS_STAGE_OFF = 0x0, HS_STAGE_ON = 0x1, } VGT_STAGES_HS_EN; typedef enum VGT_STAGES_ES_EN { ES_STAGE_OFF = 0x0, ES_STAGE_DS = 0x1, ES_STAGE_REAL = 0x2, RESERVED_ES = 0x3, } VGT_STAGES_ES_EN; typedef enum VGT_STAGES_GS_EN { GS_STAGE_OFF = 0x0, GS_STAGE_ON = 0x1, } VGT_STAGES_GS_EN; typedef enum VGT_STAGES_VS_EN { VS_STAGE_REAL = 0x0, VS_STAGE_DS = 0x1, VS_STAGE_COPY_SHADER = 0x2, RESERVED_VS = 0x3, } VGT_STAGES_VS_EN; typedef enum VGT_PERFCOUNT_SELECT { vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x0, vgt_perf_VGT_SPI_ESVERT_VALID = 0x1, vgt_perf_VGT_SPI_ESVERT_EOV = 0x2, vgt_perf_VGT_SPI_ESVERT_STALLED = 0x3, vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x4, vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x5, vgt_perf_VGT_SPI_ESVERT_STATIC = 0x6, vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x7, vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x8, vgt_perf_VGT_SPI_GSPRIM_VALID = 0x9, vgt_perf_VGT_SPI_GSPRIM_EOV = 0xa, vgt_perf_VGT_SPI_GSPRIM_CONT = 0xb, vgt_perf_VGT_SPI_GSPRIM_STALLED = 0xc, vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0xd, vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0xe, vgt_perf_VGT_SPI_GSPRIM_STATIC = 0xf, vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x10, vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x11, vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x12, vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x13, vgt_perf_VGT_SPI_VSVERT_SEND = 0x14, vgt_perf_VGT_SPI_VSVERT_EOV = 0x15, vgt_perf_VGT_SPI_VSVERT_STALLED = 0x16, vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x17, vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x18, vgt_perf_VGT_SPI_VSVERT_STATIC = 0x19, vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x1a, vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x1b, vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x1c, vgt_perf_VGT_PA_CLIPV_SEND = 0x1d, vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x1e, vgt_perf_VGT_PA_CLIPV_STALLED = 0x1f, vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x20, vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x21, vgt_perf_VGT_PA_CLIPV_STATIC = 0x22, vgt_perf_VGT_PA_CLIPP_SEND = 0x23, vgt_perf_VGT_PA_CLIPP_EOP = 0x24, vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x25, vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x26, vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x27, vgt_perf_VGT_PA_CLIPP_STALLED = 0x28, vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x29, vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x2a, vgt_perf_VGT_PA_CLIPP_STATIC = 0x2b, vgt_perf_VGT_PA_CLIPS_SEND = 0x2c, vgt_perf_VGT_PA_CLIPS_STALLED = 0x2d, vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x2e, vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x2f, vgt_perf_VGT_PA_CLIPS_STATIC = 0x30, vgt_perf_vsvert_ds_send = 0x31, vgt_perf_vsvert_api_send = 0x32, vgt_perf_hs_tif_stall = 0x33, vgt_perf_hs_input_stall = 0x34, vgt_perf_hs_interface_stall = 0x35, vgt_perf_hs_tfm_stall = 0x36, vgt_perf_te11_starved = 0x37, vgt_perf_gs_event_stall = 0x38, vgt_perf_vgt_pa_clipp_send_not_event = 0x39, vgt_perf_vgt_pa_clipp_valid_prim = 0x3a, vgt_perf_reused_es_indices = 0x3b, vgt_perf_vs_cache_hits = 0x3c, vgt_perf_gs_cache_hits = 0x3d, vgt_perf_ds_cache_hits = 0x3e, vgt_perf_total_cache_hits = 0x3f, vgt_perf_vgt_busy = 0x40, vgt_perf_vgt_gs_busy = 0x41, vgt_perf_esvert_stalled_es_tbl = 0x42, vgt_perf_esvert_stalled_gs_tbl = 0x43, vgt_perf_esvert_stalled_gs_event = 0x44, vgt_perf_esvert_stalled_gsprim = 0x45, vgt_perf_gsprim_stalled_es_tbl = 0x46, vgt_perf_gsprim_stalled_gs_tbl = 0x47, vgt_perf_gsprim_stalled_gs_event = 0x48, vgt_perf_gsprim_stalled_esvert = 0x49, vgt_perf_esthread_stalled_es_rb_full = 0x4a, vgt_perf_esthread_stalled_spi_bp = 0x4b, vgt_perf_counters_avail_stalled = 0x4c, vgt_perf_gs_rb_space_avail_stalled = 0x4d, vgt_perf_gs_issue_rtr_stalled = 0x4e, vgt_perf_gsthread_stalled = 0x4f, vgt_perf_strmout_stalled = 0x50, vgt_perf_wait_for_es_done_stalled = 0x51, vgt_perf_cm_stalled_by_gog = 0x52, vgt_perf_cm_reading_stalled = 0x53, vgt_perf_cm_stalled_by_gsfetch_done = 0x54, vgt_perf_gog_vs_tbl_stalled = 0x55, vgt_perf_gog_out_indx_stalled = 0x56, vgt_perf_gog_out_prim_stalled = 0x57, vgt_perf_waveid_stalled = 0x58, vgt_perf_gog_busy = 0x59, vgt_perf_reused_vs_indices = 0x5a, vgt_perf_sclk_reg_vld_event = 0x5b, vgt_perf_RESERVED0 = 0x5c, vgt_perf_sclk_core_vld_event = 0x5d, vgt_perf_RESERVED1 = 0x5e, vgt_perf_sclk_gs_vld_event = 0x5f, vgt_perf_VGT_SPI_LSVERT_VALID = 0x60, vgt_perf_VGT_SPI_LSVERT_EOV = 0x61, vgt_perf_VGT_SPI_LSVERT_STALLED = 0x62, vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x63, vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x64, vgt_perf_VGT_SPI_LSVERT_STATIC = 0x65, vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x66, vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x67, vgt_perf_VGT_SPI_LSWAVE_SEND = 0x68, vgt_perf_VGT_SPI_HSVERT_VALID = 0x69, vgt_perf_VGT_SPI_HSVERT_EOV = 0x6a, vgt_perf_VGT_SPI_HSVERT_STALLED = 0x6b, vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x6c, vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x6d, vgt_perf_VGT_SPI_HSVERT_STATIC = 0x6e, vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x6f, vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x70, vgt_perf_VGT_SPI_HSWAVE_SEND = 0x71, vgt_perf_ds_prims = 0x72, vgt_perf_null_tess_patches = 0x73, vgt_perf_ls_thread_groups = 0x74, vgt_perf_hs_thread_groups = 0x75, vgt_perf_es_thread_groups = 0x76, vgt_perf_vs_thread_groups = 0x77, vgt_perf_ls_done_latency = 0x78, vgt_perf_hs_done_latency = 0x79, vgt_perf_es_done_latency = 0x7a, vgt_perf_gs_done_latency = 0x7b, vgt_perf_vgt_hs_busy = 0x7c, vgt_perf_vgt_te11_busy = 0x7d, vgt_perf_ls_flush = 0x7e, vgt_perf_hs_flush = 0x7f, vgt_perf_es_flush = 0x80, vgt_perf_gs_flush = 0x81, vgt_perf_ls_done = 0x82, vgt_perf_hs_done = 0x83, vgt_perf_es_done = 0x84, vgt_perf_gs_done = 0x85, vgt_perf_vsfetch_done = 0x86, vgt_perf_RESERVED2 = 0x87, vgt_perf_es_ring_high_water_mark = 0x88, vgt_perf_gs_ring_high_water_mark = 0x89, vgt_perf_vs_table_high_water_mark = 0x8a, vgt_perf_hs_tgs_active_high_water_mark = 0x8b, } VGT_PERFCOUNT_SELECT; typedef enum IA_PERFCOUNT_SELECT { ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x0, ia_perf_MC_LAT_BIN_0 = 0x1, ia_perf_MC_LAT_BIN_1 = 0x2, ia_perf_MC_LAT_BIN_2 = 0x3, ia_perf_MC_LAT_BIN_3 = 0x4, ia_perf_MC_LAT_BIN_4 = 0x5, ia_perf_MC_LAT_BIN_5 = 0x6, ia_perf_MC_LAT_BIN_6 = 0x7, ia_perf_MC_LAT_BIN_7 = 0x8, ia_perf_ia_busy = 0x9, ia_perf_ia_sclk_reg_vld_event = 0xa, ia_perf_RESERVED0 = 0xb, ia_perf_ia_sclk_core_vld_event = 0xc, ia_perf_RESERVED1 = 0xd, ia_perf_ia_dma_return = 0xe, ia_perf_shift_starved_pipe1_event = 0xf, ia_perf_shift_starved_pipe0_event = 0x10, ia_perf_ia_stalled = 0x11, } IA_PERFCOUNT_SELECT; typedef enum WD_PERFCOUNT_SELECT { wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x0, wd_perf_RBIU_DR_FIFO_STARVED = 0x1, wd_perf_RBIU_DR_FIFO_STALLED = 0x2, wd_perf_RBIU_DI_FIFO_STARVED = 0x3, wd_perf_RBIU_DI_FIFO_STALLED = 0x4, wd_perf_wd_busy = 0x5, wd_perf_wd_sclk_reg_vld_event = 0x6, wd_perf_wd_sclk_input_vld_event = 0x7, wd_perf_wd_sclk_core_vld_event = 0x8, wd_perf_wd_stalled = 0x9, } WD_PERFCOUNT_SELECT; typedef enum WD_IA_DRAW_TYPE { WD_IA_DRAW_TYPE_DI_MM0 = 0x0, WD_IA_DRAW_TYPE_DI_MM1 = 0x1, WD_IA_DRAW_TYPE_EVENT_INIT = 0x2, WD_IA_DRAW_TYPE_EVENT_ADDR = 0x3, WD_IA_DRAW_TYPE_MIN_INDX = 0x4, WD_IA_DRAW_TYPE_MAX_INDX = 0x5, WD_IA_DRAW_TYPE_INDX_OFF = 0x6, WD_IA_DRAW_TYPE_IMM_DATA = 0x7, } WD_IA_DRAW_TYPE; #define GSTHREADID_SIZE 0x2 typedef enum SurfaceEndian { ENDIAN_NONE = 0x0, ENDIAN_8IN16 = 0x1, ENDIAN_8IN32 = 0x2, ENDIAN_8IN64 = 0x3, } SurfaceEndian; typedef enum ArrayMode { ARRAY_LINEAR_GENERAL = 0x0, ARRAY_LINEAR_ALIGNED = 0x1, ARRAY_1D_TILED_THIN1 = 0x2, ARRAY_1D_TILED_THICK = 0x3, ARRAY_2D_TILED_THIN1 = 0x4, ARRAY_PRT_TILED_THIN1 = 0x5, ARRAY_PRT_2D_TILED_THIN1 = 0x6, ARRAY_2D_TILED_THICK = 0x7, ARRAY_2D_TILED_XTHICK = 0x8, ARRAY_PRT_TILED_THICK = 0x9, ARRAY_PRT_2D_TILED_THICK = 0xa, ARRAY_PRT_3D_TILED_THIN1 = 0xb, ARRAY_3D_TILED_THIN1 = 0xc, ARRAY_3D_TILED_THICK = 0xd, ARRAY_3D_TILED_XTHICK = 0xe, ARRAY_PRT_3D_TILED_THICK = 0xf, } ArrayMode; typedef enum PipeTiling { CONFIG_1_PIPE = 0x0, CONFIG_2_PIPE = 0x1, CONFIG_4_PIPE = 0x2, CONFIG_8_PIPE = 0x3, } PipeTiling; typedef enum BankTiling { CONFIG_4_BANK = 0x0, CONFIG_8_BANK = 0x1, } BankTiling; typedef enum GroupInterleave { CONFIG_256B_GROUP = 0x0, CONFIG_512B_GROUP = 0x1, } GroupInterleave; typedef enum RowTiling { CONFIG_1KB_ROW = 0x0, CONFIG_2KB_ROW = 0x1, CONFIG_4KB_ROW = 0x2, CONFIG_8KB_ROW = 0x3, CONFIG_1KB_ROW_OPT = 0x4, CONFIG_2KB_ROW_OPT = 0x5, CONFIG_4KB_ROW_OPT = 0x6, CONFIG_8KB_ROW_OPT = 0x7, } RowTiling; typedef enum BankSwapBytes { CONFIG_128B_SWAPS = 0x0, CONFIG_256B_SWAPS = 0x1, CONFIG_512B_SWAPS = 0x2, CONFIG_1KB_SWAPS = 0x3, } BankSwapBytes; typedef enum SampleSplitBytes { CONFIG_1KB_SPLIT = 0x0, CONFIG_2KB_SPLIT = 0x1, CONFIG_4KB_SPLIT = 0x2, CONFIG_8KB_SPLIT = 0x3, } SampleSplitBytes; typedef enum NumPipes { ADDR_CONFIG_1_PIPE = 0x0, ADDR_CONFIG_2_PIPE = 0x1, ADDR_CONFIG_4_PIPE = 0x2, ADDR_CONFIG_8_PIPE = 0x3, ADDR_CONFIG_16_PIPE = 0x4, } NumPipes; typedef enum PipeInterleaveSize { ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, } PipeInterleaveSize; typedef enum BankInterleaveSize { ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, } BankInterleaveSize; typedef enum NumShaderEngines { ADDR_CONFIG_1_SHADER_ENGINE = 0x0, ADDR_CONFIG_2_SHADER_ENGINE = 0x1, } NumShaderEngines; typedef enum ShaderEngineTileSize { ADDR_CONFIG_SE_TILE_16 = 0x0, ADDR_CONFIG_SE_TILE_32 = 0x1, } ShaderEngineTileSize; typedef enum NumGPUs { ADDR_CONFIG_1_GPU = 0x0, ADDR_CONFIG_2_GPU = 0x1, ADDR_CONFIG_4_GPU = 0x2, } NumGPUs; typedef enum MultiGPUTileSize { ADDR_CONFIG_GPU_TILE_16 = 0x0, ADDR_CONFIG_GPU_TILE_32 = 0x1, ADDR_CONFIG_GPU_TILE_64 = 0x2, ADDR_CONFIG_GPU_TILE_128 = 0x3, } MultiGPUTileSize; typedef enum RowSize { ADDR_CONFIG_1KB_ROW = 0x0, ADDR_CONFIG_2KB_ROW = 0x1, ADDR_CONFIG_4KB_ROW = 0x2, } RowSize; typedef enum NumLowerPipes { ADDR_CONFIG_1_LOWER_PIPES = 0x0, ADDR_CONFIG_2_LOWER_PIPES = 0x1, } NumLowerPipes; typedef enum DebugBlockId { DBG_CLIENT_BLKID_RESERVED = 0x0, DBG_CLIENT_BLKID_dbg = 0x1, DBG_CLIENT_BLKID_dco0 = 0x2, DBG_CLIENT_BLKID_wd = 0x3, DBG_CLIENT_BLKID_vmc = 0x4, DBG_CLIENT_BLKID_scf2 = 0x5, DBG_CLIENT_BLKID_spim3 = 0x6, DBG_CLIENT_BLKID_cb3 = 0x7, DBG_CLIENT_BLKID_sx0 = 0x8, DBG_CLIENT_BLKID_cb2 = 0x9, DBG_CLIENT_BLKID_bci1 = 0xa, DBG_CLIENT_BLKID_xdma = 0xb, DBG_CLIENT_BLKID_bci0 = 0xc, DBG_CLIENT_BLKID_spim0 = 0xd, DBG_CLIENT_BLKID_mcd0 = 0xe, DBG_CLIENT_BLKID_mcc0 = 0xf, DBG_CLIENT_BLKID_cb0 = 0x10, DBG_CLIENT_BLKID_cb1 = 0x11, DBG_CLIENT_BLKID_cpc_0 = 0x12, DBG_CLIENT_BLKID_cpc_1 = 0x13, DBG_CLIENT_BLKID_cpf = 0x14, DBG_CLIENT_BLKID_rlc = 0x15, DBG_CLIENT_BLKID_grbm = 0x16, DBG_CLIENT_BLKID_bif = 0x17, DBG_CLIENT_BLKID_scf1 = 0x18, DBG_CLIENT_BLKID_sam = 0x19, DBG_CLIENT_BLKID_mcd4 = 0x1a, DBG_CLIENT_BLKID_mcc4 = 0x1b, DBG_CLIENT_BLKID_gmcon = 0x1c, DBG_CLIENT_BLKID_mcb = 0x1d, DBG_CLIENT_BLKID_vgt0 = 0x1e, DBG_CLIENT_BLKID_pc0 = 0x1f, DBG_CLIENT_BLKID_spim1 = 0x20, DBG_CLIENT_BLKID_bci2 = 0x21, DBG_CLIENT_BLKID_mcd6 = 0x22, DBG_CLIENT_BLKID_mcc6 = 0x23, DBG_CLIENT_BLKID_mcd3 = 0x24, DBG_CLIENT_BLKID_mcc3 = 0x25, DBG_CLIENT_BLKID_uvdm_0 = 0x26, DBG_CLIENT_BLKID_uvdm_1 = 0x27, DBG_CLIENT_BLKID_uvdm_2 = 0x28, DBG_CLIENT_BLKID_uvdm_3 = 0x29, DBG_CLIENT_BLKID_spim2 = 0x2a, DBG_CLIENT_BLKID_ds = 0x2b, DBG_CLIENT_BLKID_srbm = 0x2c, DBG_CLIENT_BLKID_ih = 0x2d, DBG_CLIENT_BLKID_sem = 0x2e, DBG_CLIENT_BLKID_sdma_0 = 0x2f, DBG_CLIENT_BLKID_sdma_1 = 0x30, DBG_CLIENT_BLKID_hdp = 0x31, DBG_CLIENT_BLKID_acp_0 = 0x32, DBG_CLIENT_BLKID_acp_1 = 0x33, DBG_CLIENT_BLKID_vceb_0 = 0x34, DBG_CLIENT_BLKID_vceb_1 = 0x35, DBG_CLIENT_BLKID_vceb_2 = 0x36, DBG_CLIENT_BLKID_mcd2 = 0x37, DBG_CLIENT_BLKID_mcc2 = 0x38, DBG_CLIENT_BLKID_scf3 = 0x39, DBG_CLIENT_BLKID_bci3 = 0x3a, DBG_CLIENT_BLKID_mcd5 = 0x3b, DBG_CLIENT_BLKID_mcc5 = 0x3c, DBG_CLIENT_BLKID_vgt2 = 0x3d, DBG_CLIENT_BLKID_pc2 = 0x3e, DBG_CLIENT_BLKID_smu_0 = 0x3f, DBG_CLIENT_BLKID_smu_1 = 0x40, DBG_CLIENT_BLKID_smu_2 = 0x41, DBG_CLIENT_BLKID_vcea_0 = 0x42, DBG_CLIENT_BLKID_vcea_1 = 0x43, DBG_CLIENT_BLKID_vcea_2 = 0x44, DBG_CLIENT_BLKID_vcea_3 = 0x45, DBG_CLIENT_BLKID_vcea_4 = 0x46, DBG_CLIENT_BLKID_vcea_5 = 0x47, DBG_CLIENT_BLKID_vcea_6 = 0x48, DBG_CLIENT_BLKID_scf0 = 0x49, DBG_CLIENT_BLKID_vgt1 = 0x4a, DBG_CLIENT_BLKID_pc1 = 0x4b, DBG_CLIENT_BLKID_gdc_0 = 0x4c, DBG_CLIENT_BLKID_gdc_1 = 0x4d, DBG_CLIENT_BLKID_gdc_2 = 0x4e, DBG_CLIENT_BLKID_gdc_3 = 0x4f, DBG_CLIENT_BLKID_gdc_4 = 0x50, DBG_CLIENT_BLKID_gdc_5 = 0x51, DBG_CLIENT_BLKID_gdc_6 = 0x52, DBG_CLIENT_BLKID_gdc_7 = 0x53, DBG_CLIENT_BLKID_gdc_8 = 0x54, DBG_CLIENT_BLKID_gdc_9 = 0x55, DBG_CLIENT_BLKID_gdc_10 = 0x56, DBG_CLIENT_BLKID_gdc_11 = 0x57, DBG_CLIENT_BLKID_gdc_12 = 0x58, DBG_CLIENT_BLKID_gdc_13 = 0x59, DBG_CLIENT_BLKID_gdc_14 = 0x5a, DBG_CLIENT_BLKID_gdc_15 = 0x5b, DBG_CLIENT_BLKID_gdc_16 = 0x5c, DBG_CLIENT_BLKID_gdc_17 = 0x5d, DBG_CLIENT_BLKID_gdc_18 = 0x5e, DBG_CLIENT_BLKID_gdc_19 = 0x5f, DBG_CLIENT_BLKID_gdc_20 = 0x60, DBG_CLIENT_BLKID_gdc_21 = 0x61, DBG_CLIENT_BLKID_gdc_22 = 0x62, DBG_CLIENT_BLKID_vgt3 = 0x63, DBG_CLIENT_BLKID_pc3 = 0x64, DBG_CLIENT_BLKID_uvdu_0 = 0x65, DBG_CLIENT_BLKID_uvdu_1 = 0x66, DBG_CLIENT_BLKID_uvdu_2 = 0x67, DBG_CLIENT_BLKID_uvdu_3 = 0x68, DBG_CLIENT_BLKID_uvdu_4 = 0x69, DBG_CLIENT_BLKID_uvdu_5 = 0x6a, DBG_CLIENT_BLKID_uvdu_6 = 0x6b, DBG_CLIENT_BLKID_mcd7 = 0x6c, DBG_CLIENT_BLKID_mcc7 = 0x6d, DBG_CLIENT_BLKID_cpg_0 = 0x6e, DBG_CLIENT_BLKID_cpg_1 = 0x6f, DBG_CLIENT_BLKID_gck = 0x70, DBG_CLIENT_BLKID_mcd1 = 0x71, DBG_CLIENT_BLKID_mcc1 = 0x72, DBG_CLIENT_BLKID_cb101 = 0x73, DBG_CLIENT_BLKID_cb103 = 0x74, DBG_CLIENT_BLKID_sx10 = 0x75, DBG_CLIENT_BLKID_cb102 = 0x76, DBG_CLIENT_BLKID_cb002 = 0x77, DBG_CLIENT_BLKID_cb100 = 0x78, DBG_CLIENT_BLKID_cb000 = 0x79, DBG_CLIENT_BLKID_pa00 = 0x7a, DBG_CLIENT_BLKID_pa10 = 0x7b, DBG_CLIENT_BLKID_ia0 = 0x7c, DBG_CLIENT_BLKID_ia1 = 0x7d, DBG_CLIENT_BLKID_tmonw00 = 0x7e, DBG_CLIENT_BLKID_cb001 = 0x7f, DBG_CLIENT_BLKID_cb003 = 0x80, DBG_CLIENT_BLKID_sx00 = 0x81, DBG_CLIENT_BLKID_sx20 = 0x82, DBG_CLIENT_BLKID_cb203 = 0x83, DBG_CLIENT_BLKID_cb201 = 0x84, DBG_CLIENT_BLKID_cb302 = 0x85, DBG_CLIENT_BLKID_cb202 = 0x86, DBG_CLIENT_BLKID_cb300 = 0x87, DBG_CLIENT_BLKID_cb200 = 0x88, DBG_CLIENT_BLKID_pa01 = 0x89, DBG_CLIENT_BLKID_pa11 = 0x8a, DBG_CLIENT_BLKID_sx30 = 0x8b, DBG_CLIENT_BLKID_cb303 = 0x8c, DBG_CLIENT_BLKID_cb301 = 0x8d, DBG_CLIENT_BLKID_dco = 0x8e, DBG_CLIENT_BLKID_scb0 = 0x8f, DBG_CLIENT_BLKID_scb1 = 0x90, DBG_CLIENT_BLKID_scb2 = 0x91, DBG_CLIENT_BLKID_scb3 = 0x92, DBG_CLIENT_BLKID_tmonw01 = 0x93, DBG_CLIENT_BLKID_RESERVED_LAST = 0x94, } DebugBlockId; typedef enum DebugBlockId_OLD { DBG_BLOCK_ID_RESERVED = 0x0, DBG_BLOCK_ID_DBG = 0x1, DBG_BLOCK_ID_VMC = 0x2, DBG_BLOCK_ID_PDMA = 0x3, DBG_BLOCK_ID_CG = 0x4, DBG_BLOCK_ID_SRBM = 0x5, DBG_BLOCK_ID_GRBM = 0x6, DBG_BLOCK_ID_RLC = 0x7, DBG_BLOCK_ID_CSC = 0x8, DBG_BLOCK_ID_SEM = 0x9, DBG_BLOCK_ID_IH = 0xa, DBG_BLOCK_ID_SC = 0xb, DBG_BLOCK_ID_SQ = 0xc, DBG_BLOCK_ID_AVP = 0xd, DBG_BLOCK_ID_GMCON = 0xe, DBG_BLOCK_ID_SMU = 0xf, DBG_BLOCK_ID_DMA0 = 0x10, DBG_BLOCK_ID_DMA1 = 0x11, DBG_BLOCK_ID_SPIM = 0x12, DBG_BLOCK_ID_GDS = 0x13, DBG_BLOCK_ID_SPIS = 0x14, DBG_BLOCK_ID_UNUSED0 = 0x15, DBG_BLOCK_ID_PA0 = 0x16, DBG_BLOCK_ID_PA1 = 0x17, DBG_BLOCK_ID_CP0 = 0x18, DBG_BLOCK_ID_CP1 = 0x19, DBG_BLOCK_ID_CP2 = 0x1a, DBG_BLOCK_ID_UNUSED1 = 0x1b, DBG_BLOCK_ID_UVDU = 0x1c, DBG_BLOCK_ID_UVDM = 0x1d, DBG_BLOCK_ID_VCE = 0x1e, DBG_BLOCK_ID_UNUSED2 = 0x1f, DBG_BLOCK_ID_VGT0 = 0x20, DBG_BLOCK_ID_VGT1 = 0x21, DBG_BLOCK_ID_IA = 0x22, DBG_BLOCK_ID_UNUSED3 = 0x23, DBG_BLOCK_ID_SCT0 = 0x24, DBG_BLOCK_ID_SCT1 = 0x25, DBG_BLOCK_ID_SPM0 = 0x26, DBG_BLOCK_ID_SPM1 = 0x27, DBG_BLOCK_ID_TCAA = 0x28, DBG_BLOCK_ID_TCAB = 0x29, DBG_BLOCK_ID_TCCA = 0x2a, DBG_BLOCK_ID_TCCB = 0x2b, DBG_BLOCK_ID_MCC0 = 0x2c, DBG_BLOCK_ID_MCC1 = 0x2d, DBG_BLOCK_ID_MCC2 = 0x2e, DBG_BLOCK_ID_MCC3 = 0x2f, DBG_BLOCK_ID_SX0 = 0x30, DBG_BLOCK_ID_SX1 = 0x31, DBG_BLOCK_ID_SX2 = 0x32, DBG_BLOCK_ID_SX3 = 0x33, DBG_BLOCK_ID_UNUSED4 = 0x34, DBG_BLOCK_ID_UNUSED5 = 0x35, DBG_BLOCK_ID_UNUSED6 = 0x36, DBG_BLOCK_ID_UNUSED7 = 0x37, DBG_BLOCK_ID_PC0 = 0x38, DBG_BLOCK_ID_PC1 = 0x39, DBG_BLOCK_ID_UNUSED8 = 0x3a, DBG_BLOCK_ID_UNUSED9 = 0x3b, DBG_BLOCK_ID_UNUSED10 = 0x3c, DBG_BLOCK_ID_UNUSED11 = 0x3d, DBG_BLOCK_ID_MCB = 0x3e, DBG_BLOCK_ID_UNUSED12 = 0x3f, DBG_BLOCK_ID_SCB0 = 0x40, DBG_BLOCK_ID_SCB1 = 0x41, DBG_BLOCK_ID_UNUSED13 = 0x42, DBG_BLOCK_ID_UNUSED14 = 0x43, DBG_BLOCK_ID_SCF0 = 0x44, DBG_BLOCK_ID_SCF1 = 0x45, DBG_BLOCK_ID_UNUSED15 = 0x46, DBG_BLOCK_ID_UNUSED16 = 0x47, DBG_BLOCK_ID_BCI0 = 0x48, DBG_BLOCK_ID_BCI1 = 0x49, DBG_BLOCK_ID_BCI2 = 0x4a, DBG_BLOCK_ID_BCI3 = 0x4b, DBG_BLOCK_ID_UNUSED17 = 0x4c, DBG_BLOCK_ID_UNUSED18 = 0x4d, DBG_BLOCK_ID_UNUSED19 = 0x4e, DBG_BLOCK_ID_UNUSED20 = 0x4f, DBG_BLOCK_ID_CB00 = 0x50, DBG_BLOCK_ID_CB01 = 0x51, DBG_BLOCK_ID_CB02 = 0x52, DBG_BLOCK_ID_CB03 = 0x53, DBG_BLOCK_ID_CB04 = 0x54, DBG_BLOCK_ID_UNUSED21 = 0x55, DBG_BLOCK_ID_UNUSED22 = 0x56, DBG_BLOCK_ID_UNUSED23 = 0x57, DBG_BLOCK_ID_CB10 = 0x58, DBG_BLOCK_ID_CB11 = 0x59, DBG_BLOCK_ID_CB12 = 0x5a, DBG_BLOCK_ID_CB13 = 0x5b, DBG_BLOCK_ID_CB14 = 0x5c, DBG_BLOCK_ID_UNUSED24 = 0x5d, DBG_BLOCK_ID_UNUSED25 = 0x5e, DBG_BLOCK_ID_UNUSED26 = 0x5f, DBG_BLOCK_ID_TCP0 = 0x60, DBG_BLOCK_ID_TCP1 = 0x61, DBG_BLOCK_ID_TCP2 = 0x62, DBG_BLOCK_ID_TCP3 = 0x63, DBG_BLOCK_ID_TCP4 = 0x64, DBG_BLOCK_ID_TCP5 = 0x65, DBG_BLOCK_ID_TCP6 = 0x66, DBG_BLOCK_ID_TCP7 = 0x67, DBG_BLOCK_ID_TCP8 = 0x68, DBG_BLOCK_ID_TCP9 = 0x69, DBG_BLOCK_ID_TCP10 = 0x6a, DBG_BLOCK_ID_TCP11 = 0x6b, DBG_BLOCK_ID_TCP12 = 0x6c, DBG_BLOCK_ID_TCP13 = 0x6d, DBG_BLOCK_ID_TCP14 = 0x6e, DBG_BLOCK_ID_TCP15 = 0x6f, DBG_BLOCK_ID_TCP16 = 0x70, DBG_BLOCK_ID_TCP17 = 0x71, DBG_BLOCK_ID_TCP18 = 0x72, DBG_BLOCK_ID_TCP19 = 0x73, DBG_BLOCK_ID_TCP20 = 0x74, DBG_BLOCK_ID_TCP21 = 0x75, DBG_BLOCK_ID_TCP22 = 0x76, DBG_BLOCK_ID_TCP23 = 0x77, DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, DBG_BLOCK_ID_DB00 = 0x80, DBG_BLOCK_ID_DB01 = 0x81, DBG_BLOCK_ID_DB02 = 0x82, DBG_BLOCK_ID_DB03 = 0x83, DBG_BLOCK_ID_DB04 = 0x84, DBG_BLOCK_ID_UNUSED27 = 0x85, DBG_BLOCK_ID_UNUSED28 = 0x86, DBG_BLOCK_ID_UNUSED29 = 0x87, DBG_BLOCK_ID_DB10 = 0x88, DBG_BLOCK_ID_DB11 = 0x89, DBG_BLOCK_ID_DB12 = 0x8a, DBG_BLOCK_ID_DB13 = 0x8b, DBG_BLOCK_ID_DB14 = 0x8c, DBG_BLOCK_ID_UNUSED30 = 0x8d, DBG_BLOCK_ID_UNUSED31 = 0x8e, DBG_BLOCK_ID_UNUSED32 = 0x8f, DBG_BLOCK_ID_TCC0 = 0x90, DBG_BLOCK_ID_TCC1 = 0x91, DBG_BLOCK_ID_TCC2 = 0x92, DBG_BLOCK_ID_TCC3 = 0x93, DBG_BLOCK_ID_TCC4 = 0x94, DBG_BLOCK_ID_TCC5 = 0x95, DBG_BLOCK_ID_TCC6 = 0x96, DBG_BLOCK_ID_TCC7 = 0x97, DBG_BLOCK_ID_SPS00 = 0x98, DBG_BLOCK_ID_SPS01 = 0x99, DBG_BLOCK_ID_SPS02 = 0x9a, DBG_BLOCK_ID_SPS10 = 0x9b, DBG_BLOCK_ID_SPS11 = 0x9c, DBG_BLOCK_ID_SPS12 = 0x9d, DBG_BLOCK_ID_UNUSED33 = 0x9e, DBG_BLOCK_ID_UNUSED34 = 0x9f, DBG_BLOCK_ID_TA00 = 0xa0, DBG_BLOCK_ID_TA01 = 0xa1, DBG_BLOCK_ID_TA02 = 0xa2, DBG_BLOCK_ID_TA03 = 0xa3, DBG_BLOCK_ID_TA04 = 0xa4, DBG_BLOCK_ID_TA05 = 0xa5, DBG_BLOCK_ID_TA06 = 0xa6, DBG_BLOCK_ID_TA07 = 0xa7, DBG_BLOCK_ID_TA08 = 0xa8, DBG_BLOCK_ID_TA09 = 0xa9, DBG_BLOCK_ID_TA0A = 0xaa, DBG_BLOCK_ID_TA0B = 0xab, DBG_BLOCK_ID_UNUSED35 = 0xac, DBG_BLOCK_ID_UNUSED36 = 0xad, DBG_BLOCK_ID_UNUSED37 = 0xae, DBG_BLOCK_ID_UNUSED38 = 0xaf, DBG_BLOCK_ID_TA10 = 0xb0, DBG_BLOCK_ID_TA11 = 0xb1, DBG_BLOCK_ID_TA12 = 0xb2, DBG_BLOCK_ID_TA13 = 0xb3, DBG_BLOCK_ID_TA14 = 0xb4, DBG_BLOCK_ID_TA15 = 0xb5, DBG_BLOCK_ID_TA16 = 0xb6, DBG_BLOCK_ID_TA17 = 0xb7, DBG_BLOCK_ID_TA18 = 0xb8, DBG_BLOCK_ID_TA19 = 0xb9, DBG_BLOCK_ID_TA1A = 0xba, DBG_BLOCK_ID_TA1B = 0xbb, DBG_BLOCK_ID_UNUSED39 = 0xbc, DBG_BLOCK_ID_UNUSED40 = 0xbd, DBG_BLOCK_ID_UNUSED41 = 0xbe, DBG_BLOCK_ID_UNUSED42 = 0xbf, DBG_BLOCK_ID_TD00 = 0xc0, DBG_BLOCK_ID_TD01 = 0xc1, DBG_BLOCK_ID_TD02 = 0xc2, DBG_BLOCK_ID_TD03 = 0xc3, DBG_BLOCK_ID_TD04 = 0xc4, DBG_BLOCK_ID_TD05 = 0xc5, DBG_BLOCK_ID_TD06 = 0xc6, DBG_BLOCK_ID_TD07 = 0xc7, DBG_BLOCK_ID_TD08 = 0xc8, DBG_BLOCK_ID_TD09 = 0xc9, DBG_BLOCK_ID_TD0A = 0xca, DBG_BLOCK_ID_TD0B = 0xcb, DBG_BLOCK_ID_UNUSED43 = 0xcc, DBG_BLOCK_ID_UNUSED44 = 0xcd, DBG_BLOCK_ID_UNUSED45 = 0xce, DBG_BLOCK_ID_UNUSED46 = 0xcf, DBG_BLOCK_ID_TD10 = 0xd0, DBG_BLOCK_ID_TD11 = 0xd1, DBG_BLOCK_ID_TD12 = 0xd2, DBG_BLOCK_ID_TD13 = 0xd3, DBG_BLOCK_ID_TD14 = 0xd4, DBG_BLOCK_ID_TD15 = 0xd5, DBG_BLOCK_ID_TD16 = 0xd6, DBG_BLOCK_ID_TD17 = 0xd7, DBG_BLOCK_ID_TD18 = 0xd8, DBG_BLOCK_ID_TD19 = 0xd9, DBG_BLOCK_ID_TD1A = 0xda, DBG_BLOCK_ID_TD1B = 0xdb, DBG_BLOCK_ID_UNUSED47 = 0xdc, DBG_BLOCK_ID_UNUSED48 = 0xdd, DBG_BLOCK_ID_UNUSED49 = 0xde, DBG_BLOCK_ID_UNUSED50 = 0xdf, DBG_BLOCK_ID_MCD0 = 0xe0, DBG_BLOCK_ID_MCD1 = 0xe1, DBG_BLOCK_ID_MCD2 = 0xe2, DBG_BLOCK_ID_MCD3 = 0xe3, DBG_BLOCK_ID_MCD4 = 0xe4, DBG_BLOCK_ID_MCD5 = 0xe5, DBG_BLOCK_ID_UNUSED51 = 0xe6, DBG_BLOCK_ID_UNUSED52 = 0xe7, } DebugBlockId_OLD; typedef enum DebugBlockId_BY2 { DBG_BLOCK_ID_RESERVED_BY2 = 0x0, DBG_BLOCK_ID_VMC_BY2 = 0x1, DBG_BLOCK_ID_CG_BY2 = 0x2, DBG_BLOCK_ID_GRBM_BY2 = 0x3, DBG_BLOCK_ID_CSC_BY2 = 0x4, DBG_BLOCK_ID_IH_BY2 = 0x5, DBG_BLOCK_ID_SQ_BY2 = 0x6, DBG_BLOCK_ID_GMCON_BY2 = 0x7, DBG_BLOCK_ID_DMA0_BY2 = 0x8, DBG_BLOCK_ID_SPIM_BY2 = 0x9, DBG_BLOCK_ID_SPIS_BY2 = 0xa, DBG_BLOCK_ID_PA0_BY2 = 0xb, DBG_BLOCK_ID_CP0_BY2 = 0xc, DBG_BLOCK_ID_CP2_BY2 = 0xd, DBG_BLOCK_ID_UVDU_BY2 = 0xe, DBG_BLOCK_ID_VCE_BY2 = 0xf, DBG_BLOCK_ID_VGT0_BY2 = 0x10, DBG_BLOCK_ID_IA_BY2 = 0x11, DBG_BLOCK_ID_SCT0_BY2 = 0x12, DBG_BLOCK_ID_SPM0_BY2 = 0x13, DBG_BLOCK_ID_TCAA_BY2 = 0x14, DBG_BLOCK_ID_TCCA_BY2 = 0x15, DBG_BLOCK_ID_MCC0_BY2 = 0x16, DBG_BLOCK_ID_MCC2_BY2 = 0x17, DBG_BLOCK_ID_SX0_BY2 = 0x18, DBG_BLOCK_ID_SX2_BY2 = 0x19, DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, DBG_BLOCK_ID_PC0_BY2 = 0x1c, DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, DBG_BLOCK_ID_MCB_BY2 = 0x1f, DBG_BLOCK_ID_SCB0_BY2 = 0x20, DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, DBG_BLOCK_ID_SCF0_BY2 = 0x22, DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, DBG_BLOCK_ID_BCI0_BY2 = 0x24, DBG_BLOCK_ID_BCI2_BY2 = 0x25, DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, DBG_BLOCK_ID_CB00_BY2 = 0x28, DBG_BLOCK_ID_CB02_BY2 = 0x29, DBG_BLOCK_ID_CB04_BY2 = 0x2a, DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, DBG_BLOCK_ID_CB10_BY2 = 0x2c, DBG_BLOCK_ID_CB12_BY2 = 0x2d, DBG_BLOCK_ID_CB14_BY2 = 0x2e, DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, DBG_BLOCK_ID_TCP0_BY2 = 0x30, DBG_BLOCK_ID_TCP2_BY2 = 0x31, DBG_BLOCK_ID_TCP4_BY2 = 0x32, DBG_BLOCK_ID_TCP6_BY2 = 0x33, DBG_BLOCK_ID_TCP8_BY2 = 0x34, DBG_BLOCK_ID_TCP10_BY2 = 0x35, DBG_BLOCK_ID_TCP12_BY2 = 0x36, DBG_BLOCK_ID_TCP14_BY2 = 0x37, DBG_BLOCK_ID_TCP16_BY2 = 0x38, DBG_BLOCK_ID_TCP18_BY2 = 0x39, DBG_BLOCK_ID_TCP20_BY2 = 0x3a, DBG_BLOCK_ID_TCP22_BY2 = 0x3b, DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, DBG_BLOCK_ID_DB00_BY2 = 0x40, DBG_BLOCK_ID_DB02_BY2 = 0x41, DBG_BLOCK_ID_DB04_BY2 = 0x42, DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, DBG_BLOCK_ID_DB10_BY2 = 0x44, DBG_BLOCK_ID_DB12_BY2 = 0x45, DBG_BLOCK_ID_DB14_BY2 = 0x46, DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, DBG_BLOCK_ID_TCC0_BY2 = 0x48, DBG_BLOCK_ID_TCC2_BY2 = 0x49, DBG_BLOCK_ID_TCC4_BY2 = 0x4a, DBG_BLOCK_ID_TCC6_BY2 = 0x4b, DBG_BLOCK_ID_SPS00_BY2 = 0x4c, DBG_BLOCK_ID_SPS02_BY2 = 0x4d, DBG_BLOCK_ID_SPS11_BY2 = 0x4e, DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, DBG_BLOCK_ID_TA00_BY2 = 0x50, DBG_BLOCK_ID_TA02_BY2 = 0x51, DBG_BLOCK_ID_TA04_BY2 = 0x52, DBG_BLOCK_ID_TA06_BY2 = 0x53, DBG_BLOCK_ID_TA08_BY2 = 0x54, DBG_BLOCK_ID_TA0A_BY2 = 0x55, DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, DBG_BLOCK_ID_TA10_BY2 = 0x58, DBG_BLOCK_ID_TA12_BY2 = 0x59, DBG_BLOCK_ID_TA14_BY2 = 0x5a, DBG_BLOCK_ID_TA16_BY2 = 0x5b, DBG_BLOCK_ID_TA18_BY2 = 0x5c, DBG_BLOCK_ID_TA1A_BY2 = 0x5d, DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, DBG_BLOCK_ID_TD00_BY2 = 0x60, DBG_BLOCK_ID_TD02_BY2 = 0x61, DBG_BLOCK_ID_TD04_BY2 = 0x62, DBG_BLOCK_ID_TD06_BY2 = 0x63, DBG_BLOCK_ID_TD08_BY2 = 0x64, DBG_BLOCK_ID_TD0A_BY2 = 0x65, DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, DBG_BLOCK_ID_TD10_BY2 = 0x68, DBG_BLOCK_ID_TD12_BY2 = 0x69, DBG_BLOCK_ID_TD14_BY2 = 0x6a, DBG_BLOCK_ID_TD16_BY2 = 0x6b, DBG_BLOCK_ID_TD18_BY2 = 0x6c, DBG_BLOCK_ID_TD1A_BY2 = 0x6d, DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, DBG_BLOCK_ID_MCD0_BY2 = 0x70, DBG_BLOCK_ID_MCD2_BY2 = 0x71, DBG_BLOCK_ID_MCD4_BY2 = 0x72, DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, } DebugBlockId_BY2; typedef enum DebugBlockId_BY4 { DBG_BLOCK_ID_RESERVED_BY4 = 0x0, DBG_BLOCK_ID_CG_BY4 = 0x1, DBG_BLOCK_ID_CSC_BY4 = 0x2, DBG_BLOCK_ID_SQ_BY4 = 0x3, DBG_BLOCK_ID_DMA0_BY4 = 0x4, DBG_BLOCK_ID_SPIS_BY4 = 0x5, DBG_BLOCK_ID_CP0_BY4 = 0x6, DBG_BLOCK_ID_UVDU_BY4 = 0x7, DBG_BLOCK_ID_VGT0_BY4 = 0x8, DBG_BLOCK_ID_SCT0_BY4 = 0x9, DBG_BLOCK_ID_TCAA_BY4 = 0xa, DBG_BLOCK_ID_MCC0_BY4 = 0xb, DBG_BLOCK_ID_SX0_BY4 = 0xc, DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, DBG_BLOCK_ID_PC0_BY4 = 0xe, DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, DBG_BLOCK_ID_SCB0_BY4 = 0x10, DBG_BLOCK_ID_SCF0_BY4 = 0x11, DBG_BLOCK_ID_BCI0_BY4 = 0x12, DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, DBG_BLOCK_ID_CB00_BY4 = 0x14, DBG_BLOCK_ID_CB04_BY4 = 0x15, DBG_BLOCK_ID_CB10_BY4 = 0x16, DBG_BLOCK_ID_CB14_BY4 = 0x17, DBG_BLOCK_ID_TCP0_BY4 = 0x18, DBG_BLOCK_ID_TCP4_BY4 = 0x19, DBG_BLOCK_ID_TCP8_BY4 = 0x1a, DBG_BLOCK_ID_TCP12_BY4 = 0x1b, DBG_BLOCK_ID_TCP16_BY4 = 0x1c, DBG_BLOCK_ID_TCP20_BY4 = 0x1d, DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, DBG_BLOCK_ID_DB_BY4 = 0x20, DBG_BLOCK_ID_DB04_BY4 = 0x21, DBG_BLOCK_ID_DB10_BY4 = 0x22, DBG_BLOCK_ID_DB14_BY4 = 0x23, DBG_BLOCK_ID_TCC0_BY4 = 0x24, DBG_BLOCK_ID_TCC4_BY4 = 0x25, DBG_BLOCK_ID_SPS00_BY4 = 0x26, DBG_BLOCK_ID_SPS11_BY4 = 0x27, DBG_BLOCK_ID_TA00_BY4 = 0x28, DBG_BLOCK_ID_TA04_BY4 = 0x29, DBG_BLOCK_ID_TA08_BY4 = 0x2a, DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, DBG_BLOCK_ID_TA10_BY4 = 0x2c, DBG_BLOCK_ID_TA14_BY4 = 0x2d, DBG_BLOCK_ID_TA18_BY4 = 0x2e, DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, DBG_BLOCK_ID_TD00_BY4 = 0x30, DBG_BLOCK_ID_TD04_BY4 = 0x31, DBG_BLOCK_ID_TD08_BY4 = 0x32, DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, DBG_BLOCK_ID_TD10_BY4 = 0x34, DBG_BLOCK_ID_TD14_BY4 = 0x35, DBG_BLOCK_ID_TD18_BY4 = 0x36, DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, DBG_BLOCK_ID_MCD0_BY4 = 0x38, DBG_BLOCK_ID_MCD4_BY4 = 0x39, } DebugBlockId_BY4; typedef enum DebugBlockId_BY8 { DBG_BLOCK_ID_RESERVED_BY8 = 0x0, DBG_BLOCK_ID_CSC_BY8 = 0x1, DBG_BLOCK_ID_DMA0_BY8 = 0x2, DBG_BLOCK_ID_CP0_BY8 = 0x3, DBG_BLOCK_ID_VGT0_BY8 = 0x4, DBG_BLOCK_ID_TCAA_BY8 = 0x5, DBG_BLOCK_ID_SX0_BY8 = 0x6, DBG_BLOCK_ID_PC0_BY8 = 0x7, DBG_BLOCK_ID_SCB0_BY8 = 0x8, DBG_BLOCK_ID_BCI0_BY8 = 0x9, DBG_BLOCK_ID_CB00_BY8 = 0xa, DBG_BLOCK_ID_CB10_BY8 = 0xb, DBG_BLOCK_ID_TCP0_BY8 = 0xc, DBG_BLOCK_ID_TCP8_BY8 = 0xd, DBG_BLOCK_ID_TCP16_BY8 = 0xe, DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, DBG_BLOCK_ID_DB00_BY8 = 0x10, DBG_BLOCK_ID_DB10_BY8 = 0x11, DBG_BLOCK_ID_TCC0_BY8 = 0x12, DBG_BLOCK_ID_SPS00_BY8 = 0x13, DBG_BLOCK_ID_TA00_BY8 = 0x14, DBG_BLOCK_ID_TA08_BY8 = 0x15, DBG_BLOCK_ID_TA10_BY8 = 0x16, DBG_BLOCK_ID_TA18_BY8 = 0x17, DBG_BLOCK_ID_TD00_BY8 = 0x18, DBG_BLOCK_ID_TD08_BY8 = 0x19, DBG_BLOCK_ID_TD10_BY8 = 0x1a, DBG_BLOCK_ID_TD18_BY8 = 0x1b, DBG_BLOCK_ID_MCD0_BY8 = 0x1c, } DebugBlockId_BY8; typedef enum DebugBlockId_BY16 { DBG_BLOCK_ID_RESERVED_BY16 = 0x0, DBG_BLOCK_ID_DMA0_BY16 = 0x1, DBG_BLOCK_ID_VGT0_BY16 = 0x2, DBG_BLOCK_ID_SX0_BY16 = 0x3, DBG_BLOCK_ID_SCB0_BY16 = 0x4, DBG_BLOCK_ID_CB00_BY16 = 0x5, DBG_BLOCK_ID_TCP0_BY16 = 0x6, DBG_BLOCK_ID_TCP16_BY16 = 0x7, DBG_BLOCK_ID_DB00_BY16 = 0x8, DBG_BLOCK_ID_TCC0_BY16 = 0x9, DBG_BLOCK_ID_TA00_BY16 = 0xa, DBG_BLOCK_ID_TA10_BY16 = 0xb, DBG_BLOCK_ID_TD00_BY16 = 0xc, DBG_BLOCK_ID_TD10_BY16 = 0xd, DBG_BLOCK_ID_MCD0_BY16 = 0xe, } DebugBlockId_BY16; typedef enum CompareRef { REF_NEVER = 0x0, REF_LESS = 0x1, REF_EQUAL = 0x2, REF_LEQUAL = 0x3, REF_GREATER = 0x4, REF_NOTEQUAL = 0x5, REF_GEQUAL = 0x6, REF_ALWAYS = 0x7, } CompareRef; typedef enum ReadSize { READ_256_BITS = 0x0, READ_512_BITS = 0x1, } ReadSize; typedef enum DepthFormat { DEPTH_INVALID = 0x0, DEPTH_16 = 0x1, DEPTH_X8_24 = 0x2, DEPTH_8_24 = 0x3, DEPTH_X8_24_FLOAT = 0x4, DEPTH_8_24_FLOAT = 0x5, DEPTH_32_FLOAT = 0x6, DEPTH_X24_8_32_FLOAT = 0x7, } DepthFormat; typedef enum ZFormat { Z_INVALID = 0x0, Z_16 = 0x1, Z_24 = 0x2, Z_32_FLOAT = 0x3, } ZFormat; typedef enum StencilFormat { STENCIL_INVALID = 0x0, STENCIL_8 = 0x1, } StencilFormat; typedef enum CmaskMode { CMASK_CLEAR_NONE = 0x0, CMASK_CLEAR_ONE = 0x1, CMASK_CLEAR_ALL = 0x2, CMASK_ANY_EXPANDED = 0x3, CMASK_ALPHA0_FRAG1 = 0x4, CMASK_ALPHA0_FRAG2 = 0x5, CMASK_ALPHA0_FRAG4 = 0x6, CMASK_ALPHA0_FRAGS = 0x7, CMASK_ALPHA1_FRAG1 = 0x8, CMASK_ALPHA1_FRAG2 = 0x9, CMASK_ALPHA1_FRAG4 = 0xa, CMASK_ALPHA1_FRAGS = 0xb, CMASK_ALPHAX_FRAG1 = 0xc, CMASK_ALPHAX_FRAG2 = 0xd, CMASK_ALPHAX_FRAG4 = 0xe, CMASK_ALPHAX_FRAGS = 0xf, } CmaskMode; typedef enum QuadExportFormat { EXPORT_UNUSED = 0x0, EXPORT_32_R = 0x1, EXPORT_32_GR = 0x2, EXPORT_32_AR = 0x3, EXPORT_FP16_ABGR = 0x4, EXPORT_UNSIGNED16_ABGR = 0x5, EXPORT_SIGNED16_ABGR = 0x6, EXPORT_32_ABGR = 0x7, } QuadExportFormat; typedef enum QuadExportFormatOld { EXPORT_4P_32BPC_ABGR = 0x0, EXPORT_4P_16BPC_ABGR = 0x1, EXPORT_4P_32BPC_GR = 0x2, EXPORT_4P_32BPC_AR = 0x3, EXPORT_2P_32BPC_ABGR = 0x4, EXPORT_8P_32BPC_R = 0x5, } QuadExportFormatOld; typedef enum ColorFormat { COLOR_INVALID = 0x0, COLOR_8 = 0x1, COLOR_16 = 0x2, COLOR_8_8 = 0x3, COLOR_32 = 0x4, COLOR_16_16 = 0x5, COLOR_10_11_11 = 0x6, COLOR_11_11_10 = 0x7, COLOR_10_10_10_2 = 0x8, COLOR_2_10_10_10 = 0x9, COLOR_8_8_8_8 = 0xa, COLOR_32_32 = 0xb, COLOR_16_16_16_16 = 0xc, COLOR_RESERVED_13 = 0xd, COLOR_32_32_32_32 = 0xe, COLOR_RESERVED_15 = 0xf, COLOR_5_6_5 = 0x10, COLOR_1_5_5_5 = 0x11, COLOR_5_5_5_1 = 0x12, COLOR_4_4_4_4 = 0x13, COLOR_8_24 = 0x14, COLOR_24_8 = 0x15, COLOR_X24_8_32_FLOAT = 0x16, COLOR_RESERVED_23 = 0x17, } ColorFormat; typedef enum SurfaceFormat { FMT_INVALID = 0x0, FMT_8 = 0x1, FMT_16 = 0x2, FMT_8_8 = 0x3, FMT_32 = 0x4, FMT_16_16 = 0x5, FMT_10_11_11 = 0x6, FMT_11_11_10 = 0x7, FMT_10_10_10_2 = 0x8, FMT_2_10_10_10 = 0x9, FMT_8_8_8_8 = 0xa, FMT_32_32 = 0xb, FMT_16_16_16_16 = 0xc, FMT_32_32_32 = 0xd, FMT_32_32_32_32 = 0xe, FMT_RESERVED_4 = 0xf, FMT_5_6_5 = 0x10, FMT_1_5_5_5 = 0x11, FMT_5_5_5_1 = 0x12, FMT_4_4_4_4 = 0x13, FMT_8_24 = 0x14, FMT_24_8 = 0x15, FMT_X24_8_32_FLOAT = 0x16, FMT_RESERVED_33 = 0x17, FMT_11_11_10_FLOAT = 0x18, FMT_16_FLOAT = 0x19, FMT_32_FLOAT = 0x1a, FMT_16_16_FLOAT = 0x1b, FMT_8_24_FLOAT = 0x1c, FMT_24_8_FLOAT = 0x1d, FMT_32_32_FLOAT = 0x1e, FMT_10_11_11_FLOAT = 0x1f, FMT_16_16_16_16_FLOAT = 0x20, FMT_3_3_2 = 0x21, FMT_6_5_5 = 0x22, FMT_32_32_32_32_FLOAT = 0x23, FMT_RESERVED_36 = 0x24, FMT_1 = 0x25, FMT_1_REVERSED = 0x26, FMT_GB_GR = 0x27, FMT_BG_RG = 0x28, FMT_32_AS_8 = 0x29, FMT_32_AS_8_8 = 0x2a, FMT_5_9_9_9_SHAREDEXP = 0x2b, FMT_8_8_8 = 0x2c, FMT_16_16_16 = 0x2d, FMT_16_16_16_FLOAT = 0x2e, FMT_4_4 = 0x2f, FMT_32_32_32_FLOAT = 0x30, FMT_BC1 = 0x31, FMT_BC2 = 0x32, FMT_BC3 = 0x33, FMT_BC4 = 0x34, FMT_BC5 = 0x35, FMT_BC6 = 0x36, FMT_BC7 = 0x37, FMT_32_AS_32_32_32_32 = 0x38, FMT_APC3 = 0x39, FMT_APC4 = 0x3a, FMT_APC5 = 0x3b, FMT_APC6 = 0x3c, FMT_APC7 = 0x3d, FMT_CTX1 = 0x3e, FMT_RESERVED_63 = 0x3f, } SurfaceFormat; typedef enum BUF_DATA_FORMAT { BUF_DATA_FORMAT_INVALID = 0x0, BUF_DATA_FORMAT_8 = 0x1, BUF_DATA_FORMAT_16 = 0x2, BUF_DATA_FORMAT_8_8 = 0x3, BUF_DATA_FORMAT_32 = 0x4, BUF_DATA_FORMAT_16_16 = 0x5, BUF_DATA_FORMAT_10_11_11 = 0x6, BUF_DATA_FORMAT_11_11_10 = 0x7, BUF_DATA_FORMAT_10_10_10_2 = 0x8, BUF_DATA_FORMAT_2_10_10_10 = 0x9, BUF_DATA_FORMAT_8_8_8_8 = 0xa, BUF_DATA_FORMAT_32_32 = 0xb, BUF_DATA_FORMAT_16_16_16_16 = 0xc, BUF_DATA_FORMAT_32_32_32 = 0xd, BUF_DATA_FORMAT_32_32_32_32 = 0xe, BUF_DATA_FORMAT_RESERVED_15 = 0xf, } BUF_DATA_FORMAT; typedef enum IMG_DATA_FORMAT { IMG_DATA_FORMAT_INVALID = 0x0, IMG_DATA_FORMAT_8 = 0x1, IMG_DATA_FORMAT_16 = 0x2, IMG_DATA_FORMAT_8_8 = 0x3, IMG_DATA_FORMAT_32 = 0x4, IMG_DATA_FORMAT_16_16 = 0x5, IMG_DATA_FORMAT_10_11_11 = 0x6, IMG_DATA_FORMAT_11_11_10 = 0x7, IMG_DATA_FORMAT_10_10_10_2 = 0x8, IMG_DATA_FORMAT_2_10_10_10 = 0x9, IMG_DATA_FORMAT_8_8_8_8 = 0xa, IMG_DATA_FORMAT_32_32 = 0xb, IMG_DATA_FORMAT_16_16_16_16 = 0xc, IMG_DATA_FORMAT_32_32_32 = 0xd, IMG_DATA_FORMAT_32_32_32_32 = 0xe, IMG_DATA_FORMAT_RESERVED_15 = 0xf, IMG_DATA_FORMAT_5_6_5 = 0x10, IMG_DATA_FORMAT_1_5_5_5 = 0x11, IMG_DATA_FORMAT_5_5_5_1 = 0x12, IMG_DATA_FORMAT_4_4_4_4 = 0x13, IMG_DATA_FORMAT_8_24 = 0x14, IMG_DATA_FORMAT_24_8 = 0x15, IMG_DATA_FORMAT_X24_8_32 = 0x16, IMG_DATA_FORMAT_RESERVED_23 = 0x17, IMG_DATA_FORMAT_RESERVED_24 = 0x18, IMG_DATA_FORMAT_RESERVED_25 = 0x19, IMG_DATA_FORMAT_RESERVED_26 = 0x1a, IMG_DATA_FORMAT_RESERVED_27 = 0x1b, IMG_DATA_FORMAT_RESERVED_28 = 0x1c, IMG_DATA_FORMAT_RESERVED_29 = 0x1d, IMG_DATA_FORMAT_RESERVED_30 = 0x1e, IMG_DATA_FORMAT_RESERVED_31 = 0x1f, IMG_DATA_FORMAT_GB_GR = 0x20, IMG_DATA_FORMAT_BG_RG = 0x21, IMG_DATA_FORMAT_5_9_9_9 = 0x22, IMG_DATA_FORMAT_BC1 = 0x23, IMG_DATA_FORMAT_BC2 = 0x24, IMG_DATA_FORMAT_BC3 = 0x25, IMG_DATA_FORMAT_BC4 = 0x26, IMG_DATA_FORMAT_BC5 = 0x27, IMG_DATA_FORMAT_BC6 = 0x28, IMG_DATA_FORMAT_BC7 = 0x29, IMG_DATA_FORMAT_RESERVED_42 = 0x2a, IMG_DATA_FORMAT_RESERVED_43 = 0x2b, IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, IMG_DATA_FORMAT_4_4 = 0x39, IMG_DATA_FORMAT_6_5_5 = 0x3a, IMG_DATA_FORMAT_1 = 0x3b, IMG_DATA_FORMAT_1_REVERSED = 0x3c, IMG_DATA_FORMAT_32_AS_8 = 0x3d, IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, } IMG_DATA_FORMAT; typedef enum BUF_NUM_FORMAT { BUF_NUM_FORMAT_UNORM = 0x0, BUF_NUM_FORMAT_SNORM = 0x1, BUF_NUM_FORMAT_USCALED = 0x2, BUF_NUM_FORMAT_SSCALED = 0x3, BUF_NUM_FORMAT_UINT = 0x4, BUF_NUM_FORMAT_SINT = 0x5, BUF_NUM_FORMAT_SNORM_OGL = 0x6, BUF_NUM_FORMAT_FLOAT = 0x7, } BUF_NUM_FORMAT; typedef enum IMG_NUM_FORMAT { IMG_NUM_FORMAT_UNORM = 0x0, IMG_NUM_FORMAT_SNORM = 0x1, IMG_NUM_FORMAT_USCALED = 0x2, IMG_NUM_FORMAT_SSCALED = 0x3, IMG_NUM_FORMAT_UINT = 0x4, IMG_NUM_FORMAT_SINT = 0x5, IMG_NUM_FORMAT_SNORM_OGL = 0x6, IMG_NUM_FORMAT_FLOAT = 0x7, IMG_NUM_FORMAT_RESERVED_8 = 0x8, IMG_NUM_FORMAT_SRGB = 0x9, IMG_NUM_FORMAT_UBNORM = 0xa, IMG_NUM_FORMAT_UBNORM_OGL = 0xb, IMG_NUM_FORMAT_UBINT = 0xc, IMG_NUM_FORMAT_UBSCALED = 0xd, IMG_NUM_FORMAT_RESERVED_14 = 0xe, IMG_NUM_FORMAT_RESERVED_15 = 0xf, } IMG_NUM_FORMAT; typedef enum TileType { ARRAY_COLOR_TILE = 0x0, ARRAY_DEPTH_TILE = 0x1, } TileType; typedef enum NonDispTilingOrder { ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, } NonDispTilingOrder; typedef enum MicroTileMode { ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, ADDR_SURF_THIN_MICRO_TILING = 0x1, ADDR_SURF_DEPTH_MICRO_TILING = 0x2, ADDR_SURF_ROTATED_MICRO_TILING = 0x3, ADDR_SURF_THICK_MICRO_TILING = 0x4, } MicroTileMode; typedef enum TileSplit { ADDR_SURF_TILE_SPLIT_64B = 0x0, ADDR_SURF_TILE_SPLIT_128B = 0x1, ADDR_SURF_TILE_SPLIT_256B = 0x2, ADDR_SURF_TILE_SPLIT_512B = 0x3, ADDR_SURF_TILE_SPLIT_1KB = 0x4, ADDR_SURF_TILE_SPLIT_2KB = 0x5, ADDR_SURF_TILE_SPLIT_4KB = 0x6, } TileSplit; typedef enum SampleSplit { ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, } SampleSplit; typedef enum PipeConfig { ADDR_SURF_P2 = 0x0, ADDR_SURF_P2_RESERVED0 = 0x1, ADDR_SURF_P2_RESERVED1 = 0x2, ADDR_SURF_P2_RESERVED2 = 0x3, ADDR_SURF_P4_8x16 = 0x4, ADDR_SURF_P4_16x16 = 0x5, ADDR_SURF_P4_16x32 = 0x6, ADDR_SURF_P4_32x32 = 0x7, ADDR_SURF_P8_16x16_8x16 = 0x8, ADDR_SURF_P8_16x32_8x16 = 0x9, ADDR_SURF_P8_32x32_8x16 = 0xa, ADDR_SURF_P8_16x32_16x16 = 0xb, ADDR_SURF_P8_32x32_16x16 = 0xc, ADDR_SURF_P8_32x32_16x32 = 0xd, ADDR_SURF_P8_32x64_32x32 = 0xe, ADDR_SURF_P8_RESERVED0 = 0xf, ADDR_SURF_P16_32x32_8x16 = 0x10, ADDR_SURF_P16_32x32_16x16 = 0x11, } PipeConfig; typedef enum NumBanks { ADDR_SURF_2_BANK = 0x0, ADDR_SURF_4_BANK = 0x1, ADDR_SURF_8_BANK = 0x2, ADDR_SURF_16_BANK = 0x3, } NumBanks; typedef enum BankWidth { ADDR_SURF_BANK_WIDTH_1 = 0x0, ADDR_SURF_BANK_WIDTH_2 = 0x1, ADDR_SURF_BANK_WIDTH_4 = 0x2, ADDR_SURF_BANK_WIDTH_8 = 0x3, } BankWidth; typedef enum BankHeight { ADDR_SURF_BANK_HEIGHT_1 = 0x0, ADDR_SURF_BANK_HEIGHT_2 = 0x1, ADDR_SURF_BANK_HEIGHT_4 = 0x2, ADDR_SURF_BANK_HEIGHT_8 = 0x3, } BankHeight; typedef enum BankWidthHeight { ADDR_SURF_BANK_WH_1 = 0x0, ADDR_SURF_BANK_WH_2 = 0x1, ADDR_SURF_BANK_WH_4 = 0x2, ADDR_SURF_BANK_WH_8 = 0x3, } BankWidthHeight; typedef enum MacroTileAspect { ADDR_SURF_MACRO_ASPECT_1 = 0x0, ADDR_SURF_MACRO_ASPECT_2 = 0x1, ADDR_SURF_MACRO_ASPECT_4 = 0x2, ADDR_SURF_MACRO_ASPECT_8 = 0x3, } MacroTileAspect; typedef enum TCC_CACHE_POLICIES { TCC_CACHE_POLICY_LRU = 0x0, TCC_CACHE_POLICY_STREAM = 0x1, TCC_CACHE_POLICY_BYPASS = 0x2, } TCC_CACHE_POLICIES; typedef enum MTYPE { MTYPE_NC_NV = 0x0, MTYPE_NC = 0x1, MTYPE_CC = 0x2, MTYPE_UC = 0x3, } MTYPE; typedef enum PERFMON_COUNTER_MODE { PERFMON_COUNTER_MODE_ACCUM = 0x0, PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, PERFMON_COUNTER_MODE_MAX = 0x2, PERFMON_COUNTER_MODE_DIRTY = 0x3, PERFMON_COUNTER_MODE_SAMPLE = 0x4, PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, PERFMON_COUNTER_MODE_RESERVED = 0xf, } PERFMON_COUNTER_MODE; typedef enum PERFMON_SPM_MODE { PERFMON_SPM_MODE_OFF = 0x0, PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, PERFMON_SPM_MODE_RESERVED_5 = 0x5, PERFMON_SPM_MODE_RESERVED_6 = 0x6, PERFMON_SPM_MODE_RESERVED_7 = 0x7, PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, } PERFMON_SPM_MODE; typedef enum SurfaceTiling { ARRAY_LINEAR = 0x0, ARRAY_TILED = 0x1, } SurfaceTiling; typedef enum SurfaceArray { ARRAY_1D = 0x0, ARRAY_2D = 0x1, ARRAY_3D = 0x2, ARRAY_3D_SLICE = 0x3, } SurfaceArray; typedef enum ColorArray { ARRAY_2D_ALT_COLOR = 0x0, ARRAY_2D_COLOR = 0x1, ARRAY_3D_SLICE_COLOR = 0x3, } ColorArray; typedef enum DepthArray { ARRAY_2D_ALT_DEPTH = 0x0, ARRAY_2D_DEPTH = 0x1, } DepthArray; #endif /* GFX_7_2_ENUM_H */ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/include/asic_reg/gfx_7_2_sh_mask.h000066400000000000000000036552761446477712600274050ustar00rootroot00000000000000/* * Copyright (C) 2014 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef GFX_7_2_SH_MASK_H #define GFX_7_2_SH_MASK_H #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 #define CB_COLOR_CONTROL__MODE_MASK 0x70 #define CB_COLOR_CONTROL__MODE__SHIFT 0x4 #define CB_COLOR_CONTROL__ROP3_MASK 0xff0000 #define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 #define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f #define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 #define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 #define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d #define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000 #define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e #define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000 #define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f #define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f #define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 #define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0 #define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 #define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 #define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d #define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000 #define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e #define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000 #define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f #define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f #define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 #define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0 #define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 #define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 #define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d #define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000 #define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e #define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000 #define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f #define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f #define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 #define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0 #define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 #define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 #define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d #define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000 #define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e #define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000 #define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f #define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f #define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 #define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0 #define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 #define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 #define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d #define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000 #define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e #define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000 #define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f #define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f #define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 #define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0 #define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 #define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 #define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d #define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000 #define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e #define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000 #define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f #define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f #define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 #define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0 #define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 #define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 #define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d #define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000 #define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e #define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000 #define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f #define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f #define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 #define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0 #define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 #define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 #define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d #define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000 #define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e #define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000 #define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f #define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff #define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 #define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff #define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 #define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff #define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 #define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff #define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 #define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff #define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 #define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff #define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 #define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff #define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 #define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff #define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 #define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff #define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0 #define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 #define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14 #define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff #define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0 #define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 #define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14 #define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff #define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0 #define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 #define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14 #define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff #define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0 #define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 #define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14 #define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff #define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0 #define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 #define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14 #define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff #define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0 #define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 #define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14 #define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff #define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0 #define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 #define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14 #define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff #define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0 #define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 #define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14 #define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff #define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 #define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000 #define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd #define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff #define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 #define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000 #define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd #define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff #define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 #define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000 #define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd #define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff #define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 #define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000 #define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd #define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff #define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 #define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000 #define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd #define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff #define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 #define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000 #define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd #define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff #define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 #define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000 #define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd #define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff #define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 #define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000 #define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd #define CB_COLOR0_INFO__ENDIAN_MASK 0x3 #define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 #define CB_COLOR0_INFO__FORMAT_MASK 0x7c #define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 #define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80 #define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7 #define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700 #define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 #define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800 #define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb #define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000 #define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd #define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000 #define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe #define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000 #define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf #define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000 #define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 #define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000 #define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 #define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000 #define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 #define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000 #define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13 #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a #define CB_COLOR1_INFO__ENDIAN_MASK 0x3 #define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 #define CB_COLOR1_INFO__FORMAT_MASK 0x7c #define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 #define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80 #define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7 #define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700 #define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 #define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800 #define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb #define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000 #define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd #define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000 #define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe #define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000 #define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf #define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000 #define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 #define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000 #define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 #define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000 #define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 #define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000 #define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13 #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a #define CB_COLOR2_INFO__ENDIAN_MASK 0x3 #define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 #define CB_COLOR2_INFO__FORMAT_MASK 0x7c #define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 #define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80 #define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7 #define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700 #define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 #define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800 #define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb #define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000 #define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd #define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000 #define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe #define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000 #define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf #define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000 #define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 #define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000 #define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 #define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000 #define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 #define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000 #define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13 #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a #define CB_COLOR3_INFO__ENDIAN_MASK 0x3 #define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 #define CB_COLOR3_INFO__FORMAT_MASK 0x7c #define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 #define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80 #define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7 #define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700 #define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 #define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800 #define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb #define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000 #define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd #define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000 #define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe #define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000 #define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf #define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000 #define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 #define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000 #define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 #define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000 #define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 #define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000 #define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13 #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a #define CB_COLOR4_INFO__ENDIAN_MASK 0x3 #define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 #define CB_COLOR4_INFO__FORMAT_MASK 0x7c #define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 #define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80 #define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7 #define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700 #define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 #define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800 #define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb #define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000 #define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd #define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000 #define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe #define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000 #define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf #define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000 #define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 #define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000 #define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 #define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000 #define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 #define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000 #define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13 #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a #define CB_COLOR5_INFO__ENDIAN_MASK 0x3 #define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 #define CB_COLOR5_INFO__FORMAT_MASK 0x7c #define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 #define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80 #define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7 #define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700 #define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 #define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800 #define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb #define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000 #define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd #define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000 #define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe #define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000 #define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf #define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000 #define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 #define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000 #define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 #define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000 #define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 #define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000 #define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13 #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a #define CB_COLOR6_INFO__ENDIAN_MASK 0x3 #define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 #define CB_COLOR6_INFO__FORMAT_MASK 0x7c #define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 #define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80 #define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7 #define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700 #define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 #define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800 #define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb #define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000 #define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd #define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000 #define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe #define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000 #define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf #define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000 #define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 #define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000 #define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 #define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000 #define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 #define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000 #define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13 #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a #define CB_COLOR7_INFO__ENDIAN_MASK 0x3 #define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 #define CB_COLOR7_INFO__FORMAT_MASK 0x7c #define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 #define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80 #define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7 #define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700 #define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 #define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800 #define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb #define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000 #define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd #define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000 #define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe #define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000 #define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf #define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000 #define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 #define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000 #define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 #define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000 #define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 #define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000 #define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13 #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa #define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000 #define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa #define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000 #define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa #define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000 #define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa #define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000 #define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa #define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000 #define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa #define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000 #define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa #define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000 #define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa #define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000 #define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 #define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff #define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff #define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff #define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff #define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff #define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff #define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff #define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff #define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff #define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 #define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff #define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0 #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 #define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf #define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 #define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0 #define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 #define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00 #define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 #define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000 #define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc #define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000 #define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 #define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000 #define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 #define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000 #define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 #define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000 #define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c #define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf #define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 #define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0 #define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 #define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00 #define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 #define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000 #define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc #define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000 #define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 #define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000 #define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 #define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000 #define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 #define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000 #define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0 #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000 #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000 #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000 #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 #define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000 #define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000 #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000 #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000 #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000 #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000 #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000 #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0 #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800 #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000 #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 #define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000 #define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00 #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000 #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf #define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff000000 #define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x18 #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1 #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1 #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 #define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff #define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 #define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 #define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 #define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c #define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff #define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 #define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c #define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff #define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 #define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 #define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c #define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff #define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 #define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 #define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf #define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f #define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x1 #define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x0 #define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x2 #define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x1 #define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x4 #define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x2 #define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x8 #define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x3 #define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x10 #define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x4 #define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x20 #define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x5 #define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x40 #define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x6 #define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x80 #define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x7 #define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x100 #define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x8 #define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x200 #define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x9 #define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x400 #define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0xa #define CB_DEBUG_BUS_13__MU_STATE_MASK 0x7f800 #define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0xb #define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x1 #define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x0 #define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x2 #define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x1 #define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x4 #define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x2 #define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x8 #define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x3 #define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x10 #define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x4 #define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x20 #define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x5 #define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x40 #define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x6 #define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x80 #define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x7 #define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x100 #define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x8 #define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x3 #define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x0 #define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x4 #define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x2 #define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x8 #define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x3 #define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x10 #define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x4 #define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x20 #define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x5 #define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x40 #define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x6 #define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x80 #define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x7 #define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x100 #define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x8 #define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x3f #define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x0 #define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x3c0 #define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x6 #define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0xfc00 #define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0xa #define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0xf0000 #define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x10 #define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x100000 #define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14 #define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x200000 #define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15 #define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x400000 #define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16 #define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x1 #define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x0 #define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x2 #define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x1 #define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x4 #define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x2 #define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x8 #define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x3 #define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x10 #define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x4 #define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x20 #define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x5 #define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x40 #define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x6 #define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x80 #define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x7 #define CB_DEBUG_BUS_18__NOT_USED_MASK 0xffffff #define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x0 #define CP_DFY_CNTL__POLICY_MASK 0x300 #define CP_DFY_CNTL__POLICY__SHIFT 0x8 #define CP_DFY_CNTL__VOL_MASK 0x400 #define CP_DFY_CNTL__VOL__SHIFT 0xa #define CP_DFY_CNTL__ATC_MASK 0x800 #define CP_DFY_CNTL__ATC__SHIFT 0xb #define CP_DFY_STAT__BURST_COUNT_MASK 0xffff #define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 #define CP_DFY_STAT__TAGS_PENDING_MASK 0xff0000 #define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 #define CP_DFY_STAT__BUSY_MASK 0x80000000 #define CP_DFY_STAT__BUSY__SHIFT 0x1f #define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff #define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 #define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0 #define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 #define CP_DFY_DATA_0__DATA_MASK 0xffffffff #define CP_DFY_DATA_0__DATA__SHIFT 0x0 #define CP_DFY_DATA_1__DATA_MASK 0xffffffff #define CP_DFY_DATA_1__DATA__SHIFT 0x0 #define CP_DFY_DATA_2__DATA_MASK 0xffffffff #define CP_DFY_DATA_2__DATA__SHIFT 0x0 #define CP_DFY_DATA_3__DATA_MASK 0xffffffff #define CP_DFY_DATA_3__DATA__SHIFT 0x0 #define CP_DFY_DATA_4__DATA_MASK 0xffffffff #define CP_DFY_DATA_4__DATA__SHIFT 0x0 #define CP_DFY_DATA_5__DATA_MASK 0xffffffff #define CP_DFY_DATA_5__DATA__SHIFT 0x0 #define CP_DFY_DATA_6__DATA_MASK 0xffffffff #define CP_DFY_DATA_6__DATA__SHIFT 0x0 #define CP_DFY_DATA_7__DATA_MASK 0xffffffff #define CP_DFY_DATA_7__DATA__SHIFT 0x0 #define CP_DFY_DATA_8__DATA_MASK 0xffffffff #define CP_DFY_DATA_8__DATA__SHIFT 0x0 #define CP_DFY_DATA_9__DATA_MASK 0xffffffff #define CP_DFY_DATA_9__DATA__SHIFT 0x0 #define CP_DFY_DATA_10__DATA_MASK 0xffffffff #define CP_DFY_DATA_10__DATA__SHIFT 0x0 #define CP_DFY_DATA_11__DATA_MASK 0xffffffff #define CP_DFY_DATA_11__DATA__SHIFT 0x0 #define CP_DFY_DATA_12__DATA_MASK 0xffffffff #define CP_DFY_DATA_12__DATA__SHIFT 0x0 #define CP_DFY_DATA_13__DATA_MASK 0xffffffff #define CP_DFY_DATA_13__DATA__SHIFT 0x0 #define CP_DFY_DATA_14__DATA_MASK 0xffffffff #define CP_DFY_DATA_14__DATA__SHIFT 0x0 #define CP_DFY_DATA_15__DATA_MASK 0xffffffff #define CP_DFY_DATA_15__DATA__SHIFT 0x0 #define CP_RB0_BASE__RB_BASE_MASK 0xffffffff #define CP_RB0_BASE__RB_BASE__SHIFT 0x0 #define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff #define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 #define CP_RB_BASE__RB_BASE_MASK 0xffffffff #define CP_RB_BASE__RB_BASE__SHIFT 0x0 #define CP_RB1_BASE__RB_BASE_MASK 0xffffffff #define CP_RB1_BASE__RB_BASE__SHIFT 0x0 #define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff #define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 #define CP_RB2_BASE__RB_BASE_MASK 0xffffffff #define CP_RB2_BASE__RB_BASE__SHIFT 0x0 #define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f #define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 #define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00 #define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 #define CP_RB0_CNTL__BUF_SWAP_MASK 0x30000 #define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x10 #define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000 #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 #define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 #define CP_RB0_CNTL__CACHE_POLICY_MASK 0x3000000 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 #define CP_RB0_CNTL__RB_VOLATILE_MASK 0x4000000 #define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x1a #define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000 #define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 #define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f #define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f #define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 #define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00 #define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 #define CP_RB_CNTL__BUF_SWAP_MASK 0x30000 #define CP_RB_CNTL__BUF_SWAP__SHIFT 0x10 #define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000 #define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 #define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 #define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 #define CP_RB_CNTL__CACHE_POLICY_MASK 0x3000000 #define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 #define CP_RB_CNTL__RB_VOLATILE_MASK 0x4000000 #define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x1a #define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000 #define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b #define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 #define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f #define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f #define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 #define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00 #define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 #define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000 #define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 #define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 #define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 #define CP_RB1_CNTL__CACHE_POLICY_MASK 0x3000000 #define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 #define CP_RB1_CNTL__RB_VOLATILE_MASK 0x4000000 #define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x1a #define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000 #define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 #define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f #define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f #define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 #define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00 #define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 #define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000 #define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 #define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 #define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 #define CP_RB2_CNTL__CACHE_POLICY_MASK 0x3000000 #define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 #define CP_RB2_CNTL__RB_VOLATILE_MASK 0x4000000 #define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x1a #define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000 #define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 #define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f #define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff #define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 #define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 #define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 #define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 #define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 #define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 #define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 #define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 #define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 #define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff #define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 #define CP_RB_WPTR__RB_WPTR_MASK 0xfffff #define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 #define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff #define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 #define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff #define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 #define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffc #define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x2 #define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0xff #define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x0 #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000 #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b #define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d #define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 #define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 #define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000 #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000 #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000 #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000 #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000 #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000 #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000 #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000 #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000 #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000 #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000 #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 #define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000 #define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000 #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 #define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000 #define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000 #define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000 #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 #define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000 #define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b #define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000 #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d #define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000 #define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e #define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000 #define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000 #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 #define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x80000 #define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x13 #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000 #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000 #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000 #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000 #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000 #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000 #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000 #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000 #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000 #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000 #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000 #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000 #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000 #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000 #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000 #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000 #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000 #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000 #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000 #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000 #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000 #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000 #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000 #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000 #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f #define CP_DEVICE_ID__DEVICE_ID_MASK 0xff #define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 #define CP_RING0_PRIORITY__PRIORITY_MASK 0x3 #define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3 #define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_RING1_PRIORITY__PRIORITY_MASK 0x3 #define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3 #define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_RING2_PRIORITY__PRIORITY_MASK 0x3 #define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3 #define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3 #define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0 #define CP_RB_VMID__RB0_VMID_MASK 0xf #define CP_RB_VMID__RB0_VMID__SHIFT 0x0 #define CP_RB_VMID__RB1_VMID_MASK 0xf00 #define CP_RB_VMID__RB1_VMID__SHIFT 0x8 #define CP_RB_VMID__RB2_VMID_MASK 0xf0000 #define CP_RB_VMID__RB2_VMID__SHIFT 0x10 #define CP_ME0_PIPE0_VMID__VMID_MASK 0xf #define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 #define CP_ME0_PIPE1_VMID__VMID_MASK 0xf #define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 #define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0xfff #define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 #define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff #define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 #define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0xfff #define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 #define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0xfff #define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 #define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff #define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 #define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f #define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f #define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f #define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff #define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 #define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff #define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 #define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x1 #define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x0 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2 #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 #define CP_MEM_SLP_CNTL__RESERVED_MASK 0xfc #define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00 #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000 #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 #define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 #define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 #define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3 #define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 #define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0xf0 #define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x4 #define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x3c00 #define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0xa #define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000 #define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 #define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x3 #define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x0 #define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0xf0 #define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x4 #define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x3c00 #define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0xa #define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0xf0000 #define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x10 #define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x3 #define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x0 #define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0xf0 #define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x4 #define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x3c00 #define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0xa #define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0xf0000 #define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x10 #define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x3 #define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x0 #define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0xf0 #define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x4 #define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x3c00 #define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0xa #define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0xf0000 #define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x10 #define CP_FETCHER_SOURCE__ME_SRC_MASK 0x1 #define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0 #define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff #define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000 #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e #define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000 #define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b #define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d #define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 #define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e #define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 #define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 #define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 #define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b #define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d #define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 #define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e #define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 #define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 #define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3 #define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3 #define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3 #define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3 #define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 #define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3 #define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3 #define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3 #define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3 #define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 #define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff #define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 #define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x7ff #define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 #define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x7ff #define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 #define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xfff #define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 #define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xfff #define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 #define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff #define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 #define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x7ff #define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 #define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x7ff #define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 #define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xfff #define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 #define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xfff #define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 #define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7 #define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 #define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff #define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00 #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000 #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 #define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000 #define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 #define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff #define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 #define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00 #define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 #define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000 #define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 #define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000 #define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 #define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff #define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 #define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000 #define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10 #define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff #define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 #define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK 0xffff0000 #define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT 0x10 #define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xffff #define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 #define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1 #define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 #define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2 #define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 #define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1 #define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 #define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2 #define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 #define CP_CPC_STATUS__DC0_BUSY_MASK 0x4 #define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 #define CP_CPC_STATUS__DC1_BUSY_MASK 0x8 #define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 #define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10 #define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 #define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20 #define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 #define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40 #define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 #define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80 #define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 #define CP_CPC_STATUS__MIU_RDREQ_BUSY_MASK 0x100 #define CP_CPC_STATUS__MIU_RDREQ_BUSY__SHIFT 0x8 #define CP_CPC_STATUS__MIU_WRREQ_BUSY_MASK 0x200 #define CP_CPC_STATUS__MIU_WRREQ_BUSY__SHIFT 0x9 #define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa #define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800 #define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb #define CP_CPC_STATUS__QU_BUSY_MASK 0x1000 #define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc #define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000 #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d #define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000 #define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e #define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000 #define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1 #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2 #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4 #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8 #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10 #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40 #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80 #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100 #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200 #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000 #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000 #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000 #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000 #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000 #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000 #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000 #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000 #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000 #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000 #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000 #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000 #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000 #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d #define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL_MASK 0x1 #define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL__SHIFT 0x0 #define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL_MASK 0x2 #define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL__SHIFT 0x1 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10 #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40 #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100 #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ_MASK 0x800 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ__SHIFT 0xb #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK_MASK 0x1000 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK__SHIFT 0xc #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000 #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ_MASK 0x80000 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ__SHIFT 0x13 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK_MASK 0x100000 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK__SHIFT 0x14 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1 #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 #define CP_CPF_STATUS__CSF_BUSY_MASK 0x2 #define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 #define CP_CPF_STATUS__MIU_RDREQ_BUSY_MASK 0x4 #define CP_CPF_STATUS__MIU_RDREQ_BUSY__SHIFT 0x2 #define CP_CPF_STATUS__MIU_WRREQ_BUSY_MASK 0x8 #define CP_CPF_STATUS__MIU_WRREQ_BUSY__SHIFT 0x3 #define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10 #define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 #define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20 #define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40 #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80 #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 #define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100 #define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 #define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200 #define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800 #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb #define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000 #define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc #define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000 #define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd #define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000 #define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe #define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000 #define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf #define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000 #define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e #define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000 #define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 #define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2 #define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4 #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8 #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10 #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20 #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40 #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80 #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100 #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200 #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800 #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000 #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000 #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000 #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000 #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000 #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000 #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000 #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000 #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000 #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000 #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000 #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000 #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000 #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000 #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000 #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000 #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000 #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000 #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e #define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000 #define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1 #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2 #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4 #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8 #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 #define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10 #define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x4 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 #define CP_CPC_MC_CNTL__PACK_DELAY_CNT_MASK 0x1f #define CP_CPC_MC_CNTL__PACK_DELAY_CNT__SHIFT 0x0 #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10 #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 #define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c #define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000 #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 #define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e #define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000 #define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 #define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f #define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f #define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f #define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f #define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f #define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f #define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf #define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 #define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff #define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 #define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff #define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 #define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff #define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 #define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff #define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 #define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000 #define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 #define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100 #define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 #define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff #define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0 #define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff #define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0 #define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3 #define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0 #define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc #define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2 #define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00 #define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa #define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000 #define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12 #define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000 #define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13 #define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP_MASK 0x300000 #define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP__SHIFT 0x14 #define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000 #define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17 #define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff #define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000 #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc #define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x6000000 #define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19 #define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK 0x8000000 #define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT 0x1b #define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff #define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0 #define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000 #define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 #define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000 #define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d #define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x3 #define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x0 #define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc #define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 #define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff #define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 #define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff #define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 #define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff #define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK 0x3 #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT 0x0 #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x3 #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x0 #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1 #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 #define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff #define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 #define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff #define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 #define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff #define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 #define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff #define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 #define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff #define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 #define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff #define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 #define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff #define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 #define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff #define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 #define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff #define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 #define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000 #define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 #define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff #define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 #define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc #define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 #define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff #define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 #define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000 #define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 #define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000 #define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d #define CP_APPEND_DATA__DATA_MASK 0xffffffff #define CP_APPEND_DATA__DATA__SHIFT 0x0 #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0 #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0 #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 #define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f #define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 #define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1 #define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 #define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2 #define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 #define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40 #define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 #define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80 #define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 #define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100 #define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 #define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200 #define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 #define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400 #define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa #define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800 #define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb #define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000 #define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc #define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000 #define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd #define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000 #define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000 #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf #define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x10000 #define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x10 #define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000 #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 #define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000 #define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 #define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000 #define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 #define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000 #define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 #define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000 #define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 #define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000 #define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 #define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000 #define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000 #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000 #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d #define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff #define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 #define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff #define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 #define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff #define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 #define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff #define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 #define CP_COHER_STATUS__MEID_MASK 0x3000000 #define CP_COHER_STATUS__MEID__SHIFT 0x18 #define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000 #define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e #define CP_COHER_STATUS__STATUS_MASK 0x80000000 #define CP_COHER_STATUS__STATUS__SHIFT 0x1f #define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff #define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 #define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff #define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 #define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff #define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 #define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff #define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 #define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff #define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 #define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff #define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 #define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000 #define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x6000 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd #define CP_DMA_ME_CONTROL__SRC_VOLATILE_MASK 0x8000 #define CP_DMA_ME_CONTROL__SRC_VOLATILE__SHIFT 0xf #define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000 #define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 #define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000 #define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x6000000 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 #define CP_DMA_ME_CONTROL__DST_VOLATILE_MASK 0x8000000 #define CP_DMA_ME_CONTROL__DST_VOLATILE__SHIFT 0x1b #define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000 #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d #define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff #define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 #define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000 #define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15 #define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000 #define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16 #define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000 #define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18 #define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000 #define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a #define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000 #define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b #define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000 #define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c #define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000 #define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d #define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000 #define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 #define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff #define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 #define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000 #define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x6000 #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd #define CP_DMA_PFP_CONTROL__SRC_VOLATILE_MASK 0x8000 #define CP_DMA_PFP_CONTROL__SRC_VOLATILE__SHIFT 0xf #define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000 #define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 #define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000 #define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18 #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x6000000 #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 #define CP_DMA_PFP_CONTROL__DST_VOLATILE_MASK 0x8000000 #define CP_DMA_PFP_CONTROL__DST_VOLATILE__SHIFT 0x1b #define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000 #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d #define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff #define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 #define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000 #define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15 #define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000 #define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16 #define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000 #define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18 #define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000 #define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a #define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000 #define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b #define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000 #define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c #define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000 #define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d #define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000 #define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e #define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30 #define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 #define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000 #define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 #define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000 #define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c #define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000 #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d #define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000 #define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e #define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff #define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000 #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c #define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff #define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1 #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2 #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 #define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x8000 #define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0xf #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000 #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 #define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff #define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 #define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff #define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 #define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff #define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 #define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff #define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 #define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff #define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 #define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff #define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 #define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff #define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 #define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff #define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1 #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4 #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10 #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000 #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000 #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd #define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK 0x4000 #define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT 0xe #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000 #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf #define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10000 #define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x10 #define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK 0x20000 #define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT 0x11 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000 #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000 #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000 #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000 #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2 #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4 #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10 #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20 #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 #define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK 0x40 #define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT 0x6 #define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x80 #define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x7 #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100 #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200 #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800 #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000 #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000 #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000 #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000 #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000 #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000 #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000 #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000 #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000 #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000 #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000 #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4 #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10 #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20 #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40 #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80 #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 #define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x100 #define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x8 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800 #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000 #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000 #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40 #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 #define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80 #define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 #define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100 #define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 #define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200 #define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 #define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400 #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000 #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000 #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000 #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe #define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000 #define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf #define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000 #define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 #define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000 #define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 #define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000 #define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 #define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000 #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 #define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000 #define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 #define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000 #define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 #define CP_STAT__MIU_RDREQ_BUSY_MASK 0x80 #define CP_STAT__MIU_RDREQ_BUSY__SHIFT 0x7 #define CP_STAT__MIU_WRREQ_BUSY_MASK 0x100 #define CP_STAT__MIU_WRREQ_BUSY__SHIFT 0x8 #define CP_STAT__ROQ_RING_BUSY_MASK 0x200 #define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 #define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400 #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa #define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800 #define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb #define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000 #define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc #define CP_STAT__DC_BUSY_MASK 0x2000 #define CP_STAT__DC_BUSY__SHIFT 0xd #define CP_STAT__PFP_BUSY_MASK 0x8000 #define CP_STAT__PFP_BUSY__SHIFT 0xf #define CP_STAT__MEQ_BUSY_MASK 0x10000 #define CP_STAT__MEQ_BUSY__SHIFT 0x10 #define CP_STAT__ME_BUSY_MASK 0x20000 #define CP_STAT__ME_BUSY__SHIFT 0x11 #define CP_STAT__QUERY_BUSY_MASK 0x40000 #define CP_STAT__QUERY_BUSY__SHIFT 0x12 #define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000 #define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 #define CP_STAT__INTERRUPT_BUSY_MASK 0x100000 #define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 #define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000 #define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 #define CP_STAT__DMA_BUSY_MASK 0x400000 #define CP_STAT__DMA_BUSY__SHIFT 0x16 #define CP_STAT__RCIU_BUSY_MASK 0x800000 #define CP_STAT__RCIU_BUSY__SHIFT 0x17 #define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000 #define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 #define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000 #define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19 #define CP_STAT__CE_BUSY_MASK 0x4000000 #define CP_STAT__CE_BUSY__SHIFT 0x1a #define CP_STAT__TCIU_BUSY_MASK 0x8000000 #define CP_STAT__TCIU_BUSY__SHIFT 0x1b #define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000 #define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c #define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d #define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000 #define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e #define CP_STAT__CP_BUSY_MASK 0x80000000 #define CP_STAT__CP_BUSY__SHIFT 0x1f #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 #define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00 #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000 #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 #define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK 0x1f #define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT 0x0 #define CP_MC_TAG_CNTL__TAG_RAM_INDEX_MASK 0x3f #define CP_MC_TAG_CNTL__TAG_RAM_INDEX__SHIFT 0x0 #define CP_MC_TAG_CNTL__TAG_RAM_SEL_MASK 0x30000 #define CP_MC_TAG_CNTL__TAG_RAM_SEL__SHIFT 0x10 #define CP_MC_TAG_DATA__TAG_RAM_DATA_MASK 0xffffffff #define CP_MC_TAG_DATA__TAG_RAM_DATA__SHIFT 0x0 #define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf #define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0 #define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x3f00 #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 #define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf #define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0 #define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10 #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40 #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 #define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100 #define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 #define CP_ME_CNTL__CE_HALT_MASK 0x1000000 #define CP_ME_CNTL__CE_HALT__SHIFT 0x18 #define CP_ME_CNTL__CE_STEP_MASK 0x2000000 #define CP_ME_CNTL__CE_STEP__SHIFT 0x19 #define CP_ME_CNTL__PFP_HALT_MASK 0x4000000 #define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a #define CP_ME_CNTL__PFP_STEP_MASK 0x8000000 #define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b #define CP_ME_CNTL__ME_HALT_MASK 0x10000000 #define CP_ME_CNTL__ME_HALT__SHIFT 0x1c #define CP_ME_CNTL__ME_STEP_MASK 0x20000000 #define CP_ME_CNTL__ME_STEP__SHIFT 0x1d #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700 #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000 #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000 #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c #define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK 0x1 #define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT 0x0 #define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff #define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 #define CP_RB_RPTR__RB_RPTR_MASK 0xfffff #define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 #define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff #define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 #define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff #define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 #define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0 #define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 #define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff #define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 #define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff #define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 #define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc #define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 #define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff #define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 #define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff #define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 #define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc #define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 #define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff #define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 #define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff #define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 #define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc #define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 #define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff #define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 #define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff #define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 #define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff #define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 #define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff #define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 #define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc #define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 #define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff #define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 #define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff #define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 #define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff #define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 #define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00 #define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 #define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff #define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 #define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 #define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00 #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 #define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000 #define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 #define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff #define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 #define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00 #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000 #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 #define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000 #define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 #define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 #define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00 #define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 #define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000 #define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 #define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 #define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00 #define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 #define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 #define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 #define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff #define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 #define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 #define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 #define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff #define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 #define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000 #define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc #define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x30000 #define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 #define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff #define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000 #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000 #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000 #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 #define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff #define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 #define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff #define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 #define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff #define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 #define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000 #define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 #define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff #define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 #define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000 #define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 #define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff #define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000 #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000 #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000 #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13 #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000 #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14 #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000 #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f #define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf #define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 #define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0 #define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000 #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f #define CP_RINGID__RINGID_MASK 0x3 #define CP_RINGID__RINGID__SHIFT 0x0 #define CP_PIPEID__PIPE_ID_MASK 0x3 #define CP_PIPEID__PIPE_ID__SHIFT 0x0 #define CP_VMID__VMID_MASK 0xf #define CP_VMID__VMID__SHIFT 0x0 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00 #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 #define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000 #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 #define CP_HPD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff #define CP_HPD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 #define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff #define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 #define CP_HPD_EOP_VMID__VMID_MASK 0xf #define CP_HPD_EOP_VMID__VMID__SHIFT 0x0 #define CP_HPD_EOP_CONTROL__EOP_SIZE_MASK 0x3f #define CP_HPD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 #define CP_HPD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100 #define CP_HPD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 #define CP_HPD_EOP_CONTROL__PROCESSING_QID_MASK 0xe00 #define CP_HPD_EOP_CONTROL__PROCESSING_QID__SHIFT 0x9 #define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000 #define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc #define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000 #define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd #define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000 #define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe #define CP_HPD_EOP_CONTROL__EOP_ATC_MASK 0x800000 #define CP_HPD_EOP_CONTROL__EOP_ATC__SHIFT 0x17 #define CP_HPD_EOP_CONTROL__CACHE_POLICY_MASK 0x3000000 #define CP_HPD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 #define CP_HPD_EOP_CONTROL__EOP_VOLATILE_MASK 0x4000000 #define CP_HPD_EOP_CONTROL__EOP_VOLATILE__SHIFT 0x1a #define CP_HPD_EOP_CONTROL__PEND_Q_SEM_MASK 0x70000000 #define CP_HPD_EOP_CONTROL__PEND_Q_SEM__SHIFT 0x1c #define CP_HPD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000 #define CP_HPD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f #define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc #define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 #define CP_HQD_ACTIVE__ACTIVE_MASK 0x1 #define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 #define CP_HQD_VMID__VMID_MASK 0xf #define CP_HQD_VMID__VMID__SHIFT 0x0 #define CP_HQD_VMID__IB_VMID_MASK 0xf00 #define CP_HQD_VMID__IB_VMID__SHIFT 0x8 #define CP_HQD_VMID__VQID_MASK 0x3ff0000 #define CP_HQD_VMID__VQID__SHIFT 0x10 #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1 #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00 #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000 #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3 #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 #define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1 #define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 #define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10 #define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 #define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00 #define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 #define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff #define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 #define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff #define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f #define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff #define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f #define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00 #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x30000 #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x10 #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000 #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 #define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000 #define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17 #define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x3000000 #define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 #define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK 0x4000000 #define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT 0x1a #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000 #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000 #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e #define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000 #define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 #define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff #define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 #define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff #define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000 #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 #define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000 #define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17 #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x3000000 #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 #define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK 0x4000000 #define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT 0x1a #define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000 #define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f #define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff #define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 #define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700 #define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000 #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 #define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000 #define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17 #define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x3000000 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 #define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK 0x4000000 #define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT 0x1a #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000 #define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e #define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000 #define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f #define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f #define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x3 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1 #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 #define CP_HQD_SEMA_CMD__RETRY_MASK 0x1 #define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 #define CP_HQD_SEMA_CMD__RESULT_MASK 0x6 #define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 #define CP_HQD_MSG_TYPE__ACTION_MASK 0x3 #define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 #define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS_MASK 0x3 #define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS__SHIFT 0x0 #define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT_MASK 0xc #define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT__SHIFT 0x2 #define CP_HQD_HQ_SCHEDULER0__RSV_5_4_MASK 0x30 #define CP_HQD_HQ_SCHEDULER0__RSV_5_4__SHIFT 0x4 #define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE_MASK 0x40 #define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE__SHIFT 0x6 #define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK 0x80 #define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT 0x7 #define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK 0x100 #define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT 0x8 #define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED_MASK 0x200 #define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED__SHIFT 0x9 #define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED_MASK 0x400 #define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED__SHIFT 0xa #define CP_HQD_HQ_SCHEDULER0__RSVR_31_11_MASK 0xfffff800 #define CP_HQD_HQ_SCHEDULER0__RSVR_31_11__SHIFT 0xb #define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff #define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 #define CP_MQD_CONTROL__VMID_MASK 0xf #define CP_MQD_CONTROL__VMID__SHIFT 0x0 #define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000 #define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17 #define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x3000000 #define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 #define CP_MQD_CONTROL__MQD_VOLATILE_MASK 0x4000000 #define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT 0x1a #define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff #define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 #define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff #define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 #define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff #define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 #define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff #define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 #define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf #define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0 #define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0 #define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4 #define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00 #define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8 #define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000 #define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd #define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000 #define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf #define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000 #define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11 #define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000 #define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13 #define DB_Z_INFO__FORMAT_MASK 0x3 #define DB_Z_INFO__FORMAT__SHIFT 0x0 #define DB_Z_INFO__NUM_SAMPLES_MASK 0xc #define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 #define DB_Z_INFO__TILE_SPLIT_MASK 0xe000 #define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd #define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000 #define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14 #define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 #define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b #define DB_Z_INFO__READ_SIZE_MASK 0x10000000 #define DB_Z_INFO__READ_SIZE__SHIFT 0x1c #define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000 #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d #define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000 #define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f #define DB_STENCIL_INFO__FORMAT_MASK 0x1 #define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 #define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000 #define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd #define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000 #define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14 #define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 #define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d #define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff #define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0 #define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800 #define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb #define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff #define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0 #define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff #define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 #define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000 #define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd #define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000 #define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 #define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000 #define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1 #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2 #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 #define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4 #define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 #define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8 #define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10 #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20 #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40 #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 #define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80 #define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 #define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00 #define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1 #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2 #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 #define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70 #define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 #define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00 #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000 #define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000 #define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 #define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000 #define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000 #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000 #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3 #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40 #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80 #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100 #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200 #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa #define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800 #define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000 #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000 #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000 #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000 #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000 #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000 #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000 #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000 #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000 #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c #define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000 #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20 #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40 #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80 #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100 #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200 #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800 #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000 #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000 #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 #define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7 #define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 #define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70 #define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700 #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000 #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000 #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 #define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000 #define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 #define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000 #define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 #define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000 #define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000 #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000 #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 #define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000 #define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000 #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1 #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2 #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4 #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 #define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30 #define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 #define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40 #define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80 #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100 #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200 #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 #define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400 #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800 #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000 #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000 #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd #define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff #define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 #define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff #define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 #define DB_STENCIL_CLEAR__CLEAR_MASK 0xff #define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 #define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff #define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 #define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff #define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 #define DB_HTILE_SURFACE__LINEAR_MASK 0x1 #define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0 #define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2 #define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4 #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 #define DB_HTILE_SURFACE__PRELOAD_MASK 0x8 #define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 #define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0 #define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 #define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00 #define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000 #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 #define DB_PRELOAD_CONTROL__START_X_MASK 0xff #define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 #define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00 #define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 #define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000 #define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 #define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000 #define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 #define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff #define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 #define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00 #define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 #define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000 #define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 #define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000 #define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 #define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00 #define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000 #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000 #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7 #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0 #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000 #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc #define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000 #define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7 #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0 #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000 #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc #define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000 #define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 #define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1 #define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 #define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2 #define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4 #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8 #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 #define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70 #define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 #define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80 #define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 #define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700 #define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 #define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000 #define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000 #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000 #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f #define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf #define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 #define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0 #define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 #define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00 #define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 #define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000 #define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc #define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000 #define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 #define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000 #define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe #define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000 #define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 #define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff #define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 #define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 #define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 #define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c #define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff #define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa #define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 #define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 #define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 #define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 #define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 #define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c #define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff #define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa #define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 #define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 #define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000 #define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 #define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 #define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c #define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff #define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa #define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 #define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 #define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000 #define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 #define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 #define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1 #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2 #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 #define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4 #define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 #define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8 #define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 #define DB_DEBUG__FORCE_Z_MODE_MASK 0x30 #define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40 #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80 #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300 #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc #define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000 #define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000 #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000 #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 #define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000 #define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000 #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000 #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 #define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000 #define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000 #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000 #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000 #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 #define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000 #define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000 #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000 #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1 #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2 #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4 #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8 #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20 #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5 #define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40 #define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6 #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80 #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7 #define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100 #define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8 #define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00 #define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000 #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000 #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000 #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10 #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000 #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000 #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000 #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000 #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000 #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000 #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f #define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4 #define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8 #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10 #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20 #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40 #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80 #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100 #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200 #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800 #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000 #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc #define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000 #define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000 #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000 #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000 #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000 #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000 #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000 #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000 #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000 #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000 #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000 #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 #define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000 #define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000 #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000 #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000 #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000 #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d #define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK 0xc0000000 #define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT 0x1e #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1 #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2 #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4 #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8 #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 #define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0 #define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4 #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0 #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000 #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 #define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f #define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 #define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0 #define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 #define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800 #define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb #define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000 #define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf #define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000 #define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 #define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000 #define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b #define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000 #define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c #define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000 #define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d #define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000 #define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e #define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000 #define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f #define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3 #define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 #define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc #define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 #define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30 #define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 #define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0 #define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 #define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300 #define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 #define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00 #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa #define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000 #define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc #define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000 #define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe #define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000 #define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 #define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000 #define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80 #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 #define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000 #define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000 #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15 #define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000 #define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19 #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0 #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0 #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5 #define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00 #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa #define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000 #define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000 #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00 #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000 #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000 #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 #define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf #define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0 #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 #define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000 #define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f #define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff #define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 #define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff #define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 #define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3 #define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 #define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff #define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0 #define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff #define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0 #define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff #define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0 #define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff #define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0 #define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff #define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0 #define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff #define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0 #define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff #define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0 #define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff #define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0 #define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff #define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0 #define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff #define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0 #define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff #define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0 #define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff #define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0 #define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff #define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0 #define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff #define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0 #define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff #define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0 #define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff #define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0 #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 #define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff #define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 #define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff #define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 #define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff #define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 #define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff #define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 #define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 #define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 #define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 #define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc #define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 #define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 #define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 #define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 #define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 #define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc #define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 #define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 #define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 #define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 #define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 #define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 #define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 #define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c #define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 #define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e #define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff #define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 #define GB_GPU_ID__GPU_ID_MASK 0xf #define GB_GPU_ID__GPU_ID__SHIFT 0x0 #define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf #define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 #define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0 #define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 #define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00 #define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 #define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000 #define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc #define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000 #define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 #define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000 #define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 #define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000 #define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 #define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000 #define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c #define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 #define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c #define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 #define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0 #define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 #define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800 #define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000 #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 #define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000 #define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 #define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 #define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3 #define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 #define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc #define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30 #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 #define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0 #define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 #define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000 #define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10 #define GB_EDC_MODE__DED_MODE_MASK 0x300000 #define GB_EDC_MODE__DED_MODE__SHIFT 0x14 #define GB_EDC_MODE__PROP_FED_MASK 0x20000000 #define GB_EDC_MODE__PROP_FED__SHIFT 0x1d #define GB_EDC_MODE__BYPASS_MASK 0x80000000 #define GB_EDC_MODE__BYPASS__SHIFT 0x1f #define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2 #define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 #define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1 #define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 #define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff #define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 #define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff #define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 #define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff #define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 #define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff #define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 #define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff #define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 #define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff #define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 #define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff #define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0 #define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff #define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0 #define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff #define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 #define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff #define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 #define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff #define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 #define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff #define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 #define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff #define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 #define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff #define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 #define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff #define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 #define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff #define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 #define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff #define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0 #define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff #define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0 #define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff #define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 #define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff #define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 #define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff #define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0 #define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff #define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0 #define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff #define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 #define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff #define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 #define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff #define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 #define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7 #define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 #define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff #define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 #define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 #define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 #define GRBM_CNTL__READ_TIMEOUT_MASK 0xff #define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0 #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 #define GRBM_PWR_CNTL__REQ_TYPE_MASK 0xf #define GRBM_PWR_CNTL__REQ_TYPE__SHIFT 0x0 #define GRBM_PWR_CNTL__RSP_TYPE_MASK 0xf0 #define GRBM_PWR_CNTL__RSP_TYPE__SHIFT 0x4 #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 #define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20 #define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200 #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 #define GRBM_STATUS__DB_CLEAN_MASK 0x1000 #define GRBM_STATUS__DB_CLEAN__SHIFT 0xc #define GRBM_STATUS__CB_CLEAN_MASK 0x2000 #define GRBM_STATUS__CB_CLEAN__SHIFT 0xd #define GRBM_STATUS__TA_BUSY_MASK 0x4000 #define GRBM_STATUS__TA_BUSY__SHIFT 0xe #define GRBM_STATUS__GDS_BUSY_MASK 0x8000 #define GRBM_STATUS__GDS_BUSY__SHIFT 0xf #define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000 #define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 #define GRBM_STATUS__VGT_BUSY_MASK 0x20000 #define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 #define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000 #define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 #define GRBM_STATUS__IA_BUSY_MASK 0x80000 #define GRBM_STATUS__IA_BUSY__SHIFT 0x13 #define GRBM_STATUS__SX_BUSY_MASK 0x100000 #define GRBM_STATUS__SX_BUSY__SHIFT 0x14 #define GRBM_STATUS__WD_BUSY_MASK 0x200000 #define GRBM_STATUS__WD_BUSY__SHIFT 0x15 #define GRBM_STATUS__SPI_BUSY_MASK 0x400000 #define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 #define GRBM_STATUS__BCI_BUSY_MASK 0x800000 #define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 #define GRBM_STATUS__SC_BUSY_MASK 0x1000000 #define GRBM_STATUS__SC_BUSY__SHIFT 0x18 #define GRBM_STATUS__PA_BUSY_MASK 0x2000000 #define GRBM_STATUS__PA_BUSY__SHIFT 0x19 #define GRBM_STATUS__DB_BUSY_MASK 0x4000000 #define GRBM_STATUS__DB_BUSY__SHIFT 0x1a #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000 #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c #define GRBM_STATUS__CP_BUSY_MASK 0x20000000 #define GRBM_STATUS__CP_BUSY__SHIFT 0x1d #define GRBM_STATUS__CB_BUSY_MASK 0x40000000 #define GRBM_STATUS__CB_BUSY__SHIFT 0x1e #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000 #define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10 #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20 #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40 #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80 #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100 #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200 #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800 #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000 #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000 #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd #define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000 #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe #define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000 #define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 #define GRBM_STATUS2__TC_BUSY_MASK 0x2000000 #define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 #define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000 #define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c #define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000 #define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d #define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000 #define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e #define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2 #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 #define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4 #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 #define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000 #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 #define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000 #define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 #define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000 #define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 #define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000 #define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 #define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000 #define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a #define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000 #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b #define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000 #define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d #define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000 #define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e #define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000 #define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f #define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2 #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 #define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4 #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 #define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000 #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 #define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000 #define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 #define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000 #define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 #define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000 #define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 #define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000 #define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a #define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000 #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b #define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000 #define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d #define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000 #define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e #define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000 #define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f #define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2 #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 #define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4 #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 #define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000 #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 #define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000 #define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 #define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000 #define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 #define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000 #define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 #define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000 #define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a #define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000 #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b #define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000 #define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d #define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000 #define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e #define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000 #define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f #define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2 #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 #define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4 #define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 #define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000 #define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 #define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000 #define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 #define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000 #define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 #define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000 #define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 #define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000 #define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a #define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000 #define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b #define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000 #define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d #define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000 #define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e #define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000 #define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1 #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4 #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000 #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000 #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000 #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000 #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 #define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f #define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0 #define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff #define GRBM_DEBUG_DATA__DATA__SHIFT 0x0 #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 #define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00 #define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 #define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000 #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 #define GRBM_DEBUG__IGNORE_RDY_MASK 0x2 #define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1 #define GRBM_DEBUG__IGNORE_FAO_MASK 0x20 #define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5 #define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40 #define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6 #define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80 #define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7 #define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00 #define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8 #define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000 #define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc #define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1 #define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0 #define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2 #define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1 #define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4 #define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2 #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8 #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3 #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10 #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4 #define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20 #define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15 #define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 #define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000 #define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 #define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000 #define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 #define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 #define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f #define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000 #define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1 #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000 #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 #define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff #define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0 #define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff #define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 #define GRBM_NOWHERE__DATA_MASK 0xffffffff #define GRBM_NOWHERE__DATA__SHIFT 0x0 #define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1 #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2 #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8 #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10 #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20 #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 #define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100 #define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 #define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200 #define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 #define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400 #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa #define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800 #define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000 #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000 #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000 #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000 #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000 #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1 #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2 #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4 #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8 #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10 #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20 #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40 #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80 #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100 #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200 #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800 #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000 #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000 #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000 #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000 #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 #define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2 #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4 #define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8 #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10 #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000 #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000 #define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe #define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000 #define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000 #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000 #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000 #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 #define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000 #define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000 #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000 #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000 #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000 #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000 #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 #define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff #define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 #define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff #define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 #define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff #define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 #define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff #define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 #define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff #define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1 #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 #define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8 #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10 #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5 #define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000 #define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c #define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000 #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d #define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000 #define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e #define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000 #define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1 #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0 #define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1 #define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 #define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6 #define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 #define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38 #define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 #define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff #define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 #define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000 #define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 #define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff #define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 #define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000 #define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 #define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff #define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3 #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4 #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8 #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10 #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2 #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4 #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20 #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40 #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00 #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000 #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000 #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f #define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1 #define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 #define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2 #define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 #define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4 #define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 #define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18 #define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0 #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700 #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000 #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000 #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000 #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 #define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff #define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7 #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10 #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000 #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000 #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000 #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c #define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff #define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 #define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 #define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff #define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 #define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 #define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff #define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 #define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 #define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff #define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 #define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 #define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff #define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 #define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 #define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff #define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 #define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 #define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff #define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 #define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 #define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff #define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 #define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 #define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff #define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 #define PA_SC_EDGERULE__ER_TRI_MASK 0xf #define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 #define PA_SC_EDGERULE__ER_POINT_MASK 0xf0 #define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 #define PA_SC_EDGERULE__ER_RECT_MASK 0xf00 #define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 #define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000 #define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc #define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000 #define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 #define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000 #define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 #define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000 #define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200 #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 #define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400 #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800 #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000 #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc #define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff #define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 #define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000 #define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000 #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d #define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1 #define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2 #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4 #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8 #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 #define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1 #define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2 #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4 #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8 #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70 #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80 #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100 #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200 #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800 #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000 #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000 #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000 #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000 #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000 #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000 #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000 #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 #define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30 #define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 #define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40 #define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 #define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80 #define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 #define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300 #define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 #define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00 #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa #define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000 #define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc #define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000 #define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe #define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000 #define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 #define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000 #define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 #define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000 #define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 #define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000 #define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 #define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000 #define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a #define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000 #define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 #define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff #define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 #define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff #define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 #define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 #define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff #define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 #define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000 #define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 #define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff #define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 #define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000 #define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000 #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 #define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff #define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 #define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff #define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 #define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f #define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff #define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000 #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2 #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4 #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20 #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 #define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0 #define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6 #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100 #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8 #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200 #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000 #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000 #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000 #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18 #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000 #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19 #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000 #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000 #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000 #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d #define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000 #define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e #define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000 #define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0 #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000 #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000 #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17 #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0 #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000 #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000 #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 #define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff #define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 #define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000 #define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 #define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff #define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 #define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000 #define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 #define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff #define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 #define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000 #define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 #define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff #define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 #define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000 #define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 #define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff #define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 #define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff #define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 #define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff #define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 #define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000 #define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f #define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000 #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f #define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 #define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000 #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000 #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f #define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f #define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f #define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0 #define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff #define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0 #define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f #define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0 #define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff #define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0 #define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff #define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0 #define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100 #define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8 #define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600 #define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9 #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800 #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000 #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000 #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000 #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000 #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000 #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10 #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000 #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11 #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000 #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12 #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000 #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13 #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000 #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14 #define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000 #define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15 #define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000 #define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16 #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000 #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17 #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000 #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18 #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000 #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19 #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000 #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000 #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000 #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000 #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000 #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000 #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f #define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff #define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0 #define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700 #define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8 #define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800 #define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb #define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000 #define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe #define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000 #define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11 #define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000 #define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14 #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000 #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15 #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000 #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16 #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000 #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17 #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000 #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18 #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000 #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19 #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000 #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a #define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000 #define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c #define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000 #define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000 #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000 #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f #define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7 #define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0 #define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38 #define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3 #define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0 #define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6 #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00 #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8 #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000 #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000 #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10 #define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000 #define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14 #define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000 #define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15 #define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000 #define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16 #define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000 #define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17 #define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000 #define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18 #define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000 #define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19 #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000 #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000 #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000 #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000 #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000 #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000 #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b #define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000 #define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c #define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000 #define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d #define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000 #define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e #define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000 #define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f #define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff #define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0 #define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00 #define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8 #define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000 #define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000 #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12 #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000 #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14 #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000 #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16 #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000 #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18 #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000 #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19 #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000 #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000 #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000 #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000 #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000 #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7 #define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0 #define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8 #define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3 #define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10 #define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4 #define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20 #define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5 #define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40 #define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6 #define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80 #define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7 #define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00 #define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8 #define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000 #define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc #define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000 #define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe #define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000 #define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf #define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000 #define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10 #define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000 #define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11 #define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000 #define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15 #define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000 #define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0 #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0 #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6 #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000 #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc #define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000 #define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12 #define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000 #define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13 #define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000 #define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14 #define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000 #define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15 #define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000 #define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18 #define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000 #define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e #define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff #define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0 #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000 #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10 #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000 #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15 #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000 #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a #define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f #define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0 #define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80 #define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7 #define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00 #define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8 #define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000 #define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000 #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12 #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000 #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13 #define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000 #define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14 #define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 #define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b #define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000 #define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c #define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000 #define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d #define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000 #define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e #define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f #define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0 #define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80 #define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7 #define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00 #define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8 #define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000 #define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000 #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12 #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000 #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13 #define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000 #define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14 #define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 #define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b #define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000 #define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c #define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000 #define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d #define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000 #define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e #define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f #define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0 #define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80 #define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7 #define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00 #define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8 #define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000 #define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000 #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12 #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000 #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13 #define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000 #define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14 #define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 #define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b #define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000 #define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c #define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000 #define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d #define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000 #define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e #define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f #define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f #define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0 #define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80 #define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7 #define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00 #define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8 #define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000 #define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000 #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12 #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000 #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13 #define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000 #define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14 #define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 #define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b #define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000 #define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c #define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000 #define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d #define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000 #define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e #define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000 #define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f #define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f #define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0 #define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0 #define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc #define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a #define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e #define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f #define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f #define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0 #define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380 #define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7 #define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00 #define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa #define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000 #define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf #define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000 #define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10 #define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000 #define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14 #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000 #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16 #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000 #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17 #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000 #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18 #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000 #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c #define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f #define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0 #define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180 #define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7 #define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00 #define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9 #define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000 #define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf #define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000 #define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10 #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000 #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17 #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000 #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a #define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff #define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0 #define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00 #define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8 #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000 #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000 #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd #define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000 #define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe #define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000 #define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15 #define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000 #define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17 #define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000 #define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18 #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000 #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19 #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000 #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000 #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000 #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000 #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000 #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000 #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f #define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3 #define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0 #define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c #define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2 #define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00 #define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8 #define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000 #define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe #define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000 #define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf #define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000 #define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10 #define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000 #define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12 #define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000 #define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13 #define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000 #define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14 #define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000 #define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15 #define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000 #define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16 #define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000 #define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c #define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000 #define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d #define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000 #define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e #define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000 #define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f #define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff #define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0 #define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000 #define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10 #define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff #define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0 #define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000 #define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10 #define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff #define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0 #define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000 #define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10 #define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff #define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0 #define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000 #define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe #define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000 #define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf #define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000 #define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10 #define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000 #define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13 #define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000 #define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14 #define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000 #define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17 #define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000 #define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18 #define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000 #define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a #define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000 #define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d #define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000 #define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f #define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff #define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0 #define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000 #define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe #define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000 #define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c #define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000 #define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e #define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000 #define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f #define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3 #define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0 #define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc #define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2 #define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3 #define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0 #define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc #define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2 #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1 #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2 #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4 #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20 #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40 #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 #define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380 #define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800 #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb #define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000 #define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc #define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000 #define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe #define COMPUTE_DIM_X__SIZE_MASK 0xffffffff #define COMPUTE_DIM_X__SIZE__SHIFT 0x0 #define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff #define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 #define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff #define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 #define COMPUTE_START_X__START_MASK 0xffffffff #define COMPUTE_START_X__START__SHIFT 0x0 #define COMPUTE_START_Y__START_MASK 0xffffffff #define COMPUTE_START_Y__START__SHIFT 0x0 #define COMPUTE_START_Z__START_MASK 0xffffffff #define COMPUTE_START_Z__START__SHIFT 0x0 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1 #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1 #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 #define COMPUTE_PGM_LO__DATA_MASK 0xffffffff #define COMPUTE_PGM_LO__DATA__SHIFT 0x0 #define COMPUTE_PGM_HI__DATA_MASK 0xff #define COMPUTE_PGM_HI__DATA__SHIFT 0x0 #define COMPUTE_PGM_HI__INST_ATC_MASK 0x100 #define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8 #define COMPUTE_TBA_LO__DATA_MASK 0xffffffff #define COMPUTE_TBA_LO__DATA__SHIFT 0x0 #define COMPUTE_TBA_HI__DATA_MASK 0xff #define COMPUTE_TBA_HI__DATA__SHIFT 0x0 #define COMPUTE_TMA_LO__DATA_MASK 0xffffffff #define COMPUTE_TMA_LO__DATA__SHIFT 0x0 #define COMPUTE_TMA_HI__DATA_MASK 0xff #define COMPUTE_TMA_HI__DATA__SHIFT 0x0 #define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f #define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 #define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0 #define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 #define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00 #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa #define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000 #define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc #define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000 #define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 #define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000 #define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 #define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000 #define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 #define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000 #define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 #define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000 #define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 #define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000 #define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 #define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1 #define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 #define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e #define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 #define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40 #define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 #define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80 #define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 #define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100 #define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 #define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200 #define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800 #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000 #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd #define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000 #define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf #define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000 #define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 #define COMPUTE_VMID__DATA_MASK 0xf #define COMPUTE_VMID__DATA__SHIFT 0x0 #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000 #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000 #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000 #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000 #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000 #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 #define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff #define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 #define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 #define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 #define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff #define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 #define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff #define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 #define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff #define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1 #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 #define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3 #define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 #define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4 #define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 #define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8 #define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 #define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10 #define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 #define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 #define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff #define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 #define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff #define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0 #define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000 #define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15 #define CSPRIV_CONNECT__VMID_MASK 0x3c000000 #define CSPRIV_CONNECT__VMID__SHIFT 0x1a #define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000 #define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f #define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff #define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0 #define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff #define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0 #define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff #define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0 #define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff #define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0 #define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000 #define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000 #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18 #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000 #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19 #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000 #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a #define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000 #define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b #define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000 #define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c #define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f #define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0 #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1 #define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 #define RLC_CNTL__FORCE_RETRY_MASK 0x2 #define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 #define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4 #define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 #define RLC_CNTL__RLC_STEP_F32_MASK 0x8 #define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 #define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10 #define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4 #define RLC_CNTL__RESERVED_MASK 0xffffff00 #define RLC_CNTL__RESERVED__SHIFT 0x8 #define RLC_DEBUG_SELECT__SELECT_MASK 0xff #define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0 #define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00 #define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8 #define RLC_DEBUG__DATA_MASK 0xffffffff #define RLC_DEBUG__DATA__SHIFT 0x0 #define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3 #define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0 #define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4 #define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2 #define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8 #define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3 #define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10 #define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4 #define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0 #define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5 #define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00 #define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9 #define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000 #define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd #define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000 #define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14 #define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000 #define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18 #define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000 #define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a #define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000 #define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b #define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000 #define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c #define RLC_MC_CNTL__RESERVED_MASK 0xe0000000 #define RLC_MC_CNTL__RESERVED__SHIFT 0x1d #define RLC_STAT__RLC_BUSY_MASK 0x1 #define RLC_STAT__RLC_BUSY__SHIFT 0x0 #define RLC_STAT__RLC_GPM_BUSY_MASK 0x2 #define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1 #define RLC_STAT__RLC_SPM_BUSY_MASK 0x4 #define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2 #define RLC_STAT__RESERVED_MASK 0xfffffff8 #define RLC_STAT__RESERVED__SHIFT 0x3 #define RLC_SAFE_MODE__REQ_MASK 0x1 #define RLC_SAFE_MODE__REQ__SHIFT 0x0 #define RLC_SAFE_MODE__MESSAGE_MASK 0x1e #define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 #define RLC_SAFE_MODE__RESERVED_MASK 0xffffffe0 #define RLC_SAFE_MODE__RESERVED__SHIFT 0x5 #define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1 #define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0 #define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe #define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2 #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 #define RLC_MEM_SLP_CNTL__RESERVED_MASK 0xfc #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 #define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 #define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7 #define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1 #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 #define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2 #define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4 #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 #define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8 #define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0 #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 #define RLC_LB_CNTL__RESERVED_MASK 0xfffff000 #define RLC_LB_CNTL__RESERVED__SHIFT 0xc #define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff #define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 #define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff #define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 #define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff #define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0 #define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff #define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 #define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1 #define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0 #define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe #define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1 #define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10 #define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4 #define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0 #define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5 #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 #define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00 #define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000 #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 #define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff #define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0 #define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xffffff00 #define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0x8 #define RLC_GPM_DEBUG__DATA_MASK 0xffffffff #define RLC_GPM_DEBUG__DATA__SHIFT 0x0 #define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff #define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 #define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000 #define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc #define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff #define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1 #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 #define RLC_GPM_STAT__RLC_BUSY_MASK 0x1 #define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 #define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2 #define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 #define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4 #define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 #define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8 #define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 #define RLC_GPM_STAT__RESERVED_MASK 0xfffffff0 #define RLC_GPM_STAT__RESERVED__SHIFT 0x4 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0 #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 #define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff #define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 #define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2 #define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4 #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8 #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 #define RLC_PG_CNTL__RESERVED_MASK 0xfff0 #define RLC_PG_CNTL__RESERVED__SHIFT 0x4 #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000 #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 #define RLC_PG_CNTL__RESERVED1_MASK 0xf80000 #define RLC_PG_CNTL__RESERVED1__SHIFT 0x13 #define RLC_PG_CNTL__PG_ERROR_STATUS_MASK 0xff000000 #define RLC_PG_CNTL__PG_ERROR_STATUS__SHIFT 0x18 #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00 #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000 #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000 #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1 #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2 #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4 #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8 #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 #define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0 #define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 #define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf #define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0 #define RLC_GPM_VMID_THREAD0__RESERVED_MASK 0xfffffff0 #define RLC_GPM_VMID_THREAD0__RESERVED__SHIFT 0x4 #define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf #define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0 #define RLC_GPM_VMID_THREAD1__RESERVED_MASK 0xfffffff0 #define RLC_GPM_VMID_THREAD1__RESERVED__SHIFT 0x4 #define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff #define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1 #define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2 #define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000 #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000 #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d #define RLC_CGCG_CGLS_CTRL__SPARE_MASK 0x80000000 #define RLC_CGCG_CGLS_CTRL__SPARE__SHIFT 0x1f #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00 #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000 #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 #define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff #define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 #define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00 #define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000 #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 #define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000 #define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 #define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff #define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 #define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1 #define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 #define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe #define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 #define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00 #define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000 #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 #define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff #define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00 #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000 #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 #define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000 #define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 #define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00 #define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 #define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1 #define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2 #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4 #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8 #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000 #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1 #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 #define RLC_SMU_PG_CTRL__START_PG_MASK 0x1 #define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0 #define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe #define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1 #define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1 #define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0 #define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe #define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1 #define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf #define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 #define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30 #define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 #define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0 #define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa #define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x3800 #define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0xc000 #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xe #define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xffff0000 #define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x10 #define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff #define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 #define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff #define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 #define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff #define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x20000 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x11 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x40000 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x12 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x80000 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x13 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x100000 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x14 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x200000 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x15 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x400000 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x16 #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff800000 #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x17 #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff #define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 #define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100 #define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 #define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200 #define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 #define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400 #define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa #define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800 #define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb #define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000 #define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc #define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000 #define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd #define RLC_SERDES_WR_CTRL__RESERVED_1_MASK 0xc000 #define RLC_SERDES_WR_CTRL__RESERVED_1__SHIFT 0xe #define RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK 0x10000 #define RLC_SERDES_WR_CTRL__CGLS_ENABLE__SHIFT 0x10 #define RLC_SERDES_WR_CTRL__CGLS_DISABLE_MASK 0x20000 #define RLC_SERDES_WR_CTRL__CGLS_DISABLE__SHIFT 0x11 #define RLC_SERDES_WR_CTRL__CGLS_ON_MASK 0x40000 #define RLC_SERDES_WR_CTRL__CGLS_ON__SHIFT 0x12 #define RLC_SERDES_WR_CTRL__CGLS_OFF_MASK 0x80000 #define RLC_SERDES_WR_CTRL__CGLS_OFF__SHIFT 0x13 #define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK 0x100000 #define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0__SHIFT 0x14 #define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1_MASK 0x200000 #define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1__SHIFT 0x15 #define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK 0x400000 #define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0__SHIFT 0x16 #define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK 0x800000 #define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1__SHIFT 0x17 #define RLC_SERDES_WR_CTRL__RESERVED_2_MASK 0xf000000 #define RLC_SERDES_WR_CTRL__RESERVED_2__SHIFT 0x18 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000 #define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c #define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff #define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x20000 #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x11 #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x40000 #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x12 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x80000 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x13 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x100000 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x14 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x200000 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x15 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x400000 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x16 #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff800000 #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x17 #define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff #define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 #define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff #define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 #define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff #define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 #define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff #define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 #define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff #define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 #define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff #define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 #define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff #define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 #define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff #define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 #define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff #define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0 #define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff #define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 #define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00 #define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 #define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff #define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 #define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0 #define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 #define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00 #define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 #define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000 #define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc #define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000 #define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 #define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000 #define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 #define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000 #define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 #define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000 #define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 #define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0 #define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 #define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00 #define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 #define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000 #define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc #define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000 #define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 #define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000 #define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000 #define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 #define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000 #define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 #define RLC_GPR_REG1__DATA_MASK 0xffffffff #define RLC_GPR_REG1__DATA__SHIFT 0x0 #define RLC_GPR_REG2__DATA_MASK 0xffffffff #define RLC_GPR_REG2__DATA__SHIFT 0x0 #define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf #define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0 #define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0 #define RLC_SPM_VMID__RESERVED__SHIFT 0x4 #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1 #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 #define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe #define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1 #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 #define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe #define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 #define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff #define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0 #define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00 #define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8 #define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000 #define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf #define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000 #define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10 #define RLC_SPM_DEBUG__DATA_MASK 0xffffffff #define RLC_SPM_DEBUG__DATA__SHIFT 0x0 #define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff #define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0 #define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff #define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 #define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff #define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 #define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff #define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000 #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc #define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000 #define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000 #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000 #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800 #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000 #define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 #define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 #define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f #define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa #define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000 #define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 #define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40 #define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1 #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2 #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4 #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8 #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10 #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20 #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40 #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80 #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100 #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200 #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800 #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000 #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc #define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000 #define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000 #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000 #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1 #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2 #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4 #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8 #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10 #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20 #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40 #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80 #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100 #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200 #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800 #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000 #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000 #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000 #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000 #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1 #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 #define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40 #define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000 #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1 #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10 #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100 #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000 #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000 #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 #define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000 #define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000 #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 #define SPI_TMPRING_SIZE__WAVES_MASK 0xfff #define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 #define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 #define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0 #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00 #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000 #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0 #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00 #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000 #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000 #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000 #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000 #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000 #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 #define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000 #define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc #define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000 #define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe #define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000 #define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 #define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000 #define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 #define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff #define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 #define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000 #define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 #define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff #define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 #define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000 #define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 #define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1 #define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0 #define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2 #define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1 #define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4 #define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2 #define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8 #define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3 #define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10 #define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4 #define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20 #define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5 #define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40 #define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6 #define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1 #define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0 #define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2 #define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1 #define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4 #define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2 #define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8 #define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3 #define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10 #define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4 #define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20 #define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5 #define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff #define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0 #define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00 #define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8 #define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000 #define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10 #define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000 #define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18 #define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff #define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0 #define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00 #define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8 #define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000 #define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10 #define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000 #define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18 #define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x1f #define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x1f #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 #define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x1f #define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 #define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x1f #define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 #define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x1f #define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 #define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x1f #define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 #define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x1f #define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 #define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x1f #define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 #define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x1f #define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x1f #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1 #define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 #define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3 #define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0 #define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc #define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2 #define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70 #define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4 #define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80 #define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7 #define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100 #define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8 #define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200 #define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9 #define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000 #define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf #define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000 #define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10 #define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff #define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 #define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200 #define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 #define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff #define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0 #define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff #define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0 #define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff #define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0 #define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff #define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0 #define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff #define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0 #define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff #define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1 #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf #define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0 #define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 #define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00 #define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 #define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000 #define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000 #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf #define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf #define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0 #define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 #define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00 #define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 #define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000 #define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000 #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf #define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf #define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0 #define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 #define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00 #define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 #define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000 #define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000 #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf #define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf #define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0 #define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 #define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00 #define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 #define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000 #define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000 #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf #define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf #define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0 #define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 #define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00 #define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 #define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000 #define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000 #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf #define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0 #define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 #define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00 #define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 #define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000 #define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000 #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf #define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf #define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0 #define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 #define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00 #define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 #define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000 #define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000 #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf #define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf #define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0 #define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 #define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00 #define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 #define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000 #define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000 #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf #define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf #define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0 #define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 #define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00 #define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 #define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000 #define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000 #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf #define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf #define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0 #define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 #define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00 #define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 #define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000 #define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000 #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf #define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0 #define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 #define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00 #define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 #define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000 #define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000 #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf #define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf #define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0 #define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 #define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00 #define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 #define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000 #define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000 #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf #define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000 #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000 #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 #define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000 #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000 #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 #define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000 #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000 #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 #define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000 #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000 #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 #define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000 #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000 #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 #define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000 #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000 #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 #define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000 #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000 #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 #define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000 #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000 #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 #define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000 #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000 #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 #define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000 #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000 #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 #define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000 #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000 #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 #define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000 #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000 #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000 #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000 #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000 #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000 #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000 #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b #define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1 #define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0 #define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe #define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1 #define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0 #define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4 #define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00 #define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa #define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000 #define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18 #define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000 #define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19 #define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000 #define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f #define SPI_DEBUG_READ__DATA_MASK 0xffffff #define SPI_DEBUG_READ__DATA__SHIFT 0x0 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff #define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff #define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff #define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa #define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff #define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 #define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff #define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 #define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf #define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0 #define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 #define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00 #define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000 #define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc #define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000 #define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 #define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000 #define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000 #define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 #define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000 #define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80 #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100 #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000 #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 #define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1 #define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0 #define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2 #define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1 #define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4 #define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2 #define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8 #define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3 #define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10 #define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4 #define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20 #define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5 #define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40 #define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6 #define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80 #define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7 #define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100 #define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8 #define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200 #define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9 #define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400 #define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa #define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800 #define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb #define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000 #define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc #define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000 #define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd #define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000 #define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe #define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000 #define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000 #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10 #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000 #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11 #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000 #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12 #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000 #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13 #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000 #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14 #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000 #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15 #define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000 #define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16 #define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000 #define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17 #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0 #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 #define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000 #define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc #define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000 #define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 #define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000 #define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000 #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 #define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000 #define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 #define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000 #define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f #define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 #define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00 #define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 #define CGTS_RD_REG__READ_DATA_MASK 0x3fff #define CGTS_RD_REG__READ_DATA__SHIFT 0x0 #define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 #define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 #define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 #define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 #define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f #define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f #define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f #define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f #define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f #define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f #define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f #define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f #define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f #define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f #define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f #define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f #define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f #define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f #define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f #define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f #define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000 #define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f #define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0 #define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 #define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 #define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 #define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f #define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000 #define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f #define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa #define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b #define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 #define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000 #define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000 #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000 #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000 #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f #define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 #define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000 #define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19 #define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000 #define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e #define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 #define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f #define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000 #define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000 #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000 #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000 #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 #define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10 #define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000 #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000 #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000 #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000 #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000 #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000 #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000 #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000 #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000 #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000 #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 #define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000 #define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f #define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff #define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0 #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000 #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f #define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1 #define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0 #define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2 #define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1 #define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4 #define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2 #define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8 #define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3 #define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10 #define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10 #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000 #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11 #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000 #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12 #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000 #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13 #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000 #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14 #define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000 #define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15 #define SPI_LB_CTR_CTRL__LOAD_MASK 0x1 #define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 #define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff #define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 #define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff #define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 #define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff #define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 #define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00 #define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 #define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000 #define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000 #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 #define BCI_DEBUG_READ__DATA_MASK 0xffffff #define BCI_DEBUG_READ__DATA__SHIFT 0x0 #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 #define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff #define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff #define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff #define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f #define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0 #define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000 #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc #define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000 #define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000 #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000 #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16 #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000 #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000 #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 #define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000 #define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19 #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000 #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1 #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40 #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80 #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00 #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000 #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 #define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff #define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000 #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 #define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 #define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff #define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff #define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff #define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f #define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0 #define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000 #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc #define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000 #define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000 #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000 #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16 #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000 #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000 #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000 #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a #define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000 #define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000 #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1 #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40 #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80 #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb #define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000 #define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000 #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd #define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff #define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000 #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 #define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f #define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1 #define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e #define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1 #define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40 #define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80 #define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7 #define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00 #define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8 #define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000 #define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14 #define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1 #define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e #define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1 #define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40 #define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80 #define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7 #define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000 #define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10 #define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff #define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff #define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff #define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f #define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0 #define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000 #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc #define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000 #define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000 #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000 #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16 #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000 #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000 #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 #define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000 #define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19 #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000 #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1 #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40 #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80 #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 #define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff #define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000 #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 #define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1 #define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e #define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1 #define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40 #define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80 #define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7 #define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00 #define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8 #define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000 #define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14 #define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff #define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff #define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff #define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f #define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0 #define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00 #define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa #define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000 #define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc #define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000 #define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14 #define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000 #define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15 #define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000 #define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16 #define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000 #define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17 #define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000 #define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18 #define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000 #define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a #define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000 #define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b #define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000 #define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e #define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1 #define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e #define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1 #define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40 #define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80 #define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7 #define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00 #define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8 #define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000 #define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14 #define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff #define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000 #define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10 #define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000 #define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16 #define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1 #define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e #define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1 #define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40 #define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80 #define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7 #define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000 #define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10 #define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff #define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff #define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff #define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f #define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0 #define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000 #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc #define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000 #define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000 #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000 #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16 #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000 #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 #define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000 #define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18 #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000 #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1 #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40 #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80 #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7 #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100 #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8 #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00 #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9 #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0 #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 #define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1 #define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e #define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1 #define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40 #define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80 #define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7 #define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000 #define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10 #define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff #define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff #define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff #define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff #define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f #define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0 #define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00 #define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa #define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000 #define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc #define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000 #define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14 #define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000 #define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15 #define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000 #define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16 #define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000 #define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17 #define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000 #define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18 #define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000 #define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a #define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000 #define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d #define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1 #define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e #define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1 #define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40 #define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6 #define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80 #define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7 #define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000 #define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10 #define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff #define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0 #define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000 #define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10 #define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 #define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16 #define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 #define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff #define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 #define SQ_CONFIG__UNUSED_MASK 0xff #define SQ_CONFIG__UNUSED__SHIFT 0x0 #define SQ_CONFIG__DEBUG_EN_MASK 0x100 #define SQ_CONFIG__DEBUG_EN__SHIFT 0x8 #define SQ_CONFIG__DISABLE_SCA_BYPASS_MASK 0x200 #define SQ_CONFIG__DISABLE_SCA_BYPASS__SHIFT 0x9 #define SQ_CONFIG__DISABLE_IB_DEP_CHECK_MASK 0x400 #define SQ_CONFIG__DISABLE_IB_DEP_CHECK__SHIFT 0xa #define SQ_CONFIG__ENABLE_SOFT_CLAUSE_MASK 0x800 #define SQ_CONFIG__ENABLE_SOFT_CLAUSE__SHIFT 0xb #define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000 #define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000 #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000 #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000 #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf #define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3 #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 #define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc #define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 #define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30 #define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 #define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40 #define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 #define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80 #define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 #define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100 #define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 #define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200 #define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 #define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400 #define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa #define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800 #define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb #define SQC_CACHES__INST_INVALIDATE_MASK 0x1 #define SQC_CACHES__INST_INVALIDATE__SHIFT 0x0 #define SQC_CACHES__DATA_INVALIDATE_MASK 0x2 #define SQC_CACHES__DATA_INVALIDATE__SHIFT 0x1 #define SQC_CACHES__INVALIDATE_VOLATILE_MASK 0x4 #define SQC_CACHES__INVALIDATE_VOLATILE__SHIFT 0x2 #define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f #define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 #define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380 #define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 #define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00 #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa #define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f #define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 #define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00 #define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 #define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000 #define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c #define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000 #define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d #define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000 #define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e #define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000 #define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00 #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000 #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000 #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 #define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff #define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 #define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1 #define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 #define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1 #define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 #define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2 #define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 #define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4 #define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 #define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8 #define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 #define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10 #define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 #define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20 #define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 #define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40 #define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 #define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00 #define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000 #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd #define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff #define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 #define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000 #define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1 #define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 #define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 #define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 #define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 #define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 #define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 #define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 #define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 #define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c #define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 #define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 #define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 #define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 #define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 #define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 #define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 #define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c #define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0xff #define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000 #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 #define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000 #define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000 #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 #define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000 #define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c #define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f #define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 #define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff #define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 #define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000 #define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 #define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000 #define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b #define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000 #define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f #define SQ_TIME_HI__TIME_MASK 0xffffffff #define SQ_TIME_HI__TIME__SHIFT 0x0 #define SQ_TIME_LO__TIME_MASK 0xffffffff #define SQ_TIME_LO__TIME__SHIFT 0x0 #define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff #define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 #define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf #define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 #define SQ_THREAD_TRACE_BASE2__ATC_MASK 0x10 #define SQ_THREAD_TRACE_BASE2__ATC__SHIFT 0x4 #define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff #define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 #define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f #define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 #define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20 #define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 #define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80 #define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 #define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00 #define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 #define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000 #define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000 #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000 #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf #define SQ_THREAD_TRACE_MASK__RANDOM_SEED_MASK 0xffff0000 #define SQ_THREAD_TRACE_MASK__RANDOM_SEED__SHIFT 0x10 #define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff #define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 #define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff #define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 #define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff #define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 #define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff #define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 #define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7 #define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 #define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38 #define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 #define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0 #define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 #define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00 #define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 #define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000 #define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc #define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000 #define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf #define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000 #define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 #define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000 #define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000 #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000 #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 #define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000 #define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a #define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000 #define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b #define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000 #define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000 #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e #define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000 #define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000 #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffff #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000 #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 #define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff #define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 #define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000 #define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 #define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000 #define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 #define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000 #define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d #define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000 #define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e #define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000 #define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f #define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff #define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 #define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7 #define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 #define SQ_LB_CTR_CTRL__START_MASK 0x1 #define SQ_LB_CTR_CTRL__START__SHIFT 0x0 #define SQ_LB_CTR_CTRL__LOAD_MASK 0x2 #define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 #define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4 #define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 #define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff #define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0 #define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff #define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0 #define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff #define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0 #define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff #define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0 #define SQC_SECDED_CNT__INST_SEC_MASK 0xff #define SQC_SECDED_CNT__INST_SEC__SHIFT 0x0 #define SQC_SECDED_CNT__INST_DED_MASK 0xff00 #define SQC_SECDED_CNT__INST_DED__SHIFT 0x8 #define SQC_SECDED_CNT__DATA_SEC_MASK 0xff0000 #define SQC_SECDED_CNT__DATA_SEC__SHIFT 0x10 #define SQC_SECDED_CNT__DATA_DED_MASK 0xff000000 #define SQC_SECDED_CNT__DATA_DED__SHIFT 0x18 #define SQ_SEC_CNT__LDS_SEC_MASK 0x3f #define SQ_SEC_CNT__LDS_SEC__SHIFT 0x0 #define SQ_SEC_CNT__SGPR_SEC_MASK 0x1f00 #define SQ_SEC_CNT__SGPR_SEC__SHIFT 0x8 #define SQ_SEC_CNT__VGPR_SEC_MASK 0x1ff0000 #define SQ_SEC_CNT__VGPR_SEC__SHIFT 0x10 #define SQ_DED_CNT__LDS_DED_MASK 0x3f #define SQ_DED_CNT__LDS_DED__SHIFT 0x0 #define SQ_DED_CNT__SGPR_DED_MASK 0x1f00 #define SQ_DED_CNT__SGPR_DED__SHIFT 0x8 #define SQ_DED_CNT__VGPR_DED_MASK 0x1ff0000 #define SQ_DED_CNT__VGPR_DED__SHIFT 0x10 #define SQ_DED_INFO__WAVE_ID_MASK 0xf #define SQ_DED_INFO__WAVE_ID__SHIFT 0x0 #define SQ_DED_INFO__SIMD_ID_MASK 0x30 #define SQ_DED_INFO__SIMD_ID__SHIFT 0x4 #define SQ_DED_INFO__SOURCE_MASK 0x1c0 #define SQ_DED_INFO__SOURCE__SHIFT 0x6 #define SQ_DED_INFO__VM_ID_MASK 0x1e00 #define SQ_DED_INFO__VM_ID__SHIFT 0x9 #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 #define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000 #define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000 #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000 #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff #define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 #define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7 #define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 #define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38 #define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 #define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 #define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 #define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00 #define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 #define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000 #define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc #define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000 #define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf #define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000 #define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13 #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000 #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000 #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 #define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000 #define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18 #define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000 #define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19 #define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000 #define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a #define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000 #define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b #define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000 #define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 #define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00 #define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 #define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000 #define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 #define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000 #define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a #define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000 #define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e #define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff #define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 #define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000 #define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe #define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000 #define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c #define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000 #define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f #define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7 #define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 #define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38 #define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 #define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 #define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 #define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00 #define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 #define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000 #define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc #define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000 #define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 #define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000 #define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14 #define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000 #define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19 #define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000 #define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a #define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000 #define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b #define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000 #define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c #define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff #define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 #define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000 #define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd #define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff #define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 #define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000 #define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000 #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000 #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 #define SQ_IMG_RSRC_WORD6__UNUNSED_MASK 0xffe00000 #define SQ_IMG_RSRC_WORD6__UNUNSED__SHIFT 0x15 #define SQ_IMG_RSRC_WORD7__UNUNSED_MASK 0xffffffff #define SQ_IMG_RSRC_WORD7__UNUNSED__SHIFT 0x0 #define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7 #define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 #define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38 #define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 #define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0 #define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00 #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000 #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000 #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000 #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000 #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000 #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 #define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000 #define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 #define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000 #define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000 #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c #define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000 #define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d #define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff #define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 #define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000 #define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc #define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000 #define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 #define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000 #define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c #define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff #define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000 #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000 #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 #define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000 #define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 #define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000 #define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000 #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c #define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000 #define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000 #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e #define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff #define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 #define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff #define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 #define SQ_IND_INDEX__WAVE_ID_MASK 0xf #define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 #define SQ_IND_INDEX__SIMD_ID_MASK 0x30 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 #define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0 #define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 #define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000 #define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc #define SQ_IND_INDEX__FORCE_READ_MASK 0x2000 #define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd #define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000 #define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe #define SQ_IND_INDEX__UNINDEXED_MASK 0x8000 #define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf #define SQ_IND_INDEX__INDEX_MASK 0xffff0000 #define SQ_IND_INDEX__INDEX__SHIFT 0x10 #define SQ_CMD__CMD_MASK 0x7 #define SQ_CMD__CMD__SHIFT 0x0 #define SQ_CMD__MODE_MASK 0x70 #define SQ_CMD__MODE__SHIFT 0x4 #define SQ_CMD__CHECK_VMID_MASK 0x80 #define SQ_CMD__CHECK_VMID__SHIFT 0x7 #define SQ_CMD__TRAP_ID_MASK 0x700 #define SQ_CMD__TRAP_ID__SHIFT 0x8 #define SQ_CMD__WAVE_ID_MASK 0xf0000 #define SQ_CMD__WAVE_ID__SHIFT 0x10 #define SQ_CMD__SIMD_ID_MASK 0x300000 #define SQ_CMD__SIMD_ID__SHIFT 0x14 #define SQ_CMD__QUEUE_ID_MASK 0x7000000 #define SQ_CMD__QUEUE_ID__SHIFT 0x18 #define SQ_CMD__VM_ID_MASK 0xf0000000 #define SQ_CMD__VM_ID__SHIFT 0x1c #define SQ_IND_DATA__DATA_MASK 0xffffffff #define SQ_IND_DATA__DATA__SHIFT 0x0 #define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff #define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 #define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff #define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 #define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf #define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0 #define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0 #define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4 #define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff #define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 #define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff #define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 #define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff #define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 #define SQ_WAVE_PC_HI__PC_HI_MASK 0xff #define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 #define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7 #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 #define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8 #define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10 #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 #define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300 #define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 #define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00 #define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa #define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x70000 #define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 #define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0x380000 #define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x13 #define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0xc00000 #define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x16 #define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x1000000 #define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x18 #define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x6000000 #define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x19 #define SQ_WAVE_IB_DBG0__KILL_MASK 0x8000000 #define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1b #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x10000000 #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1c #define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff #define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 #define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff #define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 #define SQ_WAVE_STATUS__SCC_MASK 0x1 #define SQ_WAVE_STATUS__SCC__SHIFT 0x0 #define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6 #define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 #define SQ_WAVE_STATUS__WAVE_PRIO_MASK 0x18 #define SQ_WAVE_STATUS__WAVE_PRIO__SHIFT 0x3 #define SQ_WAVE_STATUS__PRIV_MASK 0x20 #define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 #define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40 #define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 #define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80 #define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 #define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100 #define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 #define SQ_WAVE_STATUS__EXECZ_MASK 0x200 #define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 #define SQ_WAVE_STATUS__VCCZ_MASK 0x400 #define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa #define SQ_WAVE_STATUS__IN_TG_MASK 0x800 #define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb #define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000 #define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc #define SQ_WAVE_STATUS__HALT_MASK 0x2000 #define SQ_WAVE_STATUS__HALT__SHIFT 0xd #define SQ_WAVE_STATUS__TRAP_MASK 0x4000 #define SQ_WAVE_STATUS__TRAP__SHIFT 0xe #define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000 #define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf #define SQ_WAVE_STATUS__VALID_MASK 0x10000 #define SQ_WAVE_STATUS__VALID__SHIFT 0x10 #define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000 #define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 #define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000 #define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 #define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000 #define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 #define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000 #define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14 #define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000 #define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15 #define SQ_WAVE_STATUS__DATA_ATC_MASK 0x400000 #define SQ_WAVE_STATUS__DATA_ATC__SHIFT 0x16 #define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000 #define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17 #define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL_MASK 0x7000000 #define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL__SHIFT 0x18 #define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000 #define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b #define SQ_WAVE_MODE__FP_ROUND_MASK 0xf #define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 #define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0 #define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 #define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100 #define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 #define SQ_WAVE_MODE__IEEE_MASK 0x200 #define SQ_WAVE_MODE__IEEE__SHIFT 0x9 #define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400 #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa #define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800 #define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb #define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000 #define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc #define SQ_WAVE_MODE__VSKIP_MASK 0x10000000 #define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c #define SQ_WAVE_MODE__CSP_MASK 0xe0000000 #define SQ_WAVE_MODE__CSP__SHIFT 0x1d #define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff #define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 #define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000 #define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 #define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000 #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d #define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf #define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 #define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30 #define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 #define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0 #define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 #define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00 #define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 #define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000 #define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc #define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000 #define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd #define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000 #define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 #define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000 #define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 #define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000 #define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 #define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000 #define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b #define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000 #define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e #define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f #define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00 #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 #define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000 #define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000 #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 #define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff #define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 #define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000 #define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc #define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf #define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 #define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70 #define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 #define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00 #define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 #define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000 #define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc #define SQ_WAVE_M0__M0_MASK 0xffffffff #define SQ_WAVE_M0__M0__SHIFT 0x0 #define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff #define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0 #define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff #define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0 #define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff #define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0 #define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff #define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0 #define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff #define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 #define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff #define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 #define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff #define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 #define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff #define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 #define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff #define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 #define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff #define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 #define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff #define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 #define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff #define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 #define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff #define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 #define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff #define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 #define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff #define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 #define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff #define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1 #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2 #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0xf0 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4 #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1 #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0 #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 #define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff #define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 #define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff #define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 #define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000 #define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 #define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff #define SH_MEM_APE1_BASE__BASE__SHIFT 0x0 #define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff #define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0 #define SH_MEM_CONFIG__PTR32_MASK 0x1 #define SH_MEM_CONFIG__PTR32__SHIFT 0x0 #define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x2 #define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x1 #define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0xc #define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x2 #define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0x70 #define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x4 #define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x380 #define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x7 #define SQC_POLICY__DATA_L1_POLICY_0_MASK 0x1 #define SQC_POLICY__DATA_L1_POLICY_0__SHIFT 0x0 #define SQC_POLICY__DATA_L1_POLICY_1_MASK 0x2 #define SQC_POLICY__DATA_L1_POLICY_1__SHIFT 0x1 #define SQC_POLICY__DATA_L1_POLICY_2_MASK 0x4 #define SQC_POLICY__DATA_L1_POLICY_2__SHIFT 0x2 #define SQC_POLICY__DATA_L1_POLICY_3_MASK 0x8 #define SQC_POLICY__DATA_L1_POLICY_3__SHIFT 0x3 #define SQC_POLICY__DATA_L1_POLICY_4_MASK 0x10 #define SQC_POLICY__DATA_L1_POLICY_4__SHIFT 0x4 #define SQC_POLICY__DATA_L1_POLICY_5_MASK 0x20 #define SQC_POLICY__DATA_L1_POLICY_5__SHIFT 0x5 #define SQC_POLICY__DATA_L1_POLICY_6_MASK 0x40 #define SQC_POLICY__DATA_L1_POLICY_6__SHIFT 0x6 #define SQC_POLICY__DATA_L1_POLICY_7_MASK 0x80 #define SQC_POLICY__DATA_L1_POLICY_7__SHIFT 0x7 #define SQC_POLICY__DATA_L2_POLICY_0_MASK 0x300 #define SQC_POLICY__DATA_L2_POLICY_0__SHIFT 0x8 #define SQC_POLICY__DATA_L2_POLICY_1_MASK 0xc00 #define SQC_POLICY__DATA_L2_POLICY_1__SHIFT 0xa #define SQC_POLICY__DATA_L2_POLICY_2_MASK 0x3000 #define SQC_POLICY__DATA_L2_POLICY_2__SHIFT 0xc #define SQC_POLICY__DATA_L2_POLICY_3_MASK 0xc000 #define SQC_POLICY__DATA_L2_POLICY_3__SHIFT 0xe #define SQC_POLICY__DATA_L2_POLICY_4_MASK 0x30000 #define SQC_POLICY__DATA_L2_POLICY_4__SHIFT 0x10 #define SQC_POLICY__DATA_L2_POLICY_5_MASK 0xc0000 #define SQC_POLICY__DATA_L2_POLICY_5__SHIFT 0x12 #define SQC_POLICY__DATA_L2_POLICY_6_MASK 0x300000 #define SQC_POLICY__DATA_L2_POLICY_6__SHIFT 0x14 #define SQC_POLICY__DATA_L2_POLICY_7_MASK 0xc00000 #define SQC_POLICY__DATA_L2_POLICY_7__SHIFT 0x16 #define SQC_POLICY__INST_L2_POLICY_MASK 0x3000000 #define SQC_POLICY__INST_L2_POLICY__SHIFT 0x18 #define SQC_VOLATILE__DATA_L1_MASK 0xf #define SQC_VOLATILE__DATA_L1__SHIFT 0x0 #define SQC_VOLATILE__DATA_L2_MASK 0xf0 #define SQC_VOLATILE__DATA_L2__SHIFT 0x4 #define SQC_VOLATILE__INST_L2_MASK 0x100 #define SQC_VOLATILE__INST_L2__SHIFT 0x8 #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10 #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10 #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0 #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600 #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 #define SQ_THREAD_TRACE_WORD_INST__SIZE_MASK 0x800 #define SQ_THREAD_TRACE_WORD_INST__SIZE__SHIFT 0xb #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf000 #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xc #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10 #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20 #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0 #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00 #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000 #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0 #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 #define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000 #define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000 #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10 #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20 #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0 #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00 #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000 #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000 #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000 #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000 #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000 #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10 #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20 #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 #define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0 #define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00 #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10 #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60 #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 #define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300 #define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 #define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00 #define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa #define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000 #define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc #define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000 #define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe #define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000 #define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 #define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000 #define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 #define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000 #define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 #define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000 #define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 #define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000 #define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 #define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000 #define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 #define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000 #define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18 #define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000 #define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0 #define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2 #define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 #define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8 #define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3 #define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10 #define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4 #define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20 #define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5 #define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40 #define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6 #define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80 #define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7 #define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000 #define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18 #define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000 #define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a #define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff #define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0 #define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100 #define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8 #define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200 #define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9 #define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00 #define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000 #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000 #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12 #define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000 #define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14 #define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000 #define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18 #define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000 #define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a #define SQ_SOP2__SSRC0_MASK 0xff #define SQ_SOP2__SSRC0__SHIFT 0x0 #define SQ_SOP2__SSRC1_MASK 0xff00 #define SQ_SOP2__SSRC1__SHIFT 0x8 #define SQ_SOP2__SDST_MASK 0x7f0000 #define SQ_SOP2__SDST__SHIFT 0x10 #define SQ_SOP2__OP_MASK 0x3f800000 #define SQ_SOP2__OP__SHIFT 0x17 #define SQ_SOP2__ENCODING_MASK 0xc0000000 #define SQ_SOP2__ENCODING__SHIFT 0x1e #define SQ_VOP1__SRC0_MASK 0x1ff #define SQ_VOP1__SRC0__SHIFT 0x0 #define SQ_VOP1__OP_MASK 0x1fe00 #define SQ_VOP1__OP__SHIFT 0x9 #define SQ_VOP1__VDST_MASK 0x1fe0000 #define SQ_VOP1__VDST__SHIFT 0x11 #define SQ_VOP1__ENCODING_MASK 0xfe000000 #define SQ_VOP1__ENCODING__SHIFT 0x19 #define SQ_MTBUF_1__VADDR_MASK 0xff #define SQ_MTBUF_1__VADDR__SHIFT 0x0 #define SQ_MTBUF_1__VDATA_MASK 0xff00 #define SQ_MTBUF_1__VDATA__SHIFT 0x8 #define SQ_MTBUF_1__SRSRC_MASK 0x1f0000 #define SQ_MTBUF_1__SRSRC__SHIFT 0x10 #define SQ_MTBUF_1__SLC_MASK 0x400000 #define SQ_MTBUF_1__SLC__SHIFT 0x16 #define SQ_MTBUF_1__TFE_MASK 0x800000 #define SQ_MTBUF_1__TFE__SHIFT 0x17 #define SQ_MTBUF_1__SOFFSET_MASK 0xff000000 #define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 #define SQ_EXP_1__VSRC0_MASK 0xff #define SQ_EXP_1__VSRC0__SHIFT 0x0 #define SQ_EXP_1__VSRC1_MASK 0xff00 #define SQ_EXP_1__VSRC1__SHIFT 0x8 #define SQ_EXP_1__VSRC2_MASK 0xff0000 #define SQ_EXP_1__VSRC2__SHIFT 0x10 #define SQ_EXP_1__VSRC3_MASK 0xff000000 #define SQ_EXP_1__VSRC3__SHIFT 0x18 #define SQ_MUBUF_1__VADDR_MASK 0xff #define SQ_MUBUF_1__VADDR__SHIFT 0x0 #define SQ_MUBUF_1__VDATA_MASK 0xff00 #define SQ_MUBUF_1__VDATA__SHIFT 0x8 #define SQ_MUBUF_1__SRSRC_MASK 0x1f0000 #define SQ_MUBUF_1__SRSRC__SHIFT 0x10 #define SQ_MUBUF_1__SLC_MASK 0x400000 #define SQ_MUBUF_1__SLC__SHIFT 0x16 #define SQ_MUBUF_1__TFE_MASK 0x800000 #define SQ_MUBUF_1__TFE__SHIFT 0x17 #define SQ_MUBUF_1__SOFFSET_MASK 0xff000000 #define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 #define SQ_INST__ENCODING_MASK 0xffffffff #define SQ_INST__ENCODING__SHIFT 0x0 #define SQ_EXP_0__EN_MASK 0xf #define SQ_EXP_0__EN__SHIFT 0x0 #define SQ_EXP_0__TGT_MASK 0x3f0 #define SQ_EXP_0__TGT__SHIFT 0x4 #define SQ_EXP_0__COMPR_MASK 0x400 #define SQ_EXP_0__COMPR__SHIFT 0xa #define SQ_EXP_0__DONE_MASK 0x800 #define SQ_EXP_0__DONE__SHIFT 0xb #define SQ_EXP_0__VM_MASK 0x1000 #define SQ_EXP_0__VM__SHIFT 0xc #define SQ_EXP_0__ENCODING_MASK 0xfc000000 #define SQ_EXP_0__ENCODING__SHIFT 0x1a #define SQ_MUBUF_0__OFFSET_MASK 0xfff #define SQ_MUBUF_0__OFFSET__SHIFT 0x0 #define SQ_MUBUF_0__OFFEN_MASK 0x1000 #define SQ_MUBUF_0__OFFEN__SHIFT 0xc #define SQ_MUBUF_0__IDXEN_MASK 0x2000 #define SQ_MUBUF_0__IDXEN__SHIFT 0xd #define SQ_MUBUF_0__GLC_MASK 0x4000 #define SQ_MUBUF_0__GLC__SHIFT 0xe #define SQ_MUBUF_0__ADDR64_MASK 0x8000 #define SQ_MUBUF_0__ADDR64__SHIFT 0xf #define SQ_MUBUF_0__LDS_MASK 0x10000 #define SQ_MUBUF_0__LDS__SHIFT 0x10 #define SQ_MUBUF_0__OP_MASK 0x1fc0000 #define SQ_MUBUF_0__OP__SHIFT 0x12 #define SQ_MUBUF_0__ENCODING_MASK 0xfc000000 #define SQ_MUBUF_0__ENCODING__SHIFT 0x1a #define SQ_VOP3_0__VDST_MASK 0xff #define SQ_VOP3_0__VDST__SHIFT 0x0 #define SQ_VOP3_0__ABS_MASK 0x700 #define SQ_VOP3_0__ABS__SHIFT 0x8 #define SQ_VOP3_0__CLAMP_MASK 0x800 #define SQ_VOP3_0__CLAMP__SHIFT 0xb #define SQ_VOP3_0__OP_MASK 0x3fe0000 #define SQ_VOP3_0__OP__SHIFT 0x11 #define SQ_VOP3_0__ENCODING_MASK 0xfc000000 #define SQ_VOP3_0__ENCODING__SHIFT 0x1a #define SQ_VOP2__SRC0_MASK 0x1ff #define SQ_VOP2__SRC0__SHIFT 0x0 #define SQ_VOP2__VSRC1_MASK 0x1fe00 #define SQ_VOP2__VSRC1__SHIFT 0x9 #define SQ_VOP2__VDST_MASK 0x1fe0000 #define SQ_VOP2__VDST__SHIFT 0x11 #define SQ_VOP2__OP_MASK 0x7e000000 #define SQ_VOP2__OP__SHIFT 0x19 #define SQ_VOP2__ENCODING_MASK 0x80000000 #define SQ_VOP2__ENCODING__SHIFT 0x1f #define SQ_MTBUF_0__OFFSET_MASK 0xfff #define SQ_MTBUF_0__OFFSET__SHIFT 0x0 #define SQ_MTBUF_0__OFFEN_MASK 0x1000 #define SQ_MTBUF_0__OFFEN__SHIFT 0xc #define SQ_MTBUF_0__IDXEN_MASK 0x2000 #define SQ_MTBUF_0__IDXEN__SHIFT 0xd #define SQ_MTBUF_0__GLC_MASK 0x4000 #define SQ_MTBUF_0__GLC__SHIFT 0xe #define SQ_MTBUF_0__ADDR64_MASK 0x8000 #define SQ_MTBUF_0__ADDR64__SHIFT 0xf #define SQ_MTBUF_0__OP_MASK 0x70000 #define SQ_MTBUF_0__OP__SHIFT 0x10 #define SQ_MTBUF_0__DFMT_MASK 0x780000 #define SQ_MTBUF_0__DFMT__SHIFT 0x13 #define SQ_MTBUF_0__NFMT_MASK 0x3800000 #define SQ_MTBUF_0__NFMT__SHIFT 0x17 #define SQ_MTBUF_0__ENCODING_MASK 0xfc000000 #define SQ_MTBUF_0__ENCODING__SHIFT 0x1a #define SQ_SOPP__SIMM16_MASK 0xffff #define SQ_SOPP__SIMM16__SHIFT 0x0 #define SQ_SOPP__OP_MASK 0x7f0000 #define SQ_SOPP__OP__SHIFT 0x10 #define SQ_SOPP__ENCODING_MASK 0xff800000 #define SQ_SOPP__ENCODING__SHIFT 0x17 #define SQ_FLAT_0__GLC_MASK 0x10000 #define SQ_FLAT_0__GLC__SHIFT 0x10 #define SQ_FLAT_0__SLC_MASK 0x20000 #define SQ_FLAT_0__SLC__SHIFT 0x11 #define SQ_FLAT_0__OP_MASK 0x1fc0000 #define SQ_FLAT_0__OP__SHIFT 0x12 #define SQ_FLAT_0__ENCODING_MASK 0xfc000000 #define SQ_FLAT_0__ENCODING__SHIFT 0x1a #define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff #define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 #define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00 #define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 #define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3fe0000 #define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x11 #define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000 #define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a #define SQ_MIMG_1__VADDR_MASK 0xff #define SQ_MIMG_1__VADDR__SHIFT 0x0 #define SQ_MIMG_1__VDATA_MASK 0xff00 #define SQ_MIMG_1__VDATA__SHIFT 0x8 #define SQ_MIMG_1__SRSRC_MASK 0x1f0000 #define SQ_MIMG_1__SRSRC__SHIFT 0x10 #define SQ_MIMG_1__SSAMP_MASK 0x3e00000 #define SQ_MIMG_1__SSAMP__SHIFT 0x15 #define SQ_SMRD__OFFSET_MASK 0xff #define SQ_SMRD__OFFSET__SHIFT 0x0 #define SQ_SMRD__IMM_MASK 0x100 #define SQ_SMRD__IMM__SHIFT 0x8 #define SQ_SMRD__SBASE_MASK 0x7e00 #define SQ_SMRD__SBASE__SHIFT 0x9 #define SQ_SMRD__SDST_MASK 0x3f8000 #define SQ_SMRD__SDST__SHIFT 0xf #define SQ_SMRD__OP_MASK 0x7c00000 #define SQ_SMRD__OP__SHIFT 0x16 #define SQ_SMRD__ENCODING_MASK 0xf8000000 #define SQ_SMRD__ENCODING__SHIFT 0x1b #define SQ_SOP1__SSRC0_MASK 0xff #define SQ_SOP1__SSRC0__SHIFT 0x0 #define SQ_SOP1__OP_MASK 0xff00 #define SQ_SOP1__OP__SHIFT 0x8 #define SQ_SOP1__SDST_MASK 0x7f0000 #define SQ_SOP1__SDST__SHIFT 0x10 #define SQ_SOP1__ENCODING_MASK 0xff800000 #define SQ_SOP1__ENCODING__SHIFT 0x17 #define SQ_SOPC__SSRC0_MASK 0xff #define SQ_SOPC__SSRC0__SHIFT 0x0 #define SQ_SOPC__SSRC1_MASK 0xff00 #define SQ_SOPC__SSRC1__SHIFT 0x8 #define SQ_SOPC__OP_MASK 0x7f0000 #define SQ_SOPC__OP__SHIFT 0x10 #define SQ_SOPC__ENCODING_MASK 0xff800000 #define SQ_SOPC__ENCODING__SHIFT 0x17 #define SQ_FLAT_1__ADDR_MASK 0xff #define SQ_FLAT_1__ADDR__SHIFT 0x0 #define SQ_FLAT_1__DATA_MASK 0xff00 #define SQ_FLAT_1__DATA__SHIFT 0x8 #define SQ_FLAT_1__TFE_MASK 0x800000 #define SQ_FLAT_1__TFE__SHIFT 0x17 #define SQ_FLAT_1__VDST_MASK 0xff000000 #define SQ_FLAT_1__VDST__SHIFT 0x18 #define SQ_DS_1__ADDR_MASK 0xff #define SQ_DS_1__ADDR__SHIFT 0x0 #define SQ_DS_1__DATA0_MASK 0xff00 #define SQ_DS_1__DATA0__SHIFT 0x8 #define SQ_DS_1__DATA1_MASK 0xff0000 #define SQ_DS_1__DATA1__SHIFT 0x10 #define SQ_DS_1__VDST_MASK 0xff000000 #define SQ_DS_1__VDST__SHIFT 0x18 #define SQ_VOP3_1__SRC0_MASK 0x1ff #define SQ_VOP3_1__SRC0__SHIFT 0x0 #define SQ_VOP3_1__SRC1_MASK 0x3fe00 #define SQ_VOP3_1__SRC1__SHIFT 0x9 #define SQ_VOP3_1__SRC2_MASK 0x7fc0000 #define SQ_VOP3_1__SRC2__SHIFT 0x12 #define SQ_VOP3_1__OMOD_MASK 0x18000000 #define SQ_VOP3_1__OMOD__SHIFT 0x1b #define SQ_VOP3_1__NEG_MASK 0xe0000000 #define SQ_VOP3_1__NEG__SHIFT 0x1d #define SQ_MIMG_0__DMASK_MASK 0xf00 #define SQ_MIMG_0__DMASK__SHIFT 0x8 #define SQ_MIMG_0__UNORM_MASK 0x1000 #define SQ_MIMG_0__UNORM__SHIFT 0xc #define SQ_MIMG_0__GLC_MASK 0x2000 #define SQ_MIMG_0__GLC__SHIFT 0xd #define SQ_MIMG_0__DA_MASK 0x4000 #define SQ_MIMG_0__DA__SHIFT 0xe #define SQ_MIMG_0__R128_MASK 0x8000 #define SQ_MIMG_0__R128__SHIFT 0xf #define SQ_MIMG_0__TFE_MASK 0x10000 #define SQ_MIMG_0__TFE__SHIFT 0x10 #define SQ_MIMG_0__LWE_MASK 0x20000 #define SQ_MIMG_0__LWE__SHIFT 0x11 #define SQ_MIMG_0__OP_MASK 0x1fc0000 #define SQ_MIMG_0__OP__SHIFT 0x12 #define SQ_MIMG_0__SLC_MASK 0x2000000 #define SQ_MIMG_0__SLC__SHIFT 0x19 #define SQ_MIMG_0__ENCODING_MASK 0xfc000000 #define SQ_MIMG_0__ENCODING__SHIFT 0x1a #define SQ_SOPK__SIMM16_MASK 0xffff #define SQ_SOPK__SIMM16__SHIFT 0x0 #define SQ_SOPK__SDST_MASK 0x7f0000 #define SQ_SOPK__SDST__SHIFT 0x10 #define SQ_SOPK__OP_MASK 0xf800000 #define SQ_SOPK__OP__SHIFT 0x17 #define SQ_SOPK__ENCODING_MASK 0xf0000000 #define SQ_SOPK__ENCODING__SHIFT 0x1c #define SQ_DS_0__OFFSET0_MASK 0xff #define SQ_DS_0__OFFSET0__SHIFT 0x0 #define SQ_DS_0__OFFSET1_MASK 0xff00 #define SQ_DS_0__OFFSET1__SHIFT 0x8 #define SQ_DS_0__GDS_MASK 0x20000 #define SQ_DS_0__GDS__SHIFT 0x11 #define SQ_DS_0__OP_MASK 0x3fc0000 #define SQ_DS_0__OP__SHIFT 0x12 #define SQ_DS_0__ENCODING_MASK 0xfc000000 #define SQ_DS_0__ENCODING__SHIFT 0x1a #define SQ_VOPC__SRC0_MASK 0x1ff #define SQ_VOPC__SRC0__SHIFT 0x0 #define SQ_VOPC__VSRC1_MASK 0x1fe00 #define SQ_VOPC__VSRC1__SHIFT 0x9 #define SQ_VOPC__OP_MASK 0x1fe0000 #define SQ_VOPC__OP__SHIFT 0x11 #define SQ_VOPC__ENCODING_MASK 0xfe000000 #define SQ_VOPC__ENCODING__SHIFT 0x19 #define SQ_VINTRP__VSRC_MASK 0xff #define SQ_VINTRP__VSRC__SHIFT 0x0 #define SQ_VINTRP__ATTRCHAN_MASK 0x300 #define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 #define SQ_VINTRP__ATTR_MASK 0xfc00 #define SQ_VINTRP__ATTR__SHIFT 0xa #define SQ_VINTRP__OP_MASK 0x30000 #define SQ_VINTRP__OP__SHIFT 0x10 #define SQ_VINTRP__VDST_MASK 0x3fc0000 #define SQ_VINTRP__VDST__SHIFT 0x12 #define SQ_VINTRP__ENCODING_MASK 0xfc000000 #define SQ_VINTRP__ENCODING__SHIFT 0x1a #define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf #define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000 #define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f #define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf #define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000 #define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x1000000 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f #define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf #define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000 #define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x1000000 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f #define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf #define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000 #define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x1000000 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f #define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf #define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000 #define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x1000000 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x18 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1 #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0 #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2 #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1 #define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4 #define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2 #define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8 #define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3 #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10 #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4 #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20 #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5 #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40 #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6 #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80 #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7 #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100 #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8 #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200 #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9 #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400 #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800 #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000 #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000 #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000 #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000 #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000 #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10 #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000 #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11 #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000 #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12 #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000 #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13 #define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000 #define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a #define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000 #define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b #define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000 #define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c #define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000 #define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d #define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000 #define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e #define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000 #define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f #define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1 #define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0 #define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2 #define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1 #define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4 #define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2 #define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8 #define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3 #define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10 #define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4 #define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20 #define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5 #define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40 #define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6 #define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80 #define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7 #define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100 #define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8 #define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200 #define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9 #define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400 #define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa #define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800 #define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb #define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000 #define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc #define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000 #define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd #define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000 #define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe #define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000 #define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf #define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000 #define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10 #define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000 #define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11 #define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000 #define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12 #define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000 #define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13 #define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000 #define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14 #define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000 #define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15 #define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000 #define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16 #define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000 #define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17 #define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000 #define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18 #define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000 #define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19 #define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f #define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 #define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80 #define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x7 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa #define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa #define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 #define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa #define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 #define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa #define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 #define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCC_CTRL__CACHE_SIZE_MASK 0x3 #define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 #define TCC_CTRL__RATE_MASK 0xc #define TCC_CTRL__RATE__SHIFT 0x2 #define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0 #define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 #define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000 #define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc #define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000 #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 #define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000 #define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14 #define TCC_EDC_COUNTER__SEC_COUNT_MASK 0xf #define TCC_EDC_COUNTER__SEC_COUNT__SHIFT 0x0 #define TCC_EDC_COUNTER__DED_COUNT_MASK 0xf0000 #define TCC_EDC_COUNTER__DED_COUNT__SHIFT 0x10 #define TCC_REDUNDANCY__MC_SEL0_MASK 0x1 #define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 #define TCC_REDUNDANCY__MC_SEL1_MASK 0x2 #define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 #define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf #define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f #define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf #define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f #define TCS_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf #define TCS_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 #define TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 #define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f #define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff #define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff #define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c #define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff #define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 #define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 #define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c #define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff #define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 #define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 #define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf #define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff #define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c #define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff #define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c #define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff #define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 #define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 #define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c #define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff #define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 #define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 #define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCS_CTRL__RATE_MASK 0x3 #define TCS_CTRL__RATE__SHIFT 0x0 #define TCS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff #define TCS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define TCS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 #define TCS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define TCS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define TCS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define TCS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 #define TCS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 #define TCS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 #define TCS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c #define TCS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff #define TCS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define TCS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 #define TCS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define TCS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 #define TCS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 #define TCS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 #define TCS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c #define TCS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff #define TCS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define TCS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 #define TCS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 #define TCS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 #define TCS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c #define TCS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff #define TCS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 #define TCS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 #define TCS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 #define TCS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 #define TCS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c #define TCS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff #define TCS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 #define TCS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 #define TCS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 #define TCS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 #define TCS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c #define TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff #define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 #define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff #define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 #define TD_CNTL__SYNC_PHASE_SH_MASK 0x3 #define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 #define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30 #define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4 #define TD_CNTL__PAD_STALL_EN_MASK 0x100 #define TD_CNTL__PAD_STALL_EN__SHIFT 0x8 #define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600 #define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 #define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800 #define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb #define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000 #define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf #define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000 #define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 #define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000 #define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12 #define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000 #define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 #define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000 #define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 #define TD_STATUS__BUSY_MASK 0x80000000 #define TD_STATUS__BUSY__SHIFT 0x1f #define TD_DEBUG_INDEX__INDEX_MASK 0x1f #define TD_DEBUG_INDEX__INDEX__SHIFT 0x0 #define TD_DEBUG_DATA__DATA_MASK 0xffffffff #define TD_DEBUG_DATA__DATA__SHIFT 0x0 #define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff #define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 #define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 #define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 #define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c #define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff #define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 #define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa #define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 #define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 #define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 #define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 #define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 #define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TD_SCRATCH__SCRATCH_MASK 0xffffffff #define TD_SCRATCH__SCRATCH__SHIFT 0x0 #define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000 #define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd #define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000 #define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 #define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000 #define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1 #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 #define TA_CNTL_AUX__RESERVED_MASK 0xe #define TA_CNTL_AUX__RESERVED__SHIFT 0x1 #define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000 #define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 #define TA_RESERVED_010C__Unused_MASK 0xffffffff #define TA_RESERVED_010C__Unused__SHIFT 0x0 #define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff #define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 #define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff #define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 #define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000 #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc #define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000 #define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd #define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000 #define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe #define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000 #define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 #define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000 #define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 #define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000 #define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 #define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000 #define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 #define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000 #define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 #define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000 #define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 #define TA_STATUS__IN_BUSY_MASK 0x1000000 #define TA_STATUS__IN_BUSY__SHIFT 0x18 #define TA_STATUS__FG_BUSY_MASK 0x2000000 #define TA_STATUS__FG_BUSY__SHIFT 0x19 #define TA_STATUS__LA_BUSY_MASK 0x4000000 #define TA_STATUS__LA_BUSY__SHIFT 0x1a #define TA_STATUS__FL_BUSY_MASK 0x8000000 #define TA_STATUS__FL_BUSY__SHIFT 0x1b #define TA_STATUS__TA_BUSY_MASK 0x10000000 #define TA_STATUS__TA_BUSY__SHIFT 0x1c #define TA_STATUS__FA_BUSY_MASK 0x20000000 #define TA_STATUS__FA_BUSY__SHIFT 0x1d #define TA_STATUS__AL_BUSY_MASK 0x40000000 #define TA_STATUS__AL_BUSY__SHIFT 0x1e #define TA_STATUS__BUSY_MASK 0x80000000 #define TA_STATUS__BUSY__SHIFT 0x1f #define TA_DEBUG_INDEX__INDEX_MASK 0x1f #define TA_DEBUG_INDEX__INDEX__SHIFT 0x0 #define TA_DEBUG_DATA__DATA_MASK 0xffffffff #define TA_DEBUG_DATA__DATA__SHIFT 0x0 #define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff #define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 #define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 #define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 #define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c #define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff #define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 #define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa #define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 #define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 #define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 #define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 #define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TA_SCRATCH__SCRATCH_MASK 0xffffffff #define TA_SCRATCH__SCRATCH__SHIFT 0x0 #define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff #define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0 #define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1 #define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0 #define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6 #define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1 #define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18 #define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3 #define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0 #define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5 #define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00 #define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8 #define TCP_INVALIDATE__START_MASK 0x1 #define TCP_INVALIDATE__START__SHIFT 0x0 #define TCP_STATUS__TCP_BUSY_MASK 0x1 #define TCP_STATUS__TCP_BUSY__SHIFT 0x0 #define TCP_CNTL__FORCE_HIT_MASK 0x1 #define TCP_CNTL__FORCE_HIT__SHIFT 0x0 #define TCP_CNTL__FORCE_MISS_MASK 0x2 #define TCP_CNTL__FORCE_MISS__SHIFT 0x1 #define TCP_CNTL__L1_SIZE_MASK 0xc #define TCP_CNTL__L1_SIZE__SHIFT 0x2 #define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10 #define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4 #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20 #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 #define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000 #define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000 #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 #define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000 #define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c #define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000 #define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d #define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf #define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0 #define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0 #define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4 #define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00 #define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8 #define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000 #define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc #define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000 #define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10 #define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000 #define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14 #define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000 #define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18 #define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000 #define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c #define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf #define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0 #define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0 #define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4 #define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00 #define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8 #define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000 #define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc #define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000 #define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10 #define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000 #define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14 #define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000 #define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18 #define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000 #define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c #define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf #define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 #define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30 #define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4 #define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0 #define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6 #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200 #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9 #define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff #define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0 #define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000 #define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 #define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000 #define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d #define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff #define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c #define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff #define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c #define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff #define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 #define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 #define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c #define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff #define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 #define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 #define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 #define TCP_EDC_COUNTER__SEC_COUNT_MASK 0xf #define TCP_EDC_COUNTER__SEC_COUNT__SHIFT 0x0 #define TCP_EDC_COUNTER__DED_COUNT_MASK 0xf0000 #define TCP_EDC_COUNTER__DED_COUNT__SHIFT 0x10 #define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3 #define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 #define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc #define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 #define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30 #define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 #define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0 #define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 #define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300 #define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 #define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00 #define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa #define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000 #define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc #define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000 #define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe #define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000 #define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 #define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000 #define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 #define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000 #define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 #define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000 #define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 #define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000 #define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 #define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000 #define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a #define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000 #define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c #define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 #define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e #define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3 #define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 #define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc #define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 #define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30 #define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 #define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0 #define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 #define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300 #define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 #define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00 #define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa #define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000 #define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc #define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000 #define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe #define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000 #define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 #define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000 #define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 #define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000 #define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 #define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000 #define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 #define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000 #define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 #define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000 #define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a #define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000 #define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c #define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 #define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e #define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1 #define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 #define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2 #define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 #define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4 #define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 #define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8 #define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 #define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10 #define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 #define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20 #define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 #define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40 #define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 #define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80 #define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 #define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100 #define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 #define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200 #define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 #define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400 #define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa #define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800 #define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb #define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000 #define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc #define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000 #define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd #define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000 #define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe #define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000 #define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf #define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000 #define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 #define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000 #define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 #define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000 #define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 #define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000 #define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 #define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000 #define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 #define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000 #define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 #define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000 #define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 #define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000 #define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 #define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000 #define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 #define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000 #define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 #define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000 #define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a #define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000 #define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b #define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000 #define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c #define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000 #define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d #define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000 #define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e #define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000 #define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f #define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3 #define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 #define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc #define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 #define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30 #define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 #define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0 #define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 #define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300 #define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa #define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000 #define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc #define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000 #define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe #define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000 #define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 #define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000 #define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 #define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000 #define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 #define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000 #define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 #define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000 #define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 #define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000 #define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a #define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000 #define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c #define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 #define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e #define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3 #define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 #define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc #define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 #define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0 #define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 #define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300 #define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 #define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00 #define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa #define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000 #define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc #define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000 #define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe #define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000 #define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 #define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000 #define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 #define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000 #define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 #define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000 #define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 #define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000 #define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 #define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000 #define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a #define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000 #define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c #define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 #define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e #define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3 #define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 #define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc #define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 #define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30 #define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 #define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0 #define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 #define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300 #define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 #define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00 #define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa #define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000 #define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc #define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000 #define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe #define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000 #define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 #define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000 #define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 #define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000 #define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 #define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000 #define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 #define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000 #define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 #define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000 #define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a #define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000 #define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c #define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000 #define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e #define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3 #define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 #define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc #define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 #define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30 #define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 #define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0 #define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 #define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300 #define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 #define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00 #define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa #define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000 #define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc #define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000 #define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe #define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000 #define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 #define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000 #define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 #define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000 #define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 #define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000 #define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 #define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000 #define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 #define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000 #define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a #define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000 #define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c #define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000 #define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e #define TC_CFG_L1_VOLATILE__VOL_MASK 0xf #define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 #define TC_CFG_L2_VOLATILE__VOL_MASK 0xf #define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 #define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff #define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 #define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff #define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 #define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff #define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 #define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff #define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 #define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0 #define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 #define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0 #define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 #define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0 #define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 #define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0 #define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 #define TCP_WATCH0_CNTL__MASK_MASK 0xffffff #define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 #define TCP_WATCH0_CNTL__VMID_MASK 0xf000000 #define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 #define TCP_WATCH0_CNTL__MODE_MASK 0x60000000 #define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d #define TCP_WATCH0_CNTL__VALID_MASK 0x80000000 #define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f #define TCP_WATCH1_CNTL__MASK_MASK 0xffffff #define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 #define TCP_WATCH1_CNTL__VMID_MASK 0xf000000 #define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 #define TCP_WATCH1_CNTL__MODE_MASK 0x60000000 #define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d #define TCP_WATCH1_CNTL__VALID_MASK 0x80000000 #define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f #define TCP_WATCH2_CNTL__MASK_MASK 0xffffff #define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 #define TCP_WATCH2_CNTL__VMID_MASK 0xf000000 #define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 #define TCP_WATCH2_CNTL__MODE_MASK 0x60000000 #define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d #define TCP_WATCH2_CNTL__VALID_MASK 0x80000000 #define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f #define TCP_WATCH3_CNTL__MASK_MASK 0xffffff #define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 #define TCP_WATCH3_CNTL__VMID_MASK 0xf000000 #define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 #define TCP_WATCH3_CNTL__MODE_MASK 0x60000000 #define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d #define TCP_WATCH3_CNTL__VALID_MASK 0x80000000 #define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f #define TD_CGTT_CTRL__ON_DELAY_MASK 0xf #define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 #define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 #define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 #define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 #define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a #define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 #define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c #define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d #define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 #define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e #define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 #define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f #define TA_CGTT_CTRL__ON_DELAY_MASK 0xf #define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 #define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 #define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 #define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 #define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a #define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 #define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c #define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d #define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 #define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e #define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 #define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f #define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f #define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f #define TCI_STATUS__TCI_BUSY_MASK 0x1 #define TCI_STATUS__TCI_BUSY__SHIFT 0x0 #define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff #define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 #define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000 #define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 #define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000 #define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1 #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 #define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe #define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6 #define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 #define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 #define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180 #define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 #define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1 #define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2 #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 #define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4 #define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 #define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8 #define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10 #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 #define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20 #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 #define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40 #define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 #define GDS_ENHANCE2__MISC_MASK 0xffff #define GDS_ENHANCE2__MISC__SHIFT 0x0 #define GDS_ENHANCE2__UNUSED_MASK 0xffff0000 #define GDS_ENHANCE2__UNUSED__SHIFT 0x10 #define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 #define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 #define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 #define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 #define GDS_PROTECTION_FAULT__GRBM_MASK 0x4 #define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 #define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38 #define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 #define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0 #define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 #define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00 #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa #define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000 #define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc #define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 #define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 #define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 #define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 #define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4 #define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 #define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8 #define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 #define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10 #define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 #define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00 #define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 #define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 #define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 #define GDS_SECDED_CNT__DED_MASK 0xffff #define GDS_SECDED_CNT__DED__SHIFT 0x0 #define GDS_SECDED_CNT__SEC_MASK 0xffff0000 #define GDS_SECDED_CNT__SEC__SHIFT 0x10 #define GDS_GRBM_SECDED_CNT__DED_MASK 0xffff #define GDS_GRBM_SECDED_CNT__DED__SHIFT 0x0 #define GDS_GRBM_SECDED_CNT__SEC_MASK 0xffff0000 #define GDS_GRBM_SECDED_CNT__SEC__SHIFT 0x10 #define GDS_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1 #define GDS_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 #define GDS_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2 #define GDS_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 #define GDS_OA_DED__ME0_CS_DED_MASK 0x4 #define GDS_OA_DED__ME0_CS_DED__SHIFT 0x2 #define GDS_OA_DED__UNUSED0_MASK 0x8 #define GDS_OA_DED__UNUSED0__SHIFT 0x3 #define GDS_OA_DED__ME1_PIPE0_DED_MASK 0x10 #define GDS_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 #define GDS_OA_DED__ME1_PIPE1_DED_MASK 0x20 #define GDS_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 #define GDS_OA_DED__ME1_PIPE2_DED_MASK 0x40 #define GDS_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 #define GDS_OA_DED__ME1_PIPE3_DED_MASK 0x80 #define GDS_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 #define GDS_OA_DED__ME2_PIPE0_DED_MASK 0x100 #define GDS_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 #define GDS_OA_DED__ME2_PIPE1_DED_MASK 0x200 #define GDS_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 #define GDS_OA_DED__ME2_PIPE2_DED_MASK 0x400 #define GDS_OA_DED__ME2_PIPE2_DED__SHIFT 0xa #define GDS_OA_DED__ME2_PIPE3_DED_MASK 0x800 #define GDS_OA_DED__ME2_PIPE3_DED__SHIFT 0xb #define GDS_OA_DED__UNUSED1_MASK 0xfffff000 #define GDS_OA_DED__UNUSED1__SHIFT 0xc #define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f #define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0 #define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0 #define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5 #define GDS_DEBUG_DATA__DATA_MASK 0xffffffff #define GDS_DEBUG_DATA__DATA__SHIFT 0x0 #define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f #define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff #define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 #define GDS_RD_DATA__READ_DATA_MASK 0xffffffff #define GDS_RD_DATA__READ_DATA__SHIFT 0x0 #define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff #define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 #define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff #define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 #define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff #define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 #define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff #define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 #define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff #define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 #define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff #define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 #define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff #define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 #define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff #define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 #define GDS_ATOM_CNTL__AINC_MASK 0x3f #define GDS_ATOM_CNTL__AINC__SHIFT 0x0 #define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0 #define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 #define GDS_ATOM_CNTL__DMODE_MASK 0x100 #define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 #define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffe00 #define GDS_ATOM_CNTL__UNUSED2__SHIFT 0x9 #define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1 #define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 #define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe #define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 #define GDS_ATOM_BASE__BASE_MASK 0xffff #define GDS_ATOM_BASE__BASE__SHIFT 0x0 #define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000 #define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 #define GDS_ATOM_SIZE__SIZE_MASK 0xffff #define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 #define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000 #define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 #define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff #define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 #define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00 #define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 #define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff #define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 #define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00 #define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 #define GDS_ATOM_DST__DST_MASK 0xffffffff #define GDS_ATOM_DST__DST__SHIFT 0x0 #define GDS_ATOM_OP__OP_MASK 0xff #define GDS_ATOM_OP__OP__SHIFT 0x0 #define GDS_ATOM_OP__UNUSED_MASK 0xffffff00 #define GDS_ATOM_OP__UNUSED__SHIFT 0x8 #define GDS_ATOM_SRC0__DATA_MASK 0xffffffff #define GDS_ATOM_SRC0__DATA__SHIFT 0x0 #define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff #define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 #define GDS_ATOM_SRC1__DATA_MASK 0xffffffff #define GDS_ATOM_SRC1__DATA__SHIFT 0x0 #define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff #define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 #define GDS_ATOM_READ0__DATA_MASK 0xffffffff #define GDS_ATOM_READ0__DATA__SHIFT 0x0 #define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff #define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 #define GDS_ATOM_READ1__DATA_MASK 0xffffffff #define GDS_ATOM_READ1__DATA__SHIFT 0x0 #define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff #define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 #define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f #define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 #define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0 #define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 #define GDS_GWS_RESOURCE__FLAG_MASK 0x1 #define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 #define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe #define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 #define GDS_GWS_RESOURCE__TYPE_MASK 0x2000 #define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd #define GDS_GWS_RESOURCE__DED_MASK 0x4000 #define GDS_GWS_RESOURCE__DED__SHIFT 0xe #define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000 #define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf #define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x7ff0000 #define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 #define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x8000000 #define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b #define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000 #define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c #define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000 #define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 #define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000 #define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 #define GDS_OA_CNTL__INDEX_MASK 0xf #define GDS_OA_CNTL__INDEX__SHIFT 0x0 #define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0 #define GDS_OA_CNTL__UNUSED__SHIFT 0x4 #define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff #define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 #define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff #define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 #define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0xf0000 #define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x10 #define GDS_OA_ADDRESS__CRAWLER_MASK 0xf00000 #define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x14 #define GDS_OA_ADDRESS__UNUSED_MASK 0x3f000000 #define GDS_OA_ADDRESS__UNUSED__SHIFT 0x18 #define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000 #define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e #define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000 #define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f #define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff #define GDS_OA_INCDEC__VALUE__SHIFT 0x0 #define GDS_OA_INCDEC__INCDEC_MASK 0x80000000 #define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f #define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff #define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 #define GDS_DEBUG_REG0__spare1_MASK 0x3f #define GDS_DEBUG_REG0__spare1__SHIFT 0x0 #define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40 #define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6 #define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80 #define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7 #define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000 #define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc #define GDS_DEBUG_REG0__cstate_MASK 0x1e000 #define GDS_DEBUG_REG0__cstate__SHIFT 0xd #define GDS_DEBUG_REG0__buff_write_MASK 0x20000 #define GDS_DEBUG_REG0__buff_write__SHIFT 0x11 #define GDS_DEBUG_REG0__flush_request_MASK 0x40000 #define GDS_DEBUG_REG0__flush_request__SHIFT 0x12 #define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000 #define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13 #define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000 #define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14 #define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000 #define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15 #define GDS_DEBUG_REG0__spare_MASK 0xffc00000 #define GDS_DEBUG_REG0__spare__SHIFT 0x16 #define GDS_DEBUG_REG1__tag_hit_MASK 0x1 #define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0 #define GDS_DEBUG_REG1__tag_miss_MASK 0x2 #define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1 #define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc #define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2 #define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000 #define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11 #define GDS_DEBUG_REG1__data_ready_MASK 0x40000 #define GDS_DEBUG_REG1__data_ready__SHIFT 0x12 #define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000 #define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13 #define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000 #define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14 #define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000 #define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15 #define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000 #define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16 #define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000 #define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17 #define GDS_DEBUG_REG1__spare_MASK 0xff000000 #define GDS_DEBUG_REG1__spare__SHIFT 0x18 #define GDS_DEBUG_REG2__ds_full_MASK 0x1 #define GDS_DEBUG_REG2__ds_full__SHIFT 0x0 #define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2 #define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1 #define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4 #define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2 #define GDS_DEBUG_REG2__cmd_write_MASK 0x8 #define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3 #define GDS_DEBUG_REG2__app_sel_MASK 0xf0 #define GDS_DEBUG_REG2__app_sel__SHIFT 0x4 #define GDS_DEBUG_REG2__req_MASK 0x7fff00 #define GDS_DEBUG_REG2__req__SHIFT 0x8 #define GDS_DEBUG_REG2__spare_MASK 0xff800000 #define GDS_DEBUG_REG2__spare__SHIFT 0x17 #define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff #define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0 #define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800 #define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb #define GDS_DEBUG_REG3__spare_MASK 0xffff8000 #define GDS_DEBUG_REG3__spare__SHIFT 0xf #define GDS_DEBUG_REG4__gws_busy_MASK 0x1 #define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0 #define GDS_DEBUG_REG4__gws_req_MASK 0x2 #define GDS_DEBUG_REG4__gws_req__SHIFT 0x1 #define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4 #define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2 #define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8 #define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3 #define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200 #define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9 #define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400 #define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa #define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800 #define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb #define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000 #define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc #define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000 #define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd #define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000 #define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe #define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000 #define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf #define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000 #define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10 #define GDS_DEBUG_REG4__cmd_write_MASK 0x20000 #define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11 #define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000 #define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12 #define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000 #define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13 #define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000 #define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14 #define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000 #define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15 #define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000 #define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16 #define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000 #define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17 #define GDS_DEBUG_REG4__spare_MASK 0xff000000 #define GDS_DEBUG_REG4__spare__SHIFT 0x18 #define GDS_DEBUG_REG5__write_dis_MASK 0x1 #define GDS_DEBUG_REG5__write_dis__SHIFT 0x0 #define GDS_DEBUG_REG5__dec_error_MASK 0x2 #define GDS_DEBUG_REG5__dec_error__SHIFT 0x1 #define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4 #define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2 #define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8 #define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3 #define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10 #define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4 #define GDS_DEBUG_REG5__spare_MASK 0xe0 #define GDS_DEBUG_REG5__spare__SHIFT 0x5 #define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00 #define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8 #define GDS_DEBUG_REG5__spare1_MASK 0xffc00000 #define GDS_DEBUG_REG5__spare1__SHIFT 0x16 #define GDS_DEBUG_REG6__oa_busy_MASK 0x1 #define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0 #define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e #define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1 #define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0 #define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5 #define GDS_DEBUG_REG6__spare_MASK 0xffe00000 #define GDS_DEBUG_REG6__spare__SHIFT 0x15 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa #define GDS_VMID0_BASE__BASE_MASK 0xffff #define GDS_VMID0_BASE__BASE__SHIFT 0x0 #define GDS_VMID1_BASE__BASE_MASK 0xffff #define GDS_VMID1_BASE__BASE__SHIFT 0x0 #define GDS_VMID2_BASE__BASE_MASK 0xffff #define GDS_VMID2_BASE__BASE__SHIFT 0x0 #define GDS_VMID3_BASE__BASE_MASK 0xffff #define GDS_VMID3_BASE__BASE__SHIFT 0x0 #define GDS_VMID4_BASE__BASE_MASK 0xffff #define GDS_VMID4_BASE__BASE__SHIFT 0x0 #define GDS_VMID5_BASE__BASE_MASK 0xffff #define GDS_VMID5_BASE__BASE__SHIFT 0x0 #define GDS_VMID6_BASE__BASE_MASK 0xffff #define GDS_VMID6_BASE__BASE__SHIFT 0x0 #define GDS_VMID7_BASE__BASE_MASK 0xffff #define GDS_VMID7_BASE__BASE__SHIFT 0x0 #define GDS_VMID8_BASE__BASE_MASK 0xffff #define GDS_VMID8_BASE__BASE__SHIFT 0x0 #define GDS_VMID9_BASE__BASE_MASK 0xffff #define GDS_VMID9_BASE__BASE__SHIFT 0x0 #define GDS_VMID10_BASE__BASE_MASK 0xffff #define GDS_VMID10_BASE__BASE__SHIFT 0x0 #define GDS_VMID11_BASE__BASE_MASK 0xffff #define GDS_VMID11_BASE__BASE__SHIFT 0x0 #define GDS_VMID12_BASE__BASE_MASK 0xffff #define GDS_VMID12_BASE__BASE__SHIFT 0x0 #define GDS_VMID13_BASE__BASE_MASK 0xffff #define GDS_VMID13_BASE__BASE__SHIFT 0x0 #define GDS_VMID14_BASE__BASE_MASK 0xffff #define GDS_VMID14_BASE__BASE__SHIFT 0x0 #define GDS_VMID15_BASE__BASE_MASK 0xffff #define GDS_VMID15_BASE__BASE__SHIFT 0x0 #define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 #define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff #define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 #define GDS_GWS_VMID0__BASE_MASK 0x3f #define GDS_GWS_VMID0__BASE__SHIFT 0x0 #define GDS_GWS_VMID0__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID0__SIZE__SHIFT 0x10 #define GDS_GWS_VMID1__BASE_MASK 0x3f #define GDS_GWS_VMID1__BASE__SHIFT 0x0 #define GDS_GWS_VMID1__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID1__SIZE__SHIFT 0x10 #define GDS_GWS_VMID2__BASE_MASK 0x3f #define GDS_GWS_VMID2__BASE__SHIFT 0x0 #define GDS_GWS_VMID2__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID2__SIZE__SHIFT 0x10 #define GDS_GWS_VMID3__BASE_MASK 0x3f #define GDS_GWS_VMID3__BASE__SHIFT 0x0 #define GDS_GWS_VMID3__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID3__SIZE__SHIFT 0x10 #define GDS_GWS_VMID4__BASE_MASK 0x3f #define GDS_GWS_VMID4__BASE__SHIFT 0x0 #define GDS_GWS_VMID4__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID4__SIZE__SHIFT 0x10 #define GDS_GWS_VMID5__BASE_MASK 0x3f #define GDS_GWS_VMID5__BASE__SHIFT 0x0 #define GDS_GWS_VMID5__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID5__SIZE__SHIFT 0x10 #define GDS_GWS_VMID6__BASE_MASK 0x3f #define GDS_GWS_VMID6__BASE__SHIFT 0x0 #define GDS_GWS_VMID6__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID6__SIZE__SHIFT 0x10 #define GDS_GWS_VMID7__BASE_MASK 0x3f #define GDS_GWS_VMID7__BASE__SHIFT 0x0 #define GDS_GWS_VMID7__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID7__SIZE__SHIFT 0x10 #define GDS_GWS_VMID8__BASE_MASK 0x3f #define GDS_GWS_VMID8__BASE__SHIFT 0x0 #define GDS_GWS_VMID8__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID8__SIZE__SHIFT 0x10 #define GDS_GWS_VMID9__BASE_MASK 0x3f #define GDS_GWS_VMID9__BASE__SHIFT 0x0 #define GDS_GWS_VMID9__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID9__SIZE__SHIFT 0x10 #define GDS_GWS_VMID10__BASE_MASK 0x3f #define GDS_GWS_VMID10__BASE__SHIFT 0x0 #define GDS_GWS_VMID10__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID10__SIZE__SHIFT 0x10 #define GDS_GWS_VMID11__BASE_MASK 0x3f #define GDS_GWS_VMID11__BASE__SHIFT 0x0 #define GDS_GWS_VMID11__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID11__SIZE__SHIFT 0x10 #define GDS_GWS_VMID12__BASE_MASK 0x3f #define GDS_GWS_VMID12__BASE__SHIFT 0x0 #define GDS_GWS_VMID12__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID12__SIZE__SHIFT 0x10 #define GDS_GWS_VMID13__BASE_MASK 0x3f #define GDS_GWS_VMID13__BASE__SHIFT 0x0 #define GDS_GWS_VMID13__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID13__SIZE__SHIFT 0x10 #define GDS_GWS_VMID14__BASE_MASK 0x3f #define GDS_GWS_VMID14__BASE__SHIFT 0x0 #define GDS_GWS_VMID14__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID14__SIZE__SHIFT 0x10 #define GDS_GWS_VMID15__BASE_MASK 0x3f #define GDS_GWS_VMID15__BASE__SHIFT 0x0 #define GDS_GWS_VMID15__SIZE_MASK 0x7f0000 #define GDS_GWS_VMID15__SIZE__SHIFT 0x10 #define GDS_OA_VMID0__MASK_MASK 0xffff #define GDS_OA_VMID0__MASK__SHIFT 0x0 #define GDS_OA_VMID0__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID0__UNUSED__SHIFT 0x10 #define GDS_OA_VMID1__MASK_MASK 0xffff #define GDS_OA_VMID1__MASK__SHIFT 0x0 #define GDS_OA_VMID1__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID1__UNUSED__SHIFT 0x10 #define GDS_OA_VMID2__MASK_MASK 0xffff #define GDS_OA_VMID2__MASK__SHIFT 0x0 #define GDS_OA_VMID2__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID2__UNUSED__SHIFT 0x10 #define GDS_OA_VMID3__MASK_MASK 0xffff #define GDS_OA_VMID3__MASK__SHIFT 0x0 #define GDS_OA_VMID3__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID3__UNUSED__SHIFT 0x10 #define GDS_OA_VMID4__MASK_MASK 0xffff #define GDS_OA_VMID4__MASK__SHIFT 0x0 #define GDS_OA_VMID4__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID4__UNUSED__SHIFT 0x10 #define GDS_OA_VMID5__MASK_MASK 0xffff #define GDS_OA_VMID5__MASK__SHIFT 0x0 #define GDS_OA_VMID5__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID5__UNUSED__SHIFT 0x10 #define GDS_OA_VMID6__MASK_MASK 0xffff #define GDS_OA_VMID6__MASK__SHIFT 0x0 #define GDS_OA_VMID6__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID6__UNUSED__SHIFT 0x10 #define GDS_OA_VMID7__MASK_MASK 0xffff #define GDS_OA_VMID7__MASK__SHIFT 0x0 #define GDS_OA_VMID7__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID7__UNUSED__SHIFT 0x10 #define GDS_OA_VMID8__MASK_MASK 0xffff #define GDS_OA_VMID8__MASK__SHIFT 0x0 #define GDS_OA_VMID8__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID8__UNUSED__SHIFT 0x10 #define GDS_OA_VMID9__MASK_MASK 0xffff #define GDS_OA_VMID9__MASK__SHIFT 0x0 #define GDS_OA_VMID9__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID9__UNUSED__SHIFT 0x10 #define GDS_OA_VMID10__MASK_MASK 0xffff #define GDS_OA_VMID10__MASK__SHIFT 0x0 #define GDS_OA_VMID10__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID10__UNUSED__SHIFT 0x10 #define GDS_OA_VMID11__MASK_MASK 0xffff #define GDS_OA_VMID11__MASK__SHIFT 0x0 #define GDS_OA_VMID11__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID11__UNUSED__SHIFT 0x10 #define GDS_OA_VMID12__MASK_MASK 0xffff #define GDS_OA_VMID12__MASK__SHIFT 0x0 #define GDS_OA_VMID12__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID12__UNUSED__SHIFT 0x10 #define GDS_OA_VMID13__MASK_MASK 0xffff #define GDS_OA_VMID13__MASK__SHIFT 0x0 #define GDS_OA_VMID13__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID13__UNUSED__SHIFT 0x10 #define GDS_OA_VMID14__MASK_MASK 0xffff #define GDS_OA_VMID14__MASK__SHIFT 0x0 #define GDS_OA_VMID14__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID14__UNUSED__SHIFT 0x10 #define GDS_OA_VMID15__MASK_MASK 0xffff #define GDS_OA_VMID15__MASK__SHIFT 0x0 #define GDS_OA_VMID15__UNUSED_MASK 0xffff0000 #define GDS_OA_VMID15__UNUSED__SHIFT 0x10 #define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1 #define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 #define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2 #define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 #define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4 #define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 #define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8 #define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 #define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10 #define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 #define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20 #define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 #define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40 #define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 #define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80 #define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 #define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100 #define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 #define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200 #define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 #define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400 #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa #define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800 #define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb #define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000 #define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc #define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000 #define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd #define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000 #define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe #define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000 #define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf #define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000 #define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 #define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000 #define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 #define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000 #define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 #define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000 #define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 #define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000 #define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 #define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000 #define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 #define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000 #define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 #define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000 #define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 #define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000 #define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 #define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000 #define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 #define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000 #define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a #define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000 #define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b #define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000 #define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c #define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000 #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d #define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000 #define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e #define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000 #define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f #define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1 #define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 #define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2 #define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 #define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4 #define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 #define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8 #define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 #define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10 #define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 #define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20 #define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 #define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40 #define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 #define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80 #define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 #define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100 #define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 #define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200 #define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 #define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400 #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa #define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800 #define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb #define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000 #define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc #define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000 #define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd #define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000 #define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe #define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000 #define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf #define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000 #define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 #define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000 #define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 #define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000 #define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 #define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000 #define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 #define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000 #define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 #define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000 #define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 #define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000 #define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 #define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000 #define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 #define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000 #define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 #define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000 #define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 #define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000 #define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a #define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000 #define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b #define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000 #define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c #define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000 #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d #define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000 #define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e #define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000 #define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f #define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1 #define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00 #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 #define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4 #define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 #define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8 #define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3 #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10 #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20 #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40 #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80 #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100 #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200 #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800 #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb #define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000 #define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc #define GDS_OA_RESET__RESET_MASK 0x1 #define GDS_OA_RESET__RESET__SHIFT 0x0 #define GDS_OA_RESET__PIPE_ID_MASK 0xff00 #define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 #define GDS_ENHANCE__MISC_MASK 0xffff #define GDS_ENHANCE__MISC__SHIFT 0x0 #define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000 #define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 #define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000 #define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 #define GDS_ENHANCE__UNUSED_MASK 0xfffc0000 #define GDS_ENHANCE__UNUSED__SHIFT 0x12 #define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff #define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 #define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00 #define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 #define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000 #define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc #define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xffff0000 #define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x10 #define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7 #define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 #define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7 #define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 #define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3 #define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 #define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc #define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10 #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 #define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20 #define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 #define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40 #define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 #define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f #define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 #define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000 #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12 #define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000 #define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 #define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff #define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 #define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff #define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 #define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3 #define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 #define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc #define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 #define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30 #define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0xc0 #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 #define VGT_DMA_INDEX_TYPE__ATC_MASK 0x100 #define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x8 #define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200 #define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 #define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400 #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 #define IA_ENHANCE__MISC_MASK 0xffffffff #define IA_ENHANCE__MISC__SHIFT 0x0 #define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff #define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 #define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff #define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 #define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff #define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000 #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000 #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 #define VGT_IMMED_DATA__DATA_MASK 0xffffffff #define VGT_IMMED_DATA__DATA__SHIFT 0x0 #define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3 #define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 #define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff #define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 #define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff #define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 #define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f #define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1 #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2 #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 #define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff #define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 #define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1 #define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 #define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1 #define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 #define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff #define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 #define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff #define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 #define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff #define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1 #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 #define VGT_ENHANCE__MISC_MASK 0xffffffff #define VGT_ENHANCE__MISC__SHIFT 0x0 #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7 #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 #define VGT_HOS_CNTL__TESS_MODE_MASK 0x3 #define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000 #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000 #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000 #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 #define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf #define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 #define VGT_GROUP_DECR__DECR_MASK 0xf #define VGT_GROUP_DECR__DECR__SHIFT 0x0 #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1 #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2 #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4 #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8 #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 #define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00 #define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 #define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000 #define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1 #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2 #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4 #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8 #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 #define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00 #define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 #define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000 #define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0 #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000 #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000 #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0 #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000 #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000 #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 #define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7 #define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 #define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000 #define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 #define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x6 #define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x1 #define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 #define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 #define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x10 #define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x4 #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 #define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x6 #define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x1 #define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 #define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 #define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x10 #define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x4 #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 #define VGT_GS_MODE__MODE_MASK 0x7 #define VGT_GS_MODE__MODE__SHIFT 0x0 #define VGT_GS_MODE__RESERVED_0_MASK 0x8 #define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 #define VGT_GS_MODE__CUT_MODE_MASK 0x30 #define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 #define VGT_GS_MODE__RESERVED_1_MASK 0x7c0 #define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 #define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800 #define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb #define VGT_GS_MODE__RESERVED_2_MASK 0x1000 #define VGT_GS_MODE__RESERVED_2__SHIFT 0xc #define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000 #define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd #define VGT_GS_MODE__COMPUTE_MODE_MASK 0x4000 #define VGT_GS_MODE__COMPUTE_MODE__SHIFT 0xe #define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK 0x8000 #define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT 0xf #define VGT_GS_MODE__ELEMENT_INFO_EN_MASK 0x10000 #define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT 0x10 #define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000 #define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 #define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000 #define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 #define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000 #define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 #define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000 #define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 #define VGT_GS_MODE__ONCHIP_MASK 0x600000 #define VGT_GS_MODE__ONCHIP__SHIFT 0x15 #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800 #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000 #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3 #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20 #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0 #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 #define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200 #define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800 #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000 #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000 #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd #define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000 #define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 #define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1 #define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0 #define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2 #define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1 #define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4 #define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2 #define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff #define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 #define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700 #define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 #define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800 #define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb #define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000 #define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe #define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000 #define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 #define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80 #define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00 #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 #define VGT_FIFO_DEPTHS__RESERVED_1_MASK 0x400000 #define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT 0x16 #define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff #define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 #define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff #define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 #define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf #define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 #define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f #define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3 #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 #define IA_CNTL_STATUS__IA_BUSY_MASK 0x1 #define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 #define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2 #define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4 #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 #define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8 #define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 #define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10 #define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1 #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2 #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4 #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8 #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70 #define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000 #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 #define IA_VMID_OVERRIDE__ENABLE_MASK 0x1 #define IA_VMID_OVERRIDE__ENABLE__SHIFT 0x0 #define IA_VMID_OVERRIDE__VMID_MASK 0x1e #define IA_VMID_OVERRIDE__VMID__SHIFT 0x1 #define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3 #define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 #define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4 #define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 #define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18 #define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 #define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20 #define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 #define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0 #define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 #define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100 #define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8 #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 #define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff #define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000 #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 #define VGT_TF_PARAM__TYPE_MASK 0x3 #define VGT_TF_PARAM__TYPE__SHIFT 0x0 #define VGT_TF_PARAM__PARTITIONING_MASK 0x1c #define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 #define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0 #define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 #define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100 #define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 #define VGT_TF_PARAM__DEPRECATED_MASK 0x200 #define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00 #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa #define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000 #define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe #define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x18000 #define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf #define VGT_TF_RING_SIZE__SIZE_MASK 0xffff #define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1 #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80 #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 #define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff #define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 #define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1 #define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 #define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc #define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000 #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000 #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000 #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 #define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff #define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0 #define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff #define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 #define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff #define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 #define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff #define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 #define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff #define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 #define WD_CNTL_STATUS__WD_BUSY_MASK 0x1 #define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2 #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 #define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4 #define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 #define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8 #define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 #define WD_ENHANCE__MISC_MASK 0xffffffff #define WD_ENHANCE__MISC__SHIFT 0x0 #define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff #define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 #define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000 #define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000 #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 #define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x1 #define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0 #define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 #define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 #define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 #define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f #define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 #define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 #define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 #define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e #define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 #define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f #define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf #define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 #define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 #define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 #define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 #define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b #define CGTT_WD_CLK_CTRL__ADC_OVERRIDE_MASK 0x10000000 #define CGTT_WD_CLK_CTRL__ADC_OVERRIDE__SHIFT 0x1c #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000 #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 #define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f #define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f #define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0 #define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40 #define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6 #define VGT_DEBUG_DATA__DATA_MASK 0xffffffff #define VGT_DEBUG_DATA__DATA__SHIFT 0x0 #define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f #define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0 #define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40 #define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6 #define IA_DEBUG_DATA__DATA_MASK 0xffffffff #define IA_DEBUG_DATA__DATA__SHIFT 0x0 #define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1 #define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2 #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 #define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4 #define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 #define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8 #define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 #define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10 #define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 #define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20 #define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 #define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40 #define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 #define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80 #define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 #define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100 #define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 #define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200 #define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 #define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f #define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0 #define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40 #define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6 #define WD_DEBUG_DATA__DATA_MASK 0xffffffff #define WD_DEBUG_DATA__DATA__SHIFT 0x0 #define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 #define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 #define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 #define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 #define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1 #define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0 #define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2 #define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1 #define WD_DEBUG_REG0__wd_busy_MASK 0x4 #define WD_DEBUG_REG0__wd_busy__SHIFT 0x2 #define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8 #define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3 #define WD_DEBUG_REG0__rbiu_busy_MASK 0x10 #define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4 #define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20 #define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5 #define WD_DEBUG_REG0__spl_di_busy_MASK 0x40 #define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6 #define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80 #define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7 #define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100 #define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8 #define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200 #define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9 #define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400 #define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa #define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800 #define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb #define WD_DEBUG_REG0__SPARE2_MASK 0x1000 #define WD_DEBUG_REG0__SPARE2__SHIFT 0xc #define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000 #define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd #define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000 #define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe #define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000 #define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf #define WD_DEBUG_REG0__SPARE3_MASK 0x10000 #define WD_DEBUG_REG0__SPARE3__SHIFT 0x10 #define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000 #define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11 #define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000 #define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12 #define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000 #define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13 #define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000 #define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14 #define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000 #define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15 #define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000 #define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16 #define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000 #define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17 #define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 #define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 #define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000 #define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19 #define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000 #define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a #define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000 #define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b #define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 #define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c #define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000 #define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d #define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000 #define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e #define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000 #define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f #define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1 #define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0 #define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2 #define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1 #define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4 #define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2 #define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8 #define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3 #define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10 #define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4 #define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20 #define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5 #define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40 #define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6 #define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80 #define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7 #define WD_DEBUG_REG1__SPARE0_MASK 0x100 #define WD_DEBUG_REG1__SPARE0__SHIFT 0x8 #define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200 #define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9 #define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400 #define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa #define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800 #define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb #define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000 #define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc #define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000 #define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11 #define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000 #define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14 #define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000 #define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a #define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000 #define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b #define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000 #define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c #define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000 #define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d #define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000 #define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e #define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000 #define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f #define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1 #define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0 #define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2 #define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1 #define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4 #define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2 #define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8 #define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3 #define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10 #define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4 #define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20 #define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5 #define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40 #define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6 #define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80 #define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7 #define WD_DEBUG_REG2__SPARE0_MASK 0x100 #define WD_DEBUG_REG2__SPARE0__SHIFT 0x8 #define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200 #define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9 #define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400 #define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa #define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800 #define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb #define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000 #define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc #define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000 #define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11 #define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000 #define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14 #define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000 #define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000 #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b #define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000 #define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c #define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000 #define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000 #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000 #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f #define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1 #define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0 #define WD_DEBUG_REG3__SPARE0_MASK 0x2 #define WD_DEBUG_REG3__SPARE0__SHIFT 0x1 #define WD_DEBUG_REG3__pipe0_dr_MASK 0x4 #define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2 #define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8 #define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3 #define WD_DEBUG_REG3__pipe1_dr_MASK 0x10 #define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4 #define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20 #define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5 #define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40 #define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6 #define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80 #define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7 #define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300 #define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8 #define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400 #define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa #define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800 #define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb #define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000 #define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc #define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000 #define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd #define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000 #define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe #define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000 #define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf #define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000 #define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10 #define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000 #define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11 #define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000 #define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12 #define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000 #define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13 #define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000 #define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14 #define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000 #define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15 #define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000 #define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16 #define WD_DEBUG_REG3__SPARE1_MASK 0x800000 #define WD_DEBUG_REG3__SPARE1__SHIFT 0x17 #define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000 #define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18 #define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000 #define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19 #define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000 #define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a #define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000 #define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b #define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000 #define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c #define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000 #define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d #define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000 #define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e #define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000 #define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f #define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1 #define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0 #define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2 #define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1 #define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4 #define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2 #define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8 #define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3 #define WD_DEBUG_REG4__pipe0_dr_MASK 0x10 #define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4 #define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20 #define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5 #define WD_DEBUG_REG4__pipe1_dr_MASK 0x40 #define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6 #define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80 #define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7 #define WD_DEBUG_REG4__pipe2_dr_MASK 0x100 #define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8 #define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200 #define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9 #define WD_DEBUG_REG4__pipe3_ld_MASK 0x400 #define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa #define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800 #define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb #define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000 #define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc #define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000 #define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd #define WD_DEBUG_REG4__di_type_p0_MASK 0xc000 #define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe #define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000 #define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10 #define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000 #define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13 #define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000 #define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14 #define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000 #define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15 #define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000 #define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16 #define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000 #define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17 #define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000 #define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18 #define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000 #define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19 #define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000 #define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a #define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000 #define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b #define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000 #define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c #define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000 #define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d #define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000 #define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e #define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000 #define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f #define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1 #define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0 #define WD_DEBUG_REG5__SPARE0_MASK 0x2 #define WD_DEBUG_REG5__SPARE0__SHIFT 0x1 #define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4 #define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2 #define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8 #define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3 #define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10 #define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4 #define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20 #define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5 #define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40 #define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6 #define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80 #define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7 #define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300 #define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8 #define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400 #define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa #define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800 #define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb #define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000 #define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc #define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000 #define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd #define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000 #define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe #define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000 #define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf #define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000 #define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10 #define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000 #define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11 #define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000 #define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12 #define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000 #define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13 #define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000 #define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14 #define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000 #define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15 #define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000 #define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16 #define WD_DEBUG_REG5__SPARE1_MASK 0x800000 #define WD_DEBUG_REG5__SPARE1__SHIFT 0x17 #define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000 #define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18 #define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000 #define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19 #define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000 #define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a #define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000 #define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b #define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000 #define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c #define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000 #define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d #define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000 #define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e #define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000 #define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f #define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1 #define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0 #define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2 #define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1 #define IA_DEBUG_REG0__ia_busy_MASK 0x4 #define IA_DEBUG_REG0__ia_busy__SHIFT 0x2 #define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8 #define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3 #define IA_DEBUG_REG0__SPARE0_MASK 0x10 #define IA_DEBUG_REG0__SPARE0__SHIFT 0x4 #define IA_DEBUG_REG0__dma_req_busy_MASK 0x20 #define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5 #define IA_DEBUG_REG0__dma_busy_MASK 0x40 #define IA_DEBUG_REG0__dma_busy__SHIFT 0x6 #define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80 #define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7 #define IA_DEBUG_REG0__grp_busy_MASK 0x100 #define IA_DEBUG_REG0__grp_busy__SHIFT 0x8 #define IA_DEBUG_REG0__SPARE1_MASK 0x200 #define IA_DEBUG_REG0__SPARE1__SHIFT 0x9 #define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400 #define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa #define IA_DEBUG_REG0__grp_dma_read_MASK 0x800 #define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb #define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000 #define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc #define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000 #define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd #define IA_DEBUG_REG0__SPARE2_MASK 0xffc000 #define IA_DEBUG_REG0__SPARE2__SHIFT 0xe #define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 #define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 #define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000 #define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19 #define IA_DEBUG_REG0__SPARE3_MASK 0x4000000 #define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a #define IA_DEBUG_REG0__SPARE4_MASK 0x8000000 #define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b #define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 #define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c #define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 #define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d #define IA_DEBUG_REG0__SPARE5_MASK 0x40000000 #define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e #define IA_DEBUG_REG0__SPARE6_MASK 0x80000000 #define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f #define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1 #define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0 #define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2 #define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1 #define IA_DEBUG_REG1__start_new_packet_MASK 0x4 #define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2 #define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8 #define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3 #define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10 #define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4 #define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60 #define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5 #define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80 #define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7 #define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100 #define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8 #define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200 #define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9 #define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400 #define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa #define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800 #define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb #define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000 #define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc #define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000 #define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd #define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000 #define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe #define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000 #define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf #define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000 #define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10 #define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000 #define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11 #define IA_DEBUG_REG1__stage2_dr_MASK 0x40000 #define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12 #define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000 #define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13 #define IA_DEBUG_REG1__stage3_dr_MASK 0x100000 #define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14 #define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000 #define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15 #define IA_DEBUG_REG1__stage4_dr_MASK 0x400000 #define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16 #define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000 #define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17 #define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000 #define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18 #define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000 #define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19 #define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000 #define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a #define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000 #define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b #define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000 #define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c #define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000 #define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d #define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000 #define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e #define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000 #define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f #define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1 #define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0 #define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2 #define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1 #define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4 #define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2 #define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8 #define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3 #define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10 #define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4 #define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60 #define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5 #define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80 #define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7 #define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100 #define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8 #define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200 #define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9 #define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400 #define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa #define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800 #define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb #define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000 #define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc #define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000 #define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd #define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000 #define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe #define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000 #define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf #define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000 #define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10 #define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000 #define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11 #define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000 #define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12 #define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000 #define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13 #define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000 #define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14 #define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000 #define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15 #define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000 #define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16 #define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000 #define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17 #define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000 #define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18 #define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000 #define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19 #define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000 #define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a #define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000 #define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b #define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000 #define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c #define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000 #define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d #define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000 #define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e #define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000 #define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f #define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1 #define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0 #define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2 #define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1 #define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4 #define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2 #define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8 #define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3 #define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10 #define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4 #define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20 #define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5 #define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40 #define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6 #define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80 #define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7 #define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100 #define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8 #define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200 #define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9 #define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400 #define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa #define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800 #define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb #define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000 #define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc #define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000 #define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd #define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000 #define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe #define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000 #define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf #define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000 #define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10 #define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000 #define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11 #define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000 #define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12 #define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000 #define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13 #define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000 #define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14 #define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000 #define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15 #define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000 #define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16 #define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000 #define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17 #define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000 #define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18 #define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000 #define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a #define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000 #define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b #define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000 #define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c #define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000 #define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d #define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000 #define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e #define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000 #define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f #define IA_DEBUG_REG4__pipe0_dr_MASK 0x1 #define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0 #define IA_DEBUG_REG4__pipe1_dr_MASK 0x2 #define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1 #define IA_DEBUG_REG4__pipe2_dr_MASK 0x4 #define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2 #define IA_DEBUG_REG4__pipe3_dr_MASK 0x8 #define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3 #define IA_DEBUG_REG4__pipe4_dr_MASK 0x10 #define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4 #define IA_DEBUG_REG4__pipe5_dr_MASK 0x20 #define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5 #define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40 #define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6 #define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80 #define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7 #define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100 #define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8 #define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200 #define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9 #define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400 #define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa #define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800 #define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb #define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000 #define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc #define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000 #define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd #define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000 #define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe #define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000 #define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf #define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000 #define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10 #define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000 #define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11 #define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000 #define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14 #define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000 #define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15 #define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000 #define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18 #define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000 #define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19 #define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000 #define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a #define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000 #define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c #define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000 #define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d #define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000 #define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e #define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000 #define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f #define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff #define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0 #define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000 #define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10 #define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000 #define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e #define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000 #define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f #define IA_DEBUG_REG6__current_shift_q_MASK 0xf #define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0 #define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0 #define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4 #define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00 #define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8 #define IA_DEBUG_REG6__first_group_partial_MASK 0x2000 #define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd #define IA_DEBUG_REG6__second_group_partial_MASK 0x4000 #define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe #define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000 #define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf #define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000 #define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10 #define IA_DEBUG_REG6__next_group_partial_MASK 0x200000 #define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15 #define IA_DEBUG_REG6__after_group_partial_MASK 0x400000 #define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16 #define IA_DEBUG_REG6__extract_group_MASK 0x800000 #define IA_DEBUG_REG6__extract_group__SHIFT 0x17 #define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000 #define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18 #define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf #define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0 #define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0 #define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4 #define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00 #define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8 #define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000 #define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc #define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000 #define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10 #define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000 #define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14 #define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000 #define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17 #define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000 #define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18 #define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000 #define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19 #define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000 #define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a #define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000 #define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b #define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000 #define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c #define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000 #define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d #define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000 #define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e #define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000 #define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f #define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f #define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0 #define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20 #define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5 #define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40 #define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6 #define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80 #define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7 #define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100 #define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8 #define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200 #define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9 #define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400 #define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa #define IA_DEBUG_REG8__grp_continued_MASK 0x800 #define IA_DEBUG_REG8__grp_continued__SHIFT 0xb #define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000 #define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc #define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000 #define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf #define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000 #define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15 #define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000 #define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18 #define IA_DEBUG_REG8__grp_eop_MASK 0x2000000 #define IA_DEBUG_REG8__grp_eop__SHIFT 0x19 #define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000 #define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a #define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000 #define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b #define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000 #define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c #define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1 #define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0 #define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2 #define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1 #define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4 #define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2 #define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8 #define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3 #define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10 #define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4 #define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20 #define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5 #define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40 #define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6 #define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80 #define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7 #define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100 #define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8 #define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200 #define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9 #define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400 #define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa #define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800 #define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb #define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000 #define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc #define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000 #define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd #define IA_DEBUG_REG9__SPARE0_MASK 0x4000 #define IA_DEBUG_REG9__SPARE0__SHIFT 0xe #define IA_DEBUG_REG9__SPARE1_MASK 0x8000 #define IA_DEBUG_REG9__SPARE1__SHIFT 0xf #define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000 #define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10 #define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000 #define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11 #define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000 #define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12 #define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000 #define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13 #define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000 #define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14 #define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1 #define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0 #define VGT_DEBUG_REG0__SPARE9_MASK 0x2 #define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1 #define VGT_DEBUG_REG0__vgt_busy_MASK 0x4 #define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2 #define VGT_DEBUG_REG0__SPARE8_MASK 0x8 #define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3 #define VGT_DEBUG_REG0__SPARE7_MASK 0x10 #define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4 #define VGT_DEBUG_REG0__SPARE6_MASK 0x20 #define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5 #define VGT_DEBUG_REG0__SPARE5_MASK 0x40 #define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6 #define VGT_DEBUG_REG0__SPARE4_MASK 0x80 #define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7 #define VGT_DEBUG_REG0__pi_busy_MASK 0x100 #define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8 #define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200 #define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9 #define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400 #define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa #define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800 #define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb #define VGT_DEBUG_REG0__gs_busy_MASK 0x1000 #define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc #define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000 #define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd #define VGT_DEBUG_REG0__tm_busy_MASK 0x4000 #define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe #define VGT_DEBUG_REG0__cm_busy_MASK 0x8000 #define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf #define VGT_DEBUG_REG0__gog_busy_MASK 0x10000 #define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10 #define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000 #define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11 #define VGT_DEBUG_REG0__SPARE10_MASK 0x40000 #define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12 #define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000 #define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13 #define VGT_DEBUG_REG0__SPARE3_MASK 0x100000 #define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14 #define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000 #define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15 #define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000 #define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16 #define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000 #define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17 #define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 #define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 #define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000 #define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19 #define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000 #define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a #define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000 #define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b #define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000 #define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c #define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 #define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d #define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000 #define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e #define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000 #define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f #define VGT_DEBUG_REG1__SPARE9_MASK 0x1 #define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0 #define VGT_DEBUG_REG1__SPARE8_MASK 0x2 #define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1 #define VGT_DEBUG_REG1__SPARE7_MASK 0x4 #define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2 #define VGT_DEBUG_REG1__SPARE6_MASK 0x8 #define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3 #define VGT_DEBUG_REG1__SPARE5_MASK 0x10 #define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4 #define VGT_DEBUG_REG1__SPARE4_MASK 0x20 #define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5 #define VGT_DEBUG_REG1__SPARE3_MASK 0x40 #define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6 #define VGT_DEBUG_REG1__SPARE2_MASK 0x80 #define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7 #define VGT_DEBUG_REG1__SPARE1_MASK 0x100 #define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8 #define VGT_DEBUG_REG1__SPARE0_MASK 0x200 #define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9 #define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400 #define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa #define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800 #define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb #define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000 #define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc #define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000 #define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd #define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000 #define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe #define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000 #define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf #define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000 #define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10 #define VGT_DEBUG_REG1__SPARE12_MASK 0x20000 #define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11 #define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000 #define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12 #define VGT_DEBUG_REG1__SPARE11_MASK 0x80000 #define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13 #define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000 #define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14 #define VGT_DEBUG_REG1__SPARE10_MASK 0x200000 #define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15 #define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000 #define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16 #define VGT_DEBUG_REG1__SPARE23_MASK 0x800000 #define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17 #define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000 #define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18 #define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000 #define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19 #define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000 #define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a #define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000 #define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b #define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000 #define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c #define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000 #define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d #define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000 #define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e #define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000 #define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f #define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1 #define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0 #define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2 #define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1 #define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4 #define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2 #define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8 #define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3 #define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10 #define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4 #define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20 #define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5 #define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40 #define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6 #define VGT_DEBUG_REG2__grpModBusy_MASK 0x80 #define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7 #define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100 #define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8 #define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200 #define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9 #define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400 #define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa #define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800 #define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb #define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000 #define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc #define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000 #define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd #define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000 #define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe #define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000 #define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf #define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000 #define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10 #define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000 #define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11 #define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000 #define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12 #define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000 #define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13 #define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000 #define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14 #define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000 #define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15 #define VGT_DEBUG_REG2__p0_dr_MASK 0x400000 #define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16 #define VGT_DEBUG_REG2__p1_dr_MASK 0x800000 #define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17 #define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000 #define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18 #define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000 #define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19 #define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000 #define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a #define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000 #define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b #define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000 #define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c #define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000 #define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d #define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff #define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0 #define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000 #define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc #define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000 #define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12 #define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000 #define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a #define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff #define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0 #define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00 #define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8 #define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000 #define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18 #define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000 #define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d #define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000 #define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e #define VGT_DEBUG_REG4__SPARE_MASK 0x80000000 #define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f #define VGT_DEBUG_REG5__SPARE4_MASK 0x7 #define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0 #define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8 #define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3 #define VGT_DEBUG_REG5__SPARE3_MASK 0x700 #define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8 #define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800 #define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb #define VGT_DEBUG_REG5__SPARE2_MASK 0x70000 #define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10 #define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000 #define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13 #define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000 #define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18 #define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000 #define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b #define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff #define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0 #define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000 #define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10 #define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1 #define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0 #define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2 #define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1 #define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4 #define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2 #define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8 #define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3 #define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10 #define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4 #define VGT_DEBUG_REG7__SPARE_MASK 0xffe0 #define VGT_DEBUG_REG7__SPARE__SHIFT 0x5 #define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000 #define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10 #define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1 #define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0 #define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2 #define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1 #define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4 #define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2 #define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8 #define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3 #define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10 #define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4 #define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20 #define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5 #define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40 #define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6 #define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80 #define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7 #define VGT_DEBUG_REG8__valid_r2_MASK 0x100 #define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8 #define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200 #define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9 #define VGT_DEBUG_REG8__r0_rtr_MASK 0x400 #define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa #define VGT_DEBUG_REG8__r1_rtr_MASK 0x800 #define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb #define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000 #define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc #define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000 #define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd #define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000 #define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe #define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000 #define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf #define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000 #define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10 #define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000 #define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11 #define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000 #define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12 #define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000 #define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13 #define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000 #define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14 #define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000 #define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15 #define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000 #define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16 #define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000 #define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17 #define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000 #define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18 #define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000 #define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19 #define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000 #define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a #define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000 #define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b #define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000 #define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c #define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000 #define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d #define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000 #define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e #define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000 #define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f #define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3 #define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0 #define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4 #define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2 #define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8 #define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3 #define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10 #define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4 #define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20 #define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5 #define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40 #define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6 #define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80 #define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7 #define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100 #define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8 #define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200 #define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9 #define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400 #define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa #define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800 #define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb #define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000 #define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12 #define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000 #define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13 #define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000 #define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16 #define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000 #define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17 #define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000 #define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18 #define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000 #define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19 #define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000 #define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a #define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000 #define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b #define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000 #define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c #define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000 #define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d #define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000 #define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e #define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000 #define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f #define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f #define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0 #define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20 #define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5 #define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40 #define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6 #define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180 #define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7 #define VGT_DEBUG_REG10__SPARE2_MASK 0x600 #define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9 #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800 #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000 #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc #define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000 #define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd #define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000 #define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17 #define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1 #define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0 #define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2 #define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1 #define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4 #define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2 #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8 #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3 #define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10 #define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4 #define VGT_DEBUG_REG11__SPARE1_MASK 0x20 #define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5 #define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40 #define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6 #define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80 #define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7 #define VGT_DEBUG_REG11__hold_eswave_MASK 0x100 #define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8 #define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200 #define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9 #define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400 #define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa #define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800 #define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb #define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000 #define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc #define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000 #define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd #define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000 #define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe #define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000 #define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf #define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000 #define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10 #define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000 #define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11 #define VGT_DEBUG_REG11__SPARE0_MASK 0x40000 #define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12 #define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000 #define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13 #define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000 #define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14 #define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000 #define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15 #define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000 #define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16 #define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000 #define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17 #define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000 #define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18 #define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000 #define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19 #define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000 #define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000 #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b #define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000 #define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c #define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000 #define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d #define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000 #define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e #define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000 #define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f #define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7 #define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0 #define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38 #define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3 #define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0 #define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6 #define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00 #define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9 #define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000 #define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc #define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000 #define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf #define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000 #define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12 #define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000 #define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15 #define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000 #define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18 #define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000 #define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b #define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000 #define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e #define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000 #define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f #define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7 #define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0 #define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38 #define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3 #define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0 #define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6 #define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00 #define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9 #define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000 #define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc #define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000 #define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf #define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000 #define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12 #define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000 #define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16 #define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000 #define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17 #define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000 #define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18 #define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000 #define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19 #define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000 #define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a #define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000 #define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b #define VGT_DEBUG_REG14__SPARE3_MASK 0xf #define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0 #define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10 #define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4 #define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20 #define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5 #define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40 #define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6 #define VGT_DEBUG_REG14__SPARE8_MASK 0x180 #define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7 #define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200 #define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9 #define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400 #define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa #define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800 #define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb #define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000 #define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc #define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000 #define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15 #define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000 #define VGT_DEBUG_REG14__SPARE__SHIFT 0x16 #define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000 #define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19 #define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000 #define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a #define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000 #define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b #define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000 #define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c #define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000 #define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d #define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000 #define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e #define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000 #define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f #define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1 #define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0 #define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2 #define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1 #define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4 #define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2 #define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8 #define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3 #define VGT_DEBUG_REG15__counters_full_MASK 0x10 #define VGT_DEBUG_REG15__counters_full__SHIFT 0x4 #define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0 #define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5 #define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00 #define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa #define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000 #define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf #define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000 #define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14 #define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000 #define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a #define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000 #define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c #define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000 #define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d #define VGT_DEBUG_REG16__gog_busy_MASK 0x1 #define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0 #define VGT_DEBUG_REG16__gog_state_q_MASK 0xe #define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1 #define VGT_DEBUG_REG16__r0_rtr_MASK 0x10 #define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4 #define VGT_DEBUG_REG16__r1_rtr_MASK 0x20 #define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5 #define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40 #define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6 #define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80 #define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7 #define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100 #define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8 #define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200 #define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9 #define VGT_DEBUG_REG16__r2_rtr_MASK 0x400 #define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa #define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800 #define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb #define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000 #define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc #define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000 #define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd #define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000 #define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe #define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000 #define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf #define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000 #define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10 #define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000 #define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11 #define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000 #define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12 #define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000 #define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13 #define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000 #define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14 #define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000 #define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15 #define VGT_DEBUG_REG16__send_event_q_MASK 0x400000 #define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16 #define VGT_DEBUG_REG16__SPARE24_MASK 0x800000 #define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17 #define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000 #define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18 #define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000 #define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19 #define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000 #define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c #define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000 #define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d #define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000 #define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e #define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000 #define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f #define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f #define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0 #define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0 #define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6 #define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000 #define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc #define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000 #define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12 #define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1 #define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0 #define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2 #define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1 #define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4 #define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2 #define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8 #define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3 #define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10 #define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4 #define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20 #define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5 #define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40 #define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6 #define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80 #define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7 #define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700 #define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8 #define VGT_DEBUG_REG18__valid_indices_MASK 0x800 #define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb #define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000 #define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc #define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000 #define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd #define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000 #define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe #define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000 #define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf #define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000 #define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10 #define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000 #define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11 #define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000 #define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12 #define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000 #define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13 #define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000 #define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14 #define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000 #define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15 #define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000 #define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16 #define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000 #define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17 #define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000 #define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18 #define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000 #define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b #define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000 #define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c #define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000 #define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d #define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1 #define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0 #define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2 #define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1 #define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4 #define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2 #define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8 #define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3 #define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10 #define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4 #define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20 #define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5 #define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40 #define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6 #define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80 #define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7 #define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100 #define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8 #define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200 #define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9 #define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400 #define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa #define VGT_DEBUG_REG19__hold_prim_MASK 0x800 #define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb #define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000 #define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc #define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000 #define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd #define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000 #define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe #define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000 #define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf #define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000 #define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10 #define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000 #define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11 #define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000 #define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12 #define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000 #define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13 #define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000 #define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14 #define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000 #define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a #define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000 #define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b #define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000 #define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c #define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000 #define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e #define VGT_DEBUG_REG19__filter_event_MASK 0x80000000 #define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0 #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000 #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10 #define VGT_DEBUG_REG20__SPARE17_MASK 0x20000 #define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11 #define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000 #define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12 #define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000 #define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16 #define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000 #define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d #define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000 #define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e #define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000 #define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f #define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1 #define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0 #define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2 #define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1 #define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4 #define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2 #define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8 #define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3 #define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10 #define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4 #define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20 #define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5 #define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40 #define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6 #define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80 #define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7 #define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100 #define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8 #define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200 #define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9 #define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400 #define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa #define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800 #define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb #define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000 #define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc #define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000 #define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd #define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000 #define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe #define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000 #define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf #define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000 #define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10 #define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000 #define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11 #define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000 #define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14 #define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000 #define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15 #define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000 #define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16 #define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000 #define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17 #define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000 #define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18 #define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000 #define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19 #define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000 #define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a #define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000 #define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b #define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000 #define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c #define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000 #define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d #define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000 #define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e #define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000 #define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f #define VGT_DEBUG_REG22__cm_state16_MASK 0x3 #define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0 #define VGT_DEBUG_REG22__cm_state17_MASK 0xc #define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2 #define VGT_DEBUG_REG22__cm_state18_MASK 0x30 #define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4 #define VGT_DEBUG_REG22__cm_state19_MASK 0xc0 #define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6 #define VGT_DEBUG_REG22__cm_state20_MASK 0x300 #define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8 #define VGT_DEBUG_REG22__cm_state21_MASK 0xc00 #define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa #define VGT_DEBUG_REG22__cm_state22_MASK 0x3000 #define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc #define VGT_DEBUG_REG22__cm_state23_MASK 0xc000 #define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe #define VGT_DEBUG_REG22__cm_state24_MASK 0x30000 #define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10 #define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000 #define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12 #define VGT_DEBUG_REG22__cm_state26_MASK 0x300000 #define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14 #define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000 #define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16 #define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000 #define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18 #define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000 #define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a #define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000 #define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c #define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000 #define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e #define VGT_DEBUG_REG23__frmt_busy_MASK 0x1 #define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0 #define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2 #define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1 #define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4 #define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2 #define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8 #define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3 #define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10 #define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4 #define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20 #define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5 #define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40 #define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6 #define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80 #define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7 #define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100 #define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8 #define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200 #define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9 #define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400 #define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa #define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800 #define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb #define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000 #define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc #define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000 #define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd #define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000 #define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe #define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000 #define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf #define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000 #define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11 #define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000 #define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15 #define VGT_DEBUG_REG23__SPARE_MASK 0xff000000 #define VGT_DEBUG_REG23__SPARE__SHIFT 0x18 #define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff #define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0 #define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000 #define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18 #define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000 #define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a #define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff #define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0 #define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000 #define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a #define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000 #define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e #define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000 #define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f #define VGT_DEBUG_REG26__cm_state0_MASK 0x3 #define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0 #define VGT_DEBUG_REG26__cm_state1_MASK 0xc #define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2 #define VGT_DEBUG_REG26__cm_state2_MASK 0x30 #define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4 #define VGT_DEBUG_REG26__cm_state3_MASK 0xc0 #define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6 #define VGT_DEBUG_REG26__cm_state4_MASK 0x300 #define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8 #define VGT_DEBUG_REG26__cm_state5_MASK 0xc00 #define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa #define VGT_DEBUG_REG26__cm_state6_MASK 0x3000 #define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc #define VGT_DEBUG_REG26__cm_state7_MASK 0xc000 #define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe #define VGT_DEBUG_REG26__cm_state8_MASK 0x30000 #define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10 #define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000 #define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12 #define VGT_DEBUG_REG26__cm_state10_MASK 0x300000 #define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14 #define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000 #define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16 #define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000 #define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18 #define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000 #define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a #define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000 #define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c #define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000 #define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e #define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1 #define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0 #define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2 #define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1 #define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4 #define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2 #define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8 #define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3 #define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10 #define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4 #define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20 #define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5 #define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40 #define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6 #define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80 #define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7 #define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300 #define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8 #define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400 #define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa #define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800 #define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb #define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000 #define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc #define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000 #define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe #define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000 #define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf #define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000 #define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10 #define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000 #define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11 #define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000 #define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12 #define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000 #define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13 #define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000 #define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14 #define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000 #define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f #define VGT_DEBUG_REG28__con_state_q_MASK 0xf #define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0 #define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10 #define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4 #define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20 #define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5 #define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40 #define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 #define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80 #define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7 #define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100 #define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8 #define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200 #define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9 #define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400 #define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa #define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800 #define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb #define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000 #define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc #define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000 #define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd #define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000 #define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe #define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000 #define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf #define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000 #define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10 #define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000 #define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11 #define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000 #define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12 #define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000 #define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13 #define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000 #define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14 #define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000 #define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 #define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000 #define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16 #define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000 #define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17 #define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000 #define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18 #define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000 #define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19 #define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000 #define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a #define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000 #define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b #define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000 #define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c #define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000 #define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d #define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000 #define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e #define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000 #define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f #define VGT_DEBUG_REG29__con_state_q_MASK 0xf #define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0 #define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10 #define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4 #define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20 #define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5 #define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40 #define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 #define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80 #define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7 #define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100 #define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8 #define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200 #define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9 #define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400 #define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa #define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800 #define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb #define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000 #define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc #define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000 #define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd #define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000 #define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe #define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000 #define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf #define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000 #define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10 #define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000 #define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11 #define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000 #define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12 #define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000 #define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13 #define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000 #define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14 #define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000 #define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 #define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000 #define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16 #define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000 #define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17 #define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000 #define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18 #define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000 #define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19 #define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000 #define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a #define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000 #define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b #define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000 #define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c #define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000 #define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d #define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000 #define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e #define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000 #define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f #define VGT_DEBUG_REG30__pipe0_dr_MASK 0x1 #define VGT_DEBUG_REG30__pipe0_dr__SHIFT 0x0 #define VGT_DEBUG_REG30__pipe0_tf_dr_MASK 0x2 #define VGT_DEBUG_REG30__pipe0_tf_dr__SHIFT 0x1 #define VGT_DEBUG_REG30__pipe2_dr_MASK 0x4 #define VGT_DEBUG_REG30__pipe2_dr__SHIFT 0x2 #define VGT_DEBUG_REG30__event_or_null_p0_q_MASK 0x8 #define VGT_DEBUG_REG30__event_or_null_p0_q__SHIFT 0x3 #define VGT_DEBUG_REG30__pipe0_rtr_MASK 0x10 #define VGT_DEBUG_REG30__pipe0_rtr__SHIFT 0x4 #define VGT_DEBUG_REG30__pipe1_rtr_MASK 0x20 #define VGT_DEBUG_REG30__pipe1_rtr__SHIFT 0x5 #define VGT_DEBUG_REG30__pipe1_tf_rtr_MASK 0x40 #define VGT_DEBUG_REG30__pipe1_tf_rtr__SHIFT 0x6 #define VGT_DEBUG_REG30__pipe2_rtr_MASK 0x80 #define VGT_DEBUG_REG30__pipe2_rtr__SHIFT 0x7 #define VGT_DEBUG_REG30__ttp_patch_fifo_full_MASK 0x100 #define VGT_DEBUG_REG30__ttp_patch_fifo_full__SHIFT 0x8 #define VGT_DEBUG_REG30__ttp_patch_fifo_empty_MASK 0x200 #define VGT_DEBUG_REG30__ttp_patch_fifo_empty__SHIFT 0x9 #define VGT_DEBUG_REG30__ttp_tf0_fifo_empty_MASK 0x400 #define VGT_DEBUG_REG30__ttp_tf0_fifo_empty__SHIFT 0xa #define VGT_DEBUG_REG30__ttp_tf1_fifo_empty_MASK 0x800 #define VGT_DEBUG_REG30__ttp_tf1_fifo_empty__SHIFT 0xb #define VGT_DEBUG_REG30__ttp_tf2_fifo_empty_MASK 0x1000 #define VGT_DEBUG_REG30__ttp_tf2_fifo_empty__SHIFT 0xc #define VGT_DEBUG_REG30__ttp_tf3_fifo_empty_MASK 0x2000 #define VGT_DEBUG_REG30__ttp_tf3_fifo_empty__SHIFT 0xd #define VGT_DEBUG_REG30__ttp_tf4_fifo_empty_MASK 0x4000 #define VGT_DEBUG_REG30__ttp_tf4_fifo_empty__SHIFT 0xe #define VGT_DEBUG_REG30__ttp_tf5_fifo_empty_MASK 0x8000 #define VGT_DEBUG_REG30__ttp_tf5_fifo_empty__SHIFT 0xf #define VGT_DEBUG_REG30__tf_fetch_state_q_MASK 0x70000 #define VGT_DEBUG_REG30__tf_fetch_state_q__SHIFT 0x10 #define VGT_DEBUG_REG30__last_tf_of_tg_MASK 0x80000 #define VGT_DEBUG_REG30__last_tf_of_tg__SHIFT 0x13 #define VGT_DEBUG_REG30__tf_pointer_p0_q_MASK 0xf00000 #define VGT_DEBUG_REG30__tf_pointer_p0_q__SHIFT 0x14 #define VGT_DEBUG_REG30__dynamic_hs_p0_q_MASK 0x1000000 #define VGT_DEBUG_REG30__dynamic_hs_p0_q__SHIFT 0x18 #define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q_MASK 0x2000000 #define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q__SHIFT 0x19 #define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q_MASK 0x4000000 #define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q__SHIFT 0x1a #define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q_MASK 0x8000000 #define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q__SHIFT 0x1b #define VGT_DEBUG_REG30__tf_xfer_count_p2_q_MASK 0x30000000 #define VGT_DEBUG_REG30__tf_xfer_count_p2_q__SHIFT 0x1c #define VGT_DEBUG_REG30__pipe4_dr_MASK 0x40000000 #define VGT_DEBUG_REG30__pipe4_dr__SHIFT 0x1e #define VGT_DEBUG_REG30__pipe4_rtr_MASK 0x80000000 #define VGT_DEBUG_REG30__pipe4_rtr__SHIFT 0x1f #define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1 #define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0 #define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2 #define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1 #define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4 #define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2 #define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8 #define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3 #define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10 #define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4 #define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20 #define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5 #define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40 #define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6 #define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80 #define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7 #define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100 #define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8 #define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200 #define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9 #define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400 #define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa #define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800 #define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb #define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000 #define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc #define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000 #define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd #define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000 #define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe #define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000 #define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf #define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000 #define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10 #define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000 #define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11 #define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000 #define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12 #define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000 #define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13 #define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000 #define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14 #define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000 #define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15 #define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000 #define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16 #define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000 #define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17 #define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000 #define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18 #define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000 #define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19 #define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000 #define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a #define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000 #define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b #define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000 #define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c #define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000 #define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d #define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000 #define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e #define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000 #define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f #define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1 #define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0 #define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2 #define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1 #define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4 #define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2 #define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8 #define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3 #define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10 #define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4 #define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20 #define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5 #define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40 #define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6 #define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80 #define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7 #define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100 #define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8 #define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200 #define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9 #define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400 #define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa #define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800 #define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb #define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000 #define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc #define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000 #define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe #define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000 #define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf #define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000 #define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10 #define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000 #define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11 #define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000 #define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12 #define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000 #define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13 #define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000 #define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14 #define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000 #define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15 #define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000 #define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16 #define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000 #define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17 #define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000 #define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18 #define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000 #define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19 #define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000 #define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a #define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000 #define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b #define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000 #define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c #define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1 #define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0 #define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2 #define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1 #define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4 #define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2 #define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8 #define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3 #define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10 #define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4 #define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20 #define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5 #define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40 #define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6 #define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80 #define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7 #define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100 #define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8 #define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200 #define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9 #define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400 #define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa #define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800 #define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb #define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000 #define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc #define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000 #define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd #define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000 #define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe #define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000 #define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf #define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000 #define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10 #define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000 #define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11 #define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000 #define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12 #define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000 #define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13 #define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000 #define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14 #define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000 #define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15 #define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000 #define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16 #define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000 #define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17 #define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000 #define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18 #define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000 #define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a #define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000 #define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c #define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000 #define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d #define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000 #define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e #define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000 #define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f #define VGT_DEBUG_REG34__con_state_q_MASK 0xf #define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0 #define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10 #define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4 #define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20 #define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5 #define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40 #define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 #define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80 #define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7 #define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100 #define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8 #define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200 #define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9 #define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400 #define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa #define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800 #define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb #define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000 #define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc #define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000 #define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd #define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000 #define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe #define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000 #define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf #define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000 #define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10 #define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000 #define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11 #define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000 #define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12 #define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000 #define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13 #define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000 #define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14 #define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000 #define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 #define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000 #define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16 #define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000 #define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17 #define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000 #define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18 #define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000 #define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19 #define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000 #define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a #define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000 #define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b #define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000 #define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c #define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000 #define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d #define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000 #define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e #define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000 #define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f #define VGT_DEBUG_REG35__pipe0_dr_MASK 0x1 #define VGT_DEBUG_REG35__pipe0_dr__SHIFT 0x0 #define VGT_DEBUG_REG35__pipe1_dr_MASK 0x2 #define VGT_DEBUG_REG35__pipe1_dr__SHIFT 0x1 #define VGT_DEBUG_REG35__pipe0_rtr_MASK 0x4 #define VGT_DEBUG_REG35__pipe0_rtr__SHIFT 0x2 #define VGT_DEBUG_REG35__pipe1_rtr_MASK 0x8 #define VGT_DEBUG_REG35__pipe1_rtr__SHIFT 0x3 #define VGT_DEBUG_REG35__tfreq_tg_fifo_empty_MASK 0x10 #define VGT_DEBUG_REG35__tfreq_tg_fifo_empty__SHIFT 0x4 #define VGT_DEBUG_REG35__tfreq_tg_fifo_full_MASK 0x20 #define VGT_DEBUG_REG35__tfreq_tg_fifo_full__SHIFT 0x5 #define VGT_DEBUG_REG35__tf_data_fifo_busy_q_MASK 0x40 #define VGT_DEBUG_REG35__tf_data_fifo_busy_q__SHIFT 0x6 #define VGT_DEBUG_REG35__tf_data_fifo_rtr_q_MASK 0x80 #define VGT_DEBUG_REG35__tf_data_fifo_rtr_q__SHIFT 0x7 #define VGT_DEBUG_REG35__tf_skid_fifo_empty_MASK 0x100 #define VGT_DEBUG_REG35__tf_skid_fifo_empty__SHIFT 0x8 #define VGT_DEBUG_REG35__tf_skid_fifo_full_MASK 0x200 #define VGT_DEBUG_REG35__tf_skid_fifo_full__SHIFT 0x9 #define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q_MASK 0x400 #define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q__SHIFT 0xa #define VGT_DEBUG_REG35__last_req_of_tg_p2_MASK 0x800 #define VGT_DEBUG_REG35__last_req_of_tg_p2__SHIFT 0xb #define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q_MASK 0x3f000 #define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q__SHIFT 0xc #define VGT_DEBUG_REG35__event_flag_p1_q_MASK 0x40000 #define VGT_DEBUG_REG35__event_flag_p1_q__SHIFT 0x12 #define VGT_DEBUG_REG35__null_flag_p1_q_MASK 0x80000 #define VGT_DEBUG_REG35__null_flag_p1_q__SHIFT 0x13 #define VGT_DEBUG_REG35__tf_data_fifo_cnt_q_MASK 0x7f00000 #define VGT_DEBUG_REG35__tf_data_fifo_cnt_q__SHIFT 0x14 #define VGT_DEBUG_REG35__second_tf_ret_data_q_MASK 0x8000000 #define VGT_DEBUG_REG35__second_tf_ret_data_q__SHIFT 0x1b #define VGT_DEBUG_REG35__first_req_of_tg_p1_q_MASK 0x10000000 #define VGT_DEBUG_REG35__first_req_of_tg_p1_q__SHIFT 0x1c #define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out_MASK 0x20000000 #define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out__SHIFT 0x1d #define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out_MASK 0x40000000 #define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out__SHIFT 0x1e #define VGT_DEBUG_REG35__TC_VGT_rdret_data_in_MASK 0x80000000 #define VGT_DEBUG_REG35__TC_VGT_rdret_data_in__SHIFT 0x1f #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff #define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c #define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff #define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c #define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff #define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 #define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 #define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c #define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff #define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 #define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 #define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff #define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 #define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa #define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 #define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 #define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 #define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 #define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 #define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c #define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff #define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 #define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c #define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff #define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 #define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 #define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c #define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff #define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 #define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 #define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff #define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 #define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 #define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c #define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff #define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 #define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 #define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c #define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff #define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 #define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 #define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c #define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff #define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 #define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 #define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 #define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff #define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 #define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff #define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 #define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1 #define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 #define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2 #define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2 #define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10 #define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 #define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff #define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 #define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000 #define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 #define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff #define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b #define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff #define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 #define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00 #define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 #define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000 #define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 #define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000 #define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 #define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff #define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 #define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00 #define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 #define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000 #define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 #define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000 #define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 #define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff #define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 #define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00 #define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 #define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000 #define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 #define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000 #define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 #define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1 #define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 #define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2 #define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2 #define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10 #define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 #define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff #define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 #define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000 #define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 #define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff #define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b #define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff #define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 #define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00 #define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 #define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000 #define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 #define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000 #define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 #define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff #define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 #define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00 #define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 #define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000 #define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 #define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000 #define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 #define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff #define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 #define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00 #define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 #define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000 #define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 #define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000 #define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 #define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1 #define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 #define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2 #define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1 #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2 #define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10 #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 #define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff #define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 #define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000 #define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 #define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff #define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b #define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff #define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 #define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00 #define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 #define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000 #define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 #define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000 #define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 #define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff #define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 #define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00 #define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 #define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000 #define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 #define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000 #define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 #define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff #define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 #define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00 #define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 #define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000 #define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 #define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000 #define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 #define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1 #define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 #define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2 #define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1 #define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2 #define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10 #define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 #define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff #define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 #define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000 #define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 #define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff #define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b #define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff #define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 #define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00 #define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 #define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000 #define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 #define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000 #define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 #define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff #define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 #define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00 #define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 #define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000 #define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 #define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000 #define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 #define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff #define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 #define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00 #define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 #define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000 #define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 #define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000 #define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 #endif /* GFX_7_2_SH_MASK_H */ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/include/kfd_pm4_opcodes.h000066400000000000000000000107751446477712600257130ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef KFD_PM4_OPCODES_H #define KFD_PM4_OPCODES_H enum it_opcode_type { IT_NOP = 0x10, IT_SET_BASE = 0x11, IT_CLEAR_STATE = 0x12, IT_INDEX_BUFFER_SIZE = 0x13, IT_DISPATCH_DIRECT = 0x15, IT_DISPATCH_INDIRECT = 0x16, IT_ATOMIC_GDS = 0x1D, IT_OCCLUSION_QUERY = 0x1F, IT_SET_PREDICATION = 0x20, IT_REG_RMW = 0x21, IT_COND_EXEC = 0x22, IT_PRED_EXEC = 0x23, IT_DRAW_INDIRECT = 0x24, IT_DRAW_INDEX_INDIRECT = 0x25, IT_INDEX_BASE = 0x26, IT_DRAW_INDEX_2 = 0x27, IT_CONTEXT_CONTROL = 0x28, IT_INDEX_TYPE = 0x2A, IT_DRAW_INDIRECT_MULTI = 0x2C, IT_DRAW_INDEX_AUTO = 0x2D, IT_NUM_INSTANCES = 0x2F, IT_DRAW_INDEX_MULTI_AUTO = 0x30, IT_INDIRECT_BUFFER_CNST = 0x33, IT_STRMOUT_BUFFER_UPDATE = 0x34, IT_DRAW_INDEX_OFFSET_2 = 0x35, IT_DRAW_PREAMBLE = 0x36, IT_WRITE_DATA = 0x37, IT_DRAW_INDEX_INDIRECT_MULTI = 0x38, IT_MEM_SEMAPHORE = 0x39, IT_COPY_DW = 0x3B, IT_WAIT_REG_MEM = 0x3C, IT_INDIRECT_BUFFER = 0x3F, IT_COPY_DATA = 0x40, IT_PFP_SYNC_ME = 0x42, IT_SURFACE_SYNC = 0x43, IT_COND_WRITE = 0x45, IT_EVENT_WRITE = 0x46, IT_EVENT_WRITE_EOP = 0x47, IT_EVENT_WRITE_EOS = 0x48, IT_RELEASE_MEM = 0x49, IT_PREAMBLE_CNTL = 0x4A, IT_DMA_DATA = 0x50, IT_ACQUIRE_MEM = 0x58, IT_REWIND = 0x59, IT_LOAD_UCONFIG_REG = 0x5E, IT_LOAD_SH_REG = 0x5F, IT_LOAD_CONFIG_REG = 0x60, IT_LOAD_CONTEXT_REG = 0x61, IT_SET_CONFIG_REG = 0x68, IT_SET_CONTEXT_REG = 0x69, IT_SET_CONTEXT_REG_INDIRECT = 0x73, IT_SET_SH_REG = 0x76, IT_SET_SH_REG_OFFSET = 0x77, IT_SET_QUEUE_REG = 0x78, IT_SET_UCONFIG_REG = 0x79, IT_SCRATCH_RAM_WRITE = 0x7D, IT_SCRATCH_RAM_READ = 0x7E, IT_LOAD_CONST_RAM = 0x80, IT_WRITE_CONST_RAM = 0x81, IT_DUMP_CONST_RAM = 0x83, IT_INCREMENT_CE_COUNTER = 0x84, IT_INCREMENT_DE_COUNTER = 0x85, IT_WAIT_ON_CE_COUNTER = 0x86, IT_WAIT_ON_DE_COUNTER_DIFF = 0x88, IT_SWITCH_BUFFER = 0x8B, IT_SET_RESOURCES = 0xA0, IT_MAP_PROCESS = 0xA1, IT_MAP_QUEUES = 0xA2, IT_UNMAP_QUEUES = 0xA3, IT_QUERY_STATUS = 0xA4, IT_RUN_LIST = 0xA5, }; #define PM4_TYPE_0 0 #define PM4_TYPE_2 2 #define PM4_TYPE_3 3 #endif /* KFD_PM4_OPCODES_H */ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/include/pm4_pkt_struct_ai.h000066400000000000000000000124311446477712600262750ustar00rootroot00000000000000/* * Copyright (C) 2016-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __PM4_PKT_STRUCT_AI_H__ #define __PM4_PKT_STRUCT_AI_H__ #ifndef PM4_MEC_RELEASE_MEM_AI_DEFINED #define PM4_MEC_RELEASE_MEM_AI_DEFINED enum AI_MEC_RELEASE_MEM_event_index_enum { event_index__mec_release_mem__end_of_pipe = 5, event_index__mec_release_mem__shader_done = 6 }; enum AI_MEC_RELEASE_MEM_cache_policy_enum { cache_policy__mec_release_mem__lru = 0, cache_policy__mec_release_mem__stream = 1 }; enum AI_MEC_RELEASE_MEM_pq_exe_status_enum { pq_exe_status__mec_release_mem__default = 0, pq_exe_status__mec_release_mem__phase_update = 1 }; enum AI_MEC_RELEASE_MEM_dst_sel_enum { dst_sel__mec_release_mem__memory_controller = 0, dst_sel__mec_release_mem__tc_l2 = 1, dst_sel__mec_release_mem__queue_write_pointer_register = 2, dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 }; enum AI_MEC_RELEASE_MEM_int_sel_enum { int_sel__mec_release_mem__none = 0, int_sel__mec_release_mem__send_interrupt_only = 1, int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2, int_sel__mec_release_mem__send_data_after_write_confirm = 3, int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4, int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5, int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 }; enum AI_MEC_RELEASE_MEM_data_sel_enum { data_sel__mec_release_mem__none = 0, data_sel__mec_release_mem__send_32_bit_low = 1, data_sel__mec_release_mem__send_64_bit_data = 2, data_sel__mec_release_mem__send_gpu_clock_counter = 3, data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4, data_sel__mec_release_mem__store_gds_data_to_memory = 5 }; typedef struct PM4_MEC_RELEASE_MEM_AI { union { PM4_TYPE_3_HEADER header; unsigned int ordinal1; }; union { struct { unsigned int event_type:6; unsigned int reserved1:2; AI_MEC_RELEASE_MEM_event_index_enum event_index:4; unsigned int tcl1_vol_action_ena:1; unsigned int tc_vol_action_ena:1; unsigned int reserved2:1; unsigned int tc_wb_action_ena:1; unsigned int tcl1_action_ena:1; unsigned int tc_action_ena:1; unsigned int reserved3:1; unsigned int tc_nc_action_ena:1; unsigned int tc_wc_action_ena:1; unsigned int tc_md_action_ena:1; unsigned int reserved4:3; AI_MEC_RELEASE_MEM_cache_policy_enum cache_policy:2; unsigned int reserved5:2; AI_MEC_RELEASE_MEM_pq_exe_status_enum pq_exe_status:1; unsigned int reserved6:2; } bitfields2; unsigned int ordinal2; }; union { struct { unsigned int reserved7:16; AI_MEC_RELEASE_MEM_dst_sel_enum dst_sel:2; unsigned int reserved8:6; AI_MEC_RELEASE_MEM_int_sel_enum int_sel:3; unsigned int reserved9:2; AI_MEC_RELEASE_MEM_data_sel_enum data_sel:3; } bitfields3; unsigned int ordinal3; }; union { struct { unsigned int reserved10:2; unsigned int address_lo_32b:30; } bitfields4a; struct { unsigned int reserved11:3; unsigned int address_lo_64b:29; } bitfields4b; unsigned int reserved12; unsigned int ordinal4; }; union { unsigned int address_hi; unsigned int reserved13; unsigned int ordinal5; }; union { unsigned int data_lo; unsigned int cmp_data_lo; struct { unsigned int dw_offset:16; unsigned int num_dwords:16; } bitfields6c; unsigned int reserved14; unsigned int ordinal6; }; union { unsigned int data_hi; unsigned int cmp_data_hi; unsigned int reserved15; unsigned int reserved16; unsigned int ordinal7; }; unsigned int int_ctxid; } PM4MEC_RELEASE_MEM_AI, *PPM4MEC_RELEASE_MEM_AI; #endif // PM4_MEC_RELEASE_MEM_AI_DEFINED #endif // __PM4_PKT_STRUCT_AI_H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/include/pm4_pkt_struct_ci.h000066400000000000000000000104011446477712600262720ustar00rootroot00000000000000/* * Copyright (C) 2012-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __PM4_PKT_STRUCT_CI_H__ #define __PM4_PKT_STRUCT_CI_H__ enum WRITE_DATA_CI_atc_enum { atc_write_data_NOT_USE_ATC_0 = 0, atc_write_data_USE_ATC_1 = 1 }; enum WRITE_DATA_CI_engine_sel { engine_sel_write_data_ci_MICRO_ENGINE_0 = 0, engine_sel_write_data_ci_PREFETCH_PARSER_1 = 1, engine_sel_write_data_ci_CONST_ENG_2 = 2 }; typedef struct _PM4WRITE_DATA_CI { union { PM4_TYPE_3_HEADER header; unsigned int ordinal1; }; union { struct { unsigned int reserved1:8; MEC_WRITE_DATA_dst_sel_enum dst_sel:4; unsigned int reserved2:4; MEC_WRITE_DATA_addr_incr_enum addr_incr:1; unsigned int reserved3:3; MEC_WRITE_DATA_wr_confirm_enum wr_confirm:1; unsigned int reserved4:3; WRITE_DATA_CI_atc_enum atc:1; MEC_WRITE_DATA_cache_policy_enum cache_policy:2; unsigned int volatile_setting:1; unsigned int reserved5:2; WRITE_DATA_CI_engine_sel engine_sel:2; } bitfields2; unsigned int ordinal2; }; unsigned int dst_addr_lo; unsigned int dst_address_hi; unsigned int data[1]; // 1..N of these fields } PM4WRITE_DATA_CI, *PPM4WRITE_DATA_CI; enum MEC_RELEASE_MEM_CI_atc_enum { atc_mec_release_mem_ci_NOT_USE_ATC_0 = 0, atc_mec_release_mem_ci_USE_ATC_1 = 1 }; typedef struct _PM4_RELEASE_MEM_CI { union { PM4_TYPE_3_HEADER header; unsigned int ordinal1; }; union { struct { unsigned int event_type:6; unsigned int reserved1:2; MEC_RELEASE_MEM_event_index_enum event_index:4; unsigned int l1_vol:1; unsigned int l2_vol:1; unsigned int reserved:1; unsigned int l2_wb:1; unsigned int l1_inv:1; unsigned int l2_inv:1; unsigned int reserved2:6; MEC_RELEASE_MEM_CI_atc_enum atc:1; MEC_RELEASE_MEM_cache_policy_enum cache_policy:2; unsigned int volatile_setting:1; unsigned int reserved3:4; } bitfields2; unsigned int ordinal2; }; union { struct { unsigned int reserved4:16; MEC_RELEASE_MEM_dst_sel_enum dst_sel:2; unsigned int reserved5:6; MEC_RELEASE_MEM_int_sel_enum int_sel:3; unsigned int reserved6:2; MEC_RELEASE_MEM_data_sel_enum data_sel:3; } bitfields3; unsigned int ordinal3; }; union { struct { unsigned int reserved7:2; unsigned int address_lo_dword_aligned:30; } bitfields4a; struct { unsigned int reserved8:3; unsigned int address_lo_qword_aligned:29; } bitfields4b; unsigned int ordinal4; }; unsigned int addr_hi; union { unsigned int data_lo; struct { unsigned int offset:16; unsigned int num_dwords:16; } bitfields5b; unsigned int ordinal6; }; unsigned int data_hi; } PM4_RELEASE_MEM_CI, *PPM4_RELEASE_MEM_CI; #endif // __PM4_PKT_STRUCT_CI_H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/include/pm4_pkt_struct_common.h000066400000000000000000000245641446477712600272060ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __PM4_PKT_STRUCT_COMMON_H__ #define __PM4_PKT_STRUCT_COMMON_H__ #ifndef PM4_HEADER_DEFINED #define PM4_HEADER_DEFINED typedef union PM4_TYPE_3_HEADER { struct { unsigned int predicate : 1; ///< predicated version of packet when set unsigned int shaderType: 1; ///< 0: Graphics, 1: Compute Shader unsigned int reserved1 : 6; ///< reserved unsigned int opcode : 8; ///< IT opcode unsigned int count : 14;///< number of DWORDs - 1 in the information body. unsigned int type : 2; ///< packet identifier. It should be 3 for type 3 packets }; unsigned int u32All; } PM4_TYPE_3_HEADER; #endif // PM4_HEADER_DEFINED //--------------------DISPATCH_DIRECT-------------------- typedef struct _PM4_DISPATCH_DIRECT { union { PM4_TYPE_3_HEADER header; ///header unsigned int ordinal1; }; unsigned int dim_x; unsigned int dim_y; unsigned int dim_z; unsigned int dispatch_initiator; } PM4DISPATCH_DIRECT, *PPM4DISPATCH_DIRECT; //--------------------INDIRECT_BUFFER-------------------- enum INDIRECT_BUFFER_cache_policy_enum { cache_policy_indirect_buffer_LRU_0 = 0, cache_policy_indirect_buffer_STREAM_1 = 1, cache_policy_indirect_buffer_BYPASS_2 = 2 }; //--------------------EVENT_WRITE-------------------- enum EVENT_WRITE_event_index_enum { event_index_event_write_OTHER_0 = 0, event_index_event_write_ZPASS_DONE_1 = 1, event_index_event_write_SAMPLE_PIPELINESTAT_2 = 2, event_index_event_write_SAMPLE_STREAMOUTSTAT_3 = 3, event_index_event_write_CS_VS_PS_PARTIAL_FLUSH_4 = 4, event_index_event_write_RESERVED_EOP_5 = 5, event_index_event_write_RESERVED_EOS_6 = 6, event_index_event_write_CACHE_FLUSH_7 = 7 }; typedef struct _PM4_EVENT_WRITE { union { PM4_TYPE_3_HEADER header; ///header unsigned int ordinal1; }; union { struct { unsigned int event_type:6; unsigned int reserved1:2; EVENT_WRITE_event_index_enum event_index:4; unsigned int reserved2:20; } bitfields2; unsigned int ordinal2; }; union { struct { unsigned int reserved3:3; unsigned int address_lo:29; } bitfields3; unsigned int ordinal3; }; union { struct { unsigned int address_hi:16; unsigned int reserved4:16; } bitfields4; unsigned int ordinal4; }; } PM4EVENT_WRITE, *PPM4EVENT_WRITE; //--------------------SET_SH_REG-------------------- typedef struct _PM4_SET_SH_REG { union { PM4_TYPE_3_HEADER header; ///header unsigned int ordinal1; }; union { struct { unsigned int reg_offset:16; unsigned int reserved1:16; } bitfields2; unsigned int ordinal2; }; unsigned int reg_data[1]; //1..N of these fields } PM4SET_SH_REG, *PPM4SET_SH_REG; //--------------------ACQUIRE_MEM-------------------- enum ACQUIRE_MEM_engine_enum { engine_acquire_mem_PFP_0 = 0, engine_acquire_mem_ME_1 = 1 }; typedef struct _PM4_ACQUIRE_MEM { union { PM4_TYPE_3_HEADER header; ///header unsigned int ordinal1; }; union { struct { unsigned int coher_cntl:31; ACQUIRE_MEM_engine_enum engine:1; } bitfields2; unsigned int ordinal2; }; unsigned int coher_size; union { struct { unsigned int coher_size_hi:8; unsigned int reserved1:24; } bitfields3; unsigned int ordinal4; }; unsigned int coher_base_lo; union { struct { unsigned int coher_base_hi:25; unsigned int reserved2:7; } bitfields4; unsigned int ordinal6; }; union { struct { unsigned int poll_interval:16; unsigned int reserved3:16; } bitfields5; unsigned int ordinal7; }; } PM4ACQUIRE_MEM, *PPM4ACQUIRE_MEM; //--------------------MEC_INDIRECT_BUFFER-------------------- typedef struct _PM4_MEC_INDIRECT_BUFFER { union { PM4_TYPE_3_HEADER header; ///header unsigned int ordinal1; }; union { struct { unsigned int swap_function:2; unsigned int ib_base_lo:30; } bitfields2; unsigned int ordinal2; }; union { struct { unsigned int ib_base_hi:16; unsigned int reserved1:16; } bitfields3; unsigned int ordinal3; }; union { struct { unsigned int ib_size:20; unsigned int chain:1; unsigned int offload_polling:1; unsigned int volatile_setting:1; unsigned int valid:1; unsigned int vmid:4; INDIRECT_BUFFER_cache_policy_enum cache_policy:2; unsigned int reserved4:2; } bitfields4; unsigned int ordinal4; }; } PM4MEC_INDIRECT_BUFFER, *PPM4MEC_INDIRECT_BUFFER; //--------------------MEC_WAIT_REG_MEM-------------------- enum MEC_WAIT_REG_MEM_function_enum { function__mec_wait_reg_mem__always_pass = 0, function__mec_wait_reg_mem__less_than_ref_value = 1, function__mec_wait_reg_mem__less_than_equal_to_the_ref_value = 2, function__mec_wait_reg_mem__equal_to_the_reference_value = 3, function__mec_wait_reg_mem__not_equal_reference_value = 4, function__mec_wait_reg_mem__greater_than_or_equal_reference_value = 5, function__mec_wait_reg_mem__greater_than_reference_value = 6 }; enum MEC_WAIT_REG_MEM_mem_space_enum { mem_space__mec_wait_reg_mem__register_space = 0, mem_space__mec_wait_reg_mem__memory_space = 1 }; enum MEC_WAIT_REG_MEM_operation_enum { operation__mec_wait_reg_mem__wait_reg_mem = 0, operation__mec_wait_reg_mem__wr_wait_wr_reg = 1, operation__mec_wait_reg_mem__wait_mem_preemptable = 3 }; typedef struct PM4_MEC_WAIT_REG_MEM { union { PM4_TYPE_3_HEADER header; ///header uint32_t ordinal1; }; union { struct { MEC_WAIT_REG_MEM_function_enum function:3; uint32_t reserved1:1; MEC_WAIT_REG_MEM_mem_space_enum mem_space:2; MEC_WAIT_REG_MEM_operation_enum operation:2; uint32_t reserved2:24; } bitfields2; uint32_t ordinal2; }; union { struct { uint32_t reserved3:2; uint32_t mem_poll_addr_lo:30; } bitfields3a; struct { uint32_t reg_poll_addr:18; uint32_t reserved4:14; } bitfields3b; struct { uint32_t reg_write_addr1:18; uint32_t reserved5:14; } bitfields3c; uint32_t ordinal3; }; union { uint32_t mem_poll_addr_hi; struct { uint32_t reg_write_addr2:18; uint32_t reserved6:14; } bitfields4b; uint32_t ordinal4; }; uint32_t reference; uint32_t mask; union { struct { uint32_t poll_interval:16; uint32_t reserved7:15; uint32_t optimize_ace_offload_mode:1; } bitfields7; uint32_t ordinal7; }; } PM4MEC_WAIT_REG_MEM, *PPM4MEC_WAIT_REG_MEM; //--------------------MEC_WRITE_DATA-------------------- enum MEC_WRITE_DATA_dst_sel_enum { dst_sel_mec_write_data_MEM_MAPPED_REGISTER_0 = 0, dst_sel_mec_write_data_TC_L2_2 = 2, dst_sel_mec_write_data_GDS_3 = 3, dst_sel_mec_write_data_MEMORY_5 = 5 }; enum MEC_WRITE_DATA_addr_incr_enum { addr_incr_mec_write_data_INCREMENT_ADDR_0 = 0, addr_incr_mec_write_data_DO_NOT_INCREMENT_ADDR_1 = 1 }; enum MEC_WRITE_DATA_wr_confirm_enum { wr_confirm_mec_write_data_DO_NOT_WAIT_FOR_CONFIRMATION_0 = 0, wr_confirm_mec_write_data_WAIT_FOR_CONFIRMATION_1 = 1 }; enum MEC_WRITE_DATA_cache_policy_enum { cache_policy_mec_write_data_LRU_0 = 0, cache_policy_mec_write_data_STREAM_1 = 1, cache_policy_mec_write_data_BYPASS_2 = 2 }; //--------------------MEC_RELEASE_MEM-------------------- enum MEC_RELEASE_MEM_event_index_enum { event_index_mec_release_mem_EVENT_WRITE_EOP_5 = 5, event_index_mec_release_mem_CS_Done_6 = 6 }; enum MEC_RELEASE_MEM_cache_policy_enum { cache_policy_mec_release_mem_LRU_0 = 0, cache_policy_mec_release_mem_STREAM_1 = 1, cache_policy_mec_release_mem_BYPASS_2 = 2 }; enum MEC_RELEASE_MEM_dst_sel_enum { dst_sel_mec_release_mem_MEMORY_CONTROLLER_0 = 0, dst_sel_mec_release_mem_TC_L2_1 = 1 }; enum MEC_RELEASE_MEM_int_sel_enum { int_sel_mec_release_mem_NONE_0 = 0, int_sel_mec_release_mem_SEND_INTERRUPT_ONLY_1 = 1, int_sel_mec_release_mem_SEND_INTERRUPT_AFTER_WRITE_CONFIRM_2 = 2, int_sel_mec_release_mem_SEND_DATA_AFTER_WRITE_CONFIRM_3 = 3 }; enum MEC_RELEASE_MEM_data_sel_enum { data_sel_mec_release_mem_NONE_0 = 0, data_sel_mec_release_mem_SEND_32_BIT_LOW_1 = 1, data_sel_mec_release_mem_SEND_64_BIT_DATA_2 = 2, data_sel_mec_release_mem_SEND_GPU_CLOCK_COUNTER_3 = 3, data_sel_mec_release_mem_SEND_CP_PERFCOUNTER_HI_LO_4 = 4, data_sel_mec_release_mem_STORE_GDS_DATA_TO_MEMORY_5 = 5 }; #endif ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/include/pm4_pkt_struct_nv.h000066400000000000000000000103331446477712600263260ustar00rootroot00000000000000/* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __PM4__PKT__STRUCT__NV__HPP__ #define __PM4__PKT__STRUCT__NV__HPP__ #include "pm4_pkt_struct_ai.h" typedef struct _PM4_ACQUIRE_MEM_NV { union { PM4_TYPE_3_HEADER header; ///header unsigned int ordinal1; }; unsigned int reserved; unsigned int coher_size; union { struct { unsigned int coher_size_hi:8; unsigned int reserved1:24; } bitfields3; unsigned int ordinal4; }; unsigned int coher_base_lo; union { struct { unsigned int coher_base_hi:24; unsigned int reserved2:8; } bitfields4; unsigned int ordinal6; }; union { struct { unsigned int poll_interval:16; unsigned int reserved3:16; } bitfields5; unsigned int ordinal7; }; union { struct { unsigned int gcr_cntl:18; unsigned int reserved4:14; } bitfields6; unsigned int ordinal8; }; } PM4ACQUIRE_MEM_NV, *PPM4ACQUIRE_MEM_NV; typedef struct PM4_MEC_RELEASE_MEM_NV { union { PM4_TYPE_3_HEADER header; unsigned int ordinal1; }; union { struct { unsigned int event_type:6; unsigned int reserved1:2; AI_MEC_RELEASE_MEM_event_index_enum event_index:4; unsigned int gcr_cntl:12; unsigned int reserved4:1; AI_MEC_RELEASE_MEM_cache_policy_enum cache_policy:2; unsigned int reserved5:1; AI_MEC_RELEASE_MEM_pq_exe_status_enum pq_exe_status:1; unsigned int reserved6:3; } bitfields2; unsigned int ordinal2; }; union { struct { unsigned int reserved7:16; AI_MEC_RELEASE_MEM_dst_sel_enum dst_sel:2; unsigned int reserved8:6; AI_MEC_RELEASE_MEM_int_sel_enum int_sel:3; unsigned int reserved9:2; AI_MEC_RELEASE_MEM_data_sel_enum data_sel:3; } bitfields3; unsigned int ordinal3; }; union { struct { unsigned int reserved10:2; unsigned int address_lo_32b:30; } bitfields4a; struct { unsigned int reserved11:3; unsigned int address_lo_64b:29; } bitfields4b; unsigned int reserved12; unsigned int ordinal4; }; union { unsigned int address_hi; unsigned int reserved13; unsigned int ordinal5; }; union { unsigned int data_lo; unsigned int cmp_data_lo; struct { unsigned int dw_offset:16; unsigned int num_dwords:16; } bitfields6c; unsigned int reserved14; unsigned int ordinal6; }; union { unsigned int data_hi; unsigned int cmp_data_hi; unsigned int reserved15; unsigned int reserved16; unsigned int ordinal7; }; unsigned int int_ctxid; } PM4MEC_RELEASE_MEM_NV, *PPM4MEC_RELEASE_MEM_NV; #endif // __PM4__PKT__STRUCT__NV__HPP__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/include/sdma_pkt_struct.h000066400000000000000000000174001446477712600260510ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __SDMA_PKT_STRUCT_H__ #define __SDMA_PKT_STRUCT_H__ const unsigned int SDMA_OP_NOP = 0; const unsigned int SDMA_OP_COPY = 1; const unsigned int SDMA_OP_WRITE = 2; const unsigned int SDMA_OP_FENCE = 5; const unsigned int SDMA_OP_TRAP = 6; const unsigned int SDMA_OP_TIMESTAMP = 13; const unsigned int SDMA_OP_CONST_FILL = 11; const unsigned int SDMA_SUBOP_COPY_LINEAR = 0; const unsigned int SDMA_SUBOP_WRITE_LINEAR = 0; /* ** Definitions for SDMA_PKT_COPY_LINEAR packet */ typedef struct SDMA_PKT_COPY_LINEAR_TAG { union { struct { unsigned int op:8; unsigned int sub_op:8; unsigned int reserved_0:11; unsigned int broadcast:1; unsigned int reserved_1:4; }; unsigned int DW_0_DATA; } HEADER_UNION; union { struct { unsigned int count:22; unsigned int reserved_0:10; }; unsigned int DW_1_DATA; } COUNT_UNION; union { struct { unsigned int reserved_0:16; unsigned int dst_sw:2; unsigned int reserved_1:4; unsigned int dst_ha:1; unsigned int reserved_2:1; unsigned int src_sw:2; unsigned int reserved_3:4; unsigned int src_ha:1; unsigned int reserved_4:1; }; unsigned int DW_2_DATA; } PARAMETER_UNION; union { struct { unsigned int src_addr_31_0:32; }; unsigned int DW_3_DATA; } SRC_ADDR_LO_UNION; union { struct { unsigned int src_addr_63_32:32; }; unsigned int DW_4_DATA; } SRC_ADDR_HI_UNION; struct { union { struct { unsigned int dst_addr_31_0:32; }; unsigned int DW_5_DATA; } DST_ADDR_LO_UNION; union { struct { unsigned int dst_addr_63_32:32; }; unsigned int DW_6_DATA; } DST_ADDR_HI_UNION; } DST_ADDR[0]; } SDMA_PKT_COPY_LINEAR, *PSDMA_PKT_COPY_LINEAR; /* ** Definitions for SDMA_PKT_WRITE_UNTILED packet */ typedef struct SDMA_PKT_WRITE_UNTILED_TAG { union { struct { unsigned int op:8; unsigned int sub_op:8; unsigned int reserved_0:16; }; unsigned int DW_0_DATA; } HEADER_UNION; union { struct { unsigned int dst_addr_31_0:32; }; unsigned int DW_1_DATA; } DST_ADDR_LO_UNION; union { struct { unsigned int dst_addr_63_32:32; }; unsigned int DW_2_DATA; } DST_ADDR_HI_UNION; union { struct { unsigned int count:22; unsigned int reserved_0:2; unsigned int sw:2; unsigned int reserved_1:6; }; unsigned int DW_3_DATA; } DW_3_UNION; union { struct { unsigned int data0:32; }; unsigned int DW_4_DATA; } DATA0_UNION; } SDMA_PKT_WRITE_UNTILED, *PSDMA_PKT_WRITE_UNTILED; /* ** Definitions for SDMA_PKT_FENCE packet */ typedef struct SDMA_PKT_FENCE_TAG { union { struct { unsigned int op:8; unsigned int sub_op:8; unsigned int reserved_0:16; }; unsigned int DW_0_DATA; } HEADER_UNION; union { struct { unsigned int addr_31_0:32; }; unsigned int DW_1_DATA; } ADDR_LO_UNION; union { struct { unsigned int addr_63_32:32; }; unsigned int DW_2_DATA; } ADDR_HI_UNION; union { struct { unsigned int data:32; }; unsigned int DW_3_DATA; } DATA_UNION; } SDMA_PKT_FENCE, *PSDMA_PKT_FENCE; /* ** Definitions for SDMA_PKT_CONSTANT_FILL packet */ typedef struct SDMA_PKT_CONSTANT_FILL_TAG { union { struct { unsigned int op:8; unsigned int sub_op:8; unsigned int sw:2; unsigned int reserved_0:12; unsigned int fillsize:2; }; unsigned int DW_0_DATA; } HEADER_UNION; union { struct { unsigned int dst_addr_31_0:32; }; unsigned int DW_1_DATA; } DST_ADDR_LO_UNION; union { struct { unsigned int dst_addr_63_32:32; }; unsigned int DW_2_DATA; } DST_ADDR_HI_UNION; union { struct { unsigned int src_data_31_0:32; }; unsigned int DW_3_DATA; } DATA_UNION; union { struct { unsigned int count:22; unsigned int reserved_0:10; }; unsigned int DW_4_DATA; } COUNT_UNION; } SDMA_PKT_CONSTANT_FILL, *PSDMA_PKT_CONSTANT_FILL; /* ** Definitions for SDMA_PKT_TRAP packet */ typedef struct SDMA_PKT_TRAP_TAG { union { struct { unsigned int op:8; unsigned int sub_op:8; unsigned int reserved_0:16; }; unsigned int DW_0_DATA; } HEADER_UNION; union { struct { unsigned int int_context:28; unsigned int reserved_0:4; }; unsigned int DW_1_DATA; } INT_CONTEXT_UNION; } SDMA_PKT_TRAP, *PSDMA_PKT_TRAP; /* ** Definitions for SDMA_PKT_TIMESTAMP packet */ typedef struct SDMA_PKT_TIMESTAMP_TAG { union { struct { unsigned int op:8; unsigned int sub_op:8; unsigned int reserved_0:16; }; unsigned int DW_0_DATA; } HEADER_UNION; union { struct { unsigned int addr_31_0:32; }; unsigned int DW_1_DATA; } ADDR_LO_UNION; union { struct { unsigned int addr_63_32:32; }; unsigned int DW_2_DATA; } ADDR_HI_UNION; } SDMA_PKT_TIMESTAMP, *PSDMA_PKT_TIMESTAMP; /* ** Definitions for SDMA_PKT_NOP packet */ typedef struct SDMA_PKT_NOP_TAG { union { struct { unsigned int op:8; unsigned int sub_op:8; unsigned int count:14; unsigned int reserved_0:2; }; unsigned int DW_0_DATA; } HEADER_UNION; union { struct { unsigned int data0:32; }; unsigned int DW_1_DATA; } DATA0_UNION; } SDMA_PKT_NOP, *PSDMA_PKT_NOP; #endif // __SDMA_PKT_STRUCT_H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/scripts/000077500000000000000000000000001446477712600225345ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/scripts/kfdtest.exclude000066400000000000000000000225221446477712600255560ustar00rootroot00000000000000declare -A FILTER # Power management tests FILTER[pm]=\ "KFDPMTest.SuspendWithActiveProcess:"\ "KFDPMTest.SuspendWithIdleQueue:"\ "KFDPMTest.SuspendWithIdleQueueAfterWork" # Core tests, used in scenarios like bringup # Software scheduler mode, i. e. non HWS mode FILTER[core_sws]=\ "KFDQMTest.CreateDestroyCpQueue:"\ "KFDQMTest.SubmitNopCpQueue:"\ "KFDQMTest.SubmitPacketCpQueue:"\ "KFDQMTest.AllCpQueues:"\ "KFDQMTest.CreateDestroySdmaQueue:"\ "KFDQMTest.SubmitNopSdmaQueue:"\ "KFDQMTest.SubmitPacketSdmaQueue:"\ "KFDQMTest.AllSdmaQueues:"\ "KFDQMTest.AllXgmiSdmaQueues:"\ "KFDQMTest.AllQueues:"\ "KFDLocalMemoryTest.AccessLocalMem:"\ "KFDEventTest.SignalEvent" # HWS mode FILTER[core]=\ "${FILTER[core_sws]}:"\ "KFDCWSRTest.BasicTest" # Permanent exclusions # These tests are included for debugging, but are not executed in normal execution on any ASIC: # FILTER[pm] need human intervention, so put it here. Developers can run them # manually through "-p pm" option. # # Fragmentation test fails intermittently on different systems (see KFD-344). It # stresses memory management in unusual ways by having lots of memory allocated but # not mapped, which is not relevant to compute applications over ROCr. # # CU Masking Linear are not working correctly due to how the HW distributes work over CUs. # They are available for testing but are not currently expected to pass on CI/VI/AI. # # CU Masking Even is added here due to some non-obvious baseline measurements. Though # using wallclock to measure performance is always risky, there are just too many ASICs # where this test is failing. Ideally we'll get better CU Masking coverage via rocrtst # # The CheckZeroInitializationVram test is no longer expected to pass as KFD no longer # clears memory at allocation time. PERMANENT_BLACKLIST_ALL_ASICS=\ "-KFDEventTest.MeasureInterruptConsumption:"\ "${FILTER[pm]}:"\ "KFDLocalMemoryTest.Fragmentation:"\ "KFDQMTest.BasicCuMaskingLinear:"\ "KFDQMTest.BasicCuMaskingEven:"\ "RDMATest.GPUDirect:"\ "KFDRASTest.*:"\ "KFDLocalMemoryTest.CheckZeroInitializationVram" # This is the temporary blacklist for all ASICs. This is to be used when a test is failing consistently # on every ASIC (Kaveri, Carrizo, Hawaii, Tonga, Fiji, Polaris10, Polaris11 and Vega10 . # TODO means that a JIRA ticket needs to be created for this issue, as no documentation regarding # failures can be found # NOTE: If you update this alphabetical listing, add the corresponding JIRA ticket for reference # # KFDQMTest.GPUDoorbellWrite fails intermittently (KFD-318) # KFDQMTest.mGPUShareBO (KFD-334) # KFDHWSTest.* (SWDEV-193035) # KFDEvictTest.BurstyTest (ROCMOPS-464) # KFDEvictTest.BurstyTest (SWDEV-291256) # KFDEvictTest.BurstyTest (KFD-425) TEMPORARY_BLACKLIST_ALL_ASICS=\ "KFDQMTest.GPUDoorbellWrite:"\ "KFDQMTest.mGPUShareBO:"\ "KFDQMTest.SdmaEventInterrupt:"\ "KFDMemoryTest.CacheInvalidateOnRemoteWrite:"\ "KFDEvictTest.BurstyTest:"\ "KFDHWSTest.*:"\ "KFDSVMRangeTest.ReadOnlyRangeTest*" BLACKLIST_ALL_ASICS=\ "$PERMANENT_BLACKLIST_ALL_ASICS:"\ "$TEMPORARY_BLACKLIST_ALL_ASICS" # SDMA-based tests (KFDIPCTest.BasicTest, KFDQM.*Sdma*, KFDMemoryTest.MMBench) are all # disabled on non-Hawaii due to SDMA instability - SWDEV-101666 SDMA_BLACKLIST=\ "KFDIPCTest.*:"\ "KFDLocalMemoryTest.CheckZeroInitializationVram:"\ "KFDMemoryTest.MemoryRegister:"\ "KFDMemoryTest.MMBench:"\ "KFDMemoryTest.SignalHandling:"\ "KFDQMTest.AllQueues:"\ "KFDQMTest.*Sdma*:"\ "KFDQMTest.CreateQueueStressSingleThreaded:"\ "KFDQMTest.GPUDoorbellWrite:"\ "KFDQMTest.P2PTest:"\ "KFDPerformanceTest.P2PBandWidthTest:"\ "KFDPerformanceTest.P2POverheadTest" # Anything involving CP queue creation is failing on Kaveri. Separate them here for convenience (KFD-336) KV_QUEUE_BLACKLIST=\ "KFDExceptionTest.AddressFault:"\ "KFDExceptionTest.PermissionFault:"\ "KFDLocalMemoryTest.*:"\ "KFDEventTest.Signal*Event*:"\ "KFDQMTest.CreateQueueStressSingleThreaded:"\ "KFDQMTest.*CpQueue*:"\ "KFDQMTest.*Dispatch*:"\ "KFDQMTest.Atomics:"\ "KFDQMTest.GPUDoorbellWrite" # KFDCWSRTest.BasicTest*: SWDEV-353206 BLACKLIST_GFX10=\ "KFDMemoryTest.DeviceHdpFlush:"\ "KFDSVMEvictTest.*:"\ "KFDCWSRTest.BasicTest*" BLACKLIST_GFX10_NV2X=\ "$BLACKLIST_GFX10:"\ "KFDPerfCountersTest.*" # KFDQMTest.MultipleCpQueuesStressDispatch - SWDEV-409990 # KFDMemoryTest.FlatScratchAccess - SWDEV-329877 BLACKLIST_GFX11=\ "KFDQMTest.CreateAqlCpQueue:"\ "KFDQMTest.MultipleCpQueuesStressDispatch:"\ "KFDCWSRTest.InterruptRestore:"\ "KFDPerfCountersTest.*:"\ "KFDMemoryTest.FlatScratchAccess" # KFDQMTest.CpuWriteCoherence fails. 0 dwordsAvailable (KFD-338) # KFDMemoryTest.MemoryRegister fails on SDMA queue creation (KFD-337) FILTER[kaveri]=\ "$BLACKLIST_ALL_ASICS:"\ "$SDMA_BLACKLIST:"\ "$KV_QUEUE_BLACKLIST:"\ "KFDMemoryTest.MemoryRegister:"\ "KFDQMTest.CpuWriteCoherence" # KFDLocalMemoryTest.BasicTest is failing intermittently (KFD-368) # KFDMemoryTest.BigSysBufferStressTest was failing intermittently on 4.9 # and hangs when executed twice (KFD-312) # KFDQMTest.GPUDoorbellWrite fails on Hawaii. Could be HW-related (KFD-342) FILTER[hawaii]=\ "$BLACKLIST_ALL_ASICS:"\ "KFDLocalMemoryTest.BasicTest:"\ "KFDMemoryTest.BigSysBufferStressTest:"\ "KFDQMTest.GPUDoorbellWrite" FILTER[carrizo]=\ "$BLACKLIST_ALL_ASICS:"\ "$SDMA_BLACKLIST:"\ "KFDExceptionTest.PermissionFault" # KFDPerfCountersTest.*Trace fail (KFD-339) # KFDMemoryTest.QueryPointerInfo/MemoryRegister* (KFD-341) # The remaining tests listed here fail on map memory to GPU with a VA conflict (KFD-340) FILTER[tonga]=\ "$BLACKLIST_ALL_ASICS:"\ "$SDMA_BLACKLIST:"\ "KFDCWSRTest.BasicTest:"\ "KFDPerfCountersTest.*:"\ "KFDQMTest.OverSubscribeCpQueues" # Since Navi10 was merged, the PM4Event test takes 6min to run FILTER[fiji]=\ "$BLACKLIST_ALL_ASICS:"\ "KFDQMTest.PM4EventInterrupt:"\ "$SDMA_BLACKLIST" FILTER[polaris10]=\ "$BLACKLIST_ALL_ASICS:"\ "$SDMA_BLACKLIST" FILTER[polaris11]=\ "$BLACKLIST_ALL_ASICS:"\ "$SDMA_BLACKLIST" FILTER[polaris12]=\ "$BLACKLIST_ALL_ASICS:"\ "$SDMA_BLACKLIST" # KFDIPCTest.BasicTest (ROCMOPS-459) .CMABasicTest (ROCMOPS-460) .CrossMemoryAttachTest (ROCMOPS-461) # KFDQMTest.AllSdmaQueues (ROCMOPS-463) FILTER[vega10]=\ "$BLACKLIST_ALL_ASICS:"\ "KFDIPCTest.BasicTest:"\ "KFDIPCTest.CMABasicTest:"\ "KFDIPCTest.CrossMemoryAttachTest:"\ "KFDQMTest.AllSdmaQueues" FILTER[vega12]=\ "$BLACKLIST_ALL_ASICS:"\ "$SDMA_BLACKLIST"\ FILTER[vega20]=\ "$BLACKLIST_ALL_ASICS:"\ "$SDMA_BLACKLIST:"\ "KFDQMTest.GPUDoorbellWrite" FILTER[raven_dgpuFallback]=\ "$BLACKLIST_ALL_ASICS:"\ "$SDMA_BLACKLIST:"\ "KFDEvictTest.*:"\ "KFDMemoryTest.MemoryRegister:"\ "KFDSVMRangeTest.BasicSystemMemTest:"\ "KFDSVMRangeTest.BasicVramTest:"\ "KFDSVMRangeTest.EvictSystemRangeTest:"\ "KFDSVMRangeTest.PartialUnmapSysMemTest:"\ "KFDSVMRangeTest.MigrateTest:"\ "KFDSVMRangeTest.MigratePolicyTest:"\ "KFDSVMRangeTest.MigrateGranularityTest:"\ "KFDSVMRangeTest.MigrateLargeBufTest:"\ "KFDSVMRangeTest.MultiThreadMigrationTest:"\ "KFDSVMRangeTest.MigrateAccessInPlaceTest:"\ "KFDSVMEvictTest.QueueTest" FILTER[raven]=\ "$BLACKLIST_ALL_ASICS:"\ "$SDMA_BLACKLIST:"\ "KFDEvictTest.*:"\ "KFDSVMRangeTest.EvictSystemRangeTest:"\ "KFDSVMRangeTest.PartialUnmapSysMemTest:"\ "KFDSVMRangeTest.PrefetchTest:"\ "KFDSVMRangeTest.MultiThreadMigrationTest:"\ "KFDSVMEvictTest.QueueTest:"\ "KFDQMTest.MultipleCpQueuesStressDispatch" FILTER[renoir]=\ "$BLACKLIST_ALL_ASICS:"\ "KFDEvictTest.*:"\ "KFDMemoryTest.LargestSysBufferTest:"\ "KFDMemoryTest.SignalHandling" # KFDExceptionTest.* (KFD-435) FILTER[arcturus]=\ "$BLACKLIST_ALL_ASICS:"\ "KFDExceptionTest.FaultStorm"\ FILTER[aldebaran]=\ "$BLACKLIST_ALL_ASICS:"\ "KFDExceptionTest.FaultStorm:"\ "KFDMemoryTest.PtraceAccess:"\ "KFDMemoryTest.DeviceHdpFlush" FILTER[navi10]=\ "$BLACKLIST_ALL_ASICS:"\ "$BLACKLIST_GFX10:"\ "KFDMemoryTest.MMBench" # Need to verify the following failed tests on another machine: # Exceptions not being received during exception tests # PerfCounters return HSAKMT_STATUS_INVALID_PARAMETER # P2PBandwidth failing (wait times out) on node-to-multiple-nodes by [push, NONE] FILTER[navi12]=\ "$BLACKLIST_ALL_ASICS:"\ "$BLACKLIST_GFX10:"\ "KFDExceptionTest.*:"\ "KFDPerfCountersTest.*:"\ "KFDPerformanceTest.P2PBandWidthTest" FILTER[navi14]=\ "$BLACKLIST_ALL_ASICS:"\ "$BLACKLIST_GFX10" FILTER[sienna_cichlid]=\ "$BLACKLIST_ALL_ASICS:"\ "$BLACKLIST_GFX10_NV2X" FILTER[navy_flounder]=\ "$BLACKLIST_ALL_ASICS:"\ "$BLACKLIST_GFX10_NV2X" FILTER[dimgrey_cavefish]=\ "$BLACKLIST_ALL_ASICS:"\ "$BLACKLIST_GFX10_NV2X" FILTER[beige_goby]=\ "$BLACKLIST_ALL_ASICS:"\ "$BLACKLIST_GFX10_NV2X" FILTER[yellow_carp]=\ "$BLACKLIST_ALL_ASICS:"\ "$BLACKLIST_GFX10_NV2X" FILTER[gfx1100]=\ "$BLACKLIST_ALL_ASICS:"\ "$BLACKLIST_GFX11" # SWDEV-384028 FILTER[gfx1101]=\ "$BLACKLIST_ALL_ASICS:"\ "$BLACKLIST_GFX11:"\ "KFDExceptionTest.SdmaQueueException" FILTER[gfx1102]=\ "$BLACKLIST_ALL_ASICS:"\ "$BLACKLIST_GFX11" FILTER[gfx1103]=\ "$BLACKLIST_ALL_ASICS:"\ "$BLACKLIST_GFX11" FILTER[gfx1036]=\ "$BLACKLIST_ALL_ASICS:"\ "$BLACKLIST_GFX10_NV2X" FILTER[gfx940]=\ "$BLACKLIST_ALL_ASICS:"\ "KFDMemoryTest.LargestSysBufferTest:"\ "KFDMemoryTest.BigSysBufferStressTest:"\ "KFDMemoryTest.FlatScratchAccess:"\ "KFDIPCTest.BasicTest" FILTER[gfx941]=\ "$BLACKLIST_ALL_ASICS:"\ "KFDMemoryTest.LargestSysBufferTest:"\ "KFDMemoryTest.BigSysBufferStressTest:"\ "KFDMemoryTest.FlatScratchAccess:"\ "KFDIPCTest.BasicTest" FILTER[gfx942]=\ "$BLACKLIST_ALL_ASICS:"\ "KFDMemoryTest.LargestSysBufferTest:"\ "KFDMemoryTest.BigSysBufferStressTest:"\ "KFDMemoryTest.FlatScratchAccess:"\ "KFDIPCTest.BasicTest"ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/scripts/run_kfdtest.sh000077500000000000000000000244221446477712600254270ustar00rootroot00000000000000#!/bin/bash # # Copyright (C) 2018 Advanced Micro Devices, Inc. All Rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR # OTHER DEALINGS IN THE SOFTWARE. # # # See if we can find the SHARE/BIN dirs in their expected locations CWD="${BASH_SOURCE%/*}" while read candidate; do if [ -e "$candidate/kfdtest.exclude" ]; then source "$candidate/kfdtest.exclude" break fi done < , --platform Only run tests that"\ "pass on the specified platform. Usually you"\ "don't need this option" echo " -g , --gdb Run in debugger" echo " -n , --node NodeId to test. If"\ "not specified test will be run on all nodes" echo " -l , --list List available nodes" echo " --high Force clocks to high for test execution" echo " -d , --docker Run in docker container" echo " -e , --exclude Additional tests to exclude, in addition to kfdtest.exclude (colon-separated, single quoted string as an argument)" echo " -h , --help Prints this help" echo echo "Gtest arguments will be forwarded to the app" echo echo "Valid platform options: core_sws, core, polaris10, vega10, vega20, pm, all, and so on" echo "'all' option runs all tests" return 0 } # Print gtest_filter for the given Platform # param - Platform. getFilter() { # For regular platforms such as vega10, this will automatically generate # the valid variable BLACKLIST based on the variable platform. local platform=$1; case "$platform" in all ) gtestFilter="" ;; * ) if [ -z "${FILTER[$platform]}" ]; then echo "Unsupported platform $platform. Exiting" exit 1 fi gtestFilter="--gtest_filter=${FILTER[$platform]}" ;; esac if [ -n "$ADDITIONAL_EXCLUDE" ]; then gtestFilter="$gtestFilter:$ADDITIONAL_EXCLUDE" fi } TOPOLOGY_SYSFS_DIR=/sys/devices/virtual/kfd/kfd/topology/nodes # Prints list of HSA Nodes. HSA Nodes are identified from sysfs KFD topology. The nodes # should have valid SIMD count getHsaNodes() { for i in $(find $TOPOLOGY_SYSFS_DIR -maxdepth 1 -mindepth 1 -type d); do simdcount=$(cat $i/properties | grep simd_count | awk '{print $2}') if [ $simdcount != 0 ]; then hsaNodeList+="$(basename $i) " fi done echo "$hsaNodeList" } # Prints GPU Name for the given Node ID. If transitioned to IP discovery, # use target gfx version # param - Node ID getNodeName() { local nodeId=$1; shift; local gpuName=$(cat $TOPOLOGY_SYSFS_DIR/$nodeId/name) if [ "$gpuName" == "raven" ]; then local CpuCoresCount=$(cat $TOPOLOGY_SYSFS_DIR/$nodeId/properties | grep cpu_cores_count | awk '{print $2}') local SimdCount=$(cat $TOPOLOGY_SYSFS_DIR/$nodeId/properties | grep simd_count | awk '{print $2}') if [ "$CpuCoresCount" -eq 0 ] && [ "$SimdCount" -gt 0 ]; then gpuName="raven_dgpuFallback" fi elif [ "$gpuName" == "ip discovery" ]; then if [ -n "$HSA_OVERRIDE_GFX_VERSION" ]; then gpuName="gfx$(echo "$HSA_OVERRIDE_GFX_VERSION" | awk 'BEGIN {FS="."; RS=""} {printf "%d%x%x", $1, $2, $3 }')" else local GfxVersionDec=$(cat $TOPOLOGY_SYSFS_DIR/$nodeId/properties | grep gfx_target_version | awk '{print $2}') if [[ ${#GfxVersionDec} = 5 ]]; then GfxVersionDec="0${GfxVersionDec}" fi gpuName="gfx$(printf "$GfxVersionDec" | fold -w2 | awk 'BEGIN {FS="\n"; RS=""} {printf "%d%x%x", $1, $2, $3}')" fi fi echo "$gpuName" } # Run KfdTest independently. Two global variables set by command-line # will influence the tests as indicated below # PLATFORM - If set all tests will run with this platform filter # NODE - If set tests will be run only on this NODE, else it will be # run on all available HSA Nodes runKfdTest() { if [ "$RUN_IN_DOCKER" == "true" ]; then if [ `sudo systemctl is-active docker` != "active" ]; then echo "docker isn't active, install and setup docker first!!!!" exit 0 fi PKG_ROOT="$(getPackageRoot)" fi if [ -n "$GTEST_ARGS" ] && [ -n "$ADDITIONAL_EXCLUDE" ]; then echo "Cannot use -e and --gtest_filter flags together" exit 0 fi if [ "$NODE" == "" ]; then hsaNodes=$(getHsaNodes) if [ "$hsaNodes" == "" ]; then echo "No GPU found in the system." exit 1 fi else hsaNodes=$NODE fi for hsaNode in $hsaNodes; do nodeName=$(getNodeName $hsaNode) if [ "$PLATFORM" != "" ] && [ "$PLATFORM" != "$nodeName" ]; then echo "WARNING: Actual ASIC $nodeName treated as $PLATFORM" nodeName="$PLATFORM" fi getFilter $nodeName if [ "$RUN_IN_DOCKER" == "true" ]; then if [ "$NODE" == "" ]; then DEVICE_NODE="/dev/dri" else RENDER_NODE=$(($hsaNode + 127)) DEVICE_NODE="/dev/dri/renderD${RENDER_NODE}" fi echo "Starting testing node $hsaNode ($nodeName) in docker container" sudo docker run -it --name kfdtest_docker --user="jenkins" --network=host \ --device=/dev/kfd --device=${DEVICE_NODE} --group-add video --cap-add=SYS_PTRACE \ --security-opt seccomp=unconfined -v $PKG_ROOT:/home/jenkins/rocm \ compute-artifactory.amd.com:5000/yuho/tianli-ubuntu1604-kfdtest:01 \ /home/jenkins/rocm/utils/run_kfdtest.sh -n $hsaNode $gtestFilter $GTEST_ARGS if [ "$?" = "0" ]; then echo "Finished node $hsaNode ($nodeName) successfully in docker container" else echo "Testing failed for node $hsaNode ($nodeName) in docker container" fi sudo docker rm kfdtest_docker else echo "" echo "++++ Starting testing node $hsaNode ($nodeName) ++++" $GDB $KFDTEST "--node=$hsaNode" $gtestFilter $GTEST_ARGS echo "---- Finished testing node $hsaNode ($nodeName) ----" fi done } # Prints number of GPUs present in the system getGPUCount() { gNodes=$(getHsaNodes) gNodes=( $gNodes ) gpuCount=${#gNodes[@]} echo "$gpuCount" } while [ "$1" != "" ]; do case "$1" in -p | --platform ) shift 1; PLATFORM=$1 ;; -g | --gdb ) GDB="gdb --args" ;; -l | --list ) printGpuNodelist; exit 0 ;; -n | --node ) shift 1; NODE=$1 ;; --high) FORCE_HIGH="true" ;; -d | --docker ) RUN_IN_DOCKER="true" ;; -e | --exclude ) ADDITIONAL_EXCLUDE="$2" ; shift ;; -h | --help ) printUsage; exit 0 ;; *) GTEST_ARGS=$@; break;; esac shift 1 done # If the SMI is missing, just report and continue SMI="$(find /opt/rocm* -type l -name rocm-smi | tail -1)" if [ "$FORCE_HIGH" == "true" ]; then if [ -e "$SMI" ]; then OLDPERF=$($SMI -p | awk '/Performance Level:/ {print $NF; exit}') $($SMI --setperflevel high &> /dev/null) if [ $? != 0 ]; then echo "SMI failed to set perf level" OLDPERF="" fi else echo "Unable to set clocks to high, cannot find rocm-smi" fi fi # Set HSA_DEBUG env to run KFDMemoryTest.PtraceAccessInvisibleVram export HSA_DEBUG=1 runKfdTest # OLDPERF is only set if FORCE_HIGH and SMI both exist if [ -n "$OLDPERF" ]; then $SMI --setperflevel $OLDPERF &> /dev/null fi ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/000077500000000000000000000000001446477712600216345ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/AqlQueue.cpp000066400000000000000000000032031446477712600240600ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "AqlQueue.hpp" #include "GoogleTestExtension.hpp" AqlQueue::AqlQueue(void) { } AqlQueue::~AqlQueue(void) { } unsigned int AqlQueue::Wptr() { return *m_Resources.Queue_write_ptr; } unsigned int AqlQueue::Rptr() { return *m_Resources.Queue_read_ptr; } unsigned int AqlQueue::RptrWhenConsumed() { return Wptr(); } void AqlQueue::SubmitPacket() { // m_pending Wptr is in dwords *m_Resources.Queue_write_ptr = m_pendingWptr; *(m_Resources.Queue_DoorBell) = Wptr(); } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/AqlQueue.hpp000066400000000000000000000036161446477712600240750ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_AQL_QUEUE__H__ #define __KFD_AQL_QUEUE__H__ #include "BaseQueue.hpp" class AqlQueue : public BaseQueue { public: AqlQueue(); virtual ~AqlQueue(); // @brief Updates queue write pointer and sets the queue doorbell to the queue write pointer virtual void SubmitPacket(); // @return Read pointer in dwords virtual unsigned int Rptr(); // @return Write pointer in dwords virtual unsigned int Wptr(); // @return Expected m_Resources.Queue_read_ptr when all packets are consumed virtual unsigned int RptrWhenConsumed(); protected: virtual PACKETTYPE PacketTypeSupported() { return PACKETTYPE_AQL; } virtual _HSA_QUEUE_TYPE GetQueueType() { return HSA_QUEUE_COMPUTE_AQL; } }; #endif // __KFD_AQL_QUEUE__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/Assemble.cpp000066400000000000000000000303461446477712600241010ustar00rootroot00000000000000//////////////////////////////////////////////////////////////////////////////// // // The University of Illinois/NCSA // Open Source License (NCSA) // // Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. // // Developed by: // // AMD Research and AMD HSA Software Development // // Advanced Micro Devices, Inc. // // www.amd.com // // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to // deal with the Software without restriction, including without limitation // the rights to use, copy, modify, merge, publish, distribute, sublicense, // and/or sell copies of the Software, and to permit persons to whom the // Software is furnished to do so, subject to the following conditions: // // - Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimers. // - Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimers in // the documentation and/or other materials provided with the distribution. // - Neither the names of Advanced Micro Devices, Inc, // nor the names of its contributors may be used to endorse or promote // products derived from this Software without specific prior written // permission. // // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL // THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR // OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, // ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER // DEALINGS WITH THE SOFTWARE. // //////////////////////////////////////////////////////////////////////////////// /** * Self-contained assembler that uses the LLVM MC API to assemble AMDGCN * instructions */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if LLVM_VERSION_MAJOR > 13 #include #else #include #endif #include #include "OSWrapper.hpp" #include "Assemble.hpp" using namespace llvm; Assembler::Assembler(const uint32_t Gfxv) { SetTargetAsic(Gfxv); TextData = nullptr; TextSize = 0; LLVMInit(); } Assembler::~Assembler() { FlushText(); llvm_shutdown(); } const char* Assembler::GetInstrStream() { return TextData; } const size_t Assembler::GetInstrStreamSize() { return TextSize; } int Assembler::CopyInstrStream(char* OutBuf, const size_t BufSize) { if (TextSize > BufSize) return -2; std::copy(TextData, TextData + TextSize, OutBuf); return 0; } const char* Assembler::GetTargetAsic() { return MCPU; } /** * Set MCPU via GFX Version from Thunk * LLVM Target IDs use decimal for Maj/Min, hex for Step */ void Assembler::SetTargetAsic(const uint32_t Gfxv) { const uint8_t Major = (Gfxv >> 16) & 0xff; const uint8_t Minor = (Gfxv >> 8) & 0xff; const uint8_t Step = Gfxv & 0xff; snprintf(MCPU, ASM_MCPU_LEN, "gfx%d%d%x", Major, Minor, Step); } /** * Initialize LLVM targets and assembly printers/parsers */ void Assembler::LLVMInit() { LLVMInitializeAMDGPUTargetInfo(); LLVMInitializeAMDGPUTargetMC(); LLVMInitializeAMDGPUAsmParser(); } /** * Flush/reset TextData and TextSize to initial state */ void Assembler::FlushText() { if (TextData) delete[] TextData; TextData = nullptr; TextSize = 0; } /** * Print hex of ELF object to stdout (debug) */ void Assembler::PrintELFHex(const std::string Data) { outs() << "ASM Info: assembled ELF hex data (length " << Data.length() << "):\n"; outs() << "0x00:\t"; for (size_t i = 0; i < Data.length(); ++i) { char c = Data[i]; outs() << format_hex(static_cast(c), 4); if ((i+1) % 16 == 0) outs() << "\n" << format_hex(i+1, 4) << ":\t"; else outs() << " "; } outs() << "\n"; } /** * Print hex of raw instruction stream to stdout (debug) */ void Assembler::PrintTextHex() { outs() << "ASM Info: assembled .text hex data (length " << TextSize << "):\n"; outs() << "0x00:\t"; for (size_t i = 0; i < TextSize; i++) { outs() << format_hex(static_cast(TextData[i]), 4); if ((i+1) % 16 == 0) outs() << "\n" << format_hex(i+1, 4) << ":\t"; else outs() << " "; } outs() << "\n"; } /** * Extract raw instruction stream from .text section in ELF object * * @param RawData Raw C string of ELF object * @return 0 on success */ int Assembler::ExtractELFText(const char* RawData) { const Elf64_Ehdr* ElfHeader; const Elf64_Shdr* SectHeader; const Elf64_Shdr* SectStrTable; const char* SectStrAddr; unsigned NumSects, SectIdx; if (!(ElfHeader = reinterpret_cast(RawData))) { outs() << "ASM Error: elf data is invalid or corrupted\n"; return -1; } if (ElfHeader->e_ident[EI_CLASS] != ELFCLASS64) { outs() << "ASM Error: elf object must be of 64-bit type\n"; return -1; } SectHeader = reinterpret_cast(RawData + ElfHeader->e_shoff); SectStrTable = &SectHeader[ElfHeader->e_shstrndx]; SectStrAddr = static_cast(RawData + SectStrTable->sh_offset); // Loop through sections, break on .text NumSects = ElfHeader->e_shnum; for (SectIdx = 0; SectIdx < NumSects; SectIdx++) { std::string SectName = std::string(SectStrAddr + SectHeader[SectIdx].sh_name); if (SectName == std::string(".text")) { TextSize = SectHeader[SectIdx].sh_size; TextData = new char[TextSize]; memcpy(TextData, RawData + SectHeader[SectIdx].sh_offset, TextSize); break; } } if (SectIdx >= NumSects) { outs() << "ASM Error: couldn't locate .text section\n"; return -1; } return 0; } /** * Assemble shader, fill member vars, and copy to output buffer * * @param AssemblySource Shader source represented as a raw C string * @param OutBuf Raw instruction stream output buffer * @param BufSize Size of OutBuf (defaults to PAGE_SIZE) * @param Gfxv Optional overload to temporarily set target ASIC * @return Value of RunAssemble() (0 on success) */ int Assembler::RunAssembleBuf(const char* const AssemblySource, char* OutBuf, const size_t BufSize) { int ret = RunAssemble(AssemblySource); return ret ? ret : CopyInstrStream(OutBuf, BufSize); } int Assembler::RunAssembleBuf(const char* const AssemblySource, char* OutBuf, const size_t BufSize, const uint32_t Gfxv) { const char* defaultMCPU = GetTargetAsic(); SetTargetAsic(Gfxv); int ret = RunAssemble(AssemblySource); strncpy(MCPU, defaultMCPU, ASM_MCPU_LEN); return ret ? ret : CopyInstrStream(OutBuf, BufSize); } /** * Assemble shader and fill member vars * * @param AssemblySource Shader source represented as a raw C string * @return 0 on success */ int Assembler::RunAssemble(const char* const AssemblySource) { // Ensure target ASIC has been set if (!MCPU) { outs() << "ASM Error: target asic is uninitialized\n"; return -1; } // Delete TextData for any previous runs FlushText(); #if 0 outs() << "ASM Info: running assembly for target: " << MCPU << "\n"; outs() << "ASM Info: source:\n"; outs() << AssemblySource << "\n"; #endif // Initialize MCOptions and target triple const MCTargetOptions MCOptions; Triple TheTriple; const Target* TheTarget = TargetRegistry::lookupTarget(ArchName, TheTriple, Error); if (!TheTarget) { outs() << Error; return -1; } TheTriple.setArchName(ArchName); TheTriple.setVendorName(VendorName); TheTriple.setOSName(OSName); TripleName = TheTriple.getTriple(); TheTriple.setTriple(Triple::normalize(TripleName)); // Create MemoryBuffer for assembly source StringRef AssemblyRef(AssemblySource); std::unique_ptr BufferPtr = MemoryBuffer::getMemBuffer(AssemblyRef, "", false); if (!BufferPtr->getBufferSize()) { outs() << "ASM Error: assembly source is empty\n"; return -1; } // Instantiate SrcMgr and transfer BufferPtr ownership SourceMgr SrcMgr; SrcMgr.AddNewSourceBuffer(std::move(BufferPtr), SMLoc()); // Initialize MC interfaces and base class objects std::unique_ptr MRI( TheTarget->createMCRegInfo(TripleName)); if (!MRI) { outs() << "ASM Error: no register info for target " << MCPU << "\n"; return -1; } #if LLVM_VERSION_MAJOR > 9 std::unique_ptr MAI( TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); #else std::unique_ptr MAI( TheTarget->createMCAsmInfo(*MRI, TripleName)); #endif if (!MAI) { outs() << "ASM Error: no assembly info for target " << MCPU << "\n"; return -1; } std::unique_ptr MCII( TheTarget->createMCInstrInfo()); if (!MCII) { outs() << "ASM Error: no instruction info for target " << MCPU << "\n"; return -1; } std::unique_ptr STI( TheTarget->createMCSubtargetInfo(TripleName, MCPU, std::string())); if (!STI || !STI->isCPUStringValid(MCPU)) { outs() << "ASM Error: no subtarget info for target " << MCPU << "\n"; return -1; } // Set up the MCContext for creating symbols and MCExpr's #if LLVM_VERSION_MAJOR > 12 MCContext Ctx(TheTriple, MAI.get(), MRI.get(), STI.get(), &SrcMgr, &MCOptions); #else MCObjectFileInfo MOFI; MCContext Ctx(MAI.get(), MRI.get(), &MOFI, &SrcMgr, &MCOptions); MOFI.InitMCObjectFileInfo(TheTriple, true, Ctx); #endif // Finalize setup for output object code stream std::string Data; std::unique_ptr DataStream(std::make_unique(Data)); std::unique_ptr BOS(std::make_unique(*DataStream)); raw_pwrite_stream* OS = BOS.get(); #if LLVM_VERSION_MAJOR > 14 MCCodeEmitter* CE = TheTarget->createMCCodeEmitter(*MCII, Ctx); #else MCCodeEmitter* CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx); #endif MCAsmBackend* MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions); std::unique_ptr Streamer(TheTarget->createMCObjectStreamer( TheTriple, Ctx, std::unique_ptr(MAB), MAB->createObjectWriter(*OS), std::unique_ptr(CE), *STI, MCOptions.MCRelaxAll, MCOptions.MCIncrementalLinkerCompatible, /*DWARFMustBeAtTheEnd*/ false)); std::unique_ptr Parser( createMCAsmParser(SrcMgr, Ctx, *Streamer, *MAI)); // Set parser to target parser and run std::unique_ptr TAP( TheTarget->createMCAsmParser(*STI, *Parser, *MCII, MCOptions)); if (!TAP) { outs() << "ASM Error: no assembly parsing support for target " << MCPU << "\n"; return -1; } Parser->setTargetParser(*TAP); if (Parser->Run(true)) { outs() << "ASM Error: assembly parser failed\n"; return -1; } BOS.reset(); DataStream->flush(); int ret = ExtractELFText(Data.data()); if (ret < 0 || !TextData) { outs() << "ASM Error: .text extraction failed\n"; return ret; } #if 0 PrintELFHex(Data); PrintTextHex(); #endif return 0; } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/Assemble.hpp000066400000000000000000000062261446477712600241060ustar00rootroot00000000000000//////////////////////////////////////////////////////////////////////////////// // // The University of Illinois/NCSA // Open Source License (NCSA) // // Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. // // Developed by: // // AMD Research and AMD HSA Software Development // // Advanced Micro Devices, Inc. // // www.amd.com // // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to // deal with the Software without restriction, including without limitation // the rights to use, copy, modify, merge, publish, distribute, sublicense, // and/or sell copies of the Software, and to permit persons to whom the // Software is furnished to do so, subject to the following conditions: // // - Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimers. // - Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimers in // the documentation and/or other materials provided with the distribution. // - Neither the names of Advanced Micro Devices, Inc, // nor the names of its contributors may be used to endorse or promote // products derived from this Software without specific prior written // permission. // // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL // THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR // OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, // ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER // DEALINGS WITH THE SOFTWARE. // //////////////////////////////////////////////////////////////////////////////// #ifndef _ASSEMBLE_H_ #define _ASSEMBLE_H_ #include "OSWrapper.hpp" #define ASM_MCPU_LEN 16 class Assembler { private: const char* ArchName = "amdgcn"; const char* VendorName = "amd"; const char* OSName = "amdhsa"; char MCPU[ASM_MCPU_LEN]; std::string TripleName; std::string Error; char* TextData; size_t TextSize; void SetTargetAsic(const uint32_t Gfxv); void LLVMInit(); void FlushText(); void PrintELFHex(const std::string Data); int ExtractELFText(const char* RawData); public: Assembler(const uint32_t Gfxv); ~Assembler(); void PrintTextHex(); const char* GetTargetAsic(); const char* GetInstrStream(); const size_t GetInstrStreamSize(); int CopyInstrStream(char* OutBuf, const size_t BufSize = PAGE_SIZE); int RunAssemble(const char* const AssemblySource); int RunAssembleBuf(const char* const AssemblySource, char* OutBuf, const size_t BufSize = PAGE_SIZE); int RunAssembleBuf(const char* const AssemblySource, char* OutBuf, const size_t BufSize, const uint32_t Gfxv); }; #endif // _ASSEMBLE_H_ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/BasePacket.cpp000066400000000000000000000040331446477712600243420ustar00rootroot00000000000000/* * Copyright (C) 2017-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "BasePacket.hpp" #include "KFDTestUtil.hpp" #include "KFDBaseComponentTest.hpp" BasePacket::BasePacket(void): m_packetAllocation(NULL) { m_FamilyId = g_baseTest->GetFamilyIdFromDefaultNode(); } BasePacket::~BasePacket(void) { if (m_packetAllocation) free(m_packetAllocation); } void BasePacket::Dump() const { unsigned int size = SizeInDWords(); const HSAuint32 *packet = (const HSAuint32 *)GetPacket(); std::ostream &log = LOG(); unsigned int i; log << "Packet dump:" << std::hex; for (i = 0; i < size; i++) log << " " << std::setw(8) << std::setfill('0') << packet[i]; log << std::endl; } void *BasePacket::AllocPacket(void) { unsigned int size = SizeInBytes(); EXPECT_NE(0, size); if (!size) return NULL; m_packetAllocation = calloc(1, size); EXPECT_NOTNULL(m_packetAllocation); return m_packetAllocation; } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/BasePacket.hpp000066400000000000000000000037671446477712600243640ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_BASE_PACKET__H__ #define __KFD_BASE_PACKET__H__ /** * All packets profiles must be defined here * Every type defined here has sub-types */ enum PACKETTYPE { PACKETTYPE_PM4, PACKETTYPE_SDMA, PACKETTYPE_AQL }; // @class BasePacket class BasePacket { public: BasePacket(void); virtual ~BasePacket(void); // @returns Packet type virtual PACKETTYPE PacketType() const = 0; // @returns Pointer to the packet virtual const void *GetPacket() const = 0; // @returns Packet size in bytes virtual unsigned int SizeInBytes() const = 0; // @returns Packet size in dwordS unsigned int SizeInDWords() const { return SizeInBytes()/sizeof(unsigned int); } void Dump() const; protected: unsigned int m_FamilyId; void *m_packetAllocation; void *AllocPacket(void); }; #endif // __KFD_BASE_PACKET__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/BaseQueue.cpp000066400000000000000000000154721446477712600242300ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "BaseQueue.hpp" #include "SDMAQueue.hpp" #include "PM4Queue.hpp" #include "AqlQueue.hpp" #include "hsakmt.h" #include "KFDBaseComponentTest.hpp" BaseQueue::BaseQueue() :m_QueueBuf(NULL), m_SkipWaitConsumption(true) { } BaseQueue::~BaseQueue(void) { Destroy(); } HSAKMT_STATUS BaseQueue::Create(unsigned int NodeId, unsigned int size, HSAuint64 *pointers) { HSAKMT_STATUS status; HSA_QUEUE_TYPE type = GetQueueType(); if (m_QueueBuf != NULL) { // Queue already exists, one queue per object Destroy(); } memset(&m_Resources, 0, sizeof(m_Resources)); m_QueueBuf = new HsaMemoryBuffer(size, NodeId, true/*zero*/, false/*local*/, true/*exec*/, /*isScratch */ false, /* isReadOnly */false, /* isUncached */true); if (type == HSA_QUEUE_COMPUTE_AQL) { m_Resources.Queue_read_ptr_aql = &pointers[0]; m_Resources.Queue_write_ptr_aql = &pointers[1]; } status = hsaKmtCreateQueue(NodeId, type, DEFAULT_QUEUE_PERCENTAGE, DEFAULT_PRIORITY, m_QueueBuf->As(), m_QueueBuf->Size(), NULL, &m_Resources); if (status != HSAKMT_STATUS_SUCCESS) { return status; } if (m_Resources.Queue_read_ptr == NULL) { WARN() << "CreateQueue: read pointer value should be 0" << std::endl; status = HSAKMT_STATUS_ERROR; } if (m_Resources.Queue_write_ptr == NULL) { WARN() << "CreateQueue: write pointer value should be 0" << std::endl; status = HSAKMT_STATUS_ERROR; } // Needs to match the queue write ptr m_pendingWptr = 0; m_pendingWptr64 = 0; m_Node = NodeId; m_FamilyId = g_baseTest->GetFamilyIdFromNodeId(NodeId); return status; } HSAKMT_STATUS BaseQueue::Update(unsigned int percent, HSA_QUEUE_PRIORITY priority, bool nullifyBuffer) { void* pNewBuffer = (nullifyBuffer ? NULL : m_QueueBuf->As()); HSAuint64 newSize = (nullifyBuffer ? 0 : m_QueueBuf->Size()); return hsaKmtUpdateQueue(m_Resources.QueueId, percent, priority, pNewBuffer, newSize, NULL); } HSAKMT_STATUS BaseQueue::SetCUMask(unsigned int *mask, unsigned int mask_count) { return hsaKmtSetQueueCUMask(m_Resources.QueueId, mask_count, mask); } HSAKMT_STATUS BaseQueue::Destroy() { HSAKMT_STATUS status = HSAKMT_STATUS_SUCCESS; if (m_QueueBuf != NULL) { status = hsaKmtDestroyQueue(m_Resources.QueueId); if (status == HSAKMT_STATUS_SUCCESS) { delete m_QueueBuf; m_QueueBuf = NULL; } } return status; } void BaseQueue::PlaceAndSubmitPacket(const BasePacket &packet) { PlacePacket(packet); SubmitPacket(); } void BaseQueue::Wait4PacketConsumption(HsaEvent *event, unsigned int timeOut) { ASSERT_TRUE(!event) << "Not supported!" << std::endl; ASSERT_TRUE(WaitOnValue(m_Resources.Queue_read_ptr, RptrWhenConsumed(), timeOut)); } bool BaseQueue::AllPacketsSubmitted() { return Wptr() == Rptr(); } void BaseQueue::PlacePacket(const BasePacket &packet) { ASSERT_EQ(packet.PacketType(), PacketTypeSupported()) << "Cannot add a packet since packet type doesn't match queue"; unsigned int readPtr = Rptr(); unsigned int writePtr = m_pendingWptr; HSAuint64 writePtr64 = m_pendingWptr64; unsigned int packetSizeInDwords = packet.SizeInDWords(); unsigned int dwordsRequired = packetSizeInDwords; unsigned int queueSizeInDWord = m_QueueBuf->Size() / sizeof(uint32_t); if (writePtr + packetSizeInDwords > queueSizeInDWord) { // Wraparound expected. We need enough room to also place NOPs to avoid crossing the buffer end. dwordsRequired += queueSizeInDWord - writePtr; } unsigned int dwordsAvailable = (readPtr - 1 - writePtr + queueSizeInDWord) % queueSizeInDWord; ASSERT_GE(dwordsAvailable, dwordsRequired) << "Cannot add a packet, buffer overrun"; ASSERT_GE(queueSizeInDWord, packetSizeInDwords) << "Cannot add a packet, packet size too large"; if (writePtr + packetSizeInDwords >= queueSizeInDWord) { // Wraparound while (writePtr + packetSizeInDwords > queueSizeInDWord) { m_QueueBuf->As()[writePtr] = CMD_NOP; writePtr = (writePtr + 1) % queueSizeInDWord; writePtr64++; } // Not updating Wptr since we might want to place the packet without submission m_pendingWptr = (writePtr % queueSizeInDWord); m_pendingWptr64 = writePtr64; } memcpy(m_pendingWptr + m_QueueBuf->As(), packet.GetPacket(), packetSizeInDwords * 4); m_pendingWptr = (m_pendingWptr + packetSizeInDwords) % queueSizeInDWord; m_pendingWptr64 += packetSizeInDwords; } BaseQueue* QueueArray::GetQueue(unsigned int Node) { // If a queue exists for that node then return, else create one for (unsigned int i = 0; i < m_QueueList.size(); i++) { if (Node == m_QueueList.at(i)->GetNodeId()) return m_QueueList.at(i); } BaseQueue *pQueue = NULL; switch (m_QueueType) { case HSA_QUEUE_COMPUTE: pQueue = new PM4Queue(); break; case HSA_QUEUE_SDMA: pQueue = new SDMAQueue(); break; case HSA_QUEUE_COMPUTE_AQL: pQueue = new AqlQueue(); break; default: return NULL; } if (pQueue) { pQueue->Create(Node); m_QueueList.push_back(pQueue); } return pQueue; } void QueueArray::Destroy() { for (unsigned int i = 0; i < m_QueueList.size(); i++) delete m_QueueList.at(i); m_QueueList.clear(); } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/BaseQueue.hpp000066400000000000000000000122501446477712600242240ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_BASE_QUEUE__H__ #define __KFD_BASE_QUEUE__H__ #include #include "KFDTestUtil.hpp" #include "BasePacket.hpp" // @class BasePacket class BaseQueue { public: static const unsigned int DEFAULT_QUEUE_SIZE = PAGE_SIZE; static const HSA_QUEUE_PRIORITY DEFAULT_PRIORITY = HSA_QUEUE_PRIORITY_NORMAL; static const unsigned int DEFAULT_QUEUE_PERCENTAGE = 100; static const unsigned int ZERO_QUEUE_PERCENTAGE = 0; static const unsigned int FLUSH_GPU_CACHES_TO = 1000; BaseQueue(void); virtual ~BaseQueue(void); /** Create the queue. * @see hsaKmtCreateQueue * @param pointers is used only for creating AQL queues. Otherwise it is omitted. */ virtual HSAKMT_STATUS Create(unsigned int NodeId, unsigned int size = DEFAULT_QUEUE_SIZE, HSAuint64 *pointers = NULL); /** Update the queue. * @see hsaKmtUpdateQueue * @param percent New queue percentage * @param priority New queue priority * @param nullifyBuffer * If 'true', set the new buffer address to NULL and the size to 0. Otherwise * don't change the queue buffer address/size. */ virtual HSAKMT_STATUS Update(unsigned int percent, HSA_QUEUE_PRIORITY priority, bool nullifyBuffer); virtual HSAKMT_STATUS SetCUMask(unsigned int *mask, unsigned int mask_count); /** Destroy the queue. * @see hsaKmtDestroyQueue */ virtual HSAKMT_STATUS Destroy(); /** Wait for all the packets submitted to the queue to be consumed. (i.e. wait until RPTR=WPTR). * Note that all packets being consumed is not the same as all packets being processed. */ virtual void Wait4PacketConsumption(HsaEvent *event = NULL, unsigned int timeOut = g_TestTimeOut); /** @brief Place packet and submit it in one function */ virtual void PlaceAndSubmitPacket(const BasePacket &packet); /** @brief Copy packet to queue and update write pointer */ virtual void PlacePacket(const BasePacket &packet); /** @brief Update queue write pointer and set the queue doorbell to the queue write pointer */ virtual void SubmitPacket() = 0; /** @brief Check if all packets in queue are already processed * Compare queue read and write pointers */ bool AllPacketsSubmitted(); void SetSkipWaitConsump(int val) { m_SkipWaitConsumption = val; } int GetSkipWaitConsump() { return m_SkipWaitConsumption; } int Size() { return m_QueueBuf->Size(); } HsaQueueResource *GetResource() { return &m_Resources; } unsigned int GetPendingWptr() { return m_pendingWptr; } HSAuint64 GetPendingWptr64() { return m_pendingWptr64; } virtual _HSA_QUEUE_TYPE GetQueueType() = 0; unsigned int GetNodeId() { return m_Node; } unsigned int GetFamilyId() { return m_FamilyId; } protected: static const unsigned int CMD_NOP_TYPE_2 = 0x80000000; static const unsigned int CMD_NOP_TYPE_3 = 0xFFFF1002; unsigned int CMD_NOP; unsigned int m_pendingWptr; HSAuint64 m_pendingWptr64; HsaQueueResource m_Resources; HsaMemoryBuffer *m_QueueBuf; unsigned int m_Node; unsigned int m_FamilyId; // @return Write pointer modulo queue size in dwords virtual unsigned int Wptr() = 0; // @return Read pointer modulo queue size in dwords virtual unsigned int Rptr() = 0; // @return Expected m_Resources.Queue_read_ptr when all packets consumed virtual unsigned int RptrWhenConsumed() = 0; virtual PACKETTYPE PacketTypeSupported() = 0; private: // Some tests(such as exception) may not need wait pm4 packet consumption on CZ. int m_SkipWaitConsumption; }; // @class QueueArray // Managed QueueArray for different GPU Nodes class QueueArray { // List of Queues. One for each GPU std::vector m_QueueList; _HSA_QUEUE_TYPE m_QueueType; public: QueueArray(_HSA_QUEUE_TYPE type): m_QueueType(type) {} ~QueueArray() { Destroy(); } BaseQueue* GetQueue(unsigned int Node); void Destroy(); }; #endif // __KFD_BASE_QUEUE__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/Dispatch.cpp000066400000000000000000000271761446477712600241140ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "Dispatch.hpp" #include "PM4Packet.hpp" #include "asic_reg/gfx_7_2_d.h" #include "asic_reg/gfx_7_2_sh_mask.h" #include "KFDBaseComponentTest.hpp" #define mmCOMPUTE_PGM_RSRC3 0x2e2d Dispatch::Dispatch(const HsaMemoryBuffer& isaBuf, const bool eventAutoReset) :m_IsaBuf(isaBuf), m_IndirectBuf(PACKETTYPE_PM4, PAGE_SIZE / sizeof(unsigned int), isaBuf.Node()), m_DimX(1), m_DimY(1), m_DimZ(1), m_pArg1(NULL), m_pArg2(NULL), m_pEop(NULL), m_ScratchEn(false), m_ComputeTmpringSize(0), m_scratch_base(0ll), m_SpiPriority(0) { HsaEventDescriptor eventDesc; eventDesc.EventType = HSA_EVENTTYPE_SIGNAL; eventDesc.NodeId = isaBuf.Node(); eventDesc.SyncVar.SyncVar.UserData = NULL; eventDesc.SyncVar.SyncVarSize = 0; hsaKmtCreateEvent(&eventDesc, !eventAutoReset, false, &m_pEop); m_FamilyId = g_baseTest->GetFamilyIdFromNodeId(isaBuf.Node()); m_NeedCwsrWA = g_baseTest->NeedCwsrWA(isaBuf.Node()); } Dispatch::~Dispatch() { if (m_pEop != NULL) hsaKmtDestroyEvent(m_pEop); } void Dispatch::SetArgs(void* pArg1, void* pArg2) { m_pArg1 = pArg1; m_pArg2 = pArg2; } void Dispatch::SetDim(unsigned int x, unsigned int y, unsigned int z) { m_DimX = x; m_DimY = y; m_DimZ = z; } void Dispatch::SetScratch(int numWaves, int waveSize, HSAuint64 scratch_base) { m_ComputeTmpringSize = ((waveSize << 12) | (numWaves)); m_ScratchEn = true; m_scratch_base = scratch_base; } void Dispatch::SetSpiPriority(unsigned int priority) { m_SpiPriority = priority; } void Dispatch::Submit(BaseQueue& queue) { ASSERT_NE(m_pEop, (void*)0); EXPECT_EQ(m_FamilyId, queue.GetFamilyId()); BuildIb(); queue.PlaceAndSubmitPacket(PM4IndirectBufPacket(&m_IndirectBuf)); // Write data to SyncVar for synchronization purpose if (m_pEop->EventData.EventData.SyncVar.SyncVar.UserData != NULL) { queue.PlaceAndSubmitPacket(PM4WriteDataPacket((unsigned int*)m_pEop-> EventData.EventData.SyncVar.SyncVar.UserData, m_pEop->EventId)); } queue.PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, false, m_pEop->EventData.HWData2, m_pEop->EventId)); if (!queue.GetSkipWaitConsump()) queue.Wait4PacketConsumption(); } void Dispatch::Sync(unsigned int timeout) { ASSERT_SUCCESS(hsaKmtWaitOnEvent(m_pEop, timeout)); } // Returning with status in order to allow actions to be performed before process termination int Dispatch::SyncWithStatus(unsigned int timeout) { int stat; return ((stat = hsaKmtWaitOnEvent(m_pEop, timeout)) != HSAKMT_STATUS_SUCCESS); } void Dispatch::BuildIb() { HSAuint64 shiftedIsaAddr = m_IsaBuf.As() >> 8; unsigned int arg0, arg1, arg2, arg3; SplitU64(reinterpret_cast(m_pArg1), arg0, arg1); SplitU64(reinterpret_cast(m_pArg2), arg2, arg3); // Starts at COMPUTE_START_X const unsigned int COMPUTE_DISPATCH_DIMS_VALUES[] = { 0, // START_X 0, // START_Y 0, // START_Z 1, // NUM_THREADS_X - this is actually the number of threads in a thread group 1, // NUM_THREADS_Y 1, // NUM_THREADS_Z 0, // COMPUTE_PIPELINESTAT_ENABLE 0, // COMPUTE_PERFCOUNT_ENABLE }; unsigned int pgmRsrc2 = 0; pgmRsrc2 |= (m_ScratchEn << COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT) & COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK; pgmRsrc2 |= ((m_scratch_base ? 6 : 4) << COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT) & COMPUTE_PGM_RSRC2__USER_SGPR_MASK; pgmRsrc2 |= (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT) & COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK; pgmRsrc2 |= (1 << COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT) & COMPUTE_PGM_RSRC2__TGID_X_EN_MASK; pgmRsrc2 |= (1 << COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT) & COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK; pgmRsrc2 |= (0 << COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT) & COMPUTE_PGM_RSRC2__EXCP_EN_MASK; pgmRsrc2 |= (1 << COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT) & COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK; /* * For some special asics in the list of DEGFX11_12113 * COMPUTE_PGM_RSRC needs priv=1 to prevent hardware traps */ const bool priv = m_NeedCwsrWA; const unsigned int COMPUTE_PGM_RSRC[] = { // PGM_RSRC1 = { VGPRS: 16 SGPRS: 16 PRIORITY: m_SpiPriority FLOAT_MODE: c0 // PRIV: 0 (1 for GFX11) DX10_CLAMP: 0 DEBUG_MODE: 0 IEEE_MODE: 0 BULKY: 0 CDBG_USER: 0 } 0x000c0084 | ((m_SpiPriority & 3) << 10) | (priv << 20), pgmRsrc2 }; // Starts at COMPUTE_PGM_LO const unsigned int COMPUTE_PGM_VALUES_GFX8[] = { static_cast(shiftedIsaAddr), // PGM_LO static_cast(shiftedIsaAddr >> 32) // PGM_HI | (is_dgpu() ? 0 : (1<<8)) // including PGM_ATC=? }; // Starts at COMPUTE_PGM_LO const unsigned int COMPUTE_PGM_VALUES_GFX9[] = { static_cast(shiftedIsaAddr), // PGM_LO static_cast(shiftedIsaAddr >> 32) // PGM_HI | (is_dgpu() ? 0 : (1<<8)), // including PGM_ATC=? 0, 0, static_cast(m_scratch_base >> 8), // compute_dispatch_scratch_base static_cast(m_scratch_base >> 40) }; // Starts at COMPUTE_RESOURCE_LIMITS const unsigned int COMPUTE_RESOURCE_LIMITS[] = { 0, // COMPUTE_RESOURCE_LIMITS }; // Starts at COMPUTE_TMPRING_SIZE const unsigned int COMPUTE_TMPRING_SIZE[] = { m_ComputeTmpringSize, // COMPUTE_TMPRING_SIZE }; // Starts at COMPUTE_RESTART_X const unsigned int COMPUTE_RESTART_VALUES[] = { 0, // COMPUTE_RESTART_X 0, // COMPUTE_RESTART_Y 0, // COMPUTE_RESTART_Z 0 // COMPUTE_THREAD_TRACE_ENABLE }; // Starts at COMPUTE_USER_DATA_0 const unsigned int COMPUTE_USER_DATA_VALUES[] = { // Reg name - use in KFDtest - use in ABI arg0, // COMPUTE_USER_DATA_0 - arg0 - resource descriptor for the scratch buffer - 1st dword arg1, // COMPUTE_USER_DATA_1 - arg1 - resource descriptor for the scratch buffer - 2nd dword arg2, // COMPUTE_USER_DATA_2 - arg2 - resource descriptor for the scratch buffer - 3rd dword arg3, // COMPUTE_USER_DATA_3 - arg3 - resource descriptor for the scratch buffer - 4th dword static_cast(m_scratch_base), // COMPUTE_USER_DATA_4 - flat_scratch_lo static_cast(m_scratch_base >> 32), // COMPUTE_USER_DATA_4 - flat_scratch_hi 0, // COMPUTE_USER_DATA_6 - - AQL queue address, low part 0, // COMPUTE_USER_DATA_7 - - AQL queue address, high part 0, // COMPUTE_USER_DATA_8 - - kernel arguments block, low part 0, // COMPUTE_USER_DATA_9 - - kernel arguments block, high part 0, // COMPUTE_USER_DATA_10 - - unused 0, // COMPUTE_USER_DATA_11 - - unused 0, // COMPUTE_USER_DATA_12 - - unused 0, // COMPUTE_USER_DATA_13 - - unused 0, // COMPUTE_USER_DATA_14 - - unused 0, // COMPUTE_USER_DATA_15 - - unused }; const unsigned int DISPATCH_INIT_VALUE = 0x00000021 | (is_dgpu() ? 0 : 0x1000) | ((m_FamilyId >= FAMILY_NV) ? 0x8000 : 0); // {COMPUTE_SHADER_EN=1, PARTIAL_TG_EN=0, FORCE_START_AT_000=0, ORDERED_APPEND_ENBL=0, // ORDERED_APPEND_MODE=0, USE_THREAD_DIMENSIONS=1, ORDER_MODE=0, DISPATCH_CACHE_CNTL=0, // SCALAR_L1_INV_VOL=0, VECTOR_L1_INV_VOL=0, DATA_ATC=?, RESTORE=0} // Set CS_W32_EN for wave32 workloads for gfx10 since all the shaders used in KFDTest is 32 bit . m_IndirectBuf.AddPacket(PM4AcquireMemoryPacket(m_FamilyId)); m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_START_X, COMPUTE_DISPATCH_DIMS_VALUES, ARRAY_SIZE(COMPUTE_DISPATCH_DIMS_VALUES))); m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_PGM_LO, (m_FamilyId >= FAMILY_AI) ? COMPUTE_PGM_VALUES_GFX9 : COMPUTE_PGM_VALUES_GFX8, (m_FamilyId >= FAMILY_AI) ? ARRAY_SIZE(COMPUTE_PGM_VALUES_GFX9) : ARRAY_SIZE(COMPUTE_PGM_VALUES_GFX8))); m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_PGM_RSRC1, COMPUTE_PGM_RSRC, ARRAY_SIZE(COMPUTE_PGM_RSRC))); if (m_FamilyId == FAMILY_AL || m_FamilyId == FAMILY_AV) { const unsigned int COMPUTE_PGM_RSRC3[] = {9}; m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_PGM_RSRC3, COMPUTE_PGM_RSRC3, ARRAY_SIZE(COMPUTE_PGM_RSRC3))); } m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_RESOURCE_LIMITS, COMPUTE_RESOURCE_LIMITS, ARRAY_SIZE(COMPUTE_RESOURCE_LIMITS))); m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_TMPRING_SIZE, COMPUTE_TMPRING_SIZE, ARRAY_SIZE(COMPUTE_TMPRING_SIZE))); m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_RESTART_X, COMPUTE_RESTART_VALUES, ARRAY_SIZE(COMPUTE_RESTART_VALUES))); m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_USER_DATA_0, COMPUTE_USER_DATA_VALUES, ARRAY_SIZE(COMPUTE_USER_DATA_VALUES))); m_IndirectBuf.AddPacket(PM4DispatchDirectPacket(m_DimX, m_DimY, m_DimZ, DISPATCH_INIT_VALUE)); // EVENT_WRITE.partial_flush causes problems with preemptions in // GWS testing. Since this is specific to this PM4 command and // doesn't affect AQL, it's easier to fix KFDTest than the // firmware. // // Replace PartialFlush with an ReleaseMem (with no interrupt) + WaitRegMem // // Original: m_IndirectBuf.AddPacket(PM4PartialFlushPacket()); uint32_t *nop = m_IndirectBuf.AddPacket(PM4NopPacket(2)); // NOP packet with one dword payload for the release-mem fence m_IndirectBuf.AddPacket(PM4ReleaseMemoryPacket(m_FamilyId, true, (uint64_t)&nop[1], 0xdeadbeef)); m_IndirectBuf.AddPacket(PM4WaitRegMemPacket(true, (uint64_t)&nop[1], 0xdeadbeef, 4)); } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/Dispatch.hpp000066400000000000000000000044421446477712600241100ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_DISPATCH__H__ #define __KFD_DISPATCH__H__ #include "KFDTestUtil.hpp" #include "IndirectBuffer.hpp" #include "BaseQueue.hpp" class Dispatch { public: Dispatch(const HsaMemoryBuffer& isaBuf, const bool eventAutoReset = false); ~Dispatch(); void SetArgs(void* pArg1, void* pArg2); void SetDim(unsigned int x, unsigned int y, unsigned int z); void Submit(BaseQueue& queue); void Sync(unsigned int timeout = HSA_EVENTTIMEOUT_INFINITE); int SyncWithStatus(unsigned int timeout); void SetScratch(int numWaves, int waveSize, HSAuint64 scratch_base); void SetSpiPriority(unsigned int priority); HsaEvent *GetHsaEvent() { return m_pEop; } private: void BuildIb(); private: const HsaMemoryBuffer& m_IsaBuf; IndirectBuffer m_IndirectBuf; unsigned int m_DimX; unsigned int m_DimY; unsigned int m_DimZ; void* m_pArg1; void* m_pArg2; HsaEvent* m_pEop; bool m_ScratchEn; unsigned int m_ComputeTmpringSize; HSAuint64 m_scratch_base; unsigned int m_SpiPriority; unsigned int m_FamilyId; bool m_NeedCwsrWA; }; #endif // __KFD_DISPATCH__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/GoogleTestExtension.cpp000066400000000000000000000052011446477712600263070ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "GoogleTestExtension.hpp" #include "OSWrapper.hpp" bool Ok2Run(unsigned int testProfile) { bool testMatchProfile = true; if ((testProfile & g_TestRunProfile) == 0) { WARN() << "Test is skipped beacuse profile does not match current run mode" << std::endl; testMatchProfile = false; } return testMatchProfile; } // This predication is used when specific HW capabilities must exist for the test to succeed. bool TestReqEnvCaps(unsigned int envCaps) { bool testMatchEnv = true; if ((envCaps & g_TestENVCaps) != envCaps) { WARN() << "Test is skipped due to HW capability issues" << std::endl; testMatchEnv = false; } return testMatchEnv; } // This predication is used when specific HW capabilities must be absent for the test to succeed. // e.g Testing capabilities not supported by HW scheduling bool TestReqNoEnvCaps(unsigned int envCaps) { bool testMatchEnv = true; if ((envCaps & g_TestENVCaps) != 0) { WARN() << "Test is skipped due to HW capability issues" << std::endl; testMatchEnv = false; } return testMatchEnv; } std::ostream& operator<< (KFDLog log, LOGTYPE level) { const char *heading; if (level == LOGTYPE_WARNING) { SetConsoleTextColor(TEXTCOLOR_YELLOW); heading = "[----------] "; } else { SetConsoleTextColor(TEXTCOLOR_GREEN); heading = "[ ] "; } std::clog << heading; SetConsoleTextColor(TEXTCOLOR_WHITE); return std::clog; } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/GoogleTestExtension.hpp000066400000000000000000000070341446477712600263220ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __GOOGLETEST_EXTENSION__H__ #define __GOOGLETEST_EXTENSION__H__ #include #include "hsakmt.h" #include "KFDTestFlags.hpp" enum LOGTYPE { LOGTYPE_INFO, // msg header in green LOGTYPE_WARNING // msg header in yellow }; class KFDLog{}; std::ostream& operator << (KFDLog log, LOGTYPE level); // @brief Log additional details, to be displayed in the same format as other google test outputs // Currently not supported by gtest // Should be used like cout: LOG() << "message" << value << std::endl; #define LOG() KFDLog() << LOGTYPE_INFO #define WARN() KFDLog() << LOGTYPE_WARNING class KFDRecord: public testing::Test { public: KFDRecord(const char *val): m_val(val) {} KFDRecord(std::string &val): m_val(val) {} KFDRecord(HSAint64 val): m_val(std::to_string(val)) {} KFDRecord(HSAuint64 val): m_val(std::to_string(val)) {} KFDRecord(double val): m_val(std::to_string(val)) {} ~KFDRecord() { RecordProperty(m_key.str().c_str(), m_val.c_str()); } std::stringstream &get_key_stream() { return m_key; } virtual void TestBody() {}; private: std::string m_val; std::stringstream m_key; }; #define RECORD(val) (KFDRecord(val).get_key_stream()) // All tests MUST be in a try catch since the gtest flag to throw an exception on any fatal failure is enabled #define TEST_START(testProfile) if (Ok2Run(testProfile)) try { #define TEST_END } catch (...) {} // Used to wrap setup and teardown functions, anything that is built-in gtest and is not a test #define ROUTINE_START try { #define ROUTINE_END }catch(...) {} #define TEST_REQUIRE_ENV_CAPABILITIES(envCaps) if (!TestReqEnvCaps(envCaps)) return; #define TEST_REQUIRE_NO_ENV_CAPABILITIES(envCaps) if (!TestReqNoEnvCaps(envCaps)) return; #define ASSERT_SUCCESS(_val) ASSERT_EQ(HSAKMT_STATUS_SUCCESS, (_val)) #define EXPECT_SUCCESS(_val) EXPECT_EQ(HSAKMT_STATUS_SUCCESS, (_val)) #define ASSERT_NOTNULL(_val) ASSERT_NE((void *)NULL, _val) #define EXPECT_NOTNULL(_val) EXPECT_NE((void *)NULL, _val) // @brief Determines if it is ok to run a test given input flags bool Ok2Run(unsigned int testProfile); // @brief Checks if all HW capabilities needed for a test to run exist bool TestReqEnvCaps(unsigned int hwCaps); // @brief Checks if all HW capabilities that prevents a test from running are absent bool TestReqNoEnvCaps(unsigned int hwCaps); #endif ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/IndirectBuffer.cpp000066400000000000000000000045141446477712600252370ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "IndirectBuffer.hpp" #include "GoogleTestExtension.hpp" #include "pm4_pkt_struct_common.h" #include "PM4Packet.hpp" IndirectBuffer::IndirectBuffer(PACKETTYPE type, unsigned int sizeInDWords, unsigned int NodeId) :m_NumOfPackets(0), m_MaxSize(sizeInDWords), m_ActualSize(0), m_PacketTypeAllowed(type) { m_IndirectBuf = new HsaMemoryBuffer(sizeInDWords*sizeof(unsigned int), NodeId, true/*zero*/, false/*local*/, true/*exec*/, false/*isScratch*/, false/*isReadOnly*/, true/*isUncached*/); } IndirectBuffer::~IndirectBuffer(void) { delete m_IndirectBuf; } uint32_t *IndirectBuffer::AddPacket(const BasePacket &packet) { EXPECT_EQ(packet.PacketType(), m_PacketTypeAllowed) << "Cannot add a packet since packet type doesn't match queue"; unsigned int writePtr = m_ActualSize; EXPECT_GE(m_MaxSize, packet.SizeInDWords() + writePtr) << "Cannot add a packet, not enough room"; memcpy(m_IndirectBuf->As() + writePtr , packet.GetPacket(), packet.SizeInBytes()); m_ActualSize += packet.SizeInDWords(); m_NumOfPackets++; return m_IndirectBuf->As() + writePtr; } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/IndirectBuffer.hpp000066400000000000000000000047061446477712600252470ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __INDIRECT_BUFFER__H__ #define __INDIRECT_BUFFER__H__ #include "BasePacket.hpp" #include "KFDTestUtil.hpp" /** @class IndirectBuffer * When working with an indirect buffer, create IndirectBuffer, fill it with all the packets you want, * create an indirect packet to point to it, and submit the packet to queue */ class IndirectBuffer { public: // @param[size] Queue max size in DWords // @param[type] Packet type allowed in queue IndirectBuffer(PACKETTYPE type, unsigned int sizeInDWords, unsigned int NodeId); ~IndirectBuffer(void); // @brief Add packet to queue, all validations are done with gtest ASSERT and EXPECT uint32_t *AddPacket(const BasePacket &packet); // @returns Actual size of the indirect queue in DWords, equivalent to write pointer unsigned int SizeInDWord() { return m_ActualSize; } // @returns Indirect queue address unsigned int *Addr() { return m_IndirectBuf->As(); } protected: // Number of packets in the queue unsigned int m_NumOfPackets; // Max size of queue in DWords unsigned int m_MaxSize; // Current size of queue in DWords unsigned int m_ActualSize; HsaMemoryBuffer *m_IndirectBuf; // What packets are supported in this queue PACKETTYPE m_PacketTypeAllowed; }; #endif // __INDIRECT_BUFFER__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDASMTest.cpp000066400000000000000000000040411446477712600241440ustar00rootroot00000000000000/* * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "GoogleTestExtension.hpp" #include "KFDASMTest.hpp" #include "ShaderStore.hpp" #include "Assemble.hpp" void KFDASMTest::SetUp() {} void KFDASMTest::TearDown() {} static const std::vector TargetList = { 0x080001, 0x080002, 0x080003, 0x080005, 0x080100, 0x090000, 0x090002, 0x090004, 0x090006, 0x090008, 0x090009, 0x09000a, 0x09000c, 0x090400, 0x0a0100, 0x0a0101, 0x0a0102, 0x0a0103, 0x0a0300, 0x0a0301, 0x0a0302, 0x0a0303, 0x0a0304, 0x0a0305, 0x0a0306, }; TEST_F(KFDASMTest, AssembleShaders) { TEST_START(TESTPROFILE_RUNALL) for (auto &t : TargetList) { Assembler asmblr(t); LOG() << "Running ASM test for target " << asmblr.GetTargetAsic() << std::endl; for (auto &s : ShaderList) { EXPECT_SUCCESS(asmblr.RunAssemble(s)); } } TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDASMTest.hpp000066400000000000000000000026341446477712600241570ustar00rootroot00000000000000/* * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_ASM_TEST__H__ #define __KFD_ASM_TEST__H__ #include class KFDASMTest : public testing::Test { public: KFDASMTest() {} ~KFDASMTest() {} protected: virtual void SetUp(); virtual void TearDown(); }; #endif // __KFD_ASM_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDBaseComponentTest.cpp000066400000000000000000000205171446477712600262670ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include #include "KFDBaseComponentTest.hpp" #include "KFDTestUtil.hpp" void KFDBaseComponentTest::SetUpTestCase() { } void KFDBaseComponentTest::TearDownTestCase() { } void KFDBaseComponentTest::SetUp() { ROUTINE_START ASSERT_SUCCESS(hsaKmtOpenKFD()); EXPECT_SUCCESS(hsaKmtGetVersion(&m_VersionInfo)); memset( &m_SystemProperties, 0, sizeof(m_SystemProperties) ); memset(m_RenderNodes, 0, sizeof(m_RenderNodes)); /** In order to be correctly testing the KFD interfaces and ensure * that the KFD acknowledges relevant node parameters * for the rest of the tests and used for more specific topology tests, * call to GetSystemProperties for a system snapshot of the topology here */ ASSERT_SUCCESS(hsaKmtAcquireSystemProperties(&m_SystemProperties)); ASSERT_GT(m_SystemProperties.NumNodes, HSAuint32(0)) << "HSA has no nodes."; m_NodeInfo.Init(m_SystemProperties.NumNodes); // setting memory flags with default values , can be modified according to needs m_MemoryFlags.ui32.NonPaged = 0; // Paged m_MemoryFlags.ui32.CachePolicy = HSA_CACHING_NONCACHED; // Non cached m_MemoryFlags.ui32.ReadOnly = 0; // Read/Write m_MemoryFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; // 4KB page m_MemoryFlags.ui32.HostAccess = 1; // Host accessible m_MemoryFlags.ui32.NoSubstitute = 0; // Fall back to node 0 if needed m_MemoryFlags.ui32.GDSMemory = 0; m_MemoryFlags.ui32.Scratch = 0; const HsaNodeProperties *nodeProperties = m_NodeInfo.HsaDefaultGPUNodeProperties(); ASSERT_NOTNULL(nodeProperties) << "failed to get HSA default GPU Node properties"; m_FamilyId = FamilyIdFromNode(nodeProperties); GetHwQueueInfo(nodeProperties, &m_numCpQueues, &m_numSdmaEngines, &m_numSdmaXgmiEngines, &m_numSdmaQueuesPerEngine); g_baseTest = this; m_pAsm = new Assembler(GetGfxVersion(nodeProperties)); const testing::TestInfo* curr_test_info = ::testing::UnitTest::GetInstance()->current_test_info(); openlog("KFDTEST", LOG_CONS , LOG_USER); syslog(LOG_INFO, "[Node#%03d] STARTED ========== %s.%s ==========", m_NodeInfo.HsaDefaultGPUNode(), curr_test_info->test_case_name(), curr_test_info->name()); ROUTINE_END } void KFDBaseComponentTest::TearDown() { ROUTINE_START for (int i = 0; i < MAX_RENDER_NODES; i++) { if (m_RenderNodes[i].fd <= 0) continue; amdgpu_device_deinitialize(m_RenderNodes[i].device_handle); drmClose(m_RenderNodes[i].fd); } EXPECT_SUCCESS(hsaKmtReleaseSystemProperties()); EXPECT_SUCCESS(hsaKmtCloseKFD()); g_baseTest = NULL; if (m_pAsm) delete m_pAsm; m_pAsm = nullptr; const testing::TestInfo* curr_test_info = ::testing::UnitTest::GetInstance()->current_test_info(); if (curr_test_info->result()->Passed()) syslog(LOG_INFO, "[Node#%03d] PASSED ========== %s.%s ==========", m_NodeInfo.HsaDefaultGPUNode(), curr_test_info->test_case_name(), curr_test_info->name()); else syslog(LOG_WARNING, "[Node#%03d] FAILED ========== %s.%s ==========", m_NodeInfo.HsaDefaultGPUNode(), curr_test_info->test_case_name(), curr_test_info->name()); closelog(); ROUTINE_END } HSAuint64 KFDBaseComponentTest::GetSysMemSize() { const HsaNodeProperties *nodeProps; HsaMemoryProperties cpuMemoryProps; HSAuint64 systemMemSize = 0; /* Find System Memory size */ for (unsigned node = 0; node < m_SystemProperties.NumNodes; node++) { nodeProps = m_NodeInfo.GetNodeProperties(node); if (nodeProps != NULL && nodeProps->NumCPUCores > 0 && nodeProps->NumMemoryBanks > 0) { /* For NUMA nodes, memory is distributed among different nodes. * Compute total system memory size. KFD driver also computes * the system memory (si_meminfo) similarly */ EXPECT_SUCCESS(hsaKmtGetNodeMemoryProperties(node, 1, &cpuMemoryProps)); systemMemSize += cpuMemoryProps.SizeInBytes; } } return systemMemSize; } HSAuint64 KFDBaseComponentTest::GetVramSize(int defaultGPUNode) { const HsaNodeProperties *nodeProps; /* Find framebuffer size */ nodeProps = m_NodeInfo.GetNodeProperties(defaultGPUNode); EXPECT_NE((const HsaNodeProperties *)NULL, nodeProps); HSAuint32 numBanks = nodeProps->NumMemoryBanks; HsaMemoryProperties memoryProps[numBanks]; EXPECT_SUCCESS(hsaKmtGetNodeMemoryProperties(defaultGPUNode, numBanks, memoryProps)); unsigned bank; for (bank = 0; bank < numBanks; bank++) { if (memoryProps[bank].HeapType == HSA_HEAPTYPE_FRAME_BUFFER_PRIVATE || memoryProps[bank].HeapType == HSA_HEAPTYPE_FRAME_BUFFER_PUBLIC) return memoryProps[bank].SizeInBytes; } return 0; } unsigned int KFDBaseComponentTest::GetFamilyIdFromNodeId(unsigned int nodeId) { return FamilyIdFromNode(m_NodeInfo.GetNodeProperties(nodeId)); } /* * Some asics need CWSR workround for DEGFX11_12113 */ bool KFDBaseComponentTest::NeedCwsrWA(unsigned int nodeId) { bool needCwsrWA = false; const HsaNodeProperties *props = m_NodeInfo.GetNodeProperties(nodeId); needCwsrWA = props->EngineId.ui32.Major == 11 && props->EngineId.ui32.Minor == 0 && (props->EngineId.ui32.Stepping == 0 || props->EngineId.ui32.Stepping == 1 || props->EngineId.ui32.Stepping == 2 || props->EngineId.ui32.Stepping == 5 || (props->EngineId.ui32.Stepping == 3 && props->NumArrays > 1)); return needCwsrWA; } bool KFDBaseComponentTest::NeedNonPagedWptr(unsigned int nodeId) { return GetFamilyIdFromNodeId(nodeId) >= FAMILY_GFX11; } int KFDBaseComponentTest::FindDRMRenderNode(int gpuNode) { HsaNodeProperties *nodeProperties; _HSAKMT_STATUS status; nodeProperties = new HsaNodeProperties(); status = hsaKmtGetNodeProperties(gpuNode, nodeProperties); EXPECT_SUCCESS(status) << "Node index: " << gpuNode << "hsaKmtGetNodeProperties returned status " << status; if (status != HSAKMT_STATUS_SUCCESS) { delete nodeProperties; return -EINVAL; } int minor = nodeProperties->DrmRenderMinor; if (minor < 128) { LOG() << "Failed to get minor number " << minor << std::endl; return -EINVAL; } int index = minor - 128; if (m_RenderNodes[index].fd == 0) { m_RenderNodes[index].fd = drmOpenRender(minor); if (m_RenderNodes[index].fd < 0) { LOG() << "Failed to open render node" << std::endl; return -EINVAL; } if (amdgpu_device_initialize(m_RenderNodes[index].fd, &m_RenderNodes[index].major_version, &m_RenderNodes[index].minor_version, &m_RenderNodes[index].device_handle) != 0) { drmClose(m_RenderNodes[index].fd); m_RenderNodes[index].fd = 0; LOG() << "Failed to initialize amdgpu device" << std::endl; return -EINVAL; } } return index; } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDBaseComponentTest.hpp000066400000000000000000000114771446477712600263010ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_BASE_COMPONENT_TEST__H__ #define __KFD_BASE_COMPONENT_TEST__H__ #include #include #include #include #include #include #include #include #include "hsakmt.h" #include "OSWrapper.hpp" #include "KFDTestUtil.hpp" #include "Assemble.hpp" #include "ShaderStore.hpp" // @class KFDBaseComponentTest class KFDBaseComponentTest : public testing::Test { public: KFDBaseComponentTest(void) { m_MemoryFlags.Value = 0; } ~KFDBaseComponentTest(void) {} HSAuint64 GetSysMemSize(); HSAuint64 GetVramSize(int defaultGPUNode); #define MAX_RENDER_NODES 64 struct { int fd; uint32_t major_version; uint32_t minor_version; amdgpu_device_handle device_handle; uint32_t bdf; } m_RenderNodes[MAX_RENDER_NODES]; // @brief Finds DRM Render node corresponding to gpuNode // @return DRM Render Node if successful or -1 on failure int FindDRMRenderNode(int gpuNode); unsigned int GetFamilyIdFromNodeId(unsigned int nodeId); bool NeedCwsrWA(unsigned int nodeId); bool NeedNonPagedWptr(unsigned int nodeId); unsigned int GetFamilyIdFromDefaultNode(){ return m_FamilyId; } // @brief Executed before the first test that uses KFDBaseComponentTest. static void SetUpTestCase(); // @brief Executed after the last test from KFDBaseComponentTest. static void TearDownTestCase(); protected: HsaVersionInfo m_VersionInfo; HsaSystemProperties m_SystemProperties; unsigned int m_FamilyId; unsigned int m_numCpQueues; unsigned int m_numSdmaEngines; unsigned int m_numSdmaXgmiEngines; unsigned int m_numSdmaQueuesPerEngine; HsaMemFlags m_MemoryFlags; HsaNodeInfo m_NodeInfo; HSAint32 m_xnack; Assembler* m_pAsm; // @brief Executed before every test that uses KFDBaseComponentTest class and sets all common settings for the tests. virtual void SetUp(); // @brief Executed after every test that uses KFDBaseComponentTest class. virtual void TearDown(); bool SVMAPISupported() { bool supported = m_NodeInfo.HsaDefaultGPUNodeProperties() ->Capability.ui32.SVMAPISupported; if (!supported) LOG() << "SVM API not supported" << std::endl; return supported; } // Set xnack_override to -1 if parameter is not passed in, to avoid unnecessary code churn void SVMSetXNACKMode(int xnack_override = -1) { if (!SVMAPISupported()) return; m_xnack = -1; HSAKMT_STATUS ret = hsaKmtGetXNACKMode(&m_xnack); if (ret != HSAKMT_STATUS_SUCCESS) { LOG() << "Failed " << ret << " to get XNACK mode" << std::endl; return; } HSAint32 xnack_on = -1; char *hsa_xnack = getenv("HSA_XNACK"); // HSA_XNACK takes priority over kfdtest parameters if (hsa_xnack) xnack_on = strncmp(hsa_xnack, "0", 1); else if (xnack_override > -1) xnack_on = xnack_override; else return; // No need to set XNACK if it's already the current value if (xnack_on == m_xnack) return; ret = hsaKmtSetXNACKMode(xnack_on); if (ret != HSAKMT_STATUS_SUCCESS) LOG() << "Failed " << ret << " to set XNACK mode " << xnack_on << std::endl; else LOG() << "Setting XNACK mode to " << xnack_on << std::endl; } void SVMRestoreXNACKMode() { if (!SVMAPISupported()) return; if (m_xnack == -1) return; hsaKmtSetXNACKMode(m_xnack); } }; extern KFDBaseComponentTest* g_baseTest; #endif // __KFD_BASE_COMPONENT_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDCWSRTest.cpp000066400000000000000000000166131446477712600243120ustar00rootroot00000000000000/* * Copyright (C) 2015-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDCWSRTest.hpp" #include "Dispatch.hpp" void KFDCWSRTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); ROUTINE_END } void KFDCWSRTest::TearDown() { ROUTINE_START KFDBaseComponentTest::TearDown(); ROUTINE_END } static inline uint32_t checkCWSREnabled() { uint32_t cwsr_enable = 0; fscanf_dec("/sys/module/amdgpu/parameters/cwsr_enable", &cwsr_enable); return cwsr_enable; } /** * KFDCWSRTest.BasicTest * * This test dispatches the PersistentIterateIsa shader, which continuously increments a vgpr for * (num_witems / WAVE_SIZE) waves. While this shader is running, dequeue/requeue requests * are sent in a loop to trigger CWSRs. * * This is a paremeterized test. See the INSTANTIATE_TEST_CASE_P below for an explanation * on the parameters. * * This test defines a CWSR threshold. The shader will continuously loop until inputBuf is * filled with the known stop value, which occurs once cwsr_thresh CWSRs have been * successfully triggered. * * 4 parameterized tests are defined: * * KFDCWSRTest.BasicTest/0 * KFDCWSRTest.BasicTest/1 * KFDCWSRTest.BasicTest/2 * KFDCWSRTest.BasicTest/3 * * 0: 1 work-item, CWSR threshold of 10 * 1: 256 work-items (multi-wave), CWSR threshold of 50 * 2: 512 work-items (multi-wave), CWSR threshold of 100 * 3: 1024 work-items (multi-wave), CWSR threshold of 1000 */ TEST_P(KFDCWSRTest, BasicTest) { TEST_START(TESTPROFILE_RUNALL); int num_witems = std::get<0>(GetParam()); int cwsr_thresh = std::get<1>(GetParam()); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); if ((m_FamilyId >= FAMILY_VI) && (checkCWSREnabled())) { HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true, false, true); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(PersistentIterateIsa, isaBuffer.As())); unsigned stopval = 0x1234'5678; unsigned outval = 0x8765'4321; // 4B per work-item ==> 1 page per 1024 work-items (take ceiling) unsigned bufSize = PAGE_SIZE * ((num_witems / 1024) + (num_witems % 1024 != 0)); HsaMemoryBuffer inputBuf(bufSize, defaultGPUNode, true, false, false); HsaMemoryBuffer outputBuf(bufSize, defaultGPUNode, true, false, false); unsigned int* input = inputBuf.As(); unsigned int* output = outputBuf.As(); inputBuf.Fill(0); outputBuf.Fill(outval); PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); Dispatch dispatch(isaBuffer); dispatch.SetArgs(input, output); dispatch.SetDim(num_witems, 1, 1); dispatch.Submit(queue); Delay(5); LOG() << "Starting iteration for " << std::dec << num_witems << " work items(s) (targeting " << std::dec << cwsr_thresh << " CWSRs)" << std::endl; for (int num_cwsrs = 0; num_cwsrs < cwsr_thresh; num_cwsrs++) { // Send dequeue request EXPECT_SUCCESS(queue.Update(0, BaseQueue::DEFAULT_PRIORITY, false)); Delay(5); // Send requeue request EXPECT_SUCCESS(queue.Update(100, BaseQueue::DEFAULT_PRIORITY, false)); Delay(50); // Check for reg mangling for (int i = 0; i < num_witems; i++) { EXPECT_EQ(outval, output[i]); } } LOG() << "Successful completion for " << std::dec << num_witems << " work item(s) (CWSRs triggered: " << std::dec << cwsr_thresh << ")" << std::endl; LOG() << "Signalling shader stop..." << std::endl; inputBuf.Fill(stopval); // Wait for shader to finish or timeout if shader has vm page fault EXPECT_EQ(0, dispatch.SyncWithStatus(180000)); EXPECT_SUCCESS(queue.Destroy()); } else { LOG() << "Skipping test: No CWSR present for family ID 0x" << m_FamilyId << "." << std::endl; } TEST_END } /** * Instantiates various KFDCWSRTest.BasicTest parameterizations * Tuple Format: (num_witems, cwsr_thresh) * * num_witems: Defines the number of work-items. * cwsr_thresh: Defines the number of CWSRs to trigger. */ INSTANTIATE_TEST_CASE_P( , KFDCWSRTest, ::testing::Values( std::make_tuple(1, 10), /* Single Wave Test, 10 CWSR Triggers */ std::make_tuple(256, 50), /* Multi Wave Test, 50 CWSR Triggers */ std::make_tuple(512, 100), /* Multi Wave Test, 100 CWSR Triggers */ std::make_tuple(1024, 1000) /* Multi Wave Test, 1000 CWSR Triggers */ ) ); /** * KFDCWSRTest.InterruptRestore * * This test verifies that CP can preempt an HQD while it is restoring a dispatch. * Create queue 1. * Start a dispatch on queue 1 which runs indefinitely and fills all CU wave slots. * Create queue 2, triggering context save on queue 1. * Start a dispatch on queue 2 which runs indefinitely and fills all CU wave slots. * Create queue 3, triggering context save and restore on queues 1 and 2. * Preempt runlist. One or both queues must interrupt context restore to preempt. */ TEST_F(KFDCWSRTest, InterruptRestore) { TEST_START(TESTPROFILE_RUNALL); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); if ((m_FamilyId >= FAMILY_VI) && (checkCWSREnabled())) { HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(InfiniteLoopIsa, isaBuffer.As())); PM4Queue queue1, queue2, queue3; ASSERT_SUCCESS(queue1.Create(defaultGPUNode)); Dispatch *dispatch1, *dispatch2; dispatch1 = new Dispatch(isaBuffer); dispatch2 = new Dispatch(isaBuffer); dispatch1->SetDim(0x10000, 1, 1); dispatch2->SetDim(0x10000, 1, 1); dispatch1->Submit(queue1); ASSERT_SUCCESS(queue2.Create(defaultGPUNode)); dispatch2->Submit(queue2); // Give waves time to launch. Delay(1); ASSERT_SUCCESS(queue3.Create(defaultGPUNode)); EXPECT_SUCCESS(queue1.Destroy()); EXPECT_SUCCESS(queue2.Destroy()); EXPECT_SUCCESS(queue3.Destroy()); delete dispatch1; delete dispatch2; } else { LOG() << "Skipping test: No CWSR present for family ID 0x" << m_FamilyId << "." << std::endl; } TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDCWSRTest.hpp000066400000000000000000000030731446477712600243130ustar00rootroot00000000000000/* * Copyright (C) 2015-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_CWSR_TEST__H__ #define __KFD_CWSR_TEST__H__ #include #include "PM4Queue.hpp" #include "KFDBaseComponentTest.hpp" class KFDCWSRTest : public KFDBaseComponentTest, public ::testing::WithParamInterface> { public: KFDCWSRTest() {} ~KFDCWSRTest() {} protected: virtual void SetUp(); virtual void TearDown(); }; #endif // __KFD_CWSR_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDDBGTest.cpp000066400000000000000000000731551446477712600241340ustar00rootroot00000000000000/* * Copyright (C) 2016-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDDBGTest.hpp" #include #include #include "linux/kfd_ioctl.h" #include "KFDQMTest.hpp" #include "PM4Queue.hpp" #include "PM4Packet.hpp" #include "Dispatch.hpp" #include #if 0 static const char* loop_inc_isa = \ "\ shader loop_inc_isa\n\ asic(VI)\n\ type(CS)\n\ vgpr_count(16)\n\ trap_present(1)\n\ /* TODO Enable here Address Watch Exception: */ \n\ /*copy the parameters from scalar registers to vector registers*/\n\ v_mov_b32 v0, s0\n\ v_mov_b32 v1, s1\n\ v_mov_b32 v2, s2\n\ v_mov_b32 v3, s3\n\ v_mov_b32 v5, 0 \n\ /*Iteration 1*/\n\ v_mov_b32 v4, -1\n\ flat_atomic_inc v5, v[0:1], v4 glc \n\ s_waitcnt vmcnt(0)&lgkmcnt(0)\n\ flat_load_dword v8, v[2:3] \n\ s_waitcnt vmcnt(0)&lgkmcnt(0)\n\ v_cmp_gt_u32 vcc, 2, v5 \n\ /*Iteration 2*/\n\ v_mov_b32 v4, -1\n\ flat_atomic_inc v5, v[0:1], v4 glc \n\ s_waitcnt vmcnt(0)&lgkmcnt(0)\n\ flat_load_dword v8, v[2:3] \n\ s_waitcnt vmcnt(0)&lgkmcnt(0)\n\ v_cmp_gt_u32 vcc, 2, v5 \n\ /*Epilogue*/\n\ v_mov_b32 v5, 0 \n\ s_endpgm\n\ \n\ end\n\ "; #endif static const char* iterate_isa_gfx = \ "\ shader iterate_isa\n\ wave_size(32) \n\ type(CS)\n\ /*copy the parameters from scalar registers to vector registers*/\n\ v_mov_b32 v0, s0\n\ v_mov_b32 v1, s1\n\ v_mov_b32 v2, s2\n\ v_mov_b32 v3, s3\n\ flat_load_dword v4, v[0:1] slc /*load target iteration value*/\n\ s_waitcnt vmcnt(0)&lgkmcnt(0)\n\ v_mov_b32 v5, 0\n\ LOOP:\n\ v_add_co_u32 v5, vcc, 1, v5\n\ s_waitcnt vmcnt(0)&lgkmcnt(0)\n\ /*compare the result value (v5) to iteration value (v4),*/\n\ /*and jump if equal (i.e. if VCC is not zero after the comparison)*/\n\ v_cmp_lt_u32 vcc, v5, v4\n\ s_cbranch_vccnz LOOP\n\ flat_store_dword v[2,3], v5\n\ s_waitcnt vmcnt(0)&lgkmcnt(0)\n\ s_endpgm\n\ end\n\ "; static const char* jump_to_trap_gfx = \ "\ shader jump_to_trap\n\ wave_size(32) \n\ type(CS)\n\ /*copy the parameters from scalar registers to vector registers*/\n\ s_trap 1\n\ v_mov_b32 v0, s0\n\ v_mov_b32 v1, s1\n\ v_mov_b32 v2, s2\n\ v_mov_b32 v3, s3\n\ flat_load_dword v4, v[0:1] slc /*load target iteration value*/\n\ s_waitcnt vmcnt(0)&lgkmcnt(0)\n\ v_mov_b32 v5, 0\n\ LOOP:\n\ v_add_co_u32 v5, vcc, 1, v5\n\ s_waitcnt vmcnt(0)&lgkmcnt(0)\n\ /*compare the result value (v5) to iteration value (v4),*/\n\ /*and jump if equal (i.e. if VCC is not zero after the comparison)*/\n\ v_cmp_lt_u32 vcc, v5, v4\n\ s_cbranch_vccnz LOOP\n\ flat_store_dword v[2,3], v5\n\ s_waitcnt vmcnt(0)&lgkmcnt(0)\n\ s_endpgm\n\ end\n\ "; static const char* trap_handler_gfx = \ "\ shader trap_handler\n\ wave_size(32) \n\ type(CS)\n\ CHECK_VMFAULT:\n\ /*if trap jumped to by vmfault, restore skip m0 signalling*/\n\ s_getreg_b32 ttmp14, hwreg(HW_REG_TRAPSTS)\n\ s_and_b32 ttmp2, ttmp14, 0x800\n\ s_cbranch_scc1 RESTORE_AND_EXIT\n\ GET_DOORBELL:\n\ s_mov_b32 ttmp2, exec_lo\n\ s_mov_b32 ttmp3, exec_hi\n\ s_mov_b32 exec_lo, 0x80000000\n\ s_sendmsg 10\n\ WAIT_SENDMSG:\n\ /*wait until msb is cleared (i.e. doorbell fetched)*/\n\ s_nop 7\n\ s_bitcmp0_b32 exec_lo, 0x1F\n\ s_cbranch_scc0 WAIT_SENDMSG\n\ SEND_INTERRUPT:\n\ /* set context bit and doorbell and restore exec*/\n\ s_mov_b32 exec_hi, ttmp3\n\ s_and_b32 exec_lo, exec_lo, 0xfff\n\ s_mov_b32 ttmp3, exec_lo\n\ s_bitset1_b32 ttmp3, 23\n\ s_mov_b32 exec_lo, ttmp2\n\ s_mov_b32 ttmp2, m0\n\ /* set m0, send interrupt and restore m0 and exit trap*/\n\ s_mov_b32 m0, ttmp3\n\ s_nop 0x0\n\ s_sendmsg sendmsg(MSG_INTERRUPT)\n\ s_mov_b32 m0, ttmp2\n\ RESTORE_AND_EXIT:\n\ /* restore and increment program counter to skip shader trap jump*/\n\ s_add_u32 ttmp0, ttmp0, 4\n\ s_addc_u32 ttmp1, ttmp1, 0\n\ s_and_b32 ttmp1, ttmp1, 0xffff\n\ /* restore SQ_WAVE_IB_STS */\n\ s_lshr_b32 ttmp2, ttmp11, (26 - 15)\n\ s_and_b32 ttmp2, ttmp2, (0x8000 | 0x1F0000)\n\ s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2\n\ /* restore SQ_WAVE_STATUS */\n\ s_and_b64 exec, exec, exec\n\ s_and_b64 vcc, vcc, vcc\n\ s_setreg_b32 hwreg(HW_REG_STATUS), ttmp12\n\ s_rfe_b64 [ttmp0, ttmp1]\n\ end\n\ "; void KFDDBGTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); ROUTINE_END } void KFDDBGTest::TearDown() { ROUTINE_START /* Reset the user trap handler */ hsaKmtSetTrapHandler(m_NodeInfo.HsaDefaultGPUNode(), 0, 0, 0, 0); KFDBaseComponentTest::TearDown(); ROUTINE_END } #if 0 // Functionality is deprecated now, keeping code for reference TEST_F(KFDDBGTest, BasicAddressWatch) { TEST_START(TESTPROFILE_RUNALL) if (m_FamilyId >= FAMILY_VI) { int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); static const unsigned int TMA_TRAP_COUNT_OFFSET = 3; static const unsigned int TMA_TRAP_COUNT_VALUE = 3; ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; // Allocate Buffers on System Memory HsaMemoryBuffer trapHandler(PAGE_SIZE*2, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer isaBuf(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer dstBuf(PAGE_SIZE*4, defaultGPUNode, true, false, false); HsaMemoryBuffer tmaBuf(PAGE_SIZE, defaultGPUNode, false, false, false); // Get Address Watch TrapHandler m_pIsaGen->GetAwTrapHandler(trapHandler); ASSERT_SUCCESS(hsaKmtSetTrapHandler(defaultGPUNode, trapHandler.As(), 0x1000, tmaBuf.As(), 0x1000)); m_pIsaGen->CompileShader(loop_inc_isa, "loop_inc_isa", isaBuf); PM4Queue queue, queue_flush; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); ASSERT_SUCCESS(queue_flush.Create(defaultGPUNode)); // Set Address Watch Params // TODO: Set WatchMode[1] to Atomic in case we want to test this mode. HSA_DBG_WATCH_MODE WatchMode[2]; HSAuint64 WatchAddress[2]; HSAuint64 WatchMask[2]; HSAKMT_STATUS AddressWatchSuccess; HSAuint64 AddressMask64 = 0x0; unsigned char *secDstBuf = (unsigned char *)dstBuf.As() + 8192; WatchMode[0] = HSA_DBG_WATCH_ALL; WatchAddress[0] = (HSAuint64) dstBuf.As() & (~AddressMask64); WatchMask[0] = ~AddressMask64; WatchMode[1] = HSA_DBG_WATCH_ALL; WatchAddress[1] = (HSAuint64)secDstBuf & (~AddressMask64); WatchMask[1] = ~AddressMask64; queue_flush.PlaceAndSubmitPacket(PM4WriteDataPacket(dstBuf.As(), 0x0, 0x0)); queue_flush.PlaceAndSubmitPacket(PM4WriteDataPacket((unsigned int *)secDstBuf, 0x0, 0x0)); Delay(50); ASSERT_SUCCESS(hsaKmtDbgRegister(defaultGPUNode)); AddressWatchSuccess = hsaKmtDbgAddressWatch( defaultGPUNode, // IN 2, // # watch points &WatchMode[0], // IN reinterpret_cast(&WatchAddress[0]), // IN &WatchMask[0], // IN, optional NULL); // IN, optional EXPECT_EQ(AddressWatchSuccess, HSAKMT_STATUS_SUCCESS); Dispatch dispatch(isaBuf); dispatch.SetArgs(dstBuf.As(), reinterpret_cast(secDstBuf)); dispatch.SetDim(1, 1, 1); /* TODO: Use Memory ordering rules w/ atomics for host-GPU memory syncs. * Set to std::memory_order_seq_cst */ dispatch.Submit(queue); Delay(50); dispatch.Sync(g_TestTimeOut); // Check that we got trap handler calls due to add watch triggers EXPECT_GE(*(tmaBuf.As()+ TMA_TRAP_COUNT_OFFSET), TMA_TRAP_COUNT_VALUE); EXPECT_SUCCESS(hsaKmtDbgUnregister(defaultGPUNode)); EXPECT_SUCCESS(queue.Destroy()); EXPECT_SUCCESS(queue_flush.Destroy()); } else { LOG() << "Skipping test: Test not supported on family ID 0x" << m_FamilyId << "." << std::endl; } TEST_END } #endif #if 0 // Deprecated - Reference Use Only /** * checkDebugVersion: * Inputs: * HSAuint32 requiredMajor * -- Required major version number * HSAuint32 requiredMinor * -- Required minor version number * Output: * bool: * i) false if major version of thunk and kernel are not the same * ii) false if kernel minor version is less than the required * version if the major version is the required version. * iii) false if thunk minor version is less than the required * version if the major version is the required version. * iv) false if hsaKmtGetKernelDebugTrapVersionInfo() call fails. * v) true otherwise. * */ static bool checkDebugVersion(HSAuint32 requiredMajor, HSAuint32 requiredMinor) { HSAuint32 kernelMajorNumber = 0; HSAuint32 kernelMinorNumber = 0; HSAuint32 thunkMajorNumber = 0; HSAuint32 thunkMinorNumber = 0; hsaKmtGetThunkDebugTrapVersionInfo(&thunkMajorNumber, &thunkMinorNumber); if (hsaKmtGetKernelDebugTrapVersionInfo(&kernelMajorNumber, &kernelMinorNumber)) { LOG() << "Failed to get kernel debugger version!" << std::endl; return false; } if (kernelMajorNumber != thunkMajorNumber) return false; if (kernelMajorNumber < requiredMajor || (kernelMajorNumber == requiredMajor && kernelMinorNumber < requiredMinor)) return false; if (thunkMajorNumber < requiredMajor || (thunkMajorNumber == requiredMajor && thunkMinorNumber < requiredMinor)) return false; return true; } #endif #if 0 // Deprecated - Reference Use Only TEST_F(KFDDBGTest, BasicDebuggerSuspendResume) { TEST_START(TESTPROFILE_RUNALL) if (m_FamilyId >= FAMILY_AI) { int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HSAuint32 Flags = 0; if(!checkDebugVersion(0, 2)) { LOG() << "Test disabled due to debug API version mismatch"; goto exit; } HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer iterateBuf(PAGE_SIZE, defaultGPUNode, true, false, false); HsaMemoryBuffer resultBuf(PAGE_SIZE, defaultGPUNode, true, false, false); unsigned int* iter = iterateBuf.As(); unsigned int* result = resultBuf.As(); int suspendTimeout = 500; int syncStatus; m_pIsaGen->CompileShader(iterate_isa_gfx, "iterate_isa", isaBuffer); PM4Queue queue1; HsaQueueResource *qResources; HSA_QUEUEID queue_ids[2]; ASSERT_SUCCESS(queue1.Create(defaultGPUNode)); Dispatch *dispatch1; dispatch1 = new Dispatch(isaBuffer); dispatch1->SetArgs(&iter[0], &result[0]); dispatch1->SetDim(1, 1, 1); // Need a loop large enough so we don't finish before we call Suspend. // 150000000 takes between 5 and 6 seconds, which is long enough // to test the suspend/resume. iter[0] = 150000000; ASSERT_EQ(ptrace(PTRACE_TRACEME, 0, 0, 0), 0); ASSERT_SUCCESS(hsaKmtEnableDebugTrap(defaultGPUNode, INVALID_QUEUEID)); // Submit the shader, queue1 dispatch1->Submit(queue1); qResources = queue1.GetResource(); queue_ids[0] = qResources->QueueId; ASSERT_SUCCESS(hsaKmtQueueSuspend( INVALID_PID, 1, // one queue queue_ids, 10, // grace period Flags)); syncStatus = dispatch1->SyncWithStatus(suspendTimeout); ASSERT_NE(syncStatus, HSAKMT_STATUS_SUCCESS); ASSERT_NE(iter[0], result[0]); // The shader hasn't finished, we will wait for 20 seconds, // and then check if it has finished. If it was suspended, // it should not have finished. Delay(20000); // Check that the shader has not finished yet. syncStatus = dispatch1->SyncWithStatus(suspendTimeout); ASSERT_NE(syncStatus, HSAKMT_STATUS_SUCCESS); ASSERT_NE(iter[0], result[0]); ASSERT_SUCCESS(hsaKmtQueueResume( INVALID_PID, 1, // Num queues queue_ids, Flags)); dispatch1->Sync(); ASSERT_EQ(iter[0], result[0]); EXPECT_SUCCESS(queue1.Destroy()); ASSERT_SUCCESS(hsaKmtDisableDebugTrap(defaultGPUNode)); } else { LOG() << "Skipping test: Test not supported on family ID 0x" << m_FamilyId << "." << std::endl; } exit: LOG() << std::endl; TEST_END } #endif #if 0 // Deprecated - Reference Use Only TEST_F(KFDDBGTest, BasicDebuggerQueryQueueStatus) { TEST_START(TESTPROFILE_RUNALL) if (m_FamilyId >= FAMILY_AI) { int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); HSAint32 PollFd; ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (!checkDebugVersion(0, 2)) { LOG() << "Test disabled due to debug API version mismatch"; goto exit; } // enable debug trap and check poll fd creation ASSERT_SUCCESS(hsaKmtEnableDebugTrapWithPollFd(defaultGPUNode, INVALID_QUEUEID, &PollFd)); ASSERT_GT(PollFd, 0) << "failed to create polling file descriptor"; // create shader and trap bufs then enable 2nd level trap HsaMemoryBuffer isaBuf(PAGE_SIZE, defaultGPUNode, true, false, true); HsaMemoryBuffer iterBuf(PAGE_SIZE, defaultGPUNode, true, false, false); HsaMemoryBuffer resBuf(PAGE_SIZE, defaultGPUNode, true, false, false); HsaMemoryBuffer trap(PAGE_SIZE*2, defaultGPUNode, true, false, true); HsaMemoryBuffer tmaBuf(PAGE_SIZE, defaultGPUNode, false, false, false); ASSERT_SUCCESS(hsaKmtSetTrapHandler(defaultGPUNode, trap.As(), 0x1000, tmaBuf.As(), 0x1000)); // compile and dispatch shader m_pIsaGen->CompileShader(jump_to_trap_gfx, "jump_to_trap", isaBuf); m_pIsaGen->CompileShader(trap_handler_gfx, "trap_handler", trap); PM4Queue queue; HsaQueueResource *qResources; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); unsigned int* iter = iterBuf.As(); unsigned int* result = resBuf.As(); int suspendTimeout = 500; int syncStatus; iter[0] = 150000000; Dispatch *dispatch; dispatch = new Dispatch(isaBuf); dispatch->SetArgs(&iter[0], &result[0]); dispatch->SetDim(1, 1, 1); dispatch->Submit(queue); qResources = queue.GetResource(); // poll, read and query for pending trap event struct pollfd fds[1]; fds[0].fd = PollFd; fds[0].events = POLLIN | POLLRDNORM; ASSERT_GT(poll(fds, 1, 5000), 0); char trapChar; ASSERT_GT(read(PollFd, &trapChar, 1), 0); ASSERT_EQ('t', trapChar); HSAuint32 invalidQid = 0xffffffff; HSAuint32 qid = invalidQid; HSA_QUEUEID queueIds[1] = { qResources->QueueId}; HSA_DEBUG_EVENT_TYPE EventReceived; bool IsSuspended = false; bool IsNew = false; ASSERT_SUCCESS(hsaKmtQueryDebugEvent(defaultGPUNode, INVALID_PID, &qid, false, &EventReceived, &IsSuspended, &IsNew)); ASSERT_NE(qid, invalidQid); ASSERT_EQ(IsSuspended, false); ASSERT_EQ(IsNew, true); ASSERT_EQ(EventReceived, HSA_DEBUG_EVENT_TYPE_TRAP); // suspend queue, get snapshot, query suspended queue // and clear pending event ASSERT_SUCCESS(hsaKmtQueueSuspend(INVALID_PID, 1, queueIds, 10, 0)); syncStatus = dispatch->SyncWithStatus(suspendTimeout); ASSERT_NE(syncStatus, HSAKMT_STATUS_SUCCESS); ASSERT_NE(iter[0], result[0]); struct kfd_queue_snapshot_entry qssBuf[1] = {}; HSAuint32 QssEntries = 0; // get only number of queues and don't update the snapshot buffer ASSERT_SUCCESS(hsaKmtGetQueueSnapshot(INVALID_NODEID, INVALID_PID, false, reinterpret_cast(qssBuf), &QssEntries)); ASSERT_EQ(QssEntries, 1); ASSERT_EQ(qssBuf[0].ctx_save_restore_address, 0); ASSERT_EQ(qssBuf[0].ring_base_address, 0); ASSERT_EQ(qssBuf[0].ring_size, 0); // update the snapshot buffer QssEntries = 1; ASSERT_SUCCESS(hsaKmtGetQueueSnapshot(INVALID_NODEID, INVALID_PID, false, reinterpret_cast(qssBuf), &QssEntries)); ASSERT_EQ(QssEntries, 1); ASSERT_NE(qssBuf[0].ctx_save_restore_address, 0); ASSERT_NE(qssBuf[0].ring_base_address, 0); ASSERT_NE(qssBuf[0].ring_size, 0); ASSERT_SUCCESS(hsaKmtQueryDebugEvent(defaultGPUNode, INVALID_PID, &qid, true, &EventReceived, &IsSuspended, &IsNew)); ASSERT_EQ(IsSuspended, true); ASSERT_SUCCESS(hsaKmtQueueResume(INVALID_PID, 1, queueIds, 0)); ASSERT_SUCCESS(hsaKmtQueryDebugEvent(defaultGPUNode, INVALID_PID, &qid, false, &EventReceived, &IsSuspended, &IsNew)); ASSERT_EQ(IsSuspended, false); ASSERT_EQ(IsNew, false); ASSERT_EQ(EventReceived, HSA_DEBUG_EVENT_TYPE_NONE); dispatch->Sync(); ASSERT_EQ(iter[0], result[0]); EXPECT_SUCCESS(queue.Destroy()); ASSERT_SUCCESS(hsaKmtDisableDebugTrap(defaultGPUNode)); ASSERT_EQ(close(PollFd), 0); } else { LOG() << "Skipping test: Test not supported on family ID 0x" << m_FamilyId << "." << std::endl; } exit: LOG() << std::endl; TEST_END } #endif #if 0 // clean up routine // Deprecated - Reference Use Only static void ExitVMFaultQueryChild(std::string errMsg, int exitStatus, HSAint32 pollFd, PM4Queue *queue1, PM4Queue *queue2, HsaEvent *event, int gpuNode) { if (queue1) queue1->Destroy(); if (queue2) queue2->Destroy(); if (event) { int ret = hsaKmtDestroyEvent(event); if (ret) { exitStatus = 1; errMsg = "event failed to be destroyed"; } } if (pollFd >= 0) close(pollFd); if (gpuNode >= 0) { int ret = hsaKmtDisableDebugTrap(gpuNode); if (ret) { exitStatus = 1; errMsg = "debug trap failed to disable"; } } if (!errMsg.empty()) WARN() << errMsg << std::endl; exit(exitStatus); } #endif #if 0 // Deprecated - Reference Use Only TEST_F(KFDDBGTest, BasicDebuggerQueryVMFaultQueueStatus) { TEST_START(TESTPROFILE_RUNALL) if (m_FamilyId >= FAMILY_AI) { int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (!checkDebugVersion(0, 2)) { LOG() << "Test disabled due to debug API version mismatch"; goto exit; } pid_t childPid = fork(); ASSERT_GE(childPid, 0); // fork to child since vm faults halt all queues if (childPid == 0) { HSAint32 PollFd; HSAKMT_STATUS ret; bool childStatus; ret = hsaKmtOpenKFD(); if (ret != HSAKMT_STATUS_SUCCESS) ExitVMFaultQueryChild("KFD open failed", 1, -1, NULL, NULL, NULL, -1); // enable debug trap and check poll fd creation ret = hsaKmtEnableDebugTrapWithPollFd(defaultGPUNode, INVALID_QUEUEID, &PollFd); if (ret != HSAKMT_STATUS_SUCCESS || PollFd <= 0) ExitVMFaultQueryChild("enable debug trap with poll fd failed", 1, -1, NULL, NULL, NULL, defaultGPUNode); // create shader, vmfault and trap bufs then enable 2nd level trap HsaMemoryBuffer vmFaultBuf(PAGE_SIZE, defaultGPUNode, true, false, true); HsaMemoryBuffer srcBuf(PAGE_SIZE, defaultGPUNode, false); srcBuf.Fill(0xABCDABCD); HsaMemoryBuffer isaBuf(PAGE_SIZE, defaultGPUNode, true, false, true); HsaMemoryBuffer iterBuf(PAGE_SIZE, defaultGPUNode, true, false, false); HsaMemoryBuffer resBuf(PAGE_SIZE, defaultGPUNode, true, false, false); HsaMemoryBuffer trap(PAGE_SIZE*2, defaultGPUNode, true, false, true); HsaMemoryBuffer tmaBuf(PAGE_SIZE, defaultGPUNode, false, false, false); ret = hsaKmtSetTrapHandler(defaultGPUNode, trap.As(), 0x1000, tmaBuf.As(), 0x1000); if (ret != HSAKMT_STATUS_SUCCESS) ExitVMFaultQueryChild("setting trap handler failed", 1, PollFd, NULL, NULL, NULL, defaultGPUNode); // compile and dispatch shader m_pIsaGen->CompileShader(jump_to_trap_gfx, "jump_to_trap", isaBuf); m_pIsaGen->CompileShader(trap_handler_gfx, "trap_handler", trap); PM4Queue queue1, queue2; HSAuint32 qid1; if (queue1.Create(defaultGPUNode) != HSAKMT_STATUS_SUCCESS) ExitVMFaultQueryChild("queue 1 creation failed", 1, PollFd, NULL, NULL, NULL, defaultGPUNode); if (queue2.Create(defaultGPUNode) != HSAKMT_STATUS_SUCCESS) ExitVMFaultQueryChild("queue 2 creation failed", 1, PollFd, &queue1, NULL, NULL, defaultGPUNode); unsigned int* iter = iterBuf.As(); unsigned int* result = resBuf.As(); int suspendTimeout = 500; iter[0] = 150000000; Dispatch *dispatch1; dispatch1 = new Dispatch(isaBuf); dispatch1->SetArgs(&iter[0], &result[0]); dispatch1->SetDim(1, 1, 1); dispatch1->Submit(queue1); // poll, read and query pending trap event struct pollfd fds[1]; fds[0].fd = PollFd; fds[0].events = POLLIN | POLLRDNORM; if (poll(fds, 1, 5000) <= 0) ExitVMFaultQueryChild("poll wake on pending trap event failed", 1, PollFd, &queue1, &queue2, NULL, defaultGPUNode); int kMaxSize = 4096; char fifoBuf[kMaxSize]; childStatus = read(PollFd, fifoBuf, 1) == -1\ || strchr(fifoBuf, 't') == NULL; if (childStatus) ExitVMFaultQueryChild("read on pending trap event failed", 1, PollFd, &queue1, &queue2, NULL, defaultGPUNode); memset(fifoBuf, 0, sizeof(fifoBuf)); HSA_DEBUG_EVENT_TYPE EventReceived; bool IsSuspended; bool IsNew; HSAuint32 invalidQid = 0xffffffff; qid1 = invalidQid; ret = hsaKmtQueryDebugEvent(defaultGPUNode, INVALID_PID, &qid1, false, &EventReceived, &IsSuspended, &IsNew); childStatus = ret != HSAKMT_STATUS_SUCCESS || EventReceived != HSA_DEBUG_EVENT_TYPE_TRAP; if (childStatus) ExitVMFaultQueryChild("query on pending trap event failed", 1, PollFd, &queue1, &queue2, NULL, defaultGPUNode); // create and wait on pending vmfault event HsaEvent *vmFaultEvent; HsaEventDescriptor eventDesc; eventDesc.EventType = HSA_EVENTTYPE_MEMORY; eventDesc.NodeId = defaultGPUNode; eventDesc.SyncVar.SyncVar.UserData = NULL; eventDesc.SyncVar.SyncVarSize = 0; ret = hsaKmtCreateEvent(&eventDesc, true, false, &vmFaultEvent); if (ret != HSAKMT_STATUS_SUCCESS) ExitVMFaultQueryChild("create vmfault event failed", 1, PollFd, &queue1, &queue2, NULL, defaultGPUNode); Dispatch dispatch2(vmFaultBuf, false); dispatch2.SetArgs( reinterpret_cast(srcBuf.As()), reinterpret_cast(0xABBAABBAULL)); dispatch2.SetDim(1, 1, 1); dispatch2.Submit(queue2); ret = hsaKmtWaitOnEvent(vmFaultEvent, g_TestTimeOut); if (ret != HSAKMT_STATUS_SUCCESS) ExitVMFaultQueryChild("wait on vmfault event failed", 1, PollFd, &queue1, &queue2, vmFaultEvent, defaultGPUNode); // poll, read and query on pending vmfault event if (poll(fds, 1, 5000) <= 0) ExitVMFaultQueryChild("poll wake on vmfault event failed", 1, PollFd, &queue1, &queue2, vmFaultEvent, defaultGPUNode); childStatus = read(PollFd, fifoBuf, kMaxSize) == -1 || strchr(fifoBuf, 'v') == NULL || strchr(fifoBuf, 't'); if (childStatus) ExitVMFaultQueryChild("read on vmfault event failed", 1, PollFd, &queue1, &queue2, vmFaultEvent, defaultGPUNode); ret = hsaKmtQueryDebugEvent(defaultGPUNode, INVALID_PID, &qid1, true, &EventReceived, &IsSuspended, &IsNew); childStatus = ret != HSAKMT_STATUS_SUCCESS || EventReceived != HSA_DEBUG_EVENT_TYPE_TRAP_VMFAULT; if (childStatus) ExitVMFaultQueryChild("query on vmfault event failed", 1, PollFd, &queue1, &queue2, vmFaultEvent, defaultGPUNode); ExitVMFaultQueryChild("", 0, PollFd, &queue1, &queue2, vmFaultEvent, defaultGPUNode); } else { int childStatus; ASSERT_EQ(childPid, waitpid(childPid, &childStatus, 0)); ASSERT_NE(0, WIFEXITED(childStatus)); ASSERT_EQ(0, WEXITSTATUS(childStatus)); } } else { LOG() << "Skipping test: Test not supported on family ID 0x" << m_FamilyId << "." << std::endl; } exit: LOG() << std::endl; TEST_END } #endif ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDDBGTest.hpp000066400000000000000000000027151446477712600241330ustar00rootroot00000000000000/* * Copyright (C) 2016-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_DBG_TEST__H__ #define __KFD_DBG_TEST__H__ #include #include "KFDBaseComponentTest.hpp" class KFDDBGTest : public KFDBaseComponentTest { public: KFDDBGTest() {} ~KFDDBGTest() {} protected: virtual void SetUp(); virtual void TearDown(); }; #endif // __KFD_DBG_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDEventTest.cpp000066400000000000000000000353521446477712600246160ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include "KFDEventTest.hpp" #include "PM4Queue.hpp" #include "PM4Packet.hpp" void KFDEventTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); m_pHsaEvent = NULL; ROUTINE_END } void KFDEventTest::TearDown() { ROUTINE_START // Not all tests create an event, destroy only if there is one if (m_pHsaEvent != NULL) { // hsaKmtDestroyEvent moved to TearDown to make sure it is being called EXPECT_SUCCESS(hsaKmtDestroyEvent(m_pHsaEvent)); } KFDBaseComponentTest::TearDown(); ROUTINE_END } TEST_F(KFDEventTest, CreateDestroyEvent) { TEST_START(TESTPROFILE_RUNALL); ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, m_NodeInfo.HsaDefaultGPUNode(), &m_pHsaEvent)); EXPECT_NE(0, m_pHsaEvent->EventData.HWData2); // Destroy event is being called in test TearDown TEST_END; } TEST_F(KFDEventTest, CreateMaxEvents) { TEST_START(TESTPROFILE_RUNALL); static const unsigned int MAX_EVENT_NUMBER = 256; HsaEvent* pHsaEvent[MAX_EVENT_NUMBER]; unsigned int i = 0; for (i = 0; i < MAX_EVENT_NUMBER; i++) { pHsaEvent[i] = NULL; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, m_NodeInfo.HsaDefaultGPUNode(), &pHsaEvent[i])); } for (i = 0; i < MAX_EVENT_NUMBER; i++) { EXPECT_SUCCESS(hsaKmtDestroyEvent(pHsaEvent[i])); } TEST_END; } TEST_F(KFDEventTest, SignalEvent) { TEST_START(TESTPROFILE_RUNALL); PM4Queue queue; HsaEvent *tmp_event; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &tmp_event)); /* Intentionally let event id for m_pHsaEvent be non zero */ ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &m_pHsaEvent)); ASSERT_NE(0, m_pHsaEvent->EventData.HWData2); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); /* From gfx9 onward, m_pHsaEvent->EventId will also be passed to int_ctxid in * the Release Mem packet, which is used as context id in ISR. */ queue.PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, false, m_pHsaEvent->EventData.HWData2, m_pHsaEvent->EventId)); queue.Wait4PacketConsumption(); EXPECT_SUCCESS(hsaKmtWaitOnEvent(m_pHsaEvent, g_TestTimeOut)); EXPECT_SUCCESS(hsaKmtDestroyEvent(tmp_event)); EXPECT_SUCCESS(queue.Destroy()); TEST_END; } /* test event signaling with event age enabled wait */ TEST_F(KFDEventTest, SignalEventExt) { TEST_START(TESTPROFILE_RUNALL); PM4Queue queue; HsaEvent *tmp_event; uint64_t event_age; if (m_VersionInfo.KernelInterfaceMajorVersion == 1 && m_VersionInfo.KernelInterfaceMinorVersion < 14) { LOG() << "event age tracking isn't supported in KFD. Exiting." << std::endl; return; } int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &tmp_event)); /* Intentionally let event id for m_pHsaEvent be non zero */ ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &m_pHsaEvent)); ASSERT_NE(0, m_pHsaEvent->EventData.HWData2); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); /* 1. event_age gets incremented every time when the event signals */ event_age = 1; queue.PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, false, m_pHsaEvent->EventData.HWData2, m_pHsaEvent->EventId)); EXPECT_SUCCESS(hsaKmtWaitOnEvent_Ext(m_pHsaEvent, g_TestTimeOut, &event_age)); ASSERT_EQ(event_age, 2); queue.PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, false, m_pHsaEvent->EventData.HWData2, m_pHsaEvent->EventId)); EXPECT_SUCCESS(hsaKmtWaitOnEvent_Ext(m_pHsaEvent, g_TestTimeOut, &event_age)); ASSERT_EQ(event_age, 3); /* 2. event wait return without sleep after the event signals */ queue.PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, false, m_pHsaEvent->EventData.HWData2, m_pHsaEvent->EventId)); sleep(1); /* wait for event signaling */ EXPECT_SUCCESS(hsaKmtWaitOnEvent_Ext(m_pHsaEvent, g_TestTimeOut, &event_age)); ASSERT_EQ(event_age, 4); /* 3. signaling from CPU */ hsaKmtSetEvent(m_pHsaEvent); EXPECT_SUCCESS(hsaKmtWaitOnEvent_Ext(m_pHsaEvent, g_TestTimeOut, &event_age)); ASSERT_EQ(event_age, 5); /* 4. when event_age is 0, hsaKmtWaitOnEvent_Ext always sleeps */ event_age = 0; ASSERT_EQ(HSAKMT_STATUS_WAIT_TIMEOUT, hsaKmtWaitOnEvent_Ext(m_pHsaEvent, g_TestTimeOut, &event_age)); /* 5. when event_age is 0, it always stays 0 after the event signals */ queue.PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, false, m_pHsaEvent->EventData.HWData2, m_pHsaEvent->EventId)); EXPECT_SUCCESS(hsaKmtWaitOnEvent_Ext(m_pHsaEvent, g_TestTimeOut, &event_age)); ASSERT_EQ(event_age, 0); EXPECT_SUCCESS(hsaKmtDestroyEvent(tmp_event)); EXPECT_SUCCESS(queue.Destroy()); TEST_END; } static uint64_t gettime() { struct timespec ts; clock_gettime(CLOCK_MONOTONIC, &ts); return ((int64_t)ts.tv_sec) * 1000 * 1000 * 1000 + ts.tv_nsec; } static inline double pow2_round_up(int num) { return pow(2, ceil(log(num)/log(2))); } class QueueAndSignalBenchmark { private: static const int HISTORY_SIZE = 100; int mNumEvents; int mHistorySlot; uint64_t mTimeHistory[HISTORY_SIZE]; uint64_t mLatHistory[HISTORY_SIZE]; public: QueueAndSignalBenchmark(int events) : mNumEvents(events), mHistorySlot(0) { memset(mTimeHistory, 0, sizeof(mTimeHistory)); memset(mLatHistory, 0, sizeof(mLatHistory)); } int queueAndSignalEvents(int node, int eventCount, uint64_t &time, uint64_t &latency) { int r; uint64_t startTime; PM4Queue queue; unsigned int familyId = g_baseTest->GetFamilyIdFromNodeId(node); HsaEvent** pHsaEvent = reinterpret_cast(calloc(eventCount, sizeof(HsaEvent*))); size_t packetSize = PM4ReleaseMemoryPacket(familyId, false, 0, 0).SizeInBytes(); int qSize = fmax(PAGE_SIZE, pow2_round_up(packetSize*eventCount + 1)); time = 0; r = queue.Create(node, qSize); if (r != HSAKMT_STATUS_SUCCESS) goto exit; for (int i = 0; i < eventCount; i++) { r = CreateQueueTypeEvent(false, false, node, &pHsaEvent[i]); if (r != HSAKMT_STATUS_SUCCESS) goto exit; queue.PlacePacket(PM4ReleaseMemoryPacket(familyId, false, pHsaEvent[i]->EventData.HWData2, pHsaEvent[i]->EventId)); } startTime = gettime(); queue.SubmitPacket(); for (int i = 0; i < eventCount; i++) { r = hsaKmtWaitOnEvent(pHsaEvent[i], g_TestTimeOut); if (r != HSAKMT_STATUS_SUCCESS) goto exit; if (i == 0) latency = gettime() - startTime; } time = gettime() - startTime; exit: for (int i = 0; i < eventCount; i++) { if (pHsaEvent[i]) hsaKmtDestroyEvent(pHsaEvent[i]); } queue.Destroy(); return r; } void run(int node) { int r = 0; uint64_t time = 0, latency = 0; uint64_t avgLat = 0, avgTime = 0; uint64_t minTime = ULONG_MAX, maxTime = 0; uint64_t minLat = ULONG_MAX, maxLat = 0; ASSERT_EQ(queueAndSignalEvents(node, mNumEvents, time, latency), HSAKMT_STATUS_SUCCESS); mTimeHistory[mHistorySlot%HISTORY_SIZE] = time; mLatHistory[mHistorySlot%HISTORY_SIZE] = latency; for (int i = 0; i < HISTORY_SIZE; i++) { minTime = mTimeHistory[i] < minTime ? mTimeHistory[i] : minTime; maxTime = mTimeHistory[i] > maxTime ? mTimeHistory[i] : maxTime; avgTime += mTimeHistory[i]; minLat = mLatHistory[i] < minLat ? mLatHistory[i] : minLat; maxLat = mLatHistory[i] > maxLat ? mLatHistory[i] : maxLat; avgLat += mLatHistory[i]; } avgTime /= HISTORY_SIZE; avgLat /= HISTORY_SIZE; mHistorySlot++; printf("\033[KEvents: %d History: %d/%d\n", mNumEvents, mHistorySlot, HISTORY_SIZE); printf("\033[KMin Latency: %f ms\n", (float)minLat/1000000); printf("\033[KMax Latency: %f ms\n", (float)maxLat/1000000); printf("\033[KAvg Latency: %f ms\n", (float)avgLat/1000000); printf("\033[K Min Rate: %f IH/ms\n", ((float)mNumEvents)/maxTime*1000000); printf("\033[K Max Rate: %f IH/ms\n", ((float)mNumEvents)/minTime*1000000); printf("\033[K Avg Rate: %f IH/ms\n", ((float)mNumEvents)/avgTime*1000000); } }; TEST_F(KFDEventTest, MeasureInterruptConsumption) { TEST_START(TESTPROFILE_RUNALL); QueueAndSignalBenchmark latencyBench(128); QueueAndSignalBenchmark sustainedBench(4095); printf("\033[2J"); while (true) { printf("\033[H"); printf("--------------------------\n"); latencyBench.run(m_NodeInfo.HsaDefaultGPUNode()); printf("--------------------------\n"); sustainedBench.run(m_NodeInfo.HsaDefaultGPUNode()); printf("--------------------------\n"); } TEST_END; } TEST_F(KFDEventTest, SignalMaxEvents) { TEST_START(TESTPROFILE_RUNALL); static const unsigned int MAX_EVENT_NUMBER = 4095; uint64_t time, latency; QueueAndSignalBenchmark maxEventTest(MAX_EVENT_NUMBER); maxEventTest.queueAndSignalEvents(m_NodeInfo.HsaDefaultGPUNode(), MAX_EVENT_NUMBER, time, latency); TEST_END; } TEST_F(KFDEventTest, SignalMultipleEventsWaitForAll) { TEST_START(TESTPROFILE_RUNALL); static const unsigned int EVENT_NUMBER = 64; // 64 is the maximum for hsaKmtWaitOnMultipleEvents static const unsigned int WAIT_BETWEEN_SUBMISSIONS_MS = 50; HsaEvent* pHsaEvent[EVENT_NUMBER]; unsigned int i = 0; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; for (i = 0; i < EVENT_NUMBER; i++) { pHsaEvent[i] = NULL; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &pHsaEvent[i])); } PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); unsigned int pktSizeDwords = 0; for (i = 0; i < EVENT_NUMBER; i++) { queue.PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, false, pHsaEvent[i]->EventData.HWData2, pHsaEvent[i]->EventId)); queue.Wait4PacketConsumption(); Delay(WAIT_BETWEEN_SUBMISSIONS_MS); } EXPECT_SUCCESS(hsaKmtWaitOnMultipleEvents(pHsaEvent, EVENT_NUMBER, true, g_TestTimeOut)); EXPECT_SUCCESS(queue.Destroy()); for (i = 0; i < EVENT_NUMBER; i++) EXPECT_SUCCESS(hsaKmtDestroyEvent(pHsaEvent[i])); TEST_END; } /* Send an event interrupt with 0 context ID. Test that KFD handles it * gracefully and with good performance. On current GPUs and firmware it * should be handled on a fast path. */ TEST_F(KFDEventTest, SignalInvalidEvent) { TEST_START(TESTPROFILE_RUNALL); PM4Queue queue; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; // Create some dummy events, to make the slow path a bit slower static const unsigned int EVENT_NUMBER = 4094; HsaEvent* pHsaEvent[EVENT_NUMBER]; for (int i = 0; i < EVENT_NUMBER; i++) { pHsaEvent[i] = NULL; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &pHsaEvent[i])); } ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &m_pHsaEvent)); ASSERT_NE(0, m_pHsaEvent->EventData.HWData2); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); static const unsigned int REPS = 2000; HSAuint64 duration[REPS]; HSAuint64 total = 0, min = 1000000, max = 0; for (int i = 0; i < REPS; i++) { // Invalid signal packet queue.PlacePacket(PM4ReleaseMemoryPacket(m_FamilyId, false, 0, 0)); // Submit valid signal packet queue.PlacePacket(PM4ReleaseMemoryPacket(m_FamilyId, false, m_pHsaEvent->EventData.HWData2, m_pHsaEvent->EventId)); HSAuint64 startTime = GetSystemTickCountInMicroSec(); queue.SubmitPacket(); EXPECT_SUCCESS(hsaKmtWaitOnEvent(m_pHsaEvent, g_TestTimeOut)); duration[i] = GetSystemTickCountInMicroSec() - startTime; total += duration[i]; if (duration[i] < min) min = duration[i]; if (duration[i] > max) max = duration[i]; } double mean = (double)(total - min - max) / (REPS - 2); double variance = 0; bool skippedMin = false, skippedMax = false; HSAuint64 newMin = max, newMax = min; for (int i = 0; i < REPS; i++) { if (!skippedMin && duration[i] == min) { skippedMin = true; continue; } if (!skippedMax && duration[i] == max) { skippedMax = true; continue; } if (duration[i] < newMin) newMin = duration[i]; if (duration[i] > newMax) newMax = duration[i]; double diff = mean - duration[i]; variance += diff*diff; } variance /= REPS - 2; double stdDev = sqrt(variance); LOG() << "Time for event handling (min/avg/max [std.dev] in us) " << std::dec << newMin << "/" << mean << "/" << newMax << " [" << stdDev << "]\n"; EXPECT_SUCCESS(queue.Destroy()); for (int i = 0; i < EVENT_NUMBER; i++) EXPECT_SUCCESS(hsaKmtDestroyEvent(pHsaEvent[i])); TEST_END; } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDEventTest.hpp000066400000000000000000000032311446477712600246120ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDBaseComponentTest.hpp" #ifndef __KFD_EVENT_TEST__H__ #define __KFD_EVENT_TEST__H__ class KFDEventTest : public KFDBaseComponentTest { public: KFDEventTest(void) {} ~KFDEventTest(void) {} // @brief Executed before every test in KFDEventTest. virtual void SetUp(); // @brief Executed after every test in KFDEventTest. virtual void TearDown(); protected: static const unsigned int EVENT_TIMEOUT = 5000; // 5 seconds HsaEvent* m_pHsaEvent; }; #endif // __KFD_EVENT_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDEvictTest.cpp000066400000000000000000000461141446477712600246050ustar00rootroot00000000000000/* * Copyright (C) 2017-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include "KFDEvictTest.hpp" #include "PM4Queue.hpp" #include "PM4Packet.hpp" #include "SDMAPacket.hpp" #include "SDMAQueue.hpp" #include "Dispatch.hpp" #define N_PROCESSES (2) /* Number of processes running in parallel, must be at least 2 */ #define ALLOCATE_BUF_SIZE_MB (64) #define ALLOCATE_RETRY_TIMES (3) #define MAX_WAVEFRONTS (512) #define SDMA_NOP 0x0 void KFDEvictTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); ROUTINE_END } void KFDEvictTest::TearDown() { ROUTINE_START KFDBaseComponentTest::TearDown(); ROUTINE_END } void KFDEvictTest::AllocBuffers(HSAuint32 defaultGPUNode, HSAuint32 count, HSAuint64 vramBufSize, std::vector &pBuffers) { HSAuint64 totalMB; totalMB = N_PROCESSES*count*(vramBufSize>>20); if (m_IsParent) { LOG() << "Allocating " << N_PROCESSES << "*" << count << "*" << (vramBufSize>>20) << "(=" << totalMB << ")MB VRAM in KFD" << std::endl; } HsaMemMapFlags mapFlags = {0}; HSAKMT_STATUS ret; HSAuint32 retry = 0; m_Flags.Value = 0; m_Flags.ui32.PageSize = HSA_PAGE_SIZE_4KB; m_Flags.ui32.HostAccess = 0; m_Flags.ui32.NonPaged = 1; for (HSAuint32 i = 0; i < count; ) { ret = hsaKmtAllocMemory(defaultGPUNode, vramBufSize, m_Flags, &m_pBuf); if (ret == HSAKMT_STATUS_SUCCESS) { if (is_dgpu()) { if (hsaKmtMapMemoryToGPUNodes(m_pBuf, vramBufSize, NULL, mapFlags, 1, reinterpret_cast(&defaultGPUNode)) == HSAKMT_STATUS_ERROR) { EXPECT_SUCCESS(hsaKmtFreeMemory(m_pBuf, vramBufSize)); LOG() << "Map failed for " << i << "/" << count << " buffer. Retrying allocation" << std::endl; goto retry; } } pBuffers.push_back(m_pBuf); i++; retry = 0; continue; } retry: if (retry++ > ALLOCATE_RETRY_TIMES) { break; } /* Wait for 1 second to try allocate again */ sleep(1); } } void KFDEvictTest::FreeBuffers(std::vector &pBuffers, HSAuint64 vramBufSize) { for (HSAuint32 i = 0; i < pBuffers.size(); i++) { m_pBuf = pBuffers[i]; if (m_pBuf != NULL) { if (is_dgpu()) EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(m_pBuf)); EXPECT_SUCCESS(hsaKmtFreeMemory(m_pBuf, vramBufSize)); } } } void KFDEvictTest::AllocAmdgpuBo(int rn, HSAuint64 vramBufSize, amdgpu_bo_handle &handle) { struct amdgpu_bo_alloc_request alloc; alloc.alloc_size = vramBufSize / N_PROCESSES; alloc.phys_alignment = PAGE_SIZE; alloc.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM; alloc.flags = AMDGPU_GEM_CREATE_VRAM_CLEARED; if (m_IsParent) { LOG() << "Allocating " << N_PROCESSES << "*" << (vramBufSize >> 20) / N_PROCESSES << "(=" << (vramBufSize >> 20) << ")MB VRAM in GFX" << std::endl; } ASSERT_EQ(0, amdgpu_bo_alloc(m_RenderNodes[rn].device_handle, &alloc, &handle)); } void KFDEvictTest::FreeAmdgpuBo(amdgpu_bo_handle handle) { ASSERT_EQ(0, amdgpu_bo_free(handle)); } static int amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size, unsigned alignment, unsigned heap, uint64_t flags, amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address, amdgpu_va_handle *va_handle) { struct amdgpu_bo_alloc_request request = {}; amdgpu_bo_handle buf_handle; amdgpu_va_handle handle; uint64_t vmc_addr; int r; request.alloc_size = size; request.phys_alignment = alignment; request.preferred_heap = heap; request.flags = flags; r = amdgpu_bo_alloc(dev, &request, &buf_handle); if (r) return r; r = amdgpu_va_range_alloc(dev, amdgpu_gpu_va_range_general, size, alignment, 0, &vmc_addr, &handle, 0); if (r) goto error_va_alloc; r = amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_MAP); if (r) goto error_va_map; r = amdgpu_bo_cpu_map(buf_handle, cpu); if (r) goto error_cpu_map; *bo = buf_handle; *mc_address = vmc_addr; *va_handle = handle; return 0; error_cpu_map: amdgpu_bo_cpu_unmap(buf_handle); error_va_map: amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP); error_va_alloc: amdgpu_bo_free(buf_handle); return r; } static inline int amdgpu_bo_unmap_and_free(amdgpu_bo_handle bo, amdgpu_va_handle va_handle, uint64_t mc_addr, uint64_t size) { amdgpu_bo_cpu_unmap(bo); amdgpu_bo_va_op(bo, 0, size, mc_addr, 0, AMDGPU_VA_OP_UNMAP); amdgpu_va_range_free(va_handle); amdgpu_bo_free(bo); return 0; } static inline int amdgpu_get_bo_list(amdgpu_device_handle dev, amdgpu_bo_handle bo1, amdgpu_bo_handle bo2, amdgpu_bo_list_handle *list) { amdgpu_bo_handle resources[] = {bo1, bo2}; return amdgpu_bo_list_create(dev, bo2 ? 2 : 1, resources, NULL, list); } void KFDEvictTest::AmdgpuCommandSubmissionSdmaNop(int rn, amdgpu_bo_handle handle, PM4Queue *computeQueue = NULL) { amdgpu_context_handle contextHandle; amdgpu_bo_handle ibResultHandle; void *ibResultCpu; uint64_t ibResultMcAddress; struct amdgpu_cs_request ibsRequest; struct amdgpu_cs_ib_info ibInfo; struct amdgpu_cs_fence fenceStatus; amdgpu_bo_list_handle boList; amdgpu_va_handle vaHandle; uint32_t *ptr; uint32_t expired; unsigned failCount = 0; ASSERT_EQ(0, amdgpu_cs_ctx_create(m_RenderNodes[rn].device_handle, &contextHandle)); ASSERT_EQ(0, amdgpu_bo_alloc_and_map(m_RenderNodes[rn].device_handle, PAGE_SIZE, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 0, &ibResultHandle, &ibResultCpu, &ibResultMcAddress, &vaHandle)); ASSERT_EQ(0, amdgpu_get_bo_list(m_RenderNodes[rn].device_handle, ibResultHandle, handle, &boList)); /* Fill Nop cammands in IB */ ptr = reinterpret_cast(ibResultCpu); for (int i = 0; i < 16; i++) ptr[i] = SDMA_NOP; memset(&ibInfo, 0, sizeof(struct amdgpu_cs_ib_info)); ibInfo.ib_mc_address = ibResultMcAddress; ibInfo.size = 16; memset(&ibsRequest, 0, sizeof(struct amdgpu_cs_request)); ibsRequest.ip_type = AMDGPU_HW_IP_DMA; ibsRequest.ring = 0; ibsRequest.number_of_ibs = 1; ibsRequest.ibs = &ibInfo; ibsRequest.resources = boList; ibsRequest.fence_info.handle = NULL; memset(&fenceStatus, 0, sizeof(struct amdgpu_cs_fence)); for (int i = 0; i < 100; i++) { int r = amdgpu_cs_submit(contextHandle, 0, &ibsRequest, 1); Delay(50); if (r) { failCount++; ASSERT_LE(failCount, 2); continue; } fenceStatus.context = contextHandle; fenceStatus.ip_type = AMDGPU_HW_IP_DMA; fenceStatus.ip_instance = 0; fenceStatus.ring = 0; fenceStatus.fence = ibsRequest.seq_no; EXPECT_EQ(0, amdgpu_cs_query_fence_status(&fenceStatus, g_TestTimeOut*1000000, 0, &expired)); if (!expired) WARN() << "CS did not signal completion" << std::endl; /* If a compute queue is given, submit a short compute job * every 16 loops (about once a second). If the process was * evicted, restore can take quite long. */ if (computeQueue && (i & 0xf) == 0) { computeQueue->PlaceAndSubmitPacket(PM4NopPacket()); computeQueue->Wait4PacketConsumption(NULL, 10000); } } EXPECT_EQ(0, amdgpu_bo_list_destroy(boList)); EXPECT_EQ(0, amdgpu_bo_unmap_and_free(ibResultHandle, vaHandle, ibResultMcAddress, PAGE_SIZE)); EXPECT_EQ(0, amdgpu_cs_ctx_free(contextHandle)); } /* Evict and restore procedure basic test * * Use N_PROCESSES processes to allocate vram buf size larger than total vram size * * ALLOCATE_BUF_SIZE_MB buf allocation size * * buf is equal to (vramSizeMB / (vramBufSizeMB * N_PROCESSES) ) + 8 * Total vram all processes allocated: 8GB for 4GB Fiji, and 20GB for 16GB Vega10 * * Eviction and restore will happen many times: * ttm will evict buffers of another process if there is not enough free vram * process restore will evict buffers of another process * * Sometimes the allocation may fail (maybe that is normal) * ALLOCATE_RETRY_TIMES max retry times to allocate * * This is basic test with no queue, so vram is not used by the GPU during test * * TODO: * - Synchronization between the processes, so they know for sure when * they are done allocating memory */ TEST_F(KFDEvictTest, BasicTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HSAuint64 vramBufSize = ALLOCATE_BUF_SIZE_MB * 1024 * 1024; HSAuint64 vramSize = GetVramSize(defaultGPUNode); HSAuint64 sysMemSize = GetSysMemSize(); if (!vramSize) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } if (m_NodeInfo.IsAppAPU(defaultGPUNode)) { LOG() << "Skipping test on AppAPU." << std::endl; return; } LOG() << "Found VRAM of " << std::dec << (vramSize >> 20) << "MB" << std::endl; LOG() << "Found System RAM of " << std::dec << (sysMemSize >> 20) << "MB" << std::endl; // Use 7/8 of VRAM between all processes HSAuint64 testSize = vramSize * 7 / 8; HSAuint32 count = testSize / (vramBufSize * N_PROCESSES); if (count == 0) { LOG() << "Skipping test: Not enough system memory available." << std::endl; return; } /* Fork the child processes */ ForkChildProcesses(N_PROCESSES); int rn = FindDRMRenderNode(defaultGPUNode); if (rn < 0) { LOG() << "Skipping test: Could not find render node for default GPU." << std::endl; WaitChildProcesses(); return; } std::vector pBuffers; AllocBuffers(defaultGPUNode, count, vramBufSize, pBuffers); /* Allocate gfx vram size of at most one third system memory */ HSAuint64 size = sysMemSize / 3 < testSize / 2 ? sysMemSize / 3 : testSize / 2; amdgpu_bo_handle handle; AllocAmdgpuBo(rn, size, handle); AmdgpuCommandSubmissionSdmaNop(rn, handle); FreeAmdgpuBo(handle); LOG() << m_psName << "free buffer" << std::endl; FreeBuffers(pBuffers, vramBufSize); WaitChildProcesses(); TEST_END } /* Evict and restore queue test * * N_PROCESSES processes read all local buffers in parallel while buffers are evicted and restored * If GPU vm page fault happens, then test shader will stop and failed to write specific value * at dest buffer. Test will report failed. * * Steps: * - fork N_PROCESSES processes, each process does the same below * - allocate local buffers, each buffer size is 64MB * - allocate zero initialized host access address buffer and result buffer * address buffer to pass address of local buffers to shader * result buffer to store shader output result * - submit queue to run ReadMemory shader * - shader start m_DimX wavefronts, each wavefront keep reading one local buffer * - notify shader to quit * - check result buffer with specific value to confirm all wavefronts quit normally */ TEST_F(KFDEvictTest, QueueTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL) HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; unsigned int count = MAX_WAVEFRONTS; const HsaNodeProperties *pNodeProperties = m_NodeInfo.HsaDefaultGPUNodeProperties(); /* Skip test for chip if it doesn't have CWSR, which the test depends on */ if (m_FamilyId < FAMILY_VI || isTonga(pNodeProperties)) { LOG() << std::hex << "Skipping test: No CWSR present for family ID 0x" << m_FamilyId << "." << std::endl; return; } if (m_NodeInfo.IsAppAPU(defaultGPUNode)) { LOG() << "Skipping test on AppAPU." << std::endl; return; } HSAuint32 i; HSAuint64 vramSize = GetVramSize(defaultGPUNode); HSAuint64 sysMemSize = GetSysMemSize(); if (!vramSize) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } LOG() << "Found VRAM of " << std::dec << (vramSize >> 20) << "MB" << std::endl; LOG() << "Found System RAM of " << std::dec << (sysMemSize >> 20) << "MB" << std::endl; // Use 7/8 of VRAM between all processes HSAuint64 testSize = vramSize * 7 / 8; HSAuint32 vramBufSize = testSize / (count * N_PROCESSES); vramBufSize = (vramBufSize / (1024 * 1024)) * (1024 * 1024); if (vramBufSize == 0) { LOG() << "Skipping test: Not enough system memory available." << std::endl; return; } /* Assert all buffer address can be stored within one page * because only one page host memory srcBuf is allocated */ ASSERT_LE(count, PAGE_SIZE/sizeof(unsigned int *)); /* Fork the child processes */ ForkChildProcesses(N_PROCESSES); int rn = FindDRMRenderNode(defaultGPUNode); if (rn < 0) { LOG() << "Skipping test: Could not find render node for default GPU." << std::endl; WaitChildProcesses(); return; } HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer addrBuffer(PAGE_SIZE, defaultGPUNode); HsaMemoryBuffer resultBuffer(PAGE_SIZE, defaultGPUNode); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(ReadMemoryIsa, isaBuffer.As())); PM4Queue pm4Queue; ASSERT_SUCCESS(pm4Queue.Create(defaultGPUNode)); Dispatch dispatch0(isaBuffer); std::vector pBuffers; AllocBuffers(defaultGPUNode, count, vramBufSize, pBuffers); /* Allocate gfx vram size of at most one third system memory */ HSAuint64 size = sysMemSize / 3 < testSize / 2 ? sysMemSize / 3 : testSize / 2; amdgpu_bo_handle handle; AllocAmdgpuBo(rn, size, handle); unsigned int wavefront_num = pBuffers.size(); LOG() << m_psName << "wavefront number " << wavefront_num << std::endl; void **localBufAddr = addrBuffer.As(); unsigned int *result = resultBuffer.As(); for (i = 0; i < wavefront_num; i++) *(localBufAddr + i) = pBuffers[i]; for (i = 0; i < wavefront_num; i++) *(result + i) = vramBufSize; dispatch0.SetArgs(localBufAddr, result); dispatch0.SetDim(wavefront_num, 1, 1); /* Submit the packet and start shader */ dispatch0.Submit(pm4Queue); AmdgpuCommandSubmissionSdmaNop(rn, handle); /* Uncomment this line for debugging */ // LOG() << m_psName << "notify shader to quit" << std::endl; /* Fill address buffer so shader quits */ addrBuffer.Fill(0x5678); /* Wait for shader to finish or timeout if shader has vm page fault */ EXPECT_EQ(0, dispatch0.SyncWithStatus(180000)); EXPECT_SUCCESS(pm4Queue.Destroy()); FreeAmdgpuBo(handle); /* Uncomment this line for debugging */ // LOG() << m_psName << "free buffer" << std::endl; /* Cleanup */ FreeBuffers(pBuffers, vramBufSize); /* Check if all wavefronts finished successfully */ for (i = 0; i < wavefront_num; i++) EXPECT_EQ(0x5678, *(result + i)); WaitChildProcesses(); TEST_END } /* Evict a queue running in bursts, so that the process has a chance * to be idle when restored but the queue needs to resume to perform * more work later. This test is designed to stress the idle process * eviction optimization in KFD that leaves idle processes evicted * until the next time the doorbell page is accessed. */ TEST_F(KFDEvictTest, BurstyTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HSAuint64 vramBufSize = ALLOCATE_BUF_SIZE_MB * 1024 * 1024; if (m_NodeInfo.IsAppAPU(defaultGPUNode)) { LOG() << "Skipping test on AppAPU." << std::endl; return; } HSAuint64 vramSize = GetVramSize(defaultGPUNode); HSAuint64 sysMemSize = GetSysMemSize(); if (!vramSize) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } LOG() << "Found VRAM of " << std::dec << (vramSize >> 20) << "MB" << std::endl; LOG() << "Found System RAM of " << std::dec << (sysMemSize >> 20) << "MB" << std::endl; // Use 7/8 of VRAM between all processes HSAuint64 testSize = vramSize * 7 / 8; HSAuint32 count = testSize / (vramBufSize * N_PROCESSES); if (count == 0) { LOG() << "Skipping test: Not enough system memory available." << std::endl; return; } /* Fork the child processes */ ForkChildProcesses(N_PROCESSES); int rn = FindDRMRenderNode(defaultGPUNode); if (rn < 0) { LOG() << "Skipping test: Could not find render node for default GPU." << std::endl; WaitChildProcesses(); return; } PM4Queue pm4Queue; ASSERT_SUCCESS(pm4Queue.Create(defaultGPUNode)); std::vector pBuffers; AllocBuffers(defaultGPUNode, count, vramBufSize, pBuffers); /* Allocate gfx vram size of at most one third system memory */ HSAuint64 size = sysMemSize / 3 < testSize / 2 ? sysMemSize / 3 : testSize / 2; amdgpu_bo_handle handle; AllocAmdgpuBo(rn, size, handle); AmdgpuCommandSubmissionSdmaNop(rn, handle, &pm4Queue); FreeAmdgpuBo(handle); LOG() << m_psName << "free buffer" << std::endl; FreeBuffers(pBuffers, vramBufSize); EXPECT_SUCCESS(pm4Queue.Destroy()); WaitChildProcesses(); TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDEvictTest.hpp000066400000000000000000000042171446477712600246100ustar00rootroot00000000000000/* * Copyright (C) 2017-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_EVICT_TEST__H__ #define __KFD_EVICT_TEST__H__ #include #include #include "KFDMultiProcessTest.hpp" #include "PM4Queue.hpp" // @class KFDEvictTest // Test eviction and restore procedure using two processes class KFDEvictTest : public KFDMultiProcessTest { public: KFDEvictTest(void) {} ~KFDEvictTest(void) {} protected: virtual void SetUp(); virtual void TearDown(); void AllocBuffers(HSAuint32 defaultGPUNode, HSAuint32 count, HSAuint64 vramBufSize, std::vector &pBuffers); void FreeBuffers(std::vector &pBuffers, HSAuint64 vramBufSize); void AllocAmdgpuBo(int rn, HSAuint64 vramBufSize, amdgpu_bo_handle &handle); void FreeAmdgpuBo(amdgpu_bo_handle handle); void AmdgpuCommandSubmissionSdmaNop(int rn, amdgpu_bo_handle handle, PM4Queue *computeQueue); protected: // Members HsaMemFlags m_Flags; void* m_pBuf; }; #endif // __KFD_EVICT_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDExceptionTest.cpp000066400000000000000000000317711446477712600254740ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDExceptionTest.hpp" #include "PM4Queue.hpp" #include "PM4Packet.hpp" #include "SDMAPacket.hpp" #include "SDMAQueue.hpp" #include "Dispatch.hpp" #include void KFDExceptionTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); LOG() << "This Exception test might cause expected page fault " "error logs at kernel level." << std::endl; ROUTINE_END } void KFDExceptionTest::TearDown() { ROUTINE_START KFDBaseComponentTest::TearDown(); // WORKAROUND: This needs to be fixed in the kernel // Wait 500ms for the kernel to process any fault storms before the // next test to avoid reporting incorrect faults in the next test. Delay(500); ROUTINE_END } /* Test for memory exception. The function expects a Memory Fault to be * triggered by the GPU when it tries to copy dword from pSrc to pDst. * Should be called from a Child Process since the Memory Fault causes * all the queues to be halted. */ void KFDExceptionTest::TestMemoryException(int defaultGPUNode, HSAuint64 pSrc, HSAuint64 pDst, unsigned int dimX, unsigned int dimY, unsigned int dimZ) { PM4Queue queue; HsaEvent *vmFaultEvent; HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); HSAuint64 faultAddress, page_mask = ~((HSAuint64)PAGE_SIZE - 1); Dispatch dispatch(isaBuffer, false); HsaEventDescriptor eventDesc; eventDesc.EventType = HSA_EVENTTYPE_MEMORY; eventDesc.NodeId = defaultGPUNode; eventDesc.SyncVar.SyncVar.UserData = NULL; eventDesc.SyncVar.SyncVarSize = 0; ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); m_ChildStatus = queue.Create(defaultGPUNode); if (m_ChildStatus != HSAKMT_STATUS_SUCCESS) { WARN() << "Queue create failed" << std::endl; return; } m_ChildStatus = hsaKmtCreateEvent(&eventDesc, true, false, &vmFaultEvent); if (m_ChildStatus != HSAKMT_STATUS_SUCCESS) { WARN() << "Event create failed" << std::endl; goto queuefail; } dispatch.SetDim(dimX, dimY, dimZ); dispatch.SetArgs(reinterpret_cast(pSrc), reinterpret_cast(pDst)); dispatch.Submit(queue); m_ChildStatus = hsaKmtWaitOnEvent(vmFaultEvent, g_TestTimeOut); if (m_ChildStatus != HSAKMT_STATUS_SUCCESS) { WARN() << "Wait failed. No Exception triggered" << std::endl; goto eventfail; } if (vmFaultEvent->EventData.EventType != HSA_EVENTTYPE_MEMORY) { WARN() << "Unexpected Event Received " << vmFaultEvent->EventData.EventType << std::endl; m_ChildStatus = HSAKMT_STATUS_ERROR; goto eventfail; } faultAddress = vmFaultEvent->EventData.EventData.MemoryAccessFault.VirtualAddress; if (faultAddress != (pSrc & page_mask) && faultAddress != (pDst & page_mask) ) { WARN() << "Unexpected Fault Address " << faultAddress << " expected " << (pSrc & page_mask) << " or " << (pDst & page_mask) << std::endl; m_ChildStatus = HSAKMT_STATUS_ERROR; } eventfail: hsaKmtDestroyEvent(vmFaultEvent); queuefail: queue.Destroy(); } void KFDExceptionTest::TestSdmaException(int defaultGPUNode, void *pDst) { SDMAQueue queue; HsaEvent *vmFaultEvent; HSAuint64 faultAddress, page_mask = ~((HSAuint64)PAGE_SIZE - 1); HsaEventDescriptor eventDesc; eventDesc.EventType = HSA_EVENTTYPE_MEMORY; eventDesc.NodeId = defaultGPUNode; eventDesc.SyncVar.SyncVar.UserData = NULL; eventDesc.SyncVar.SyncVarSize = 0; m_ChildStatus = queue.Create(defaultGPUNode); if (m_ChildStatus != HSAKMT_STATUS_SUCCESS) { WARN() << "Queue create failed" << std::endl; return; } m_ChildStatus = hsaKmtCreateEvent(&eventDesc, true, false, &vmFaultEvent); if (m_ChildStatus != HSAKMT_STATUS_SUCCESS) { WARN() << "Event create failed" << std::endl; goto queuefail; } queue.PlaceAndSubmitPacket(SDMAWriteDataPacket(queue.GetFamilyId(), reinterpret_cast(pDst), 0x02020202)); m_ChildStatus = hsaKmtWaitOnEvent(vmFaultEvent, g_TestTimeOut); if (m_ChildStatus != HSAKMT_STATUS_SUCCESS) { WARN() << "Wait failed. No Exception triggered" << std::endl; goto eventfail; } if (vmFaultEvent->EventData.EventType != HSA_EVENTTYPE_MEMORY) { WARN() << "Unexpected Event Received " << vmFaultEvent->EventData.EventType << std::endl; m_ChildStatus = HSAKMT_STATUS_ERROR; goto eventfail; } faultAddress = vmFaultEvent->EventData.EventData.MemoryAccessFault.VirtualAddress; if (faultAddress != ((HSAuint64)pDst & page_mask) ) { WARN() << "Unexpected Fault Address " << faultAddress << " expected " << ((HSAuint64)pDst & page_mask) << std::endl; m_ChildStatus = HSAKMT_STATUS_ERROR; } eventfail: hsaKmtDestroyEvent(vmFaultEvent); queuefail: queue.Destroy(); } /* Test Bad Address access in a child process */ TEST_F(KFDExceptionTest, AddressFault) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId == FAMILY_RV) { LOG() << "Skipping test: IOMMU issues on Raven." << std::endl; return; } m_ChildPid = fork(); if (m_ChildPid == 0) { KFDBaseComponentTest::TearDown(); KFDBaseComponentTest::SetUp(); HsaMemoryBuffer srcBuffer(PAGE_SIZE, defaultGPUNode, false); srcBuffer.Fill(0xAA55AA55); TestMemoryException(defaultGPUNode, srcBuffer.As(), 0x12345678ULL); } else { int childStatus; waitpid(m_ChildPid, &childStatus, 0); if (is_dgpu()) { EXPECT_EQ(WIFEXITED(childStatus), true); EXPECT_EQ(WEXITSTATUS(childStatus), HSAKMT_STATUS_SUCCESS); } else { EXPECT_EQ(WIFSIGNALED(childStatus), true); EXPECT_EQ(WTERMSIG(childStatus), SIGSEGV); } } TEST_END } /* Allocate Read Only buffer. Test Memory Exception failure by * attempting to write to that buffer in the child process. */ TEST_F(KFDExceptionTest, PermissionFault) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId == FAMILY_RV) { LOG() << "Skipping test: IOMMU issues on Raven." << std::endl; return; } m_ChildPid = fork(); if (m_ChildPid == 0) { KFDBaseComponentTest::TearDown(); KFDBaseComponentTest::SetUp(); HsaMemoryBuffer readOnlyBuffer(PAGE_SIZE, defaultGPUNode, false /*zero*/, false /*isLocal*/, true /*isExec*/, false /*isScratch*/, true /*isReadOnly*/); HsaMemoryBuffer srcSysBuffer(PAGE_SIZE, defaultGPUNode, false); srcSysBuffer.Fill(0xAA55AA55); TestMemoryException(defaultGPUNode, srcSysBuffer.As(), readOnlyBuffer.As()); } else { int childStatus; waitpid(m_ChildPid, &childStatus, 0); if (is_dgpu()) { EXPECT_EQ(WIFEXITED(childStatus), true); EXPECT_EQ(WEXITSTATUS(childStatus), HSAKMT_STATUS_SUCCESS); } else { EXPECT_EQ(WIFSIGNALED(childStatus), true); EXPECT_EQ(WTERMSIG(childStatus), SIGSEGV); } } TEST_END } /* Allocate Read Only user pointer buffer. Test Memory Exception failure by * attempting to write to that buffer in the child process. */ TEST_F(KFDExceptionTest, PermissionFaultUserPointer) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId == FAMILY_RV) { LOG() << "Skipping test: IOMMU issues on Raven." << std::endl; return; } m_ChildPid = fork(); if (m_ChildPid == 0) { KFDBaseComponentTest::TearDown(); KFDBaseComponentTest::SetUp(); void *pBuf = mmap(NULL, PAGE_SIZE, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_NE(pBuf, MAP_FAILED); EXPECT_SUCCESS(hsaKmtRegisterMemory(pBuf, PAGE_SIZE)); EXPECT_SUCCESS(hsaKmtMapMemoryToGPU(pBuf, PAGE_SIZE, NULL)); HsaMemoryBuffer srcSysBuffer(PAGE_SIZE, defaultGPUNode, false); srcSysBuffer.Fill(0xAA55AA55); TestMemoryException(defaultGPUNode, srcSysBuffer.As(), (HSAuint64)pBuf); } else { int childStatus; waitpid(m_ChildPid, &childStatus, 0); if (is_dgpu()) { EXPECT_EQ(WIFEXITED(childStatus), true); EXPECT_EQ(WEXITSTATUS(childStatus), HSAKMT_STATUS_SUCCESS); } else { EXPECT_EQ(WIFSIGNALED(childStatus), true); EXPECT_EQ(WTERMSIG(childStatus), SIGSEGV); } } TEST_END } /* Test VM fault storm handling by copying to/from invalid pointers * with lots of work items at the same time */ TEST_F(KFDExceptionTest, FaultStorm) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId == FAMILY_RV) { LOG() << "Skipping test: IOMMU issues on Raven." << std::endl; return; } HSAKMT_STATUS status; m_ChildPid = fork(); if (m_ChildPid == 0) { KFDBaseComponentTest::TearDown(); KFDBaseComponentTest::SetUp(); TestMemoryException(defaultGPUNode, 0x12345678, 0x76543210, 1024, 1024, 1); } else { int childStatus; waitpid(m_ChildPid, &childStatus, 0); if (is_dgpu()) { EXPECT_EQ(WIFEXITED(childStatus), true); EXPECT_EQ(WEXITSTATUS(childStatus), HSAKMT_STATUS_SUCCESS); } else { EXPECT_EQ(WIFSIGNALED(childStatus), true); EXPECT_EQ(WTERMSIG(childStatus), SIGSEGV); } } TEST_END } /* */ TEST_F(KFDExceptionTest, SdmaQueueException) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId == FAMILY_RV) { LOG() << "Skipping test: IOMMU issues on Raven." << std::endl; return; } HSAKMT_STATUS status; m_ChildPid = fork(); if (m_ChildPid == 0) { unsigned int* pDb = NULL; unsigned int *nullPtr = NULL; KFDBaseComponentTest::TearDown(); KFDBaseComponentTest::SetUp(); m_MemoryFlags.ui32.NonPaged = 1; m_MemoryFlags.ui32.HostAccess = 0; ASSERT_SUCCESS(hsaKmtAllocMemory(defaultGPUNode, PAGE_SIZE, m_MemoryFlags, reinterpret_cast(&pDb))); // verify that pDb is not null before it's being used ASSERT_NE(nullPtr, pDb) << "hsaKmtAllocMemory returned a null pointer"; ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(pDb, PAGE_SIZE, NULL)); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(pDb)); TestSdmaException(defaultGPUNode, pDb); EXPECT_SUCCESS(hsaKmtFreeMemory(pDb, PAGE_SIZE)); } else { int childStatus; waitpid(m_ChildPid, &childStatus, 0); if (is_dgpu()) { EXPECT_EQ(WIFEXITED(childStatus), true); EXPECT_EQ(WEXITSTATUS(childStatus), HSAKMT_STATUS_SUCCESS); } else { EXPECT_EQ(WIFSIGNALED(childStatus), true); EXPECT_EQ(WTERMSIG(childStatus), SIGSEGV); } } TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDExceptionTest.hpp000066400000000000000000000047261446477712600255010ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_EXCEPTION_TEST__H__ #define __KFD_EXCEPTION_TEST__H__ #include #include "KFDBaseComponentTest.hpp" class KFDExceptionTest : public KFDBaseComponentTest { public: KFDExceptionTest() : m_ChildPid(-1) { /* Because there could be early return before m_ChildPid is set * by fork(), we should initialize m_ChildPid to a non-zero value * to avoid possible exit of the main process. */ } ~KFDExceptionTest() { /* exit() is necessary for the child process. Otherwise when the * child process finishes, gtest assumes the test has finished and * starts the next test while the parent is still active. */ if (m_ChildPid == 0) { if (!m_ChildStatus && HasFatalFailure()) m_ChildStatus = HSAKMT_STATUS_ERROR; exit(m_ChildStatus); } } protected: virtual void SetUp(); virtual void TearDown(); void TestMemoryException(int defaultGPUNode, HSAuint64 pSrc, HSAuint64 pDst, unsigned int dimX = 1, unsigned int dimY = 1, unsigned int dimZ = 1); void TestSdmaException(int defaultGPUNode, void *pDst); protected: // Members pid_t m_ChildPid; HSAKMT_STATUS m_ChildStatus; }; #endif // __KFD_EXCEPTION_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDGWSTest.cpp000066400000000000000000000071631446477712600241740ustar00rootroot00000000000000/* * Copyright (C) 2014-2019 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDGWSTest.hpp" #include "PM4Queue.hpp" #include "PM4Packet.hpp" #include "Dispatch.hpp" void KFDGWSTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); ROUTINE_END } void KFDGWSTest::TearDown() { ROUTINE_START KFDBaseComponentTest::TearDown(); ROUTINE_END } TEST_F(KFDGWSTest, Allocate) { TEST_START(TESTPROFILE_RUNALL); HSAuint32 firstGWS; PM4Queue queue; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; const HsaNodeProperties *pNodeProperties = m_NodeInfo.HsaDefaultGPUNodeProperties(); if (!pNodeProperties || !pNodeProperties->NumGws) { LOG() << "Skip test: GPU node doesn't support GWS" << std::endl; return; } ASSERT_SUCCESS(queue.Create(defaultGPUNode)); ASSERT_SUCCESS(hsaKmtAllocQueueGWS(queue.GetResource()->QueueId, pNodeProperties->NumGws,&firstGWS)); EXPECT_EQ(0, firstGWS); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDGWSTest, Semaphore) { TEST_START(TESTPROFILE_RUNALL); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; const HsaNodeProperties *pNodeProperties = m_NodeInfo.HsaDefaultGPUNodeProperties(); HSAuint32 firstGWS; HSAuint32 numResources = 1; PM4Queue queue; if (!pNodeProperties || !pNodeProperties->NumGws) { LOG() << "Skip test: GPU node doesn't support GWS" << std::endl; return; } HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer buffer(PAGE_SIZE, defaultGPUNode, true, false, false); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); ASSERT_SUCCESS(hsaKmtAllocQueueGWS(queue.GetResource()->QueueId, pNodeProperties->NumGws,&firstGWS)); EXPECT_EQ(0, firstGWS); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(GwsInitIsa, isaBuffer.As())); Dispatch dispatch0(isaBuffer); buffer.Fill(numResources, 0, 4); dispatch0.SetArgs(buffer.As(), NULL); dispatch0.Submit(queue); dispatch0.Sync(); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(GwsAtomicIncreaseIsa, isaBuffer.As())); Dispatch dispatch(isaBuffer); dispatch.SetArgs(buffer.As(), NULL); dispatch.SetDim(1024, 16, 16); dispatch.Submit(queue); dispatch.Sync(); EXPECT_EQ(1024*16*16+1, *buffer.As()); EXPECT_SUCCESS(queue.Destroy()); TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDGWSTest.hpp000066400000000000000000000027151446477712600241770ustar00rootroot00000000000000/* * Copyright (C) 2014-2019 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_GWS_TEST__H__ #define __KFD_GWS_TEST__H__ #include #include "KFDBaseComponentTest.hpp" class KFDGWSTest : public KFDBaseComponentTest { public: KFDGWSTest() {} ~KFDGWSTest() {} protected: virtual void SetUp(); virtual void TearDown(); }; #endif // __KFD_GWS_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDGraphicsInterop.cpp000066400000000000000000000206301446477712600257670ustar00rootroot00000000000000/* * Copyright (C) 2016-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDGraphicsInterop.hpp" #include "Dispatch.hpp" #include "PM4Queue.hpp" TEST_F(KFDGraphicsInterop, RegisterGraphicsHandle) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; const HsaNodeProperties *pNodeProps = m_NodeInfo.GetNodeProperties(defaultGPUNode); const HSAuint32 familyID = FamilyIdFromNode(pNodeProps); if (isTonga(pNodeProps)) { LOG() << "Skipping test: Tonga workaround in thunk returns incorrect allocation size." << std::endl; return; } HSAuint32 nodes[1] = {(uint32_t)defaultGPUNode}; const char metadata[] = "This data is really meta."; unsigned metadata_size = strlen(metadata)+1; int rn = FindDRMRenderNode(defaultGPUNode); if (rn < 0) { LOG() << "Skipping test: Could not find render node for default GPU node." << std::endl; return; } // Create the buffer with metadata and get a dmabuf handle to it struct amdgpu_bo_alloc_request alloc; amdgpu_bo_handle handle; if (familyID == FAMILY_CZ || isTonga(pNodeProps)) alloc.alloc_size = PAGE_SIZE * 8; else alloc.alloc_size = PAGE_SIZE; alloc.phys_alignment = PAGE_SIZE; alloc.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM; alloc.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; ASSERT_EQ(0, amdgpu_bo_alloc(m_RenderNodes[rn].device_handle, &alloc, &handle)); void *pCpuMap; ASSERT_EQ(0, amdgpu_bo_cpu_map(handle, &pCpuMap)); memset(pCpuMap, 0xaa, PAGE_SIZE); EXPECT_EQ(0, amdgpu_bo_cpu_unmap(handle)); struct amdgpu_bo_metadata meta; meta.flags = 0; meta.tiling_info = 0; meta.size_metadata = metadata_size; memcpy(meta.umd_metadata, metadata, metadata_size); EXPECT_EQ(0, amdgpu_bo_set_metadata(handle, &meta)); uint32_t dmabufFd; EXPECT_EQ(0, amdgpu_bo_export(handle, amdgpu_bo_handle_type_dma_buf_fd, &dmabufFd)); // Register it with HSA HsaGraphicsResourceInfo info; ASSERT_SUCCESS(hsaKmtRegisterGraphicsHandleToNodes(dmabufFd, &info, 1, nodes)); /* DMA buffer handle and GEM handle are no longer needed, KFD * should have taken a reference to the BO */ EXPECT_EQ(0, close(dmabufFd)); EXPECT_EQ(0, amdgpu_bo_free(handle)); // Check that buffer size and metadata match EXPECT_EQ(info.SizeInBytes, alloc.alloc_size); EXPECT_EQ(info.MetadataSizeInBytes, metadata_size); EXPECT_EQ(0, strcmp(metadata, (const char *)info.Metadata)); // Map the buffer ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(info.MemoryAddress, info.SizeInBytes, NULL)); // Copy contents to a system memory buffer for comparison HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); HsaMemoryBuffer dstBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/); PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); Dispatch dispatch(isaBuffer); dispatch.SetArgs(info.MemoryAddress, dstBuffer.As()); dispatch.Submit(queue); dispatch.Sync(g_TestTimeOut); EXPECT_SUCCESS(queue.Destroy()); EXPECT_EQ(dstBuffer.As()[0], 0xaaaaaaaa); // Test QueryMem before the cleanup HsaPointerInfo ptrInfo; EXPECT_SUCCESS(hsaKmtQueryPointerInfo((const void *)info.MemoryAddress, &ptrInfo)); EXPECT_EQ(ptrInfo.Type, HSA_POINTER_REGISTERED_GRAPHICS); EXPECT_EQ(ptrInfo.Node, (HSAuint32)defaultGPUNode); EXPECT_EQ(ptrInfo.GPUAddress, (HSAuint64)info.MemoryAddress); EXPECT_EQ(ptrInfo.SizeInBytes, alloc.alloc_size); EXPECT_EQ(ptrInfo.MemFlags.ui32.CoarseGrain, 1); // Cleanup EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(info.MemoryAddress)); EXPECT_SUCCESS(hsaKmtDeregisterMemory(info.MemoryAddress)); TEST_END } #if 0 /* This test isn't testing things the way we wanted it to. It is flaky and * will end up failing if the memory is evicted, which isn't possible for what * it is intended to test. It needs a rework */ /* Third-party device memory can be registered for GPU access in * ROCm stack. Test this feature. Third party device is mimicked * in multi-GPU system using Graphics stack (libdrm). CPU accessible * device memory is allocated using Graphics stack on gpuNode2 and * this memory will be registered on gpuNode1 for GPU access. */ TEST_F(KFDGraphicsInterop, RegisterForeignDeviceMem) { TEST_START(TESTPROFILE_RUNALL) if (!is_dgpu()) { LOG() << "Skipping test: Only supported on multi-dGPU system." << std::endl; return; } const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); if (gpuNodes.size() < 2) { LOG() << "Skipping test: At least two GPUs are required." << std::endl; return; } /* gpuNode2 must have public memory (large bar) to allocate CPU accessible * device memory. */ HSAint32 gpuNode1 = m_NodeInfo.HsaDefaultGPUNode(), gpuNode2 = 0; const HsaNodeProperties *pNodeProperties; gpuNode2 = m_NodeInfo.FindLargeBarGPUNode(); if (gpuNode2 < 0) { LOG() << "Skipping test: At least one large bar GPU is required." << std::endl; return; } if (gpuNode1 == gpuNode2) { for (unsigned i = 0; i < gpuNodes.size(); i++) { if (gpuNodes.at(i) != gpuNode2) { gpuNode1 = gpuNodes.at(i); break; } } } const HsaNodeProperties *pNodeProps = m_NodeInfo.GetNodeProperties(gpuNode2); const HSAuint32 familyID = FamilyIdFromNode(pNodeProps); int rn = FindDRMRenderNode(gpuNode2); if (rn < 0) { LOG() << "Skipping test: Cound not find render node for 2nd GPU." << std::endl; return; } // Allocate CPU accessible device memory on gpuNode2 struct amdgpu_bo_alloc_request alloc; amdgpu_bo_handle handle; if (familyID == FAMILY_CZ || isTonga(pNodeProps)) alloc.alloc_size = PAGE_SIZE * 8; else alloc.alloc_size = PAGE_SIZE; alloc.phys_alignment = PAGE_SIZE; alloc.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM; alloc.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; ASSERT_EQ(0, amdgpu_bo_alloc(m_RenderNodes[rn].device_handle, &alloc, &handle)); void *pCpuMap; ASSERT_EQ(0, amdgpu_bo_cpu_map(handle, &pCpuMap)); memset(pCpuMap, 0xAA, PAGE_SIZE); /* Register third-party device memory in KFD. Test GPU access * by carrying out a simple copy test */ HsaMemoryBuffer lockDeviceMemory(pCpuMap, PAGE_SIZE); HsaMemoryBuffer isaBuffer(PAGE_SIZE, gpuNode1, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer dstBuffer(PAGE_SIZE, gpuNode1, true/*zero*/); PM4Queue queue; Dispatch dispatch(isaBuffer); m_pIsaGen->GetCopyDwordIsa(isaBuffer); ASSERT_SUCCESS(queue.Create(gpuNode1)); dispatch.SetArgs(lockDeviceMemory.As(), dstBuffer.As()); dispatch.Submit(queue); dispatch.Sync(g_TestTimeOut); EXPECT_SUCCESS(queue.Destroy()); EXPECT_EQ(dstBuffer.As()[0], 0xAAAAAAAA); EXPECT_EQ(0, amdgpu_bo_cpu_unmap(handle)); EXPECT_EQ(0, amdgpu_bo_free(handle)); TEST_END } #endif ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDGraphicsInterop.hpp000066400000000000000000000027441446477712600260020ustar00rootroot00000000000000/* * Copyright (C) 2016-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDMemoryTest.hpp" #ifndef __KFD_GRAPHICS_INTEROP_TEST__H__ #define __KFD_GRAPHICS_INTEROP_TEST__H__ // @class KFDGraphicsInteropTest // Adds access to graphics device for interoperability testing class KFDGraphicsInterop : public KFDMemoryTest { public: KFDGraphicsInterop(void) {} ~KFDGraphicsInterop(void) {} }; #endif ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDHWSTest.cpp000066400000000000000000000105331446477712600241700ustar00rootroot00000000000000/* * Copyright (C) 2019 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDHWSTest.hpp" void KFDHWSTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); ROUTINE_END } void KFDHWSTest::TearDown() { ROUTINE_START KFDBaseComponentTest::TearDown(); ROUTINE_END } void KFDHWSTest::RunTest(unsigned nProcesses, unsigned nQueues, unsigned nLoops) { int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; unsigned q, l; bool timeout = false; /* Fork the child processes */ ForkChildProcesses(nProcesses); // Create queues PM4Queue *queues = new PM4Queue[nQueues]; for (q = 0; q < nQueues; q++) ASSERT_SUCCESS(queues[q].Create(defaultGPUNode)); // Create dispatch pointers. Each loop iteration creates fresh dispatches Dispatch **dispatch = new Dispatch*[nQueues]; for (q = 0; q < nQueues; q++) dispatch[q] = NULL; // Logging: Each process prints its index after each loop iteration, all in one line. std::ostream &log = LOG() << std::dec << "Process " << m_ProcessIndex << " starting." << std::endl; // Run work on all queues HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(NoopIsa, isaBuffer.As())); for (l = 0; l < nLoops; l++) { for (q = 0; q < nQueues; q++) { if (dispatch[q]) delete dispatch[q]; dispatch[q] = new Dispatch(isaBuffer); dispatch[q]->SetArgs(NULL, NULL); dispatch[q]->SetDim(1, 1, 1); dispatch[q]->Submit(queues[q]); } for (q = 0; q < nQueues; q++) { timeout = dispatch[q]->SyncWithStatus(g_TestTimeOut); if (timeout) goto timeout; } log << m_ProcessIndex; } timeout: log << std::endl; if (timeout) { WARN() << "Process " << m_ProcessIndex << " timeout." << std::endl; } else { LOG() << "Process " << m_ProcessIndex << " done. Waiting ..." << std::endl; // Wait here before destroying queues. If another process' queues // are soft-hanging, destroying queues can resolve the soft-hang // by changing the run list. Make sure the other process's // dispatches have a chance to time out first. Delay(g_TestTimeOut+1000); } // Destroy queues and dispatches. Destroying the queues first // ensures that the memory allocated by the Dispatch is no longer // accessed by the GPU. LOG() << "Process " << m_ProcessIndex << " cleaning up." << std::endl; for (q = 0; q < nQueues; q++) { EXPECT_SUCCESS(queues[q].Destroy()); if (dispatch[q]) delete dispatch[q]; } delete[] queues; delete[] dispatch; // This is after all the cleanup to avoid leaving any garbage // behind, but before WaitChildProcesses to ensure a child process // with a timeout exits with an error that can be detected by the // parent. ASSERT_FALSE(timeout); WaitChildProcesses(); } TEST_F(KFDHWSTest, MultiProcessOversubscribed) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); RunTest(3, 13, 40); TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDHWSTest.hpp000066400000000000000000000031011446477712600241660ustar00rootroot00000000000000/* * Copyright (C) 2019 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_HWS_TEST__H__ #define __KFD_HWS_TEST__H__ #include #include "PM4Queue.hpp" #include "KFDMultiProcessTest.hpp" #include "Dispatch.hpp" class KFDHWSTest : public KFDMultiProcessTest { public: KFDHWSTest() {} ~KFDHWSTest() {} protected: virtual void SetUp(); virtual void TearDown(); void RunTest(unsigned nProcesses, unsigned nQueues, unsigned nLoops); }; #endif // __KFD_QCM_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDIPCTest.cpp000066400000000000000000000202611446477712600241410ustar00rootroot00000000000000/* * Copyright (C) 2017-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDIPCTest.hpp" #include #include #include #include #include #include #include #include #include "PM4Queue.hpp" #include "PM4Packet.hpp" #include "SDMAQueue.hpp" #include "SDMAPacket.hpp" void KFDIPCTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); ROUTINE_END } void KFDIPCTest::TearDown() { ROUTINE_START KFDBaseComponentTest::TearDown(); ROUTINE_END } KFDIPCTest::~KFDIPCTest(void) { /* exit() is necessary for the child process. Otherwise when the * child process finishes, gtest assumes the test has finished and * starts the next test while the parent is still active. */ if (m_ChildPid == 0) exit(::testing::UnitTest::GetInstance()->current_test_info()->result()->Failed()); } /* Import shared Local Memory from parent process. Check for the pattern * filled in by the parent process. Then fill a new pattern. * * Check import handle has same HsaMemFlags as export handle to verify thunk and KFD * import export handle ioctl pass HsaMemFlags correctly. */ void KFDIPCTest::BasicTestChildProcess(int defaultGPUNode, int *pipefd, HsaMemFlags mflags) { /* Open KFD device for child process. This needs to called before * any memory definitions */ TearDown(); SetUp(); SDMAQueue sdmaQueue; HsaSharedMemoryHandle sharedHandleLM; HSAuint64 size = PAGE_SIZE, sharedSize; HsaMemoryBuffer tempSysBuffer(size, defaultGPUNode, false); HSAuint32 *sharedLocalBuffer = NULL; HsaMemMapFlags mapFlags = {0}; /* Read from Pipe the shared Handle. Import shared Local Memory */ ASSERT_GE(read(pipefd[0], reinterpret_cast(&sharedHandleLM), sizeof(sharedHandleLM)), 0); ASSERT_SUCCESS(hsaKmtRegisterSharedHandle(&sharedHandleLM, reinterpret_cast(&sharedLocalBuffer), &sharedSize)); ASSERT_SUCCESS(hsaKmtMapMemoryToGPUNodes(sharedLocalBuffer, sharedSize, NULL, mapFlags, 1, reinterpret_cast(&defaultGPUNode))); /* Check for pattern in the shared Local Memory */ ASSERT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); size = size < sharedSize ? size : sharedSize; sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), tempSysBuffer.As(), sharedLocalBuffer, size)); sdmaQueue.Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(tempSysBuffer.As(), 0xAAAAAAAA)); /* Fill in the Local Memory with different pattern */ sdmaQueue.PlaceAndSubmitPacket(SDMAWriteDataPacket(sdmaQueue.GetFamilyId(), sharedLocalBuffer, 0xBBBBBBBB)); sdmaQueue.Wait4PacketConsumption(); HsaPointerInfo ptrInfo; EXPECT_SUCCESS(hsaKmtQueryPointerInfo(sharedLocalBuffer, &ptrInfo)); EXPECT_EQ(ptrInfo.Type, HSA_POINTER_REGISTERED_SHARED); EXPECT_EQ(ptrInfo.Node, (HSAuint32)defaultGPUNode); EXPECT_EQ(ptrInfo.GPUAddress, (HSAuint64)sharedLocalBuffer); EXPECT_EQ(ptrInfo.SizeInBytes, sharedSize); EXPECT_EQ(ptrInfo.MemFlags.Value, mflags.Value); /* Clean up */ EXPECT_SUCCESS(sdmaQueue.Destroy()); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(sharedLocalBuffer)); EXPECT_SUCCESS(hsaKmtDeregisterMemory(sharedLocalBuffer)); } /* Fill a pattern into Local Memory and share with the child process. * Then wait until Child process to exit and check for the new pattern * filled in by the child process. */ void KFDIPCTest::BasicTestParentProcess(int defaultGPUNode, pid_t cpid, int *pipefd, HsaMemFlags mflags) { HSAuint64 size = PAGE_SIZE, sharedSize; int status; HSAuint64 AlternateVAGPU; void *toShareLocalBuffer; HsaMemoryBuffer tempSysBuffer(PAGE_SIZE, defaultGPUNode, false); SDMAQueue sdmaQueue; HsaSharedMemoryHandle sharedHandleLM; HsaMemMapFlags mapFlags = {0}; ASSERT_SUCCESS(hsaKmtAllocMemory(defaultGPUNode, size, mflags, &toShareLocalBuffer)); /* Fill a Local Buffer with a pattern */ ASSERT_SUCCESS(hsaKmtMapMemoryToGPUNodes(toShareLocalBuffer, size, &AlternateVAGPU, mapFlags, 1, reinterpret_cast(&defaultGPUNode))); tempSysBuffer.Fill(0xAAAAAAAA); /* Copy pattern in Local Memory before sharing it */ ASSERT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), toShareLocalBuffer, tempSysBuffer.As(), size)); sdmaQueue.Wait4PacketConsumption(); /* Share it with the child process */ ASSERT_SUCCESS(hsaKmtShareMemory(toShareLocalBuffer, size, &sharedHandleLM)); ASSERT_GE(write(pipefd[1], reinterpret_cast(&sharedHandleLM), sizeof(sharedHandleLM)), 0); /* Wait for the child to finish */ waitpid(cpid, &status, 0); EXPECT_EQ(WIFEXITED(status), 1); EXPECT_EQ(WEXITSTATUS(status), 0); /* Check for the new pattern filled in by child process */ sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), tempSysBuffer.As(), toShareLocalBuffer, size)); sdmaQueue.Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(tempSysBuffer.As(), 0xBBBBBBBB)); /* Clean up */ EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(toShareLocalBuffer)); EXPECT_SUCCESS(sdmaQueue.Destroy()); } /* Test IPC memory. * 1. Parent Process [Create/Fill] LocalMemory (LM) --share--> Child Process * 2. Child Process import LM and check for the pattern. * 3. Child Process fill in a new pattern and quit. * 4. Parent Process wait for the Child process to finish and then check for * the new pattern in LM * * IPC support is limited to Local Memory. */ TEST_F(KFDIPCTest, BasicTest) { TEST_START(TESTPROFILE_RUNALL) const std::vector& GpuNodes = m_NodeInfo.GetNodesWithGPU(); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); int pipefd[2]; HsaMemFlags mflags = {0}; ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (!GetVramSize(defaultGPUNode)) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } /* Test libhsakmt fork() clean up by defining some buffers. These * buffers gets duplicated in the child process but not are not valid * as it doesn't have proper mapping in GPU. The clean up code in libhsakmt * should handle it */ volatile HSAuint32 stackData[1]; HsaMemoryBuffer tmpSysBuffer(PAGE_SIZE, defaultGPUNode, false); HsaMemoryBuffer tmpUserptrBuffer((void *)&stackData[0], sizeof(HSAuint32)); /* Create Pipes for communicating shared handles */ ASSERT_EQ(pipe(pipefd), 0); /* Create a child process and share the above Local Memory with it */ mflags.ui32.NonPaged = 1; mflags.ui32.CoarseGrain = 1; m_ChildPid = fork(); if (m_ChildPid == 0) BasicTestChildProcess(defaultGPUNode, pipefd, mflags); /* Child Process */ else BasicTestParentProcess(defaultGPUNode, m_ChildPid, pipefd, mflags); /* Parent proces */ /* Code path executed by both parent and child with respective fds */ close(pipefd[1]); close(pipefd[0]); TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDIPCTest.hpp000066400000000000000000000111041446477712600241420ustar00rootroot00000000000000/* * Copyright (C) 2017-2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDBaseComponentTest.hpp" #include "BaseQueue.hpp" #ifndef __KFD_MEMORY_TEST__H__ #define __KFD_MEMORY_TEST__H__ #define CMA_MEMORY_TEST_ARRAY_SIZE 4 #define CMA_TEST_COUNT 3 enum CMA_MEM_TYPE { CMA_MEM_TYPE_SYSTEM = 0, CMA_MEM_TYPE_USERPTR, CMA_MEM_TYPE_LOCAL_MEM, }; enum CMA_TEST_TYPE { CMA_READ_TEST = 0, CMA_WRITE_TEST }; enum CMA_TEST_STATUS { CMA_TEST_SUCCESS = 0, CMA_IPC_PIPE_ERROR = 1, CMA_CHECK_PATTERN_ERROR, CMA_TEST_ABORT, CMA_TEST_NOMEM, CMA_PARENT_FAIL, CMA_TEST_HSA_READ_FAIL, CMA_TEST_HSA_WRITE_FAIL }; /* @struct testMemoryDescriptor * @brief Describes test buffers for Cross Memory Attach Test. */ struct testMemoryDescriptor { CMA_MEM_TYPE m_MemType; HSAuint64 m_MemSize; /* The buffer will be initialized with this pattern */ HSAuint32 m_FillPattern; /* After CMA test, this pattern is expected in the first word */ HSAuint32 m_CheckFirstWordPattern; /* After CMA test, this pattern is expected in the last word */ HSAuint32 m_CheckLastWordPattern; testMemoryDescriptor(CMA_MEM_TYPE memType, HSAuint64 memSize, HSAuint32 fillPattern, HSAuint32 firstCheckPattern, HSAuint32 lastCheckPattern) : m_MemType(memType), m_MemSize(memSize), m_FillPattern(fillPattern), m_CheckFirstWordPattern(firstCheckPattern), m_CheckLastWordPattern(lastCheckPattern) {} ~testMemoryDescriptor(){} }; /* @class KFDCMAArray * @brief Array of buffers that will be passed between the parent and child * process for Cross memory read and write tests */ class KFDCMAArray { /* Used to store the actual buffer array */ HsaMemoryBuffer* m_MemArray[CMA_MEMORY_TEST_ARRAY_SIZE]; /* Used for passing to thunk CMA functions */ HsaMemoryRange m_HsaMemoryRange[CMA_MEMORY_TEST_ARRAY_SIZE]; /* Though previous arrays are fixed sizes only m_ValidCount * ones are valid */ HSAuint64 m_ValidCount; QueueArray m_QueueArray; public: KFDCMAArray(); ~KFDCMAArray() { Destroy(); } CMA_TEST_STATUS Init(testMemoryDescriptor(*memDescriptor)[CMA_MEMORY_TEST_ARRAY_SIZE], int node); CMA_TEST_STATUS Destroy(); HsaMemoryRange* getMemoryRange() { return m_HsaMemoryRange; } HSAuint64 getValidRangeCount() { return m_ValidCount; } void FillPattern(testMemoryDescriptor(*memDescriptor)[CMA_MEMORY_TEST_ARRAY_SIZE]); CMA_TEST_STATUS checkPattern(testMemoryDescriptor(*memDescriptor)[CMA_MEMORY_TEST_ARRAY_SIZE]); CMA_TEST_STATUS sendCMAArray(int writePipe); CMA_TEST_STATUS recvCMAArray(int readPipe); }; // @class KFDIPCTest class KFDIPCTest : public KFDBaseComponentTest { public: KFDIPCTest(void) : m_ChildPid(-1) {} ~KFDIPCTest(void); protected: virtual void SetUp(); virtual void TearDown(); /* For IPC testing */ void BasicTestChildProcess(int defaultGPUNode, int *pipefd, HsaMemFlags mflags); void BasicTestParentProcess(int defaultGPUNode, pid_t childPid, int *pipefd, HsaMemFlags mflags); /* For CMA testing */ CMA_TEST_STATUS CrossMemoryAttachChildProcess(int defaultGPUNode, int writePipe, int readPipe, CMA_TEST_TYPE testType); CMA_TEST_STATUS CrossMemoryAttachParentProcess(int defaultGPUNode, pid_t cid, int writePipe, int readPipe, CMA_TEST_TYPE testType); protected: pid_t m_ChildPid; }; #endif // __KFD_MEMORY_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDLocalMemoryTest.cpp000066400000000000000000000520501446477712600257520ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDLocalMemoryTest.hpp" #include "PM4Queue.hpp" #include "PM4Packet.hpp" #include "SDMAPacket.hpp" #include "SDMAQueue.hpp" #include "Dispatch.hpp" void KFDLocalMemoryTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); ROUTINE_END } void KFDLocalMemoryTest::TearDown() { ROUTINE_START KFDBaseComponentTest::TearDown(); ROUTINE_END } TEST_F(KFDLocalMemoryTest, AccessLocalMem) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; /* Skip test if not on dGPU path, which the test depends on */ if (!is_dgpu()) { LOG() << "Not dGPU path, skipping the test" << std::endl; return; } //local memory HsaMemoryBuffer destBuf(PAGE_SIZE, defaultGPUNode, false, true); HsaEvent *event; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &event)); PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); queue.PlaceAndSubmitPacket(PM4WriteDataPacket(destBuf.As(), 0, 0)); queue.Wait4PacketConsumption(event); hsaKmtDestroyEvent(event); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDLocalMemoryTest, BasicTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); PM4Queue queue; HSAuint64 AlternateVAGPU; unsigned int BufferSize = PAGE_SIZE; HsaMemMapFlags mapFlags = {0}; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (!GetVramSize(defaultGPUNode)) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode); HsaMemoryBuffer srcSysBuffer(BufferSize, defaultGPUNode, false); HsaMemoryBuffer destSysBuffer(BufferSize, defaultGPUNode); HsaMemoryBuffer srcLocalBuffer(BufferSize, defaultGPUNode, false, true); HsaMemoryBuffer dstLocalBuffer(BufferSize, defaultGPUNode, false, true); srcSysBuffer.Fill(0x01010101); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); ASSERT_SUCCESS(hsaKmtMapMemoryToGPUNodes(srcLocalBuffer.As(), srcLocalBuffer.Size(), &AlternateVAGPU, mapFlags, 1, reinterpret_cast(&defaultGPUNode))); ASSERT_SUCCESS(hsaKmtMapMemoryToGPUNodes(dstLocalBuffer.As(), dstLocalBuffer.Size(), &AlternateVAGPU, mapFlags, 1, reinterpret_cast(&defaultGPUNode))); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); queue.SetSkipWaitConsump(0); Dispatch dispatch(isaBuffer); dispatch.SetArgs(srcSysBuffer.As(), srcLocalBuffer.As()); dispatch.Submit(queue); dispatch.Sync(g_TestTimeOut); dispatch.SetArgs(srcLocalBuffer.As(), dstLocalBuffer.As()); dispatch.Submit(queue); dispatch.Sync(g_TestTimeOut); dispatch.SetArgs(dstLocalBuffer.As(), destSysBuffer.As()); dispatch.Submit(queue); dispatch.Sync(g_TestTimeOut); EXPECT_SUCCESS(queue.Destroy()); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(srcLocalBuffer.As())); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(dstLocalBuffer.As())); EXPECT_EQ(destSysBuffer.As()[0], 0x01010101); TEST_END } TEST_F(KFDLocalMemoryTest, VerifyContentsAfterUnmapAndMap) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); PM4Queue queue; HSAuint64 AlternateVAGPU; unsigned int BufferSize = PAGE_SIZE; HsaMemMapFlags mapFlags = {0}; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (!GetVramSize(defaultGPUNode)) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode); HsaMemoryBuffer SysBufferA(BufferSize, defaultGPUNode, false); HsaMemoryBuffer SysBufferB(BufferSize, defaultGPUNode, true); HsaMemoryBuffer LocalBuffer(BufferSize, defaultGPUNode, false, true); SysBufferA.Fill(0x01010101); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); queue.SetSkipWaitConsump(0); if (!is_dgpu()) ASSERT_SUCCESS(hsaKmtMapMemoryToGPUNodes(LocalBuffer.As(), LocalBuffer.Size(), &AlternateVAGPU, mapFlags, 1, reinterpret_cast(&defaultGPUNode))); Dispatch dispatch(isaBuffer); dispatch.SetArgs(SysBufferA.As(), LocalBuffer.As()); dispatch.Submit(queue); dispatch.Sync(g_TestTimeOut); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(LocalBuffer.As())); EXPECT_SUCCESS(hsaKmtMapMemoryToGPUNodes(LocalBuffer.As(), LocalBuffer.Size(), &AlternateVAGPU, mapFlags, 1, reinterpret_cast(&defaultGPUNode))); dispatch.SetArgs(LocalBuffer.As(), SysBufferB.As()); dispatch.Submit(queue); dispatch.Sync(g_TestTimeOut); EXPECT_SUCCESS(queue.Destroy()); EXPECT_EQ(SysBufferB.As()[0], 0x01010101); if (!is_dgpu()) EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(LocalBuffer.As())); TEST_END } /* Deliberately fragment GPUVM aperture to fill up address space * * General idea: Allocate buffers, but don't map them to GPU. This * will reserve virtual address space without pinning physical * memory. It should allow using more address space than physically * available memory. * * Even without pinning memory, TTM will still commit memory at * allocation time and swap out movable buffers to system memory or * even the hard drive, if it needs to. So we can't allocate arbitrary * amounts of virtual memory. * * Strategy to maximize the amount of allocated, fragmented address * space while keeping the amount of committed memory bounded at all * times: * * 1. Allocate N blocks of a given size, initially 1 page * 2. Free every other block, creating holes in the address space. * This frees up half the memory * 3. Allocate N/4 blocks of 2-pages each. This requires as much * memory as was freed in step 2. The block size is bigger than * the 1-page holes, so new address space will be used. * 4. Free half the blocks just allocated, and half of the * remaining blocks of step 1. This creates 3-page holes between * the 1-page blocks from step 1, and 2-page holes between the * 2-page blocks from step 3. It frees up half of the total * memory. * 5. Double the block size to 4, devide number of blocks by 2. * Again, this will require the amount of memory freed in step 4. * The block size 4 is bigger than the biggest hole (3 pages). * 6. Free half the memory again, creating 7-page holes between * 1-page blocks, 6-page holes between 2-page blocks, and 4-page * holes between 4-page blocks. * * Repeat, doubling block size and halving number of blocks in each * iteration. Each iteration starts and ends with half the total * memory free. Because the block size is always bigger than the * biggest hole, each iteration increases the amount of address space * occupied by half the total memory size. Once the block size reaches * half of the free memory (1/4 of total memory) the limit is reached. * * With 2^n pages available memory, n * 2^(n-1) pages of address space * can be reserved. At the end of that process, half the memory will * be free. * * Total memory | Fragmented address space * order | pages | size | pages | size | ratio * ------+-------+------+-------+-------+------- * 2 | 4 | 16K | 4 | 16K | 1 * 3 | 8 | 32K | 12 | 48K | 1.5 * 4 | 16 | 64K | 32 | 128K | 2 * 5 | 32 | 128K | 80 | 320K | 2.5 * 6 | 64 | 256K | 192 | 768K | 3 * 7 | 128 | 512K | 448 | 1.75M | 3.5 * 8 | 256 | 1M | 1M | 4M | 4 * 9 | 512 | 2M | 2.25M | 9M | 4.5 * 10 | 1K | 4M | 5M | 20M | 5 * 11 | 2K | 8M | 11M | 44M | 5.5 * 12 | 4K | 16M | 24M | 96M | 6 * 13 | 8K | 32M | 52M | 208M | 6.5 * 14 | 16K | 64M | 112M | 448M | 7 * 15 | 32K | 128M | 240M | 960M | 7.5 * 16 | 64K | 256M | 512M | 2G | 8 * 17 | 128K | 512M | 1088M | 4.25G | 8.5 * 18 | 256K | 1G | 2.25G | 9G | 9 * 19 | 512K | 2G | 4.75G | 19G | 9.5 * 20 | 1M | 4G | 10G | 40G | 10 */ TEST_F(KFDLocalMemoryTest, Fragmentation) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HSAuint64 fbSize; fbSize = GetVramSize(defaultGPUNode); if (!fbSize) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } else { LOG() << "Found VRAM of " << std::dec << (fbSize >> 20) << "MB." << std::endl; } /* Use up to half of available memory. Using more results in * excessive memory movement in TTM and slows down the test too * much. maxOrder is the size of the biggest block that will be * allocated. It's 1/4 of the usable memory, so 1/8 the total FB * size in pages. * * Use 8x bigger page size on dGPU to match Tonga alignment * workaround. Also nicely matches the 8x bigger GPUVM address * space on AMDGPU compared to RADEON. */ unsigned pageSize = is_dgpu() ? PAGE_SIZE*8 : PAGE_SIZE; fbSize /= pageSize; unsigned maxOrder = 0; // Limit maxOrder up to 14 so this test doesn't run longer than 10 mins while (((fbSize >> maxOrder) >= 16) && (maxOrder < 14)) maxOrder++; /* Queue and memory used by the shader copy tests */ HsaMemoryBuffer sysBuffer(PAGE_SIZE, defaultGPUNode, false); PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); /* Allocate and test memory using the strategy explained at the top */ HSAKMT_STATUS status; HsaMemFlags memFlags = {0}; HsaMemMapFlags mapFlags = {0}; memFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; memFlags.ui32.HostAccess = 0; memFlags.ui32.NonPaged = 1; struct { void **pointers; unsigned long nPages; } pages[maxOrder+1]; unsigned order, o; unsigned long p; HSAuint64 size; unsigned value = 0; memset(pages, 0, sizeof(pages)); for (order = 0; order <= maxOrder; order++) { // At maxOrder, block size is 1/4 of available memory pages[order].nPages = 1UL << (maxOrder - order + 2); // At order != 0, 1/2 the memory is already allocated if (order > 0) pages[order].nPages >>= 1; // Allocate page pointers pages[order].pointers = new void *[pages[order].nPages]; EXPECT_NE((void **)NULL, pages[order].pointers) << "Couldn't allocate memory for " << pages[order].nPages << " pointers at order " << order << std::endl; if (!pages[order].pointers) { pages[order].nPages = 0; break; } /* Allocate buffers and access the start and end of every one: * 1. Copy from sysBuffer[0] to start of block * 2. Copy from start of block to end of block * 3. Copy from end of block to sysBuffer[1] * 4. Compare results */ size = (HSAuint64)(1 << order) * pageSize; LOG() << std::dec << "Trying to allocate " << pages[order].nPages << " order " << order << " blocks " << std::endl; for (p = 0; p < pages[order].nPages; p++) { status = hsaKmtAllocMemory(defaultGPUNode, size, memFlags, &pages[order].pointers[p]); if (status != HSAKMT_STATUS_SUCCESS) { EXPECT_EQ(HSAKMT_STATUS_NO_MEMORY, status); pages[order].nPages = p; break; } void *bufferEnd = reinterpret_cast(reinterpret_cast(pages[order].pointers[p]) + size - sizeof(unsigned)); sysBuffer.As()[0] = ++value; status = hsaKmtMapMemoryToGPUNodes(pages[order].pointers[p], size, NULL, mapFlags, 1, reinterpret_cast(&defaultGPUNode)); if (status != HSAKMT_STATUS_SUCCESS) { ASSERT_SUCCESS(hsaKmtFreeMemory(pages[order].pointers[p], size)); pages[order].nPages = p; break; } Dispatch dispatch1(isaBuffer); dispatch1.SetArgs(sysBuffer.As(), pages[order].pointers[p]); dispatch1.Submit(queue); // no sync needed for multiple GPU dispatches to the same queue Dispatch dispatch2(isaBuffer); dispatch2.SetArgs(pages[order].pointers[p], bufferEnd); dispatch2.Submit(queue); // no sync needed for multiple GPU dispatches to the same queue Dispatch dispatch3(isaBuffer); dispatch3.SetArgs(bufferEnd, reinterpret_cast(&(sysBuffer.As()[1]))); dispatch3.Submit(queue); dispatch3.Sync(g_TestTimeOut); EXPECT_EQ(value, sysBuffer.As()[1]); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(pages[order].pointers[p])); } LOG() << " Got " << pages[order].nPages << ", end of last block addr: " << reinterpret_cast(reinterpret_cast(pages[order].pointers[p-1]) + size - 1) << std::endl; // Now free half the memory for (o = 0; o <= order; o++) { unsigned long step = 1UL << (order - o + 1); unsigned long offset = (step >> 1) - 1; size = (HSAuint64)(1 << o) * pageSize; LOG() << " Freeing every " << step << "th order " << o << " block starting with " << offset << std::endl; for (p = offset; p < pages[o].nPages; p += step) { ASSERT_NE((void **)NULL, pages[o].pointers[p]); EXPECT_SUCCESS(hsaKmtFreeMemory(pages[o].pointers[p], size)); pages[o].pointers[p] = NULL; } } } /* Clean up */ for (order = 0; order <= maxOrder; order++) { if (pages[order].pointers == NULL) continue; size = (HSAuint64)(1 << order) * pageSize; for (p = 0; p < pages[order].nPages; p++) if (pages[order].pointers[p] != NULL) EXPECT_SUCCESS(hsaKmtFreeMemory(pages[order].pointers[p], size)); delete[] pages[order].pointers; } EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDLocalMemoryTest, CheckZeroInitializationVram) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; /* Testing VRAM */ HSAuint64 vramSizeMB = GetVramSize(defaultGPUNode) >> 20; if (!vramSizeMB) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } HSAuint64 vramBufSizeMB = vramSizeMB >> 2; /* limit the buffer size in order not to overflow the SDMA queue buffer. */ if (vramBufSizeMB > 1024) { vramBufSizeMB = 1024; } HSAuint64 vramBufSize = vramBufSizeMB * 1024 * 1024; /* Make sure the entire VRAM is used at least once */ int count = (vramSizeMB + vramBufSizeMB - 1) / vramBufSizeMB + 1; LOG() << "Using " << std::dec << vramBufSizeMB << "MB VRAM buffer to test " << std::dec << count << " times"<< std::endl; SDMAQueue sdmaQueue; ASSERT_SUCCESS(sdmaQueue.Create(defaultGPUNode, 8 * PAGE_SIZE)); HsaMemoryBuffer tmpBuffer(PAGE_SIZE, 0, true /* zero */); volatile HSAuint32 *tmp = tmpBuffer.As(); unsigned int offset = 2060; // a constant offset, should be 4 aligned. while (count--) { HsaMemoryBuffer localBuffer(vramBufSize, defaultGPUNode, false, true); EXPECT_TRUE(localBuffer.IsPattern(0, 0, sdmaQueue, tmp)); for (HSAuint64 i = offset; i < vramBufSize;) { EXPECT_TRUE(localBuffer.IsPattern(i, 0, sdmaQueue, tmp)); i += 4096; } /* Checking last 4 bytes */ EXPECT_TRUE(localBuffer.IsPattern(vramBufSize - 4, 0, sdmaQueue, tmp)); localBuffer.Fill(0xABCDEFFF, sdmaQueue); } TEST_END } TEST_F(KFDLocalMemoryTest, MapVramToGPUNodesTest) { TEST_START(TESTPROFILE_RUNALL); HSAint32 src_node; HSAint32 dst_node; HsaPointerInfo info; const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); if (gpuNodes.size() < 2) { LOG() << "Skipping test: Test requires at least two GPUs." << std::endl; return; } if (g_TestDstNodeId != -1 && g_TestNodeId != -1) { src_node = g_TestNodeId; dst_node = g_TestDstNodeId; } else { int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); dst_node = m_NodeInfo.FindLargeBarGPUNode(); if (dst_node < 0) { LOG() << "Skipping test: Test requires at least one large bar GPU." << std::endl; return; } if (dst_node != defaultGPUNode) { /* At least one node should be defaultGPUNode */ src_node = defaultGPUNode; } else { for (auto node : gpuNodes) { if (node != dst_node) { src_node = node; break; } } } } if (!m_NodeInfo.IsPeerAccessibleByNode(dst_node, src_node)) { LOG() << "Skipping test: GPUs are not peer-accessible" << std::endl; return; } LOG() << "Testing from GPU " << src_node << " to GPU " << dst_node << std::endl; void *shared_addr; HSAuint32 nodes[] = { (HSAuint32)src_node, (HSAuint32)dst_node }; HsaMemFlags memFlags = {0}; memFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; memFlags.ui32.HostAccess = 1; memFlags.ui32.NonPaged = 1; memFlags.ui32.ExecuteAccess = 1; HsaMemMapFlags mapFlags = {0}; EXPECT_SUCCESS(hsaKmtAllocMemory(nodes[1], PAGE_SIZE, memFlags, &shared_addr)); EXPECT_SUCCESS(hsaKmtRegisterMemoryToNodes(shared_addr, PAGE_SIZE, 2, nodes)); EXPECT_SUCCESS(hsaKmtMapMemoryToGPUNodes(shared_addr, PAGE_SIZE, NULL, mapFlags, 2, nodes)); EXPECT_SUCCESS(hsaKmtQueryPointerInfo(shared_addr, &info)); EXPECT_EQ(info.NRegisteredNodes, 2); EXPECT_EQ(info.NMappedNodes, 2); EXPECT_SUCCESS(hsaKmtMapMemoryToGPUNodes(shared_addr, PAGE_SIZE, NULL, mapFlags, 1, &nodes[0])); EXPECT_SUCCESS(hsaKmtQueryPointerInfo(shared_addr, &info)); EXPECT_EQ(info.NRegisteredNodes, 2); EXPECT_EQ(info.NMappedNodes, 1); EXPECT_EQ(info.MappedNodes[0], nodes[0]); EXPECT_SUCCESS(hsaKmtMapMemoryToGPUNodes(shared_addr, PAGE_SIZE, NULL, mapFlags, 1, &nodes[1])); EXPECT_SUCCESS(hsaKmtQueryPointerInfo(shared_addr, &info)); EXPECT_EQ(info.NRegisteredNodes, 2); EXPECT_EQ(info.NMappedNodes, 1); EXPECT_EQ(info.MappedNodes[0], nodes[1]); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(shared_addr)); EXPECT_SUCCESS(hsaKmtQueryPointerInfo(shared_addr, &info)); EXPECT_EQ(info.NRegisteredNodes, 2); EXPECT_EQ(info.NMappedNodes, 0); EXPECT_SUCCESS(hsaKmtMapMemoryToGPUNodes(shared_addr, PAGE_SIZE, NULL, mapFlags, 1, &nodes[0])); EXPECT_SUCCESS(hsaKmtQueryPointerInfo(shared_addr, &info)); EXPECT_EQ(info.NRegisteredNodes, 2); EXPECT_EQ(info.NMappedNodes, 1); EXPECT_EQ(info.MappedNodes[0], nodes[0]); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(shared_addr)); EXPECT_SUCCESS(hsaKmtFreeMemory(shared_addr, PAGE_SIZE)); TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDLocalMemoryTest.hpp000066400000000000000000000027751446477712600257700ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_LOCALMEMORY_TEST__H__ #define __KFD_LOCALMEMORY_TEST__H__ #include #include "KFDBaseComponentTest.hpp" class KFDLocalMemoryTest : public KFDBaseComponentTest { public: KFDLocalMemoryTest() {} ~KFDLocalMemoryTest() {} protected: virtual void SetUp(); virtual void TearDown(); }; #endif // __KFD_LOCALMEMORY_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDMemoryTest.cpp000066400000000000000000003276531446477712600250150ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDMemoryTest.hpp" #include #include #include #include #include #include #include #include #include #include #include "Dispatch.hpp" #include "PM4Queue.hpp" #include "PM4Packet.hpp" #include "SDMAQueue.hpp" #include "SDMAPacket.hpp" #include "linux/kfd_ioctl.h" /* Captures user specified time (seconds) to sleep */ extern unsigned int g_SleepTime; void KFDMemoryTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); ROUTINE_END } void KFDMemoryTest::TearDown() { ROUTINE_START KFDBaseComponentTest::TearDown(); ROUTINE_END } #include #define GB(x) ((x) << 30) /* * Try to map as much as possible system memory to gpu * to see if KFD supports 1TB memory correctly or not. * After this test case, we can observe if there are any side effects. * NOTICE: There are memory usage limit checks in hsa/kfd according to the total * physical system memory. */ TEST_F(KFDMemoryTest, MMapLarge) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL) if (!is_dgpu()) { LOG() << "Skipping test: Test not supported on APU." << std::endl; return; } HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; const HSAuint64 nObjects = 1<<14; HSAuint64 *AlternateVAGPU = new HSAuint64[nObjects]; ASSERT_NE((HSAuint64)AlternateVAGPU, 0); HsaMemMapFlags mapFlags = {0}; HSAuint64 s; char *addr; HSAuint64 flags = MAP_ANONYMOUS | MAP_PRIVATE; /* Test up to 1TB memory*/ s = GB(1024ULL) / nObjects; addr = reinterpret_cast(mmap(0, s, PROT_READ | PROT_WRITE, flags, -1, 0)); ASSERT_NE(addr, MAP_FAILED); memset(addr, 0, s); int i = 0; /* Allocate 1024GB, aka 1TB*/ for (; i < nObjects; i++) { /* Code snippet to allow CRIU checkpointing */ if (i == (1 << 6)) { if (g_SleepTime > 0) { LOG() << "Pause for: " << g_SleepTime << " seconds" << std::endl; sleep(g_SleepTime); } } if (hsaKmtRegisterMemory(addr + i, s - i)) break; if (hsaKmtMapMemoryToGPUNodes(addr + i, s - i, &AlternateVAGPU[i], mapFlags, 1, reinterpret_cast(&defaultGPUNode))) { hsaKmtDeregisterMemory(addr + i); break; } } LOG() << "Successfully registered and mapped " << (i * s >> 30) << "GB system memory to gpu" << std::endl; RECORD(i * s >> 30) << "Mmap-SysMem-Size"; while (i--) { EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(reinterpret_cast(AlternateVAGPU[i]))); EXPECT_SUCCESS(hsaKmtDeregisterMemory(reinterpret_cast(AlternateVAGPU[i]))); } munmap(addr, s); delete []AlternateVAGPU; TEST_END } /* Keep memory mapped to default node * Keep mapping/unmapping memory to/from non-default node * A shader running on default node consistantly accesses * memory - make sure memory is always accessible by default, * i.e. there is no gpu vm fault. * Synchronization b/t host program and shader: * 1. Host initializes src and dst buffer to 0 * 2. Shader keeps reading src buffer and check value * 3. Host writes src buffer to 0x5678 to indicate quit, polling dst until it becomes 0x5678 * 4. Shader write dst buffer to 0x5678 after src changes to 0x5678, then quits * 5. Host program quits after dst becomes 0x5678 * Need at least two gpu nodes to run the test. The default node has to be a gfx9 node, * otherwise, test is skipped. Use kfdtest --node=$$ to specify the default node * This test case is introduced as a side-result of investigation of SWDEV-134798, which * is a gpu vm fault while running rocr conformance test. Here we try to simulate the * same test behaviour. */ TEST_F(KFDMemoryTest, MapUnmapToNodes) { TEST_START(TESTPROFILE_RUNALL) if (m_FamilyId < FAMILY_AI) { LOG() << "Skipping test: Test requires gfx9 and later asics." << std::endl; return; } const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); if (gpuNodes.size() < 2) { LOG() << "Skipping test: At least two GPUs are required." << std::endl; return; } HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); LOG() << "default GPU node" << defaultGPUNode << std::endl; ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HSAuint32 nondefaultNode; for (unsigned i = 0; i < gpuNodes.size(); i++) { if (gpuNodes.at(i) != defaultGPUNode) { nondefaultNode = gpuNodes.at(i); break; } } HSAuint32 mapNodes[2] = {defaultGPUNode, nondefaultNode}; HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer srcBuffer(PAGE_SIZE, defaultGPUNode); HsaMemoryBuffer dstBuffer(PAGE_SIZE, defaultGPUNode); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(PollMemoryIsa, isaBuffer.As())); PM4Queue pm4Queue; ASSERT_SUCCESS(pm4Queue.Create(defaultGPUNode)); Dispatch dispatch0(isaBuffer); dispatch0.SetArgs(srcBuffer.As(), dstBuffer.As()); dispatch0.Submit(pm4Queue); HsaMemMapFlags memFlags = {0}; memFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; memFlags.ui32.HostAccess = 1; for (unsigned i = 0; i < 1<<14; i ++) { hsaKmtMapMemoryToGPUNodes(srcBuffer.As(), PAGE_SIZE, NULL, memFlags, (i>>5)&1+1, mapNodes); } /* Fill src buffer so shader quits */ srcBuffer.Fill(0x5678); WaitOnValue(dstBuffer.As(), 0x5678); EXPECT_EQ(*dstBuffer.As(), 0x5678); EXPECT_SUCCESS(pm4Queue.Destroy()); TEST_END } // Basic test of hsaKmtMapMemoryToGPU and hsaKmtUnmapMemoryToGPU TEST_F(KFDMemoryTest , MapMemoryToGPU) { TEST_START(TESTPROFILE_RUNALL) unsigned int *nullPtr = NULL; unsigned int* pDb = NULL; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; ASSERT_SUCCESS(hsaKmtAllocMemory(defaultGPUNode /* system */, PAGE_SIZE, m_MemoryFlags, reinterpret_cast(&pDb))); // verify that pDb is not null before it's being used ASSERT_NE(nullPtr, pDb) << "hsaKmtAllocMemory returned a null pointer"; ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(pDb, PAGE_SIZE, NULL)); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(pDb)); // Release the buffers EXPECT_SUCCESS(hsaKmtFreeMemory(pDb, PAGE_SIZE)); TEST_END } // Following tests are for hsaKmtAllocMemory with invalid params TEST_F(KFDMemoryTest, InvalidMemoryPointerAlloc) { TEST_START(TESTPROFILE_RUNALL) m_MemoryFlags.ui32.NoNUMABind = 1; EXPECT_EQ(HSAKMT_STATUS_INVALID_PARAMETER, hsaKmtAllocMemory(0 /* system */, PAGE_SIZE, m_MemoryFlags, NULL)); TEST_END } TEST_F(KFDMemoryTest, ZeroMemorySizeAlloc) { TEST_START(TESTPROFILE_RUNALL) unsigned int* pDb = NULL; EXPECT_EQ(HSAKMT_STATUS_INVALID_PARAMETER, hsaKmtAllocMemory(0 /* system */, 0, m_MemoryFlags, reinterpret_cast(&pDb))); TEST_END } // Basic test for hsaKmtAllocMemory TEST_F(KFDMemoryTest, MemoryAlloc) { TEST_START(TESTPROFILE_RUNALL) unsigned int* pDb = NULL; m_MemoryFlags.ui32.NoNUMABind = 1; EXPECT_SUCCESS(hsaKmtAllocMemory(0 /* system */, PAGE_SIZE, m_MemoryFlags, reinterpret_cast(&pDb))); TEST_END } // Basic test for hsaKmtAllocMemory TEST_F(KFDMemoryTest, MemoryAllocAll) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); HsaMemFlags memFlags = {0}; memFlags.ui32.NonPaged = 1; // sys mem vs vram HSAuint64 available; if (m_VersionInfo.KernelInterfaceMinorVersion < 9) { LOG() << "Available memory IOCTL not present in KFD. Exiting." << std::endl; return; } void *object = NULL; int shrink = 21, success = HSAKMT_STATUS_NO_MEMORY; EXPECT_SUCCESS(hsaKmtAvailableMemory(defaultGPUNode, &available)); LOG() << "Available: " << available << " bytes" << std::endl; HSAuint64 leeway = (10 << shrink), size = available + leeway; for (int i = 0; i < available >> shrink; i++) { if (hsaKmtAllocMemory(defaultGPUNode, size, memFlags, &object) == HSAKMT_STATUS_SUCCESS) { success = hsaKmtFreeMemory(object, available); break; } size -= (1 << shrink); } if (success == HSAKMT_STATUS_SUCCESS) { LOG() << "Allocated: " << size << " bytes" << std::endl; if (size > available + leeway) { LOG() << "Under-reported available memory!" << std::endl; } if (size < available - leeway) { LOG() << "Over-reported available memory!" << std::endl; } } EXPECT_SUCCESS(success); TEST_END } TEST_F(KFDMemoryTest, AccessPPRMem) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (is_dgpu()) { LOG() << "Skipping test: Test requires APU." << std::endl; return; } unsigned int *destBuf = (unsigned int *)VirtualAllocMemory(NULL, PAGE_SIZE, MEM_READ | MEM_WRITE); PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaEvent *event; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &event)); queue.PlaceAndSubmitPacket(PM4WriteDataPacket(destBuf, 0xABCDEF09, 0x12345678)); queue.Wait4PacketConsumption(event); WaitOnValue(destBuf, 0xABCDEF09); WaitOnValue(destBuf + 1, 0x12345678); hsaKmtDestroyEvent(event); EXPECT_SUCCESS(queue.Destroy()); /* This sleep hides the dmesg PPR message storm on Raven, which happens * when the CPU buffer is freed before the excessive PPRs are all * consumed by IOMMU HW. Because of that, a kernel driver workaround * is put in place to address that, so we don't need to wait here. */ // sleep(5); VirtualFreeMemory(destBuf, PAGE_SIZE); TEST_END } // Linux OS-specific Test for registering OS allocated memory TEST_F(KFDMemoryTest, MemoryRegister) { const HsaNodeProperties *pNodeProperties = m_NodeInfo.HsaDefaultGPUNodeProperties(); TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; /* Different unaligned memory locations to be mapped for GPU * access: * * - initialized data segment (file backed) * - stack (anonymous memory) * * Separate them enough so they are in different cache lines * (64-byte = 16-dword). */ static volatile HSAuint32 globalData = 0xdeadbeef; volatile HSAuint32 stackData[17] = {0}; const unsigned dstOffset = 0; const unsigned sdmaOffset = 16; HsaMemoryBuffer srcBuffer((void *)&globalData, sizeof(HSAuint32)); HsaMemoryBuffer dstBuffer((void *)&stackData[dstOffset], sizeof(HSAuint32)); HsaMemoryBuffer sdmaBuffer((void *)&stackData[sdmaOffset], sizeof(HSAuint32)); /* Create PM4 and SDMA queues before fork+COW to test queue * eviction and restore */ PM4Queue pm4Queue; SDMAQueue sdmaQueue; ASSERT_SUCCESS(pm4Queue.Create(defaultGPUNode)); ASSERT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); /* First submit just so the queues are not empty, and to get the * TLB populated (in case we need to flush TLBs somewhere after * updating the page tables) */ Dispatch dispatch0(isaBuffer); dispatch0.SetArgs(srcBuffer.As(), dstBuffer.As()); dispatch0.Submit(pm4Queue); dispatch0.Sync(g_TestTimeOut); sdmaQueue.PlaceAndSubmitPacket(SDMAWriteDataPacket(sdmaQueue.GetFamilyId(), sdmaBuffer.As(), 0x12345678)); sdmaQueue.Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(&stackData[sdmaOffset], 0x12345678)); /* Fork a child process to mark pages as COW */ pid_t pid = fork(); ASSERT_GE(pid, 0); if (pid == 0) { /* Child process waits for a SIGTERM from the parent. It can't * make any write access to the stack because we want the * parent to make the first write access and get a new copy. A * busy loop is the safest way to do that, since any function * call (e.g. sleep) would write to the stack. */ while (1) {} WARN() << "Shouldn't get here!" << std::endl; exit(0); } /* Parent process writes to COW page(s) and gets a new copy. MMU * notifier needs to update the GPU mapping(s) for the test to * pass. */ globalData = 0xD00BED00; stackData[dstOffset] = 0xdeadbeef; stackData[sdmaOffset] = 0xdeadbeef; /* Terminate the child process before a possible test failure that * would leave it spinning in the background indefinitely. */ int status; EXPECT_EQ(0, kill(pid, SIGTERM)); EXPECT_EQ(pid, waitpid(pid, &status, 0)); EXPECT_NE(0, WIFSIGNALED(status)); EXPECT_EQ(SIGTERM, WTERMSIG(status)); /* Now check that the GPU is accessing the correct page */ Dispatch dispatch1(isaBuffer); dispatch1.SetArgs(srcBuffer.As(), dstBuffer.As()); dispatch1.Submit(pm4Queue); dispatch1.Sync(g_TestTimeOut); sdmaQueue.PlaceAndSubmitPacket(SDMAWriteDataPacket(sdmaQueue.GetFamilyId(), sdmaBuffer.As(), 0xD0BED0BE)); sdmaQueue.Wait4PacketConsumption(); EXPECT_SUCCESS(pm4Queue.Destroy()); EXPECT_SUCCESS(sdmaQueue.Destroy()); EXPECT_EQ(0xD00BED00, globalData); EXPECT_EQ(0xD00BED00, stackData[dstOffset]); EXPECT_EQ(0xD0BED0BE, stackData[sdmaOffset]); TEST_END } TEST_F(KFDMemoryTest, MemoryRegisterSamePtr) { if (!is_dgpu()) { LOG() << "Skipping test: Will run on APU once APU+dGPU supported." << std::endl; return; } TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); HSAuint64 nGPU = gpuNodes.size(); // number of gpu nodes static volatile HSAuint32 mem[4]; HSAuint64 gpuva1, gpuva2; /* Same address, different size */ EXPECT_SUCCESS(hsaKmtRegisterMemory((void *)&mem[0], sizeof(HSAuint32)*2)); EXPECT_SUCCESS(hsaKmtMapMemoryToGPU((void *)&mem[0], sizeof(HSAuint32)*2, &gpuva1)); EXPECT_SUCCESS(hsaKmtRegisterMemory((void *)&mem[0], sizeof(HSAuint32))); EXPECT_SUCCESS(hsaKmtMapMemoryToGPU((void *)&mem[0], sizeof(HSAuint32), &gpuva2)); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(reinterpret_cast(gpuva1))); EXPECT_SUCCESS(hsaKmtDeregisterMemory(reinterpret_cast(gpuva1))); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(reinterpret_cast(gpuva2))); EXPECT_SUCCESS(hsaKmtDeregisterMemory(reinterpret_cast(gpuva2))); /* Same address, same size */ HsaMemMapFlags memFlags = {0}; memFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; memFlags.ui32.HostAccess = 1; HSAuint32 nodes[nGPU]; for (unsigned int i = 0; i < nGPU; i++) nodes[i] = gpuNodes.at(i); EXPECT_SUCCESS(hsaKmtRegisterMemoryToNodes((void *)&mem[2], sizeof(HSAuint32)*2, nGPU, nodes)); EXPECT_SUCCESS(hsaKmtMapMemoryToGPUNodes((void *)&mem[2], sizeof(HSAuint32) * 2, &gpuva1, memFlags, nGPU, nodes)); EXPECT_SUCCESS(hsaKmtRegisterMemoryToNodes((void *)&mem[2], sizeof(HSAuint32) * 2, nGPU, nodes)); EXPECT_SUCCESS(hsaKmtMapMemoryToGPUNodes((void *)&mem[2], sizeof(HSAuint32) * 2, &gpuva2, memFlags, nGPU, nodes)); EXPECT_EQ(gpuva1, gpuva2); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(reinterpret_cast(gpuva1))); EXPECT_SUCCESS(hsaKmtDeregisterMemory(reinterpret_cast(gpuva1))); /* Confirm that we still have access to the memory, mem[2] */ PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); mem[2] = 0x0; queue.PlaceAndSubmitPacket(PM4WriteDataPacket(reinterpret_cast(gpuva2), 0xdeadbeef)); queue.PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, true, 0, 0)); queue.Wait4PacketConsumption(); EXPECT_EQ(true, WaitOnValue((unsigned int *)(&mem[2]), 0xdeadbeef)); EXPECT_SUCCESS(queue.Destroy()); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(reinterpret_cast(gpuva2))); EXPECT_SUCCESS(hsaKmtDeregisterMemory(reinterpret_cast(gpuva2))); TEST_END } /* FlatScratchAccess * Since HsaMemoryBuffer has to be associated with a specific GPU node, this function in the current form * will not work for multiple GPU nodes. For now test only one default GPU node. * TODO: Generalize it to support multiple nodes */ #define SCRATCH_SLICE_SIZE 0x10000 #define SCRATCH_SLICE_NUM 3 #define SCRATCH_SIZE (SCRATCH_SLICE_NUM * SCRATCH_SLICE_SIZE) #define SCRATCH_SLICE_OFFSET(i) ((i) * SCRATCH_SLICE_SIZE) TEST_F(KFDMemoryTest, FlatScratchAccess) { TEST_START(TESTPROFILE_RUNALL) if (m_FamilyId == FAMILY_CI || m_FamilyId == FAMILY_KV) { LOG() << "Skipping test: VI-based shader not supported on other ASICs." << std::endl; return; } int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer scratchBuffer(SCRATCH_SIZE, defaultGPUNode, false/*zero*/, false/*local*/, false/*exec*/, true /*scratch*/); // Unmap scratch for sub-allocation mapping tests ASSERT_SUCCESS(hsaKmtUnmapMemoryToGPU(scratchBuffer.As())); // Map and unmap a few slices in different order: 2-0-1, 0-2-1 ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(scratchBuffer.As() + SCRATCH_SLICE_OFFSET(2), SCRATCH_SLICE_SIZE, NULL)); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(scratchBuffer.As() + SCRATCH_SLICE_OFFSET(0), SCRATCH_SLICE_SIZE, NULL)); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(scratchBuffer.As() + SCRATCH_SLICE_OFFSET(1), SCRATCH_SLICE_SIZE, NULL)); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(scratchBuffer.As() + SCRATCH_SLICE_OFFSET(1))); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(scratchBuffer.As() + SCRATCH_SLICE_OFFSET(2))); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(scratchBuffer.As() + SCRATCH_SLICE_OFFSET(0))); // Map everything for test below ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(scratchBuffer.As(), SCRATCH_SIZE, NULL)); HsaMemoryBuffer srcMemBuffer(PAGE_SIZE, defaultGPUNode); HsaMemoryBuffer dstMemBuffer(PAGE_SIZE, defaultGPUNode); // Initialize the srcBuffer to some fixed value srcMemBuffer.Fill(0x01010101); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(ScratchCopyDwordIsa, isaBuffer.As())); const HsaNodeProperties *pNodeProperties = m_NodeInfo.GetNodeProperties(defaultGPUNode); /* TODO: Add support to all GPU Nodes. * The loop over the system nodes is removed as the test can be executed only on GPU nodes. This * also requires changes to be made to all the HsaMemoryBuffer variables defined above, as * HsaMemoryBuffer is now associated with a Node. */ if (pNodeProperties != NULL) { // Get the aperture of the scratch buffer HsaMemoryProperties *memoryProperties = new HsaMemoryProperties[pNodeProperties->NumMemoryBanks]; EXPECT_SUCCESS(hsaKmtGetNodeMemoryProperties(defaultGPUNode, pNodeProperties->NumMemoryBanks, memoryProperties)); for (unsigned int bank = 0; bank < pNodeProperties->NumMemoryBanks; bank++) { if (memoryProperties[bank].HeapType == HSA_HEAPTYPE_GPU_SCRATCH) { int numWaves = pNodeProperties->NumShaderBanks; // WAVES must be >= # SE int waveSize = 1; // Amount of space used by each wave in units of 256 dwords PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HSAuint64 scratchApertureAddr = memoryProperties[bank].VirtualBaseAddress; // Create a dispatch packet to copy Dispatch dispatchSrcToScratch(isaBuffer); // Setup the dispatch packet // Copying from the source Memory Buffer to the scratch buffer dispatchSrcToScratch.SetArgs(srcMemBuffer.As(), reinterpret_cast(scratchApertureAddr)); dispatchSrcToScratch.SetDim(1, 1, 1); dispatchSrcToScratch.SetScratch(numWaves, waveSize, scratchBuffer.As()); // Submit the packet dispatchSrcToScratch.Submit(queue); dispatchSrcToScratch.Sync(); // Create another dispatch packet to copy scratch buffer contents to destination buffer. Dispatch dispatchScratchToDst(isaBuffer); // Set the arguments to copy from the scratch buffer to the destination buffer dispatchScratchToDst.SetArgs(reinterpret_cast(scratchApertureAddr), dstMemBuffer.As()); dispatchScratchToDst.SetDim(1, 1, 1); dispatchScratchToDst.SetScratch(numWaves, waveSize, scratchBuffer.As()); // Submit the packet dispatchScratchToDst.Submit(queue); dispatchScratchToDst.Sync(); // Check that the scratch buffer contents were correctly copied over to the system memory buffer EXPECT_EQ(dstMemBuffer.As()[0], 0x01010101); } } delete [] memoryProperties; } TEST_END } TEST_F(KFDMemoryTest, GetTileConfigTest) { TEST_START(TESTPROFILE_RUNALL) HSAuint32 tile_config[32] = {0}; HSAuint32 macro_tile_config[16] = {0}; unsigned int i; HsaGpuTileConfig config = {0}; config.TileConfig = tile_config; config.MacroTileConfig = macro_tile_config; config.NumTileConfigs = 32; config.NumMacroTileConfigs = 16; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_SUCCESS(hsaKmtGetTileConfig(defaultGPUNode, &config)); LOG() << "tile_config:" << std::endl; for (i = 0; i < config.NumTileConfigs; i++) LOG() << "\t" << std::dec << i << ": 0x" << std::hex << tile_config[i] << std::endl; LOG() << "macro_tile_config:" << std::endl; for (i = 0; i < config.NumMacroTileConfigs; i++) LOG() << "\t" << std::dec << i << ": 0x" << std::hex << macro_tile_config[i] << std::endl; LOG() << "gb_addr_config: 0x" << std::hex << config.GbAddrConfig << std::endl; LOG() << "num_banks: 0x" << std::hex << config.NumBanks << std::endl; LOG() << "num_ranks: 0x" << std::hex << config.NumRanks << std::endl; TEST_END } void KFDMemoryTest::BinarySearchLargestBuffer(int allocNode, const HsaMemFlags &memFlags, HSAuint64 highMB, int nodeToMap, HSAuint64 *lastSizeMB) { int ret; int iter = 0; HsaMemMapFlags mapFlags = {0}; HSAuint64 granularityMB = highMB > 512 ? 128 : 16; /* Testing big buffers in VRAM */ unsigned int * pDb = NULL; HSAuint64 lowMB = 0; highMB = (highMB + granularityMB - 1) & ~(granularityMB - 1); HSAuint64 sizeMB; HSAuint64 size = 0; while (highMB - lowMB > granularityMB) { sizeMB = (lowMB + highMB) / 2; size = sizeMB * 1024 * 1024; ret = hsaKmtAllocMemory(allocNode, size, memFlags, reinterpret_cast(&pDb)); if (ret) { highMB = sizeMB; continue; } /* Code snippet to allow CRIU checkpointing */ iter++; if (iter == 3) { if (g_SleepTime > 0) { LOG() << "Pause for: " << g_SleepTime << " seconds" << std::endl; sleep(g_SleepTime); } } ret = hsaKmtMapMemoryToGPUNodes(pDb, size, NULL, mapFlags, 1, reinterpret_cast(&nodeToMap)); if (ret) { EXPECT_SUCCESS(hsaKmtFreeMemory(pDb, size)); highMB = sizeMB; continue; } EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(pDb)); EXPECT_SUCCESS(hsaKmtFreeMemory(pDb, size)); lowMB = sizeMB; } if (lastSizeMB) *lastSizeMB = lowMB; } /* * Largest*BufferTest allocates, maps/unmaps, and frees the largest possible * buffers. Its size is found using binary search in the range * (0, RAM SIZE) with a granularity of 128M. Also, the similar logic is * repeated on local buffers (VRAM). * Please note we limit the largest possible system buffer to be smaller than * the RAM size. The reason is that the system buffer can make use of virtual * memory so that a system buffer could be very large even though the RAM size * is small. For example, on a typical Carrizo platform, the largest allocated * system buffer could be more than 14G even though it only has 4G memory. * In that situation, it will take too much time to finish the test because of * the onerous memory swap operation. So we limit the buffer size that way. */ TEST_F(KFDMemoryTest, LargestSysBufferTest) { if (!is_dgpu()) { LOG() << "Skipping test: Running on APU fails and locks the system." << std::endl; return; } TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HSAuint64 lastTestedSizeMB = 0; HSAuint64 sysMemSizeMB; sysMemSizeMB = GetSysMemSize() >> 20; LOG() << "Found System Memory of " << std::dec << sysMemSizeMB << "MB" << std::endl; BinarySearchLargestBuffer(0, m_MemoryFlags, sysMemSizeMB, defaultGPUNode, &lastTestedSizeMB); LOG() << "The largest allocated system buffer is " << std::dec << lastTestedSizeMB << "MB" << std::endl; TEST_END } TEST_F(KFDMemoryTest, LargestVramBufferTest) { if (!is_dgpu()) { LOG() << "Skipping test: Running on APU fails and locks the system." << std::endl; return; } TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HSAuint64 lastTestedSizeMB = 0; HsaMemFlags memFlags = {0}; memFlags.ui32.HostAccess = 0; memFlags.ui32.NonPaged = 1; HSAuint64 vramSizeMB; vramSizeMB = GetVramSize(defaultGPUNode) >> 20; LOG() << "Found VRAM of " << std::dec << vramSizeMB << "MB." << std::endl; BinarySearchLargestBuffer(defaultGPUNode, memFlags, vramSizeMB, defaultGPUNode, &lastTestedSizeMB); LOG() << "The largest allocated VRAM buffer is " << std::dec << lastTestedSizeMB << "MB" << std::endl; /* Make sure 3/4 vram can be allocated.*/ EXPECT_GE(lastTestedSizeMB * 4, vramSizeMB * 3); if (lastTestedSizeMB * 16 < vramSizeMB * 15) WARN() << "The largest allocated VRAM buffer size is smaller than the expected " << vramSizeMB * 15 / 16 << "MB" << std::endl; TEST_END } /* * BigSysBufferStressTest allocates and maps 128M system buffers in a loop until it * fails, then unmaps and frees them afterwards. Meanwhile, a queue task is * performed on each buffer. */ TEST_F(KFDMemoryTest, BigSysBufferStressTest) { if (!is_dgpu()) { LOG() << "Skipping test: Running on APU fails and locks the system." << std::endl; return; } TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); HSAuint64 AlternateVAGPU; HsaMemMapFlags mapFlags = {0}; int ret; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; /* Repeatedly allocate and map big buffers in system memory until it fails, * then unmap and free them. */ #define ARRAY_ENTRIES 2048 int i = 0, allocationCount = 0; unsigned int* pDb_array[ARRAY_ENTRIES]; HSAuint64 block_size_mb = 128; HSAuint64 block_size = block_size_mb * 1024 * 1024; /* Test 4 times to see if there is any memory leak.*/ for (int repeat = 1; repeat < 5; repeat++) { for (i = 0; i < ARRAY_ENTRIES; i++) { ret = hsaKmtAllocMemory(0 /* system */, block_size, m_MemoryFlags, reinterpret_cast(&pDb_array[i])); if (ret) break; ret = hsaKmtMapMemoryToGPUNodes(pDb_array[i], block_size, &AlternateVAGPU, mapFlags, 1, reinterpret_cast(&defaultGPUNode)); if (ret) { EXPECT_SUCCESS(hsaKmtFreeMemory(pDb_array[i], block_size)); break; } } LOG() << "Allocated system buffers time " << std::dec << repeat << ": " << i << " * " << block_size_mb << "MB" << std::endl; if (allocationCount == 0) allocationCount = i; EXPECT_GE(i, allocationCount) << "There might be memory leak!" << std::endl; for (int j = 0; j < i; j++) { EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(pDb_array[j])); EXPECT_SUCCESS(hsaKmtFreeMemory(pDb_array[j], block_size)); } } TEST_END } #define VRAM_ALLOCATION_ALIGN (1 << 21) //Align VRAM allocations to 2MB TEST_F(KFDMemoryTest, MMBench) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); unsigned testIndex, sizeIndex, memType, nMemTypes; const char *memTypeStrings[2] = {"SysMem", "VRAM"}; const struct { unsigned size; unsigned num; } bufParams[] = { /* Buffer sizes in x16 increments. Limit memory usage to about * 1GB. For small sizes we use 1000 buffers, which means we * conveniently measure microseconds and report nanoseconds. */ {PAGE_SIZE , 1000}, /* 4KB */ {PAGE_SIZE << 4, 1000}, /* 64KB */ {PAGE_SIZE << 9, 500}, /* 2MB */ {PAGE_SIZE << 13, 32}, /* 32MB */ {PAGE_SIZE << 18, 1}, /* 1GB */ }; const unsigned nSizes = sizeof(bufParams) / sizeof(bufParams[0]); const unsigned nTests = nSizes << 2; #define TEST_BUFSIZE(index) (bufParams[(index) % nSizes].size) #define TEST_NBUFS(index) (bufParams[(index) % nSizes].num) #define TEST_MEMTYPE(index) ((index / nSizes) & 0x1) #define TEST_SDMA(index) (((index / nSizes) >> 1) & 0x1) void *bufs[1000]; HSAuint64 start, end; unsigned i; HSAKMT_STATUS ret; HsaMemFlags memFlags = {0}; HsaMemMapFlags mapFlags = {0}; HSAuint64 altVa; HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HSAuint64 vramSizeMB = GetVramSize(defaultGPUNode) >> 20; const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); bool is_all_large_bar = true; for (unsigned i = 0; i < gpuNodes.size(); i++) { if (!m_NodeInfo.IsGPUNodeLargeBar(gpuNodes.at(i))) { is_all_large_bar = false; break; } } LOG() << "Found VRAM of " << std::dec << vramSizeMB << "MB." << std::endl; if (vramSizeMB == 0) nMemTypes = 1; else nMemTypes = 2; /* Two SDMA queues to interleave user mode SDMA with memory * management on either SDMA engine. Make the queues long enough * to buffer at least nBufs x WriteData packets (7 dwords per * packet). */ SDMAQueue sdmaQueue[2]; ASSERT_SUCCESS(sdmaQueue[0].Create(defaultGPUNode, PAGE_SIZE*8)); ASSERT_SUCCESS(sdmaQueue[1].Create(defaultGPUNode, PAGE_SIZE*8)); HsaMemoryBuffer sdmaBuffer(PAGE_SIZE, 0); /* system memory */ #define INTERLEAVE_SDMA() do { \ if (interleaveSDMA) { \ sdmaQueue[0].PlaceAndSubmitPacket( \ SDMAWriteDataPacket(sdmaQueue[0].GetFamilyId(), sdmaBuffer.As(), \ 0x12345678)); \ sdmaQueue[1].PlaceAndSubmitPacket( \ SDMAWriteDataPacket(sdmaQueue[1].GetFamilyId(), sdmaBuffer.As()+16, \ 0x12345678)); \ } \ } while (0) #define IDLE_SDMA() do { \ if (interleaveSDMA) { \ sdmaQueue[0].Wait4PacketConsumption(); \ sdmaQueue[1].Wait4PacketConsumption(); \ } \ } while (0) LOG() << "Test (avg. ns)\t alloc mapOne umapOne mapAll umapAll free" << std::endl; for (testIndex = 0; testIndex < nTests; testIndex++) { unsigned bufSize = TEST_BUFSIZE(testIndex); unsigned nBufs = TEST_NBUFS(testIndex); unsigned memType = TEST_MEMTYPE(testIndex); bool interleaveSDMA = TEST_SDMA(testIndex); unsigned bufLimit; HSAuint64 allocTime, map1Time, unmap1Time, mapAllTime, unmapAllTime, freeTime; HSAuint32 allocNode; /* Code snippet to allow CRIU checkpointing */ if (testIndex == 3) { if (g_SleepTime > 0) { LOG() << "Pause for: " << g_SleepTime << " seconds" << std::endl; sleep(g_SleepTime); } } if ((testIndex % nSizes) == 0) LOG() << "--------------------------------------------------------------------------" << std::endl; if (memType >= nMemTypes) continue; // skip unsupported mem types if (memType == 0) { allocNode = 0; memFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; memFlags.ui32.HostAccess = 1; memFlags.ui32.NonPaged = 0; memFlags.ui32.NoNUMABind = 1; } else { allocNode = defaultGPUNode; memFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; memFlags.ui32.HostAccess = 0; memFlags.ui32.NonPaged = 1; /* Buffer sizes are 2MB aligned to match new allocation policy. * Upper limit of buffer number to fit 80% vram size. */ bufLimit = ((vramSizeMB << 20) * 8 / 10) / ALIGN_UP(bufSize, VRAM_ALLOCATION_ALIGN); if (bufLimit == 0) continue; // skip when bufSize > vram /* When vram is too small to fit all the buffers, fill 90% vram size*/ nBufs = (nBufs < bufLimit) ? nBufs : bufLimit; } /* Allocation */ start = GetSystemTickCountInMicroSec(); for (i = 0; i < nBufs; i++) { ASSERT_SUCCESS(hsaKmtAllocMemory(allocNode, bufSize, memFlags, &bufs[i])); INTERLEAVE_SDMA(); } allocTime = GetSystemTickCountInMicroSec() - start; IDLE_SDMA(); /* Map to one GPU */ start = GetSystemTickCountInMicroSec(); for (i = 0; i < nBufs; i++) { ASSERT_SUCCESS(hsaKmtMapMemoryToGPUNodes(bufs[i], bufSize, &altVa, mapFlags, 1, &defaultGPUNode)); INTERLEAVE_SDMA(); } map1Time = GetSystemTickCountInMicroSec() - start; IDLE_SDMA(); /* Unmap from GPU */ start = GetSystemTickCountInMicroSec(); for (i = 0; i < nBufs; i++) { EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(bufs[i])); INTERLEAVE_SDMA(); } unmap1Time = GetSystemTickCountInMicroSec() - start; IDLE_SDMA(); /* Map to all GPUs */ if (is_all_large_bar) { start = GetSystemTickCountInMicroSec(); for (i = 0; i < nBufs; i++) { ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(bufs[i], bufSize, &altVa)); INTERLEAVE_SDMA(); } mapAllTime = GetSystemTickCountInMicroSec() - start; IDLE_SDMA(); /* Unmap from all GPUs */ start = GetSystemTickCountInMicroSec(); for (i = 0; i < nBufs; i++) { EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(bufs[i])); INTERLEAVE_SDMA(); } unmapAllTime = GetSystemTickCountInMicroSec() - start; IDLE_SDMA(); } /* Free */ start = GetSystemTickCountInMicroSec(); for (i = 0; i < nBufs; i++) { EXPECT_SUCCESS(hsaKmtFreeMemory(bufs[i], bufSize)); INTERLEAVE_SDMA(); } freeTime = GetSystemTickCountInMicroSec() - start; IDLE_SDMA(); allocTime = allocTime * 1000 / nBufs; map1Time = map1Time * 1000 / nBufs; unmap1Time = unmap1Time * 1000 / nBufs; mapAllTime = mapAllTime * 1000 / nBufs; unmapAllTime = unmapAllTime * 1000 / nBufs; freeTime = freeTime * 1000 / nBufs; unsigned bufSizeLog; char bufSizeUnit; if (bufSize < (1 << 20)) { bufSizeLog = bufSize >> 10; bufSizeUnit = 'K'; } else if (bufSize < (1 << 30)) { bufSizeLog = bufSize >> 20; bufSizeUnit = 'M'; } else { bufSizeLog = bufSize >> 30; bufSizeUnit = 'G'; } LOG() << std::dec << std::setiosflags(std::ios::right) << std::setw(3) << bufSizeLog << bufSizeUnit << "-" << memTypeStrings[memType] << "-" << (interleaveSDMA ? "SDMA\t" : "noSDMA\t") << std::setw(9) << allocTime << std::setw(9) << map1Time << std::setw(9) << unmap1Time << std::setw(9) << mapAllTime << std::setw(9) << unmapAllTime << std::setw(9) << freeTime << std::endl; #define MMBENCH_KEY_PREFIX memTypeStrings[memType] << "-" \ << (interleaveSDMA ? "SDMA" : "noSDMA") << "-" \ << (bufSize >> 10) << "K-" RECORD(allocTime) << MMBENCH_KEY_PREFIX << "alloc"; RECORD(map1Time) << MMBENCH_KEY_PREFIX << "mapOne"; RECORD(unmap1Time) << MMBENCH_KEY_PREFIX << "unmapOne"; RECORD(mapAllTime) << MMBENCH_KEY_PREFIX << "mapAll"; RECORD(unmapAllTime) << MMBENCH_KEY_PREFIX << "unmapAll"; RECORD(freeTime) << MMBENCH_KEY_PREFIX << "free"; } TEST_END } TEST_F(KFDMemoryTest, QueryPointerInfo) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; unsigned int bufSize = PAGE_SIZE * 8; // CZ and Tonga need 8 pages HsaPointerInfo ptrInfo; const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); HSAuint64 nGPU = gpuNodes.size(); // number of gpu nodes /* GraphicHandle is tested at KFDGraphicsInterop.RegisterGraphicsHandle */ /*** Memory allocated on CPU node ***/ HsaMemoryBuffer hostBuffer(bufSize, 0/*node*/, false, false/*local*/); EXPECT_SUCCESS(hsaKmtQueryPointerInfo(hostBuffer.As(), &ptrInfo)); EXPECT_EQ(ptrInfo.Type, HSA_POINTER_ALLOCATED); EXPECT_EQ(ptrInfo.Node, 0); EXPECT_EQ(ptrInfo.MemFlags.Value, hostBuffer.Flags().Value); EXPECT_EQ(ptrInfo.CPUAddress, hostBuffer.As()); EXPECT_EQ(ptrInfo.GPUAddress, (HSAuint64)hostBuffer.As()); EXPECT_EQ(ptrInfo.SizeInBytes, (HSAuint64)hostBuffer.Size()); EXPECT_EQ(ptrInfo.MemFlags.ui32.CoarseGrain, 0); if (is_dgpu()) { EXPECT_EQ((HSAuint64)ptrInfo.NMappedNodes, nGPU); // Check NMappedNodes again after unmapping the memory hsaKmtUnmapMemoryToGPU(hostBuffer.As()); hsaKmtQueryPointerInfo(hostBuffer.As(), &ptrInfo); } EXPECT_EQ((HSAuint64)ptrInfo.NMappedNodes, 0); /* Skip testing local memory if the platform does not have it */ if (GetVramSize(defaultGPUNode)) { HsaMemoryBuffer localBuffer(bufSize, defaultGPUNode, false, true); EXPECT_SUCCESS(hsaKmtQueryPointerInfo(localBuffer.As(), &ptrInfo)); EXPECT_EQ(ptrInfo.Type, HSA_POINTER_ALLOCATED); EXPECT_EQ(ptrInfo.Node, defaultGPUNode); EXPECT_EQ(ptrInfo.MemFlags.Value, localBuffer.Flags().Value); EXPECT_EQ(ptrInfo.CPUAddress, localBuffer.As()); EXPECT_EQ(ptrInfo.GPUAddress, (HSAuint64)localBuffer.As()); EXPECT_EQ(ptrInfo.SizeInBytes, (HSAuint64)localBuffer.Size()); EXPECT_EQ(ptrInfo.MemFlags.ui32.CoarseGrain, 1); HSAuint32 *addr = localBuffer.As() + 4; EXPECT_SUCCESS(hsaKmtQueryPointerInfo(reinterpret_cast(addr), &ptrInfo)); EXPECT_EQ(ptrInfo.GPUAddress, (HSAuint64)localBuffer.As()); } /** Registered memory: user pointer */ static volatile HSAuint32 mem[4]; // 8 bytes for register only and // 8 bytes for register to nodes HsaMemoryBuffer hsaBuffer((void *)(&mem[0]), sizeof(HSAuint32)*2); /* * APU doesn't use userptr. * User pointers registered with SVM API, does not create vm_object_t. * Therefore, pointer info can not be queried. */ if (is_dgpu() && mem != hsaBuffer.As()) { EXPECT_SUCCESS(hsaKmtQueryPointerInfo((void *)(&mem[0]), &ptrInfo)); EXPECT_EQ(ptrInfo.Type, HSA_POINTER_REGISTERED_USER); EXPECT_EQ(ptrInfo.CPUAddress, &mem[0]); EXPECT_EQ(ptrInfo.GPUAddress, (HSAuint64)hsaBuffer.As()); EXPECT_EQ(ptrInfo.SizeInBytes, sizeof(HSAuint32)*2); EXPECT_EQ(ptrInfo.NRegisteredNodes, 0); EXPECT_EQ(ptrInfo.NMappedNodes, nGPU); EXPECT_EQ(ptrInfo.MemFlags.ui32.CoarseGrain, 1); // Register to nodes HSAuint32 nodes[nGPU]; for (unsigned int i = 0; i < nGPU; i++) nodes[i] = gpuNodes.at(i); EXPECT_SUCCESS(hsaKmtRegisterMemoryToNodes((void *)(&mem[2]), sizeof(HSAuint32)*2, nGPU, nodes)); EXPECT_SUCCESS(hsaKmtQueryPointerInfo((void *)(&mem[2]), &ptrInfo)); EXPECT_EQ(ptrInfo.NRegisteredNodes, nGPU); EXPECT_SUCCESS(hsaKmtDeregisterMemory((void *)(&mem[2]))); } /* Not a starting address, but an address inside the memory range * should also get the memory information */ HSAuint32 *address = hostBuffer.As() + 1; EXPECT_SUCCESS(hsaKmtQueryPointerInfo(reinterpret_cast(address), &ptrInfo)); EXPECT_EQ(ptrInfo.Type, HSA_POINTER_ALLOCATED); EXPECT_EQ(ptrInfo.CPUAddress, hostBuffer.As()); if (is_dgpu() && &mem[1] != hsaBuffer.As() + 1) { EXPECT_SUCCESS(hsaKmtQueryPointerInfo((void *)(&mem[1]), &ptrInfo)); EXPECT_EQ(ptrInfo.Type, HSA_POINTER_REGISTERED_USER); EXPECT_EQ(ptrInfo.CPUAddress, &mem[0]); } /*** Set user data ***/ char userData[16] = "This is a test."; EXPECT_SUCCESS(hsaKmtSetMemoryUserData(hostBuffer.As(), reinterpret_cast(userData))); EXPECT_SUCCESS(hsaKmtQueryPointerInfo(hostBuffer.As(), &ptrInfo)); EXPECT_EQ(ptrInfo.UserData, (void *)userData); TEST_END } /* Linux OS-specific test for a debugger accessing HSA memory in a * debugged process. * * Allocates a system memory and a visible local memory buffer (if * possible). Forks a child process that PTRACE_ATTACHes to the parent * to access its memory like a debugger would. Child copies data in * the parent process using PTRACE_PEEKDATA and PTRACE_POKEDATA. After * the child terminates, the parent checks that the copy was * successful. */ TEST_F(KFDMemoryTest, PtraceAccess) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemFlags memFlags = {0}; memFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; memFlags.ui32.HostAccess = 1; void *mem[2]; unsigned i; /* Offset in the VRAM buffer to test crossing non-contiguous * buffer boundaries. The second access starting from offset * sizeof(HSAint64)+1 will cross a node boundary in a single access, * for node sizes of 4MB or smaller. */ const HSAuint64 VRAM_OFFSET = (4 << 20) - 2 * sizeof(HSAint64); // Alloc system memory from node 0 and initialize it memFlags.ui32.NonPaged = 0; memFlags.ui32.NoNUMABind = 1; ASSERT_SUCCESS(hsaKmtAllocMemory(0, PAGE_SIZE*2, memFlags, &mem[0])); for (i = 0; i < 4*sizeof(HSAint64) + 4; i++) { (reinterpret_cast(mem[0]))[i] = i; // source (reinterpret_cast(mem[0]))[PAGE_SIZE+i] = 0; // destination } // Try to alloc local memory from GPU node memFlags.ui32.NonPaged = 1; if (m_NodeInfo.IsGPUNodeLargeBar(defaultGPUNode)) { EXPECT_SUCCESS(hsaKmtAllocMemory(defaultGPUNode, PAGE_SIZE*2 + (4 << 20), memFlags, &mem[1])); mem[1] = reinterpret_cast(reinterpret_cast(mem[1]) + VRAM_OFFSET); for (i = 0; i < 4*sizeof(HSAint64) + 4; i++) { (reinterpret_cast(mem[1]))[i] = i; (reinterpret_cast(mem[1]))[PAGE_SIZE+i] = 0; } } else { LOG() << "Not testing local memory, it's invisible" << std::endl; mem[1] = NULL; } /* Allow any process to trace this one. If kernel is built without * Yama, this is not needed, and this call will fail. */ #ifdef PR_SET_PTRACER prctl(PR_SET_PTRACER, PR_SET_PTRACER_ANY, 0, 0, 0); #endif // Find current pid so the child can trace it pid_t tracePid = getpid(); // Fork the child pid_t childPid = fork(); ASSERT_GE(childPid, 0); if (childPid == 0) { int traceStatus; int err = 0, r; /* Child process: we catch any exceptions to make sure we detach * from the traced process, because terminating without detaching * leaves the traced process stopped. */ r = ptrace(PTRACE_ATTACH, tracePid, NULL, NULL); if (r) { WARN() << "PTRACE_ATTACH failed: " << r << std::endl; exit(1); } try { do { waitpid(tracePid, &traceStatus, 0); } while (!WIFSTOPPED(traceStatus)); for (i = 0; i < 4; i++) { // Test 4 different (mis-)alignments, leaving 1-byte gaps between longs HSAuint8 *addr = reinterpret_cast(reinterpret_cast(mem[0]) + i) + i; errno = 0; long data = ptrace(PTRACE_PEEKDATA, tracePid, addr, NULL); EXPECT_EQ(0, errno); EXPECT_EQ(0, ptrace(PTRACE_POKEDATA, tracePid, addr + PAGE_SIZE, reinterpret_cast(data))); if (mem[1] == NULL) continue; addr = reinterpret_cast(reinterpret_cast(mem[1]) + i) + i; errno = 0; data = ptrace(PTRACE_PEEKDATA, tracePid, addr, NULL); EXPECT_EQ(0, errno); EXPECT_EQ(0, ptrace(PTRACE_POKEDATA, tracePid, addr + PAGE_SIZE, reinterpret_cast(data))); } } catch (...) { err = 1; } r = ptrace(PTRACE_DETACH, tracePid, NULL, NULL); if (r) { WARN() << "PTRACE_DETACH failed: " << r << std::endl; exit(1); } exit(err); } else { int childStatus; // Parent process, just wait for the child to finish EXPECT_EQ(childPid, waitpid(childPid, &childStatus, 0)); EXPECT_NE(0, WIFEXITED(childStatus)); EXPECT_EQ(0, WEXITSTATUS(childStatus)); } // Clear gaps in the source that should not have been copied (reinterpret_cast(mem[0]))[ sizeof(long) ] = 0; (reinterpret_cast(mem[0]))[2*sizeof(long) + 1] = 0; (reinterpret_cast(mem[0]))[3*sizeof(long) + 2] = 0; (reinterpret_cast(mem[0]))[4*sizeof(long) + 3] = 0; // Check results EXPECT_EQ(0, memcmp(mem[0], reinterpret_cast(mem[0]) + PAGE_SIZE, sizeof(long)*4 + 4)); // Free memory EXPECT_SUCCESS(hsaKmtFreeMemory(mem[0], PAGE_SIZE*2)); if (mem[1]) { (reinterpret_cast(mem[1]))[ sizeof(HSAint64) ] = 0; (reinterpret_cast(mem[1]))[2*sizeof(HSAint64) + 1] = 0; (reinterpret_cast(mem[1]))[3*sizeof(HSAint64) + 2] = 0; (reinterpret_cast(mem[1]))[4*sizeof(HSAint64) + 3] = 0; EXPECT_EQ(0, memcmp(mem[1], reinterpret_cast(mem[1]) + PAGE_SIZE, sizeof(HSAint64)*4 + 4)); mem[1] = reinterpret_cast(reinterpret_cast(mem[1]) - VRAM_OFFSET); EXPECT_SUCCESS(hsaKmtFreeMemory(mem[1], PAGE_SIZE*2)); } TEST_END } TEST_F(KFDMemoryTest, PtraceAccessInvisibleVram) { char *hsaDebug = getenv("HSA_DEBUG"); if (!is_dgpu()) { LOG() << "Skipping test: There is no VRAM on APU." << std::endl; return; } if (!hsaDebug || !strcmp(hsaDebug, "0")) { LOG() << "Skipping test: HSA_DEBUG environment variable not set." << std::endl; return; } TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemMapFlags mapFlags = {0}; HsaMemFlags memFlags = {0}; memFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; /* Allocate host not accessible vram */ memFlags.ui32.HostAccess = 0; memFlags.ui32.NonPaged = 1; void *mem, *mem0, *mem1; unsigned size = PAGE_SIZE*2 + (4 << 20); HSAuint64 data[2] = {0xdeadbeefdeadbeef, 0xcafebabecafebabe}; unsigned int data0[2] = {0xdeadbeef, 0xdeadbeef}; unsigned int data1[2] = {0xcafebabe, 0xcafebabe}; const HSAuint64 VRAM_OFFSET = (4 << 20) - sizeof(HSAuint64); ASSERT_SUCCESS(hsaKmtAllocMemory(defaultGPUNode, size, memFlags, &mem)); ASSERT_SUCCESS(hsaKmtMapMemoryToGPUNodes(mem, size, NULL, mapFlags, 1, reinterpret_cast(&defaultGPUNode))); /* Set the word before 4M boundary to 0xdeadbeefdeadbeef * and the word after 4M boundary to 0xcafebabecafebabe */ mem0 = reinterpret_cast(reinterpret_cast(mem) + VRAM_OFFSET); mem1 = reinterpret_cast(reinterpret_cast(mem) + VRAM_OFFSET + sizeof(HSAuint64)); PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); queue.PlaceAndSubmitPacket(PM4WriteDataPacket((unsigned int *)mem0, data0[0], data0[1])); queue.PlaceAndSubmitPacket(PM4WriteDataPacket((unsigned int *)mem1, data1[0], data1[1])); queue.PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, true, 0, 0)); queue.Wait4PacketConsumption(); /* Allow any process to trace this one. If kernel is built without * Yama, this is not needed, and this call will fail. */ #ifdef PR_SET_PTRACER prctl(PR_SET_PTRACER, PR_SET_PTRACER_ANY, 0, 0, 0); #endif // Find out my pid so the child can trace it pid_t tracePid = getpid(); // Fork the child pid_t childPid = fork(); ASSERT_GE(childPid, 0); if (childPid == 0) { int traceStatus; int err = 0, r; /* Child process: we catch any exceptions to make sure we detach * from the traced process, because terminating without detaching * leaves the traced process stopped. */ r = ptrace(PTRACE_ATTACH, tracePid, NULL, NULL); if (r) { WARN() << "PTRACE_ATTACH failed: " << r << std::endl; exit(1); } try { do { waitpid(tracePid, &traceStatus, 0); } while (!WIFSTOPPED(traceStatus)); /* Peek the memory */ errno = 0; HSAint64 data0 = ptrace(PTRACE_PEEKDATA, tracePid, mem0, NULL); EXPECT_EQ(0, errno); EXPECT_EQ(data[0], data0); HSAint64 data1 = ptrace(PTRACE_PEEKDATA, tracePid, mem1, NULL); EXPECT_EQ(0, errno); EXPECT_EQ(data[1], data1); /* Swap mem0 and mem1 by poking */ EXPECT_EQ(0, ptrace(PTRACE_POKEDATA, tracePid, mem0, reinterpret_cast(data[1]))); EXPECT_EQ(0, errno); EXPECT_EQ(0, ptrace(PTRACE_POKEDATA, tracePid, mem1, reinterpret_cast(data[0]))); EXPECT_EQ(0, errno); } catch (...) { err = 1; } r = ptrace(PTRACE_DETACH, tracePid, NULL, NULL); if (r) { WARN() << "PTRACE_DETACH failed: " << r << std::endl; exit(1); } exit(err); } else { int childStatus; // Parent process, just wait for the child to finish EXPECT_EQ(childPid, waitpid(childPid, &childStatus, 0)); EXPECT_NE(0, WIFEXITED(childStatus)); EXPECT_EQ(0, WEXITSTATUS(childStatus)); } /* Use shader to read back data to check poke results */ HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); // dstBuffer is cpu accessible gtt memory HsaMemoryBuffer dstBuffer(PAGE_SIZE, defaultGPUNode); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(ScratchCopyDwordIsa, isaBuffer.As())); Dispatch dispatch0(isaBuffer); dispatch0.SetArgs(mem0, dstBuffer.As()); dispatch0.Submit(queue); dispatch0.Sync(); EXPECT_EQ(data1[0], dstBuffer.As()[0]); Dispatch dispatch1(isaBuffer); dispatch1.SetArgs(mem1, dstBuffer.As()); dispatch1.Submit(queue); dispatch1.Sync(); WaitOnValue(dstBuffer.As(), data0[0]); EXPECT_EQ(data0[0], dstBuffer.As()[0]); // Clean up EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(mem)); EXPECT_SUCCESS(hsaKmtFreeMemory(mem, size)); EXPECT_SUCCESS(queue.Destroy()); TEST_END } void CatchSignal(int IntrSignal) { LOG() << "Interrupt Signal " << std::dec << IntrSignal << " Received" << std::endl; } TEST_F(KFDMemoryTest, SignalHandling) { TEST_START(TESTPROFILE_RUNALL) if (!is_dgpu()) { LOG() << "Skipping test: Test not supported on APU." << std::endl; return; } unsigned int *nullPtr = NULL; unsigned int* pDb = NULL; struct sigaction sa; SDMAQueue queue; HSAuint64 size, sysMemSize; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; sa.sa_handler = CatchSignal; sigemptyset(&sa.sa_mask); sa.sa_flags = 0; pid_t ParentPid = getpid(); EXPECT_EQ(0, sigaction(SIGUSR1, &sa, NULL)) << "An error occurred while setting a signal handler"; sysMemSize = GetSysMemSize(); /* System (kernel) memory are limited to 3/8th System RAM * Try to allocate 1/4th System RAM */ size = (sysMemSize >> 2) & ~(HSAuint64)(PAGE_SIZE - 1); /* We don't need a too large buffer for this test. If it is too large, * on some platform, the upcoming hsaKmtAllocMemory() might fail. In * order to avoid this flaky behavior, limit the size to 3G. */ size = size > (3ULL << 30) ? (3ULL << 30) : size; m_MemoryFlags.ui32.NoNUMABind = 1; ASSERT_SUCCESS(hsaKmtAllocMemory(0 /* system */, size, m_MemoryFlags, reinterpret_cast(&pDb))); // Verify that pDb is not null before it's being used EXPECT_NE(nullPtr, pDb) << "hsaKmtAllocMemory returned a null pointer"; pid_t childPid = fork(); ASSERT_GE(childPid, 0); if (childPid == 0) { EXPECT_EQ(0, kill(ParentPid, SIGUSR1)); exit(0); } else { LOG() << "Start Memory Mapping..." << std::endl; ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(pDb, size, NULL)); LOG() << "Mapping finished" << std::endl; int childStatus; pid_t pid; // Parent process, just wait for the child to finish do { pid = waitpid(childPid, &childStatus, 0); } while(pid == -1 && errno == EINTR); EXPECT_EQ(childPid, pid); EXPECT_NE(0, WIFEXITED(childStatus)); EXPECT_EQ(0, WEXITSTATUS(childStatus)); } pDb[0] = 0x02020202; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); queue.PlaceAndSubmitPacket(SDMAWriteDataPacket(queue.GetFamilyId(), pDb, 0x01010101) ); queue.Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(pDb, 0x01010101)); EXPECT_SUCCESS(queue.Destroy()); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(pDb)); // Release the buffers EXPECT_SUCCESS(hsaKmtFreeMemory(pDb, size)); TEST_END } TEST_F(KFDMemoryTest, CheckZeroInitializationSysMem) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); int ret; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HSAuint64 sysMemSizeMB = GetSysMemSize() >> 20; /* Testing system memory */ HSAuint64 * pDb = NULL; HSAuint64 sysBufSizeMB = sysMemSizeMB >> 2; HSAuint64 sysBufSize = sysBufSizeMB * 1024 * 1024; int count = 5; LOG() << "Using " << std::dec << sysBufSizeMB << "MB system buffer to test " << std::dec << count << " times" << std::endl; unsigned int offset = 257; // a constant offset, should be smaller than 512. unsigned int size = sysBufSize / sizeof(*pDb); m_MemoryFlags.ui32.NoNUMABind = 1; while (count--) { ret = hsaKmtAllocMemory(0 /* system */, sysBufSize, m_MemoryFlags, reinterpret_cast(&pDb)); if (ret) { LOG() << "Failed to allocate system buffer of" << std::dec << sysBufSizeMB << "MB" << std::endl; return; } /* Check the first 64 bits */ EXPECT_EQ(0, pDb[0]); pDb[0] = 1; for (HSAuint64 i = offset; i < size;) { EXPECT_EQ(0, pDb[i]); pDb[i] = i + 1; // set it to non zero i += 4096 / sizeof(*pDb); } /* check the last 64 bit */ EXPECT_EQ(0, pDb[size-1]); pDb[size-1] = size; EXPECT_SUCCESS(hsaKmtFreeMemory(pDb, sysBufSize)); } TEST_END } static inline void access(volatile void *sd, int size, int rw) { /* Most likely sitting in cache*/ static struct DUMMY { char dummy[1024]; } dummy; while ((size -= sizeof(dummy)) >= 0) { if (rw == 0) dummy = *(struct DUMMY *)((char*)sd + size); else *(struct DUMMY *)((char*)sd + size) = dummy; } } /* * On large-bar system, test the visible vram access speed. * KFD is not allowed to alloc visible vram on non-largebar system. */ TEST_F(KFDMemoryTest, MMBandWidth) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); unsigned nBufs = 1000; /* measure us, report ns */ unsigned testIndex, sizeIndex, memType; const unsigned nMemTypes = 2; const char *memTypeStrings[nMemTypes] = {"SysMem", "VRAM"}; const unsigned nSizes = 4; const unsigned bufSizes[nSizes] = {PAGE_SIZE, PAGE_SIZE*4, PAGE_SIZE*16, PAGE_SIZE*64}; const unsigned nTests = nSizes * nMemTypes; const unsigned tmpBufferSize = PAGE_SIZE*64; #define _TEST_BUFSIZE(index) (bufSizes[index % nSizes]) #define _TEST_MEMTYPE(index) ((index / nSizes) % nMemTypes) void *bufs[nBufs]; HSAuint64 start; unsigned i; HSAKMT_STATUS ret; HsaMemFlags memFlags = {0}; HsaMemMapFlags mapFlags = {0}; HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HSAuint64 vramSizeMB = GetVramSize(defaultGPUNode) >> 20; LOG() << "Found VRAM of " << std::dec << vramSizeMB << "MB." << std::endl; if (!m_NodeInfo.IsGPUNodeLargeBar(defaultGPUNode) || !vramSizeMB) { LOG() << "Skipping test: Test requires a large bar GPU." << std::endl; return; } void *tmp = mmap(0, tmpBufferSize, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_NE(tmp, MAP_FAILED); memset(tmp, 0, tmpBufferSize); LOG() << "Test (avg. ns)\t memcpyRTime memcpyWTime accessRTime accessWTime" << std::endl; for (testIndex = 0; testIndex < nTests; testIndex++) { unsigned bufSize = _TEST_BUFSIZE(testIndex); unsigned memType = _TEST_MEMTYPE(testIndex); HSAuint64 mcpRTime, mcpWTime, accessRTime, accessWTime; HSAuint32 allocNode; unsigned bufLimit; if ((testIndex & (nSizes-1)) == 0) LOG() << "----------------------------------------------------------------------" << std::endl; if (memType == 0) { allocNode = 0; memFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; memFlags.ui32.HostAccess = 1; memFlags.ui32.NonPaged = 0; memFlags.ui32.NoNUMABind = 1; } else { /* Alloc visible vram*/ allocNode = defaultGPUNode; memFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; memFlags.ui32.HostAccess = 1; memFlags.ui32.NonPaged = 1; /* Buffer sizes are 2MB aligned to match new allocation policy. * Upper limit of buffer number to fit 80% vram size. */ bufLimit = ((vramSizeMB << 20) * 8 / 10) / ALIGN_UP(bufSize, VRAM_ALLOCATION_ALIGN); if (bufLimit == 0) continue; // skip when bufSize > vram /* When vram is too small to fit all the buffers, fill 80% vram size*/ nBufs = std::min(nBufs , bufLimit); } for (i = 0; i < nBufs; i++) ASSERT_SUCCESS(hsaKmtAllocMemory(allocNode, bufSize, memFlags, &bufs[i])); start = GetSystemTickCountInMicroSec(); for (i = 0; i < nBufs; i++) { memcpy(bufs[i], tmp, bufSize); } mcpWTime = GetSystemTickCountInMicroSec() - start; start = GetSystemTickCountInMicroSec(); for (i = 0; i < nBufs; i++) { access(bufs[i], bufSize, 1); } accessWTime = GetSystemTickCountInMicroSec() - start; start = GetSystemTickCountInMicroSec(); for (i = 0; i < nBufs; i++) { memcpy(tmp, bufs[i], bufSize); } mcpRTime = GetSystemTickCountInMicroSec() - start; start = GetSystemTickCountInMicroSec(); for (i = 0; i < nBufs; i++) { access(bufs[i], bufSize, 0); } accessRTime = GetSystemTickCountInMicroSec() - start; for (i = 0; i < nBufs; i++) EXPECT_SUCCESS(hsaKmtFreeMemory(bufs[i], bufSize)); LOG() << std::dec << std::right << std::setw(3) << (bufSize >> 10) << "K-" << std::left << std::setw(14) << memTypeStrings[memType] << std::right << std::setw(12) << mcpRTime << std::setw(12) << mcpWTime << std::setw(12) << accessRTime << std::setw(12) << accessWTime << std::endl; #define MMBANDWIDTH_KEY_PREFIX memTypeStrings[memType] << "-" \ << (bufSize >> 10) << "K" << "-" RECORD(mcpRTime) << MMBANDWIDTH_KEY_PREFIX << "mcpRTime"; RECORD(mcpWTime) << MMBANDWIDTH_KEY_PREFIX << "mcpWTime"; RECORD(accessRTime) << MMBANDWIDTH_KEY_PREFIX << "accessRTime"; RECORD(accessWTime) << MMBANDWIDTH_KEY_PREFIX << "accessWTime"; // skip slow tests if (mcpRTime + mcpWTime + accessRTime + accessWTime > 5000000) break; } munmap(tmp, tmpBufferSize); TEST_END } /* For the purpose of testing HDP flush from CPU. * Use CPU to write to coherent vram and check * from shader. * Asic before gfx9 doesn't support user space * HDP flush so only run on vega10 and after. * This should only run on large bar system. */ TEST_F(KFDMemoryTest, HostHdpFlush) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); HsaMemFlags memoryFlags = m_MemoryFlags; /* buffer[0]: signal; buffer[1]: Input to shader; buffer[2]: Output to * shader */ unsigned int *buffer = NULL; HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; const HsaNodeProperties *pNodeProperties = m_NodeInfo.GetNodeProperties(defaultGPUNode); HSAuint32 *mmioBase = NULL; unsigned int *nullPtr = NULL; if (!pNodeProperties) { LOG() << "Failed to get gpu node properties." << std::endl; return; } if (m_FamilyId < FAMILY_AI) { LOG() << "Skipping test: Test requires gfx9 and later asics." << std::endl; return; } HSAuint64 vramSizeMB = GetVramSize(defaultGPUNode) >> 20; if (!m_NodeInfo.IsGPUNodeLargeBar(defaultGPUNode) || !vramSizeMB) { LOG() << "Skipping test: Test requires a large bar GPU." << std::endl; return; } HsaMemoryProperties *memoryProperties = new HsaMemoryProperties[pNodeProperties->NumMemoryBanks]; EXPECT_SUCCESS(hsaKmtGetNodeMemoryProperties(defaultGPUNode, pNodeProperties->NumMemoryBanks, memoryProperties)); for (unsigned int bank = 0; bank < pNodeProperties->NumMemoryBanks; bank++) { if (memoryProperties[bank].HeapType == HSA_HEAPTYPE_MMIO_REMAP) { mmioBase = (unsigned int *)memoryProperties[bank].VirtualBaseAddress; break; } } if (mmioBase == nullPtr) { LOG() << "Skipping test: bsecause mmioBase is nullPtr, the mmio remap feature is not supported." << std::endl; return; } memoryFlags.ui32.NonPaged = 1; memoryFlags.ui32.CoarseGrain = 0; ASSERT_SUCCESS(hsaKmtAllocMemory(defaultGPUNode, PAGE_SIZE, memoryFlags, reinterpret_cast(&buffer))); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(buffer, PAGE_SIZE, NULL)); /* Signal is dead from the beginning*/ buffer[0] = 0xdead; buffer[1] = 0xfeeb; buffer[2] = 0xfeed; /* Submit a shader to poll the signal*/ PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyOnSignalIsa, isaBuffer.As())); Dispatch dispatch0(isaBuffer); dispatch0.SetArgs(buffer, NULL); dispatch0.Submit(queue); buffer[1] = 0xbeef; /* Flush HDP */ mmioBase[KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL/4] = 0x1; buffer[0] = 0xcafe; /* Check test result*/ dispatch0.Sync(); mmioBase[KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL/4] = 0x1; EXPECT_EQ(0xbeef, buffer[2]); // Clean up EXPECT_SUCCESS(queue.Destroy()); delete [] memoryProperties; EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(buffer)); EXPECT_SUCCESS(hsaKmtFreeMemory(buffer, PAGE_SIZE)); TEST_END } /* Test HDP flush from device. * Use shader on device 1 to write vram of device 0 * and flush HDP of device 0. Read vram from device 0 * and write back to vram to check the result from CPU. * Asic before gfx9 doesn't support device HDP flush * so only run on vega10 and after. * This should only run on system with at least one * large bar node (which is used as device 0). */ TEST_F(KFDMemoryTest, DeviceHdpFlush) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); HsaMemFlags memoryFlags = m_MemoryFlags; /* buffer is physically on device 0. * buffer[0]: Use as signaling b/t devices; * buffer[1]: Device 1 write to buffer[1] and device 0 read it * buffer[2]: Device 0 copy buffer[1] to buffer[2] for CPU to check */ unsigned int *buffer = NULL; const HsaNodeProperties *pNodeProperties; HSAuint32 *mmioBase = NULL; unsigned int *nullPtr = NULL; std::vector nodes; int numPeers; const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); if (gpuNodes.size() < 2) { LOG() << "Skipping test: At least two GPUs are required." << std::endl; return; } /* Users can use "--node=gpu1 --dst_node=gpu2" to specify devices */ if (g_TestDstNodeId != -1 && g_TestNodeId != -1) { nodes.push_back(g_TestNodeId); nodes.push_back(g_TestDstNodeId); if (!m_NodeInfo.IsPeerAccessibleByNode(g_TestDstNodeId, g_TestNodeId)) { LOG() << "Skipping test: first GPU specified is not peer-accessible." << std::endl; return; } if (nodes[0] == nodes[1]) { LOG() << "Skipping test: Different GPUs must be specified (2 GPUs required)." << std::endl; return; } } else { HSAint32 defaultGPU = m_NodeInfo.HsaDefaultGPUNode(); m_NodeInfo.FindAccessiblePeers(&nodes, defaultGPU); if (nodes.size() < 2) { LOG() << "Skipping test: Test requires at least one large bar GPU." << std::endl; LOG() << " or two GPUs are XGMI connected." << std::endl; return; } } const HsaNodeProperties *pNodePropertiesDev1 = NULL; unsigned int m_FamilyIdDev1 = 0; pNodeProperties = m_NodeInfo.GetNodeProperties(nodes[0]); pNodePropertiesDev1 = m_NodeInfo.GetNodeProperties(nodes[1]); if (!pNodeProperties || !pNodePropertiesDev1) { LOG() << "Failed to get gpu node properties." << std::endl; return; } m_FamilyIdDev1 = FamilyIdFromNode(pNodePropertiesDev1); if (m_FamilyId < FAMILY_AI || m_FamilyIdDev1 < FAMILY_AI) { LOG() << "Skipping test: Test requires gfx9 and later asics." << std::endl; return; } if (m_NodeInfo.IsNodeXGMItoCPU(nodes[0])) { LOG() << "Skipping test: PCIe link to CPU is required." << std::endl; return; } if (!m_NodeInfo.IsGPUNodeLargeBar(nodes[0])) { LOG() << "Skipping test: Test requires device 0 large bar GPU." << std::endl; return; } HsaMemoryProperties *memoryProperties = new HsaMemoryProperties[pNodeProperties->NumMemoryBanks]; EXPECT_SUCCESS(hsaKmtGetNodeMemoryProperties(nodes[0], pNodeProperties->NumMemoryBanks, memoryProperties)); for (unsigned int bank = 0; bank < pNodeProperties->NumMemoryBanks; bank++) { if (memoryProperties[bank].HeapType == HSA_HEAPTYPE_MMIO_REMAP) { mmioBase = (unsigned int *)memoryProperties[bank].VirtualBaseAddress; break; } } if (mmioBase == nullPtr) { LOG() << "Skipping test: bsecause mmioBase is nullPtr, the mmio remap feature is not supported." << std::endl; return; } memoryFlags.ui32.NonPaged = 1; memoryFlags.ui32.CoarseGrain = 0; ASSERT_SUCCESS(hsaKmtAllocMemory(nodes[0], PAGE_SIZE, memoryFlags, reinterpret_cast(&buffer))); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(buffer, PAGE_SIZE, NULL)); /* Signal is dead from the beginning*/ buffer[0] = 0xdead; buffer[1] = 0xfeeb; buffer[2] = 0xfeeb; /* Submit shaders*/ PM4Queue queue; ASSERT_SUCCESS(queue.Create(nodes[0])); HsaMemoryBuffer isaBuffer(PAGE_SIZE, nodes[0], true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyOnSignalIsa, isaBuffer.As())); Dispatch dispatch(isaBuffer); dispatch.SetArgs(buffer, NULL); dispatch.Submit(queue); PM4Queue queue0; ASSERT_SUCCESS(queue0.Create(nodes[1])); HsaMemoryBuffer isaBuffer0(PAGE_SIZE, nodes[1], true/*zero*/, false/*local*/, true/*exec*/); /* Temporarily set target ASIC for Dev1 */ ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(WriteAndSignalIsa, isaBuffer0.As(), PAGE_SIZE, GetGfxVersion(pNodePropertiesDev1))); Dispatch dispatch0(isaBuffer0); dispatch0.SetArgs(buffer, mmioBase); dispatch0.Submit(queue0); /* Check test result*/ dispatch0.Sync(); dispatch.Sync(); EXPECT_EQ(0xbeef, buffer[2]); // Clean up EXPECT_SUCCESS(queue.Destroy()); EXPECT_SUCCESS(queue0.Destroy()); delete [] memoryProperties; EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(buffer)); EXPECT_SUCCESS(hsaKmtFreeMemory(buffer, PAGE_SIZE)); TEST_END } /* Test should only run on Arcturus series which has the new RW mtype * Map a local VRAM with RW mtype (coarse grain for upper layer), * read it locally to cache it and write with local SDMA, remote devices( * CPU or Remote GPU shader connected with PCIe or XGMI), * then read again. The second read should get back what SDMA wrote, * since the cache should be invalidated on write and second read * should go to physical VRAM instead of cache. */ TEST_F(KFDMemoryTest, CacheInvalidateOnSdmaWrite) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); HsaMemoryBuffer tmpBuffer(PAGE_SIZE, 0, true /* zero */); volatile HSAuint32 *tmp = tmpBuffer.As(); const int dwLocation = 100; if (m_FamilyId != FAMILY_AR) { LOG() << "Skipping test: Test requires arcturus series asics." << std::endl; return; } HsaMemoryBuffer buffer(PAGE_SIZE, defaultGPUNode, false/*zero*/, true/*local*/, false/*exec*/); SDMAQueue sdmaQueue; ASSERT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); buffer.Fill(0, sdmaQueue, 0, PAGE_SIZE); sdmaQueue.PlacePacket(SDMAWriteDataPacket(sdmaQueue.GetFamilyId(), buffer.As(), 0x5678)); /* Read buffer from shader to fill cache */ PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(PollMemoryIsa, isaBuffer.As())); Dispatch dispatch(isaBuffer); dispatch.SetArgs(buffer.As(), buffer.As()+dwLocation); dispatch.Submit(queue); /* Delay 100ms to make sure shader executed*/ Delay(100); /* SDMA writes to buffer. Shader should get what sdma writes and quits*/ sdmaQueue.SubmitPacket(); sdmaQueue.Wait4PacketConsumption(); /* Check test result*/ dispatch.Sync(); EXPECT_EQ(buffer.IsPattern(dwLocation*sizeof(int), 0x5678, sdmaQueue, tmp), true); // Clean up EXPECT_SUCCESS(queue.Destroy()); EXPECT_SUCCESS(sdmaQueue.Destroy()); TEST_END } TEST_F(KFDMemoryTest, CacheInvalidateOnCPUWrite) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); if (m_FamilyId != FAMILY_AR) { LOG() << "Skipping test: Test requires arcturus series asics." << std::endl; return; } if (!m_NodeInfo.IsGPUNodeLargeBar(defaultGPUNode)) { LOG() << "Skipping test: Test requires a large bar GPU." << std::endl; return; } int *buffer; HsaMemFlags memFlags = {0}; /* Host accessible vram */ memFlags.ui32.HostAccess = 1; memFlags.ui32.NonPaged = 1; memFlags.ui32.CoarseGrain = 1; ASSERT_SUCCESS(hsaKmtAllocMemory(defaultGPUNode, PAGE_SIZE, memFlags, reinterpret_cast(&buffer))); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(buffer, PAGE_SIZE, NULL)); *buffer = 0; /* Read buffer from shader to fill cache */ PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(PollMemoryIsa, isaBuffer.As())); Dispatch dispatch(isaBuffer); dispatch.SetArgs(buffer, buffer+100); dispatch.Submit(queue); /* Delay 100ms to make sure shader executed*/ Delay(100); /* CPU writes to buffer. Shader should get what CPU writes and quits*/ *buffer = 0x5678; /* Check test result*/ dispatch.Sync(); EXPECT_EQ(buffer[100], 0x5678); // Clean up EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(buffer)); EXPECT_SUCCESS(hsaKmtFreeMemory(buffer, PAGE_SIZE)); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDMemoryTest, CacheInvalidateOnRemoteWrite) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); HsaMemoryBuffer tmpBuffer(PAGE_SIZE, 0, true /* zero */); volatile HSAuint32 *tmp = tmpBuffer.As(); const int dwLocation = 100; const int dwLocation1 = 50; if (m_FamilyId != FAMILY_AR) { LOG() << "Skipping test: Test requires arcturus series asics." << std::endl; return; } const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); if (gpuNodes.size() < 2) { LOG() << "Skipping test: At least two GPUs are required." << std::endl; return; } HSAuint32 nondefaultNode; for (unsigned i = 0; i < gpuNodes.size(); i++) { if (gpuNodes.at(i) != defaultGPUNode) { nondefaultNode = gpuNodes.at(i); break; } } HsaMemoryBuffer buffer(PAGE_SIZE, defaultGPUNode, false/*zero*/, true/*local*/, false/*exec*/); buffer.MapMemToNodes(&nondefaultNode, 1); SDMAQueue sdmaQueue; ASSERT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); buffer.Fill(0, sdmaQueue, 0, PAGE_SIZE); /* Read buffer from shader to fill cache */ PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(PollMemoryIsa, isaBuffer.As())); Dispatch dispatch(isaBuffer); dispatch.SetArgs(buffer.As(), buffer.As()+dwLocation); dispatch.Submit(queue); /* Delay 100ms to make sure shader executed*/ Delay(100); /* Using a remote shader to copy data from dwLocation1 to the beginning of the buffer. * Local shader should get what remote writes and quits */ PM4Queue queue1; ASSERT_SUCCESS(queue1.Create(nondefaultNode)); buffer.Fill(0x5678, sdmaQueue, dwLocation1*sizeof(int), 4); HsaMemoryBuffer isaBuffer1(PAGE_SIZE, nondefaultNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); Dispatch dispatch1(isaBuffer1); dispatch1.SetArgs(buffer.As()+dwLocation1, buffer.As()); dispatch1.Submit(queue1); dispatch1.Sync(g_TestTimeOut); /* Check test result*/ dispatch.Sync(); EXPECT_EQ(buffer.IsPattern(dwLocation*sizeof(int), 0x5678, sdmaQueue, tmp), true); // Clean up EXPECT_SUCCESS(queue.Destroy()); EXPECT_SUCCESS(queue1.Destroy()); EXPECT_SUCCESS(sdmaQueue.Destroy()); TEST_END } /* Test is for new cache coherence on Aldebaran. It is to verify * two GPUs can coherently share a fine grain FB. */ TEST_F(KFDMemoryTest, VramCacheCoherenceWithRemoteGPU) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); HsaMemoryBuffer tmpBuffer(PAGE_SIZE, 0, true /* zero */); volatile HSAuint32 *tmp = tmpBuffer.As(); const int dwSource = 0x40 * sizeof(int); /* At 3rd cache line */ const int dwLocation = 0x80 * sizeof(int); /* At 5th cache line */ if (m_FamilyId != FAMILY_AL && m_FamilyId != FAMILY_AV) { LOG() << "Skipping test: Test requires aldebaran or aqua vanjaram series asics." << std::endl; return; } const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); if (gpuNodes.size() < 2) { LOG() << "Skipping test: At least two GPUs are required." << std::endl; return; } HSAuint32 nondefaultNode; for (unsigned i = 0; i < gpuNodes.size(); i++) { if (gpuNodes.at(i) != defaultGPUNode) { nondefaultNode = gpuNodes.at(i); break; } } unsigned int nodes[2] = {defaultGPUNode, nondefaultNode}; /* Allocate a local FB */ HsaMemoryBuffer buffer(PAGE_SIZE, defaultGPUNode, false/*zero*/, true/*local*/, false/*exec*/); buffer.MapMemToNodes(&nodes[0], 2); SDMAQueue sdmaQueue; ASSERT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); buffer.Fill(0, sdmaQueue, 0, PAGE_SIZE); buffer.Fill(0x5678, sdmaQueue, dwSource, 4); /* Read buffer[0] as flag from local shader to fill cache line (64 dws) * which should has 0 at buffer[1] */ PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(PollAndCopyIsa, isaBuffer.As())); Dispatch dispatch(isaBuffer); dispatch.SetArgs(buffer.As(), buffer.As()+dwLocation); dispatch.Submit(queue); /* Delay 100ms to make sure shader executed*/ Delay(100); /* Using remote shader to write the flag and copy value from dwSource * to dwLocation in buffer. * Local shader should get the flag and execute CopyMemory */ PM4Queue queue1; ASSERT_SUCCESS(queue1.Create(nondefaultNode)); HsaMemoryBuffer isaBuffer1(PAGE_SIZE, nondefaultNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(WriteFlagAndValueIsa, isaBuffer1.As())); Dispatch dispatch1(isaBuffer1); dispatch1.SetArgs(buffer.As(), buffer.As()+dwSource); dispatch1.Submit(queue1); dispatch1.Sync(g_TestTimeOut); /* Check test result*/ dispatch.Sync(g_TestTimeOut); EXPECT_EQ(buffer.IsPattern(dwLocation, 0x5678, sdmaQueue, tmp), true); // Clean up EXPECT_SUCCESS(queue.Destroy()); EXPECT_SUCCESS(queue1.Destroy()); EXPECT_SUCCESS(sdmaQueue.Destroy()); TEST_END } /* Test is for new cache coherence on A+A(Aldebaran). It is to verify * new XGMI coherence HW link in caches between CPU and GPUs * in local FB with fine grain mode. */ TEST_F(KFDMemoryTest, VramCacheCoherenceWithCPU) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (m_FamilyId != FAMILY_AL && m_FamilyId != FAMILY_AV) { LOG() << "Skipping test: Test requires aldebaran or aqua vanjaram series asics." << std::endl; return; } HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); const int dwLocation = 0x80; if (!m_NodeInfo.IsNodeXGMItoCPU(defaultGPUNode)) { LOG() << "Skipping test: XGMI link to CPU is required." << std::endl; return; } unsigned int *buffer; HsaMemFlags memFlags = {0}; /* Allocate a fine grain local FB accessed by CPU */ memFlags.ui32.HostAccess = 1; memFlags.ui32.NonPaged = 1; ASSERT_SUCCESS(hsaKmtAllocMemory(defaultGPUNode, PAGE_SIZE, memFlags, reinterpret_cast(&buffer))); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(buffer, PAGE_SIZE, NULL)); buffer[0] = 0; buffer[dwLocation] = 0; /* Read buffer from shader to fill cache */ PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(PollAndCopyIsa, isaBuffer.As())); Dispatch dispatch(isaBuffer); dispatch.SetArgs(buffer, buffer+dwLocation); dispatch.Submit(queue); /* Delay 100ms to make sure shader executed*/ Delay(100); /* CPU writes to buffer. Shader should get 0x5678 CPU writes * after cache invalidating(buffer_invl2) and quits */ buffer[1] = 0x5678; buffer[0] = 1; /* Check test result*/ dispatch.Sync(g_TestTimeOut); EXPECT_EQ(buffer[dwLocation], 0x5678); // Clean up EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(buffer)); EXPECT_SUCCESS(hsaKmtFreeMemory(buffer, PAGE_SIZE)); EXPECT_SUCCESS(queue.Destroy()); TEST_END } /* Test is for new cache coherence on Aldebaran. It is to verify * new XGMI coherence HW link in caches between CPU and GPUs * in system RAM. */ TEST_F(KFDMemoryTest, SramCacheCoherenceWithGPU) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (m_FamilyId != FAMILY_AL && m_FamilyId != FAMILY_AV) { LOG() << "Skipping test: Test requires aldebaran or aqua vanjaram series asics." << std::endl; return; } int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); const int dwLocation = 0x80; if (!m_NodeInfo.IsNodeXGMItoCPU(defaultGPUNode)) { LOG() << "Skipping test: XGMI link to CPU is required." << std::endl; return; } unsigned int *fineBuffer = NULL; unsigned int tmp; ASSERT_SUCCESS(hsaKmtAllocMemory(defaultGPUNode /* system */, PAGE_SIZE, m_MemoryFlags, reinterpret_cast(&fineBuffer))); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(fineBuffer, PAGE_SIZE, NULL)); fineBuffer[0] = 0; fineBuffer[1] = 0; /* Read buffer from CPU to fill cache */ tmp = fineBuffer[dwLocation]; /* Read fine grain buffer from shader to fill cache */ PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(PollAndCopyIsa, isaBuffer.As())); Dispatch dispatch(isaBuffer); dispatch.SetArgs(fineBuffer, fineBuffer+dwLocation); dispatch.Submit(queue); /* Delay 100ms to make sure shader executed*/ Delay(100); /* CPU writes to buffer. Shader should get what CPU writes and quits*/ fineBuffer[1] = 0x5678; fineBuffer[0] = 1; /* Check test result, based on KFDEventTest.SignalEvent passed. * if Sync times out, * it means coherence issue that GPU doesn't read what CPU wrote. * if buffer value is not expected, * it means coherence issue that CPU doesn't read what GPU wrote. */ dispatch.Sync(g_TestTimeOut); EXPECT_EQ(fineBuffer[dwLocation], 0x5678); // Clean up EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(fineBuffer)); EXPECT_SUCCESS(hsaKmtFreeMemory(fineBuffer, PAGE_SIZE)); EXPECT_SUCCESS(queue.Destroy()); TEST_END } void KFDMemoryTest::AcquireReleaseTestRunCPU(HSAuint32 acquireNode, bool scalar) { LOG() << "Testing coherency from CPU to node " << std::dec << acquireNode << std::endl; /* Allocate shared buffer - must be at least 64 * 6 bytes */ HsaMemoryBuffer buffer(PAGE_SIZE, acquireNode, false/*zero*/, false/*local*/, false/*exec*/); buffer.MapMemToNodes(&acquireNode, 1); /* Allocate output buffer and insert magic numbers */ HsaMemoryBuffer outputBuffer(PAGE_SIZE, acquireNode, true, false, false); outputBuffer.As()[0x40] = 99; outputBuffer.As()[0x80] = 99; outputBuffer.As()[0xc0] = 99; outputBuffer.As()[0x100] = 99; outputBuffer.As()[0x140] = 99; /* Flush results of previous tests from the buffer */ /* This would be done with SDMA, but SDMA doesn't work on some Aqua Vanjaram emulators */ PM4Queue flushQueue; ASSERT_SUCCESS(flushQueue.Create(acquireNode)); HsaMemoryBuffer flushBuffer(PAGE_SIZE, acquireNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(FlushBufferForAcquireReleaseIsa, flushBuffer.As())); Dispatch flushDispatch(flushBuffer); flushDispatch.SetArgs(buffer.As(), NULL); flushDispatch.SetDim(1, 1, 1); flushDispatch.Submit(flushQueue); flushDispatch.Sync(g_TestTimeOut); /* Start acquiring thread */ PM4Queue acquireQueue; ASSERT_SUCCESS(acquireQueue.Create(acquireNode)); HsaMemoryBuffer acquireBuffer(PAGE_SIZE, acquireNode, true/*zero*/, false/*local*/, true/*exec*/); if (!scalar) ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(ReadAcquireVectorIsa, acquireBuffer.As())); else ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(ReadAcquireScalarIsa, acquireBuffer.As())); Dispatch acquireDispatch(acquireBuffer); acquireDispatch.SetArgs(buffer.As(), outputBuffer.As()); acquireDispatch.SetDim(1, 1, 1); acquireDispatch.Submit(acquireQueue); /* Delay 100ms to ensure acquirer is waiting */ Delay(100); if (!scalar) { buffer.As()[0x40] = 0x1; buffer.As()[0x80] = 0x2; buffer.As()[0xc0] = 0x3; buffer.As()[0x100] = 0x4; buffer.As()[0x140] = 0x5; } else { buffer.As()[0x40] = 0x6; buffer.As()[0x80] = 0x7; buffer.As()[0xc0] = 0x8; buffer.As()[0x100] = 0x9; buffer.As()[0x140] = 0xa; } buffer.As()[0x0] = 0x1; acquireDispatch.Sync(g_TestTimeOut); /* Check test result*/ if (!scalar) { EXPECT_EQ(0x1, outputBuffer.As()[0x40]); EXPECT_EQ(0x2, outputBuffer.As()[0x80]); EXPECT_EQ(0x3, outputBuffer.As()[0xc0]); EXPECT_EQ(0x4, outputBuffer.As()[0x100]); EXPECT_EQ(0x5, outputBuffer.As()[0x140]); } else { EXPECT_EQ(0x6, outputBuffer.As()[0x40]); EXPECT_EQ(0x7, outputBuffer.As()[0x80]); EXPECT_EQ(0x8, outputBuffer.As()[0xc0]); EXPECT_EQ(0x9, outputBuffer.As()[0x100]); EXPECT_EQ(0xa, outputBuffer.As()[0x140]); } /* * Guide to results: * 0x99: acquiring shader did not write to output buffer at all * 0x77: coherency error. Either releasing shader did not write or acquiring shader read stale value * All five EXPECT_EQ fail: error occurs even when releasing shader bypasses cache * Only first four EXPECT_EQ fail: error occurs only when releasing shader uses cache */ /* Clean up */ EXPECT_SUCCESS(acquireQueue.Destroy()); EXPECT_SUCCESS(flushQueue.Destroy()); } void KFDMemoryTest::AcquireReleaseTestRun(HSAuint32 acquireNode, HSAuint32 releaseNode, bool localToRemote, bool scalar) { LOG() << "Testing coherency from node " << std::dec << releaseNode << " to node " << std::dec << acquireNode << std::endl; /* Allocate shared buffer - must be at least 64 * 6 bytes */ HSAuint32 localNode; if (!localToRemote) localNode = acquireNode; else localNode = releaseNode; HsaMemoryBuffer buffer(PAGE_SIZE, localNode, false/*zero*/, true/*local*/, false/*exec*/); unsigned int nodes[2] = {acquireNode, releaseNode}; buffer.MapMemToNodes(&nodes[0], 2); /* Allocate output buffer and insert magic numbers */ HsaMemoryBuffer outputBuffer(PAGE_SIZE, acquireNode, true, false, false); outputBuffer.As()[0x40] = 99; outputBuffer.As()[0x80] = 99; outputBuffer.As()[0xc0] = 99; outputBuffer.As()[0x100] = 99; outputBuffer.As()[0x140] = 99; /* Flush results of previous tests from the buffer */ /* This would be done with SDMA, but SDMA doesn't work on some Aqua Vanjaram emulators */ PM4Queue flushQueue; ASSERT_SUCCESS(flushQueue.Create(acquireNode)); HsaMemoryBuffer flushBuffer(PAGE_SIZE, acquireNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(FlushBufferForAcquireReleaseIsa, flushBuffer.As())); Dispatch flushDispatch(flushBuffer); flushDispatch.SetArgs(buffer.As(), NULL); flushDispatch.SetDim(1, 1, 1); flushDispatch.Submit(flushQueue); flushDispatch.Sync(g_TestTimeOut); /* Start acquiring thread */ PM4Queue acquireQueue; ASSERT_SUCCESS(acquireQueue.Create(acquireNode)); HsaMemoryBuffer acquireBuffer(PAGE_SIZE, acquireNode, true/*zero*/, false/*local*/, true/*exec*/); if (!scalar) ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(ReadAcquireVectorIsa, acquireBuffer.As())); else ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(ReadAcquireScalarIsa, acquireBuffer.As())); Dispatch acquireDispatch(acquireBuffer); acquireDispatch.SetArgs(buffer.As(), outputBuffer.As()); acquireDispatch.SetDim(1, 1, 1); acquireDispatch.Submit(acquireQueue); /* Delay 100ms to ensure acquirer is waiting */ Delay(100); /* Start releasing thread */ PM4Queue releaseQueue; ASSERT_SUCCESS(releaseQueue.Create(releaseNode)); HsaMemoryBuffer releaseBuffer(PAGE_SIZE, releaseNode, true/*zero*/, false/*local*/, true/*exec*/); if (!scalar) ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(WriteReleaseVectorIsa, releaseBuffer.As())); else ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(WriteReleaseScalarIsa, releaseBuffer.As())); Dispatch releaseDispatch(releaseBuffer); releaseDispatch.SetArgs(buffer.As(), NULL); releaseDispatch.SetDim(1, 1, 1); releaseDispatch.Submit(releaseQueue); /* Wait for threads to finish */ releaseDispatch.Sync(g_TestTimeOut); acquireDispatch.Sync(g_TestTimeOut); /* Check test result*/ if (!scalar) { EXPECT_EQ(0x1, outputBuffer.As()[0x40]); EXPECT_EQ(0x2, outputBuffer.As()[0x80]); EXPECT_EQ(0x3, outputBuffer.As()[0xc0]); EXPECT_EQ(0x4, outputBuffer.As()[0x100]); EXPECT_EQ(0x5, outputBuffer.As()[0x140]); } else { EXPECT_EQ(0x6, outputBuffer.As()[0x40]); EXPECT_EQ(0x7, outputBuffer.As()[0x80]); EXPECT_EQ(0x8, outputBuffer.As()[0xc0]); EXPECT_EQ(0x9, outputBuffer.As()[0x100]); EXPECT_EQ(0xa, outputBuffer.As()[0x140]); } /* * Guide to results: * 0x99: acquiring shader did not write to output buffer at all * 0x77: coherency error. Either releasing shader did not write or acquiring shader read stale value * All five EXPECT_EQ fail: error occurs even when releasing shader bypasses cache * Only first four EXPECT_EQ fail: error occurs only when releasing shader uses cache */ /* Clean up */ EXPECT_SUCCESS(acquireQueue.Destroy()); EXPECT_SUCCESS(releaseQueue.Destroy()); EXPECT_SUCCESS(flushQueue.Destroy()); } /* A test of the memory coherence features on Aqua_Vanjaram. * One shader stores values at 5 positions in memory, then performs * a write-release. The other shader performs a read-acquire, then loads * those 5 values, then stores them in a CPU-visible buffer * * withinGPU: When true, the two shaders will be loaded onto two nodes within * the same GPU. When false, the two shaders will be loaded onto different * GPUs. * * localToRemote: When true, the shared memory will be local to the releasing node. * When false, the shared memory will be local to the acquiring node. * * scalar: When true, the shared data will be stored and loaded with scalar instructions. * When false, the shared data will be stored and loaded with vector instructions. */ void KFDMemoryTest::AcquireReleaseTest(bool withinGPU, bool localToRemote, bool scalar) { if (m_FamilyId != FAMILY_AV) { LOG() << "Skipping test: Test requires aqua vanjaram series asics." << std::endl; return; } /* Find second node - nodes with the same DrmRenderMinor are on the same GPU */ const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); HSAuint32 acquireNode; HSAint32 acquireDRM; bool foundSecondNode = false; for (unsigned i = 0; i < gpuNodes.size(); i++) { acquireNode = gpuNodes.at(i); acquireDRM = m_NodeInfo.GetNodeProperties(acquireNode)->DrmRenderMinor; for (unsigned j = 0; j < gpuNodes.size(); j++) { if (!withinGPU) { if (m_NodeInfo.GetNodeProperties(gpuNodes.at(j))->DrmRenderMinor != acquireDRM) { foundSecondNode = true; AcquireReleaseTestRun(acquireNode, gpuNodes.at(j), localToRemote, scalar); } } else { if (m_NodeInfo.GetNodeProperties(gpuNodes.at(j))->DrmRenderMinor == acquireDRM && gpuNodes.at(j) != acquireNode) { foundSecondNode = true; AcquireReleaseTestRun(acquireNode, gpuNodes.at(j), localToRemote, scalar); } } } } if (!foundSecondNode) { if (!withinGPU) { LOG() << "Skipping test: At least two GPUs are required." << std::endl; } else { LOG() << "Skipping test: At least two nodes on the same GPU are required." << std::endl; } } } TEST_F(KFDMemoryTest, AcquireReleaseCPU) { if (m_FamilyId != FAMILY_AV) { LOG() << "Skipping test: Test requires aqua vanjaram series asics." << std::endl; return; } /* Find second node - nodes with the same DrmRenderMinor are on the same GPU */ const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); HSAuint32 acquireNode; for (unsigned i = 0; i < gpuNodes.size(); i++) { acquireNode = gpuNodes.at(i); AcquireReleaseTestRunCPU(acquireNode, true); AcquireReleaseTestRunCPU(acquireNode, false); } } TEST_F(KFDMemoryTest, AcquireReleaseFarLocalVector) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); AcquireReleaseTest(false /* multi-GPU */, false /* acquirer is local */, false /* vector */); TEST_END } TEST_F(KFDMemoryTest, AcquireReleaseFarLocalScalar) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); AcquireReleaseTest(false /* multi-GPU */, false /* acquirer is local */, true /* scalar */); TEST_END } TEST_F(KFDMemoryTest, AcquireReleaseFarRemoteVector) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); AcquireReleaseTest(false /* multi-GPU */, true /* releaser is local */, false /* vector */); TEST_END } TEST_F(KFDMemoryTest, AcquireReleaseFarRemoteScalar) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); AcquireReleaseTest(false /* multi-GPU */, true /* releaser is local */, true /* scalar */); TEST_END } TEST_F(KFDMemoryTest, AcquireReleaseCloseLocalVector) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); AcquireReleaseTest(true /* within-GPU */, false /* acquirer is local */, false /* vector */); TEST_END } TEST_F(KFDMemoryTest, AcquireReleaseCloseLocalScalar) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); AcquireReleaseTest(true /* within-GPU */, false /* acquirer is local */, true /* scalar */); TEST_END } TEST_F(KFDMemoryTest, AcquireReleaseCloseRemoteVector) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); AcquireReleaseTest(true /* within-GPU */, true /* releaser is local */, false /* vector */); TEST_END } TEST_F(KFDMemoryTest, AcquireReleaseCloseRemoteScalar) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); AcquireReleaseTest(true /* within-GPU */, true /* releaser is local */, true /* scalar */); TEST_END } /* Application register same userptr to multiple GPUs using multiple threads * Test multiple threads register/deregister same userptr, to verify Thunk race handling */ struct ThreadParams { void* pBuf; HSAuint64 BufferSize; HSAuint64 VAGPU; pthread_barrier_t *barrier; }; static unsigned int RegisterThread(void* p) { struct ThreadParams* pArgs = reinterpret_cast(p); pthread_barrier_wait(pArgs->barrier); EXPECT_SUCCESS(hsaKmtRegisterMemory(pArgs->pBuf, pArgs->BufferSize)); EXPECT_SUCCESS(hsaKmtMapMemoryToGPU(pArgs->pBuf, pArgs->BufferSize, &pArgs->VAGPU)); return 0; } static unsigned int UnregisterThread(void* p) { struct ThreadParams* pArgs = reinterpret_cast(p); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(reinterpret_cast(pArgs->VAGPU))); pthread_barrier_wait(pArgs->barrier); EXPECT_SUCCESS(hsaKmtDeregisterMemory(reinterpret_cast(pArgs->VAGPU))); return 0; } #define N_THREADS 32 TEST_F(KFDMemoryTest, MultiThreadRegisterUserptrTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HSAuint32 test_loops = 1; HSAuint64 BufferSize = 1UL << 27; void *pBuf = mmap(NULL, BufferSize, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_NE(pBuf, MAP_FAILED); struct ThreadParams params[N_THREADS]; HSAuint64 threadId[N_THREADS]; pthread_barrier_t barrier; ASSERT_SUCCESS(pthread_barrier_init(&barrier, NULL, N_THREADS)); for (HSAuint32 loop = 0; loop < test_loops; loop++) { for (HSAuint32 i = 0; i < N_THREADS; i++) { params[i].pBuf = pBuf; params[i].BufferSize = BufferSize; params[i].VAGPU = 0; params[i].barrier = &barrier; } for (HSAuint32 i = 0; i < N_THREADS; i++) ASSERT_EQ(true, StartThread(&RegisterThread, ¶ms[i], threadId[i])); for (HSAuint32 i = 0; i < N_THREADS; i++) WaitForThread(threadId[i]); for (HSAuint32 i = 0; i < N_THREADS; i++) ASSERT_EQ(params[0].VAGPU, params[i].VAGPU); for (HSAuint32 i = 0; i < N_THREADS; i++) ASSERT_EQ(true, StartThread(&UnregisterThread, ¶ms[i], threadId[i])); for (HSAuint32 i = 0; i < N_THREADS; i++) WaitForThread(threadId[i]); } pthread_barrier_destroy(&barrier); munmap(pBuf, BufferSize); TEST_END } TEST_F(KFDMemoryTest, ExportDMABufTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (m_VersionInfo.KernelInterfaceMinorVersion < 12) { LOG() << "Skipping test, requires KFD ioctl version 1.12 or newer" << std::endl; return; } HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; // Use a GTT BO for export because it's conveniently CPU accessible. // On multi-GPU systems this also checks for interactions with driver- // internal DMA buf use for DMA attachment to multiple GPUs HsaMemFlags memFlags = m_MemoryFlags; memFlags.ui32.NonPaged = 1; HSAuint32 *buf; ASSERT_SUCCESS(hsaKmtAllocMemory(0, PAGE_SIZE, memFlags, reinterpret_cast(&buf))); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(buf, PAGE_SIZE, NULL)); for (int i = 0; i < PAGE_SIZE/4; i++) buf[i] = i; const HSAuint64 INDEX = 25; const HSAuint64 SIZE = 25; HSAuint64 offset; int fd; // Expected error: address out of range (not a BO) ASSERT_EQ(HSAKMT_STATUS_INVALID_PARAMETER, hsaKmtExportDMABufHandle(buf + PAGE_SIZE/4, SIZE*4, &fd, &offset)); // Expected error: size out of range ASSERT_EQ(HSAKMT_STATUS_INVALID_PARAMETER, hsaKmtExportDMABufHandle(buf + INDEX, PAGE_SIZE, &fd, &offset)); // For real this time. Check that the offset matches ASSERT_SUCCESS(hsaKmtExportDMABufHandle(buf + INDEX, SIZE*4, &fd, &offset)); ASSERT_EQ(INDEX*4, offset); // Free the original BO. The memory should persist as long as the DMA buf // handle exists. ASSERT_SUCCESS(hsaKmtUnmapMemoryToGPU(buf)); ASSERT_SUCCESS(hsaKmtFreeMemory(buf, PAGE_SIZE)); // Import the BO using the Interop API and check the contents. It doesn't // map the import for CPU access, which gives us an excuse to test GPU // mapping of the imported BO as well. HsaGraphicsResourceInfo info; ASSERT_SUCCESS(hsaKmtRegisterGraphicsHandleToNodes(fd, &info, 1, &defaultGPUNode)); buf = reinterpret_cast(info.MemoryAddress); ASSERT_EQ(info.SizeInBytes, PAGE_SIZE); HsaMemMapFlags mapFlags = {0}; ASSERT_SUCCESS(hsaKmtMapMemoryToGPUNodes(buf, PAGE_SIZE, NULL, mapFlags, 1, &defaultGPUNode)); PM4Queue pm4Queue; ASSERT_SUCCESS(pm4Queue.Create(defaultGPUNode)); HsaMemoryBuffer dstBuffer(PAGE_SIZE, defaultGPUNode); HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); for (int i = 0; i < PAGE_SIZE/4; i++) { Dispatch dispatch(isaBuffer); dispatch.SetArgs(&buf[i], dstBuffer.As()); dispatch.Submit(pm4Queue); dispatch.Sync(g_TestTimeOut); ASSERT_EQ(i, *dstBuffer.As()); } ASSERT_SUCCESS(pm4Queue.Destroy()); ASSERT_SUCCESS(hsaKmtUnmapMemoryToGPU(buf)); ASSERT_SUCCESS(hsaKmtDeregisterMemory(buf)); ASSERT_EQ(0, close(fd)); TEST_END } TEST_F(KFDMemoryTest, VA_VRAM_Only_AllocTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (m_VersionInfo.KernelInterfaceMinorVersion < 12) { LOG() << "Skipping test, requires KFD ioctl version 1.12 or newer" << std::endl; return; } HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemFlags memFlags = m_MemoryFlags; memFlags.ui32.NonPaged = 1; memFlags.ui32.HostAccess = 0; HsaMemMapFlags mapFlags = {0}; HSAuint32 *buf; /*alloc va without vram alloc*/ memFlags.ui32.OnlyAddress = 1; ASSERT_SUCCESS(hsaKmtAllocMemory(defaultGPUNode, PAGE_SIZE, memFlags, reinterpret_cast(&buf))); /*mapping VA allocated by kfd api would fail*/ ASSERT_EQ(HSAKMT_STATUS_INVALID_PARAMETER, hsaKmtMapMemoryToGPU(buf, PAGE_SIZE, NULL)); ASSERT_EQ(HSAKMT_STATUS_INVALID_PARAMETER, hsaKmtMapMemoryToGPUNodes(buf, PAGE_SIZE, NULL, mapFlags, 1, reinterpret_cast(&defaultGPUNode))); ASSERT_SUCCESS(hsaKmtFreeMemory(buf, PAGE_SIZE)); /*alloc vram without va assigned*/ memFlags.ui32.OnlyAddress = 0; memFlags.ui32.NoAddress = 1; ASSERT_SUCCESS(hsaKmtAllocMemory(defaultGPUNode, PAGE_SIZE, memFlags, reinterpret_cast(&buf))); /*mapping handle allocated by kfd API would fail*/ ASSERT_EQ(HSAKMT_STATUS_INVALID_PARAMETER, hsaKmtMapMemoryToGPU(buf, PAGE_SIZE, NULL)); ASSERT_EQ(HSAKMT_STATUS_INVALID_PARAMETER, hsaKmtMapMemoryToGPUNodes(buf, PAGE_SIZE, NULL, mapFlags, 1, reinterpret_cast(&defaultGPUNode))); ASSERT_SUCCESS(hsaKmtFreeMemory(buf, PAGE_SIZE)); TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDMemoryTest.hpp000066400000000000000000000042241446477712600250040ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDBaseComponentTest.hpp" #ifndef __KFD_MEMORY_TEST__H__ #define __KFD_MEMORY_TEST__H__ /* @class KFDTopologyTest * This class has no additional features to KFDBaseComponentTest * The separation was made so we are able to group all memory tests together */ class KFDMemoryTest : public KFDBaseComponentTest { public: KFDMemoryTest(void) {} ~KFDMemoryTest(void) {} protected: virtual void SetUp(); virtual void TearDown(); protected: void BinarySearchLargestBuffer(int allocNode, const HsaMemFlags &memFlags, HSAuint64 highMB, int nodeToMap, HSAuint64 *lastSizeMB); void AcquireReleaseTestRunCPU(HSAuint32 acquireNode, bool scalar); void AcquireReleaseTestRun(HSAuint32 acquireNode, HSAuint32 releaseNode, bool localToRemote, bool scalar); void AcquireReleaseTest(bool withinGPU, bool localToRemote, bool scalar); }; #endif // __KFD_MEMORY_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDMultiProcessTest.cpp000066400000000000000000000051311446477712600261560ustar00rootroot00000000000000/* * Copyright (C) 2019 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDMultiProcessTest.hpp" void KFDMultiProcessTest::ForkChildProcesses(int nprocesses) { int i; for (i = 0; i < nprocesses - 1; ++i) { pid_t pid = fork(); ASSERT_GE(pid, 0); if (pid == 0) { /* Child process */ /* Cleanup file descriptors copied from parent process * then call SetUp->hsaKmtOpenKFD to create new process */ m_psName = "Test process " + std::to_string(i) + " "; TearDown(); SetUp(); m_ChildPids.clear(); m_IsParent = false; m_ProcessIndex = i; return; } /* Parent process */ m_ChildPids.push_back(pid); } m_psName = "Test process " + std::to_string(i) + " "; m_ProcessIndex = i; } void KFDMultiProcessTest::WaitChildProcesses() { if (m_IsParent) { /* Only run by parent process */ int childStatus; int childExitOkNum = 0; int size = m_ChildPids.size(); for (HSAuint32 i = 0; i < size; i++) { pid_t pid = m_ChildPids.front(); waitpid(pid, &childStatus, 0); if (WIFEXITED(childStatus) == 1 && WEXITSTATUS(childStatus) == 0) childExitOkNum++; m_ChildPids.erase(m_ChildPids.begin()); } EXPECT_EQ(childExitOkNum, size); } /* Child process or parent process finished successfully */ m_ChildStatus = HSAKMT_STATUS_SUCCESS; } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDMultiProcessTest.hpp000066400000000000000000000042001446477712600261570ustar00rootroot00000000000000/* * Copyright (C) 2019 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_MULTI_PROCESS_TEST__H__ #define __KFD_MULTI_PROCESS_TEST__H__ #include #include #include "KFDBaseComponentTest.hpp" // @class KFDMultiProcessTest // Base class for tests forking multiple child processes class KFDMultiProcessTest : public KFDBaseComponentTest { public: KFDMultiProcessTest(void): m_ChildStatus(HSAKMT_STATUS_ERROR), m_IsParent(true) {} ~KFDMultiProcessTest(void) { if (!m_IsParent) { /* Child process has to exit * otherwise gtest will continue other tests */ exit(m_ChildStatus); } try { WaitChildProcesses(); } catch (...) {} } protected: void ForkChildProcesses(int nprocesses); void WaitChildProcesses(); protected: // Members std::string m_psName; int m_ProcessIndex; std::vector m_ChildPids; HSAKMT_STATUS m_ChildStatus; bool m_IsParent; }; #endif // __KFD_MULTI_PROCESS_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDOpenCloseKFDTest.cpp000066400000000000000000000055311446477712600257450ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDOpenCloseKFDTest.hpp" #include "KFDTestUtil.hpp" // Before every test from this class fixture, open KFD void KFDOpenCloseKFDTest::SetUp() { ROUTINE_START ASSERT_SUCCESS(hsaKmtOpenKFD() ); ROUTINE_END } // After every test from this class fixture, close KFD void KFDOpenCloseKFDTest::TearDown() { ROUTINE_START EXPECT_SUCCESS(hsaKmtCloseKFD() ); ROUTINE_END } /* This test does not use class KFDOpenCloseKFDTest but is placed here * since it's testing same topic as other test * Verify that calling hsaKmtCloseKFD on a closed KFD will return right status */ TEST(KFDCloseKFDTest, CloseAClosedKfd ) { TEST_START(TESTPROFILE_RUNALL) ASSERT_EQ(HSAKMT_STATUS_KERNEL_IO_CHANNEL_NOT_OPENED, hsaKmtCloseKFD()); TEST_END } // Verify that calling hsaKmtCloseKFD on an already opened KFD will return right status TEST_F(KFDOpenCloseKFDTest, OpenAlreadyOpenedKFD ) { TEST_START(TESTPROFILE_RUNALL) EXPECT_EQ(HSAKMT_STATUS_KERNEL_ALREADY_OPENED, hsaKmtOpenKFD()); EXPECT_SUCCESS(hsaKmtCloseKFD()); TEST_END } // Testing the normal scenario: open followed by close (done in the setup and teardown functions) TEST_F(KFDOpenCloseKFDTest, OpenCloseKFD ) { } TEST_F(KFDOpenCloseKFDTest, InvalidKFDHandleTest ) { TEST_START(TESTPROFILE_RUNALL) HsaVersionInfo m_VersionInfo; pid_t m_ChildPid = fork(); if (m_ChildPid == 0) { EXPECT_EQ(HSAKMT_STATUS_KERNEL_IO_CHANNEL_NOT_OPENED, hsaKmtGetVersion(&m_VersionInfo)); exit(0); } else { int childStatus; EXPECT_EQ(m_ChildPid, waitpid(m_ChildPid, &childStatus, 0)); EXPECT_NE(0, WIFEXITED(childStatus)); EXPECT_EQ(0, WEXITSTATUS(childStatus)); } TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDOpenCloseKFDTest.hpp000066400000000000000000000033331446477712600257500ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include #include "hsakmt.h" #ifndef __KFD_OPEN_CLOSE_KFD_TEST__H__ #define __KFD_OPEN_CLOSE_KFD_TEST__H__ // @class KFDOpenCloseKFDTest class KFDOpenCloseKFDTest : public testing::Test { public: KFDOpenCloseKFDTest(void) {} ~KFDOpenCloseKFDTest(void) {} protected: // @brief Executed before every test that uses KFDOpenCloseKFDTest class, sets all common settings for the tests. virtual void SetUp(); // @brief Executed after every test that uses KFDOpenCloseKFDTest class virtual void TearDown(); }; #endif // __KFD_OPEN_CLOSE_KFD_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDPMTest.cpp000066400000000000000000000063331446477712600240460ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDPMTest.hpp" #include "KFDTestUtil.hpp" #include "PM4Packet.hpp" #include "PM4Queue.hpp" #include "hsakmt.h" void KFDPMTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); ROUTINE_END } void KFDPMTest::TearDown() { ROUTINE_START KFDBaseComponentTest::TearDown(); ROUTINE_END } TEST_F(KFDPMTest, SuspendWithActiveProcess) { TEST_START(TESTPROFILE_RUNALL) EXPECT_EQ(true, SuspendAndWakeUp()); TEST_END } TEST_F(KFDPMTest, SuspendWithIdleQueue) { TEST_START(TESTPROFILE_RUNALL) PM4Queue queue; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); EXPECT_EQ(true, SuspendAndWakeUp()); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDPMTest, SuspendWithIdleQueueAfterWork) { TEST_START(TESTPROFILE_RUNALL) PM4Queue queue; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer destBuffer(PAGE_SIZE, defaultGPUNode); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaEvent *event; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &event)); queue.PlaceAndSubmitPacket(PM4WriteDataPacket(destBuffer.As(), 0x1, 0x2)); queue.Wait4PacketConsumption(event); WaitOnValue(&(destBuffer.As()[0]), 0x1); WaitOnValue(&(destBuffer.As()[1]), 0x2); destBuffer.Fill(0); EXPECT_EQ(true, SuspendAndWakeUp()); queue.PlaceAndSubmitPacket(PM4WriteDataPacket(&(destBuffer.As()[2]), 0x3, 0x4)); queue.Wait4PacketConsumption(event); EXPECT_EQ(destBuffer.As()[0], 0); EXPECT_EQ(destBuffer.As()[1], 0); WaitOnValue(&(destBuffer.As()[2]), 0x3); WaitOnValue(&(destBuffer.As()[3]), 0x4); hsaKmtDestroyEvent(event); EXPECT_SUCCESS(queue.Destroy()); TEST_END } // TODO: Suspend while workload is being executed by a queue ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDPMTest.hpp000066400000000000000000000027031446477712600240500ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFDPMTEST_HPP__ #define __KFDPMTEST_HPP__ #include #include "KFDBaseComponentTest.hpp" class KFDPMTest : public KFDBaseComponentTest { public: KFDPMTest() {} ~KFDPMTest() {} protected: virtual void SetUp(); virtual void TearDown(); }; #endif // __KFDPMTEST_HPP__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDPerfCounters.cpp000066400000000000000000000257551446477712600253220ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDPerfCounters.hpp" void KFDPerfCountersTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); ROUTINE_END } void KFDPerfCountersTest::TearDown() { ROUTINE_START KFDBaseComponentTest::TearDown(); ROUTINE_END } static struct block_name_table { char name[32]; HSA_UUID uuid; } block_lookup_table[] = { {"CB ", {0x9ba429c6, 0xaf2d, 0x4b38, 0xb3, 0x49, 0x15, 0x72, 0x71, 0xbe, 0xac, 0x6a}}, {"CPF ", {0x2b0ad2b5, 0x1c43, 0x4f46, 0xa7, 0xbc, 0xe1, 0x19, 0x41, 0x1e, 0xa6, 0xc9}}, {"CPG ", {0x590ec94d, 0x20f0, 0x448f, 0x8d, 0xff, 0x31, 0x6c, 0x67, 0x9d, 0xe7, 0xff}}, {"DB ", {0x3d1a47fc, 0x0013, 0x4ed4, 0x83, 0x06, 0x82, 0x2c, 0xa0, 0xb7, 0xa6, 0xc2}}, {"GDS ", {0xf59276ec, 0x2526, 0x4bf8, 0x8e, 0xc0, 0x11, 0x8f, 0x77, 0x70, 0x0d, 0xc9}}, {"GRBM ", {0x8f00933c, 0xc33d, 0x4801, 0x97, 0xb7, 0x70, 0x07, 0xf7, 0x85, 0x73, 0xad}}, {"GRBMSE ", {0x34ebd8d7, 0x7c8b, 0x4d15, 0x88, 0xfa, 0x0e, 0x4e, 0x4a, 0xf5, 0x9a, 0xc1}}, {"IA ", {0x34276944, 0x4264, 0x4fcd, 0x9d, 0x6e, 0xae, 0x26, 0x45, 0x82, 0xec, 0x51}}, {"MC ", {0x13900b57, 0x4956, 0x4d98, 0x81, 0xd0, 0x68, 0x52, 0x19, 0x37, 0xf5, 0x9c}}, {"PASC ", {0xb0e7fb5d, 0x0efc, 0x4744, 0xb5, 0x16, 0x5d, 0x23, 0xdc, 0x1f, 0xd5, 0x6c}}, {"PASU ", {0x9a152b6a, 0x1fad, 0x45f2, 0xa5, 0xbf, 0xf1, 0x63, 0x82, 0x6b, 0xd0, 0xcd}}, {"SPI ", {0xeda81044, 0xd62c, 0x47eb, 0xaf, 0x89, 0x4f, 0x6f, 0xbf, 0x3b, 0x38, 0xe0}}, {"SRBM ", {0x9f8040e0, 0x6830, 0x4019, 0xac, 0xc8, 0x46, 0x3c, 0x9e, 0x44, 0x5b, 0x89}}, {"SQ ", {0xb5c396b6, 0xd310, 0x47e4, 0x86, 0xfc, 0x5c, 0xc3, 0x4, 0x3a, 0xf5, 0x8}}, {"SX ", {0xbdb8d737, 0x43cc, 0x4162, 0xbe, 0x52, 0x51, 0xcf, 0xb8, 0x47, 0xbe, 0xaf}}, {"TA ", {0xc01ee43d, 0xad92, 0x44b1, 0x8a, 0xb9, 0xbe, 0x5e, 0x69, 0x6c, 0xee, 0xa7}}, {"TCA ", {0x333e393f, 0xe147, 0x4f49, 0xa6, 0xd1, 0x60, 0x91, 0x4c, 0x70, 0x86, 0xb0}}, {"TCC ", {0x848ce855, 0xd805, 0x4566, 0xa8, 0xab, 0x73, 0xe8, 0x84, 0xcc, 0x6b, 0xff}}, {"TCP ", {0xe10a013b, 0x17d4, 0x4bf5, 0xb0, 0x89, 0x42, 0x95, 0x91, 0x05, 0x9b, 0x60}}, {"TCS ", {0x4126245c, 0x4d96, 0x4d1a, 0x8a, 0xed, 0xa9, 0x39, 0xd4, 0xcc, 0x8e, 0xc9}}, {"TD ", {0x7d7c0fe4, 0xfe41, 0x4fea, 0x92, 0xc9, 0x45, 0x44, 0xd7, 0x70, 0x6d, 0xc6}}, {"VGT ", {0x0b6a8cb7, 0x7a01, 0x409f, 0xa2, 0x2c, 0x30, 0x14, 0x85, 0x4f, 0x13, 0x59}}, {"WD ", {0x0e176789, 0x46ed, 0x4b02, 0x97, 0x2a, 0x91, 0x6d, 0x2f, 0xac, 0x24, 0x4a}}, {"IOMMUV2", {0x80969879, 0xb0f6, 0x4be6, 0x97, 0xf6, 0x6a, 0x63, 0x0, 0xf5, 0x10, 0x1d}}, {"DRIVER ", {0xea9b5ae1, 0x6c3f, 0x44b3, 0x89, 0x54, 0xda, 0xf0, 0x75, 0x65, 0xa9, 0xa}} }; void KFDPerfCountersTest::GetBlockName(HSA_UUID uuid, char *name, uint32_t name_len, char *uuid_str, uint32_t uuid_str_len) { uint32_t i, table_size; table_size = sizeof(block_lookup_table) / sizeof(struct block_name_table); snprintf(name, name_len, "unknown"); for (i = 0; i < table_size; i++) { if (!memcmp(&block_lookup_table[i].uuid, &uuid, sizeof(HSA_UUID))) { if (name) snprintf(name, name_len, "%s", block_lookup_table[i].name); break; } } if (uuid_str) snprintf(uuid_str, uuid_str_len, "%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x", uuid.Data1, uuid.Data2, uuid.Data3, uuid.Data4[0], uuid.Data4[1], uuid.Data4[2], uuid.Data4[3], uuid.Data4[4], uuid.Data4[5], uuid.Data4[6], uuid.Data4[7]); } TEST_F(KFDPerfCountersTest, GetCounterProperties) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaCounterProperties* pProps = NULL; ASSERT_SUCCESS(hsaKmtPmcGetCounterProperties(defaultGPUNode, &pProps)); /* Verifying that there is at least one block */ ASSERT_NE(0, pProps->NumBlocks) << "No performance counters blocks"; LOG() << std::dec << pProps->NumBlocks << " blocks found." << std::endl; HsaCounterBlockProperties *block; block = &pProps->Blocks[0]; for (HSAuint32 i = 0; i < pProps->NumBlocks; i++) { char uuid_string[37] = ""; char name[32] = ""; GetBlockName(block->BlockId, name, 32, uuid_string, 37); char type[32]; switch (block->Counters[0].Type) { case HSA_PROFILE_TYPE_PRIVILEGED_IMMEDIATE: snprintf(type, sizeof(type), "Priv Immediate"); break; case HSA_PROFILE_TYPE_PRIVILEGED_STREAMING: snprintf(type, sizeof(type), "Priv Streaming"); break; case HSA_PROFILE_TYPE_NONPRIV_IMMEDIATE: snprintf(type, sizeof(type), "Non-priv Immediate"); break; case HSA_PROFILE_TYPE_NONPRIV_STREAMING: snprintf(type, sizeof(type), "Non-priv Immediate"); break; default: snprintf(type, sizeof(type), "Unknown"); break; } LOG() << name << " (" << uuid_string << "): " << type << ", " << block->NumCounters << " counter IDs" << std::endl; block = reinterpret_cast(&block->Counters[block->NumCounters]); } TEST_END } TEST_F(KFDPerfCountersTest, RegisterTrace) { TEST_START(TESTPROFILE_RUNALL) HsaCounterProperties* pProps; HsaPmcTraceRoot root; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; pProps = NULL; ASSERT_SUCCESS(hsaKmtPmcGetCounterProperties(defaultGPUNode, &pProps)); /* Verifying that there is at least one block */ ASSERT_NE(0, pProps->NumBlocks) << "No performance counters blocks"; HsaCounterBlockProperties *block = &pProps->Blocks[0]; bool priv_block_found = false; for (HSAuint32 i = 0; i < pProps->NumBlocks; i++) { if (block->Counters[0].Type <= HSA_PROFILE_TYPE_PRIVILEGED_STREAMING) { priv_block_found = true; break; } block = reinterpret_cast(&block->Counters[block->NumCounters]); } if (!priv_block_found) { LOG() << "Skipping test: No privileged block is found." << std::endl; return; } /* Registering trace */ ASSERT_SUCCESS(hsaKmtPmcRegisterTrace(defaultGPUNode, block->NumConcurrent, block->Counters, &root)); EXPECT_SUCCESS(hsaKmtPmcUnregisterTrace(defaultGPUNode, root.TraceId)); TEST_END } TEST_F(KFDPerfCountersTest, StartStopQueryTrace) { TEST_START(TESTPROFILE_RUNALL) HsaPmcTraceRoot root; HsaCounterProperties* pProps; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; pProps = NULL; ASSERT_SUCCESS(hsaKmtPmcGetCounterProperties(defaultGPUNode, &pProps)); /* Verifying that there is at least one block */ ASSERT_NE(0, pProps->NumBlocks) << "No performance counters blocks"; HsaCounterBlockProperties *block = &pProps->Blocks[0]; bool priv_block_found = false; for (HSAuint32 i = 0; i < pProps->NumBlocks; i++) { if (block->Counters[0].Type <= HSA_PROFILE_TYPE_PRIVILEGED_STREAMING) { priv_block_found = true; break; } block = reinterpret_cast(&block->Counters[block->NumCounters]); } if (!priv_block_found) { LOG() << "Skipping test: No privileged block is found." << std::endl; return; } if (getuid()) { /* Non-root */ LOG() << "Skipping test: Privileged counters requires the user as root." << std::endl; return; } /* Registering trace */ ASSERT_SUCCESS(hsaKmtPmcRegisterTrace(defaultGPUNode, block->NumConcurrent, block->Counters, &root)); /* Acquiring access for the trace */ ASSERT_SUCCESS(hsaKmtPmcAcquireTraceAccess(defaultGPUNode, root.TraceId)); /* Allocating memory buffer for the trace */ HsaMemoryBuffer membuf(PAGE_SIZE, defaultGPUNode); /* Starting the trace */ ASSERT_SUCCESS(hsaKmtPmcStartTrace(root.TraceId, membuf.As(), membuf.Size())); /* Delay between START and STOP tracing */ Delay(START_STOP_DELAY); /* Stopping the trace */ ASSERT_SUCCESS(hsaKmtPmcStopTrace(root.TraceId)); /* Querying the trace */ ASSERT_SUCCESS(hsaKmtPmcQueryTrace(root.TraceId)); uint64_t *buf = membuf.As(); for (uint32_t i = 0; i < block->NumConcurrent; i++, buf++) LOG() << "Counter " << std::dec << i << ": " << *buf << std::endl; /* Releasing the trace */ EXPECT_SUCCESS(hsaKmtPmcReleaseTraceAccess(0, root.TraceId)); EXPECT_SUCCESS(hsaKmtPmcUnregisterTrace(defaultGPUNode, root.TraceId)); TEST_END } TEST_F(KFDPerfCountersTest, ClockCountersBasicTest) { TEST_START(TESTPROFILE_RUNALL) HsaClockCounters counters1; HsaClockCounters counters2; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; EXPECT_SUCCESS(hsaKmtGetClockCounters(defaultGPUNode, &counters1)); Delay(100); EXPECT_SUCCESS(hsaKmtGetClockCounters(defaultGPUNode, &counters2)); EXPECT_NE(0, counters1.GPUClockCounter); EXPECT_NE(0, counters2.GPUClockCounter); EXPECT_NE(0, counters1.SystemClockCounter); EXPECT_NE(0, counters2.SystemClockCounter); EXPECT_GT(counters2.GPUClockCounter, counters1.GPUClockCounter); EXPECT_GT(counters2.SystemClockCounter, counters1.SystemClockCounter); TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDPerfCounters.hpp000066400000000000000000000033231446477712600253120ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFDPERFCOUNTERS_HPP__ #define __KFDPERFCOUNTERS_HPP__ #include #include "KFDBaseComponentTest.hpp" class KFDPerfCountersTest : public KFDBaseComponentTest { public: KFDPerfCountersTest() {} ~KFDPerfCountersTest() {} static const unsigned int START_STOP_DELAY = 10000; // 10 sec tracing protected: virtual void SetUp(); virtual void TearDown(); void GetBlockName(HSA_UUID uuid, char *name, uint32_t name_len, char *uuid_str, uint32_t uuid_str_len); }; #endif // __KFDPERFCOUNTERS_HPP__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDPerformanceTest.cpp000066400000000000000000000322241446477712600257710ustar00rootroot00000000000000/* * Copyright (C) 2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include "PM4Queue.hpp" #include "PM4Packet.hpp" #include "SDMAPacket.hpp" #include "SDMAQueue.hpp" #include "AqlQueue.hpp" #include "KFDTestUtilQueue.hpp" #include #include #include "KFDBaseComponentTest.hpp" class KFDPerformanceTest: public KFDBaseComponentTest { protected: virtual void SetUp(); virtual void TearDown(); }; void KFDPerformanceTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); ROUTINE_END } void KFDPerformanceTest::TearDown() { ROUTINE_START KFDBaseComponentTest::TearDown(); ROUTINE_END } enum P2PDirection { IN = 1, OUT = 2, IN_OUT = 3, NONE = 4, }; /* * Do the copy of one GPU from & to multiple GPUs. */ static void testNodeToNodes(HSAuint32 n1, const HSAuint32 *const n2Array, int n, P2PDirection n1Direction, P2PDirection n2Direction, HSAuint64 size, HSAuint64 *speed, HSAuint64 *speed2, std::stringstream *msg, bool isTestOverhead = false, HSAuint64 *time = 0) { ASSERT_GT(16, unsigned(n - 1)); HSAuint32 n2[n]; void *n1Mem, *n2Mem[n]; HsaMemFlags memFlags = {0}; memFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; memFlags.ui32.HostAccess = 0; memFlags.ui32.NonPaged = 1; SDMACopyParams array[n * 4]; int array_count = 0; HSAuint64 alloc_size = ALIGN_UP(size, PAGE_SIZE); std::vector copyArray; int i; ASSERT_SUCCESS(hsaKmtAllocMemory(n1, alloc_size, memFlags, &n1Mem)); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(n1Mem, alloc_size, NULL)); for (i = 0; i < n; i++) { n2[i] = n2Array[i]; ASSERT_SUCCESS(hsaKmtAllocMemory(n2[i], alloc_size, memFlags, &n2Mem[i])); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(n2Mem[i], alloc_size, NULL)); } for (i = 0; i < n; i++) { if (n1Direction != NONE) ASSERT_NE(n1, 0); if (n2Direction != NONE) ASSERT_NE(n2[i], 0); do { if (n1Direction == IN || n1Direction == IN_OUT) /* n2Mem -> n1Mem*/ array[array_count++] = {n1, n2Mem[i], n1Mem, size, n1/*group id, just a hint*/}; if (n1Direction == OUT || n1Direction == IN_OUT) /* n1Mem -> n2Mem*/ array[array_count++] = {n1, n1Mem, n2Mem[i], size, n1}; /* Issue two copies to make full use of sdma.*/ } while (n1Direction < IN_OUT && n == 1 && array_count % 2); /* Do nothing if no IN or OUT specified.*/ do { if (n2Direction == IN || n2Direction == IN_OUT) /* n1Mem -> n2Mem*/ array[array_count++] = {n2[i], n1Mem, n2Mem[i], size, n2[i]}; if (n2Direction == OUT || n2Direction == IN_OUT) /* n2Mem -> n1Mem*/ array[array_count++] = {n2[i], n2Mem[i], n1Mem, size, n2[i]}; } while (n2Direction < IN_OUT && array_count % 2); } /* We measure a bunch of packets.*/ if (isTestOverhead) { for (i = 0; i < 1000; i++) for (int j = 0; j < array_count; j++) copyArray.push_back(array[j]); sdma_multicopy(copyArray, 1, HEAD_TAIL); *time = CounterToNanoSec(copyArray[0].timeConsumption / (1000 * array_count)); } else /* It did not respect the group id we set above.*/ sdma_multicopy(array, array_count, speed, speed2, msg); EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(n1Mem)); EXPECT_SUCCESS(hsaKmtFreeMemory(n1Mem, alloc_size)); for (i = 0; i < n; i++) { EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(n2Mem[i])); EXPECT_SUCCESS(hsaKmtFreeMemory(n2Mem[i], alloc_size)); } } TEST_F(KFDPerformanceTest, P2PBandWidthTest) { TEST_START(TESTPROFILE_RUNALL); if (!is_dgpu()) { LOG() << "Skipping test: Can't have 2 APUs on the same system." << std::endl; return; } const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); std::vector nodes; const bool isSpecified = g_TestDstNodeId != -1 && g_TestNodeId != -1; int numPeers = 0; if (isSpecified) { if (g_TestNodeId != g_TestDstNodeId) { nodes.push_back(g_TestNodeId); nodes.push_back(g_TestDstNodeId); if ((m_NodeInfo.IsPeerAccessibleByNode(g_TestNodeId, g_TestDstNodeId) && m_NodeInfo.IsPeerAccessibleByNode(g_TestDstNodeId, g_TestNodeId))) numPeers = 2; } } else { nodes = m_NodeInfo.GetNodesWithGPU(); numPeers = nodes.size(); } if (numPeers < 2) { LOG() << "Skipping test: Need at least two large bar GPU or XGMI connected." << std::endl; return; } g_TestTimeOut *= numPeers; std::vector sysNodes(nodes); // include sysMem node 0... sysNodes.insert(sysNodes.begin(),0); const int total_tests = 7; const char *test_suits_string[total_tests] = { "Copy from node to node by [push, NONE]", "Copy from node to node by [pull, NONE]", "Full duplex copy from node to node by [push|pull, NONE]", "Full duplex copy from node to node by [push, push]", "Full duplex copy from node to node by [pull, pull]", "Copy from node to multiple nodes by [push, NONE]", "Copy from multiple nodes to node by [push, NONE]", }; const P2PDirection test_suits[total_tests][2] = { /* One node used.*/ {OUT, NONE}, {IN, NONE}, {IN_OUT,NONE}, /* two nodes used.*/ {OUT, OUT}, {IN, IN}, /* Multi nodes used*/ {OUT, NONE}, {NONE, OUT}, }; const int twoNodesIdx = 3; const int multiNodesIdx = 5; const HSAuint32 size = 32ULL << 20; int s = 0; //test index; std::stringstream msg; char str[64]; if (isSpecified) { HSAuint32 n1 = g_TestNodeId; HSAuint32 n2 = g_TestDstNodeId; HSAuint64 speed, speed2; LOG() << "Copy from node to node by [push, pull]" << std::endl; snprintf(str, sizeof(str), "[%d -> %d] ", n1, n2); testNodeToNodes(n1, &n2, 1, OUT, IN, size, &speed, &speed2, &msg); LOG() << std::dec << str << (float)speed / 1024 << " - " << (float)speed2 / 1024 << " GB/s" << std::endl; goto exit; } for (; s < twoNodesIdx; s++) { LOG() << test_suits_string[s] << std::endl; msg << test_suits_string[s] << std::endl; for (unsigned i = 0; i < nodes.size(); i++) { /* Src node is a GPU.*/ HSAuint32 n1 = nodes[i]; HSAuint64 speed, speed2; /* Pick up dst node which can be sysMem.*/ for (unsigned j = 0; j < sysNodes.size(); j++) { HSAuint32 n2 = sysNodes[j]; if (n1 == n2) continue; if (!m_NodeInfo.IsPeerAccessibleByNode(n2, n1)) continue; snprintf(str, sizeof(str), "[%d -> %d] ", n1, n2); msg << str << std::endl; testNodeToNodes(n1, &n2, 1, test_suits[s][0], test_suits[s][1], size, &speed, &speed2, &msg); LOG() << std::dec << str << (float)speed / 1024 << " - " << (float)speed2 / 1024 << " GB/s" << std::endl; } } } for (; s < multiNodesIdx; s++) { LOG() << test_suits_string[s] << std::endl; msg << test_suits_string[s] << std::endl; for (unsigned i = 0; i < nodes.size(); i++) { HSAuint32 n1 = nodes[i]; HSAuint64 speed, speed2; for (unsigned j = i + 1; j < nodes.size(); j++) { HSAuint32 n2 = nodes[j]; if (!m_NodeInfo.IsPeerAccessibleByNode(n2, n1) || !m_NodeInfo.IsPeerAccessibleByNode(n1, n2)) continue; snprintf(str, sizeof(str), "[%d <-> %d] ", n1, n2); msg << str << std::endl; testNodeToNodes(n1, &n2, 1, test_suits[s][0], test_suits[s][1], size, &speed, &speed2, &msg); LOG() << std::dec << str << (float)speed / 1024 << " - " << (float)speed2 / 1024 << " GB/s" << std::endl; } } } for (; s < total_tests && !isSpecified; s++) { LOG() << test_suits_string[s] << std::endl; msg << test_suits_string[s] << std::endl; /* Just use GPU nodes to do copy.*/ std::vector &src = test_suits[s][0] != NONE ? nodes : sysNodes; std::vector &dst = test_suits[s][1] != NONE ? nodes : sysNodes; for (unsigned i = 0; i < src.size(); i++) { HSAuint32 n1 = src[i]; HSAuint64 speed, speed2; HSAuint32 n2[dst.size()]; int n = 0; char str[64]; for (unsigned j = 0; j < dst.size(); j++) { if (dst[j] != n1) { if (test_suits[s][0] != NONE && !m_NodeInfo.IsPeerAccessibleByNode(dst[j], n1)) continue; if (test_suits[s][1] != NONE && !m_NodeInfo.IsPeerAccessibleByNode(n1, dst[j])) continue; n2[n++] = dst[j]; } } /* At least 2 dst GPUs.*/ if (n < 2) continue; if (test_suits[s][1] == OUT) snprintf(str, sizeof(str), "[[%d...%d] -> %d] ", dst.front(), dst.back(), n1); else snprintf(str, sizeof(str), "[%d -> [%d...%d]] ", n1, dst.front(), dst.back()); msg << str << std::endl; testNodeToNodes(n1, n2, n, test_suits[s][0], test_suits[s][1], size, &speed, &speed2, &msg); LOG() << std::dec << str << (float)speed / 1024 << " - " << (float)speed2 / 1024 << " GB/s" << std::endl; } } g_TestTimeOut /= numPeers; exit: /* New line.*/ LOG() << std::endl << msg.str() << std::endl; TEST_END } TEST_F(KFDPerformanceTest, P2POverheadTest) { TEST_START(TESTPROFILE_RUNALL); if (!is_dgpu()) { LOG() << "Skipping test: Can't have 2 APUs on the same system." << std::endl; return; } const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); std::vector nodes; nodes = m_NodeInfo.GetNodesWithGPU(); int numPeers = nodes.size(); if (numPeers < 2) { LOG() << "Skipping test: Need at least two large bar GPU or XGMI connected." << std::endl; return; } std::vector sysNodes(nodes); // include sysMem node 0... sysNodes.insert(sysNodes.begin(),0); /* size should be small.*/ const HSAuint32 sizeArray[] = {4, 8, 16, 64, 256, 1024}; const int total_tests = 3; const char *test_suits_string[total_tests] = { "[push] ", "[pull] ", "[push|pull]", }; const P2PDirection test_suits[total_tests] = {OUT, IN, IN_OUT}; std::stringstream msg; int s; //test index; msg << "Test (avg. ns) | Size"; for (auto &size : sizeArray) msg << "\t" << size; LOG() << msg.str() << std::endl; LOG() << "-----------------------------------------------------------------------" << std::endl; for (s = 0; s < total_tests; s++) { for (unsigned i = 0; i < nodes.size(); i++) { /* Src node is a GPU.*/ HSAuint32 n1 = nodes[i]; HSAuint64 time; /* Pick up dst node which can be sysMem.*/ for (unsigned j = 0; j < sysNodes.size(); j++) { HSAuint32 n2 = sysNodes[j]; std::stringstream msg; if (n1 != n2 && !m_NodeInfo.IsPeerAccessibleByNode(n2, n1)) continue; msg << test_suits_string[s] << "[" << n1 << " -> " << n2 << "]"; for (auto &size : sizeArray) { testNodeToNodes(n1, &n2, 1, test_suits[s], NONE, size, 0, 0, 0, 1, &time); msg << "\t" << time; } LOG() << msg.str() << std::endl; } } } TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDQMTest.cpp000066400000000000000000002041721446477712600240500ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include "KFDQMTest.hpp" #include "PM4Queue.hpp" #include "PM4Packet.hpp" #include "SDMAPacket.hpp" #include "XgmiOptimizedSDMAQueue.hpp" #include "AqlQueue.hpp" #include #include "Dispatch.hpp" void KFDQMTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); ROUTINE_END } void KFDQMTest::TearDown() { ROUTINE_START KFDBaseComponentTest::TearDown(); ROUTINE_END } TEST_F(KFDQMTest, CreateDestroyCpQueue) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDQMTest, SubmitNopCpQueue) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; PM4Queue queue; HsaEvent *event; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &event)); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); queue.PlaceAndSubmitPacket(PM4NopPacket()); queue.Wait4PacketConsumption(event); hsaKmtDestroyEvent(event); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDQMTest, SubmitPacketCpQueue) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer destBuf(PAGE_SIZE, defaultGPUNode, false); destBuf.Fill(0xFF); HsaEvent *event; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &event)); PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); queue.PlaceAndSubmitPacket(PM4WriteDataPacket(destBuf.As(), 0, 0)); queue.Wait4PacketConsumption(event); EXPECT_TRUE(WaitOnValue(destBuf.As(), 0)); hsaKmtDestroyEvent(event); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDQMTest, AllCpQueues) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer destBuf(PAGE_SIZE, defaultGPUNode, false); destBuf.Fill(0xFF); std::vector queues(m_numCpQueues); for (unsigned int qidx = 0; qidx < m_numCpQueues; ++qidx) ASSERT_SUCCESS(queues[qidx].Create(defaultGPUNode)) << " QueueId=" << qidx; for (unsigned int qidx = 0; qidx < m_numCpQueues; ++qidx) { queues[qidx].PlaceAndSubmitPacket(PM4WriteDataPacket(destBuf.As()+qidx*2, qidx, qidx)); queues[qidx].PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, true, 0, 0)); queues[qidx].Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(destBuf.As()+qidx*2, qidx)); } for (unsigned int qidx = 0; qidx < m_numCpQueues; ++qidx) EXPECT_SUCCESS(queues[qidx].Destroy()); TEST_END } TEST_F(KFDQMTest, CreateDestroySdmaQueue) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; SDMAQueue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDQMTest, SubmitNopSdmaQueue) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; SDMAQueue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); queue.PlaceAndSubmitPacket(SDMANopPacket()); queue.Wait4PacketConsumption(); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDQMTest, SubmitPacketSdmaQueue) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer destBuf(PAGE_SIZE, defaultGPUNode, false); destBuf.Fill(0xFF); SDMAQueue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); queue.PlaceAndSubmitPacket(SDMAWriteDataPacket(queue.GetFamilyId(), destBuf.As(), 0x02020202)); queue.Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(destBuf.As(), 0x02020202)); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDQMTest, AllSdmaQueues) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); int bufSize = PAGE_SIZE; ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; const unsigned int numSdmaQueues = m_numSdmaEngines * m_numSdmaQueuesPerEngine; LOG() << "Regular SDMA engines number: " << m_numSdmaEngines << " SDMA queues per engine: " << m_numSdmaQueuesPerEngine << std::endl; HsaMemoryBuffer destBuf(bufSize << 1 , defaultGPUNode, false); HsaMemoryBuffer srcBuf(bufSize, defaultGPUNode, false); destBuf.Fill(0xFF); std::vector queues(numSdmaQueues); for (unsigned int qidx = 0; qidx < numSdmaQueues; ++qidx) ASSERT_SUCCESS(queues[qidx].Create(defaultGPUNode)); for (unsigned int qidx = 0; qidx < numSdmaQueues; ++qidx) { destBuf.Fill(0x0); srcBuf.Fill(qidx + 0xa0); queues[qidx].PlaceAndSubmitPacket( SDMACopyDataPacket(queues[qidx].GetFamilyId(), destBuf.As(), srcBuf.As(), bufSize)); queues[qidx].PlaceAndSubmitPacket( SDMAWriteDataPacket(queues[qidx].GetFamilyId(), destBuf.As() + bufSize/4, 0x02020202)); queues[qidx].Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(destBuf.As() + bufSize/4, 0x02020202)); EXPECT_SUCCESS(memcmp( destBuf.As(), srcBuf.As(), bufSize)); } for (unsigned int qidx = 0; qidx < numSdmaQueues; ++qidx) EXPECT_SUCCESS(queues[qidx].Destroy()); TEST_END } TEST_F(KFDQMTest, AllXgmiSdmaQueues) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); int bufSize = PAGE_SIZE; int j; ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; const unsigned int numXgmiSdmaQueues = m_numSdmaXgmiEngines * m_numSdmaQueuesPerEngine; LOG() << "XGMI SDMA engines number: " << m_numSdmaXgmiEngines << " SDMA queues per engine: " << m_numSdmaQueuesPerEngine << std::endl; HsaMemoryBuffer destBuf(bufSize << 1 , defaultGPUNode, false); HsaMemoryBuffer srcBuf(bufSize, defaultGPUNode, false); destBuf.Fill(0xFF); std::vector xgmiSdmaQueues(numXgmiSdmaQueues); for (j = 0; j < numXgmiSdmaQueues; ++j) ASSERT_SUCCESS(xgmiSdmaQueues[j].Create(defaultGPUNode)); for (j = 0; j < numXgmiSdmaQueues; ++j) { destBuf.Fill(0x0); srcBuf.Fill(j + 0xa0); xgmiSdmaQueues[j].PlaceAndSubmitPacket( SDMACopyDataPacket(xgmiSdmaQueues[j].GetFamilyId(), destBuf.As(), srcBuf.As(), bufSize)); xgmiSdmaQueues[j].PlaceAndSubmitPacket( SDMAWriteDataPacket(xgmiSdmaQueues[j].GetFamilyId(), destBuf.As() + bufSize/4, 0x02020202)); xgmiSdmaQueues[j].Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(destBuf.As() + bufSize/4, 0x02020202)); EXPECT_SUCCESS(memcmp( destBuf.As(), srcBuf.As(), bufSize)); } for (j = 0; j < numXgmiSdmaQueues; ++j) EXPECT_SUCCESS(xgmiSdmaQueues[j].Destroy()); TEST_END } TEST_F(KFDQMTest, AllQueues) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); int bufSize = PAGE_SIZE; ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; unsigned int i, j; const unsigned int numCpQueues = m_numCpQueues; const unsigned int numSdmaQueues = m_numSdmaEngines * m_numSdmaQueuesPerEngine; const unsigned int numXgmiSdmaQueues = m_numSdmaXgmiEngines * m_numSdmaQueuesPerEngine; HsaMemoryBuffer destBufCp(PAGE_SIZE, defaultGPUNode, false); destBufCp.Fill(0xFF); HsaMemoryBuffer destBuf(bufSize << 1 , defaultGPUNode, false); HsaMemoryBuffer srcBuf(bufSize, defaultGPUNode, false); destBuf.Fill(0xFF); std::vector cpQueues(numCpQueues); std::vector sdmaQueues(numSdmaQueues); std::vector xgmiSdmaQueues(numXgmiSdmaQueues); for (i = 0; i < numCpQueues; ++i) ASSERT_SUCCESS(cpQueues[i].Create(defaultGPUNode)) << " QueueId=" << i; for (j = 0; j < numSdmaQueues; ++j) ASSERT_SUCCESS(sdmaQueues[j].Create(defaultGPUNode)); for (j = 0; j < numXgmiSdmaQueues; ++j) ASSERT_SUCCESS(xgmiSdmaQueues[j].Create(defaultGPUNode)); for (i = 0; i < numCpQueues; ++i) { cpQueues[i].PlaceAndSubmitPacket(PM4WriteDataPacket(destBufCp.As()+i*2, i, i)); cpQueues[i].PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, true, 0, 0)); cpQueues[i].Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(destBufCp.As()+i*2, i)); } for (j = 0; j < numSdmaQueues; ++j) { destBuf.Fill(0x0); srcBuf.Fill(j + 0xa0); sdmaQueues[j].PlaceAndSubmitPacket( SDMACopyDataPacket(sdmaQueues[j].GetFamilyId(), destBuf.As(), srcBuf.As(), bufSize)); sdmaQueues[j].PlaceAndSubmitPacket( SDMAWriteDataPacket(sdmaQueues[j].GetFamilyId(), destBuf.As() + bufSize/4, 0x02020202)); sdmaQueues[j].Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(destBuf.As() + bufSize/4, 0x02020202)); EXPECT_SUCCESS(memcmp( destBuf.As(), srcBuf.As(), bufSize)); } for (j = 0; j < numXgmiSdmaQueues; ++j) { destBuf.Fill(0x0); srcBuf.Fill(j + 0xa0); xgmiSdmaQueues[j].PlaceAndSubmitPacket( SDMACopyDataPacket(xgmiSdmaQueues[j].GetFamilyId(), destBuf.As(), srcBuf.As(), bufSize)); xgmiSdmaQueues[j].PlaceAndSubmitPacket( SDMAWriteDataPacket(xgmiSdmaQueues[j].GetFamilyId(), destBuf.As() + bufSize/4, 0x02020202)); xgmiSdmaQueues[j].Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(destBuf.As() + bufSize/4, 0x02020202)); EXPECT_SUCCESS(memcmp( destBuf.As(), srcBuf.As(), bufSize)); } for (i = 0; i < numCpQueues; ++i) EXPECT_SUCCESS(cpQueues[i].Destroy()); for (j = 0; j < numSdmaQueues; ++j) EXPECT_SUCCESS(sdmaQueues[j].Destroy()); for (j = 0; j < numXgmiSdmaQueues; ++j) EXPECT_SUCCESS(xgmiSdmaQueues[j].Destroy()); TEST_END } /* The following test is designed to reproduce an intermittent hang on * Fiji and other VI/Polaris GPUs. This test typically hangs in a few * seconds. According to analysis done by HW engineers, the culprit * seems to be PCIe speed switching. The problem can be worked around * by disabling the lowest DPM level on Fiji. */ TEST_F(KFDQMTest, SdmaConcurrentCopies) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; #define BUFFER_SIZE (64*1024) #define NPACKETS 1 #define COPY_SIZE (BUFFER_SIZE / NPACKETS) HsaMemoryBuffer srcBuf(BUFFER_SIZE, 0, true); HsaMemoryBuffer dstBuf(BUFFER_SIZE, defaultGPUNode, false, is_dgpu() ? true : false); SDMAQueue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); std::ostream &log = LOG(); char progress[] = "-\b"; log << "Running ... "; for (unsigned i = 0; i < 100000; i++) { if (i % 1000 == 0) { const char progressSteps[4] = {'-', '\\', '|', '/'}; progress[0] = progressSteps[(i/1000) % 4]; log << progress; } for (unsigned j = 0; j < NPACKETS; j++) queue.PlacePacket( SDMACopyDataPacket(queue.GetFamilyId(), dstBuf.As()+COPY_SIZE*j, srcBuf.As()+COPY_SIZE*j, COPY_SIZE)); queue.SubmitPacket(); /* Waste a variable amount of time. Submission timing * while SDMA runs concurrently seems to be critical for * reproducing the hang */ for (int k = 0; k < (i & 0xfff); k++) memcpy(srcBuf.As()+PAGE_SIZE, srcBuf.As(), 1024); /* Wait for idle every 8 packets to allow the SDMA engine to * run concurrently for a bit without getting too far ahead */ if ((i & 0x7) == 0) queue.Wait4PacketConsumption(); } log << "Done." << std::endl; queue.PlaceAndSubmitPacket(SDMAWriteDataPacket(queue.GetFamilyId(), srcBuf.As(), 0x02020202)); queue.Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(srcBuf.As(), 0x02020202)); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDQMTest, DisableCpQueueByUpdateWithNullAddress) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer destBuf(PAGE_SIZE, defaultGPUNode, false); destBuf.Fill(0xFFFFFFFF); PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaEvent *event; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &event)); queue.PlaceAndSubmitPacket(PM4WriteDataPacket(destBuf.As(), 0, 0)); queue.Wait4PacketConsumption(event); WaitOnValue(destBuf.As(), 0); destBuf.Fill(0xFFFFFFFF); EXPECT_SUCCESS(queue.Update(BaseQueue::DEFAULT_QUEUE_PERCENTAGE, BaseQueue::DEFAULT_PRIORITY, true)); queue.PlaceAndSubmitPacket(PM4WriteDataPacket(destBuf.As(), 1, 1)); // Don't sync since we don't expect rptr to change when the queue is disabled. Delay(2000); EXPECT_EQ(destBuf.As()[0], 0xFFFFFFFF) << "Packet executed even though the queue is supposed to be disabled!"; EXPECT_SUCCESS(queue.Update(BaseQueue::DEFAULT_QUEUE_PERCENTAGE, BaseQueue::DEFAULT_PRIORITY, false)); queue.Wait4PacketConsumption(event); WaitOnValue(destBuf.As(), 1); hsaKmtDestroyEvent(event); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDQMTest, DisableSdmaQueueByUpdateWithNullAddress) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer destBuf(PAGE_SIZE, defaultGPUNode, false); destBuf.Fill(0xFFFFFFFF); SDMAQueue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); queue.PlaceAndSubmitPacket(SDMAWriteDataPacket(queue.GetFamilyId(), destBuf.As(), 0)); WaitOnValue(destBuf.As(), 0); destBuf.Fill(0xFFFFFFFF); EXPECT_SUCCESS(queue.Update(BaseQueue::DEFAULT_QUEUE_PERCENTAGE, BaseQueue::DEFAULT_PRIORITY, true)); queue.PlaceAndSubmitPacket(SDMAWriteDataPacket(queue.GetFamilyId(), destBuf.As(), 0)); // Don't sync since we don't expect rptr to change when the queue is disabled. Delay(2000); EXPECT_EQ(destBuf.As()[0], 0xFFFFFFFF) << "Packet executed even though the queue is supposed to be disabled!"; EXPECT_SUCCESS(queue.Update(BaseQueue::DEFAULT_QUEUE_PERCENTAGE, BaseQueue::DEFAULT_PRIORITY, false)); queue.Wait4PacketConsumption(); WaitOnValue(destBuf.As(), 0); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDQMTest, DisableCpQueueByUpdateWithZeroPercentage) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer destBuf(PAGE_SIZE, defaultGPUNode, false); destBuf.Fill(0xFFFFFFFF); PM4Queue queue; ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaEvent *event; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &event)); PM4WriteDataPacket packet1, packet2; packet1.InitPacket(destBuf.As(), 0, 0); packet2.InitPacket(destBuf.As(), 1, 1); queue.PlaceAndSubmitPacket(packet1); queue.Wait4PacketConsumption(event); WaitOnValue(destBuf.As(), 0); destBuf.Fill(0xFFFFFFFF); EXPECT_SUCCESS(queue.Update(0/*percentage*/, BaseQueue::DEFAULT_PRIORITY, false)); queue.PlaceAndSubmitPacket(packet2); // Don't sync since we don't expect rptr to change when the queue is disabled. Delay(2000); EXPECT_EQ(destBuf.As()[0], 0xFFFFFFFF) << "Packet executed even though the queue is supposed to be disabled!"; EXPECT_SUCCESS(queue.Update(BaseQueue::DEFAULT_QUEUE_PERCENTAGE, BaseQueue::DEFAULT_PRIORITY, false)); queue.Wait4PacketConsumption(event); WaitOnValue(destBuf.As(), 1); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDQMTest, CreateQueueStressSingleThreaded) { TEST_START(TESTPROFILE_RUNALL) static const HSAuint64 TEST_TIME_SEC = 15; HSAuint64 initialTime = GetSystemTickCountInMicroSec(); unsigned int numIter = 0; HSAuint64 timePassed = 0; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; do { // The following means we'll get the order 0,0 => 0,1 => 1,0 => 1,1 so we cover all options. unsigned int firstToCreate = (numIter % 2 != 0) ? 1 : 0; unsigned int firstToDestroy = (numIter % 4 > 1) ? 1 : 0; unsigned int secondToCreate = (firstToCreate + 1)%2; unsigned int secondToDestroy = (firstToDestroy + 1)%2; BaseQueue *queues[2] = {new PM4Queue(), new SDMAQueue()}; ASSERT_SUCCESS(queues[firstToCreate]->Create(defaultGPUNode)); ASSERT_SUCCESS(queues[secondToCreate]->Create(defaultGPUNode)); EXPECT_SUCCESS(queues[firstToDestroy]->Destroy()); EXPECT_SUCCESS(queues[secondToDestroy]->Destroy()); delete queues[0]; delete queues[1]; ++numIter; HSAuint64 curTime = GetSystemTickCountInMicroSec(); timePassed = (curTime - initialTime) / 1000000; } while (timePassed < TEST_TIME_SEC); TEST_END } TEST_F(KFDQMTest, OverSubscribeCpQueues) { TEST_START(TESTPROFILE_RUNALL) if (m_FamilyId == FAMILY_CI || m_FamilyId == FAMILY_KV) { LOG() << "Skipping test: CI doesn't have HW scheduling." << std::endl; return; } static const unsigned int MAX_CP_QUEUES = 65; static const unsigned int MAX_PACKETS = 100; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer destBuf(PAGE_SIZE, defaultGPUNode, false); destBuf.Fill(0xFF); PM4Queue queues[MAX_CP_QUEUES]; for (unsigned int qidx = 0; qidx < MAX_CP_QUEUES; ++qidx) ASSERT_SUCCESS(queues[qidx].Create(defaultGPUNode)) << " QueueId=" << qidx; for (unsigned int qidx = 0; qidx < MAX_CP_QUEUES; ++qidx) { unsigned int pktSizeDw = 0; for (unsigned int i = 0; i < MAX_PACKETS; i++) { PM4WriteDataPacket packet; packet.InitPacket(destBuf.As()+qidx*2, qidx+i, qidx+i); // two dwords per packet queues[qidx].PlacePacket(packet); } } for (unsigned int qidx = 0; qidx < MAX_CP_QUEUES; ++qidx) queues[qidx].SubmitPacket(); // Delaying for 5 seconds in order to get all the results Delay(5000); for (unsigned int qidx = 0; qidx < MAX_CP_QUEUES; ++qidx) EXPECT_TRUE(queues[qidx].AllPacketsSubmitted())<< "QueueId=" << qidx;; for (unsigned int qidx = 0; qidx < MAX_CP_QUEUES; ++qidx) EXPECT_SUCCESS(queues[qidx].Destroy()); TEST_END } HSAint64 KFDQMTest::TimeConsumedwithCUMask(int node, uint32_t* mask, uint32_t mask_count) { HsaMemoryBuffer isaBuffer(PAGE_SIZE, node, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer dstBuffer(PAGE_SIZE, node, true, false, false); HsaMemoryBuffer ctlBuffer(PAGE_SIZE, node, true, false, false); EXPECT_SUCCESS(m_pAsm->RunAssembleBuf(LoopIsa, isaBuffer.As())); Dispatch dispatch(isaBuffer); dispatch.SetDim(1024, 16, 16); PM4Queue queue; EXPECT_SUCCESS(queue.Create(node)); EXPECT_SUCCESS(queue.SetCUMask(mask, mask_count)); queue.SetSkipWaitConsump(true); HSAuint64 startTime = GetSystemTickCountInMicroSec(); dispatch.Submit(queue); dispatch.Sync(); HSAuint64 endTime = GetSystemTickCountInMicroSec(); EXPECT_SUCCESS(queue.Destroy()); return endTime - startTime; } /* To cover for outliers, allow us to get the Average time based on a specified number of iterations */ HSAint64 KFDQMTest::GetAverageTimeConsumedwithCUMask(int node, uint32_t* mask, uint32_t mask_count, int iterations) { HSAint64 timeArray[iterations]; HSAint64 timeTotal = 0; if (iterations < 1) { LOG() << "ERROR: At least 1 iteration must be performed" << std::endl; return 0; } for (int x = 0; x < iterations; x++) { timeArray[x] = TimeConsumedwithCUMask(node, mask, mask_count); timeTotal += timeArray[x]; } if (timeTotal == 0) { LOG() << "ERROR: Total time reported as 0. Exiting" << std::endl; return 0; } for (int x = 0; x < iterations; x++) { HSAint64 variance = timeArray[x] / (timeTotal / iterations); if (variance < CuNegVariance || variance > CuPosVariance) LOG() << "WARNING: Measurement #" << x << "/" << iterations << " (" << timeArray[x] << ") is at least " << CuVariance*100 << "% away from the mean (" << timeTotal/iterations << ")" << std::endl; } return timeTotal / iterations; } /* * Apply CU masking in a linear fashion, adding 1 CU per iteration * until all Shader Engines are full */ TEST_F(KFDQMTest, BasicCuMaskingLinear) { TEST_START(TESTPROFILE_RUNALL); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId >= FAMILY_VI) { const HsaNodeProperties *pNodeProperties = m_NodeInfo.GetNodeProperties(defaultGPUNode); uint32_t ActiveCU = (pNodeProperties->NumFComputeCores / pNodeProperties->NumSIMDPerCU); uint32_t numSEs = pNodeProperties->NumShaderBanks; LOG() << std::dec << "# Compute cores: " << pNodeProperties->NumFComputeCores << std::endl; LOG() << std::dec << "# SIMDs per CU: " << pNodeProperties->NumSIMDPerCU << std::endl; LOG() << std::dec << "# Shader engines: " << numSEs << std::endl; LOG() << std::dec << "# Active CUs: " << ActiveCU << std::endl; HSAint64 TimewithCU1, TimewithCU; uint32_t maskNumDwords = (ActiveCU + 31) / 32; /* Round up to the nearest multiple of 32 */ uint32_t maskNumBits = maskNumDwords * 32; uint32_t mask[maskNumDwords]; double ratio; mask[0] = 0x1; for (int i = 1; i < maskNumDwords; i++) mask[i] = 0x0; /* Execute once to get any HW optimizations out of the way */ TimeConsumedwithCUMask(defaultGPUNode, mask, maskNumBits); LOG() << "Getting baseline performance numbers (CU Mask: 0x1)" << std::endl; TimewithCU1 = GetAverageTimeConsumedwithCUMask(defaultGPUNode, mask, maskNumBits, 3); for (int nCUs = 2; nCUs <= ActiveCU; nCUs++) { int maskIndex = (nCUs - 1) / 32; mask[maskIndex] |= 1 << ((nCUs - 1) % 32); TimewithCU = TimeConsumedwithCUMask(defaultGPUNode, mask, maskNumBits); ratio = (double)(TimewithCU1) / ((double)(TimewithCU) * nCUs); LOG() << "Expected performance of " << nCUs << " CUs vs 1 CU:" << std::endl; LOG() << std::setprecision(2) << CuNegVariance << " <= " << std::fixed << std::setprecision(8) << ratio << " <= " << std::setprecision(2) << CuPosVariance << std::endl; EXPECT_TRUE((ratio >= CuNegVariance) && (ratio <= CuPosVariance)); RECORD(ratio) << "Ratio-" << nCUs << "-CUs"; } } else { LOG() << "Skipping test: Test not supported for family ID 0x" << m_FamilyId << "." << std::endl; } TEST_END } /** * Apply CU masking where the number of CUs is equal across all Shader Engines * This will work due to the HW splitting the workload unevenly across the Shader * Engines when ((#ofCUs)/(#ofShaderEngines)) is not a whole number. The tests above * will not yield viable results when an uneven distribution of CUs is used over multiple * shader engines (e.g. 0x1000100030003), until the HW changes how it schedules work. */ TEST_F(KFDQMTest, BasicCuMaskingEven) { TEST_START(TESTPROFILE_RUNALL); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId >= FAMILY_VI) { const HsaNodeProperties *pNodeProperties = m_NodeInfo.GetNodeProperties(defaultGPUNode); uint32_t ActiveCU = (pNodeProperties->NumFComputeCores / pNodeProperties->NumSIMDPerCU); uint32_t numShaderEngines = pNodeProperties->NumShaderBanks; if (numShaderEngines == 1) { LOG() << "Skipping test: Only 1 Shader Engine present." << std::endl; return; } LOG() << std::dec << "# Compute cores: " << pNodeProperties->NumFComputeCores << std::endl; LOG() << std::dec << "# SIMDs per CU: " << pNodeProperties->NumSIMDPerCU << std::endl; LOG() << std::dec << "# Shader engines: " << numShaderEngines << std::endl; LOG() << std::dec << "# Active CUs: " << ActiveCU << std::endl; HSAint64 TimewithCU1, TimewithCU; uint32_t maskNumDwords = (ActiveCU + 31) / 32; /* Round up to the nearest multiple of 32 */ uint32_t maskNumBits = maskNumDwords * 32; uint32_t mask[maskNumDwords]; int numCuPerShader = ActiveCU / numShaderEngines; double ratio; /* In KFD we symmetrically map mask to all SEs: * mask[0] bit0 -> se0 cu0; * mask[0] bit1 -> se1 cu0; * ... (if # SE is 4) * mask[0] bit4 -> se0 cu1; * ... */ /* Set Mask to 1 CU per SE */ memset(mask, 0, maskNumDwords * sizeof(uint32_t)); for (int i = 0; i < numShaderEngines; i++) { int maskIndex = (i / 32) % maskNumDwords; mask[maskIndex] |= 1 << (i % 32); } /* Execute once to get any HW optimizations out of the way */ TimeConsumedwithCUMask(defaultGPUNode, mask, maskNumBits); LOG() << "Getting baseline performance numbers (1 CU per SE)" << std::endl; TimewithCU1 = GetAverageTimeConsumedwithCUMask(defaultGPUNode, mask, maskNumBits, 3); /* Each loop will add 1 more CU per SE. We use the mod and divide to handle * when SEs aren't distributed in multiples of 32 (e.g. Tonga) * OR the new bit in for simplicity instead of re-creating the mask each iteration */ for (int x = 0; x < numCuPerShader; x++) { for (int se = 0; se < numShaderEngines; se++) { int offset = x * numShaderEngines + se; int maskIndex = (offset / 32) % maskNumDwords; mask[maskIndex] |= 1 << (offset % 32); } int nCUs = x + 1; TimewithCU = TimeConsumedwithCUMask(defaultGPUNode, mask, maskNumBits); ratio = (double)(TimewithCU1) / ((double)(TimewithCU) * nCUs); LOG() << "Expected performance of " << nCUs << " CU(s)/SE vs 1 CU/SE:" << std::endl; LOG() << std::setprecision(2) << CuNegVariance << " <= " << std::fixed << std::setprecision(8) << ratio << " <= " << std::setprecision(2) << CuPosVariance << std::endl; EXPECT_TRUE((ratio >= CuNegVariance) && (ratio <= CuPosVariance)); RECORD(ratio) << "Ratio-" << nCUs << "-CUs"; } } else { LOG() << "Skipping test: Test not supported for family ID 0x" << m_FamilyId << "." << std::endl; } TEST_END } TEST_F(KFDQMTest, QueuePriorityOnDifferentPipe) { TEST_START(TESTPROFILE_RUNALL); if (m_FamilyId < FAMILY_VI) { LOG() << "Skipping test: Shader won't run on CI." << std::endl; return; } int node = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(node, 0) << "failed to get default GPU Node"; HsaMemoryBuffer syncBuf(PAGE_SIZE, node, true/*zero*/, false/*local*/, true/*exec*/); HSAint32 *syncBuffer = syncBuf.As(); HsaMemoryBuffer isaBuffer(PAGE_SIZE, node, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(LoopIsa, isaBuffer.As())); Dispatch dispatch[2] = { Dispatch(isaBuffer, true), Dispatch(isaBuffer, true) }; int activeTaskBitmap = 0x3; HSAuint64 startTime, endTime[2]; HsaEvent *pHsaEvent[2]; int numEvent = 2; PM4Queue queue[2]; HSA_QUEUE_PRIORITY priority[2] = { HSA_QUEUE_PRIORITY_LOW, HSA_QUEUE_PRIORITY_HIGH }; int i; for (i = 0; i < 2; i++) { syncBuffer[i] = -1; ASSERT_SUCCESS(queue[i].Create(node)); queue[i].Update(BaseQueue::DEFAULT_QUEUE_PERCENTAGE, priority[i], false); pHsaEvent[i] = dispatch[i].GetHsaEvent(); pHsaEvent[i]->EventData.EventData.SyncVar.SyncVar.UserData = &syncBuffer[i]; dispatch[i].SetDim(1024, 16, 16); } startTime = GetSystemTickCountInMicroSec(); for (i = 0; i < 2; i++) dispatch[i].Submit(queue[i]); while (activeTaskBitmap > 0) { hsaKmtWaitOnMultipleEvents(pHsaEvent, numEvent, false, g_TestTimeOut); for (i = 0; i < 2; i++) { if ((activeTaskBitmap & (1 << i)) && (syncBuffer[i] == pHsaEvent[i]->EventId)) { endTime[i] = GetSystemTickCountInMicroSec(); activeTaskBitmap &= ~(1 << i); } } } for (i = 0; i < 2; i++) { EXPECT_SUCCESS(queue[i].Destroy()); int usecs = endTime[i] - startTime; LOG() << "Task priority: " << std::dec << priority[i] << "\t"; LOG() << "Task duration: " << std::dec << usecs << "usecs" << std::endl; } TEST_END } TEST_F(KFDQMTest, QueuePriorityOnSamePipe) { TEST_START(TESTPROFILE_RUNALL); if (m_FamilyId < FAMILY_VI) { LOG() << "Skipping test: Shader won't run on CI." << std::endl; return; } int node = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(node, 0) << "failed to get default GPU Node"; HsaMemoryBuffer syncBuf(PAGE_SIZE, node, true/*zero*/, false/*local*/, true/*exec*/); HSAint32 *syncBuffer = syncBuf.As(); HsaMemoryBuffer isaBuffer(PAGE_SIZE, node, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(LoopIsa, isaBuffer.As())); Dispatch dispatch[2] = { Dispatch(isaBuffer, true), Dispatch(isaBuffer, true) }; int activeTaskBitmap = 0x3; HSAuint64 startTime, endTime[2]; HsaEvent *pHsaEvent[2]; int numEvent = 2; PM4Queue queue[13]; HSA_QUEUE_PRIORITY priority[2] = { HSA_QUEUE_PRIORITY_LOW, HSA_QUEUE_PRIORITY_HIGH }; int i; /* queue[2..12] are dummy queues. Create queue in this sequence to * render queue[0] and queue[1] on same pipe with no assumptions * about the number of pipes used by KFD. Queue #12 is a multiple * of 1, 2, 3 and 4, so it falls on pipe 0 for any number of pipes */ EXPECT_SUCCESS(queue[0].Create(node)); // Queue 0 is on Pipe 0 for (i = 2; i <= 12; i++) EXPECT_SUCCESS(queue[i].Create(node)); EXPECT_SUCCESS(queue[1].Create(node)); // Queue 12 is on Pipe 0 for (i = 0; i < 2; i++) { syncBuffer[i] = -1; queue[i].Update(BaseQueue::DEFAULT_QUEUE_PERCENTAGE, priority[i], false); pHsaEvent[i] = dispatch[i].GetHsaEvent(); pHsaEvent[i]->EventData.EventData.SyncVar.SyncVar.UserData = &syncBuffer[i]; dispatch[i].SetDim(1024, 16, 16); } startTime = GetSystemTickCountInMicroSec(); for (i = 0; i < 2; i++) dispatch[i].Submit(queue[i]); while (activeTaskBitmap > 0) { hsaKmtWaitOnMultipleEvents(pHsaEvent, numEvent, false, g_TestTimeOut); for (i = 0; i < 2; i++) { if ((activeTaskBitmap & (1 << i)) && (syncBuffer[i] == pHsaEvent[i]->EventId)) { endTime[i] = GetSystemTickCountInMicroSec(); activeTaskBitmap &= ~(1 << i); } } } for (i = 0; i < 2; i++) { int usecs = endTime[i] - startTime; LOG() << "Task priority: " << std::dec << priority[i] << "\t"; LOG() << "Task duration: " << std::dec << usecs << "usecs" << std::endl; } for (i = 0; i <= 12; i++) { EXPECT_SUCCESS(queue[i].Destroy()); } TEST_END } void KFDQMTest::SyncDispatch(const HsaMemoryBuffer& isaBuffer, void* pSrcBuf, void* pDstBuf, int node) { PM4Queue queue; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); if (node != -1) defaultGPUNode = node; ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; Dispatch dispatch(isaBuffer); dispatch.SetArgs(pSrcBuf, pDstBuf); dispatch.SetDim(1, 1, 1); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); dispatch.Submit(queue); dispatch.Sync(); EXPECT_SUCCESS(queue.Destroy()); } TEST_F(KFDQMTest, EmptyDispatch) { TEST_START(TESTPROFILE_RUNALL); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(NoopIsa, isaBuffer.As())); SyncDispatch(isaBuffer, NULL, NULL); TEST_END } TEST_F(KFDQMTest, SimpleWriteDispatch) { TEST_START(TESTPROFILE_RUNALL); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer srcBuffer(PAGE_SIZE, defaultGPUNode, false); HsaMemoryBuffer destBuffer(PAGE_SIZE, defaultGPUNode); srcBuffer.Fill(0x01010101); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); SyncDispatch(isaBuffer, srcBuffer.As(), destBuffer.As()); EXPECT_EQ(destBuffer.As()[0], 0x01010101); TEST_END } TEST_F(KFDQMTest, MultipleCpQueuesStressDispatch) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; static const unsigned int MAX_CP_QUEUES = 16; HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer srcBuffer(PAGE_SIZE, defaultGPUNode, false); HsaMemoryBuffer destBuffer(PAGE_SIZE, defaultGPUNode); unsigned int* src = srcBuffer.As(); unsigned int* dst = destBuffer.As(); static const HSAuint64 TEST_TIME_SEC = 15; HSAuint64 initialTime, curTime; unsigned int numIter = 0; HSAuint64 timePassed = 0; unsigned int i; PM4Queue queues[MAX_CP_QUEUES]; Dispatch* dispatch[MAX_CP_QUEUES]; destBuffer.Fill(0xFF); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); for (i = 0; i < MAX_CP_QUEUES; ++i) ASSERT_SUCCESS(queues[i].Create(defaultGPUNode)) << " QueueId=" << i; initialTime = GetSystemTickCountInMicroSec(); do { for (i = 0; i < MAX_CP_QUEUES; ++i) { dispatch[i] = new Dispatch(isaBuffer); src[i] = numIter; dst[i] = 0xff; dispatch[i]->SetArgs(&src[i], &dst[i]); dispatch[i]->SetDim(1, 1, 1); dispatch[i]->Submit(queues[i]); } for (i = 0; i < MAX_CP_QUEUES; ++i) { dispatch[i]->Sync(); EXPECT_EQ(dst[i], src[i]); delete dispatch[i]; } ++numIter; curTime = GetSystemTickCountInMicroSec(); timePassed = (curTime - initialTime) / 1000000; } while (timePassed < TEST_TIME_SEC); LOG() << "Total iterated : " << std::dec << numIter << std::endl; for (i = 0; i < MAX_CP_QUEUES; ++i) EXPECT_SUCCESS(queues[i].Destroy()); TEST_END } TEST_F(KFDQMTest, CpuWriteCoherence) { TEST_START(TESTPROFILE_RUNALL); PM4Queue queue; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer destBuf(PAGE_SIZE, defaultGPUNode); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaEvent *event; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &event)); /* The queue might be full and we fail to submit. There is always one word space unused in queue. * So let rptr one step ahead then we continually submit packet. */ queue.PlaceAndSubmitPacket(PM4NopPacket()); queue.Wait4PacketConsumption(); EXPECT_EQ(1, queue.Rptr()); do { queue.PlaceAndSubmitPacket(PM4NopPacket()); } while (queue.Wptr() != 0); queue.Wait4PacketConsumption(); EXPECT_EQ(0, queue.Rptr()); /* Now that the GPU has cached the PQ contents, we modify them in CPU cache and * ensure that the GPU sees the updated value: */ queue.PlaceAndSubmitPacket(PM4WriteDataPacket(destBuf.As(), 0x42, 0x42)); queue.Wait4PacketConsumption(event); WaitOnValue(destBuf.As(), 0x42); hsaKmtDestroyEvent(event); TEST_END } TEST_F(KFDQMTest, CreateAqlCpQueue) { TEST_START(TESTPROFILE_RUNALL) AqlQueue queue; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer pointers(PAGE_SIZE, defaultGPUNode, /*zero*/true, /*local*/false, /*exec*/false, /*isScratch */false, /* isReadOnly */false, /* isUncached */false, /* NonPaged */g_baseTest->NeedNonPagedWptr(defaultGPUNode)); ASSERT_SUCCESS(queue.Create(defaultGPUNode, PAGE_SIZE, pointers.As())); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDQMTest, QueueLatency) { TEST_START(TESTPROFILE_RUNALL); PM4Queue queue; const int queueSize = PAGE_SIZE * 2; const int packetSize = PM4ReleaseMemoryPacket(m_FamilyId, 0, 0, 0, 0, 0).SizeInBytes(); /* We always leave one NOP(dword) empty after packet which is required by ring itself. * We also place NOPs when queue wraparound to avoid crossing buffer end. See PlacePacket(). * So the worst case is that we need two packetSize space to place one packet. * Like below, N=NOP,E=Empty,P=Packet. * |E|E|E|E|E|E|E|rptr...wptr|E|E|E|E|E| ---> |P|P|P|P|P|P|E|rptr...wptr|N|N|N|N|N| * So to respect that, we reserve packetSize space for these additional NOPs. * Also we reserve the remainder of the division by packetSize explicitly. * Reserve another packetSize for event-based wait which uses a releseMemory packet. */ const int reservedSpace = packetSize + queueSize % packetSize + packetSize; const int slots = (queueSize - reservedSpace) / packetSize; HSAint64 queue_latency_avg = 0, queue_latency_min, queue_latency_max, queue_latency_med; HSAint64 overhead, workload; HSAint64 *queue_latency_arr = reinterpret_cast(calloc(slots, sizeof(HSAint64))); const int skip = 2; const char *fs[skip] = {"1st", "2nd"}; HsaClockCounters *ts; HSAuint64 *qts; int i = 0; ASSERT_NE((HSAuint64)queue_latency_arr, 0); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; ASSERT_SUCCESS(queue.Create(defaultGPUNode, queueSize)); LOG() << std::dec << "Queue Submit NanoSeconds (" << slots << " Packets)" << std::endl; HsaMemoryBuffer buf(ALIGN_UP(slots * sizeof(HsaClockCounters), PAGE_SIZE), 0); ts = buf.As(); HsaMemoryBuffer qbuf(ALIGN_UP(slots * sizeof(HSAuint64), PAGE_SIZE), 0); qts = qbuf.As(); HsaEvent *event; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &event)); /* GpuCounter overhead*/ do { hsaKmtGetClockCounters(defaultGPUNode, &ts[i]); } while (++i < slots); overhead = ts[slots-1].GPUClockCounter - ts[0].GPUClockCounter; overhead /= 2 * (slots - 1); /* Submit packets serially*/ i = 0; do { queue.PlacePacket(PM4ReleaseMemoryPacket(m_FamilyId, true, (HSAuint64)&qts[i], 0, true, 1)); hsaKmtGetClockCounters(defaultGPUNode, &ts[i]); queue.SubmitPacket(); queue.Wait4PacketConsumption(event); } while (++i < slots); /* Calculate timing which includes workload and overhead*/ i = 0; do { HSAint64 queue_latency = qts[i] - ts[i].GPUClockCounter; EXPECT_GE(queue_latency, 0); queue_latency_arr[i] = queue_latency; if (i >= skip) queue_latency_avg += queue_latency; } while (++i < slots); /* Calculate avg from packet[skip, slots-1] */ queue_latency_avg /= (slots - skip); /* Workload of queue packet itself */ i = 0; do { queue.PlacePacket(PM4ReleaseMemoryPacket(m_FamilyId, true, (HSAuint64)&qts[i], 0, true, 1)); } while (++i < slots); queue.SubmitPacket(); queue.Wait4PacketConsumption(event); hsaKmtDestroyEvent(event); /* qts[i] records the timestamp of the end of packet[i] which is * approximate that of the beginging of packet[i+1]. * The workload total is [0, skip], [skip+1, slots-1]. * And We ignore [0, skip], that means we ignore (skip+1) packets. */ workload = qts[slots - 1] - qts[skip]; workload /= (slots - 1 - skip); EXPECT_GE(workload, 0); i = 0; do { /* The queue_latency is not that correct as the workload and overhead are average*/ queue_latency_arr[i] -= workload + overhead; /* The First submit takes an HSAint64 time*/ if (i < skip) LOG() << "Queue Latency " << fs[i] << ": \t" << CounterToNanoSec(queue_latency_arr[i]) << std::endl; } while (++i < slots); std::sort(queue_latency_arr + skip, queue_latency_arr + slots); queue_latency_min = queue_latency_arr[skip]; queue_latency_med = queue_latency_arr[(slots+skip)/2]; queue_latency_max = queue_latency_arr[slots-1]; LOG() << "Queue Latency Avg: \t" << CounterToNanoSec(queue_latency_avg) << std::endl; LOG() << "Queue Latency Min: \t" << CounterToNanoSec(queue_latency_min) << std::endl; LOG() << "Queue Latency Median: \t" << CounterToNanoSec(queue_latency_med) << std::endl; LOG() << "Queue Latency Max: \t" << CounterToNanoSec(queue_latency_max) << std::endl; LOG() << "Queue Packet Workload: \t" << CounterToNanoSec(workload) << std::endl; LOG() << "Get GpuCounter Overhead: \t" << CounterToNanoSec(overhead) << std::endl; RECORD(CounterToNanoSec(queue_latency_avg)) << "Queue-Latency-Avg"; RECORD(CounterToNanoSec(queue_latency_min)) << "Queue-Latency-Min"; RECORD(CounterToNanoSec(queue_latency_med)) << "Queue-Latency-Med"; RECORD(CounterToNanoSec(queue_latency_max)) << "Queue-Latency-Max"; RECORD(CounterToNanoSec(workload)) << "Queue-Packet-Workload"; RECORD(CounterToNanoSec(overhead)) << "GpuCounter-Overhead"; TEST_END } TEST_F(KFDQMTest, CpQueueWraparound) { TEST_START(TESTPROFILE_RUNALL); PM4Queue queue; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer destBuf(PAGE_SIZE, defaultGPUNode); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); HsaEvent *event; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &event)); for (unsigned int pktIdx = 0; pktIdx <= PAGE_SIZE/sizeof(PM4WRITE_DATA_CI); ++pktIdx) { queue.PlaceAndSubmitPacket(PM4WriteDataPacket(destBuf.As(), pktIdx, pktIdx)); queue.Wait4PacketConsumption(event); WaitOnValue(destBuf.As(), pktIdx); } for (unsigned int pktIdx = 0; pktIdx <= PAGE_SIZE/sizeof(PM4WRITE_DATA_CI); ++pktIdx) { queue.PlaceAndSubmitPacket(PM4WriteDataPacket(destBuf.As(), pktIdx, pktIdx)); queue.Wait4PacketConsumption(event); WaitOnValue(destBuf.As(), pktIdx); } hsaKmtDestroyEvent(event); EXPECT_SUCCESS(queue.Destroy()); TEST_END } TEST_F(KFDQMTest, SdmaQueueWraparound) { TEST_START(TESTPROFILE_RUNALL); int bufSize = PAGE_SIZE; SDMAQueue queue; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer destBuf(bufSize << 1, defaultGPUNode, false); HsaMemoryBuffer srcBuf(bufSize, defaultGPUNode, false); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); for (unsigned int pktIdx = 0; pktIdx <= queue.Size()/sizeof(SDMA_PKT_COPY_LINEAR); ++pktIdx) { destBuf.Fill(0x0); srcBuf.Fill(pktIdx); queue.PlaceAndSubmitPacket( SDMACopyDataPacket(queue.GetFamilyId(), destBuf.As(), srcBuf.As(), bufSize)); queue.PlaceAndSubmitPacket( SDMAWriteDataPacket(queue.GetFamilyId(), destBuf.As() + bufSize/4, 0x02020202)); queue.Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(destBuf.As() + bufSize/4, 0x02020202)); EXPECT_SUCCESS(memcmp( destBuf.As(), srcBuf.As(), bufSize)); } for (unsigned int pktIdx = 0; pktIdx <= queue.Size()/sizeof(SDMA_PKT_WRITE_UNTILED); ++pktIdx) { queue.PlaceAndSubmitPacket(SDMAWriteDataPacket(queue.GetFamilyId(), destBuf.As(), pktIdx)); queue.Wait4PacketConsumption(); WaitOnValue(destBuf.As(), pktIdx); } EXPECT_SUCCESS(queue.Destroy()); TEST_END } struct AtomicIncThreadParams { HSAint64* pDest; volatile unsigned int count; volatile bool loop; }; unsigned int AtomicIncThread(void* pCtx) { AtomicIncThreadParams* pArgs = reinterpret_cast(pCtx); while (pArgs->loop) { AtomicInc(pArgs->pDest); ++pArgs->count; } LOG() << "CPU atomic increments finished" << std::endl; return 0; } TEST_F(KFDQMTest, Atomics) { TEST_START(TESTPROFILE_RUNALL); int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (!hasPciAtomicsSupport(defaultGPUNode)) { LOG() << "Skipping test: Node doesn't support Atomics." << std::endl; return; } HsaMemoryBuffer isaBuf(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer destBuf(PAGE_SIZE, defaultGPUNode); PM4Queue queue; ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(AtomicIncIsa, isaBuf.As())); Dispatch dispatch(isaBuf); dispatch.SetArgs(destBuf.As(), NULL); dispatch.SetDim(1024, 1, 1); hsaKmtSetMemoryPolicy(defaultGPUNode, HSA_CACHING_CACHED, HSA_CACHING_CACHED, NULL, 0); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); AtomicIncThreadParams params; params.pDest = destBuf.As(); params.loop = true; params.count = 0; uint64_t threadId; ASSERT_EQ(true, StartThread(&AtomicIncThread, ¶ms, threadId)); LOG() << "Waiting for CPU to atomic increment 1000 times" << std::endl; while (params.count < 1000) {} LOG() << "Submitting the GPU atomic increment shader" << std::endl; dispatch.Submit(queue); dispatch.Sync(); params.loop = false; WaitForThread(threadId); EXPECT_EQ(destBuf.As()[0], 1024 + params.count); LOG() << "GPU increments: 1024, CPU increments: " << std::dec << params.count << std::endl; queue.Destroy(); TEST_END } TEST_F(KFDQMTest, mGPUShareBO) { TEST_START(TESTPROFILE_RUNALL); unsigned int src_node = 2; unsigned int dst_node = 1; if (g_TestDstNodeId != -1 && g_TestNodeId != -1) { src_node = g_TestNodeId; dst_node = g_TestDstNodeId; } HsaMemoryBuffer shared_addr(PAGE_SIZE, dst_node, true, false, false, false); HsaMemoryBuffer srcNodeMem(PAGE_SIZE, src_node); HsaMemoryBuffer dstNodeMem(PAGE_SIZE, dst_node); /* Handle ISA to write to local memory BO */ HsaMemoryBuffer isaBufferSrc(PAGE_SIZE, src_node, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer isaBufferDst(PAGE_SIZE, dst_node, true/*zero*/, false/*local*/, true/*exec*/); srcNodeMem.Fill(0x05050505); ASSERT_SUCCESS(m_pAsm->RunAssemble(CopyDwordIsa)); m_pAsm->CopyInstrStream(isaBufferSrc.As()); SyncDispatch(isaBufferSrc, srcNodeMem.As(), shared_addr.As(), src_node); m_pAsm->CopyInstrStream(isaBufferDst.As()); SyncDispatch(isaBufferDst, shared_addr.As(), dstNodeMem.As(), dst_node); EXPECT_EQ(dstNodeMem.As()[0], 0x05050505); EXPECT_SUCCESS(shared_addr.UnmapMemToNodes(&dst_node, 1)); TEST_END } static void sdma_copy(HSAuint32 node, void *src, void *const dst[], int n, HSAuint64 size) { SDMAQueue sdmaQueue; HsaEvent *event; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, node, &event)); ASSERT_SUCCESS(sdmaQueue.Create(node)); sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), dst, src, n, size)); sdmaQueue.Wait4PacketConsumption(event); EXPECT_SUCCESS(sdmaQueue.Destroy()); hsaKmtDestroyEvent(event); } static void sdma_fill(HSAint32 node, void *dst, unsigned int data, HSAuint64 size) { SDMAQueue sdmaQueue; HsaEvent *event; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, node, &event)); ASSERT_SUCCESS(sdmaQueue.Create(node)); sdmaQueue.PlaceAndSubmitPacket(SDMAFillDataPacket(sdmaQueue.GetFamilyId(), dst, data, size)); sdmaQueue.Wait4PacketConsumption(event); EXPECT_SUCCESS(sdmaQueue.Destroy()); hsaKmtDestroyEvent(event); } TEST_F(KFDQMTest, P2PTest) { TEST_START(TESTPROFILE_RUNALL); if (!is_dgpu()) { LOG() << "Skipping test: Two GPUs are required, but no dGPUs are present." << std::endl; return; } const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); if (gpuNodes.size() < 2) { LOG() << "Skipping test: At least two GPUs are required." << std::endl; return; } std::vector nodes; /* This test simulates RT team's P2P part in IPCtest: * * +------------------------------------------------+ * | gpu1 gpu2 gpuX | * |gpu1 mem ----> gpu2 mem ----> gpuX mem | * | \ \ \ | * | \ \ \ | * | system buffer system buffer system buffer| * +------------------------------------------------+ * * Copy data from current GPU memory to next GPU memory and system memory * Using current GPU, aka p2p push. * Verify the system buffer has the expected content after each push. */ /* Users can use "--node=gpu1 --dst_node=gpu2" to specify devices */ if (g_TestDstNodeId != -1 && g_TestNodeId != -1) { nodes.push_back(g_TestNodeId); nodes.push_back(g_TestDstNodeId); if (!m_NodeInfo.IsPeerAccessibleByNode(g_TestNodeId, g_TestDstNodeId)) { LOG() << "Skipping test: Dst GPU specified is not peer-accessible." << std::endl; return; } if (nodes[0] == nodes[1]) { LOG() << "Skipping test: Different GPUs must be specified (2 GPUs required)." << std::endl; return; } } else { nodes = m_NodeInfo.GetNodesWithGPU(); if (nodes.size() < 2) { LOG() << "Skipping test: Test requires at least one large bar GPU." << std::endl; LOG() << " or two GPUs are XGMI connected." << std::endl; return; } } HSAuint32 *sysBuf; HSAuint32 size = 16ULL<<20; // bigger than 16MB to test non-contiguous memory HsaMemFlags memFlags = {0}; HsaMemMapFlags mapFlags = {0}; memFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; memFlags.ui32.HostAccess = 0; memFlags.ui32.NonPaged = 1; memFlags.ui32.NoNUMABind = 1; unsigned int end = size / sizeof(HSAuint32) - 1; /* 1. Allocate a system buffer and allow the access to GPUs */ EXPECT_SUCCESS(hsaKmtAllocMemory(0, size, m_MemoryFlags, reinterpret_cast(&sysBuf))); EXPECT_SUCCESS(hsaKmtMapMemoryToGPUNodes(sysBuf, size, NULL, mapFlags, nodes.size(), (HSAuint32 *)&nodes[0])); #define MAGIC_NUM 0xdeadbeaf /* First GPU fills mem with MAGIC_NUM */ void *src, *dst; HSAuint32 cur = nodes[0], next; ASSERT_SUCCESS(hsaKmtAllocMemory(cur, size, memFlags, reinterpret_cast(&src))); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(src, size, NULL)); sdma_fill(cur, src, MAGIC_NUM, size); for (unsigned i = 1; i <= nodes.size(); i++) { int n; memset(sysBuf, 0, size); /* Last GPU just copy mem to sysBuf*/ if (i == nodes.size()) { n = 1; next = 0;/*system memory node*/ dst = 0; } else { n = 2; next = nodes[i]; /* check if cur access next node */ if (!m_NodeInfo.IsPeerAccessibleByNode(next, cur)) continue; ASSERT_SUCCESS(hsaKmtAllocMemory(next, size, memFlags, reinterpret_cast(&dst))); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(dst, size, NULL)); } LOG() << "Test " << cur << " -> " << next << std::endl; /* Copy to sysBuf and next GPU*/ void *dst_array[] = {sysBuf, dst}; sdma_copy(cur, src, dst_array, n, size); /* Verify the data*/ EXPECT_EQ(sysBuf[0], MAGIC_NUM); EXPECT_EQ(sysBuf[end], MAGIC_NUM); LOG() << "PASS " << cur << " -> " << next << std::endl; EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(src)); EXPECT_SUCCESS(hsaKmtFreeMemory(src, size)); cur = next; src = dst; } EXPECT_SUCCESS(hsaKmtUnmapMemoryToGPU(sysBuf)); EXPECT_SUCCESS(hsaKmtFreeMemory(sysBuf, size)); TEST_END } TEST_F(KFDQMTest, PM4EventInterrupt) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; const HSAuint64 bufSize = PAGE_SIZE; const int packetCount = bufSize / sizeof(unsigned int); const int totalPacketSize = packetCount * PM4WriteDataPacket(0, 0).SizeInBytes() + PM4ReleaseMemoryPacket(m_FamilyId, 0, 0, 0).SizeInBytes(); const int queueSize = RoundToPowerOf2(totalPacketSize); /* 4 PM4 queues will be running at same time.*/ const int numPM4Queue = 4; HsaEvent *event[numPM4Queue]; PM4Queue queue[numPM4Queue]; HsaMemoryBuffer *destBuf[numPM4Queue]; unsigned int *buf[numPM4Queue]; for (int i = 0; i < numPM4Queue; i++) { destBuf[i] = new HsaMemoryBuffer(bufSize, defaultGPUNode, true, false); // System memory buf[i] = destBuf[i]->As(); } /* A simple loop here to give more pressure.*/ for (int test_count = 0; test_count < 1024; test_count++) { for (int i = 0; i < numPM4Queue; i++) { ASSERT_SUCCESS(queue[i].Create(defaultGPUNode, queueSize)); ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &event[i])); /* Let CP have some workload first.*/ for(int index = 0; index < packetCount; index++) queue[i].PlacePacket(PM4WriteDataPacket(buf[i] + index, 0xdeadbeaf)); /* releaseMemory packet makes sure all previous written data is visible.*/ queue[i].PlacePacket(PM4ReleaseMemoryPacket(m_FamilyId, 0, reinterpret_cast(event[i]->EventData.HWData2), event[i]->EventId, true)); } for (int i = 0; i < numPM4Queue; i++) queue[i].SubmitPacket(); for (int i = 0; i < numPM4Queue; i++) { EXPECT_SUCCESS(hsaKmtWaitOnEvent(event[i], g_TestTimeOut)); EXPECT_EQ(buf[i][0], 0xdeadbeaf); EXPECT_EQ(buf[i][packetCount - 1], 0xdeadbeaf); memset(buf[i], 0, bufSize); } for (int i = 0; i < numPM4Queue; i++) { EXPECT_SUCCESS(queue[i].Destroy()); EXPECT_SUCCESS(hsaKmtDestroyEvent(event[i])); } } for (int i = 0; i < numPM4Queue; i++) delete destBuf[i]; TEST_END } #include "KFDTestUtilQueue.hpp" TEST_F(KFDQMTest, SdmaEventInterrupt) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; const HSAuint64 bufSize = 4 << 20; HsaMemoryBuffer srcBuf(bufSize, 0); // System memory. HSAuint64 *src = srcBuf.As(); TimeStamp *tsbuf = srcBuf.As(); tsbuf = reinterpret_castALIGN_UP(tsbuf, sizeof(TimeStamp)); /* Have 3 queues created for test.*/ const int numSDMAQueue = 3; HsaEvent *event[numSDMAQueue]; SDMAQueue queue[numSDMAQueue]; HsaMemoryBuffer *destBuf[numSDMAQueue]; HSAuint64 *dst[numSDMAQueue]; for (int i = 0; i < numSDMAQueue; i++) { destBuf[i] = new HsaMemoryBuffer(bufSize, defaultGPUNode, true, false); // System memory dst[i] = destBuf[i]->As(); } /* Test 1 queue, 2 queues, 3 queues running at same time one by one.*/ for (int testSDMAQueue = 1; testSDMAQueue <= numSDMAQueue; testSDMAQueue++) /* A simple loop here to give more pressure.*/ for (int test_count = 0; test_count < 2048; test_count++) { for (int i = 0; i < testSDMAQueue; i++) { TimeStamp *ts = tsbuf + i * 32; ASSERT_SUCCESS(queue[i].Create(defaultGPUNode)); /* FIXME * We create event every time along with queue. * However that will significantly enhance the failure of sdma event timeout. */ ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, defaultGPUNode, &event[i])); /* Get the timestamp directly. The first member of HsaClockCounters and TimeStamp is GPU clock counter.*/ hsaKmtGetClockCounters(defaultGPUNode, reinterpret_cast(&ts[0])); /* Let sDMA have some workload first.*/ queue[i].PlacePacket(SDMATimePacket(&ts[1])); queue[i].PlacePacket( SDMACopyDataPacket(queue[i].GetFamilyId(), dst[i], src, bufSize)); queue[i].PlacePacket(SDMATimePacket(&ts[2])); queue[i].PlacePacket( SDMAFencePacket(queue[i].GetFamilyId(), reinterpret_cast(event[i]->EventData.HWData2), event[i]->EventId)); queue[i].PlacePacket(SDMATimePacket(&ts[3])); queue[i].PlacePacket(SDMATrapPacket(event[i]->EventId)); queue[i].PlacePacket(SDMATimePacket(&ts[4])); /* Will verify the value of srcBuf and destBuf later. Give it a different value each time.*/ src[0] = ts[0].timestamp; } for (int i = 0; i < testSDMAQueue; i++) queue[i].SubmitPacket(); for (int i = 0; i < testSDMAQueue; i++) { TimeStamp *ts = tsbuf + i * 32; HSAKMT_STATUS ret = hsaKmtWaitOnEvent(event[i], g_TestTimeOut); if (dst[i][0] != src[0]) WARN() << "SDMACopyData FAIL! " << std::dec << dst[i][0] << " VS " << src[0] << std::endl; if (ret == HSAKMT_STATUS_SUCCESS) { for (int i = 1; i <= 4; i++) /* Is queue latency too big? The workload is really small.*/ if (CounterToNanoSec(ts[i].timestamp - ts[i - 1].timestamp) > 1000000000) WARN() << "SDMA queue latency is bigger than 1s!" << std::endl; } else { WARN() << "Event On Queue " << testSDMAQueue << ":" << i << " Timeout, try to resubmit packets!" << std::endl; queue[i].SubmitPacket(); if (hsaKmtWaitOnEvent(event[i], g_TestTimeOut) == HSAKMT_STATUS_SUCCESS) WARN() << "The timeout event is signaled!" << std::endl; else WARN() << "The timeout event is lost after resubmit!" << std::endl; LOG() << "Time Consumption (ns)" << std::endl; for (int i = 1; i <= 4; i++) LOG() << std::dec << i << ": " << CounterToNanoSec(ts[i].timestamp - ts[i - 1].timestamp) << std::endl; } EXPECT_SUCCESS(ret); } for (int i = 0; i < testSDMAQueue; i++) { EXPECT_SUCCESS(queue[i].Destroy()); EXPECT_SUCCESS(hsaKmtDestroyEvent(event[i])); } } for (int i = 0; i < numSDMAQueue; i++) delete destBuf[i]; TEST_END } #define DOORBELL_WRITE_USE_SDMA TEST_F(KFDQMTest, GPUDoorbellWrite) { TEST_START(TESTPROFILE_RUNALL) int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer destBuf(PAGE_SIZE, 0, true); PM4Queue pm4Queue; #ifdef DOORBELL_WRITE_USE_SDMA SDMAQueue otherQueue; #else PM4Queue otherQueue; #endif ASSERT_SUCCESS(pm4Queue.Create(defaultGPUNode)); ASSERT_SUCCESS(otherQueue.Create(defaultGPUNode)); /* Place PM4 packet in the queue, but don't submit it */ pm4Queue.PlacePacket(PM4WriteDataPacket(destBuf.As(), 0x12345678, 0x87654321)); HsaQueueResource *qRes = pm4Queue.GetResource(); if (m_FamilyId < FAMILY_AI) { unsigned int pendingWptr = pm4Queue.GetPendingWptr(); #ifdef DOORBELL_WRITE_USE_SDMA /* Write the wptr and doorbell update using the GPU's SDMA * engine. This should submit the PM4 packet on the first * queue. */ otherQueue.PlacePacket(SDMAWriteDataPacket(otherQueue.GetFamilyId(), qRes->Queue_write_ptr, pendingWptr)); otherQueue.PlacePacket(SDMAWriteDataPacket(otherQueue.GetFamilyId(), qRes->Queue_DoorBell, pendingWptr)); #else /* Write the wptr and doorbell update using WRITE_DATA packets * on a second PM4 queue. This should submit the PM4 packet on * the first queue. */ otherQueue.PlacePacket( PM4ReleaseMemoryPacket(m_FamilyId, true, (HSAuint64)qRes->Queue_write_ptr, pendingWptr, false)); otherQueue.PlacePacket( PM4ReleaseMemoryPacket(m_FamilyId, true, (HSAuint64)qRes->Queue_DoorBell, pendingWptr, false)); #endif otherQueue.SubmitPacket(); } else { HSAuint64 pendingWptr64 = pm4Queue.GetPendingWptr64(); #ifdef DOORBELL_WRITE_USE_SDMA /* Write the wptr and doorbell update using the GPU's SDMA * engine. This should submit the PM4 packet on the first * queue. */ otherQueue.PlacePacket(SDMAWriteDataPacket(otherQueue.GetFamilyId(), qRes->Queue_write_ptr, 2, &pendingWptr64)); otherQueue.PlacePacket(SDMAWriteDataPacket(otherQueue.GetFamilyId(), qRes->Queue_DoorBell, 2, &pendingWptr64)); #else /* Write the 64-bit wptr and doorbell update using RELEASE_MEM * packets without IRQs on a second PM4 queue. RELEASE_MEM * should perform one atomic 64-bit access. This should submit * the PM4 packet on the first queue. */ otherQueue.PlacePacket( PM4ReleaseMemoryPacket(m_FamilyId, true, (HSAuint64)qRes->Queue_write_ptr, pendingWptr64, true)); otherQueue.PlacePacket( PM4ReleaseMemoryPacket(m_FamilyId, true, (HSAuint64)qRes->Queue_DoorBell, pendingWptr64, true)); #endif otherQueue.SubmitPacket(); } /* Check that the PM4 packet has been executed */ EXPECT_TRUE(WaitOnValue(destBuf.As(), 0x12345678)); EXPECT_TRUE(WaitOnValue(destBuf.As()+1, 0x87654321)); EXPECT_SUCCESS(pm4Queue.Destroy()); EXPECT_SUCCESS(otherQueue.Destroy()); TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDQMTest.hpp000066400000000000000000000040541446477712600240520ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_QCM_TEST__H__ #define __KFD_QCM_TEST__H__ #include #include "PM4Queue.hpp" #include "KFDBaseComponentTest.hpp" #include "Dispatch.hpp" class KFDQMTest : public KFDBaseComponentTest { public: KFDQMTest() {} ~KFDQMTest() {} protected: virtual void SetUp(); virtual void TearDown(); void SyncDispatch(const HsaMemoryBuffer& isaBuffer, void* pSrcBuf, void* pDstBuf, int node = -1); HSAint64 TimeConsumedwithCUMask(int node, uint32_t *mask, uint32_t mask_count); HSAint64 GetAverageTimeConsumedwithCUMask(int node, uint32_t *mask, uint32_t mask_count, int iterations); protected: // Members /* Acceptable performance for CU Masking should be within 5% of linearly-predicted performance */ const double CuVariance = 0.15; const double CuNegVariance = 1.0 - CuVariance; const double CuPosVariance = 1.0 + CuVariance; }; #endif // __KFD_QCM_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDRASTest.cpp000066400000000000000000000126121446477712600241540ustar00rootroot00000000000000/* * Copyright (C) 2019 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include "linux/kfd_ioctl.h" #include "KFDRASTest.hpp" #include "PM4Queue.hpp" #define AMDGPU_DEBUGFS_NODES "/sys/kernel/debug/dri/" #define RAS_CONTROL "ras/ras_ctrl" #define DRM_RENDER_NUMBER 64 void KFDRASTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); char path[256], name[128], tmp[128]; int renderNode, minor, i; FILE *pDriMinor, *pDriPrimary; uint32_t rasFeatures = 0; HsaEventDescriptor eventDesc; m_pRasEvent = NULL; m_setupStatus = false; m_defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); renderNode = KFDBaseComponentTest::FindDRMRenderNode(m_defaultGPUNode); if (renderNode < 0) { LOG() << "Skipping test: Could not find render node for default GPU." << std::endl; throw; } amdgpu_query_info(m_RenderNodes[renderNode].device_handle, AMDGPU_INFO_RAS_ENABLED_FEATURES, sizeof(uint32_t), &rasFeatures); if (!(rasFeatures & (AMDGPU_INFO_RAS_ENABLED_SDMA | AMDGPU_INFO_RAS_ENABLED_UMC | AMDGPU_INFO_RAS_ENABLED_GFX))) { LOG() << "Skipping test: GPU doesn't support RAS features!" << std::endl; throw; } minor = renderNode + 128; snprintf(path, sizeof(path), "%s%d/%s", AMDGPU_DEBUGFS_NODES, minor, "name"); pDriMinor = fopen(path, "r"); if (!pDriMinor) { LOG() << "Skipping test: DRM render debugfs node requires root access!" << std::endl; throw; } memset(name, 0, sizeof(name)); fread(name, sizeof(name), 1, pDriMinor); fclose(pDriMinor); for (i = 0; i < DRM_RENDER_NUMBER; i++) { snprintf(path, sizeof(path), "%s%d/%s", AMDGPU_DEBUGFS_NODES, i, "name"); pDriPrimary = fopen(path, "r"); if (!pDriPrimary) continue; memset(tmp, 0, sizeof(tmp)); fread(tmp, sizeof(tmp), 1, pDriPrimary); if (!strcmp(name, tmp)) { fclose(pDriPrimary); break; } fclose(pDriPrimary); } if (i == DRM_RENDER_NUMBER) { LOG() << "Skipping test: Could not find the debugfs node!" << std::endl; throw; } snprintf(path, sizeof(path), "%s%d/%s", AMDGPU_DEBUGFS_NODES, i, RAS_CONTROL); m_pFile = fopen(path, "w"); if (!m_pFile) { LOG() << "Skipping test: RAS error injection requires root access!" << std::endl; throw; } eventDesc.EventType = HSA_EVENTTYPE_MEMORY; eventDesc.NodeId = m_defaultGPUNode; eventDesc.SyncVar.SyncVar.UserData = NULL; eventDesc.SyncVar.SyncVarSize = 0; ASSERT_SUCCESS(hsaKmtCreateEvent(&eventDesc, true, false, &m_pRasEvent)); m_setupStatus = true; ROUTINE_END } void KFDRASTest::TearDown() { ROUTINE_START if (m_pRasEvent != NULL) { EXPECT_SUCCESS(hsaKmtDestroyEvent(m_pRasEvent)); } fclose(m_pFile); KFDBaseComponentTest::TearDown(); ROUTINE_END } TEST_F(KFDRASTest, BasicTest) { TEST_START(TESTPROFILE_RUNALL); if (!m_setupStatus) { return; } // write an uncorrectable error injection at address 0 as value 0 fwrite("inject umc ue 0 0", sizeof(char), 17, m_pFile); fflush(m_pFile); EXPECT_SUCCESS(hsaKmtWaitOnEvent(m_pRasEvent, g_TestTimeOut)); EXPECT_EQ(1, m_pRasEvent->EventData.EventData.MemoryAccessFault.Failure.ErrorType); TEST_END; } TEST_F(KFDRASTest, MixEventsTest) { TEST_START(TESTPROFILE_RUNALL); if (!m_setupStatus) { return; } PM4Queue queue; HsaEvent* pHsaEvent; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, m_defaultGPUNode, &pHsaEvent)); ASSERT_NE(0, pHsaEvent->EventData.HWData2); ASSERT_SUCCESS(queue.Create(m_defaultGPUNode)); queue.PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, false, pHsaEvent->EventData.HWData2, pHsaEvent->EventId)); queue.Wait4PacketConsumption(); EXPECT_SUCCESS(hsaKmtWaitOnEvent(pHsaEvent, g_TestTimeOut)); fwrite("inject umc ue 0 0", sizeof(char), 17, m_pFile); fflush(m_pFile); EXPECT_SUCCESS(hsaKmtWaitOnEvent(m_pRasEvent, g_TestTimeOut)); EXPECT_EQ(1, m_pRasEvent->EventData.EventData.MemoryAccessFault.Failure.ErrorType); EXPECT_SUCCESS(queue.Destroy()); EXPECT_SUCCESS(hsaKmtDestroyEvent(pHsaEvent)); TEST_END; } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDRASTest.hpp000066400000000000000000000040221446477712600241550ustar00rootroot00000000000000/* * Copyright (C) 2019 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDBaseComponentTest.hpp" #ifndef __KFD_RAS_TEST__H__ #define __KFD_RAS_TEST__H__ // To be removed when amdgpu_drm.h updated with those definitions #ifndef AMDGPU_INFO_RAS_ENABLED_FEATURES #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) #endif class KFDRASTest : public KFDBaseComponentTest { public: KFDRASTest(void) {} ~KFDRASTest(void) {} // @brief Executed before every test in KFDRASTest. virtual void SetUp(); // @brief Executed after every test in KFDRASTest. virtual void TearDown(); protected: static const unsigned int EVENT_TIMEOUT = 5000; // 5 seconds HsaEvent* m_pRasEvent; HSAint32 m_defaultGPUNode; FILE* m_pFile; bool m_setupStatus; }; #endif // __KFD_RAS_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDSVMEvictTest.cpp000066400000000000000000000311511446477712600251660ustar00rootroot00000000000000/* * Copyright (C) 2020 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDSVMEvictTest.hpp" #include #include #include #include "PM4Queue.hpp" #include "PM4Packet.hpp" #include "SDMAPacket.hpp" #include "SDMAQueue.hpp" #include "Dispatch.hpp" #define N_PROCESSES (4) /* number of processes running in parallel, at least 2 */ #define ALLOCATE_BUF_SIZE_MB (64) #define ALLOCATE_RETRY_TIMES (3) #define MAX_WAVEFRONTS (512) void KFDSVMEvictTest::SetUp() { ROUTINE_START KFDLocalMemoryTest::SetUp(); SVMSetXNACKMode(GetParam()); ROUTINE_END } void KFDSVMEvictTest::TearDown() { ROUTINE_START SVMRestoreXNACKMode(); KFDLocalMemoryTest::TearDown(); ROUTINE_END } HSAint32 KFDSVMEvictTest::GetBufferCounter(HSAuint64 vramSize, HSAuint64 vramBufSize) { HSAuint64 vramBufSizeInPages = vramBufSize >> PAGE_SHIFT; HSAuint64 sysMemSize = GetSysMemSize(); HSAuint64 size, sizeInPages; HSAuint32 count; LOG() << "Found System RAM of " << std::dec << (sysMemSize >> 20) << "MB" << std::endl; /* use one third of total system memory for eviction buffer to test * limit max allocate size to double of vramSize * count is zero if not enough memory (sysMemSize/3 + vramSize) < (vramBufSize * N_PROCESSES) */ size = sysMemSize / 3 + vramSize; size = size > vramSize << 1 ? vramSize << 1 : size; /* Check if there is enough system memory to pass test, * KFD system memory limit is 15/16. */ if (size > (sysMemSize - (sysMemSize >> 4))) return 0; sizeInPages = size >> PAGE_SHIFT; count = sizeInPages / (vramBufSizeInPages * N_PROCESSES); return count; } HSAint64 KFDSVMEvictTest::GetBufferSize(HSAuint64 vramSize, HSAuint32 count) { HSAuint64 sysMemSize = GetSysMemSize(); HSAuint64 size, sizeInPages; HSAuint64 vramBufSizeInPages; LOG() << "Found System RAM of " << std::dec << (sysMemSize >> 20) << "MB" << std::endl; /* use one third of total system memory for eviction buffer to test * limit max allocate size to duoble of vramSize * count is zero if not enough memory (sysMemSize/3 + vramSize) < (vramBufSize * N_PROCESSES) */ size = sysMemSize / 3 + vramSize; size = size > vramSize << 1 ? vramSize << 1 : size; sizeInPages = size >> PAGE_SHIFT; vramBufSizeInPages = sizeInPages / (count * N_PROCESSES); return vramBufSizeInPages << PAGE_SHIFT; } void KFDSVMEvictTest::AllocBuffers(HSAuint32 defaultGPUNode, HSAuint32 count, HSAuint64 vramBufSize, std::vector &pBuffers) { HSAuint64 totalMB; totalMB = N_PROCESSES * count * (vramBufSize >> 20); if (m_IsParent) { LOG() << "Testing " << N_PROCESSES << "*" << count << "*" << (vramBufSize>>20) << "(="<< totalMB << ")MB" << std::endl; } HSAKMT_STATUS ret; HSAuint32 retry = 0; for (HSAuint32 i = 0; i < count; i++) { m_pBuf = mmap(0, vramBufSize, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_NE(MAP_FAILED, m_pBuf); m_Flags = (HSA_SVM_FLAGS)0; retry: ret = RegisterSVMRange(defaultGPUNode, m_pBuf, vramBufSize, defaultGPUNode, m_Flags); if (ret == HSAKMT_STATUS_SUCCESS) { pBuffers.push_back(m_pBuf); retry = 0; } else { if (retry++ > ALLOCATE_RETRY_TIMES) { munmap(m_pBuf, vramBufSize); break; } printf("retry %d allocate vram\n", retry); /* wait for 1 second to try allocate again */ sleep(1); goto retry; } } } void KFDSVMEvictTest::FreeBuffers(std::vector &pBuffers, HSAuint64 vramBufSize) { for (HSAuint32 i = 0; i < pBuffers.size(); i++) { m_pBuf = pBuffers[i]; if (m_pBuf != NULL) munmap(m_pBuf, vramBufSize); } } void KFDSVMEvictTest::ForkChildProcesses(int nprocesses) { int i; for (i = 0; i < nprocesses - 1; ++i) { pid_t pid = fork(); ASSERT_GE(pid, 0); if (pid == 0) { /* Child process */ /* Cleanup file descriptors copied from parent process * then call SetUp->hsaKmtOpenKFD to create new process */ m_psName = "Test process " + std::to_string(i) + " "; TearDown(); SetUp(); m_ChildPids.clear(); m_IsParent = false; return; } /* Parent process */ m_ChildPids.push_back(pid); } m_psName = "Test process " + std::to_string(i) + " "; } void KFDSVMEvictTest::WaitChildProcesses() { if (m_IsParent) { /* only run by parent process */ int childStatus; int childExitOkNum = 0; int size = m_ChildPids.size(); for (HSAuint32 i = 0; i < size; i++) { pid_t pid = m_ChildPids.front(); waitpid(pid, &childStatus, 0); if (WIFEXITED(childStatus) == 1 && WEXITSTATUS(childStatus) == 0) childExitOkNum++; m_ChildPids.erase(m_ChildPids.begin()); } ASSERT_EQ(childExitOkNum, size); } /* child process or parent process finished successfullly */ m_ChildStatus = HSAKMT_STATUS_SUCCESS; } /* Evict and restore procedure basic test * * Use N_PROCESSES processes to allocate vram buf size larger than total vram size * * ALLOCATE_BUF_SIZE_MB buf allocation size * * number of buf is equal to (vramSizeMB / (vramBufSizeMB * N_PROCESSES) ) + 8 * Total vram all processes allocated: 8GB for 4GB Fiji, and 20GB for 16GB Vega10 * * many times of eviction and restore will happen: * ttm will evict buffers of another process if not enough free vram * process restore will evict buffers of another process * * Sometimes the allocate may fail (maybe that is normal) * ALLOCATE_RETRY_TIMES max retry times to allocate * * This is basic test, no queue so vram are not used by GPU during test * * Todo: * - Synchronization between the processes, so they know for sure when * they are done allocating memory */ TEST_P(KFDSVMEvictTest, BasicTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HSAuint64 vramBufSize = ALLOCATE_BUF_SIZE_MB * 1024 * 1024; if (m_NodeInfo.IsAppAPU(defaultGPUNode)) { LOG() << "Skipping test on AppAPU." << std::endl; return; } HSAuint64 vramSize = GetVramSize(defaultGPUNode); if (!vramSize) { LOG() << "No VRAM found, skipping the test" << std::endl; return; } else { LOG() << "Found VRAM of " << std::dec << (vramSize >> 20) << "MB" << std::endl; } HSAuint32 count = GetBufferCounter(vramSize, vramBufSize); if (count == 0) { LOG() << "Not enough system memory, skipping the test" << std::endl; return; } /* Fork the child processes */ ForkChildProcesses(N_PROCESSES); std::vector pBuffers; AllocBuffers(defaultGPUNode, count, vramBufSize, pBuffers); /* wait for other processes to finish allocation, then free buffer */ sleep(ALLOCATE_RETRY_TIMES); LOG() << m_psName << "free buffer" << std::endl; FreeBuffers(pBuffers, vramBufSize); WaitChildProcesses(); TEST_END } /* Evict and restore queue test * * N_PROCESSES processes read all local buffers in parallel while buffers are evicted and restored * If GPU vm page fault happens, then test shader will stop and failed to write specific value * at dest buffer. Test will report failed. * * Steps: * - fork N_PROCESSES processes, each process does the same below * - allocate local buffers, each buffer size is 64MB * - allocate zero initialized host access address buffer and result buffer * address buffer to pass address of local buffers to shader * result buffer to store shader output result * - submit queue to run ReadMemory shader * - shader start m_DimX wavefronts, each wavefront keep reading one local buffer * - notify shader to quit * - check result buffer with specific value to confirm all wavefronts quit normally */ TEST_P(KFDSVMEvictTest, QueueTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL) if (!SVMAPISupported()) return; HSAuint32 defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; unsigned int count = MAX_WAVEFRONTS; const HsaNodeProperties *pNodeProperties = m_NodeInfo.HsaDefaultGPUNodeProperties(); /* Skip test for chip it doesn't have CWSR, which the test depends on */ if (m_FamilyId < FAMILY_VI || isTonga(pNodeProperties) || m_FamilyId >= FAMILY_NV) { LOG() << std::hex << "Test is skipped for family ID 0x" << m_FamilyId << std::endl; return; } if (m_NodeInfo.IsAppAPU(defaultGPUNode)) { LOG() << "Skipping test on AppAPU." << std::endl; return; } HSAuint32 i; HSAuint64 vramSize = GetVramSize(defaultGPUNode); if (!vramSize) { LOG() << "No VRAM found, skipping the test" << std::endl; return; } else { LOG() << "Found VRAM of " << std::dec << (vramSize >> 20) << "MB." << std::endl; } HSAuint64 vramBufSize = GetBufferSize(vramSize, count); if (vramBufSize == 0) { LOG() << "Not enough system memory, skipping the test" << std::endl; return; } /* assert all buffer address can be stored within one page * because only one page host memory srcBuf is allocated */ ASSERT_LE(count, PAGE_SIZE/sizeof(unsigned int *)); /* Fork the child processes */ ForkChildProcesses(N_PROCESSES); HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); HsaMemoryBuffer addrBuffer(PAGE_SIZE, defaultGPUNode); HsaMemoryBuffer resultBuffer(PAGE_SIZE, defaultGPUNode); std::vector pBuffers; AllocBuffers(defaultGPUNode, count, vramBufSize, pBuffers); unsigned int wavefront_num = pBuffers.size(); LOG() << m_psName << "wavefront number " << wavefront_num << std::endl; void **localBufAddr = addrBuffer.As(); unsigned int *result = resultBuffer.As(); for (i = 0; i < wavefront_num; i++) *(localBufAddr + i) = pBuffers[i]; for (i = 0; i < wavefront_num; i++) *(result + i) = vramBufSize; ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(ReadMemoryIsa, isaBuffer.As())); PM4Queue pm4Queue; ASSERT_SUCCESS(pm4Queue.Create(defaultGPUNode)); Dispatch dispatch0(isaBuffer); dispatch0.SetArgs(localBufAddr, result); dispatch0.SetDim(wavefront_num, 1, 1); /* submit the packet and start shader */ dispatch0.Submit(pm4Queue); /* doing evict/restore queue test for 5 seconds while queue is running */ sleep(5); /* LOG() << m_psName << "notify shader to quit" << std::endl; */ /* fill address buffer so shader quits */ addrBuffer.Fill(0x5678); /* wait for shader to finish or timeout if shade has vm page fault */ dispatch0.SyncWithStatus(120000); ASSERT_SUCCESS(pm4Queue.Destroy()); /* LOG() << m_psName << "free buffer" << std::endl; */ /* cleanup */ FreeBuffers(pBuffers, vramBufSize); /* check if all wavefronts finish successfully */ for (i = 0; i < wavefront_num; i++) ASSERT_EQ(0x5678, *(result + i)); WaitChildProcesses(); TEST_END } INSTANTIATE_TEST_CASE_P(, KFDSVMEvictTest,::testing::Values(0, 1)); ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDSVMEvictTest.hpp000066400000000000000000000052411446477712600251740ustar00rootroot00000000000000/* * Copyright (C) 2020 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_SVM_EVICT_TEST__H__ #define __KFD_SVM_EVICT_TEST__H__ #include #include #include "KFDLocalMemoryTest.hpp" #include "KFDBaseComponentTest.hpp" // @class KFDEvictTest // Test eviction and restore procedure using two processes class KFDSVMEvictTest : public KFDLocalMemoryTest, public ::testing::WithParamInterface { public: KFDSVMEvictTest(void): m_ChildStatus(HSAKMT_STATUS_ERROR), m_IsParent(true) {} ~KFDSVMEvictTest(void) { if (!m_IsParent) { /* child process has to exit * otherwise gtest will continue other tests */ exit(m_ChildStatus); } try { WaitChildProcesses(); } catch (...) {} } protected: virtual void SetUp(); virtual void TearDown(); protected: std::string CreateShader(); void AllocBuffers(HSAuint32 defaultGPUNode, HSAuint32 count, HSAuint64 vramBufSize, std::vector &pBuffers); void FreeBuffers(std::vector &pBuffers, HSAuint64 vramBufSize); void ForkChildProcesses(int nprocesses); void WaitChildProcesses(); HSAint32 GetBufferCounter(HSAuint64 vramSize, HSAuint64 vramBufSize); HSAint64 GetBufferSize(HSAuint64 vramSize, HSAuint32 count); protected: // members std::string m_psName; std::vector m_ChildPids; HSA_SVM_FLAGS m_Flags; void* m_pBuf; HSAKMT_STATUS m_ChildStatus; bool m_IsParent; }; #endif // __KFD_SVM_EVICT_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDSVMRangeTest.cpp000066400000000000000000001570661446477712600251660ustar00rootroot00000000000000/* * Copyright (C) 2020 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDSVMRangeTest.hpp" #include #include #include #include "PM4Queue.hpp" #include "PM4Packet.hpp" #include "SDMAPacket.hpp" #include "SDMAQueue.hpp" #include "Dispatch.hpp" void KFDSVMRangeTest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); SVMSetXNACKMode(GetParam()); ROUTINE_END } void KFDSVMRangeTest::TearDown() { ROUTINE_START SVMRestoreXNACKMode(); KFDBaseComponentTest::TearDown(); ROUTINE_END } TEST_P(KFDSVMRangeTest, BasicSystemMemTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; PM4Queue queue; HSAuint64 AlternateVAGPU; unsigned int BufferSize = PAGE_SIZE; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (!GetVramSize(defaultGPUNode)) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode); HsaSVMRange srcSysBuffer(BufferSize, defaultGPUNode); HsaSVMRange destSysBuffer(BufferSize, defaultGPUNode); srcSysBuffer.Fill(0x01010101); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); queue.SetSkipWaitConsump(0); Dispatch dispatch(isaBuffer); dispatch.SetArgs(srcSysBuffer.As(), destSysBuffer.As()); dispatch.Submit(queue); dispatch.Sync(g_TestTimeOut); EXPECT_SUCCESS(queue.Destroy()); EXPECT_EQ(destSysBuffer.As()[0], 0x01010101); TEST_END } TEST_P(KFDSVMRangeTest, SetGetAttributesTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL) if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } int i; unsigned int BufSize = PAGE_SIZE; HsaSVMRange *sysBuffer = new HsaSVMRange(BufSize); HSAuint32 nAttributes = 5; HSA_SVM_ATTRIBUTE outputAttributes[nAttributes]; HSA_SVM_ATTRIBUTE inputAttributes[] = { {HSA_SVM_ATTR_PREFETCH_LOC, (HSAuint32)defaultGPUNode}, {HSA_SVM_ATTR_PREFERRED_LOC, (HSAuint32)defaultGPUNode}, {HSA_SVM_ATTR_SET_FLAGS, HSA_SVM_FLAG_HOST_ACCESS | HSA_SVM_FLAG_GPU_EXEC | HSA_SVM_FLAG_COHERENT}, {HSA_SVM_ATTR_GRANULARITY, 0xFF}, {HSA_SVM_ATTR_ACCESS, (HSAuint32)defaultGPUNode}, }; HSAuint32 expectedDefaultResults[] = { INVALID_NODEID, INVALID_NODEID, HSA_SVM_FLAG_HOST_ACCESS | HSA_SVM_FLAG_COHERENT, 9, 0, }; HSAint32 enable = -1; EXPECT_SUCCESS(hsaKmtGetXNACKMode(&enable)); expectedDefaultResults[4] = (enable) ? HSA_SVM_ATTR_ACCESS : HSA_SVM_ATTR_NO_ACCESS; char *pBuf = sysBuffer->As(); LOG() << "Get default atrributes" << std::endl; memcpy(outputAttributes, inputAttributes, nAttributes * sizeof(HSA_SVM_ATTRIBUTE)); EXPECT_SUCCESS(hsaKmtSVMGetAttr(pBuf, BufSize, nAttributes, outputAttributes)); for (i = 0; i < nAttributes; i++) { if (outputAttributes[i].type == HSA_SVM_ATTR_ACCESS || outputAttributes[i].type == HSA_SVM_ATTR_ACCESS_IN_PLACE || outputAttributes[i].type == HSA_SVM_ATTR_NO_ACCESS) EXPECT_EQ(outputAttributes[i].type, expectedDefaultResults[i]); else EXPECT_EQ(outputAttributes[i].value, expectedDefaultResults[i]); } LOG() << "Setting/Getting atrributes" << std::endl; memcpy(outputAttributes, inputAttributes, nAttributes * sizeof(HSA_SVM_ATTRIBUTE)); EXPECT_SUCCESS(hsaKmtSVMSetAttr(pBuf, BufSize, nAttributes, inputAttributes)); EXPECT_SUCCESS(hsaKmtSVMGetAttr(pBuf, BufSize, nAttributes, outputAttributes)); for (i = 0; i < nAttributes; i++) { if (outputAttributes[i].type == HSA_SVM_ATTR_ACCESS || outputAttributes[i].type == HSA_SVM_ATTR_ACCESS_IN_PLACE || outputAttributes[i].type == HSA_SVM_ATTR_NO_ACCESS) EXPECT_EQ(inputAttributes[i].type, outputAttributes[i].type); else EXPECT_EQ(inputAttributes[i].value, outputAttributes[i].value); } delete sysBuffer; TEST_END } TEST_P(KFDSVMRangeTest, XNACKModeTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; HSAuint32 i, j; HSAint32 r; PM4Queue queue; HSAint32 enable = 0; const std::vector gpuNodes = m_NodeInfo.GetNodesWithGPU(); EXPECT_SUCCESS(hsaKmtGetXNACKMode(&enable)); for (i = 0; i < 2; i++) { enable = !enable; r = hsaKmtSetXNACKMode(enable); if (r == HSAKMT_STATUS_SUCCESS) { LOG() << "XNACK mode: " << std::boolalpha << enable << " supported" << std::endl; for (j = 0; j < gpuNodes.size(); j++) { LOG() << "Creating queue and try to set xnack mode on node: " << gpuNodes.at(j) << std::endl; ASSERT_SUCCESS(queue.Create(gpuNodes.at(j))); EXPECT_EQ(HSAKMT_STATUS_ERROR, hsaKmtSetXNACKMode(enable)); EXPECT_SUCCESS(queue.Destroy()); } } else if (r == HSAKMT_STATUS_NOT_SUPPORTED) { LOG() << "XNACK mode: " << std::boolalpha << enable << " NOT supported" << std::endl; } } TEST_END } TEST_P(KFDSVMRangeTest, InvalidRangeTest) { TEST_START(TESTPROFILE_RUNALL) if (!SVMAPISupported()) return; HSAuint32 Flags;; HSAKMT_STATUS ret; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; Flags = HSA_SVM_FLAG_HOST_ACCESS | HSA_SVM_FLAG_COHERENT; ret = RegisterSVMRange(defaultGPUNode, reinterpret_cast(0x10000), 0x1000, 0, Flags); EXPECT_NE(ret, HSAKMT_STATUS_SUCCESS); TEST_END } void KFDSVMRangeTest::SplitRangeTest(int defaultGPUNode, int prefetch_location) { unsigned int BufSize = 16 * PAGE_SIZE; if (!SVMAPISupported()) return; HsaSVMRange *sysBuffer; HsaSVMRange *sysBuffer2; HsaSVMRange *sysBuffer3; HsaSVMRange *sysBuffer4; void *pBuf; // case 1 pBuf = mmap(0, BufSize, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); sysBuffer = new HsaSVMRange(pBuf, BufSize, defaultGPUNode, prefetch_location); sysBuffer2 = new HsaSVMRange(reinterpret_cast(pBuf) + 8192, PAGE_SIZE, defaultGPUNode, prefetch_location); delete sysBuffer2; delete sysBuffer; munmap(pBuf, BufSize); // case 2.1 pBuf = mmap(0, BufSize, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); sysBuffer = new HsaSVMRange(pBuf, BufSize, defaultGPUNode, prefetch_location); sysBuffer2 = new HsaSVMRange(reinterpret_cast(pBuf) + 4096, BufSize - 4096, defaultGPUNode, prefetch_location); delete sysBuffer2; delete sysBuffer; munmap(pBuf, BufSize); // case 2.2 pBuf = mmap(0, BufSize + 8192, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); sysBuffer = new HsaSVMRange(pBuf, BufSize, defaultGPUNode, prefetch_location); sysBuffer2 = new HsaSVMRange(reinterpret_cast(pBuf) + 8192, BufSize, defaultGPUNode, prefetch_location); delete sysBuffer2; delete sysBuffer; munmap(pBuf, BufSize + 8192); // case 3 pBuf = mmap(0, BufSize, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); sysBuffer = new HsaSVMRange(pBuf, BufSize, defaultGPUNode, prefetch_location); sysBuffer2 = new HsaSVMRange(reinterpret_cast(pBuf), BufSize - 8192, defaultGPUNode, prefetch_location); delete sysBuffer2; delete sysBuffer; munmap(pBuf, BufSize); // case 4.1 pBuf = mmap(0, BufSize, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); sysBuffer = new HsaSVMRange(pBuf, BufSize, defaultGPUNode, prefetch_location); sysBuffer2 = new HsaSVMRange(pBuf, BufSize, defaultGPUNode, prefetch_location); delete sysBuffer2; delete sysBuffer; munmap(pBuf, BufSize); // case 4.2 pBuf = mmap(0, BufSize + 8192, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); sysBuffer = new HsaSVMRange(pBuf, BufSize, defaultGPUNode, prefetch_location); sysBuffer2 = new HsaSVMRange(pBuf, BufSize + 8192, defaultGPUNode, prefetch_location); delete sysBuffer2; delete sysBuffer; munmap(pBuf, BufSize + 8192); // case 5 pBuf = mmap(0, BufSize + 65536, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); sysBuffer = new HsaSVMRange(reinterpret_cast(pBuf) + 8192, 8192, defaultGPUNode, prefetch_location); sysBuffer2 = new HsaSVMRange(reinterpret_cast(pBuf) + 32768, 8192, defaultGPUNode, prefetch_location); sysBuffer3 = new HsaSVMRange(pBuf, BufSize + 65536, defaultGPUNode, prefetch_location); delete sysBuffer2; delete sysBuffer3; delete sysBuffer; munmap(pBuf, BufSize + 65536); // case 6, unregister after free pBuf = mmap(0, BufSize, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); sysBuffer = new HsaSVMRange(reinterpret_cast(pBuf) + 8192, 8192, defaultGPUNode, prefetch_location); munmap(pBuf, BufSize); delete sysBuffer; } TEST_P(KFDSVMRangeTest, SplitSystemRangeTest) { const HsaNodeProperties *pNodeProperties = m_NodeInfo.HsaDefaultGPUNodeProperties(); TEST_START(TESTPROFILE_RUNALL) if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } SplitRangeTest(defaultGPUNode, 0); TEST_END } TEST_P(KFDSVMRangeTest, EvictSystemRangeTest) { const HsaNodeProperties *pNodeProperties = m_NodeInfo.HsaDefaultGPUNodeProperties(); TEST_START(TESTPROFILE_RUNALL) if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } HSAuint32 stackData[2 * PAGE_SIZE] = {0}; char *pBuf = reinterpret_cast(((uint64_t)stackData + PAGE_SIZE) & ~(PAGE_SIZE - 1)); HSAuint32 *globalData = reinterpret_cast(pBuf); const unsigned dstOffset = ((uint64_t)pBuf + 2 * PAGE_SIZE - (uint64_t)stackData) / 4; const unsigned sdmaOffset = dstOffset + PAGE_SIZE; *globalData = 0xdeadbeef; HsaSVMRange srcBuffer((globalData), PAGE_SIZE, defaultGPUNode); HsaSVMRange dstBuffer(&stackData[dstOffset], PAGE_SIZE, defaultGPUNode); HsaSVMRange sdmaBuffer(&stackData[sdmaOffset], PAGE_SIZE, defaultGPUNode); /* Create PM4 and SDMA queues before fork+COW to test queue * eviction and restore */ PM4Queue pm4Queue; SDMAQueue sdmaQueue; ASSERT_SUCCESS(pm4Queue.Create(defaultGPUNode)); ASSERT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode, true/*zero*/, false/*local*/, true/*exec*/); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); Dispatch dispatch0(isaBuffer); dispatch0.SetArgs(srcBuffer.As(), dstBuffer.As()); dispatch0.Submit(pm4Queue); dispatch0.Sync(g_TestTimeOut); sdmaQueue.PlaceAndSubmitPacket(SDMAWriteDataPacket(sdmaQueue.GetFamilyId(), sdmaBuffer.As(), 0x12345678)); sdmaQueue.Wait4PacketConsumption(); EXPECT_TRUE(WaitOnValue(&stackData[sdmaOffset], 0x12345678)); /* Fork a child process to mark pages as COW */ pid_t pid = fork(); ASSERT_GE(pid, 0); if (pid == 0) { /* Child process waits for a SIGTERM from the parent. It can't * make any write access to the stack because we want the * parent to make the first write access and get a new copy. A * busy loop is the safest way to do that, since any function * call (e.g. sleep) would write to the stack. */ while (1) {} WARN() << "Shouldn't get here!" << std::endl; exit(0); } /* Parent process writes to COW page(s) and gets a new copy. MMU * notifier needs to update the GPU mapping(s) for the test to * pass. */ *globalData = 0xD00BED00; stackData[dstOffset] = 0xdeadbeef; stackData[sdmaOffset] = 0xdeadbeef; /* Terminate the child process before a possible test failure that * would leave it spinning in the background indefinitely. */ int status; EXPECT_EQ(0, kill(pid, SIGTERM)); EXPECT_EQ(pid, waitpid(pid, &status, 0)); EXPECT_NE(0, WIFSIGNALED(status)); EXPECT_EQ(SIGTERM, WTERMSIG(status)); /* Now check that the GPU is accessing the correct page */ Dispatch dispatch1(isaBuffer); dispatch1.SetArgs(srcBuffer.As(), dstBuffer.As()); dispatch1.Submit(pm4Queue); dispatch1.Sync(g_TestTimeOut); sdmaQueue.PlaceAndSubmitPacket(SDMAWriteDataPacket(sdmaQueue.GetFamilyId(), sdmaBuffer.As(), 0xD0BED0BE)); sdmaQueue.Wait4PacketConsumption(); EXPECT_SUCCESS(pm4Queue.Destroy()); EXPECT_SUCCESS(sdmaQueue.Destroy()); EXPECT_EQ(0xD00BED00, *globalData); EXPECT_EQ(0xD00BED00, stackData[dstOffset]); EXPECT_EQ(0xD0BED0BE, stackData[sdmaOffset]); TEST_END } TEST_P(KFDSVMRangeTest, PartialUnmapSysMemTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; unsigned int BufSize = 16 * PAGE_SIZE; void *pBuf; PM4Queue queue; HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode); HsaSVMRange *sysBuffer; HsaSVMRange destSysBuffer(BufSize, defaultGPUNode); pBuf = mmap(0, BufSize, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); sysBuffer = new HsaSVMRange(pBuf, BufSize, defaultGPUNode, 0); sysBuffer->Fill(0x01010101); char *pBuf2 = reinterpret_cast(pBuf) + 8192; unsigned int Buf2Size = 4 * PAGE_SIZE; char *pBuf3 = pBuf2 + Buf2Size; munmap(pBuf2, Buf2Size); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); Dispatch dispatch(isaBuffer); Dispatch dispatch2(isaBuffer); dispatch.SetArgs(pBuf3, destSysBuffer.As()); dispatch.Submit(queue); dispatch.Sync(g_TestTimeOut); EXPECT_EQ(destSysBuffer.As()[0], 0x01010101); dispatch2.SetArgs(pBuf, destSysBuffer.As()); dispatch2.Submit(queue); dispatch2.Sync(g_TestTimeOut); EXPECT_EQ(destSysBuffer.As()[0], 0x01010101); EXPECT_SUCCESS(queue.Destroy()); munmap(pBuf, BufSize); TEST_END } TEST_P(KFDSVMRangeTest, BasicVramTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; PM4Queue queue; HSAuint64 AlternateVAGPU; unsigned int BufferSize = PAGE_SIZE; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (!GetVramSize(defaultGPUNode)) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode); HsaSVMRange srcSysBuffer(BufferSize, defaultGPUNode); HsaSVMRange locBuffer(BufferSize, defaultGPUNode, defaultGPUNode); HsaSVMRange destSysBuffer(BufferSize, defaultGPUNode); srcSysBuffer.Fill(0x01010101); ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); queue.SetSkipWaitConsump(0); Dispatch dispatch(isaBuffer); Dispatch dispatch2(isaBuffer); dispatch.SetArgs(srcSysBuffer.As(), locBuffer.As()); dispatch.Submit(queue); dispatch.Sync(g_TestTimeOut); dispatch2.SetArgs(locBuffer.As(), destSysBuffer.As()); dispatch2.Submit(queue); dispatch2.Sync(g_TestTimeOut); EXPECT_SUCCESS(queue.Destroy()); EXPECT_EQ(destSysBuffer.As()[0], 0x01010101); TEST_END } TEST_P(KFDSVMRangeTest, SplitVramRangeTest) { TEST_START(TESTPROFILE_RUNALL) if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } SplitRangeTest(defaultGPUNode, defaultGPUNode); TEST_END } TEST_P(KFDSVMRangeTest, PrefetchTest) { TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; unsigned int BufSize = 16 << 10; HsaSVMRange *sysBuffer; uint32_t node_id; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; sysBuffer = new HsaSVMRange(BufSize, defaultGPUNode); char *pBuf = sysBuffer->As(); /* Using invalid svm range to get prefetch node should return failed */ delete sysBuffer; EXPECT_SUCCESS(!SVMRangeGetPrefetchNode(pBuf, BufSize, &node_id)); sysBuffer = new HsaSVMRange(BufSize, defaultGPUNode); pBuf = sysBuffer->As(); char *pLocBuf = pBuf + BufSize / 2; EXPECT_SUCCESS(SVMRangeGetPrefetchNode(pBuf, BufSize, &node_id)); EXPECT_EQ(node_id, 0); EXPECT_SUCCESS(SVMRangePrefetchToNode(pLocBuf, BufSize / 2, defaultGPUNode)); EXPECT_SUCCESS(SVMRangeGetPrefetchNode(pLocBuf, BufSize / 2, &node_id)); EXPECT_EQ(node_id, defaultGPUNode); EXPECT_SUCCESS(SVMRangeGetPrefetchNode(pBuf, BufSize, &node_id)); EXPECT_EQ(node_id, 0xffffffff); delete sysBuffer; TEST_END } TEST_P(KFDSVMRangeTest, MigrateTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } if (!GetVramSize(defaultGPUNode)) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } HSAuint32 migrateRepeat = 8; unsigned int BufferSize = 16 << 20; HsaSVMRange DataBuffer(BufferSize, defaultGPUNode); HSAuint32 *pData = DataBuffer.As(); HsaSVMRange SysBuffer(BufferSize, defaultGPUNode); HSAuint32 *pBuf = SysBuffer.As(); EXPECT_SUCCESS(SVMRangePrefetchToNode(pBuf, BufferSize, 0)); HsaSVMRange SysBuffer2(BufferSize, defaultGPUNode); HSAuint32 *pBuf2 = SysBuffer2.As(); EXPECT_SUCCESS(SVMRangePrefetchToNode(pBuf2, BufferSize, 0)); SDMAQueue sdmaQueue; ASSERT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); for (HSAuint32 i = 0; i < BufferSize / 4; i++) pData[i] = i; while (migrateRepeat--) { /* Migrate from ram to vram */ EXPECT_SUCCESS(SVMRangePrefetchToNode(pBuf, BufferSize, defaultGPUNode)); EXPECT_SUCCESS(SVMRangePrefetchToNode(pBuf2, BufferSize, defaultGPUNode)); /* Update content in migrated buffer in vram */ sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), pBuf, pData, BufferSize)); sdmaQueue.Wait4PacketConsumption(); sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), pBuf2, pData, BufferSize)); sdmaQueue.Wait4PacketConsumption(); /* Migrate from vram to ram * CPU access the buffer migrated to vram have page fault * page fault trigger migration from vram back to ram * so SysBuffer should have same value as in vram */ for (HSAuint32 i = 0; i < BufferSize / 4; i++) { ASSERT_EQ(i, pBuf[i]); ASSERT_EQ(i, pBuf2[i]); } } /* If xnack off, after migrating back to ram, GPU mapping should be updated to ram * test if shade can read from ram * If xnack on, GPU mapping should be cleared, test if GPU vm fault can update * page table and shade can read from ram. */ sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), pBuf, pData, BufferSize)); sdmaQueue.Wait4PacketConsumption(); for (HSAuint32 i = 0; i < BufferSize / 4; i++) ASSERT_EQ(i, pBuf[i]); TEST_END } /* * Test if GPU mapping to system memory is correct after range on VRAM split and migrate back * to system memory. * * Steps, it is same for XNACK on or off * 1. alloc 256MB range on system memory, set ACCESS_IN_PLACE by GPU * 2. Prefetcg to migrate range to GPU VRAM * 3. Use CPU to fill the range, range is migrated back to system memory, and split by granularity, * GPU mapping update to system memory * 4. Use GPU sdma to fill the range in system memory * 5. Check if data is correct in system memory */ TEST_P(KFDSVMRangeTest, MigrateAccessInPlaceTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } if (!GetVramSize(defaultGPUNode)) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } unsigned int BufferSize = MIN(256ULL << 20, GetVramSize(defaultGPUNode) / 2); SDMAQueue sdmaQueue; ASSERT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); HsaSVMRange DataBuffer(BufferSize, defaultGPUNode); HSAuint32 *pData = DataBuffer.As(); EXPECT_SUCCESS(SVMRangeMapInPlaceToNode(pData, BufferSize, defaultGPUNode)); EXPECT_SUCCESS(SVMRangePrefetchToNode(pData, BufferSize, defaultGPUNode)); for (HSAuint32 i = 0; i < BufferSize / 4; i += 1024) pData[i] = i; /* GPU/SDMA update content in buffer migrated back to system memory */ sdmaQueue.PlaceAndSubmitPacket(SDMAFillDataPacket(sdmaQueue.GetFamilyId(), pData, 0x55AAAA55, BufferSize)); sdmaQueue.Wait4PacketConsumption(); for (HSAuint32 i = 0; i < BufferSize / 4; i += 1024) ASSERT_EQ(0x55AAAA55, pData[i]); ASSERT_SUCCESS(sdmaQueue.Destroy()); TEST_END } /* * The test changes migration granularity, then trigger CPU page fault to migrate * the svm range from vram to ram. * Check the dmesg driver output to confirm the number of CPU page fault is correct * based on granularity. * * For example, this is BufferPages = 5, while granularity change from 2 to 0 * [ 292.623498] amdgpu:svm_migrate_to_ram:744: CPU page fault address 0x7f22597ee000 * [ 292.623727] amdgpu:svm_migrate_to_ram:744: CPU page fault address 0x7f22597f0000 * [ 292.724414] amdgpu:svm_migrate_to_ram:744: CPU page fault address 0x7f22597ee000 * [ 292.724824] amdgpu:svm_migrate_to_ram:744: CPU page fault address 0x7f22597f0000 * [ 292.725094] amdgpu:svm_migrate_to_ram:744: CPU page fault address 0x7f22597f2000 * [ 292.728186] amdgpu:svm_migrate_to_ram:744: CPU page fault address 0x7f22597ee000 * [ 292.729171] amdgpu:svm_migrate_to_ram:744: CPU page fault address 0x7f22597ef000 * [ 292.729576] amdgpu:svm_migrate_to_ram:744: CPU page fault address 0x7f22597f0000 * [ 292.730010] amdgpu:svm_migrate_to_ram:744: CPU page fault address 0x7f22597f1000 * [ 292.730931] amdgpu:svm_migrate_to_ram:744: CPU page fault address 0x7f22597f2000 */ TEST_P(KFDSVMRangeTest, MigrateGranularityTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } if (!GetVramSize(defaultGPUNode)) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } HSAuint64 BufferPages = 16384; HSAuint64 BufferSize = BufferPages * PAGE_SIZE; HsaSVMRange SysBuffer(BufferSize, defaultGPUNode); HSAint32 *pBuf = SysBuffer.As(); HsaSVMRange SysBuffer2(BufferSize, defaultGPUNode); HSAint32 *pBuf2 = SysBuffer2.As(); HSAint32 Granularity; SDMAQueue sdmaQueue; ASSERT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); for (Granularity = 0; (1ULL << Granularity) <= BufferPages; Granularity++); for (HSAuint32 i = 0; i < BufferPages; i++) pBuf2[i * PAGE_SIZE / 4] = i; while (Granularity--) { /* Prefetch the entire range to vram */ EXPECT_SUCCESS(SVMRangePrefetchToNode(pBuf, BufferSize, defaultGPUNode)); EXPECT_SUCCESS(SVMRangSetGranularity(pBuf, BufferSize, Granularity)); /* Change Buffer content in vram, then migrate it back to ram */ sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), pBuf, pBuf2, BufferSize)); sdmaQueue.Wait4PacketConsumption(); /* Migrate from vram to ram */ for (HSAuint32 i = 0; i < BufferPages; i++) ASSERT_EQ(i, pBuf[i * PAGE_SIZE / 4]); } TEST_END } TEST_P(KFDSVMRangeTest, MigrateLargeBufTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; PM4Queue queue; HSAuint64 AlternateVAGPU; unsigned long BufferSize = 1L << 30; unsigned long maxSDMASize = 128L << 20; /* IB size is 4K */ unsigned long Size, i; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HSAuint64 vramSize; vramSize = GetVramSize(defaultGPUNode); if (!vramSize) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } BufferSize = MIN(BufferSize, vramSize * 3 / 4); HsaSVMRange SysBuffer(BufferSize, defaultGPUNode); SysBuffer.Fill(0x1); HsaSVMRange SysBuffer2(BufferSize, defaultGPUNode); SysBuffer2.Fill(0x2); /* Migrate from ram to vram * using same address to register to GPU to trigger migration * so LocalBuffer will have same value as SysBuffer */ HsaSVMRange LocalBuffer(SysBuffer.As(), BufferSize, defaultGPUNode, defaultGPUNode); SDMAQueue sdmaQueue; ASSERT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); for (i = 0; i < BufferSize; i += Size) { Size = (BufferSize - i) > maxSDMASize ? maxSDMASize : (BufferSize - i); sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), SysBuffer2.As() + i, LocalBuffer.As() + i, Size)); sdmaQueue.Wait4PacketConsumption(); } /* Check content in migrated buffer in vram */ for (i = 0; i < BufferSize / 4; i += 1024) ASSERT_EQ(0x1, SysBuffer2.As()[i]); /* Change LocalBuffer content in vram, then migrate it back to ram */ SysBuffer2.Fill(0x3); for (i = 0; i < BufferSize; i += Size) { Size = (BufferSize - i) > maxSDMASize ? maxSDMASize : (BufferSize - i); sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), LocalBuffer.As() + i, SysBuffer2.As() + i, Size)); sdmaQueue.Wait4PacketConsumption(); } /* Migrate from vram to ram * CPU access the buffer migrated to vram have page fault * page fault trigger migration from vram back to ram * so SysBuffer should have same value as in LocalBuffer */ EXPECT_SUCCESS(SVMRangSetGranularity(SysBuffer.As(), BufferSize, 30)); for (i = 0; i < BufferSize / 4; i += 1024) ASSERT_EQ(0x3, SysBuffer.As()[i]); /* After migrating back to ram, GPU mapping should be updated to ram * test if shade can read from ram */ SysBuffer.Fill(0x4); for (i = 0; i < BufferSize; i += Size) { Size = (BufferSize - i) > maxSDMASize ? maxSDMASize : (BufferSize - i); sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), SysBuffer2.As() + i, LocalBuffer.As() + i, Size)); sdmaQueue.Wait4PacketConsumption(); } for (i = 0; i < BufferSize / 4; i += 1024) ASSERT_EQ(0x4, SysBuffer2.As()[i]); TEST_END } TEST_P(KFDSVMRangeTest, MigratePolicyTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } if (!GetVramSize(defaultGPUNode)) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } unsigned long BufferSize = 1UL << 20; HsaSVMRange DataBuffer(BufferSize, defaultGPUNode); HSAuint64 *pData = DataBuffer.As(); HsaSVMRange SysBuffer(BufferSize, defaultGPUNode); HSAuint64 *pBuf = SysBuffer.As(); SDMAQueue sdmaQueue; ASSERT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); for (HSAuint64 i = 0; i < BufferSize / 8; i++) pData[i] = i; /* Prefetch to migrate from ram to vram */ EXPECT_SUCCESS(SVMRangePrefetchToNode(pBuf, BufferSize, defaultGPUNode)); /* Update content in migrated buffer in vram */ sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), pBuf, pData, BufferSize)); sdmaQueue.Wait4PacketConsumption(NULL, HSA_EVENTTIMEOUT_INFINITE); /* Migrate from vram to ram * CPU access the buffer migrated to vram have page fault * page fault trigger migration from vram back to ram * so SysBuffer should have same value as in vram */ for (HSAuint64 i = 0; i < BufferSize / 8; i++) { ASSERT_EQ(i, pBuf[i]); /* Update buf */ pBuf[i] = i + 1; } /* Migrate from ram to vram if xnack on * If xnack off, after migrating back to ram, GPU mapping should be updated to ram * test if shade can read from ram * If xnack on, GPU mapping should be cleared, test if GPU vm fault can update * page table and shade can read from ram. */ //#define USE_PM4_QUEUE_TRIGGER_VM_FAULT #ifdef USE_PM4_QUEUE_TRIGGER_VM_FAULT HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode); PM4Queue queue; ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); for (HSAuint64 i = 0; i < BufferSize / 8; i += 512) { Dispatch dispatch(isaBuffer); dispatch.SetArgs(pBuf + i, pData + i); dispatch.Submit(queue); dispatch.Sync(HSA_EVENTTIMEOUT_INFINITE); } #else sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), pData, pBuf, BufferSize)); sdmaQueue.Wait4PacketConsumption(NULL, HSA_EVENTTIMEOUT_INFINITE); #endif for (HSAuint64 i = 0; i < BufferSize / 8; i += 512) ASSERT_EQ(i + 1, pData[i]); ASSERT_SUCCESS(sdmaQueue.Destroy()); TEST_END } /* Multiple GPU migration test * * Steps: * 1. Prefetch pBuf, pData to all GPUs, to test migration from GPU to GPU * 2. Use sdma queue on all GPUs, to copy data from pBuf to pData * 3. Check pData data * * Notes: * With xnack on, step 2 will have retry fault on pBuf, to migrate from GPU to GPU, * retry fault on pData, to migrate from CPU to GPU * * With xnack off, pBuf and pData should prefetch to CPU to ensure multiple GPU access * * step3 migrate pData from GPU to CPU * * Test will skip if only one GPU found */ TEST_P(KFDSVMRangeTest, MultiGPUMigrationTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } const std::vector gpuNodesAll = m_NodeInfo.GetNodesWithGPU(); std::vector gpuNodes; for (auto node : gpuNodesAll) { const HsaNodeProperties *pNodeProperties; pNodeProperties = m_NodeInfo.GetNodeProperties(node); if (pNodeProperties->Capability.ui32.SVMAPISupported) gpuNodes.push_back(node); } if (gpuNodes.size() < 2) { LOG() << "Skipping test: at least two SVM supported GPUs needed." << std::endl; return; } unsigned long BufferSize = 1UL << 20; HsaSVMRange SysBuffer(BufferSize, defaultGPUNode); HSAuint64 *pBuf = SysBuffer.As(); HsaSVMRange DataBuffer(BufferSize, defaultGPUNode); HSAuint64 *pData = DataBuffer.As(); SDMAQueue sdmaQueue; for (HSAuint64 i = 0; i < BufferSize / 8; i++) pBuf[i] = i; for (auto node : gpuNodes) { EXPECT_SUCCESS(SVMRangeMapToNode(pBuf, BufferSize, node)); EXPECT_SUCCESS(SVMRangePrefetchToNode(pBuf, BufferSize, node)); EXPECT_SUCCESS(SVMRangeMapToNode(pData, BufferSize, node)); EXPECT_SUCCESS(SVMRangePrefetchToNode(pData, BufferSize, node)); } for (auto node : gpuNodes) { ASSERT_SUCCESS(sdmaQueue.Create(node)); sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), pData, pBuf, BufferSize)); sdmaQueue.Wait4PacketConsumption(); for (HSAuint64 i = 0; i < BufferSize / 8; i += 512) ASSERT_EQ(i, pData[i]); EXPECT_SUCCESS(sdmaQueue.Destroy()); } TEST_END } /* Multiple GPU access in place test * * Steps: * 1. Prefetch pBuf, pData to all GPUs, with ACCESS_IN_PLACE on GPUs * 2. Use sdma queue on all GPUs, to copy data from pBuf to pData * 3. Prefetch pData to CPU, check pData data * * Notes: * With xnack on, step 2 will have retry fault on pBuf, to migrate from GPU to GPU. * If multiple GPU on xGMI same hive, there should not have retry fault on pBuf * because mapping should update to another GPU vram through xGMI * * With xnack off, pBuf and pData should prefetch to CPU to ensure multiple GPU access * * step3 migrate pData from GPU to CPU, should not have retry fault on GPUs. * * Test will skip if only one GPU found */ TEST_P(KFDSVMRangeTest, MultiGPUAccessInPlaceTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } const std::vector gpuNodesAll = m_NodeInfo.GetNodesWithGPU(); std::vector gpuNodes; for (auto node : gpuNodesAll) { const HsaNodeProperties *pNodeProperties; pNodeProperties = m_NodeInfo.GetNodeProperties(node); if (pNodeProperties->Capability.ui32.SVMAPISupported) gpuNodes.push_back(node); } if (gpuNodes.size() < 2) { LOG() << "Skipping test: at least two SVM supported GPUs needed." << std::endl; return; } unsigned long BufferSize = 1UL << 20; HsaSVMRange SysBuffer(BufferSize, defaultGPUNode); HSAuint64 *pBuf = SysBuffer.As(); HsaSVMRange DataBuffer(BufferSize, defaultGPUNode); HSAuint64 *pData = DataBuffer.As(); SDMAQueue sdmaQueue; for (HSAuint64 i = 0; i < BufferSize / 8; i++) pBuf[i] = i; for (auto node : gpuNodes) { EXPECT_SUCCESS(SVMRangeMapInPlaceToNode(pBuf, BufferSize, node)); EXPECT_SUCCESS(SVMRangePrefetchToNode(pBuf, BufferSize, node)); EXPECT_SUCCESS(SVMRangeMapInPlaceToNode(pData, BufferSize, node)); EXPECT_SUCCESS(SVMRangePrefetchToNode(pData, BufferSize, node)); } for (auto node : gpuNodes) { ASSERT_SUCCESS(sdmaQueue.Create(node)); sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), pData, pBuf, BufferSize)); sdmaQueue.Wait4PacketConsumption(); for (HSAuint64 i = 0; i < BufferSize / 8; i += 512) ASSERT_EQ(i, pData[i]); EXPECT_SUCCESS(sdmaQueue.Destroy()); } TEST_END } /* Multiple thread migration test * * 2 threads do migration at same time to test range migration race conditon handle. * * Steps: * 1. register 128MB range on system memory, don't map to GPU, 128MB is max size to put in * sdma queue 4KB IB buffer. * 2. one thread prefetch range to GPU, another thread use sdma queue to access range at same * time to generate retry vm fault to migrate range to GPU * 3. one thread prefetch range to CPU, another thread read range to generate CPU page fault * to migrate range to CPU at same time * 4. loop test step 2 and 3 twice, to random CPU/GPU fault and prefetch migration order */ struct ReadThreadParams { HSAuint64* pBuf; HSAint64 BufferSize; int defaultGPUNode; }; unsigned int CpuReadThread(void* p) { struct ReadThreadParams* pArgs = reinterpret_cast(p); for (HSAuint64 i = 0; i < pArgs->BufferSize / 8; i += 512) EXPECT_EQ(i, pArgs->pBuf[i]); return 0; } unsigned int GpuReadThread(void* p) { struct ReadThreadParams* pArgs = reinterpret_cast(p); EXPECT_SUCCESS(SVMRangePrefetchToNode(pArgs->pBuf, pArgs->BufferSize, pArgs->defaultGPUNode)); return 0; } TEST_P(KFDSVMRangeTest, MultiThreadMigrationTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } unsigned long test_loops = 2; unsigned long BufferSize = 1UL << 27; HsaSVMRange SysBuffer(BufferSize, defaultGPUNode); HSAuint64 *pBuf = SysBuffer.As(); HsaSVMRange DataBuffer(BufferSize, defaultGPUNode); HSAuint64 *pData = DataBuffer.As(); SDMAQueue sdmaQueue; uint64_t threadId; struct ReadThreadParams params; params.pBuf = pBuf; params.BufferSize = BufferSize; params.defaultGPUNode = defaultGPUNode; EXPECT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); for (HSAuint64 i = 0; i < BufferSize / 8; i++) pBuf[i] = i; for (HSAuint64 i = 0; i < test_loops; i++) { /* 2 threads migrate to GPU */ sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), pData, pBuf, BufferSize)); ASSERT_EQ(true, StartThread(&GpuReadThread, ¶ms, threadId)); sdmaQueue.Wait4PacketConsumption(); WaitForThread(threadId); /* 2 threads migrate to cpu */ ASSERT_EQ(true, StartThread(&CpuReadThread, ¶ms, threadId)); EXPECT_SUCCESS(SVMRangePrefetchToNode(pBuf, BufferSize, 0)); WaitForThread(threadId); } EXPECT_SUCCESS(sdmaQueue.Destroy()); TEST_END } /* * Test SVM support file backed range * * Create temp file, mmap to alloc memory backed on file. * Create file backed svm range, to map to GPU for xnack on or off * Use sdma to write data to memory, should write to file * Close file, and then check if file data is updated correctly */ TEST_P(KFDSVMRangeTest, MigrateFileBackedRangeTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } char tmpfname[] = "/tmp/kfdtest-XXXXXX"; int fd = mkostemp(tmpfname, 0600); ASSERT_NE(-1, fd); size_t size = PAGE_SIZE; char *buf = reinterpret_cast(alloca(size)); memset(buf, 0x30, size); ASSERT_EQ(size, write(fd, buf, size)); void *MmapedFile = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); ASSERT_NE(MAP_FAILED, MmapedFile); HsaSVMRange filebackedRange(MmapedFile, size, defaultGPUNode, defaultGPUNode); SDMAQueue sdmaQueue; EXPECT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); sdmaQueue.PlaceAndSubmitPacket(SDMAFillDataPacket(sdmaQueue.GetFamilyId(), MmapedFile, 0x33333333, size)); sdmaQueue.Wait4PacketConsumption(); EXPECT_SUCCESS(sdmaQueue.Destroy()); munmap(MmapedFile, size); EXPECT_SUCCESS(close(fd)); fd = open(tmpfname, O_RDONLY); ASSERT_NE(-1, fd); ASSERT_EQ(size, read(fd, buf, size)); EXPECT_EQ(0x33, buf[0]); EXPECT_SUCCESS(close(fd)); EXPECT_SUCCESS(remove(tmpfname)); TEST_END } /* * Test SVM support read only range * * Map read only range to GPU, test sdma can read the range * write to range should trigger GPU vm fault for both xnack on and off */ TEST_P(KFDSVMRangeTest, ReadOnlyRangeTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (!GetVramSize(defaultGPUNode)) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } /* * Use child process to run test because the test trigger GPU vm fault, KFD evict all user queues * of the process and no more test can run after vm fault on the process. */ int pid = fork(); if (pid == 0) { TearDown(); SetUp(); } else { int childStatus; waitpid(pid, &childStatus, 0); if (is_dgpu()) { EXPECT_EQ(true, WIFEXITED(childStatus)); EXPECT_EQ(0, WEXITSTATUS(childStatus)); } else { EXPECT_EQ(true, WIFSIGNALED(childStatus)); EXPECT_EQ(SIGSEGV, WTERMSIG(childStatus)); } return; } /* Use child process to run test */ int ret = 0; HsaSVMRange inBuffer(PAGE_SIZE * 2, defaultGPUNode); HSAuint8 *pinBuf = inBuffer.As(); memset(pinBuf, 0x55, PAGE_SIZE); /* Map readonly pinBuf to GPU, sDMA should be able to read it */ mprotect(pinBuf, PAGE_SIZE, PROT_READ); HsaSVMRange outputBuffer(PAGE_SIZE, defaultGPUNode); HSAuint8 *pBuf = outputBuffer.As(); HsaEvent *vmFaultEvent; HSAuint64 faultAddress; HsaEventDescriptor eventDesc; eventDesc.EventType = HSA_EVENTTYPE_MEMORY; eventDesc.NodeId = defaultGPUNode; eventDesc.SyncVar.SyncVar.UserData = NULL; eventDesc.SyncVar.SyncVarSize = 0; ret = hsaKmtCreateEvent(&eventDesc, true, false, &vmFaultEvent); if (ret != HSAKMT_STATUS_SUCCESS) { WARN() << "Event create failed" << std::endl; exit(ret); } SDMAQueue sdmaQueue; ret = sdmaQueue.Create(defaultGPUNode); if (ret != HSAKMT_STATUS_SUCCESS) { WARN() << "Queue create failed" << std::endl; goto queue_fail; } sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), pBuf, reinterpret_cast(pinBuf), PAGE_SIZE)); sdmaQueue.Wait4PacketConsumption(); EXPECT_EQ(0x55, pBuf[0]); if (pBuf[0] != 0x55) goto event_fail; /* sDMA write to readonly pinBuf should fail with GPU vm fault, check if pinBuf content is * not changed, and KFD send HSA_EVENTTYPE_MEMORY event back with fault address pinBuf. * * This must be the last step of test because all queues are evicted after vm fault. */ memset(pBuf, 0xAA, PAGE_SIZE); sdmaQueue.PlaceAndSubmitPacket(SDMACopyDataPacket(sdmaQueue.GetFamilyId(), pinBuf, reinterpret_cast(pBuf), PAGE_SIZE)); ret = hsaKmtWaitOnEvent(vmFaultEvent, g_TestTimeOut); if (ret != HSAKMT_STATUS_SUCCESS) { WARN() << "Wait failed. No Exception triggered" << std::endl; goto event_fail; } if (vmFaultEvent->EventData.EventType != HSA_EVENTTYPE_MEMORY) { WARN() << "Unexpected Event Received " << vmFaultEvent->EventData.EventType << std::endl; ret = HSAKMT_STATUS_ERROR; goto event_fail; } faultAddress = vmFaultEvent->EventData.EventData.MemoryAccessFault.VirtualAddress; if (faultAddress != (HSAuint64)pinBuf) { WARN() << "Unexpected Fault Address " << faultAddress << std::endl; ret = HSAKMT_STATUS_ERROR; } event_fail: EXPECT_SUCCESS(sdmaQueue.Destroy()); queue_fail: hsaKmtDestroyEvent(vmFaultEvent); /* Child process exit, otherwise it will continue to run remaining tests */ exit(ret); TEST_END } /* * Test SMI HMM SVM profiling event * Use separate thread to read event the same way as ROCr and ROCProfiler */ struct ReadEventThreadParams { int nodeid; HSAuint64 *pBuf; int BufSize; pthread_barrier_t *barrier; }; unsigned int ReadSMIEventThread(void* p) { struct ReadEventThreadParams *pArgs = (struct ReadEventThreadParams *)p; char msg[HSA_SMI_EVENT_MSG_SIZE]; struct pollfd fds = {0}; HSAuint64 events; int fd; EXPECT_SUCCESS(hsaKmtOpenSMI(pArgs->nodeid, &fd)); events = HSA_SMI_EVENT_MASK_FROM_INDEX(HSA_SMI_EVENT_INDEX_MAX) - 1; EXPECT_EQ(write(fd, &events, sizeof(events)), sizeof(events)); pthread_barrier_wait(pArgs->barrier); fds.fd = fd; fds.events = POLLIN; EXPECT_GE(poll(&fds, 1, 1000), 0); memset(msg, 0, sizeof(msg)); EXPECT_GE(read(fd, msg, HSA_SMI_EVENT_MSG_SIZE), 0); int event_id, pid, size, trigger, unused; HSAuint64 timestamp; HSAuint64 addr; EXPECT_EQ(sscanf(msg, "%x %ld -%d @%lx(%d) %d->%x %x:%d %d\n", &event_id, ×tamp, &pid, &addr, &size, &unused, &unused, &unused, &unused, &trigger), 10); EXPECT_EQ(event_id, HSA_SMI_EVENT_MIGRATE_START); EXPECT_EQ((HSAuint64 *)(addr << PAGE_SHIFT), pArgs->pBuf); EXPECT_EQ(size << PAGE_SHIFT, pArgs->BufSize); EXPECT_EQ(pid, getpid()); EXPECT_EQ(trigger, HSA_MIGRATE_TRIGGER_PREFETCH); close(fd); return 0; } TEST_P(KFDSVMRangeTest, HMMProfilingEvent) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; if (m_VersionInfo.KernelInterfaceMinorVersion < 10) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (!GetVramSize(defaultGPUNode)) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } if (m_NodeInfo.IsAppAPU(defaultGPUNode)) { LOG() << "Skipping test on AppAPU." << std::endl; return; } pthread_barrier_t barrier; ASSERT_SUCCESS(pthread_barrier_init(&barrier, NULL, 2)); int BufSize = 16 << 10; HsaSVMRange SysBuffer(BufSize, defaultGPUNode); HSAuint64 *pBuf = SysBuffer.As(); struct ReadEventThreadParams pArgs = {defaultGPUNode, pBuf, BufSize, &barrier}; uint64_t threadId; ASSERT_EQ(true, StartThread(&ReadSMIEventThread, &pArgs, threadId)); pthread_barrier_wait(&barrier); EXPECT_SUCCESS(SVMRangePrefetchToNode(pBuf, BufSize, defaultGPUNode)); WaitForThread(threadId); TEST_END } /* * Test SVM support VRAM overcommitment * * Prefetch total VRAM size plus overCommitSize SVM range to VRAM. after VRAM is full, * KFD should support VRAM overcommitment by evicting SVM ranges to system memory to alloc * VRAM for new ranges. */ TEST_P(KFDSVMRangeTest, VramOvercommitTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } HSAuint64 vramSize = GetVramSize(defaultGPUNode); if (!vramSize) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } unsigned long overCommitSize = 1UL << 30; /* With XNACK off, KFD checks that all SVM memory will fit into system memory */ if (vramSize + overCommitSize > GetSysMemSize() / 2) { LOG() << "Skipping test: Not enough system memory." << std::endl; return; } unsigned long BufSize = 512UL << 20; unsigned long numBufs = (vramSize + overCommitSize) / BufSize; HSAKMT_STATUS ret; void *pBuf[numBufs]; unsigned long i; for (i = 0; i < numBufs; i++) { pBuf[i] = mmap(0, BufSize, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_NE(MAP_FAILED, pBuf[i]); ret = RegisterSVMRange(defaultGPUNode, pBuf[i], BufSize, defaultGPUNode, 0); if (ret != HSAKMT_STATUS_SUCCESS) break; } EXPECT_EQ(numBufs, i); while (i--) munmap(pBuf[i], BufSize); TEST_END } /* * Test SVM support VRAM overcommitment * * Prefetch giant overcommit SVM range to VRAM, KFD should support VRAM overcommitment * by spliting giant range into smaller ranges, evicting SVM ranges to system memory to * alloc VRAM for overcommitment ranges. */ TEST_P(KFDSVMRangeTest, VramOvercommitGiantRangeTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } HSAuint64 vramSize = GetVramSize(defaultGPUNode); if (!vramSize) { LOG() << "Skipping test: No VRAM found." << std::endl; return; } unsigned long overCommitSize = 1UL << 30; /* With XNACK off, KFD checks that all SVM memory will fit into system memory */ if (vramSize + overCommitSize > GetSysMemSize() / 2) { LOG() << "Skipping test: no enough system memory." << std::endl; return; } unsigned long BufSize = vramSize + overCommitSize; HSAKMT_STATUS ret; void *pBuf; pBuf = mmap(0, BufSize, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_NE(MAP_FAILED, pBuf); ret = RegisterSVMRange(defaultGPUNode, pBuf, BufSize, defaultGPUNode, 0); EXPECT_EQ (HSAKMT_STATUS_SUCCESS, ret); munmap(pBuf, BufSize); TEST_END } /* * Test partial range prefault * * mmap alloc 4 pages range, memset middle 2 pages, prefetch entire range to VRAM, * use sdma to memset the rest 2 pages, each page has different value 0x1, 0x2, 0x3, 0x4 * then check if all page have the specific value after migrating 4 pages to system memory. */ TEST_P(KFDSVMRangeTest, PrefaultPartialRangeTest) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); if (!SVMAPISupported()) return; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; if (m_FamilyId < FAMILY_AI) { LOG() << std::hex << "Skipping test: No svm range support for family ID 0x" << m_FamilyId << "." << std::endl; return; } unsigned long BufSize = 4 * PAGE_SIZE; HSAKMT_STATUS ret; char *pBuf; pBuf = (char *)mmap(0, BufSize, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_NE(MAP_FAILED, pBuf); memset(pBuf + PAGE_SIZE, 0x2, PAGE_SIZE); memset(pBuf + 2 * PAGE_SIZE, 0x3, PAGE_SIZE); EXPECT_SUCCESS(RegisterSVMRange(defaultGPUNode, pBuf, BufSize, 0, 0)); EXPECT_SUCCESS(SVMRangePrefetchToNode(pBuf, BufSize, defaultGPUNode)); SDMAQueue sdmaQueue; EXPECT_SUCCESS(sdmaQueue.Create(defaultGPUNode)); sdmaQueue.PlaceAndSubmitPacket(SDMAFillDataPacket(sdmaQueue.GetFamilyId(), pBuf, 0x01010101, PAGE_SIZE)); sdmaQueue.PlaceAndSubmitPacket(SDMAFillDataPacket(sdmaQueue.GetFamilyId(), pBuf + 3 * PAGE_SIZE, 0x04040404, PAGE_SIZE)); sdmaQueue.Wait4PacketConsumption(); EXPECT_SUCCESS(sdmaQueue.Destroy()); for (int i = 0; i < 4; i++) EXPECT_EQ(pBuf[i * PAGE_SIZE], i + 1); munmap(pBuf, BufSize); TEST_END } INSTANTIATE_TEST_CASE_P(, KFDSVMRangeTest,::testing::Values(0, 1)); ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDSVMRangeTest.hpp000066400000000000000000000031601446477712600251540ustar00rootroot00000000000000/* * Copyright (C) 2020 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_SVMRANGE_TEST__H__ #define __KFD_SVMRANGE_TEST__H__ #include #include "KFDBaseComponentTest.hpp" class KFDSVMRangeTest : public KFDBaseComponentTest, public ::testing::WithParamInterface { public: KFDSVMRangeTest() {} ~KFDSVMRangeTest() {} void SplitRangeTest(int defaultGPUNode, int prefetch_location); protected: virtual void SetUp(); virtual void TearDown(); }; #endif // __KFD_LOCALMEMORY_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDTestFlags.hpp000066400000000000000000000050451446477712600245720ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_TEST_FLAGS__H__ #define __KFD_TEST_FLAGS__H__ extern unsigned int g_TestRunProfile; extern unsigned int g_TestENVCaps; extern unsigned int g_TestTimeOut; extern int g_TestNodeId; extern int g_TestDstNodeId; extern bool g_IsChildProcess; // Each test should call TEST_START with the test custom profile and HW scheduling enum TESTPROFILE{ TESTPROFILE_DEV = 0x1, TESTPROFILE_PROMO = 0x2, // 0x4 - 0x8000 - unused flags // Can add any flag that will mark only part of the tests to run TESTPROFILE_RUNALL = 0xFFFF }; enum ENVCAPS{ ENVCAPS_NOADDEDCAPS = 0x0, ENVCAPS_HWSCHEDULING = 0x1, ENVCAPS_16BITPASID = 0x2, ENVCAPS_32BITLINUX = 0x4, ENVCAPS_64BITLINUX = 0x8 // 0x8 - 0x8000 - unused flags // Can add any flag that will mark specific hw limitation or capability }; enum KfdFamilyId { FAMILY_UNKNOWN = 0, FAMILY_CI, // Sea Islands: Hawaii (P), Maui (P), Bonaire (M) FAMILY_KV, // Fusion Kaveri: Spectre, Spooky; Fusion Kabini: Kalindi FAMILY_VI, // Volcanic Islands: Iceland (V), Tonga (M) FAMILY_CZ, // Carrizo, Nolan, Amur FAMILY_AI, // Arctic Islands FAMILY_RV, // Raven FAMILY_AR, // Arcturus FAMILY_AL, // Aldebaran FAMILY_AV, // Aqua Vanjaram FAMILY_NV, // Navi10 FAMILY_GFX11, // GFX11 }; #endif // __KFD_TEST_FLAGS__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDTestMain.cpp000066400000000000000000000064471446477712600244240ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "gtest/gtest.h" #include "KFDTestFlags.hpp" #include "KFDTestUtil.hpp" #include "GoogleTestExtension.hpp" #include "OSWrapper.hpp" #define KFD_TEST_DEFAULT_TIMEOUT 10000 std::ostream& operator << (std::ostream& out, TESTPROFILE profile) { switch (profile) { case TESTPROFILE_DEV: out << "Developer Test"; break; case TESTPROFILE_PROMO: out << "Promotion Test"; break; case TESTPROFILE_RUNALL: out << "Full Test"; break; default: out << "INVALID"; } return out; } unsigned int g_TestRunProfile; unsigned int g_TestENVCaps; unsigned int g_TestTimeOut; int g_TestNodeId; int g_TestDstNodeId; bool g_IsChildProcess; unsigned int g_SleepTime; unsigned int g_TestGPUFamilyId; class KFDBaseComponentTest *g_baseTest; GTEST_API_ int main(int argc, char **argv) { // Default values for run parameters g_TestRunProfile = TESTPROFILE_RUNALL; g_TestENVCaps = ENVCAPS_NOADDEDCAPS | ENVCAPS_64BITLINUX; g_TestTimeOut = KFD_TEST_DEFAULT_TIMEOUT; testing::InitGoogleTest(&argc, argv); CommandLineArguments args; memset(&args, 0, sizeof(args)); bool success = GetCommandLineArguments(argc, argv, args); if (success) { if ((GetHwCapabilityHWS() || args.HwsEnabled == HWCAP__FORCE_ENABLED) && (args.HwsEnabled != HWCAP__FORCE_DISABLED)) g_TestENVCaps |= ENVCAPS_HWSCHEDULING; g_TestRunProfile = args.TestProfile; g_IsChildProcess = args.ChildProcess; if ( args.TimeOut > 0 ) g_TestTimeOut = args.TimeOut; g_SleepTime = 0x00; if (args.SleepTime > 0) { g_SleepTime = args.SleepTime; } // If --node is not specified, then args.NodeId == -1 g_TestNodeId = args.NodeId; g_TestDstNodeId = args.DstNodeId; LOG() << "Profile: " << (TESTPROFILE)g_TestRunProfile << std::endl; LOG() << "HW capabilities: 0x" << std::hex << g_TestENVCaps << std::endl; if (g_SleepTime > 0) { LOG() << "Sleep time in seconds as specified by user: " << std::dec << g_SleepTime << std::endl; } return RUN_ALL_TESTS(); } } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDTestUtil.cpp000066400000000000000000000727531446477712600244600ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDTestUtil.hpp" #include #include #include #include #include #include "BaseQueue.hpp" #include "Dispatch.hpp" #include "SDMAPacket.hpp" void WaitUntilInput() { char dummy; printf("Press enter to continue: "); do { scanf("%c", &dummy); } while (dummy != 10); // enter key's ascii value is 10 } /* fscanf_dec - read a file whose content is a decimal number * @file [IN ] file to read * @num [OUT] number in the file * * It is copied from the same function in libhsakmt */ HSAKMT_STATUS fscanf_dec(const char *file, uint32_t *num) { FILE *fd; HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS; fd = fopen(file, "r"); if (!fd) { LOG() << "Failed to open " << file << std::endl; return HSAKMT_STATUS_INVALID_PARAMETER; } if (fscanf(fd, "%u", num) != 1) { LOG() << "Failed to parse as a decimal: " << file << std::endl;; ret = HSAKMT_STATUS_ERROR; } fclose(fd); return ret; } uint64_t RoundToPowerOf2(uint64_t val) { val--; /* Shift with amount larger than the bit width can result in * undefined behavior by compiler for release builds. * Shift till 32 bit only which is less than bit width of val. */ for (int i = 1; i <= 32; i *= 2) val |= val >> i; val++; return val; } bool WaitOnValue(const volatile unsigned int *buf, unsigned int value, unsigned int timeOut) { while (timeOut > 0 && *buf != value) { Delay(1); if (timeOut != HSA_EVENTTIMEOUT_INFINITE) timeOut--; } return *buf == value; } void SplitU64(const HSAuint64 value, unsigned int& rLoPart, unsigned int& rHiPart) { rLoPart = static_cast(value); rHiPart = static_cast(value >> 32); } bool GetHwCapabilityHWS() { unsigned int value = 0; bool valExists = ReadDriverConfigValue(CONFIG_HWS, value); /* HWS is enabled by default */ return ( (!valExists) || ( value > 0)); } HSAKMT_STATUS CreateQueueTypeEvent( bool ManualReset, // IN bool IsSignaled, // IN unsigned int NodeId, // IN HsaEvent** Event // OUT ) { HsaEventDescriptor Descriptor; // TODO: Create per-OS header with this sort of definitions #ifdef _WIN32 Descriptor.EventType = HSA_EVENTTYPE_QUEUE_EVENT; #else Descriptor.EventType = HSA_EVENTTYPE_SIGNAL; #endif Descriptor.SyncVar.SyncVar.UserData = (void*)0xABCDABCD; Descriptor.NodeId = NodeId; return hsaKmtCreateEvent(&Descriptor, ManualReset, IsSignaled, Event); } static bool is_dgpu_dev = false; bool is_dgpu() { return is_dgpu_dev; } bool hasPciAtomicsSupport(int node) { /* If we can't get Node Properties, assume a lack of Atomics support */ HsaNodeProperties *pNodeProperties = new HsaNodeProperties(); if (hsaKmtGetNodeProperties(node, pNodeProperties)) { LOG() << "Unable to get Node Properties for node " << node << std::endl; return false; } /* APUs don't have IO Links, but support Atomic Ops by default */ if (pNodeProperties->NumCPUCores && pNodeProperties->NumFComputeCores) return true; /* gfx11 is able to perform aotmic ops even PCI reports no atomic support. */ if (pNodeProperties->EngineId.ui32.Major >= 11) return true; HsaIoLinkProperties *IolinkProperties = new HsaIoLinkProperties[pNodeProperties->NumIOLinks]; if (hsaKmtGetNodeIoLinkProperties(node, pNodeProperties->NumIOLinks, IolinkProperties)) { LOG() << "Unable to get Node IO Link Information for node " << node << std::endl; return false; } /* Make sure we're checking GPU-to-CPU connection here */ for (int linkId = 0; linkId < pNodeProperties->NumIOLinks; linkId++) { /* Make sure it's a CPU */ HsaNodeProperties *linkProps = new HsaNodeProperties(); if (hsaKmtGetNodeProperties(IolinkProperties[linkId].NodeTo, linkProps)) { LOG() << "Unable to get connected device's IO Link information" << std::endl; return false; } if (linkProps->NumCPUCores) { /* IOLink flags are only valid if Override flag is set */ return (IolinkProperties[linkId].Flags.ui32.Override && !IolinkProperties[linkId].Flags.ui32.NoAtomics32bit && !IolinkProperties[linkId].Flags.ui32.NoAtomics64bit); } } return false; } unsigned int FamilyIdFromNode(const HsaNodeProperties *props) { unsigned int familyId = FAMILY_UNKNOWN; switch (props->EngineId.ui32.Major) { case 7: if (props->EngineId.ui32.Minor == 0) { if (props->EngineId.ui32.Stepping == 0) familyId = FAMILY_KV; else familyId = FAMILY_CI; } break; case 8: familyId = FAMILY_VI; if (props->EngineId.ui32.Stepping == 1) familyId = FAMILY_CZ; break; case 9: familyId = FAMILY_AI; if (props->EngineId.ui32.Minor == 4) familyId = FAMILY_AV; else if (props->EngineId.ui32.Stepping == 2) familyId = FAMILY_RV; else if (props->EngineId.ui32.Stepping == 8) familyId = FAMILY_AR; else if (props->EngineId.ui32.Stepping == 10) familyId = FAMILY_AL; break; case 10: familyId = FAMILY_NV; break; case 11: familyId = FAMILY_GFX11; break; } if (props->NumCPUCores && props->NumFComputeCores) is_dgpu_dev = false; else is_dgpu_dev = true; return familyId; } void GetHwQueueInfo(const HsaNodeProperties *props, unsigned int *p_num_cp_queues, unsigned int *p_num_sdma_engines, unsigned int *p_num_sdma_xgmi_engines, unsigned int *p_num_sdma_queues_per_engine) { if (p_num_sdma_engines) *p_num_sdma_engines = props->NumSdmaEngines; if (p_num_sdma_xgmi_engines) *p_num_sdma_xgmi_engines = props->NumSdmaXgmiEngines; if (p_num_sdma_queues_per_engine) *p_num_sdma_queues_per_engine = props->NumSdmaQueuesPerEngine; if (p_num_cp_queues) *p_num_cp_queues = props->NumCpQueues; } bool isTonga(const HsaNodeProperties *props) { /* Tonga has some workarounds in the thunk that cause certain failures */ if (props->EngineId.ui32.Major == 8 && props->EngineId.ui32.Stepping == 2) { return true; } return false; } const uint32_t GetGfxVersion(const HsaNodeProperties *props) { return ((props->EngineId.ui32.Major << 16) | (props->EngineId.ui32.Minor << 8) | (props->EngineId.ui32.Stepping)); } HSAuint64 GetSystemTickCountInMicroSec() { struct timeval t; gettimeofday(&t, 0); return t.tv_sec * 1000000ULL + t.tv_usec; } const HsaMemoryBuffer HsaMemoryBuffer::Null; HsaMemoryBuffer::HsaMemoryBuffer(HSAuint64 size, unsigned int node, bool zero, bool isLocal, bool isExec, bool isScratch, bool isReadOnly, bool isUncached, bool NonPaged) :m_Size(size), m_pUser(NULL), m_pBuf(NULL), m_Local(isLocal), m_Node(node) { m_Flags.Value = 0; HsaMemMapFlags mapFlags = {0}; bool map_specific_gpu = (node && !isScratch); if (isScratch) { m_Flags.ui32.Scratch = 1; m_Flags.ui32.HostAccess = 1; } else { m_Flags.ui32.PageSize = HSA_PAGE_SIZE_4KB; if (isLocal) { m_Flags.ui32.HostAccess = 0; m_Flags.ui32.NonPaged = 1; m_Flags.ui32.CoarseGrain = 1; EXPECT_EQ(isUncached, 0) << "Uncached flag is relevant only for system or host memory"; } else { m_Flags.ui32.HostAccess = 1; m_Flags.ui32.NonPaged = NonPaged ? 1 : 0; m_Flags.ui32.CoarseGrain = 0; m_Flags.ui32.NoNUMABind = 1; m_Flags.ui32.Uncached = isUncached; } if (isExec) m_Flags.ui32.ExecuteAccess = 1; } if (isReadOnly) m_Flags.ui32.ReadOnly = 1; if (zero) EXPECT_EQ(m_Flags.ui32.HostAccess, 1); EXPECT_SUCCESS(hsaKmtAllocMemory(m_Node, m_Size, m_Flags, &m_pBuf)); if (is_dgpu()) { if (map_specific_gpu) EXPECT_SUCCESS(hsaKmtMapMemoryToGPUNodes(m_pBuf, m_Size, NULL, mapFlags, 1, &m_Node)); else EXPECT_SUCCESS(hsaKmtMapMemoryToGPU(m_pBuf, m_Size, NULL)); m_MappedNodes = 1 << m_Node; } if (zero && !isLocal) Fill(0); } HsaMemoryBuffer::HsaMemoryBuffer(void *addr, HSAuint64 size): m_Size(size), m_pUser(addr), m_pBuf(NULL), m_Local(false), m_Node(0) { HSAuint64 gpuva = 0; EXPECT_SUCCESS(hsaKmtRegisterMemory(m_pUser, m_Size)); EXPECT_SUCCESS(hsaKmtMapMemoryToGPU(m_pUser, m_Size, &gpuva)); m_pBuf = gpuva ? (void *)gpuva : m_pUser; } HsaMemoryBuffer::HsaMemoryBuffer() :m_Size(0), m_pBuf(NULL) { } void HsaMemoryBuffer::Fill(unsigned char value, HSAuint64 offset, HSAuint64 size) { HSAuint32 uiValue; EXPECT_EQ(m_Local, 0) << "Local Memory. Call Fill(HSAuint32 value, BaseQueue& baseQueue)"; size = size ? size : m_Size; ASSERT_TRUE(size + offset <= m_Size) << "Buffer Overflow" << std::endl; if (m_pUser != NULL) memset(reinterpret_cast(m_pUser) + offset, value, size); else if (m_pBuf != NULL) memset(reinterpret_cast(m_pBuf) + offset, value, size); else ASSERT_TRUE(0) << "Invalid HsaMemoryBuffer"; } /* Fill CPU accessible buffer with the value. */ void HsaMemoryBuffer::Fill(HSAuint32 value, HSAuint64 offset, HSAuint64 size) { HSAuint64 i; HSAuint32 *ptr = NULL; EXPECT_EQ(m_Local, 0) << "Local Memory. Call Fill(HSAuint32 value, BaseQueue& baseQueue)"; size = size ? size : m_Size; EXPECT_EQ((size & (sizeof(HSAuint32) - 1)), 0) << "Not word aligned. Call Fill(unsigned char)"; ASSERT_TRUE(size + offset <= m_Size) << "Buffer Overflow" << std::endl; if (m_pUser != NULL) ptr = reinterpret_cast(reinterpret_cast(m_pUser) + offset); else if (m_pBuf != NULL) ptr = reinterpret_cast(reinterpret_cast(m_pBuf) + offset); ASSERT_NOTNULL(ptr); for (i = 0; i < size / sizeof(HSAuint32); i++) ptr[i] = value; } /* Fill GPU only accessible Local memory with @value using SDMA Constant Fill Command */ void HsaMemoryBuffer::Fill(HSAuint32 value, BaseQueue& baseQueue, HSAuint64 offset, HSAuint64 size) { HsaEvent* event = NULL; EXPECT_NE(m_Local, 0) << "Not Local Memory. Call Fill(HSAuint32 value)"; ASSERT_SUCCESS(CreateQueueTypeEvent(false, false, m_Node, &event)); ASSERT_EQ(baseQueue.GetQueueType(), HSA_QUEUE_SDMA) << "Only SDMA queues supported"; size = size ? size : m_Size; ASSERT_TRUE(size + offset <= m_Size) << "Buffer Overflow" << std::endl; baseQueue.PlacePacket(SDMAFillDataPacket(baseQueue.GetFamilyId(), (reinterpret_cast(this->As() + offset)), value, size)); baseQueue.PlacePacket(SDMAFencePacket(baseQueue.GetFamilyId(), reinterpret_cast(event->EventData.HWData2), event->EventId)); baseQueue.PlaceAndSubmitPacket(SDMATrapPacket(event->EventId)); EXPECT_SUCCESS(hsaKmtWaitOnEvent(event, g_TestTimeOut)); hsaKmtDestroyEvent(event); } /* Check if HsaMemoryBuffer[location] has the pattern specified. * Return TRUE if correct pattern else return FALSE * HsaMemoryBuffer has to be CPU accessible */ bool HsaMemoryBuffer::IsPattern(HSAuint64 location, HSAuint32 pattern) { HSAuint32 *ptr = NULL; EXPECT_EQ(m_Local, 0) << "Local Memory. Call IsPattern(..baseQueue& baseQueue)"; if (location >= m_Size) /* Out of bounds */ return false; if (m_pUser != NULL) ptr = reinterpret_cast(m_pUser); else if (m_pBuf != NULL) ptr = reinterpret_cast(m_pBuf); else return false; if (ptr) return (ptr[location/sizeof(HSAuint32)] == pattern); return false; } /* Check if HsaMemoryBuffer[location] has the pattern specified. * Return TRUE if correct pattern else return FALSE * HsaMemoryBuffer is supposed to be only GPU accessible * Use @baseQueue to copy the HsaMemoryBuffer[location] to stack and check the value */ bool HsaMemoryBuffer::IsPattern(HSAuint64 location, HSAuint32 pattern, BaseQueue& baseQueue, volatile HSAuint32 *tmp) { HsaEvent* event = NULL; int ret; EXPECT_NE(m_Local, 0) << "Not Local Memory. Call IsPattern(HSAuint64 location, HSAuint32 pattern)"; EXPECT_EQ(baseQueue.GetQueueType(), HSA_QUEUE_SDMA) << "Only SDMA queues supported"; if (location >= m_Size) /* Out of bounds */ return false; ret = CreateQueueTypeEvent(false, false, m_Node, &event); if (ret) return false; *tmp = ~pattern; baseQueue.PlacePacket(SDMACopyDataPacket(baseQueue.GetFamilyId(), (void *)tmp, reinterpret_cast(this->As() + location), sizeof(HSAuint32))); baseQueue.PlacePacket(SDMAFencePacket(baseQueue.GetFamilyId(), reinterpret_cast(event->EventData.HWData2), event->EventId)); baseQueue.PlaceAndSubmitPacket(SDMATrapPacket(event->EventId)); ret = hsaKmtWaitOnEvent(event, g_TestTimeOut); hsaKmtDestroyEvent(event); if (ret) return false; return WaitOnValue(tmp, pattern); } unsigned int HsaMemoryBuffer::Size() { return m_Size; } HsaMemFlags HsaMemoryBuffer::Flags() { return m_Flags; } unsigned int HsaMemoryBuffer::Node() const { return m_Node; } int HsaMemoryBuffer::MapMemToNodes(unsigned int *nodes, unsigned int nodes_num) { int ret, bit; ret = hsaKmtRegisterMemoryToNodes(m_pBuf, m_Size, nodes_num, nodes); if (ret != 0) return ret; ret = hsaKmtMapMemoryToGPU(m_pBuf, m_Size, NULL); if (ret != 0) { hsaKmtDeregisterMemory(m_pBuf); return ret; } for (unsigned int i = 0; i < nodes_num; i++) { bit = 1 << nodes[i]; m_MappedNodes |= bit; } return 0; } int HsaMemoryBuffer::UnmapMemToNodes(unsigned int *nodes, unsigned int nodes_num) { int ret, bit; ret = hsaKmtUnmapMemoryToGPU(m_pBuf); if (ret) return ret; hsaKmtDeregisterMemory(m_pBuf); for (unsigned int i = 0; i < nodes_num; i++) { bit = 1 << nodes[i]; m_MappedNodes &= ~bit; } return 0; } void HsaMemoryBuffer::UnmapAllNodes() { unsigned int *Arr, size, i, j; int bit; size = 0; for (i = 0; i < 8; i++) { bit = 1 << i; if (m_MappedNodes & bit) size++; } Arr = (unsigned int *)malloc(sizeof(unsigned int) * size); if (!Arr) return; for (i = 0, j =0; i < 8; i++) { bit = 1 << i; if (m_MappedNodes & bit) Arr[j++] = i; } /* * TODO: When thunk is updated, use hsaKmtRegisterToNodes. Then nodes will be used */ hsaKmtUnmapMemoryToGPU(m_pBuf); hsaKmtDeregisterMemory(m_pBuf); m_MappedNodes = 0; free(Arr); } HsaMemoryBuffer::~HsaMemoryBuffer() { if (m_pUser != NULL) { hsaKmtUnmapMemoryToGPU(m_pUser); hsaKmtDeregisterMemory(m_pUser); } else if (m_pBuf != NULL) { if (is_dgpu()) { if (m_MappedNodes) { hsaKmtUnmapMemoryToGPU(m_pBuf); hsaKmtDeregisterMemory(m_pBuf); } } hsaKmtFreeMemory(m_pBuf, m_Size); } m_pBuf = NULL; } HsaInteropMemoryBuffer::HsaInteropMemoryBuffer(HSAuint64 device_handle, HSAuint64 buffer_handle, HSAuint64 size, unsigned int node) :m_Size(0), m_pBuf(NULL), m_graphic_handle(0), m_Node(node) { HSAuint64 flat_address; EXPECT_SUCCESS(hsaKmtMapGraphicHandle(m_Node, device_handle, buffer_handle, 0, size, &flat_address)); m_pBuf = reinterpret_cast(flat_address); } HsaInteropMemoryBuffer::~HsaInteropMemoryBuffer() { hsaKmtUnmapGraphicHandle(m_Node, (HSAuint64)m_pBuf, m_Size); } HsaNodeInfo::HsaNodeInfo() { } /* Init - Get and store information about all the HSA nodes from the Thunk Library. * @NumOfNodes - Number to system nodes returned by hsaKmtAcquireSystemProperties * @Return - false: if no node information is available */ bool HsaNodeInfo::Init(int NumOfNodes) { HsaNodeProperties *nodeProperties; _HSAKMT_STATUS status; bool ret = false; for (int i = 0; i < NumOfNodes; i++) { nodeProperties = new HsaNodeProperties(); status = hsaKmtGetNodeProperties(i, nodeProperties); /* This is not a fatal test (not using assert), since even when it fails for one node * we want to get information regarding others. */ EXPECT_SUCCESS(status) << "Node index: " << i << "hsaKmtGetNodeProperties returned status " << status; if (status == HSAKMT_STATUS_SUCCESS) { m_HsaNodeProps.push_back(nodeProperties); ret = true; // Return true if atleast one information is available if (nodeProperties->NumFComputeCores) m_NodesWithGPU.push_back(i); else m_NodesWithoutGPU.push_back(i); } else { delete nodeProperties; } } return ret; } HsaNodeInfo::~HsaNodeInfo() { const HsaNodeProperties *nodeProperties; for (unsigned int i = 0; i < m_HsaNodeProps.size(); i++) delete m_HsaNodeProps.at(i); m_HsaNodeProps.clear(); } const std::vector& HsaNodeInfo::GetNodesWithGPU() const { return m_NodesWithGPU; } const HsaNodeProperties* HsaNodeInfo::GetNodeProperties(int NodeNum) const { return m_HsaNodeProps.at(NodeNum); } const HsaNodeProperties* HsaNodeInfo::HsaDefaultGPUNodeProperties() const { int NodeNum = HsaDefaultGPUNode(); if (NodeNum < 0) return NULL; return GetNodeProperties(NodeNum); } const int HsaNodeInfo::HsaDefaultGPUNode() const { if (m_NodesWithGPU.size() == 0) return -1; if (g_TestNodeId >= 0) { // Check if this is a valid Id, if so use this else use first available for (unsigned int i = 0; i < m_NodesWithGPU.size(); i++) { if (g_TestNodeId == m_NodesWithGPU.at(i)) return g_TestNodeId; } } return m_NodesWithGPU.at(0); } void HsaNodeInfo::PrintNodeInfo() const { const HsaNodeProperties *nodeProperties; for (unsigned int i = 0; i < m_HsaNodeProps.size(); i++) { nodeProperties = m_HsaNodeProps.at(i); LOG() << "***********************************" << std::endl; LOG() << "Node " << i << std::endl; LOG() << "NumCPUCores=\t" << nodeProperties->NumCPUCores << std::endl; LOG() << "NumFComputeCores=\t" << nodeProperties->NumFComputeCores << std::endl; LOG() << "NumMemoryBanks=\t" << nodeProperties->NumMemoryBanks << std::endl; LOG() << "VendorId=\t" << nodeProperties->VendorId << std::endl; LOG() << "DeviceId=\t" << nodeProperties->DeviceId << std::endl; LOG() << "***********************************" << std::endl; } LOG() << "Default GPU NODE " << HsaDefaultGPUNode() << std::endl; } const bool HsaNodeInfo::IsGPUNodeLargeBar(int node) const { const HsaNodeProperties *pNodeProperties; pNodeProperties = GetNodeProperties(node); if (pNodeProperties) { HsaMemoryProperties *memoryProperties = new HsaMemoryProperties[pNodeProperties->NumMemoryBanks]; EXPECT_SUCCESS(hsaKmtGetNodeMemoryProperties(node, pNodeProperties->NumMemoryBanks, memoryProperties)); for (unsigned bank = 0; bank < pNodeProperties->NumMemoryBanks; bank++) if (memoryProperties[bank].HeapType == HSA_HEAPTYPE_FRAME_BUFFER_PUBLIC) { delete [] memoryProperties; return true; } delete [] memoryProperties; } return false; } const bool HsaNodeInfo::IsAppAPU(int node) const { const HsaNodeProperties *pNodeProperties = GetNodeProperties(node); /* CPU with compute cores is small APU, not AppAPU */ if (pNodeProperties->NumCPUCores && pNodeProperties->NumFComputeCores) return false; HsaIoLinkProperties *IolinkProperties = new HsaIoLinkProperties[pNodeProperties->NumIOLinks]; if (hsaKmtGetNodeIoLinkProperties(node, pNodeProperties->NumIOLinks, IolinkProperties)) { LOG() << "Unable to get Node IO Link Information for node " << node << std::endl; delete [] IolinkProperties; return false; } /* Checking GPU-to-CPU connection weight */ for (int linkId = 0; linkId < pNodeProperties->NumIOLinks; linkId++) { HsaNodeProperties linkProps; if (hsaKmtGetNodeProperties(IolinkProperties[linkId].NodeTo, &linkProps)) { LOG() << "Unable to get connected device's IO Link information" << std::endl; break; } /* If it's GPU-CPU link with connection weight KFD_CRAT_INTRA_SOCKET_WEIGHT 13 */ if (linkProps.NumCPUCores && IolinkProperties[linkId].Weight == 13) { delete [] IolinkProperties; return true; } } delete [] IolinkProperties; return false; } const bool HsaNodeInfo::IsPeerAccessibleByNode(int peer, int node) const { const HsaNodeProperties *pNodeProperties; pNodeProperties = GetNodeProperties(node); if (pNodeProperties) { HsaIoLinkProperties p2pLinksProperties[pNodeProperties->NumIOLinks]; EXPECT_SUCCESS(hsaKmtGetNodeIoLinkProperties(node, pNodeProperties->NumIOLinks, p2pLinksProperties)); for (unsigned link = 0; link < pNodeProperties->NumIOLinks; link++) if (p2pLinksProperties[link].NodeTo == peer) return true; } return false; } const int HsaNodeInfo::FindLargeBarGPUNode() const { const std::vector gpuNodes = GetNodesWithGPU(); for (unsigned i = 0; i < gpuNodes.size(); i++) if (IsGPUNodeLargeBar(gpuNodes.at(i))) return gpuNodes.at(i); return -1; } const bool HsaNodeInfo::AreGPUNodesXGMI(int node0, int node1) const { const HsaNodeProperties *pNodeProperties0 = GetNodeProperties(node0); const HsaNodeProperties *pNodeProperties1 = GetNodeProperties(node1); if ((pNodeProperties0->HiveID != 0) && (pNodeProperties1->HiveID != 0) && (pNodeProperties0->HiveID == pNodeProperties1->HiveID)) return true; return false; } int HsaNodeInfo::FindAccessiblePeers(std::vector *peers, HSAuint32 node) const { peers->push_back(node); for (unsigned i = 0; i < m_NodesWithGPU.size(); i++) { if (m_NodesWithGPU.at(i) == node) continue; if (IsPeerAccessibleByNode(m_NodesWithGPU.at(i), node)) peers->push_back(m_NodesWithGPU.at(i)); } return peers->size(); } const bool HsaNodeInfo::IsNodeXGMItoCPU(int node) const { const HsaNodeProperties *pNodeProperties; bool ret = false; pNodeProperties = GetNodeProperties(node); if (pNodeProperties && pNodeProperties->NumIOLinks) { HsaIoLinkProperties *IolinkProperties = new HsaIoLinkProperties[pNodeProperties->NumIOLinks]; EXPECT_SUCCESS(hsaKmtGetNodeIoLinkProperties(node, pNodeProperties->NumIOLinks, IolinkProperties)); for (int linkId = 0; linkId < pNodeProperties->NumIOLinks; linkId++) { EXPECT_EQ(node, IolinkProperties[linkId].NodeFrom); const HsaNodeProperties *pNodeProperties0 = GetNodeProperties(IolinkProperties[linkId].NodeTo); if (pNodeProperties0->NumFComputeCores == 0 && IolinkProperties[linkId].IoLinkType == HSA_IOLINK_TYPE_XGMI) ret = true; } delete [] IolinkProperties; } return ret; } HSAKMT_STATUS RegisterSVMRange(HSAuint32 GPUNode, void *MemoryAddress, HSAuint64 SizeInBytes, HSAuint32 PrefetchNode, HSAuint32 SVMFlags) { HSA_SVM_ATTRIBUTE *attrs; HSAuint64 s_attr; HSAuint32 nattr; HSAKMT_STATUS r; nattr = 4; s_attr = sizeof(*attrs) * nattr; attrs = (HSA_SVM_ATTRIBUTE *)alloca(s_attr); attrs[0].type = HSA_SVM_ATTR_PREFETCH_LOC; attrs[0].value = PrefetchNode; attrs[1].type = HSA_SVM_ATTR_PREFERRED_LOC; attrs[1].value = PrefetchNode; attrs[2].type = HSA_SVM_ATTR_SET_FLAGS; attrs[2].value = SVMFlags; attrs[3].type = HSA_SVM_ATTR_ACCESS; attrs[3].value = GPUNode; r = hsaKmtSVMSetAttr(MemoryAddress, SizeInBytes, nattr, attrs); if (r) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS SVMRangeGetPrefetchNode(void *MemoryAddress, HSAuint64 SizeInBytes, HSAuint32 *PrefetchNode) { HSA_SVM_ATTRIBUTE attr; int r; attr.type = HSA_SVM_ATTR_PREFETCH_LOC; attr.value = 0; r = hsaKmtSVMGetAttr(MemoryAddress, SizeInBytes, 1, &attr); if (r) return HSAKMT_STATUS_ERROR; *PrefetchNode = attr.value; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS SVMRangePrefetchToNode(void *MemoryAddress, HSAuint64 SizeInBytes, HSAuint32 PrefetchNode) { HSA_SVM_ATTRIBUTE attr; int r; attr.type = HSA_SVM_ATTR_PREFETCH_LOC; attr.value = PrefetchNode; r = hsaKmtSVMSetAttr(MemoryAddress, SizeInBytes, 1, &attr); if (r) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS SVMRangeMapToNode(void *MemoryAddress, HSAuint64 SizeInBytes, HSAuint32 NodeID) { HSA_SVM_ATTRIBUTE attr; int r; attr.type = HSA_SVM_ATTR_ACCESS; attr.value = NodeID; r = hsaKmtSVMSetAttr(MemoryAddress, SizeInBytes, 1, &attr); if (r) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS SVMRangeMapInPlaceToNode(void *MemoryAddress, HSAuint64 SizeInBytes, HSAuint32 NodeID) { HSA_SVM_ATTRIBUTE attr; int r; attr.type = HSA_SVM_ATTR_ACCESS_IN_PLACE; attr.value = NodeID; r = hsaKmtSVMSetAttr(MemoryAddress, SizeInBytes, 1, &attr); if (r) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } HSAKMT_STATUS SVMRangSetGranularity(void *MemoryAddress, HSAuint64 SizeInBytes, HSAuint32 Granularity) { HSA_SVM_ATTRIBUTE attr; int r; attr.type = HSA_SVM_ATTR_GRANULARITY; attr.value = Granularity; r = hsaKmtSVMSetAttr(MemoryAddress, SizeInBytes, 1, &attr); if (r) return HSAKMT_STATUS_ERROR; return HSAKMT_STATUS_SUCCESS; } HsaSVMRange::HsaSVMRange(HSAuint64 size, HSAuint32 GPUNode) : HsaSVMRange(NULL, size, GPUNode, 0) {} HsaSVMRange::HsaSVMRange(HSAuint64 size) : HsaSVMRange(NULL, size, 0, 0, true) {} HsaSVMRange::HsaSVMRange(HSAuint64 size, HSAuint32 GPUNode, HSAuint32 PrefetchNode) : HsaSVMRange(NULL, size, GPUNode, PrefetchNode) {} HsaSVMRange::HsaSVMRange(void *addr, HSAuint64 size, HSAuint32 GPUNode, HSAuint32 PrefetchNode, bool noRegister, bool isLocal, bool isExec, bool isReadOnly): m_Size(size), m_pUser(addr), m_Local(isLocal), m_Node(PrefetchNode), m_SelfAllocated(false) { if (!m_pUser) { m_pUser = mmap(0, m_Size, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_NE(MAP_FAILED, m_pUser); m_SelfAllocated = true; } if (m_Local) m_Flags = HSA_SVM_FLAG_HOST_ACCESS; else m_Flags = HSA_SVM_FLAG_HOST_ACCESS | HSA_SVM_FLAG_COHERENT; if (isReadOnly) m_Flags |= HSA_SVM_FLAG_GPU_RO; if (isExec) m_Flags |= HSA_SVM_FLAG_GPU_EXEC; if (!noRegister) EXPECT_SUCCESS(RegisterSVMRange(GPUNode, m_pUser, m_Size, PrefetchNode, m_Flags)); } HsaSVMRange::~HsaSVMRange() { if (m_pUser != NULL) { if (m_SelfAllocated) munmap(m_pUser, m_Size); m_pUser = NULL; } } void HsaSVMRange::Fill(HSAuint32 value, HSAuint64 offset, HSAuint64 size) { HSAuint64 i; HSAuint32 *ptr = NULL; size = size ? size : m_Size; EXPECT_EQ((size & (sizeof(HSAuint32) - 1)), 0) << "Not word aligned. Call Fill(unsigned char)"; ASSERT_TRUE(size + offset <= m_Size) << "Buffer Overflow" << std::endl; if (m_pUser != NULL) ptr = reinterpret_cast(reinterpret_cast(m_pUser) + offset); ASSERT_NOTNULL(ptr); for (i = 0; i < size / sizeof(HSAuint32); i++) ptr[i] = value; } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDTestUtil.hpp000066400000000000000000000216751446477712600244620ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD__TEST__UTIL__H__ #define __KFD__TEST__UTIL__H__ #include #include #include "OSWrapper.hpp" #include "GoogleTestExtension.hpp" #include "hsakmt.h" class BaseQueue; #define ARRAY_SIZE(_x) (sizeof(_x)/sizeof(_x[0])) #define ALIGN_UP(x, align) (((uint64_t)(x) + (align) - 1) & ~(uint64_t)((align)-1)) #define CounterToNanoSec(x) ((x) * 1000 / (is_dgpu() ? 27 : 100)) void WaitUntilInput(); HSAKMT_STATUS fscanf_dec(const char *file, uint32_t *num); uint64_t RoundToPowerOf2(uint64_t val); // @brief: waits until the value is written to the buffer or until time out if received through args bool WaitOnValue(const volatile unsigned int *buf, unsigned int value, unsigned int timeOut = g_TestTimeOut); void SplitU64(const HSAuint64 value, unsigned int& rLoPart, unsigned int& rHiPart); bool GetHwCapabilityHWS(); HSAKMT_STATUS CreateQueueTypeEvent(bool ManualReset, bool IsSignaled, unsigned int NodeId, HsaEvent** Event); bool is_dgpu(); bool isTonga(const HsaNodeProperties *props); bool hasPciAtomicsSupport(int node); unsigned int FamilyIdFromNode(const HsaNodeProperties *props); const uint32_t GetGfxVersion(const HsaNodeProperties *props); void GetHwQueueInfo(const HsaNodeProperties *props, unsigned int *p_num_cp_queues, unsigned int *p_num_sdma_engines, unsigned int *p_num_sdma_xgmi_engines, unsigned int *p_num_sdma_queues_per_engine); HSAuint64 GetSystemTickCountInMicroSec(); class HsaMemoryBuffer { public: static const HsaMemoryBuffer Null; public: HsaMemoryBuffer(HSAuint64 size, unsigned int node, bool zero = true, bool isLocal = false, bool isExec = false, bool isScratch = false, bool isReadOnly = false, bool isUncached = false, bool NonPaged = false); HsaMemoryBuffer(void *addr, HSAuint64 size); template RetType As() { return reinterpret_cast(m_pBuf); } template const RetType As() const { return reinterpret_cast(m_pBuf); } /* Fill @size bytes of buffer with @value starting from @offset * If @size is 0, the whole buffer is filled with @value */ void Fill(unsigned char value, HSAuint64 offset = 0, HSAuint64 size = 0); void Fill(HSAuint32 value, HSAuint64 offset = 0, HSAuint64 size = 0); void Fill(int value, HSAuint64 offset = 0, HSAuint64 size = 0) { Fill((HSAuint32)value, offset, size); } void Fill(HSAuint32 value, BaseQueue& baseQueue, HSAuint64 offset = 0, HSAuint64 size = 0); bool IsPattern(HSAuint64 location, HSAuint32 pattern); bool IsPattern(HSAuint64 location, HSAuint32 pattern, BaseQueue& baseQueue, volatile HSAuint32 *tmp); unsigned int Size(); HsaMemFlags Flags(); unsigned int Node() const; int MapMemToNodes(unsigned int *nodes, unsigned int nodes_num); int UnmapMemToNodes(unsigned int *nodes, unsigned int nodes_num); void *GetUserPtr() { return m_pUser; } bool isLocal() { return m_Local; } ~HsaMemoryBuffer(); private: // Disable copy HsaMemoryBuffer(const HsaMemoryBuffer&); const HsaMemoryBuffer& operator=(const HsaMemoryBuffer&); void UnmapAllNodes(); HsaMemoryBuffer(); private: HsaMemFlags m_Flags; HSAuint64 m_Size; void* m_pUser; void* m_pBuf; bool m_Local; unsigned int m_Node; HSAuint64 m_MappedNodes; }; HSAKMT_STATUS RegisterSVMRange(HSAuint32 GPUNode, void *MemoryAddress, HSAuint64 SizeInBytes, HSAuint32 PrefetchNode, HSAuint32 SVMFlags); HSAKMT_STATUS SVMRangeGetPrefetchNode(void *MemoryAddress, HSAuint64 SizeInBytes, HSAuint32 *PrefetchNode); HSAKMT_STATUS SVMRangePrefetchToNode(void *MemoryAddress, HSAuint64 SizeInBytes, HSAuint32 PrefetchNode); HSAKMT_STATUS SVMRangeMapToNode(void *MemoryAddress, HSAuint64 SizeInBytes, HSAuint32 NodeID); HSAKMT_STATUS SVMRangeMapInPlaceToNode(void *MemoryAddress, HSAuint64 SizeInBytes, HSAuint32 NodeID); HSAKMT_STATUS SVMRangSetGranularity(void *MemoryAddress, HSAuint64 SizeInBytes, HSAuint32 Granularity); class HsaSVMRange { public: HsaSVMRange(HSAuint64 size, HSAuint32 GPUNode); HsaSVMRange(HSAuint64 size, HSAuint32 GPUNode, HSAuint32 PreferredNode); HsaSVMRange(HSAuint64 size); HsaSVMRange(void *addr, HSAuint64 size, HSAuint32 GPUNode, HSAuint32 PreferredNode = 0, bool noRegister = false, bool isLocal = false, bool isExec = false, bool isReadOnly = false); template RetType As() { return reinterpret_cast(m_pUser); } template const RetType As() const { return reinterpret_cast(m_pUser); } ~HsaSVMRange(); void Fill(HSAuint32 value, HSAuint64 offset = 0, HSAuint64 size = 0); private: HSAuint32 m_Flags; HSAuint64 m_Size; void* m_pUser; bool m_SelfAllocated; bool m_Local; unsigned int m_Node; }; class HsaInteropMemoryBuffer { public: HsaInteropMemoryBuffer(HSAuint64 device_handle, HSAuint64 buffer_handle, HSAuint64 size, unsigned int node); template RetType As() { return reinterpret_cast(m_pBuf); } template const RetType As() const { return reinterpret_cast(m_pBuf); } unsigned int Size(); ~HsaInteropMemoryBuffer(); private: // Disable copy HsaInteropMemoryBuffer(const HsaInteropMemoryBuffer&); const HsaInteropMemoryBuffer& operator=(const HsaInteropMemoryBuffer&); private: HSAuint64 m_Size; void* m_pBuf; HSAuint64 m_graphic_handle; unsigned int m_Node; }; // @class HsaNodeInfo - Gather and store all HSA node information from Thunk. class HsaNodeInfo { // List containing HsaNodeProperties of all Nodes available std::vector m_HsaNodeProps; // List of HSA Nodes that contain a GPU. This includes both APU and dGPU std::vector m_NodesWithGPU; // List of HSA Nodes with CPU only std::vector m_NodesWithoutGPU; public: HsaNodeInfo(); ~HsaNodeInfo(); bool Init(int NumOfNodes); /* This function should be deprecated soon. This for transistion purpose only * Currently, KfdTest is designed to test only ONE node. This function acts * as transition. */ const HsaNodeProperties* HsaDefaultGPUNodeProperties() const; const int HsaDefaultGPUNode() const; /* TODO: Use the following two functions to support multi-GPU. * const std::vector& GpuNodes = GetNodesWithGPU() * for (..GpuNodes.size()..) GetNodeProperties(GpuNodes.at(i)) */ const std::vector& GetNodesWithGPU() const; // @param node index of the node we are looking at // @param nodeProperties HsaNodeProperties returned const HsaNodeProperties* GetNodeProperties(int NodeNum) const; void PrintNodeInfo() const; const bool IsGPUNodeLargeBar(int node) const; const bool IsAppAPU(int node) const; const bool IsPeerAccessibleByNode(int peer, int node) const; // @brief Find the first available Large-BAR GPU node // @return: Node ID if successful or -1 const int FindLargeBarGPUNode() const; const bool AreGPUNodesXGMI(int node0, int node1) const; int FindAccessiblePeers(std::vector *peers, HSAuint32 node) const; /* @brief: to determine if the node is XGMI-linked to CPU * @param: node index of the node we are looking at * @return: bool true or false */ const bool IsNodeXGMItoCPU(int node) const; }; #endif // __KFD__TEST__UTIL__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDTestUtilQueue.cpp000066400000000000000000000420031446477712600254460ustar00rootroot00000000000000/* * Copyright (C) 2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include #include "SDMAQueue.hpp" #include "PM4Queue.hpp" #include "SDMAPacket.hpp" #include "PM4Packet.hpp" #include "KFDTestUtil.hpp" #include "KFDTestUtilQueue.hpp" #include "KFDBaseComponentTest.hpp" #define MB_PER_SEC(size, time) ((((size) * 1ULL) >> 20) * 1000ULL * 1000ULL * 1000ULL / (time)) class AsyncMPSQ; class AsyncMPMQ; typedef std::shared_ptr sharedAsyncMPSQ; typedef std::list AsyncMPSQList; typedef std::shared_ptr sharedPacket; typedef std::list PacketList; /* AsyncMPSQ is short for Async multiple packet single queue. * It is allowed to place a list of packets to run on one queue of the specified GPU node. */ class AsyncMPSQ { public: AsyncMPSQ() : m_queue(NULL), m_buf(NULL), m_event(NULL) { /*do nothing*/} virtual ~AsyncMPSQ(void) { Destroy(); } /* It is the main function to deal with the packet and queue.*/ void PlacePacketOnNode(PacketList &packetList, int node, TSPattern tsp); /* Run the packets placed on nodes and return immediately.*/ void Submit(void) { ASSERT_NE((HSAuint64)m_queue, NULL); m_queue->SubmitPacket(); } /* Return only when all packets are consumed. * If there is any packet issues some IO operations, wait these IO to complete too. */ void Wait(void) { ASSERT_NE((HSAuint64)m_queue, NULL); m_queue->Wait4PacketConsumption(m_event, std::max((unsigned int)6000, g_TestTimeOut)); } /* Report the time used between packet [begin, end) in Global Counter on success. * Return 0 on failure. */ HSAuint64 Report(int indexOfPacketBegin = 0, int indexOfPacketEnd = 0); /* Report the timestamp around the packet. * Return the time used on success. * Return 0 on failure. */ HSAuint64 Report(int indexOfPacket, HSAuint64 &tsBegin, HSAuint64 &tsEnd); private: BaseQueue *m_queue; HSA_QUEUE_TYPE m_queueType; HsaEvent *m_event; /* m_ts points to m_buf's memory.*/ HsaMemoryBuffer *m_buf; TimeStamp *m_ts; unsigned m_ts_count; TSPattern m_ts_pattern; void AllocTimeStampBuf(int packetCount); void Destroy(); /* It determines which queue will be created.*/ void InitQueueType(PACKETTYPE packetType) { if (packetType == PACKETTYPE_SDMA) m_queueType = HSA_QUEUE_SDMA; else if (packetType == PACKETTYPE_PM4) m_queueType = HSA_QUEUE_COMPUTE; else WARN() << "Unsupported queue type!" << std::endl; } unsigned int TimePacketSize(void) { if (m_queueType == HSA_QUEUE_SDMA) return SDMATimePacket(0).SizeInBytes(); else if (m_queueType == HSA_QUEUE_COMPUTE) return PM4ReleaseMemoryPacket(m_queue->GetFamilyId(), 0, 0, 0, 0, 0).SizeInBytes(); return 0; } void CreateNewQueue(int node, unsigned int queueSize) { if (m_queueType == HSA_QUEUE_SDMA) m_queue = new SDMAQueue(); else if (m_queueType == HSA_QUEUE_COMPUTE) m_queue = new PM4Queue(); else { m_queue = NULL; WARN() << "Unsupported queue type!" << std::endl; } if (m_queue) ASSERT_SUCCESS(m_queue->Create(node, queueSize)); } void PlaceTimestampPacket(void *addr) { if (m_queueType == HSA_QUEUE_SDMA) PlacePacket(SDMATimePacket(addr)); else if (m_queueType == HSA_QUEUE_COMPUTE) PlacePacket( PM4ReleaseMemoryPacket(m_queue->GetFamilyId(), true, (HSAuint64)addr, 0, true, true)); else WARN() << "Unsupported queue type!" << std::endl; } void PlacePacket(const BasePacket &packet) { m_queue->PlacePacket(packet); } }; void AsyncMPSQ::Destroy(void) { /* Delete queue first.*/ if (m_queue) { delete m_queue; } if (m_buf) delete m_buf; if (m_event) hsaKmtDestroyEvent(m_event); } void AsyncMPSQ::AllocTimeStampBuf(int packetCount) { if (m_ts_pattern == NOTS) { m_buf = NULL; m_ts = NULL; m_ts_count = 0; return; } if (m_ts_pattern == ALLTS) /* One extra timestamp packet.*/ m_ts_count = packetCount + 1; else m_ts_count = 2; /* One more timestamp space to fit with alignment.*/ HSAuint64 size = ALIGN_UP(sizeof(TimeStamp) * (m_ts_count + 1), PAGE_SIZE); m_buf = new HsaMemoryBuffer(size, 0, true, false); TimeStamp *array = m_buf->As(); /* SDMATimePacket need 32bytes aligned boundary dst address*/ m_ts = reinterpret_castALIGN_UP(array, sizeof(TimeStamp)); } void AsyncMPSQ::PlacePacketOnNode(PacketList &packets, int node, TSPattern tsp = ALLTS) { int nPacket = packets.size(); if (nPacket == 0) { WARN() << "Empty packetList!" << std::endl; return; } /*1: All resources should be freed.*/ Destroy(); /*2: Must initialize queueType first.*/ InitQueueType(packets.front()->PacketType()); /*3: Initialize timestamp buf second with the pattern.*/ m_ts_pattern = tsp; AllocTimeStampBuf(nPacket); /*4: Create a event for Wait().*/ CreateQueueTypeEvent(false, false, node, &m_event); int i = -1; int packetSize = 0; /* Calculate the space to put all timestamp packet.*/ int timePacketSize = TimePacketSize() * m_ts_count; /* Another one page space to put fence, trap, etc*/ int extraPacketSize = PAGE_SIZE + timePacketSize; /* To calculate the total packet size we will need to create the queue. * As the packet in the vector might be different with each other, * we have no other way to calculate the queuesize. */ for (auto &packet : packets) packetSize += packet->SizeInBytes(); /* queueSize need be power of 2.*/ const int queueSize = RoundToPowerOf2(packetSize + extraPacketSize); /*5: Create a new queue on node for the packets.*/ CreateNewQueue(node, queueSize); if (tsp != NOTS) { i++; PlaceTimestampPacket(m_ts + i); } for (auto &packet : packets) { PlacePacket(*packet); if (tsp == ALLTS) { i++; PlaceTimestampPacket(m_ts + i); } } if (tsp == HEAD_TAIL) { i++; PlaceTimestampPacket(m_ts + i); } ASSERT_EQ(i + 1, m_ts_count); } HSAuint64 AsyncMPSQ::Report(int indexOfPacket, HSAuint64 &begin, HSAuint64 &end) { /* Should not get any timestamp if NOTS is specified.*/ int error = 0; EXPECT_NE(m_ts_pattern, NOTS) << " Error " << ++error << ": No timestamp would be reported!" << std::endl; if (m_ts_pattern == HEAD_TAIL) indexOfPacket = 0; EXPECT_NE((HSAuint64)m_ts, NULL) << " Error " << ++error << ": No timestamp buf!" << std::endl; /* m_ts_count is equal to packets count + 1, see PlacePacketOnNode(). * So the max index of a packet is m_ts_count - 2. * make it unsigned to defend any minus values. */ EXPECT_GE(m_ts_count - 2, (unsigned)indexOfPacket) << " Error " << ++error << ": Index overflow!" << std::endl; if (error) return 0; begin = m_ts[indexOfPacket].timestamp; end = m_ts[indexOfPacket + 1].timestamp; return end - begin; } HSAuint64 AsyncMPSQ::Report(int indexOfPacketBegin, int indexOfPacketEnd) { HSAuint64 ts[4]; int error = 0; if (indexOfPacketEnd == 0) indexOfPacketEnd = m_ts_count - 1; EXPECT_GT((unsigned)indexOfPacketEnd, (unsigned)indexOfPacketBegin) << " Error " << ++error << ": Index inverted!" << std::endl; if (error) return 0; /* Get the timestamps around the two packets.*/ if (!Report(indexOfPacketBegin, ts[0], ts[1])) return 0; /* [begin, end)*/ if (!Report(indexOfPacketEnd - 1, ts[2], ts[3])) return 0; EXPECT_GT(ts[3], ts[0]) << " Waring: Might be wrong timestamp values!" << std::endl; return ts[3] - ts[0]; } /* AsyncMPMQ is short for Async multiple packet multiple queue. * AsyncMPMQ manages a list of AsyncMPSQ. * So the packet can be running on multiple GPU nodes at same time. */ class AsyncMPMQ { public: AsyncMPMQ(void) { /* do nothing*/} virtual ~AsyncMPMQ(void) { /*do nothing*/} sharedAsyncMPSQ PlacePacketOnNode(PacketList &packetList, int node, TSPattern tsp = ALLTS) { /* Create a sharedAsyncMPSQ object and push it into the AsyncMPSQList. * As we might submit packet to same GPU nodes several times, AsyncMPSQ * * is returned to stand for the AsyncMPSQ it is created with */ sharedAsyncMPSQ mpsq_ptr(new AsyncMPSQ); mpsq_ptr->PlacePacketOnNode(packetList, node, tsp); m_mpsqList.push_back(mpsq_ptr); return mpsq_ptr; } void Submit(void) { for (auto &mpsq : m_mpsqList) mpsq->Submit(); } void Wait(void) { for (auto &mpsq : m_mpsqList) mpsq->Wait(); } private: AsyncMPSQList m_mpsqList; }; /* * SDMA queue helper functions. */ bool sort_SDMACopyParams(const SDMACopyParams &a1, const SDMACopyParams &a2) { if (a1.node != a2.node) return a1.node < a2.node; return a1.group < a2.group; } /* * Copy from src to dst with corresponding sDMA. * It will try to merge copy on same node into one queue unless * caller forbid it by setting mashup to 0 and SDMACopyParams::group to different values. * On condition of mashup is 1, it will re-sort array into mergeable state. * All mergeable copy will be placed together. * On condition os mashup is 0, it keeps array in original order. * It will merge nearby copy if they have same group and node anyway. */ void sdma_multicopy(std::vector &array, int mashup, TSPattern tsp) { int i, packet_index = 0, queue_index = 0; PacketList packetList; AsyncMPMQ obj; std::vector handle; /* Sort it and then reduce the amount of queues if caller permits. * We might change the order of array only here. */ if (mashup) std::sort(array.begin(), array.end(), sort_SDMACopyParams); for (i = 0; i < array.size(); i++) { sharedPacket packet(new SDMACopyDataPacket(g_baseTest->GetFamilyIdFromNodeId(array[i].node), array[i].dst, array[i].src, array[i].size)); packetList.push_back(packet); /* We put the real queue_id in local handle[] to reduce some assignment.*/ array[i].queue_id = queue_index; /* Every queue has its packets with the index starts from 0.*/ array[i].packet_id = packet_index++; /* If next copy is on same node and group, try to merge it into same queue.*/ if (i + 1 < array.size() && array[i].node == array[i + 1].node && array[i].group == array[i + 1].group) continue; /* Now we have prepare one packetList, place packet into the queue on GPU node.*/ queue_index++; handle.push_back(obj.PlacePacketOnNode(packetList, array[i].node, tsp)); /* Prepare a new(empty) packetList.*/ packetList.clear(); /* Prepare a new(zero) packet index for the packets in the new queue.*/ packet_index = 0; } obj.Submit(); obj.Wait(); if (tsp == NOTS) return; /* Get the time used by packet.*/ for (i = 0; i < array.size(); i++) array[i].timeConsumption = (handle[array[i].queue_id])->Report( array[i].packet_id, array[i].timeBegin, array[i].timeEnd); } static void sdma_multicopy_report(std::vector &array, HSAuint64 countPerGroup, std::stringstream *msg, HSAuint64 &timeConsumptionMin, HSAuint64 &timeConsumptionMax, HSAuint64 &totalSizeMin, HSAuint64 &totalSizeMax) { HSAuint64 begin, end; /* There can be different count of copies in different groups in the future. * But assume they are same now. */ HSAuint64 group = array.size() / countPerGroup; HSAuint64 interval = -1; timeConsumptionMin = -1; timeConsumptionMax = 0; totalSizeMin = totalSizeMax = 0; /* Try to find out * 1) The max/min timeConsumption of one copy in all copies. * 2) The minimal average of timeConsumption of one packet in all copies. * And one char # or - stands for one interval, aka minimal average. * Say, one copy use 10ns with 10 copy packets. the other copy use 20ns * with 10 copy packets. So the interval is 1ns, the timeConsumption is 20ns. * So the ouput msg will be like * ########## //copy1 10ns * #---##----####### //copy2 20ns */ for (int i = 0; i < group; i++) { HSAuint64 begin, end, base = i * countPerGroup; begin = array[base].timeBegin; end = array[base + countPerGroup - 1].timeEnd; if (begin == 0 && end == 0) continue; if (timeConsumptionMax < end - begin) timeConsumptionMax = end - begin; if (timeConsumptionMin > end - begin) timeConsumptionMin = end - begin; } interval = timeConsumptionMin / countPerGroup; /* Draw the timestamp event for each copy list. * - means still doing copy. * # means just finish one copy. */ if (msg) for (int i = 0; i < group; i++) { HSAuint64 base = i * countPerGroup; HSAuint64 last = array[base].timeBegin; HSAuint64 timeConsumption; *msg << "[" << array[base].node << " : " << array[base].group << "] "; for (int j = 0; j < countPerGroup; j++) { timeConsumption = array[base + j].timeEnd - last; while (timeConsumption >= interval) { timeConsumption -= interval; last += interval; if (timeConsumption >= interval) *msg << "-"; else *msg << "#"; }; } *msg << std::endl; } /* Try to find out * 1) The size of all copies in all queues. * 2) The size of the copies running within the same period in all queues. * We assume all packets begin to run at same time. */ for (int i = 0; i < group; i++) { HSAuint64 base = i * countPerGroup; HSAuint64 time = 0; for (int j = 0; j < countPerGroup; j++) { totalSizeMax += array[base + j].size; if (time < timeConsumptionMin) { time += array[base + j].timeConsumption; totalSizeMin += array[base + j].size; } } } } /* * Do copy with corresponding sDMA. */ void sdma_multicopy(SDMACopyParams *copyArray, int arrayCount, HSAuint64 *minSpeed, HSAuint64 *maxSpeed, std::stringstream *msg) { const HSAuint64 countPerGroup = minSpeed || maxSpeed ? 100 : 1; std::vector array; HSAuint64 totalSizeMin, totalSizeMax, timeConsumptionMin, timeConsumptionMax; for (int i = 0; i < arrayCount; i++) { /* Each copy has its own queue.*/ copyArray[i].group = i; for (int j = 0; j < countPerGroup; j++) array.push_back(copyArray[i]); } sdma_multicopy(array, 0, ALLTS); sdma_multicopy_report(array, countPerGroup, msg, timeConsumptionMin, timeConsumptionMax, totalSizeMin, totalSizeMax); if (minSpeed) *minSpeed = MB_PER_SEC(totalSizeMin, CounterToNanoSec(timeConsumptionMin)); if (maxSpeed) *maxSpeed = MB_PER_SEC(totalSizeMax, CounterToNanoSec(timeConsumptionMax)); } /* * PM4 queue helper functions. */ // TODO ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDTestUtilQueue.hpp000066400000000000000000000050151446477712600254550ustar00rootroot00000000000000/* * Copyright (C) 2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD__TEST__UTIL__QUEUE__H__ #define __KFD__TEST__UTIL__QUEUE__H__ #include "hsakmt.h" #include typedef struct { HSAuint64 timestamp; HSAuint64 timeConsumption; HSAuint64 timeBegin; HSAuint64 timeEnd; } TimeStamp; /* We have three pattern to put timestamp packet, * NOTS: No timestamp packet insert. * ALLTS: Put timestamp packet around every packet. This is the default behavoir. * It will look like |timestamp|packet|timestamp|...|packet|timestamp| * HEAD_TAIL: Put timestmap packet at head and tail to measure the overhead of a bunch of packet. * It will look like |timestamp|packet|...|packet|timestamp| */ typedef enum { NOTS = 0, ALLTS = 1, HEAD_TAIL = 2, } TSPattern; typedef struct { /* input values*/ HSAuint32 node; void *src; void *dst; HSAuint64 size; /* input value for internal use.*/ HSAuint64 group; /* output value*/ HSAuint64 timeConsumption; HSAuint64 timeBegin; HSAuint64 timeEnd; /* private: Output values for internal use.*/ HSAuint64 queue_id; HSAuint64 packet_id; } SDMACopyParams; void sdma_multicopy(SDMACopyParams *array, int n, HSAuint64 *speedSmall = 0, HSAuint64 *speedLarge = 0, std::stringstream *s = 0); void sdma_multicopy(std::vector &array, int mashup = 1, TSPattern tsp = ALLTS); #endif //__KFD__TEST__UTIL__QUEUE__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDTopologyTest.cpp000066400000000000000000000273641446477712600253550ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDTopologyTest.hpp" #include #include const HSAuint64 KFDTopologyTest::c_4Gigabyte = (1ull << 32) - 1; const HSAuint64 KFDTopologyTest::c_40BitAddressSpace = (1ull << 40); TEST_F(KFDTopologyTest , BasicTest) { TEST_START(TESTPROFILE_RUNALL) const HsaNodeProperties *pNodeProperties; // Goes over all nodes in the sytem properties and check the basic info received for (unsigned node = 0; node < m_SystemProperties.NumNodes; node++) { pNodeProperties = m_NodeInfo.GetNodeProperties(node); if (pNodeProperties != NULL) { HSAuint64 uniqueid; if (!pNodeProperties->UniqueID) uniqueid = 0; else uniqueid = pNodeProperties->UniqueID; LOG() << "UniqueID : " << std::dec << uniqueid << " Node index: " << node << std::endl; // Checking for cpu core only if it's a cpu only node or if its KAVERI apu. if (pNodeProperties->DeviceId == 0 || FamilyIdFromNode(pNodeProperties) == FAMILY_KV) { EXPECT_GT(pNodeProperties->NumCPUCores, HSAuint32(0)) << "Node index: " << node << " No CPUs core are connected for node index"; } // If it's not a cpu only node, look for a gpu core if (pNodeProperties->DeviceId != 0) { EXPECT_GT(pNodeProperties->NumFComputeCores, HSAuint32(0)) << "Node index: " << node << "No GPUs core are connected."; // EngineId only applies to GPU, not CPU-only nodes EXPECT_GT(pNodeProperties->EngineId.ui32.uCode, 0) << "uCode version is 0"; EXPECT_GE(pNodeProperties->EngineId.ui32.Major, 7) << "Major Version is less than 7"; EXPECT_LT(pNodeProperties->EngineId.ui32.Minor, 10) << "Minor Version is greater than 9"; EXPECT_GT(pNodeProperties->uCodeEngineVersions.uCodeSDMA, 0) << "sDMA firmware version is 0"; LOG() << "VGPR Size is " << pNodeProperties->VGPRSizePerCU << " SGPR Size is " << pNodeProperties->SGPRSizePerCU << std::endl; } EXPECT_GT(pNodeProperties->NumMemoryBanks, HSAuint32(0)) << "Node index: " << node << "No MemoryBanks."; EXPECT_GT(pNodeProperties->NumCaches, HSAuint32(0)) << "Node index: " << node << "No Caches."; } } TEST_END } // This test verifies failure status on hsaKmtGetNodeProperties with invalid params TEST_F(KFDTopologyTest, GetNodePropertiesInvalidParams) { TEST_START(TESTPROFILE_RUNALL) EXPECT_EQ(HSAKMT_STATUS_INVALID_PARAMETER, hsaKmtGetNodeProperties(0, NULL)); TEST_END } // This test verifies failure status on hsaKmtGetNodeProperties with invalid params TEST_F(KFDTopologyTest, GetNodePropertiesInvalidNodeNum) { TEST_START(TESTPROFILE_RUNALL) HsaNodeProperties nodeProperties; memset(&nodeProperties, 0, sizeof(nodeProperties)); EXPECT_EQ(HSAKMT_STATUS_INVALID_NODE_UNIT, hsaKmtGetNodeProperties(m_SystemProperties.NumNodes, &nodeProperties)); TEST_END } // Test that we can get memory properties successfully per node // TODO: Check validity of values returned TEST_F(KFDTopologyTest, GetNodeMemoryProperties) { TEST_START(TESTPROFILE_RUNALL) const HsaNodeProperties *pNodeProperties; for (unsigned node = 0; node < m_SystemProperties.NumNodes; node++) { pNodeProperties = m_NodeInfo.GetNodeProperties(node); if (pNodeProperties != NULL) { HsaMemoryProperties *memoryProperties = new HsaMemoryProperties[pNodeProperties->NumMemoryBanks]; EXPECT_SUCCESS(hsaKmtGetNodeMemoryProperties(node, pNodeProperties->NumMemoryBanks, memoryProperties)); delete [] memoryProperties; } } TEST_END } // Test that the GPU local memory aperture is valid. TEST_F(KFDTopologyTest, GpuvmApertureValidate) { TEST_REQUIRE_NO_ENV_CAPABILITIES(ENVCAPS_32BITLINUX); TEST_START(TESTPROFILE_RUNALL) const HsaNodeProperties *pNodeProperties; const std::vector GpuNodes = m_NodeInfo.GetNodesWithGPU(); for (unsigned i = 0; i < GpuNodes.size(); i++) { pNodeProperties = m_NodeInfo.GetNodeProperties(GpuNodes.at(i)); if (pNodeProperties != NULL) { if (!is_dgpu() && !(FamilyIdFromNode(pNodeProperties) == FAMILY_KV)) { LOG() << "Skipping test: GPUVM framebuffer heap not exposed on APU except Kaveri." << std::endl; return; } HsaMemoryProperties *memoryProperties = new HsaMemoryProperties[pNodeProperties->NumMemoryBanks]; EXPECT_SUCCESS(hsaKmtGetNodeMemoryProperties(GpuNodes.at(i), pNodeProperties->NumMemoryBanks, memoryProperties)); bool GpuVMHeapFound = false; for (unsigned int bank = 0 ; bank < pNodeProperties->NumMemoryBanks ; bank++) { // Check for either private (small-bar/APU) or public (large-bar) if ((HSA_HEAPTYPE_FRAME_BUFFER_PRIVATE == memoryProperties[bank].HeapType) || (HSA_HEAPTYPE_FRAME_BUFFER_PUBLIC == memoryProperties[bank].HeapType)) GpuVMHeapFound = true; } EXPECT_TRUE(GpuVMHeapFound); delete [] memoryProperties; } } TEST_END } // Test that we can get cache property successfully per node // TODO: Check validity of values returned TEST_F(KFDTopologyTest, GetNodeCacheProperties) { TEST_START(TESTPROFILE_RUNALL) const HsaNodeProperties *pNodeProperties; for (unsigned node = 0; node < m_SystemProperties.NumNodes; node++) { pNodeProperties = m_NodeInfo.GetNodeProperties(node); if (pNodeProperties != NULL) { HsaCacheProperties *cacheProperties = new HsaCacheProperties[pNodeProperties->NumCaches]; EXPECT_SUCCESS(hsaKmtGetNodeCacheProperties(node, pNodeProperties->CComputeIdLo, pNodeProperties->NumCaches, cacheProperties)); if (pNodeProperties->NumCPUCores > 0) { // this is a CPU node LOG() << "CPU Node " << std::dec << node << ": " << pNodeProperties->NumCaches << " caches" << std::endl; for (unsigned n = 0; n < pNodeProperties->NumCaches; n++) { LOG()<< n << " - Level " << cacheProperties[n].CacheLevel << " Type " << cacheProperties[n].CacheType.Value << " Size " << (cacheProperties[n].CacheSize >> 10) << "K " << " Associativity " << cacheProperties[n].CacheAssociativity << " LineSize " << cacheProperties[n].CacheLineSize << " LinesPerTag " << cacheProperties[n].CacheLinesPerTag << std::endl; char string[1024] = ""; char sibling[5] = ""; for (unsigned i = 0; i < 256; i++) { if (cacheProperties[n].SiblingMap[i]) { sprintf(sibling, "%d,", i); strcat(string, sibling); } } LOG() << " ProcIdLow " << cacheProperties[n].ProcessorIdLow << " SiblingMap " << string << std::endl; } } else { // this is a GPU node LOG() << "GPU Node " << std::dec << node << ": " << pNodeProperties->NumCaches << " caches" << std::endl; for (unsigned n = 0; n < pNodeProperties->NumCaches; n++) { LOG()<< n << " - Level " << cacheProperties[n].CacheLevel << " Type " << cacheProperties[n].CacheType.Value << " Size " << cacheProperties[n].CacheSize << "K " << " Associativity " << cacheProperties[n].CacheAssociativity << " LineSize " << cacheProperties[n].CacheLineSize << " LinesPerTag " << cacheProperties[n].CacheLinesPerTag << std::endl; char string[1024] = ""; char sibling[5] = ""; for (unsigned i = 0; i < 256; i++) { if (cacheProperties[n].SiblingMap[i]) { snprintf(sibling, 5, "%d,", i); strcat(string, sibling); } } LOG() << " ProcIdLow " << cacheProperties[n].ProcessorIdLow << " SiblingMap " << string << std::endl; } } delete [] cacheProperties; } } TEST_END } // Test that we can get NodeIoLink property successfully per node // TODO: Check validity of values returned // GetNodeIoLinkProperties is disabled for now, test fails due to bug in BIOS TEST_F(KFDTopologyTest, GetNodeIoLinkProperties) { TEST_START(TESTPROFILE_RUNALL) const HsaNodeProperties *pNodeProperties; int linkId; char c; LOG() << "Topology. [FromNode]--(Weight)-->[ToNode]" << std::endl; for (unsigned node = 0; node < m_SystemProperties.NumNodes; node++) { pNodeProperties = m_NodeInfo.GetNodeProperties(node); if (pNodeProperties != NULL) { HsaIoLinkProperties *IolinkProperties = new HsaIoLinkProperties[pNodeProperties->NumIOLinks]; EXPECT_SUCCESS(hsaKmtGetNodeIoLinkProperties(node, pNodeProperties->NumIOLinks, IolinkProperties)); if (pNodeProperties->NumIOLinks == 0) { // No io_links. Just print the node LOG() << "[" << node << "]" << std::endl; continue; } for (linkId = 0; linkId < pNodeProperties->NumIOLinks; linkId++) { if (linkId == 0) { // First io_link. Print Parent Node and io_link Node EXPECT_EQ(node, IolinkProperties[linkId].NodeFrom); LOG() << "[" << IolinkProperties[linkId].NodeFrom << "]--(" << IolinkProperties[linkId].Weight << ")-->" << "[" << IolinkProperties[linkId].NodeTo << "]" << std::endl; continue; } if (linkId == (pNodeProperties->NumIOLinks - 1)) c = '`'; // last node else c = '|'; LOG() << " " << c << "--(" << IolinkProperties[linkId].Weight << ")-->" << "[" << IolinkProperties[linkId].NodeTo << "]" << std::endl; } LOG() << std::endl; delete [] IolinkProperties; } } TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/KFDTopologyTest.hpp000066400000000000000000000032331446477712600253470ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "KFDBaseComponentTest.hpp" #ifndef __KFD_TOPOLOGY_TEST__H__ #define __KFD_TOPOLOGY_TEST__H__ /* @class KFDTopologyTest * This class has no additional features to KFDBaseComponentTest * The separation was made so we are able to group all topology tests together */ class KFDTopologyTest : public KFDBaseComponentTest { public: KFDTopologyTest(void) {} ~KFDTopologyTest(void) {} static const HSAuint64 c_4Gigabyte; static const HSAuint64 c_40BitAddressSpace; }; #endif // __KFD_TOPOLOGY_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/LinuxOSWrapper.cpp000066400000000000000000000157601446477712600252530ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef WIN32 #include "OSWrapper.hpp" #include #include #include #include #include #include #include #include #include #include #include #include #include #include static int protection_flags[8] = {PROT_NONE, PROT_READ, PROT_WRITE, PROT_READ | PROT_WRITE, PROT_EXEC, PROT_EXEC | PROT_READ, PROT_EXEC | PROT_WRITE, PROT_EXEC | PROT_WRITE | PROT_READ}; void SetConsoleTextColor(TEXTCOLOR color) { // TODO: Complete } void Delay(int delayCount) { // usleep accepts time in microseconds usleep(delayCount * 1000); } void *VirtualAllocMemory(void *address, unsigned int size, int memProtection ) { void *ptr; ptr = mmap(address, size, protection_flags[memProtection], MAP_PRIVATE|MAP_ANONYMOUS, -1, 0); if (ptr == MAP_FAILED) ptr = NULL; return ptr; } bool VirtualFreeMemory(void *address, unsigned int size) { if (munmap(address, size) == 0) return true; else return false; } HSAuint64 GetLastErrorNo() { return errno; } bool MultiProcessTest(const char *testToRun, int numOfProcesses, int runsPerProcess) { // TODO: Implement return false; } bool SuspendAndWakeUp() { printf("Please press any key after the system suspends....\n"); // Use "sudo apt install pm-utils" to install the "pm-suspend" int ret = system("sudo pm-suspend"); if (ret == -1) { printf("The system linux command could not be run!\n"); return false; } else { if (WEXITSTATUS(ret)) { printf("Use 'sudo apt install pm-utils' to install 'pm-suspend' on Ubuntu\n"); return false; } } return true; } bool ReadDriverConfigValue(CONFIG_VALUE config, unsigned int& rValue) { return false; } void ComandLineArgumentsUsage() { printf("Invalid option value\n"); printf("\t--hws arg\t - Force HW capability\n"); printf("\t--profile arg\t - Test profile\n"); printf("\t--child arg\t - Child Process\n"); printf("\t--timeout arg\t - Time Out\n"); printf("\t--dst_node\t - For testing multiple nodes"); printf("\t--sleep_time\t - For testing CRIU, etc"); } bool GetCommandLineArguments(int argc, char **argv, CommandLineArguments& rArgs) { int option_index = 0; /* Make getop silent */ opterr = 0; static struct option long_options[] = { { "hws", required_argument, 0, 0 }, { "profile", required_argument, 0, 0}, { "child", required_argument, 0, 0}, { "timeout", required_argument, 0, 0}, { "node", required_argument, 0, 0 }, { "dst_node", required_argument, 0, 0 }, { "sleep_time", required_argument, 0, 0 }, { 0, 0, 0, 0 } }; rArgs.HwsEnabled = HWCAP__DEFAULT; rArgs.TestProfile = TESTPROFILE_RUNALL; rArgs.ChildProcess = false; rArgs.TimeOut = 0; rArgs.NodeId = -1; rArgs.DstNodeId = -1; rArgs.SleepTime = 0; while (true) { int c = getopt_long(argc, argv, "", long_options, &option_index); /* Detect the end of the options. */ if (c != 0) break; /* If this option sets a flag, do nothing else. */ if (long_options[option_index].flag != 0) continue; if (optarg == NULL) { ComandLineArgumentsUsage(); return false; } switch (option_index) { /* HWS case */ case 0: if (!strcmp(optarg, "disable")) { rArgs.HwsEnabled = HWCAP__FORCE_DISABLED; } else if (!strcmp(optarg, "enable")) { rArgs.HwsEnabled = HWCAP__FORCE_ENABLED; } else { ComandLineArgumentsUsage(); return false; } break; /* TEST PROFILE */ case 1: if (!strcmp(optarg, "dev")) { rArgs.TestProfile = TESTPROFILE_DEV; } else if (!strcmp(optarg, "promo")) { rArgs.TestProfile = TESTPROFILE_PROMO; } else if (!strcmp(optarg, "all")) { rArgs.TestProfile = TESTPROFILE_RUNALL; } else { ComandLineArgumentsUsage(); return false; } break; case 2: rArgs.ChildProcess = true; break; case 3: { int timeOut = atoi(optarg); if (timeOut > 0) rArgs.TimeOut = timeOut; } break; case 4: { int nodeId = atoi(optarg); if (nodeId >= 0) rArgs.NodeId = nodeId; } break; case 5: { int dstNodeId = atoi(optarg); if (dstNodeId >= 0) rArgs.DstNodeId = dstNodeId; } break; /* Sleep time - used in testing CRIU */ case 6: { int sleepTime = atoi(optarg); if (sleepTime >= 0) rArgs.SleepTime = sleepTime; } break; } } return true; } void HWMemoryBarrier() { __sync_synchronize(); } bool StartThread(unsigned int (*thread_func)(void*), void* param, uint64_t& thread_id) { pthread_t id; bool ret = false; typedef void* (*pthread_func_t)(void*); if (!pthread_create(&id, NULL, (pthread_func_t)thread_func, param)) { thread_id = (pthread_t)id; ret = true; } return ret; } bool WaitForThread(uint64_t threadId) { return 0 == pthread_join((pthread_t)threadId, NULL); } HSAint64 AtomicInc(volatile HSAint64* pValue) { return __sync_add_and_fetch(pValue, 1); } void MemoryBarrier() { __sync_synchronize(); } #endif // !WIN32 ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/OSWrapper.hpp000066400000000000000000000071271446477712600242360ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include "KFDTestFlags.hpp" #include "hsakmt.h" #ifndef __OS__WRAPPER__H__ #define __OS__WRAPPER__H__ #ifndef PAGE_SIZE #define PAGE_SIZE (1<<12) #define PAGE_SHIFT (12) #endif enum TEXTCOLOR { TEXTCOLOR_WHITE, TEXTCOLOR_GREEN, TEXTCOLOR_YELLOW }; enum OS_PRIVILEGE { OS_DRIVER_OPERATIONS, OS_SUSPEND }; enum CONFIG_VALUE { CONFIG_HWS }; enum HwCapabilityStatus { HWCAP__FORCE_DISABLED, HWCAP__DEFAULT, HWCAP__FORCE_ENABLED }; struct CommandLineArguments { HwCapabilityStatus HwsEnabled; TESTPROFILE TestProfile; bool ChildProcess; unsigned int TimeOut; int NodeId; int DstNodeId; /* Time in units of seconds */ unsigned int SleepTime; }; // It is either MEM_NONE or the bitwise OR of one or more of the following flags #define MEM_NONE 0x00 #define MEM_READ 0x01 #define MEM_WRITE 0x02 #define MEM_EXECUTE 0x4 // @brief Change console text color void SetConsoleTextColor(TEXTCOLOR color); // @params delayCount : delay time in milliseconds void Delay(int delayCount); // @brief Replacement for windows VirtualAlloc func void *VirtualAllocMemory(void *address, unsigned int size, int memProtection = MEM_READ | MEM_WRITE); // @brief Replacement for windows FreeVirtual func bool VirtualFreeMemory(void *address, unsigned int size); // @brief Retrieve the last error number HSAuint64 GetLastErrorNo(); HSAint64 AtomicInc(volatile HSAint64* pValue); void MemoryBarrier(); /* @brief: Runs the selected test case number of times required, each in a separate process * @params testToRun : Can be a specific test testcase like TestCase.TestName or if you want * to run all tests in a test case: TestCase.* and so on * @params numOfProcesses : How many processes to run in parallel * @params runsPerProcess : How many iteration a test should do per process, must be a positive number */ bool MultiProcessTest(const char *testToRun, int numOfProcesses, int runsPerProcess = 1); /* Put the system to S3/S4 power state and bring it back to S0. * @return 'true' on success, 'false' on failure. */ bool SuspendAndWakeUp(); bool ReadDriverConfigValue(CONFIG_VALUE config, unsigned int& rValue); bool GetCommandLineArguments(int argc, char **argv, CommandLineArguments& rArgs); void HWMemoryBarrier(); bool StartThread(unsigned int (*)(void*), void* pParam, uint64_t& threadId); bool WaitForThread(uint64_t threadId); #endif // __OS__WRAPPER__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/PM4Packet.cpp000066400000000000000000000423161446477712600240760ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include "PM4Packet.hpp" #include "hsakmttypes.h" #include "KFDBaseComponentTest.hpp" #include "asic_reg/gfx_7_2_enum.h" unsigned int PM4Packet::CalcCountValue() const { return (SizeInDWords() - (sizeof(PM4_TYPE_3_HEADER) / sizeof(uint32_t)) - 1); } void PM4Packet::InitPM4Header(PM4_TYPE_3_HEADER &header, it_opcode_type opCode) { header.count = CalcCountValue(); header.opcode = opCode; header.type = PM4_TYPE_3; header.shaderType = 1; // compute header.predicate = 0; header.reserved1 = 0; } unsigned int PM4WriteDataPacket::SizeInBytes() const { return (offsetof(PM4WRITE_DATA_CI, data) + m_ndw*sizeof(uint32_t)); } void PM4WriteDataPacket::InitPacket(unsigned int *destBuf, void *data) { m_pPacketData = reinterpret_cast(AllocPacket()); InitPM4Header(m_pPacketData->header, IT_WRITE_DATA); m_pPacketData->bitfields2.dst_sel = dst_sel_mec_write_data_MEMORY_5; // memory-async m_pPacketData->bitfields2.addr_incr = addr_incr_mec_write_data_INCREMENT_ADDR_0; // increment addr m_pPacketData->bitfields2.wr_confirm = wr_confirm_mec_write_data_WAIT_FOR_CONFIRMATION_1; m_pPacketData->bitfields2.atc = is_dgpu() ? atc_write_data_NOT_USE_ATC_0 : atc_write_data_USE_ATC_1; m_pPacketData->bitfields2.cache_policy = cache_policy_mec_write_data_BYPASS_2; m_pPacketData->dst_addr_lo = static_cast( reinterpret_cast(destBuf)); // byte addr m_pPacketData->dst_address_hi = static_cast( reinterpret_cast(destBuf) >> 32); memcpy(m_pPacketData->data, data, m_ndw * sizeof(uint32_t)); } PM4ReleaseMemoryPacket::PM4ReleaseMemoryPacket(unsigned int familyId, bool isPolling, uint64_t address, uint64_t data, bool is64bit, bool isTimeStamp):m_pPacketData(NULL) { m_FamilyId = familyId; if (familyId < FAMILY_AI) InitPacketCI(isPolling, address, data, is64bit, isTimeStamp); else if (familyId < FAMILY_NV) InitPacketAI(isPolling, address, data, is64bit, isTimeStamp); else InitPacketNV(isPolling, address, data, is64bit, isTimeStamp); } void PM4ReleaseMemoryPacket::InitPacketCI(bool isPolling, uint64_t address, uint64_t data, bool is64bit, bool isTimeStamp) { PM4_RELEASE_MEM_CI *pkt; m_packetSize = sizeof(PM4_RELEASE_MEM_CI); pkt = reinterpret_cast(AllocPacket()); m_pPacketData = pkt; InitPM4Header(pkt->header, IT_RELEASE_MEM); pkt->bitfields2.event_type = 0x14; pkt->bitfields2.event_index = event_index_mec_release_mem_EVENT_WRITE_EOP_5; // Possible values: // 0101(5): EVENT_WRITE_EOP event types // 0110(6): Reserved for EVENT_WRITE_EOS packet. // 0111(7): Reserved (previously) for EVENT_WRITE packet. pkt->bitfields2.l2_wb = 1; pkt->bitfields2.l2_inv = 1; pkt->bitfields2.cache_policy = cache_policy_mec_release_mem_BYPASS_2; pkt->bitfields2.atc = is_dgpu() ? atc_mec_release_mem_ci_NOT_USE_ATC_0 : atc_mec_release_mem_ci_USE_ATC_1; // ATC setting for fences and timestamps to the MC or TCL2. pkt->bitfields3.dst_sel = dst_sel_mec_release_mem_MEMORY_CONTROLLER_0; // Possible values: // 0 - memory_controller. // 1 - tc_l2. if (address) { pkt->bitfields3.int_sel = (isPolling ? int_sel_mec_release_mem_SEND_DATA_AFTER_WRITE_CONFIRM_3 : int_sel_mec_release_mem_SEND_INTERRUPT_AFTER_WRITE_CONFIRM_2); // Possible values: // 0 - None (Do not send an interrupt). // 1 - Send Interrupt Only. Program DATA_SEL 0". // 2 - Send Interrupt when Write Confirm (WC) is received from the MC. // 3 - Wait for WC, but dont send interrupt (applicable to 7.3+) [g73_1] // 4 - Reserved for INTERRUPT packet if (isTimeStamp && is64bit) pkt->bitfields3.data_sel = data_sel_mec_release_mem_SEND_GPU_CLOCK_COUNTER_3; else pkt->bitfields3.data_sel = is64bit ? data_sel_mec_release_mem_SEND_64_BIT_DATA_2 : data_sel_mec_release_mem_SEND_32_BIT_LOW_1; // Possible values: // 0 - None, i.e., Discard Data. // 1 - Send 32-bit Data Low (Discard Data High). // 2 - Send 64-bit Data. // 3 - Send current value of the 64 bit global GPU clock counter. // 4 - Send current value of the 64 bit system clock counter. // 5 - Store GDS Data to memory. // 6 - Reserved for use by the CP for Signal Semaphore. // 7 - Reserved for use by the CP for Wait Semaphore. } else { pkt->bitfields3.int_sel = (isPolling ? int_sel_mec_release_mem_NONE_0 : int_sel_mec_release_mem_SEND_INTERRUPT_ONLY_1); pkt->bitfields3.data_sel = data_sel_mec_release_mem_NONE_0; } pkt->bitfields4a.address_lo_dword_aligned = static_cast((address&0xffffffff) >> 2); pkt->addr_hi = static_cast(address>>32); pkt->data_lo = static_cast(data); pkt->data_hi = static_cast(data >> 32); } void PM4ReleaseMemoryPacket::InitPacketAI(bool isPolling, uint64_t address, uint64_t data, bool is64bit, bool isTimeStamp) { PM4MEC_RELEASE_MEM_AI *pkt; m_packetSize = sizeof(PM4MEC_RELEASE_MEM_AI); pkt = reinterpret_cast(AllocPacket()); m_pPacketData = pkt; InitPM4Header(pkt->header, IT_RELEASE_MEM); pkt->bitfields2.event_type = 0x14; pkt->bitfields2.event_index = event_index__mec_release_mem__end_of_pipe; pkt->bitfields2.tc_wb_action_ena = 1; pkt->bitfields2.tc_action_ena = 1; pkt->bitfields2.cache_policy = cache_policy__mec_release_mem__lru; pkt->bitfields3.dst_sel = dst_sel__mec_release_mem__memory_controller; if (address) { pkt->bitfields3.int_sel = (isPolling ? int_sel__mec_release_mem__send_data_after_write_confirm: int_sel__mec_release_mem__send_interrupt_after_write_confirm); if (isTimeStamp && is64bit) pkt->bitfields3.data_sel = data_sel__mec_release_mem__send_gpu_clock_counter; else pkt->bitfields3.data_sel = is64bit ? data_sel__mec_release_mem__send_64_bit_data : data_sel__mec_release_mem__send_32_bit_low; } else { pkt->bitfields3.int_sel = (isPolling ? int_sel__mec_release_mem__none: int_sel__mec_release_mem__send_interrupt_only); pkt->bitfields3.data_sel = data_sel__mec_release_mem__none; } pkt->bitfields4a.address_lo_32b = static_cast((address&0xffffffff) >> 2); pkt->address_hi = static_cast(address>>32); pkt->data_lo = static_cast(data); pkt->data_hi = static_cast(data >> 32); pkt->int_ctxid = static_cast(data); } void PM4ReleaseMemoryPacket::InitPacketNV(bool isPolling, uint64_t address, uint64_t data, bool is64bit, bool isTimeStamp) { PM4MEC_RELEASE_MEM_NV *pkt; m_packetSize = sizeof(PM4_MEC_RELEASE_MEM_NV); pkt = reinterpret_cast(AllocPacket()); m_pPacketData = pkt; InitPM4Header(pkt->header, IT_RELEASE_MEM); pkt->bitfields2.event_type = 0x14; pkt->bitfields2.event_index = event_index__mec_release_mem__end_of_pipe; pkt->bitfields2.gcr_cntl = (1<<10) | (1<<9) | (1<<8) | (1<<3) | (1<<2); pkt->bitfields2.cache_policy = cache_policy__mec_release_mem__lru; pkt->bitfields3.dst_sel = dst_sel__mec_release_mem__memory_controller; if (address) { pkt->bitfields3.int_sel = (isPolling ? int_sel__mec_release_mem__send_data_after_write_confirm: int_sel__mec_release_mem__send_interrupt_after_write_confirm); if (isTimeStamp && is64bit) pkt->bitfields3.data_sel = data_sel__mec_release_mem__send_gpu_clock_counter; else pkt->bitfields3.data_sel = is64bit ? data_sel__mec_release_mem__send_64_bit_data : data_sel__mec_release_mem__send_32_bit_low; } else { pkt->bitfields3.int_sel = (isPolling ? int_sel__mec_release_mem__none: int_sel__mec_release_mem__send_interrupt_only); pkt->bitfields3.data_sel = data_sel__mec_release_mem__none; } pkt->bitfields4a.address_lo_32b = static_cast((address&0xffffffff) >> 2); pkt->address_hi = static_cast(address>>32); pkt->data_lo = static_cast(data); pkt->data_hi = static_cast(data >> 32); pkt->int_ctxid = static_cast(data); } PM4IndirectBufPacket::PM4IndirectBufPacket(IndirectBuffer *pIb) { InitPacket(pIb); } unsigned int PM4IndirectBufPacket::SizeInBytes() const { return sizeof(PM4MEC_INDIRECT_BUFFER); } void PM4IndirectBufPacket::InitPacket(IndirectBuffer *pIb) { memset(&m_packetData, 0, SizeInBytes()); InitPM4Header(m_packetData.header, IT_INDIRECT_BUFFER); m_packetData.bitfields2.ib_base_lo = static_cast((reinterpret_cast(pIb->Addr()))) >> 2; m_packetData.bitfields3.ib_base_hi = reinterpret_cast(pIb->Addr()) >> 32; m_packetData.bitfields4.ib_size = pIb->SizeInDWord(); m_packetData.bitfields4.chain = 0; m_packetData.bitfields4.offload_polling = 0; m_packetData.bitfields4.volatile_setting = 0; m_packetData.bitfields4.valid = 1; m_packetData.bitfields4.vmid = 0; // in iommutest: vmid = queueParams.VMID; m_packetData.bitfields4.cache_policy = cache_policy_indirect_buffer_BYPASS_2; } PM4AcquireMemoryPacket::PM4AcquireMemoryPacket(unsigned int familyId):m_pPacketData(NULL) { m_FamilyId = familyId; if (familyId < FAMILY_NV) InitPacketAI(); else InitPacketNV(); } void PM4AcquireMemoryPacket::InitPacketAI(void) { PM4ACQUIRE_MEM *pkt; m_packetSize = sizeof(PM4ACQUIRE_MEM); pkt = reinterpret_cast(AllocPacket()); m_pPacketData = pkt; InitPM4Header(pkt->header, IT_ACQUIRE_MEM); pkt->bitfields2.coher_cntl = 0x28c00000; // copied from the way the HSART does this. pkt->bitfields2.engine = engine_acquire_mem_PFP_0; pkt->coher_size = 0xFFFFFFFF; pkt->bitfields3.coher_size_hi = 0; pkt->coher_base_lo = 0; pkt->bitfields4.coher_base_hi = 0; pkt->bitfields5.poll_interval = 4; // copied from the way the HSART does this. } void PM4AcquireMemoryPacket::InitPacketNV(void) { PM4ACQUIRE_MEM_NV *pkt; m_packetSize = sizeof(PM4ACQUIRE_MEM_NV); pkt = reinterpret_cast(AllocPacket()); m_pPacketData = pkt; InitPM4Header(pkt->header, IT_ACQUIRE_MEM); pkt->coher_size = 0xFFFFFFFF; pkt->bitfields3.coher_size_hi = 0; pkt->coher_base_lo = 0; pkt->bitfields4.coher_base_hi = 0; pkt->bitfields5.poll_interval = 4; //copied from the way the HSART does this. /* Invalidate gL2, gL1 with range base * Invalidate GLV, GLK (L0$) * Invalidate all Icache (GLI) */ pkt->bitfields6.gcr_cntl = (1<<14|1<<9|1<<8|1<<7|1); } PM4SetShaderRegPacket::PM4SetShaderRegPacket(void) { } PM4SetShaderRegPacket::PM4SetShaderRegPacket(unsigned int baseOffset, const unsigned int regValues[], unsigned int numRegs) { InitPacket(baseOffset, regValues, numRegs); } void PM4SetShaderRegPacket::InitPacket(unsigned int baseOffset, const unsigned int regValues[], unsigned int numRegs) { // 1st register is a part of the packet struct. m_packetSize = sizeof(PM4SET_SH_REG) + (numRegs-1)*sizeof(uint32_t); /* Allocating the size of the packet, since the packet is assembled from a struct * followed by an additional dword data */ m_pPacketData = reinterpret_cast(AllocPacket()); memset(m_pPacketData, 0, m_packetSize); InitPM4Header(m_pPacketData->header, IT_SET_SH_REG); m_pPacketData->bitfields2.reg_offset = baseOffset - PERSISTENT_SPACE_START; memcpy(m_pPacketData->reg_data, regValues, numRegs*sizeof(uint32_t)); } PM4DispatchDirectPacket::PM4DispatchDirectPacket(unsigned int dimX, unsigned int dimY, unsigned int dimZ, unsigned int dispatchInit) { InitPacket(dimX, dimY, dimZ, dispatchInit); } void PM4DispatchDirectPacket::InitPacket(unsigned int dimX, unsigned int dimY, unsigned int dimZ, unsigned int dispatchInit) { memset(&m_packetData, 0, SizeInBytes()); InitPM4Header(m_packetData.header, IT_DISPATCH_DIRECT); m_packetData.dim_x = dimX; m_packetData.dim_y = dimY; m_packetData.dim_z = dimZ; m_packetData.dispatch_initiator = dispatchInit; } unsigned int PM4DispatchDirectPacket::SizeInBytes() const { return sizeof(PM4DISPATCH_DIRECT); } PM4PartialFlushPacket::PM4PartialFlushPacket(void) { memset(&m_packetData, 0, SizeInBytes()); InitPM4Header(m_packetData.header, IT_EVENT_WRITE); m_packetData.bitfields2.event_index = event_index_event_write_CS_VS_PS_PARTIAL_FLUSH_4; m_packetData.bitfields2.event_type = CS_PARTIAL_FLUSH; } unsigned int PM4PartialFlushPacket::SizeInBytes() const { // For PARTIAL_FLUSH_CS packets, the last 2 dwordS don't exist. return sizeof(PM4EVENT_WRITE) - sizeof(uint32_t)*2; } PM4NopPacket::PM4NopPacket(unsigned int count): m_packetSize(count * 4) { m_packetData = reinterpret_cast(AllocPacket()); InitPM4Header(*m_packetData, IT_NOP); } PM4WaitRegMemPacket::PM4WaitRegMemPacket(bool memory, uint64_t addr, uint32_t ref, uint16_t pollInterval) { InitPacket(function__mec_wait_reg_mem__equal_to_the_reference_value, memory ? mem_space__mec_wait_reg_mem__memory_space : mem_space__mec_wait_reg_mem__register_space, operation__mec_wait_reg_mem__wait_reg_mem, addr, ref, 0xffffffff, pollInterval); } PM4WaitRegMemPacket::PM4WaitRegMemPacket(unsigned int function, unsigned int space, unsigned int operation, uint64_t addr, uint32_t ref, uint32_t mask, uint16_t pollInterval) { InitPacket(function, space, operation, addr, ref, mask, pollInterval); } void PM4WaitRegMemPacket::InitPacket(unsigned int function, unsigned int space, unsigned int operation, uint64_t addr, uint32_t ref, uint32_t mask, uint16_t pollInterval) { memset(&m_packetData, 0, SizeInBytes()); InitPM4Header(m_packetData.header, IT_WAIT_REG_MEM); m_packetData.bitfields2.function = (MEC_WAIT_REG_MEM_function_enum)function; m_packetData.bitfields2.mem_space = (MEC_WAIT_REG_MEM_mem_space_enum)space; m_packetData.bitfields2.operation = (MEC_WAIT_REG_MEM_operation_enum)operation; m_packetData.ordinal3 = addr; m_packetData.mem_poll_addr_hi = addr >> 32; m_packetData.reference = ref; m_packetData.mask = mask; m_packetData.bitfields7.poll_interval = pollInterval; m_packetData.bitfields7.optimize_ace_offload_mode = 1; } unsigned int PM4WaitRegMemPacket::SizeInBytes() const { return sizeof(m_packetData); } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/PM4Packet.hpp000066400000000000000000000216061446477712600241020ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_PM4_PACKET__H__ #define __KFD_PM4_PACKET__H__ #include "BasePacket.hpp" #include "kfd_pm4_opcodes.h" #include "pm4_pkt_struct_common.h" #include "pm4_pkt_struct_ci.h" #include "pm4_pkt_struct_ai.h" #include "pm4_pkt_struct_nv.h" #include "IndirectBuffer.hpp" // @class PM4Packet: Marks a group of all PM4 packets class PM4Packet : public BasePacket { public: PM4Packet(void) {} virtual ~PM4Packet(void) {} virtual PACKETTYPE PacketType() const { return PACKETTYPE_PM4; } unsigned int CalcCountValue() const; protected: void InitPM4Header(PM4_TYPE_3_HEADER &header, it_opcode_type opCode); }; // @class PM4WriteDataPacket class PM4WriteDataPacket : public PM4Packet { public: // Empty constructor, before using the packet call the init func PM4WriteDataPacket(void): m_ndw(0), m_pPacketData(NULL) {} // This contructor will also init the packet, no need for additional calls PM4WriteDataPacket(unsigned int *destBuf, unsigned int data1): m_ndw(1), m_pPacketData(NULL) {InitPacket(destBuf, &data1);} PM4WriteDataPacket(unsigned int *destBuf, unsigned int data1, unsigned int data2): m_ndw(2), m_pPacketData(NULL) { unsigned int data[2] = {data1, data2}; InitPacket(destBuf, data); } virtual ~PM4WriteDataPacket(void) {} // @returns Packet size in bytes virtual unsigned int SizeInBytes() const; // @returns Pointer to the packet virtual const void *GetPacket() const { return m_pPacketData; } // @brief Initialise the packet void InitPacket(unsigned int *destBuf, unsigned int data1) { m_ndw = 1; InitPacket(destBuf, &data1); } void InitPacket(unsigned int *destBuf, unsigned int data1, unsigned int data2) { unsigned int data[2] = {data1, data2}; m_ndw = 2; InitPacket(destBuf, data); } void InitPacket(unsigned int *destBuf, void *data); protected: unsigned int m_ndw; // PM4WRITE_DATA_CI struct contains all the packet's data PM4WRITE_DATA_CI *m_pPacketData; }; // @class PM4ReleaseMemoryPacket class PM4ReleaseMemoryPacket : public PM4Packet { public: // Empty constructor, before using the packet call the init func PM4ReleaseMemoryPacket(void): m_pPacketData(NULL) {} // This contructor will also init the packet, no need for additional calls PM4ReleaseMemoryPacket(unsigned int familyId, bool isPolling, uint64_t address, uint64_t data, bool is64bit = false, bool isTimeStamp = false); virtual ~PM4ReleaseMemoryPacket(void) {} // @returns Packet size in bytes virtual unsigned int SizeInBytes() const { return m_packetSize; } // @returns Pointer to the packet virtual const void *GetPacket() const { return m_pPacketData; } // @brief Initialise the packet private: void InitPacketCI(bool isPolling, uint64_t address, uint64_t data, bool is64bit = false, bool isTimeStamp = false); void InitPacketAI(bool isPolling, uint64_t address, uint64_t data, bool is64bit = false, bool isTimeStamp = false); void InitPacketNV(bool isPolling, uint64_t address, uint64_t data, bool is64bit = false, bool isTimeStamp = false); void *m_pPacketData; unsigned int m_packetSize; }; // @class PM4IndirectBufPacket class PM4IndirectBufPacket : public PM4Packet { public: // Empty constructor, before using the packet call the init func PM4IndirectBufPacket(void) {} // This contructor will also init the packet, no need for additional calls explicit PM4IndirectBufPacket(IndirectBuffer *pIb); virtual ~PM4IndirectBufPacket(void) {} // @returns Packet size in bytes virtual unsigned int SizeInBytes() const; // @returns Pointer to the packet virtual const void *GetPacket() const { return &m_packetData; } // @breif Initialise the packet void InitPacket(IndirectBuffer *pIb); private: // PM4MEC_INDIRECT_BUFFER struct contains all the packet's data PM4MEC_INDIRECT_BUFFER m_packetData; }; // @class PM4AcquireMemoryPacket class PM4AcquireMemoryPacket : public PM4Packet { public: PM4AcquireMemoryPacket(unsigned int familyId); virtual ~PM4AcquireMemoryPacket(void) {} // @returns the packet size in bytes virtual unsigned int SizeInBytes() const { return m_packetSize; } // @returns Pointer to the packet virtual const void *GetPacket() const { return m_pPacketData; } private: void InitPacketAI(void); void InitPacketNV(void); void *m_pPacketData; unsigned int m_packetSize; }; // @class PM4SetShaderRegPacket Packet that writes to consecutive registers starting at baseOffset. class PM4SetShaderRegPacket : public PM4Packet { public: PM4SetShaderRegPacket(void); PM4SetShaderRegPacket(unsigned int baseOffset, const unsigned int regValues[], unsigned int numRegs); virtual ~PM4SetShaderRegPacket(void) {} // @returns Packet size in bytes virtual unsigned int SizeInBytes() const { return m_packetSize; } // @returns Pointer to the packet virtual const void *GetPacket() const { return m_pPacketData; } void InitPacket(unsigned int baseOffset, const unsigned int regValues[], unsigned int numRegs); private: unsigned int m_packetSize; // PM4SET_SH_REG struct contains all the packet's data PM4SET_SH_REG *m_pPacketData; }; // @class PM4DispatchDirectPacket class PM4DispatchDirectPacket : public PM4Packet { public: PM4DispatchDirectPacket(void) {} PM4DispatchDirectPacket(unsigned int dimX, unsigned int dimY, unsigned int dimZ, unsigned int dispatchInit); virtual ~PM4DispatchDirectPacket(void) {} // @returns Packet size in bytes virtual unsigned int SizeInBytes() const; // @returns Pointer to the packet virtual const void *GetPacket() const { return &m_packetData; } void InitPacket(unsigned int dimX, unsigned int dimY, unsigned int dimZ, unsigned int dispatchInit); private: // PM4DISPATCH_DIRECT struct contains all the packet's data PM4DISPATCH_DIRECT m_packetData; }; // @class PM4PartialFlushPacket class PM4PartialFlushPacket : public PM4Packet { public: PM4PartialFlushPacket(void); virtual ~PM4PartialFlushPacket(void) {} // @returns Packet size in bytes virtual unsigned int SizeInBytes() const; // @returns Pointer to the packet virtual const void *GetPacket() const { return &m_packetData; } private: // PM4EVENT_WRITE struct contains all the packet's data PM4EVENT_WRITE m_packetData; }; // @class PM4NopPacket class PM4NopPacket : public PM4Packet { public: PM4NopPacket(unsigned int count = 1); virtual ~PM4NopPacket(void) {} // @returns Packet size in bytes virtual unsigned int SizeInBytes() const { return m_packetSize; } // @returns Pointer to the packet virtual const void *GetPacket() const { return m_packetData; } private: unsigned int m_packetSize; PM4_TYPE_3_HEADER *m_packetData; }; // @class PM4WaitRegMemPacket class PM4WaitRegMemPacket : public PM4Packet { public: PM4WaitRegMemPacket(void) {} PM4WaitRegMemPacket(bool memory, uint64_t addr, uint32_t ref, uint16_t pollInterval); PM4WaitRegMemPacket(unsigned int function, unsigned int space, unsigned int operation, uint64_t addr, uint32_t ref, uint32_t mask, uint16_t pollInterval); virtual ~PM4WaitRegMemPacket(void) {} // @returns Packet size in bytes virtual unsigned int SizeInBytes() const; // @returns Pointer to the packet virtual const void *GetPacket() const { return &m_packetData; } void InitPacket(unsigned int function, unsigned int space, unsigned int operation, uint64_t addr, uint32_t ref, uint32_t mask, uint16_t pollInterval); private: PM4MEC_WAIT_REG_MEM m_packetData; }; #endif // __KFD_PM4_PACKET__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/PM4Queue.cpp000066400000000000000000000056761446477712600237630ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "PM4Queue.hpp" #include "pm4_pkt_struct_common.h" #include "GoogleTestExtension.hpp" #include "kfd_pm4_opcodes.h" PM4Queue::PM4Queue(void) { CMD_NOP = CMD_NOP_TYPE_3; } PM4Queue::~PM4Queue(void) { } unsigned int PM4Queue::Wptr() { /* Write pointer in dwords. Simulate 32-bit wptr that wraps at * queue size even on Vega10 and later chips with 64-bit wptr. */ return *m_Resources.Queue_write_ptr % (m_QueueBuf->Size() / 4); } unsigned int PM4Queue::Rptr() { /* CP read pointer in dwords. It's still 32-bit even on Vega10. */ return *m_Resources.Queue_read_ptr; } unsigned int PM4Queue::RptrWhenConsumed() { /* On PM4 queues Rptr is always 32-bit in dword units and wraps at * queue size. The expected value when all packets are consumed is * exactly the value returned by Wptr(). */ return Wptr(); } void PM4Queue::SubmitPacket() { // m_pending Wptr is in dwords if (m_FamilyId < FAMILY_AI) { // Pre-Vega10 uses 32-bit wptr and doorbell MemoryBarrier(); *m_Resources.Queue_write_ptr = m_pendingWptr; MemoryBarrier(); *(m_Resources.Queue_DoorBell) = m_pendingWptr; } else { // Vega10 and later uses 64-bit wptr and doorbell MemoryBarrier(); *m_Resources.Queue_write_ptr_aql = m_pendingWptr64; MemoryBarrier(); *(m_Resources.Queue_DoorBell_aql) = m_pendingWptr64; } } void PM4Queue::Wait4PacketConsumption(HsaEvent *event, unsigned int timeOut) { if (event) { PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, 0, event->EventData.HWData2, event->EventId, true)); EXPECT_SUCCESS(hsaKmtWaitOnEvent(event, timeOut)); } else { BaseQueue::Wait4PacketConsumption(NULL, timeOut); } } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/PM4Queue.hpp000066400000000000000000000047671446477712600237700ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_PM4_QUEUE__H__ #define __KFD_PM4_QUEUE__H__ #include "BaseQueue.hpp" #include "PM4Packet.hpp" class PM4Queue : public BaseQueue { public: PM4Queue(void); virtual ~PM4Queue(void); // @brief update queue write pointer and sets the queue doorbell to the queue write pointer virtual void SubmitPacket(); // @ return read pointer modulo queue size in dwords virtual unsigned int Rptr(); // @ return write pointer modulo queue size in dwords virtual unsigned int Wptr(); // @ return expected m_Resources.Queue_read_ptr when all packets consumed virtual unsigned int RptrWhenConsumed(); /** Wait for all the packets submitted to the queue to be consumed. (i.e. wait until RPTR=WPTR). * Note that all packets being consumed is not the same as all packets being processed. * If event is set, wait all packets being processed. * And we can benefit from that as it has * 1) Less CPU usage (process can sleep, waiting for interrupt). * 2) Lower latency (GPU only updates RPTR in memory periodically). */ virtual void Wait4PacketConsumption(HsaEvent *event = NULL, unsigned int timeOut = g_TestTimeOut); protected: virtual PACKETTYPE PacketTypeSupported() { return PACKETTYPE_PM4; } virtual _HSA_QUEUE_TYPE GetQueueType() { return HSA_QUEUE_COMPUTE; } }; #endif // __KFD_PM4_QUEUE__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/RDMATest.cpp000066400000000000000000000075111446477712600237270ustar00rootroot00000000000000/* * Copyright (C) 2016-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "RDMATest.hpp" #include "PM4Queue.hpp" #include "PM4Packet.hpp" #include "SDMAPacket.hpp" #include "SDMAQueue.hpp" #include "Dispatch.hpp" #include "RDMAUtil.hpp" void RDMATest::SetUp() { ROUTINE_START KFDBaseComponentTest::SetUp(); ROUTINE_END } void RDMATest::TearDown() { ROUTINE_START KFDBaseComponentTest::TearDown(); ROUTINE_END } TEST_F(RDMATest, GPUDirect) { TEST_REQUIRE_ENV_CAPABILITIES(ENVCAPS_64BITLINUX); TEST_START(TESTPROFILE_RUNALL); HSAuint64 AlternateVAGPU; PM4Queue queue; unsigned int BufferSize = PAGE_SIZE; int ret; int defaultGPUNode = m_NodeInfo.HsaDefaultGPUNode(); ASSERT_GE(defaultGPUNode, 0) << "failed to get default GPU Node"; HsaMemoryBuffer isaBuffer(PAGE_SIZE, defaultGPUNode); HsaMemoryBuffer srcSysBuffer(BufferSize, defaultGPUNode, false); HsaMemoryBuffer srcLocalBuffer(BufferSize, defaultGPUNode, false, true); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(srcSysBuffer.As(), srcSysBuffer.Size(), &AlternateVAGPU)); ASSERT_SUCCESS(hsaKmtMapMemoryToGPU(srcLocalBuffer.As(), srcLocalBuffer.Size(), &AlternateVAGPU)); /* Fill up srcSysBuffer */ srcSysBuffer.Fill(0xfe); /* Put 'copy dword' command to ISA buffer */ ASSERT_SUCCESS(m_pAsm->RunAssembleBuf(CopyDwordIsa, isaBuffer.As())); ASSERT_SUCCESS(queue.Create(defaultGPUNode)); Dispatch dispatch(isaBuffer); /* Submit the command to GPU so GPU will copy from system memory * (srcSysBuffer) to local memory(srcLocalBuffer) */ dispatch.SetArgs(srcSysBuffer.As(), srcLocalBuffer.As()); dispatch.Submit(queue); dispatch.Sync(g_TestTimeOut); // GPU executed the command EXPECT_SUCCESS(queue.Destroy()); LocalMemoryAccess Rdma; Rdma.Open(); ASSERT_GE(Rdma.fd, 0) << "Failed to open RDMA"; /* GetPages asks the test driver to convert GPU virtual memory to DMA/ * Physical memory and save it in the list. rdma_mmap maps the memory to * user space memory. */ ret = Rdma.GetPages((uint64_t)srcLocalBuffer.As(), PAGE_SIZE); ASSERT_EQ(ret, 0) << "Failed to get pages"; void *gpuAddr = Rdma.MMap((uint64_t)srcLocalBuffer.As(), PAGE_SIZE); ASSERT_GE((uint64_t)gpuAddr, 0) << "Failed to map RDMA address."; /* Read the memory to confirm that application can read the local memory * correctly from the mapped address. */ EXPECT_EQ(memcmp(gpuAddr, srcSysBuffer.As(), 4), 0); Rdma.UnMap(gpuAddr, PAGE_SIZE); Rdma.Close(); TEST_END } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/RDMATest.hpp000066400000000000000000000026761446477712600237430ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __RDMA_TEST__H__ #define __RDMA_TEST__H__ #include #include "KFDBaseComponentTest.hpp" class RDMATest : public KFDBaseComponentTest { public: RDMATest() {} ~RDMATest() {} protected: virtual void SetUp(); virtual void TearDown(); }; #endif // __RDMA_TEST__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/RDMAUtil.cpp000066400000000000000000000041241446477712600237220ustar00rootroot00000000000000/* * Copyright (C) 2016-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include #include #include #include #include #include #include "amdp2ptest.h" #include "RDMAUtil.hpp" void LocalMemoryAccess::Open() { fd = open(AMDP2PTEST_DEVICE_PATH, O_RDWR); } void LocalMemoryAccess::Close() { close(fd); fd = -1; } int LocalMemoryAccess::GetPages(uint64_t gpu_va_addr, uint64_t size) { struct AMDRDMA_IOCTL_GET_PAGES_PARAM param = {0}; if (fd <= 0) return -1; param.addr = gpu_va_addr; param.length = size; return ioctl(fd, AMD2P2PTEST_IOCTL_GET_PAGES, ¶m); } void *LocalMemoryAccess::MMap(uint64_t offset, size_t size) { void *gpuAddr; if (fd <= 0) return NULL; gpuAddr = mmap(NULL, size, PROT_READ, MAP_PRIVATE, fd, offset); return gpuAddr; } void LocalMemoryAccess::UnMap(void *offset, size_t size) { munmap(offset, size); } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/RDMAUtil.hpp000066400000000000000000000026431446477712600237330ustar00rootroot00000000000000/* * Copyright (C) 2016-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __RDMA__UTIL__H__ #define __RDMA__UTIL__H__ class LocalMemoryAccess { public: int fd; void Open(void); void Close(void); int GetPages(uint64_t, uint64_t); void *MMap(uint64_t, size_t); void UnMap(void *, size_t); }; #endif // __RDMA__UTIL__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/SDMAPacket.cpp000066400000000000000000000214321446477712600242160ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include "SDMAPacket.hpp" #include "KFDTestUtil.hpp" /* Byte/dword count in many SDMA packets is 1-based in AI, meaning a * count of 1 is encoded as 0. */ #define SDMA_COUNT(c) (m_FamilyId < FAMILY_AI ? (c) : (c)-1) SDMAWriteDataPacket::SDMAWriteDataPacket(unsigned int familyId, void* destAddr, unsigned int data): packetData(NULL) { m_FamilyId = familyId; InitPacket(destAddr, 1, &data); } SDMAWriteDataPacket::SDMAWriteDataPacket(unsigned int familyId, void* destAddr, unsigned int ndw, void *data): packetData(NULL) { m_FamilyId = familyId; InitPacket(destAddr, ndw, data); } void SDMAWriteDataPacket::InitPacket(void* destAddr, unsigned int ndw, void *data) { packetSize = sizeof(SDMA_PKT_WRITE_UNTILED) + (ndw - 1) * sizeof(unsigned int); packetData = reinterpret_cast(AllocPacket()); packetData->HEADER_UNION.op = SDMA_OP_WRITE; packetData->HEADER_UNION.sub_op = SDMA_SUBOP_WRITE_LINEAR; SplitU64(reinterpret_cast(destAddr), packetData->DST_ADDR_LO_UNION.DW_1_DATA, // dst_addr_31_0 packetData->DST_ADDR_HI_UNION.DW_2_DATA); // dst_addr_63_32 packetData->DW_3_UNION.count = SDMA_COUNT(ndw); memcpy(&packetData->DATA0_UNION.DW_4_DATA, data, ndw*sizeof(unsigned int)); } #define BITS (21) #define TWO_MEG (1 << BITS) SDMACopyDataPacket::SDMACopyDataPacket(unsigned int familyId, void *const dsts[], void *src, int n, unsigned int surfsize) { int32_t size = 0, i; void **dst = reinterpret_cast(malloc(sizeof(void*) * n)); const int singlePacketSize = sizeof(SDMA_PKT_COPY_LINEAR) + sizeof(SDMA_PKT_COPY_LINEAR::DST_ADDR[0]) * n; if (n > 2) WARN() << "SDMACopyDataPacket does not support more than 2 dst addresses!" << std::endl; m_FamilyId = familyId; memcpy(dst, dsts, sizeof(void*) * n); packetSize = ((surfsize + TWO_MEG - 1) >> BITS) * singlePacketSize; SDMA_PKT_COPY_LINEAR *pSDMA = reinterpret_cast(AllocPacket()); packetData = pSDMA; while (surfsize > 0) { /* SDMA support maximum 0x3fffe0 byte in one copy, take 2M here */ if (surfsize > TWO_MEG) size = TWO_MEG; else size = surfsize; memset(pSDMA, 0, singlePacketSize); pSDMA->HEADER_UNION.op = SDMA_OP_COPY; pSDMA->HEADER_UNION.sub_op = SDMA_SUBOP_COPY_LINEAR; pSDMA->HEADER_UNION.broadcast = n > 1 ? 1 : 0; pSDMA->COUNT_UNION.count = SDMA_COUNT(size); SplitU64(reinterpret_cast(src), pSDMA->SRC_ADDR_LO_UNION.DW_3_DATA, // src_addr_31_0 pSDMA->SRC_ADDR_HI_UNION.DW_4_DATA); // src_addr_63_32 for (i = 0; i < n; i++) SplitU64(reinterpret_cast(dst[i]), pSDMA->DST_ADDR[i].DST_ADDR_LO_UNION.DW_5_DATA, // dst_addr_31_0 pSDMA->DST_ADDR[i].DST_ADDR_HI_UNION.DW_6_DATA); // dst_addr_63_32 pSDMA = reinterpret_cast(reinterpret_cast(pSDMA) + singlePacketSize); for (i = 0; i < n; i++) dst[i] = reinterpret_cast(dst[i]) + size; src = reinterpret_cast(src) + size; surfsize -= size; } free(dst); } SDMACopyDataPacket::SDMACopyDataPacket(unsigned int familyId, void* dst, void *src, unsigned int surfsize) { new (this)SDMACopyDataPacket(familyId, &dst, src, 1, surfsize); } SDMAFillDataPacket::SDMAFillDataPacket(unsigned int familyId, void *dst, unsigned int data, unsigned int size) { unsigned int copy_size; SDMA_PKT_CONSTANT_FILL *pSDMA; m_FamilyId = familyId; /* SDMA support maximum 0x3fffe0 byte in one copy. Use 2M copy_size */ m_PacketSize = ((size + TWO_MEG - 1) >> BITS) * sizeof(SDMA_PKT_CONSTANT_FILL); pSDMA = reinterpret_cast(AllocPacket()); m_PacketData = pSDMA; while (size > 0) { if (size > TWO_MEG) copy_size = TWO_MEG; else copy_size = size; pSDMA->HEADER_UNION.op = SDMA_OP_CONST_FILL; pSDMA->HEADER_UNION.sub_op = 0; /* If both size and address are DW aligned, then use DW fill */ if (!(copy_size & 0x3) && !((HSAuint64)dst & 0x3)) pSDMA->HEADER_UNION.fillsize = 2; /* DW Fill */ else pSDMA->HEADER_UNION.fillsize = 0; /* Byte Fill */ pSDMA->COUNT_UNION.count = SDMA_COUNT(copy_size); SplitU64(reinterpret_cast(dst), pSDMA->DST_ADDR_LO_UNION.DW_1_DATA, /*dst_addr_31_0*/ pSDMA->DST_ADDR_HI_UNION.DW_2_DATA); /*dst_addr_63_32*/ pSDMA->DATA_UNION.DW_3_DATA = data; pSDMA++; dst = reinterpret_cast(dst) + copy_size; size -= copy_size; } } SDMAFencePacket::SDMAFencePacket(void) { } SDMAFencePacket::SDMAFencePacket(unsigned int familyId, void* destAddr, unsigned int data) { m_FamilyId = familyId; if (m_FamilyId < FAMILY_NV) InitPacketCI(destAddr, data); else InitPacketNV(destAddr, data); } SDMAFencePacket::~SDMAFencePacket(void) { } void SDMAFencePacket::InitPacketCI(void* destAddr, unsigned int data) { memset(&packetData, 0, SizeInBytes()); packetData.HEADER_UNION.op = SDMA_OP_FENCE; SplitU64(reinterpret_cast(destAddr), packetData.ADDR_LO_UNION.DW_1_DATA, /*dst_addr_31_0*/ packetData.ADDR_HI_UNION.DW_2_DATA); /*dst_addr_63_32*/ packetData.DATA_UNION.data = data; } void SDMAFencePacket::InitPacketNV(void * destAddr,unsigned int data) { memset(&packetData, 0, SizeInBytes()); /* GPA=0 becaue we use virtual address * Snoop = 1 because we want the write be CPU coherent * System = 1 because the memory is system memory * mtype = uncached, for the purpose of CPU coherent, L2 policy doesn't matter in this case */ packetData.HEADER_UNION.DW_0_DATA = (0 << 23) | (1 << 22) | (1 << 20) | (3 << 16) | SDMA_OP_FENCE; SplitU64(reinterpret_cast(destAddr), packetData.ADDR_LO_UNION.DW_1_DATA, /*dst_addr_31_0*/ packetData.ADDR_HI_UNION.DW_2_DATA); /*dst_addr_63_32*/ packetData.DATA_UNION.data = data; } SDMATrapPacket::SDMATrapPacket(unsigned int eventID) { InitPacket(eventID); } SDMATrapPacket::~SDMATrapPacket(void) { } void SDMATrapPacket::InitPacket(unsigned int eventID) { memset(&packetData, 0, SizeInBytes()); packetData.HEADER_UNION.op = SDMA_OP_TRAP; packetData.INT_CONTEXT_UNION.int_context = eventID; } SDMATimePacket::SDMATimePacket(void *destaddr) { InitPacket(destaddr); } SDMATimePacket::~SDMATimePacket(void) { } void SDMATimePacket::InitPacket(void *destaddr) { memset(&packetData, 0, SizeInBytes()); packetData.HEADER_UNION.op = SDMA_OP_TIMESTAMP; packetData.HEADER_UNION.sub_op = 1 << 1; /* Get Global GPU Timestamp*/ if (reinterpret_cast(destaddr) & 0x1f) WARN() << "SDMATimePacket dst address must aligned to 32bytes boundary" << std::endl; SplitU64(reinterpret_cast(destaddr), packetData.ADDR_LO_UNION.DW_1_DATA, /*dst_addr_31_0*/ packetData.ADDR_HI_UNION.DW_2_DATA); /*dst_addr_63_32*/ } SDMANopPacket::SDMANopPacket(unsigned int count) { packetSize = count * sizeof(unsigned int); packetData = reinterpret_cast(AllocPacket()); packetData->HEADER_UNION.op = SDMA_OP_NOP; packetData->HEADER_UNION.sub_op = 0; packetData->HEADER_UNION.count = count - 1; } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/SDMAPacket.hpp000066400000000000000000000140241446477712600242220ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_SDMA_PACKET__H__ #define __KFD_SDMA_PACKET__H__ #include "BasePacket.hpp" #include "sdma_pkt_struct.h" // @class SDMAPacket: Marks a group of all SDMA packets class SDMAPacket : public BasePacket { public: SDMAPacket(void) {} virtual ~SDMAPacket(void) {} virtual PACKETTYPE PacketType() const { return PACKETTYPE_SDMA; } }; class SDMAWriteDataPacket : public SDMAPacket { public: // This contructor will also init the packet, no need for additional calls SDMAWriteDataPacket(unsigned int familyId, void* destAddr, unsigned int data); SDMAWriteDataPacket(unsigned int familyId, void* destAddr, unsigned int ndw, void *data); virtual ~SDMAWriteDataPacket(void) {} // @returns Pointer to the packet virtual const void *GetPacket() const { return packetData; } // @breif Initialise the packet void InitPacket(void* destAddr, unsigned int ndw, void *data); // @returns Packet size in bytes virtual unsigned int SizeInBytes() const { return packetSize; } protected: // SDMA_PKT_WRITE_UNTILED struct contains all the packet's data SDMA_PKT_WRITE_UNTILED *packetData; unsigned int packetSize; }; class SDMACopyDataPacket : public SDMAPacket { public: // This contructor will also init the packet, no need for additional calls SDMACopyDataPacket(unsigned int familyId, void *dest, void *src, unsigned int size); SDMACopyDataPacket(unsigned int familyId, void *const dst[], void *src, int n, unsigned int surfsize); virtual ~SDMACopyDataPacket(void) {} // @returns Pointer to the packet virtual const void *GetPacket() const { return packetData; } // @returns Packet size in bytes virtual unsigned int SizeInBytes() const { return packetSize; } protected: // SDMA_PKT_COPY_LINEAR struct contains all the packet's data SDMA_PKT_COPY_LINEAR *packetData; unsigned int packetSize; }; class SDMAFillDataPacket : public SDMAPacket { public: // This contructor will also init the packet, no need for additional calls SDMAFillDataPacket(unsigned int familyId, void *dest, unsigned int data, unsigned int size); virtual ~SDMAFillDataPacket(void) {} // @returns Pointer to the packet virtual const void *GetPacket() const { return m_PacketData; } // @returns Packet size in bytes virtual unsigned int SizeInBytes() const { return m_PacketSize; } protected: // SDMA_PKT_CONSTANT_FILL struct contains all the packet's data SDMA_PKT_CONSTANT_FILL *m_PacketData; unsigned int m_PacketSize; }; class SDMAFencePacket : public SDMAPacket { public: // Empty constructor, before using the packet call the init func SDMAFencePacket(void); // This contructor will also init the packet, no need for additional calls SDMAFencePacket(unsigned int familyId, void* destAddr, unsigned int data); virtual ~SDMAFencePacket(void); // @returns Pointer to the packet virtual const void *GetPacket() const { return &packetData; } // @brief Initialise the packet void InitPacketCI(void* destAddr, unsigned int data); void InitPacketNV(void* destAddr, unsigned int data); // @returns Packet size in bytes virtual unsigned int SizeInBytes() const { return sizeof(SDMA_PKT_FENCE ); } protected: // SDMA_PKT_FENCE struct contains all the packet's data SDMA_PKT_FENCE packetData; }; class SDMATrapPacket : public SDMAPacket { public: // Empty constructor, before using the packet call the init func explicit SDMATrapPacket(unsigned int eventID = 0); virtual ~SDMATrapPacket(void); // @returns Pointer to the packet virtual const void *GetPacket() const { return &packetData; } // @brief Initialise the packet void InitPacket(unsigned int eventID); // @returns Packet size in bytes virtual unsigned int SizeInBytes() const { return sizeof(SDMA_PKT_TRAP); } protected: // SDMA_PKT_TRAP struct contains all the packet's data SDMA_PKT_TRAP packetData; }; class SDMATimePacket : public SDMAPacket { public: // Empty constructor, before using the packet call the init func SDMATimePacket(void*); virtual ~SDMATimePacket(void); // @returns Pointer to the packet virtual const void *GetPacket() const { return &packetData; } // @brief Initialise the packet void InitPacket(void*); // @returns Packet size in bytes virtual unsigned int SizeInBytes() const { return sizeof(SDMA_PKT_TIMESTAMP); } protected: SDMA_PKT_TIMESTAMP packetData; }; class SDMANopPacket : public SDMAPacket { public: SDMANopPacket(unsigned int count = 1); virtual ~SDMANopPacket(void) {} // @returns Pointer to the packet virtual const void *GetPacket() const { return packetData; } // @returns Packet size in bytes virtual unsigned int SizeInBytes() const { return packetSize; } private: SDMA_PKT_NOP *packetData; unsigned int packetSize; }; #endif // __KFD_SDMA_PACKET__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/SDMAQueue.cpp000066400000000000000000000070361446477712600240770ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "SDMAQueue.hpp" #include "SDMAPacket.hpp" SDMAQueue::SDMAQueue(void) { CMD_NOP = 0; } SDMAQueue::~SDMAQueue(void) { } unsigned int SDMAQueue::Wptr() { /* In SDMA queues write pointers are saved in bytes, convert the * wptr value to dword to fit the way BaseQueue works. On Vega10 * the write ptr is 64-bit. We only read the low 32 bit (assuming * the queue buffer is smaller than 4GB) and modulo divide by the * queue size to simulate a 32-bit read pointer. */ return (*m_Resources.Queue_write_ptr % m_QueueBuf->Size()) / sizeof(unsigned int); } unsigned int SDMAQueue::Rptr() { /* In SDMA queues read pointers are saved in bytes, convert the * read value to dword to fit the way BaseQueue works. On Vega10 * the read ptr is 64-bit. We only read the low 32 bit (assuming * the queue buffer is smaller than 4GB) and modulo divide by the * queue size to simulate a 32-bit read pointer. */ return (*m_Resources.Queue_read_ptr % m_QueueBuf->Size()) / sizeof(unsigned int); } unsigned int SDMAQueue::RptrWhenConsumed() { /* Rptr is same size and byte units as Wptr. Here we only care * about the low 32-bits. When all packets are consumed, read and * write pointers should have the same value. */ return *m_Resources.Queue_write_ptr; } void SDMAQueue::SubmitPacket() { // m_pending Wptr is in dwords if (m_FamilyId < FAMILY_AI) { // Pre-Vega10 uses 32-bit wptr and doorbell unsigned int wPtrInBytes = m_pendingWptr * sizeof(unsigned int); MemoryBarrier(); *m_Resources.Queue_write_ptr = wPtrInBytes; MemoryBarrier(); *(m_Resources.Queue_DoorBell) = wPtrInBytes; } else { // Vega10 and later uses 64-bit wptr and doorbell HSAuint64 wPtrInBytes = m_pendingWptr64 * sizeof(unsigned int); MemoryBarrier(); *m_Resources.Queue_write_ptr_aql = wPtrInBytes; MemoryBarrier(); *(m_Resources.Queue_DoorBell_aql) = wPtrInBytes; } } void SDMAQueue::Wait4PacketConsumption(HsaEvent *event, unsigned int timeOut) { if (event) { PlacePacket(SDMAFencePacket(m_FamilyId, (void*)event->EventData.HWData2, event->EventId)); PlaceAndSubmitPacket(SDMATrapPacket(event->EventId)); EXPECT_SUCCESS(hsaKmtWaitOnEvent(event, timeOut)); } else { BaseQueue::Wait4PacketConsumption(NULL, timeOut); } } ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/SDMAQueue.hpp000066400000000000000000000047461446477712600241110ustar00rootroot00000000000000/* * Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_SDMA_QUEUE__H__ #define __KFD_SDMA_QUEUE__H__ #include "BaseQueue.hpp" class SDMAQueue : public BaseQueue { public: SDMAQueue(void); virtual ~SDMAQueue(void); // @brief Update queue write pointer and set the queue doorbell to the queue write pointer virtual void SubmitPacket(); /** Wait for all the packets submitted to the queue to be consumed. (i.e. wait until RPTR=WPTR). * Note that all packets being consumed is not the same as all packets being processed. * If event is set, wait all packets being processed. * And we can benefit from that as it has * 1) Less CPU usage (process can sleep, waiting for interrupt). * 2) Lower latency (GPU only updates RPTR in memory periodically). */ virtual void Wait4PacketConsumption(HsaEvent *event = NULL, unsigned int timeOut = g_TestTimeOut); protected: // @ return Write pointer modulo queue size in dwords virtual unsigned int Wptr(); // @ return Read pointer modulo queue size in dwords virtual unsigned int Rptr(); // @ return Expected m_Resources.Queue_read_ptr when all packets are consumed virtual unsigned int RptrWhenConsumed(); virtual PACKETTYPE PacketTypeSupported() { return PACKETTYPE_SDMA; } virtual _HSA_QUEUE_TYPE GetQueueType() { return HSA_QUEUE_SDMA; } }; #endif // __KFD_SDMA_QUEUE__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/ShaderStore.cpp000066400000000000000000000707441446477712600245770ustar00rootroot00000000000000/* * Copyright (C) 2021 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "ShaderStore.hpp" /** * KFDASMTest List */ const std::vector ShaderList = { NoopIsa, CopyDwordIsa, InfiniteLoopIsa, AtomicIncIsa, ScratchCopyDwordIsa, PollMemoryIsa, CopyOnSignalIsa, PollAndCopyIsa, WriteFlagAndValueIsa, WriteAndSignalIsa, LoopIsa, PersistentIterateIsa, ReadMemoryIsa, GwsInitIsa, GwsAtomicIncreaseIsa, }; /** * Macros */ #define SHADER_START ".text\n" /* Macros for portable v_add_co_u32, v_add_co_ci_u32, * and v_cmp_lt_u32. */ #define SHADER_MACROS_U32 \ " .text\n"\ " .macro V_ADD_CO_U32 vdst, src0, vsrc1\n"\ " .if (.amdgcn.gfx_generation_number >= 10)\n"\ " v_add_co_u32 \\vdst, vcc_lo, \\src0, \\vsrc1\n"\ " .elseif (.amdgcn.gfx_generation_number >= 9)\n"\ " v_add_co_u32 \\vdst, vcc, \\src0, \\vsrc1\n"\ " .else\n"\ " v_add_u32 \\vdst, vcc, \\src0, \\vsrc1\n"\ " .endif\n"\ " .endm\n"\ " .macro V_ADD_CO_CI_U32 vdst, src0, vsrc1\n"\ " .if (.amdgcn.gfx_generation_number >= 10)\n"\ " v_add_co_ci_u32 \\vdst, vcc_lo, \\src0, \\vsrc1, vcc_lo\n"\ " .elseif (.amdgcn.gfx_generation_number >= 9)\n"\ " v_addc_co_u32 \\vdst, vcc, \\src0, \\vsrc1, vcc\n"\ " .else\n"\ " v_addc_u32 \\vdst, vcc, \\src0, \\vsrc1, vcc\n"\ " .endif\n"\ " .endm\n"\ " .macro V_CMP_LT_U32 src0, vsrc1\n"\ " .if (.amdgcn.gfx_generation_number >= 10)\n"\ " v_cmp_lt_u32 vcc_lo, \\src0, \\vsrc1\n"\ " .else\n"\ " v_cmp_lt_u32 vcc, \\src0, \\vsrc1\n"\ " .endif\n"\ " .endm\n" /* Macros for portable flat load/store/atomic instructions. * * gc943 (gfx94x) deprecates glc/slc in favour of nt/sc1/sc0. * The below macros when used will always use the nt sc1 sc0 * modifiers for gfx94x, but also take in arg0 arg1 to specify * (for non-gfx94x): glc, slc, or glc slc. */ #define SHADER_MACROS_FLAT \ " .macro FLAT_LOAD_DWORD_NSS vdst, vaddr arg0 arg1\n"\ " .if (.amdgcn.gfx_generation_number == 9 && .amdgcn.gfx_generation_minor == 4)\n"\ " flat_load_dword \\vdst, \\vaddr nt sc1 sc0\n"\ " .else\n"\ " flat_load_dword \\vdst, \\vaddr \\arg0 \\arg1\n"\ " .endif\n"\ " .endm\n"\ " .macro FLAT_LOAD_DWORDX2_NSS vdst, vaddr arg0 arg1\n"\ " .if (.amdgcn.gfx_generation_number == 9 && .amdgcn.gfx_generation_minor == 4)\n"\ " flat_load_dwordx2 \\vdst, \\vaddr nt sc1 sc0\n"\ " .else\n"\ " flat_load_dwordx2 \\vdst, \\vaddr \\arg0 \\arg1\n"\ " .endif\n"\ " .endm\n"\ " .macro FLAT_STORE_DWORD_NSS vaddr, vsrc arg0 arg1\n"\ " .if (.amdgcn.gfx_generation_number == 9 && .amdgcn.gfx_generation_minor == 4)\n"\ " flat_store_dword \\vaddr, \\vsrc nt sc1 sc0\n"\ " .else\n"\ " flat_store_dword \\vaddr, \\vsrc \\arg0 \\arg1\n"\ " .endif\n"\ " .endm\n"\ " .macro FLAT_ATOMIC_ADD_NSS vdst, vaddr, vsrc arg0 arg1\n"\ " .if (.amdgcn.gfx_generation_number == 9 && .amdgcn.gfx_generation_minor == 4)\n"\ " flat_atomic_add \\vdst, \\vaddr, \\vsrc nt sc1 sc0\n"\ " .else\n"\ " flat_atomic_add \\vdst, \\vaddr, \\vsrc \\arg0 \\arg1\n"\ " .endif\n"\ " .endm\n" /** * Common */ const char *NoopIsa = SHADER_START R"( s_endpgm )"; const char *CopyDwordIsa = SHADER_START SHADER_MACROS_FLAT R"( v_mov_b32 v0, s0 v_mov_b32 v1, s1 v_mov_b32 v2, s2 v_mov_b32 v3, s3 FLAT_LOAD_DWORD_NSS v4, v[0:1] glc slc s_waitcnt 0 FLAT_STORE_DWORD_NSS v[2:3], v4 glc slc s_endpgm )"; const char *InfiniteLoopIsa = SHADER_START R"( .text LOOP: s_branch LOOP s_endpgm )"; const char *AtomicIncIsa = SHADER_START SHADER_MACROS_FLAT R"( v_mov_b32 v0, s0 v_mov_b32 v1, s1 .if (.amdgcn.gfx_generation_number >= 8) v_mov_b32 v2, 1 FLAT_ATOMIC_ADD_NSS v3, v[0:1], v2 glc slc .else v_mov_b32 v2, -1 flat_atomic_inc v3, v[0:1], v2 glc slc .endif s_waitcnt 0 s_endpgm )"; /** * KFDMemoryTest */ const char *ScratchCopyDwordIsa = SHADER_START SHADER_MACROS_FLAT R"( // Copy the parameters from scalar registers to vector registers .if (.amdgcn.gfx_generation_number >= 9) v_mov_b32 v0, s0 v_mov_b32 v1, s1 v_mov_b32 v2, s2 v_mov_b32 v3, s3 .else v_mov_b32_e32 v0, s0 v_mov_b32_e32 v1, s1 v_mov_b32_e32 v2, s2 v_mov_b32_e32 v3, s3 .endif // Setup the scratch parameters. This assumes a single 16-reg block .if (.amdgcn.gfx_generation_number >= 10) s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 .elseif (.amdgcn.gfx_generation_number == 9) s_mov_b32 flat_scratch_lo, s4 s_mov_b32 flat_scratch_hi, s5 .else s_mov_b32 flat_scratch_lo, 8 s_mov_b32 flat_scratch_hi, 0 .endif // Copy a dword between the passed addresses FLAT_LOAD_DWORD_NSS v4, v[0:1] slc s_waitcnt vmcnt(0) & lgkmcnt(0) FLAT_STORE_DWORD_NSS v[2:3], v4 slc s_endpgm )"; /* Continuously poll src buffer and check buffer value * After src buffer is filled with specific value (0x5678, * by host program), fill dst buffer with specific * value(0x5678) and quit */ const char *PollMemoryIsa = SHADER_START R"( // Assume src address in s0, s1, and dst address in s2, s3 s_movk_i32 s18, 0x5678 .if (.amdgcn.gfx_generation_number >= 10) v_mov_b32 v0, s2 v_mov_b32 v1, s3 v_mov_b32 v2, 0x5678 .endif LOOP: s_load_dword s16, s[0:1], 0x0 glc s_cmp_eq_i32 s16, s18 s_cbranch_scc0 LOOP .if (.amdgcn.gfx_generation_number >= 10) flat_store_dword v[0:1], v2 slc .else s_store_dword s18, s[2:3], 0x0 glc .endif s_endpgm )"; /* Similar to PollMemoryIsa except that the buffer * polled can be Non-coherant memory. SCC system-level * cache coherence is not supported in scalar (smem) path. * Use vmem operations with scc */ const char *PollNCMemoryIsa = SHADER_START R"( // Assume src address in s0, s1, and dst address in s2, s3 v_mov_b32 v6, 0x5678 v_mov_b32 v0, s0 v_mov_b32 v1, s1 LOOP: flat_load_dword v4, v[0:1] scc v_cmp_eq_u32 vcc, v4, v6 s_cbranch_vccz LOOP v_mov_b32 v0, s2 v_mov_b32 v1, s3 flat_store_dword v[0:1], v6 scc s_endpgm )"; /* Input: A buffer of at least 3 dwords. * DW0: used as a signal. 0xcafe means it is signaled * DW1: Input buffer for device to read. * DW2: Output buffer for device to write. * Once receive signal, device will copy DW1 to DW2 * This shader continously poll the signal buffer, * Once signal buffer is signaled, it copies input buffer * to output buffer */ const char *CopyOnSignalIsa = SHADER_START R"( // Assume input buffer in s0, s1 .if (.amdgcn.gfx_generation_number >= 10) s_add_u32 s2, s0, 0x8 s_addc_u32 s3, s1, 0x0 s_mov_b32 s18, 0xcafe v_mov_b32 v0, s0 v_mov_b32 v1, s1 v_mov_b32 v4, s2 v_mov_b32 v5, s3 .else s_mov_b32 s18, 0xcafe .endif POLLSIGNAL: s_load_dword s16, s[0:1], 0x0 glc s_cmp_eq_i32 s16, s18 s_cbranch_scc0 POLLSIGNAL s_load_dword s17, s[0:1], 0x4 glc s_waitcnt vmcnt(0) & lgkmcnt(0) .if (.amdgcn.gfx_generation_number >= 10) v_mov_b32 v2, s17 flat_store_dword v[4:5], v2 glc .else s_store_dword s17, s[0:1], 0x8 glc .endif s_waitcnt vmcnt(0) & lgkmcnt(0) s_endpgm )"; /* Continuously poll the flag at src buffer * After the flag of s[0:1] is 1 filled, * copy the value from s[0:1]+4 to dst buffer * * Note: Only works on GFX9 (only used in * aldebaran tests) */ const char *PollAndCopyIsa = SHADER_START SHADER_MACROS_FLAT R"( // Assume src buffer in s[0:1] and dst buffer in s[2:3] // Path for Aldebaran, Aqua Vanjaram .if (.amdgcn.gfx_generation_number == 9 && (.amdgcn.gfx_generation_minor == 4 || .amdgcn.gfx_generation_stepping == 10)) v_mov_b32 v0, s0 v_mov_b32 v1, s1 v_mov_b32 v18, 0x1 LOOP0: FLAT_LOAD_DWORD_NSS v16, v[0:1] glc s_waitcnt vmcnt(0) & lgkmcnt(0) v_cmp_eq_i32 vcc, v16, v18 s_cbranch_vccz LOOP0 .if (.amdgcn.gfx_generation_minor == 4) buffer_inv sc1 sc0 .else buffer_invl2 .endif s_load_dword s17, s[0:1], 0x4 glc s_waitcnt vmcnt(0) & lgkmcnt(0) s_store_dword s17, s[2:3], 0x0 glc s_waitcnt vmcnt(0) & lgkmcnt(0) buffer_wbl2 .elseif (.amdgcn.gfx_generation_number == 9) s_movk_i32 s18, 0x1 LOOP1: s_load_dword s16, s[0:1], 0x0 glc s_cmp_eq_i32 s16, s18 s_cbranch_scc0 LOOP1 s_load_dword s17, s[0:1], 0x4 glc s_waitcnt vmcnt(0) & lgkmcnt(0) s_store_dword s17, s[2:3], 0x0 glc .endif s_waitcnt vmcnt(0) & lgkmcnt(0) s_endpgm )"; /* Input0: A buffer of at least 2 dwords. * DW0: used as a signal. Write 0x1 to signal * DW1: Write the value from 2nd input buffer * for other device to read. * Input1: A buffer of at least 2 dwords. * DW0: used as the value to be written. * * Note: Only works on Aldebaran and Aqua Vanjaram */ const char *WriteFlagAndValueIsa = SHADER_START SHADER_MACROS_FLAT R"( // Assume two inputs buffer in s[0:1] and s[2:3] .if (.amdgcn.gfx_generation_number == 9 && (.amdgcn.gfx_generation_minor == 4 || .amdgcn.gfx_generation_stepping == 10)) v_mov_b32 v0, s0 v_mov_b32 v1, s1 s_load_dword s18, s[2:3], 0x0 glc s_waitcnt vmcnt(0) & lgkmcnt(0) s_store_dword s18, s[0:1], 0x4 glc s_waitcnt vmcnt(0) & lgkmcnt(0) buffer_wbl2 s_waitcnt vmcnt(0) & lgkmcnt(0) v_mov_b32 v16, 0x1 FLAT_STORE_DWORD_NSS v[0:1], v16 glc .endif s_endpgm )"; /* Input0: A buffer of at least 2 dwords. * DW0: used as a signal. Write 0xcafe to signal * DW1: Write to this buffer for other device to read. * Input1: mmio base address */ const char *WriteAndSignalIsa = SHADER_START R"( // Assume input buffer in s0, s1 .if (.amdgcn.gfx_generation_number >= 10) s_add_u32 s4, s0, 0x4 s_addc_u32 s5, s1, 0x0 v_mov_b32 v0, s0 v_mov_b32 v1, s1 v_mov_b32 v2, s2 v_mov_b32 v3, s3 v_mov_b32 v4, s4 v_mov_b32 v5, s5 v_mov_b32 v18, 0xbeef flat_store_dword v[4:5], v18 glc v_mov_b32 v18, 0x1 flat_store_dword v[2:3], v18 glc v_mov_b32 v18, 0xcafe flat_store_dword v[0:1], v18 glc .else s_mov_b32 s18, 0xbeef s_store_dword s18, s[0:1], 0x4 glc s_mov_b32 s18, 0x1 s_store_dword s18, s[2:3], 0 glc s_mov_b32 s18, 0xcafe s_store_dword s18, s[0:1], 0x0 glc .endif s_endpgm )"; /* Input: * s[0:1], A buffer of at least 64 * 6 bytes * * Store the value 0x77 at the 5 addresses 0x40, * 0x80, ..., 0x140 in the buffer * * Aqua Vanjaram only */ const char *FlushBufferForAcquireReleaseIsa = SHADER_START R"( .if (.amdgcn.gfx_generation_number == 9 && .amdgcn.gfx_generation_minor == 4) s_mov_b32 s11, 0x77 s_mov_b32 s12, 0x0 // Store some data on 5 different cache lines s_store_dword s12, s[0:1], 0x0 glc s_store_dword s11, s[0:1], 0x40 glc s_store_dword s11, s[0:1], 0x80 glc s_store_dword s11, s[0:1], 0xc0 glc s_store_dword s11, s[0:1], 0x100 glc s_store_dword s11, s[0:1], 0x140 glc s_waitcnt lgkmcnt(0) .endif s_endpgm )"; /* Input: * s[0:1], A buffer of at least 64 * 6 bytes, * shared with the acquiring shader * * Store the values 1 - 5 at the 5 addresses 0x40, * 0x80, ..., 0x140 in the buffer, then signal * the flag at address 0x0 in the buffer. * * Uses vector stores * * Aqua Vanjaram only */ const char *WriteReleaseVectorIsa = SHADER_START R"( .if (.amdgcn.gfx_generation_number == 9 && .amdgcn.gfx_generation_minor == 4) v_mov_b32 v11, 0x1 v_mov_b32 v12, 0x2 v_mov_b32 v13, 0x3 v_mov_b32 v14, 0x4 v_mov_b32 v15, 0x5 v_mov_b32 v21, 0x40 v_mov_b32 v22, 0x80 v_mov_b32 v23, 0xc0 v_mov_b32 v24, 0x100 v_mov_b32 v25, 0x140 // Store some data on 5 different cache lines global_store_dword v21, v11, s[0:1] global_store_dword v22, v12, s[0:1] global_store_dword v23, v13, s[0:1] global_store_dword v24, v14, s[0:1] global_store_dword v25, v15, s[0:1] nt sc1 sc0 s_waitcnt vmcnt(0) // Write-Release s_mov_b32 s16, 0x1 buffer_wbl2 sc1 sc0 s_waitcnt vmcnt(0) & lgkmcnt(0) s_store_dword s16, s[0:1], 0x0 glc .endif s_endpgm )"; /* Input: * s[0:1], A buffer of at least 64 * 6 bytes, * shared with the acquiring shader * * Store the values 6 - 10 at the 5 addresses 0x40, * 0x80, ..., 0x140 in the buffer, then signal * the flag at address 0x0 in the buffer. * * Uses scalar stores * * Aqua Vanjaram only */ const char *WriteReleaseScalarIsa = SHADER_START R"( .if (.amdgcn.gfx_generation_number == 9 && .amdgcn.gfx_generation_minor == 4) s_mov_b32 s11, 0x6 s_mov_b32 s12, 0x7 s_mov_b32 s13, 0x8 s_mov_b32 s14, 0x9 s_mov_b32 s15, 0xa // Store some data on 5 different cache lines s_store_dword s11, s[0:1], 0x40 s_store_dword s12, s[0:1], 0x80 s_store_dword s13, s[0:1], 0xc0 s_store_dword s14, s[0:1], 0x100 s_store_dword s15, s[0:1], 0x140 glc s_waitcnt lgkmcnt(0) // Write-Release s_dcache_wb // WB Scalar L1 cache s_mov_b32 s16, 0x1 buffer_wbl2 sc1 sc0 s_waitcnt vmcnt(0) & lgkmcnt(0) s_store_dword s16, s[0:1], 0x0 glc s_waitcnt lgkmcnt(0) .endif s_endpgm )"; /* Input: * s[0:1], A buffer of at least 64 * 6 bytes, * shared with the releasing shader * s[2:3], A buffer of at least 64 * 6 bytes, * accessible by the CPU, used for output * * Polls the flag at address 0x0 in the shared buffer. * When the signal is received, read the values * at the 5 addresses 0x40, 0x80, ... 0x140, * and store them at the same locations in * the output buffer * * Uses vector loads * * Aqua Vanjaram only */ const char *ReadAcquireVectorIsa = SHADER_START R"( .if (.amdgcn.gfx_generation_number == 9 && .amdgcn.gfx_generation_minor == 4) // Read-Acquire s_mov_b32 s18, 0x1 LOOP: s_load_dword s17, s[0:1], 0x0 glc s_waitcnt lgkmcnt(0) s_cmp_eq_i32 s17, s18 s_cbranch_scc0 LOOP buffer_inv sc1 sc0 // Load data v_mov_b32 v21, 0x40 v_mov_b32 v22, 0x80 v_mov_b32 v23, 0xc0 v_mov_b32 v24, 0x100 v_mov_b32 v25, 0x140 global_load_dword v11, v21, s[0:1] global_load_dword v12, v22, s[0:1] global_load_dword v13, v23, s[0:1] global_load_dword v14, v24, s[0:1] global_load_dword v15, v25, s[0:1] s_waitcnt vmcnt(0) // Store data for output v_mov_b32 v21, 0x40 v_mov_b32 v22, 0x80 v_mov_b32 v23, 0xc0 v_mov_b32 v24, 0x100 v_mov_b32 v25, 0x140 global_store_dword v21, v11, s[2:3] nt sc1 sc0 global_store_dword v22, v12, s[2:3] nt sc1 sc0 global_store_dword v23, v13, s[2:3] nt sc1 sc0 global_store_dword v24, v14, s[2:3] nt sc1 sc0 global_store_dword v25, v15, s[2:3] nt sc1 sc0 s_waitcnt vmcnt(0) .endif s_endpgm )"; /* Input: * s[0:1], A buffer of at least 64 * 6 bytes, * shared with the releasing shader * s[2:3], A buffer of at least 64 * 6 bytes, * accessible by the CPU, used for output * * Polls the flag at address 0x0 in the shared buffer. * When the signal is received, read the values * at the 5 addresses 0x40, 0x80, ... 0x140, * and store them at the same locations in * the output buffer * * Uses scalar loads * * Aqua Vanjaram only */ const char *ReadAcquireScalarIsa = SHADER_START R"( .if (.amdgcn.gfx_generation_number == 9 && .amdgcn.gfx_generation_minor == 4) // Read-Acquire s_mov_b32 s18, 0x1 LOOP: s_load_dword s17, s[0:1], 0x0 glc s_waitcnt lgkmcnt(0) s_cmp_eq_i32 s17, s18 s_cbranch_scc0 LOOP buffer_inv sc1 sc0 // Load data s_load_dword s21, s[0:1], 0x40 s_load_dword s22, s[0:1], 0x80 s_load_dword s23, s[0:1], 0xc0 s_load_dword s24, s[0:1], 0x100 s_load_dword s25, s[0:1], 0x140 s_waitcnt lgkmcnt(0) // Store data for output s_store_dword s21, s[2:3], 0x40 glc s_store_dword s22, s[2:3], 0x80 glc s_store_dword s23, s[2:3], 0xc0 glc s_store_dword s24, s[2:3], 0x100 glc s_store_dword s25, s[2:3], 0x140 glc s_waitcnt lgkmcnt(0) .endif s_endpgm )"; /** * KFDQMTest */ /* A simple isa loop program with dense mathematic operations * s1 controls the number iterations of the loop * This shader can be used by GFX8, GFX9 and GFX10 */ const char *LoopIsa = SHADER_START R"( s_movk_i32 s0, 0x0008 s_movk_i32 s1, 0x00ff v_mov_b32 v0, 0 v_mov_b32 v1, 0 v_mov_b32 v2, 0 v_mov_b32 v3, 0 v_mov_b32 v4, 0 v_mov_b32 v5, 0 v_mov_b32 v6, 0 v_mov_b32 v7, 0 v_mov_b32 v8, 0 v_mov_b32 v9, 0 v_mov_b32 v10, 0 v_mov_b32 v11, 0 v_mov_b32 v12, 0 v_mov_b32 v13, 0 v_mov_b32 v14, 0 v_mov_b32 v15, 0 v_mov_b32 v16, 0 LOOP: s_mov_b32 s8, s4 s_mov_b32 s9, s1 s_mov_b32 s10, s6 s_mov_b32 s11, s7 s_cmp_le_i32 s1, s0 s_cbranch_scc1 END_OF_PGM v_add_f32 v0, 2.0, v0 v_cvt_f32_i32 v17, s1 s_waitcnt lgkmcnt(0) v_add_f32 v18, s8, v17 v_add_f32 v19, s9, v17 v_add_f32 v20, s10, v17 v_add_f32 v21, s11, v17 v_add_f32 v22, s12, v17 v_add_f32 v23, s13, v17 v_add_f32 v24, s14, v17 v_add_f32 v17, s15, v17 v_log_f32 v25, v18 v_mul_f32 v25, v22, v25 v_exp_f32 v25, v25 v_log_f32 v26, v19 v_mul_f32 v26, v23, v26 v_exp_f32 v26, v26 v_log_f32 v27, v20 v_mul_f32 v27, v24, v27 v_exp_f32 v27, v27 v_log_f32 v28, v21 v_mul_f32 v28, v17, v28 v_exp_f32 v28, v28 v_add_f32 v5, v5, v25 v_add_f32 v6, v6, v26 v_add_f32 v7, v7, v27 v_add_f32 v8, v8, v28 v_mul_f32 v18, 0x3fb8aa3b, v18 v_exp_f32 v18, v18 v_mul_f32 v19, 0x3fb8aa3b, v19 v_exp_f32 v19, v19 v_mul_f32 v20, 0x3fb8aa3b, v20 v_exp_f32 v20, v20 v_mul_f32 v21, 0x3fb8aa3b, v21 v_exp_f32 v21, v21 v_add_f32 v9, v9, v18 v_add_f32 v10, v10, v19 v_add_f32 v11, v11, v20 v_add_f32 v12, v12, v21 v_sqrt_f32 v18, v22 v_sqrt_f32 v19, v23 v_sqrt_f32 v20, v24 v_sqrt_f32 v21, v17 v_add_f32 v13, v13, v18 v_add_f32 v14, v14, v19 v_add_f32 v15, v15, v20 v_add_f32 v16, v16, v21 v_rsq_f32 v18, v22 v_rsq_f32 v19, v23 v_rsq_f32 v20, v24 v_rsq_f32 v17, v17 v_add_f32 v1, v1, v18 v_add_f32 v2, v2, v19 v_add_f32 v3, v3, v20 v_add_f32 v4, v4, v17 s_add_u32 s0, s0, 1 s_branch LOOP END_OF_PGM: s_endpgm )"; /** * KFDCWSRTest */ /* Initial state: * s[0:1] - input buffer base address * s[2:3] - output buffer base address * s4 - workgroup id * v0 - workitem id * Registers: * v0 - calculated workitem = v0 + s4 * NUM_THREADS_X, which is s4 * v[4:5] - corresponding output buf address: s[2:3] + v0 * 4 * v6 - register storing known-value output for mangle testing * v7 - counter */ const char *PersistentIterateIsa = SHADER_START SHADER_MACROS_U32 SHADER_MACROS_FLAT R"( // Compute address of output buffer v_mov_b32 v0, s4 // use workgroup id as index v_lshlrev_b32 v0, 2, v0 // v0 *= 4 V_ADD_CO_U32 v4, s2, v0 // v[4:5] = s[2:3] + v0 * 4 v_mov_b32 v5, s3 // v[4:5] = s[2:3] + v0 * 4 V_ADD_CO_CI_U32 v5, v5, 0 // v[4:5] = s[2:3] + v0 * 4 // Store known-value output in register FLAT_LOAD_DWORD_NSS v6, v[4:5] glc s_waitcnt vmcnt(0) & lgkmcnt(0) // wait for memory reads to finish // Initialize counter v_mov_b32 v7, 0 LOOP: flat_store_dword v[4:5], v6 // store known-val in output V_ADD_CO_U32 v7, 1, v7 // increment counter s_load_dword s6, s[0:1], 0 glc s_waitcnt vmcnt(0) & lgkmcnt(0) // wait for memory reads to finish s_cmp_eq_i32 s6, 0x12345678 // compare input buf to stopval s_cbranch_scc1 L_QUIT // branch if notified to quit by host s_branch LOOP L_QUIT: s_waitcnt vmcnt(0) & lgkmcnt(0) s_endpgm )"; /** * KFDEvictTest */ /* Shader to read local buffers using multiple wavefronts in parallel * until address buffer is filled with specific value 0x5678 by host program, * then each wavefront fills value 0x5678 at corresponding result buffer and quit * * Initial state: * s[0:1] - address buffer base address * s[2:3] - result buffer base address * s4 - workgroup id * v0 - workitem id, always 0 because NUM_THREADS_X(number of threads) in workgroup set to 1 * Registers: * v0 - calculated workitem id, v0 = v0 + s4 * NUM_THREADS_X * v[2:3] - address of corresponding local buf address offset: s[0:1] + v0 * 8 * v[4:5] - corresponding output buf address: s[2:3] + v0 * 4 * v[6:7] - local buf address used for read test * v11 - size of local buffer in MB */ const char *ReadMemoryIsa = SHADER_START SHADER_MACROS_U32 SHADER_MACROS_FLAT R"( // Compute address of corresponding output buffer v_mov_b32 v0, s4 // use workgroup id as index v_lshlrev_b32 v0, 2, v0 // v0 *= 4 V_ADD_CO_U32 v4, s2, v0 // v[4:5] = s[2:3] + v0 * 4 v_mov_b32 v5, s3 // v[4:5] = s[2:3] + v0 * 4 V_ADD_CO_CI_U32 v5, v5, 0 // v[4:5] = s[2:3] + v0 * 4 // Compute input buffer offset used to store corresponding local buffer address v_lshlrev_b32 v0, 1, v0 // v0 *= 8 V_ADD_CO_U32 v2, s0, v0 // v[2:3] = s[0:1] + v0 * 8 v_mov_b32 v3, s1 // v[2:3] = s[0:1] + v0 * 8 V_ADD_CO_CI_U32 v3, v3, 0 // v[2:3] = s[0:1] + v0 * 8 // Load local buffer size from output buffer FLAT_LOAD_DWORD_NSS v11, v[4:5] slc // Load 64bit local buffer address stored at v[2:3] to v[6:7] FLAT_LOAD_DWORDX2_NSS v[6:7], v[2:3] slc s_waitcnt vmcnt(0) & lgkmcnt(0) // wait for memory reads to finish v_mov_b32 v8, 0x5678 s_movk_i32 s8, 0x5678 L_REPEAT: s_load_dword s16, s[0:1], 0x0 glc s_waitcnt vmcnt(0) & lgkmcnt(0) // wait for memory reads to finish s_cmp_eq_i32 s16, s8 s_cbranch_scc1 L_QUIT // if notified to quit by host // Loop read local buffer starting at v[6:7] // every 4k page only read once v_mov_b32 v9, 0 v_mov_b32 v10, 0x1000 // 4k page v_mov_b32 v12, v6 v_mov_b32 v13, v7 L_LOOP_READ: FLAT_LOAD_DWORDX2_NSS v[14:15], v[12:13] slc V_ADD_CO_U32 v9, v9, v10 V_ADD_CO_U32 v12, v12, v10 V_ADD_CO_CI_U32 v13, v13, 0 V_CMP_LT_U32 v9, v11 s_cbranch_vccnz L_LOOP_READ s_branch L_REPEAT L_QUIT: flat_store_dword v[4:5], v8 s_waitcnt vmcnt(0) & lgkmcnt(0) // wait for memory writes to finish s_endpgm )"; /** * KFDGWSTest */ /* Shader to initialize gws counter to 1 */ const char *GwsInitIsa = SHADER_START R"( s_mov_b32 m0, 0 s_nop 0 s_load_dword s16, s[0:1], 0x0 glc s_waitcnt 0 v_mov_b32 v0, s16 s_waitcnt 0 ds_gws_init v0 offset:0 gds s_waitcnt 0 s_endpgm )"; /* Atomically increase a value in memory * This is expected to be executed from * multiple work groups simultaneously. * GWS semaphore is used to guarantee * the operation is atomic. */ const char *GwsAtomicIncreaseIsa = SHADER_START R"( // Assume src address in s0, s1 .if (.amdgcn.gfx_generation_number >= 10) s_mov_b32 m0, 0 s_mov_b32 exec_lo, 0x1 v_mov_b32 v0, s0 v_mov_b32 v1, s1 ds_gws_sema_p offset:0 gds s_waitcnt 0 flat_load_dword v2, v[0:1] glc dlc s_waitcnt 0 v_add_nc_u32 v2, v2, 1 flat_store_dword v[0:1], v2 s_waitcnt_vscnt null, 0 ds_gws_sema_v offset:0 gds .else s_mov_b32 m0, 0 s_nop 0 ds_gws_sema_p offset:0 gds s_waitcnt 0 s_load_dword s16, s[0:1], 0x0 glc s_waitcnt 0 s_add_u32 s16, s16, 1 s_store_dword s16, s[0:1], 0x0 glc s_waitcnt lgkmcnt(0) ds_gws_sema_v offset:0 gds .endif s_waitcnt 0 s_endpgm )"; ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/ShaderStore.hpp000066400000000000000000000042521446477712600245730ustar00rootroot00000000000000/* * Copyright (C) 2021 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _SHADERSTORE_H_ #define _SHADERSTORE_H_ #include /* KFDASMTest List */ extern const std::vector ShaderList; /* Common */ extern const char *NoopIsa; extern const char *CopyDwordIsa; extern const char *InfiniteLoopIsa; extern const char *AtomicIncIsa; /* KFDMemoryTest */ extern const char *ScratchCopyDwordIsa; extern const char *PollMemoryIsa; extern const char *PollNCMemoryIsa; extern const char *CopyOnSignalIsa; extern const char *PollAndCopyIsa; extern const char *WriteFlagAndValueIsa; extern const char *WriteAndSignalIsa; extern const char *WriteReleaseVectorIsa; extern const char *WriteReleaseScalarIsa; extern const char *ReadAcquireVectorIsa; extern const char *ReadAcquireScalarIsa; extern const char *FlushBufferForAcquireReleaseIsa; /* KFDQMTest */ extern const char *LoopIsa; /* KFDCWSRTest */ extern const char *PersistentIterateIsa; /* KFDEvictTest */ extern const char *ReadMemoryIsa; /* KFDGWSTest */ extern const char *GwsInitIsa; extern const char *GwsAtomicIncreaseIsa; #endif // _SHADERSTORE_H_ ROCT-Thunk-Interface-rocm-5.7.0/tests/kfdtest/src/XgmiOptimizedSDMAQueue.hpp000066400000000000000000000030431446477712600266100ustar00rootroot00000000000000/* * Copyright (C) 2014-2019 Advanced Micro Devices, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __KFD_XGMI_OPTIMIZED_SDMA_QUEUE__H__ #define __KFD_XGMI_OPTIMIZED_SDMA_QUEUE__H__ #include "SDMAQueue.hpp" class XgmiOptimizedSDMAQueue : public SDMAQueue { public: XgmiOptimizedSDMAQueue(void) {CMD_NOP = 0;} virtual ~XgmiOptimizedSDMAQueue(void) {} protected: virtual _HSA_QUEUE_TYPE GetQueueType() { return HSA_QUEUE_SDMA_XGMI; } }; #endif // __KFD_XGMI_OPTIMIZED_SDMA_QUEUE__H__ ROCT-Thunk-Interface-rocm-5.7.0/tests/rdma/000077500000000000000000000000001446477712600203245ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/rdma/simple/000077500000000000000000000000001446477712600216155ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/rdma/simple/app/000077500000000000000000000000001446477712600223755ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/rdma/simple/app/CMakeLists.txt000066400000000000000000000004201446477712600251310ustar00rootroot00000000000000cmake_minimum_required (VERSION 2.6) project (rdma_test) link_directories($ENV{ROOT_OF_ROOTS}/out/lib) include_directories($ENV{LIBHSAKMT_ROOT}/include) include_directories(../drv) add_executable(rdma_test rdma_test.cpp) target_link_libraries(rdma_test libhsakmt.so) ROCT-Thunk-Interface-rocm-5.7.0/tests/rdma/simple/app/rdma_test.cpp000066400000000000000000000172571446477712600250770ustar00rootroot00000000000000/* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include "hsakmt.h" #include "amdp2ptest.h" int rdma_fd = -1; void rdma_open() { rdma_fd = open(AMDP2PTEST_DEVICE_PATH, O_RDWR); if (-1 == rdma_fd ) { int ret = errno; fprintf(stderr, "error opening driver (errno=%d/%s)\n", ret, strerror(ret)); exit(EXIT_FAILURE); } } void rdma_close() { int retcode = close(rdma_fd); if (-1 == retcode) { fprintf(stderr, "error closing driver (errno=%d/%s)\n", retcode, strerror(retcode)); exit(EXIT_FAILURE); } rdma_fd = -1; } int rdma_map(uint64_t gpu_ptr, size_t size, void **cpu_ptr) { int ret = 0; *cpu_ptr = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, rdma_fd, gpu_ptr); if (*cpu_ptr == NULL) { int __errno = errno; *cpu_ptr = NULL; fprintf(stderr, "Can't BAR, error=%s(%d) size=%zu offset=%llx\n", strerror(__errno), __errno, size, (long long unsigned)gpu_ptr); ret = __errno; } return ret; } int rdma_unmap(void *cpu_ptr, size_t size) { int ret = 0; int retcode = munmap(cpu_ptr, size); if (-1 == retcode) { int __errno = errno; fprintf(stderr, "can't unmap BAR, error=%s(%d) size=%zu\n", strerror(__errno), __errno, size); ret = __errno; } return ret; } void run_rdma_tests(HSAuint32 Node, HsaMemoryProperties *MemoryProperty) { printf("Size 0x%lx (%ld MB)\n", MemoryProperty->SizeInBytes, MemoryProperty->SizeInBytes / (1024 * 1024)); printf("VirtualBaseAddress 0x%lx\n", MemoryProperty->VirtualBaseAddress); void *cpu_ptr; int ret = 0; void *MemoryAddress = 0; HSAuint64 SizeInBytes = 4096; HsaMemFlags memFlags = {0}; memFlags.ui32.NonPaged = 1; memFlags.ui32.CachePolicy = HSA_CACHING_WRITECOMBINED; memFlags.ui32.NoSubstitute = 1; memFlags.ui32.PageSize = HSA_PAGE_SIZE_4KB; // memFlags.ui32.HostAccess = 1; memFlags.ui32.CoarseGrain = 1; HSAKMT_STATUS status = hsaKmtAllocMemory(Node, SizeInBytes, memFlags, &MemoryAddress); if (status != HSAKMT_STATUS_SUCCESS) { fprintf(stderr, "Failure to allocate memory. Status %d\n", status); exit(EXIT_FAILURE); } printf("Memory allocated. Address 0x%p\n", MemoryAddress); struct AMDRDMA_IOCTL_GET_PAGE_SIZE_PARAM get_page_size = {0}; get_page_size.addr = (uint64_t) MemoryAddress; get_page_size.length = SizeInBytes; ret = ioctl(rdma_fd, AMD2P2PTEST_IOCTL_GET_PAGE_SIZE, &get_page_size); if (ret != 0) { fprintf(stderr, "AMD2P2PTEST_IOCTL_GET_PAGE_SIZE error (errno=%d/%s)\n", ret, strerror(ret)); exit(EXIT_FAILURE); } printf("GPU Page size: 0x%ld\n", get_page_size.page_size); struct AMDRDMA_IOCTL_GET_PAGES_PARAM get_cpu_ptr = {0}; get_cpu_ptr.addr = (uint64_t) MemoryAddress; get_cpu_ptr.length = SizeInBytes; ret = ioctl(rdma_fd, AMD2P2PTEST_IOCTL_GET_PAGES, &get_cpu_ptr); if (ret != 0) { fprintf(stderr, "AMD2P2PTEST_IOCTL_GET_PAGES error (errno=%d/%s)\n", ret, strerror(ret)); exit(EXIT_FAILURE); } ret = rdma_map((uint64_t)MemoryAddress, 4096, &cpu_ptr); if (ret < 0) { exit(EXIT_FAILURE); } printf("CPU Virtual address 0x%p\n", cpu_ptr); hsaKmtFreeMemory(MemoryAddress, SizeInBytes); } int main(void) { HsaVersionInfo VersionInfo; HSAKMT_STATUS status = hsaKmtOpenKFD(); if( status == HSAKMT_STATUS_SUCCESS) { status = hsaKmtGetVersion(&VersionInfo); if(status == HSAKMT_STATUS_SUCCESS) { printf("Kernel Interface Major Version: %d\n", VersionInfo.KernelInterfaceMajorVersion); printf("Kernel Interface Minor Version: %d\n", VersionInfo.KernelInterfaceMinorVersion); } } rdma_open(); HsaSystemProperties SystemProperties = {0}; status = hsaKmtAcquireSystemProperties(&SystemProperties); if(status != HSAKMT_STATUS_SUCCESS) { fprintf(stderr, "hsaKmtAcquireSystemProperties call failed. Error: %d\n", status); exit(EXIT_FAILURE); } printf("System properties: Number of nodes: %d\n", SystemProperties.NumNodes); for (HSAuint32 iNode = 0; iNode < SystemProperties.NumNodes; iNode++) { HsaNodeProperties NodeProperties = {0}; status = hsaKmtGetNodeProperties(iNode, &NodeProperties); if(status != HSAKMT_STATUS_SUCCESS) { fprintf(stderr, "hsaKmtGetNodeProperties (Node = %d) call failed. Error: %d\n", iNode, status); exit(EXIT_FAILURE); } printf("Node %d -> Number of Memory Banks = %d\n", iNode, NodeProperties.NumMemoryBanks); HsaMemoryProperties* MemoryProperties = new HsaMemoryProperties[NodeProperties.NumMemoryBanks]; status = hsaKmtGetNodeMemoryProperties(iNode, NodeProperties.NumMemoryBanks, MemoryProperties); if(status != HSAKMT_STATUS_SUCCESS) { fprintf(stderr, "hsaKmtGetNodeMemoryProperties (Node = %d) call failed. Error: %d\n", iNode, status); exit(EXIT_FAILURE); } for (HSAuint32 iMemBank = 0; iMemBank < NodeProperties.NumMemoryBanks; iMemBank++) { printf("Heap type: %d\n", MemoryProperties[iMemBank].HeapType); if (MemoryProperties[iMemBank].HeapType == HSA_HEAPTYPE_FRAME_BUFFER_PUBLIC) { // We found local memory available for RDMA operation. // Run some tests on it. run_rdma_tests(iNode, &MemoryProperties[iMemBank]); } } } status = hsaKmtReleaseSystemProperties(); if(status != HSAKMT_STATUS_SUCCESS) { fprintf(stderr, "hsaKmtReleaseSystemProperties call failed. Error: %d\n", status); exit(EXIT_FAILURE); } rdma_close(); status = hsaKmtCloseKFD(); if(status != HSAKMT_STATUS_SUCCESS) { fprintf(stderr, "hsaKmtCloseKFD call failed. Error: %d\n", status); exit(EXIT_FAILURE); } return EXIT_SUCCESS; } ROCT-Thunk-Interface-rocm-5.7.0/tests/rdma/simple/drv/000077500000000000000000000000001446477712600224105ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/rdma/simple/drv/Makefile000066400000000000000000000022751446477712600240560ustar00rootroot00000000000000 ifeq ($(src),) src := $$PWD endif ifneq ($(KERNELRELEASE),) # Specify default location of RDMA header RDMA_HEADER_DIR := $(ROOT_OF_ROOTS)/kernel/drivers/gpu/drm/amd/include ifeq ("$(wildcard $(RDMA_HEADER_DIR)/amd_rdma.h)","") RDMA_HEADER_DIR := /usr/src/linux-headers-$(shell uname -r)/drivers/gpu/drm/amd/include ifeq ("$(wildcard $(RDMA_HEADER_DIR)/amd_rdma.h)","") $(error amd_rdma.h header is not found) endif endif $(info INFO: RDMA Header directory is $(RDMA_HEADER_DIR)) kver_major:=$(shell echo $(KERNELRELEASE) | awk -F '.' '// { print $$2;}' ) obj-m += amdp2ptest.o ccflags-y += -I $(RDMA_HEADER_DIR) else KDIR ?= /lib/modules/$(shell uname -r)/build REL := $(subst ., , $(subst -, , $(shell uname -r))) REL_MAJOR := $(word 1,$(REL)) REL_MEDIUM := $(word 2,$(REL)) REL_MINOR := $(word 3,$(REL)) all: default default: @ $(MAKE) -C $(KDIR) M=$$PWD modules install: $(MAKE) -C $(KDIR) M=$$PWD modules_install help: $(MAKE) -C $(KDIR) M=$$PWD help clean: rm -rf *.o *.ko* *.mod.* .*.cmd Module.symvers modules.order .tmp_versions/ *~ core .depend TAGS TAGS: find $(KERNELDIR) -follow -name \*.h -o -name \*.c |xargs etags .PHONY: clean all help install default linksyms endif ROCT-Thunk-Interface-rocm-5.7.0/tests/rdma/simple/drv/amdp2ptest.c000066400000000000000000000274031446477712600246450ustar00rootroot00000000000000/* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "amd_rdma.h" #include "amdp2ptest.h" MODULE_AUTHOR("serguei.sagalovitch@amd.com"); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("AMD RDMA basic API test kernel-mode driver"); MODULE_VERSION("1.0"); const struct amd_rdma_interface *rdma_interface; struct va_pages_node { struct list_head node; struct amd_p2p_page_table *pages; }; struct amdp2ptest_pages_list { struct list_head head; struct mutex lock; }; #define MSG_INFO(fmt, args ...) \ pr_info(AMDP2PTEST_DEVICE_NAME ": " fmt, ## args) #define MSG_ERR(fmt, args ...) \ pr_err(AMDP2PTEST_DEVICE_NAME ": " fmt, ## args) #define MSG_warn(fmt, args ...) \ pr_warn(AMDP2PTEST_DEVICE_NAME ": " fmt, ## args) static void free_callback(struct amd_p2p_page_table *page_table, void *client_priv) { struct va_pages_node *va_pages = NULL; struct amdp2ptest_pages_list *list = client_priv; struct list_head *p, *n; MSG_ERR("Free callback is called on va 0x%llx\n", page_table->va); list_for_each_safe(p, n, &list->head) { va_pages = list_entry(p, struct va_pages_node, node); if (va_pages->pages == page_table) { MSG_INFO("Found free page table to free\n"); mutex_lock(&list->lock); list_del(&va_pages->node); mutex_unlock(&list->lock); kfree(va_pages); /* Note: Do not break from loop to allow test * situation when "get_pages" would be called * on the same memory several times **/ } } } static int amdp2ptest_open(struct inode *inode, struct file *filp) { struct amdp2ptest_pages_list *list; MSG_INFO("Open driver\n"); list = kmalloc(sizeof(struct amdp2ptest_pages_list), GFP_KERNEL); if (!list) { MSG_ERR("Can't alloc kernel memory to store list stucture\n"); return -ENOMEM; } INIT_LIST_HEAD(&list->head); mutex_init(&list->lock); filp->private_data = list; return 0; } static int amdp2ptest_release(struct inode *inode, struct file *filp) { struct va_pages_node *va_pages = NULL; int retcode; struct amdp2ptest_pages_list *list = filp->private_data; struct list_head *p, *n; MSG_INFO("Close driver\n"); list_for_each_safe(p, n, &list->head) { va_pages = list_entry(p, struct va_pages_node, node); MSG_INFO("Free pages: VA 0x%llx\n", va_pages->pages->va); retcode = rdma_interface->put_pages(va_pages->pages); if (retcode != 0) MSG_ERR("Could not put pages back: %d\n", retcode); mutex_lock(&list->lock); list_del(&va_pages->node); mutex_unlock(&list->lock); kfree(va_pages); } filp->private_data = NULL; kfree(list); return 0; } static int ioctl_get_page_size(struct file *filp, unsigned long arg) { struct AMDRDMA_IOCTL_GET_PAGE_SIZE_PARAM params = {0}; unsigned long page_size; int result; MSG_INFO("AMD2P2PTEST_IOCTL_GET_PAGE_SIZE"); if (copy_from_user(¶ms, (void *)arg, sizeof(params))) { MSG_ERR("copy_from_user failed on pointer %p\n", (void *)arg); return -EFAULT; } MSG_INFO("addr %llx, length %llx\n", params.addr, params.length); result = rdma_interface->get_page_size(params.addr, params.length, get_task_pid(current, PIDTYPE_PID), &page_size); if (result) { MSG_ERR("Could not get page size. %d", result); return -EFAULT; } params.page_size = page_size; MSG_INFO("Page size %llx\n", params.page_size); if (copy_to_user((void *)arg, ¶ms, sizeof(params))) { MSG_ERR("copy_to_user failed on user pointer %p\n", (void *)arg); return -EFAULT; } return 0; } static int ioctl_get_pages(struct file *filp, unsigned long arg) { struct va_pages_node *va_pages = NULL; struct amdp2ptest_pages_list *list = filp->private_data; struct AMDRDMA_IOCTL_GET_PAGES_PARAM params = {0}; int result; struct amd_p2p_page_table *pages; MSG_INFO("AMD2P2PTEST_IOCTL_GET_PAGES"); if (copy_from_user(¶ms, (void *)arg, sizeof(params))) { MSG_ERR("copy_from_user failed on pointer %p\n", (void *)arg); return -EFAULT; } MSG_INFO("addr %llx, length %llx\n", params.addr, params.length); result = rdma_interface->get_pages(params.addr, params.length, get_task_pid(current, PIDTYPE_PID), 0, /* There is no dma_device for which to get pages -> no IOMMU support is needed */ &pages, free_callback, list /* Pointer to the list */ ); if (result) { MSG_ERR("Could not get pages table. %d", result); return -EFAULT; } if (copy_to_user((void *)arg, ¶ms, sizeof(params))) { MSG_ERR("copy_to_user failed on user pointer %p\n", (void *)arg); rdma_interface->put_pages(pages); return -EFAULT; } va_pages = kmalloc(sizeof(struct va_pages_node), GFP_KERNEL); if (va_pages == 0) { MSG_ERR("Can't alloc kernel memory\n"); rdma_interface->put_pages(pages); return -ENOMEM; } memset(va_pages, 0, sizeof(struct va_pages_node)); va_pages->pages = pages; mutex_lock(&list->lock); list_add(&va_pages->node, &list->head); mutex_unlock(&list->lock); return 0; } static int ioctl_put_pages(struct file *filp, unsigned long arg) { struct va_pages_node *va_pages = NULL; struct amdp2ptest_pages_list *list = filp->private_data; struct AMDRDMA_IOCTL_PUT_PAGES_PARAM params = {0}; struct list_head *p, *n; int retcode; MSG_INFO("AMD2P2PTEST_IOCTL_PUT_PAGES"); if (copy_from_user(¶ms, (void *)arg, sizeof(params))) { MSG_ERR("copy_from_user failed on pointer %p\n", (void *)arg); return -EFAULT; } MSG_INFO("addr %llx, length %llx\n", params.addr, params.length); list_for_each_safe(p, n, &list->head) { va_pages = list_entry(p, struct va_pages_node, node); if (va_pages->pages->va == params.addr && va_pages->pages->size == params.length) { retcode = rdma_interface->put_pages(va_pages->pages); if (retcode != 0) { MSG_ERR("Could not put pages back: %d\n", retcode); } mutex_lock(&list->lock); list_del(&va_pages->node); mutex_unlock(&list->lock); kfree(va_pages); /* Note: Do not break from loop to allow test * situation when "get_pages" would be called * on the same memory several times **/ } } return 0; } static const struct ioctl_handler_map { int (*handler)(struct file *filp, unsigned long arg); unsigned int cmd; } handlers[] = { { ioctl_get_page_size, AMD2P2PTEST_IOCTL_GET_PAGE_SIZE }, { ioctl_get_pages, AMD2P2PTEST_IOCTL_GET_PAGES }, { ioctl_put_pages, AMD2P2PTEST_IOCTL_PUT_PAGES }, { NULL, 0 } }; static long amdp2ptest_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { int result = -EINVAL; int i; for (i = 0; handlers[i].handler != NULL; i++) if (cmd == handlers[i].cmd) { result = handlers[i].handler(filp, arg); break; } return result; } static int amdp2ptest_mmap(struct file *filp, struct vm_area_struct *vma) { int i; struct scatterlist *sg; struct va_pages_node *va_pages = NULL; struct amdp2ptest_pages_list *list = filp->private_data; size_t size = vma->vm_end - vma->vm_start; struct list_head *p, *n; uint64_t gpu_va = vma->vm_pgoff << PAGE_SHIFT; MSG_INFO("Mapping to CPU user space\n"); MSG_INFO("Begin vm_end 0x%lx, vm_start 0x%lx\n", vma->vm_end, vma->vm_start); MSG_INFO("vm_pgoff / pfn 0x%lx\n", vma->vm_pgoff); MSG_INFO("gpu_va / phys. address 0x%llx\n", gpu_va); if (size != PAGE_SIZE) { MSG_ERR("Mapping works now only per page size=%ld", PAGE_SIZE); return -EINVAL; } /* This is the first very simple version of getting CPU pointer for * the single page. * The logic is the following: * - We get GPU VA address and enumerate list to find "get_pages" * node for such range * - Then we enumerate sg table to find the correct dma_address * * NOTE/TODO: Assumption is that the page size is 4KB to allow testing * of the basic logic. Eventually more complex logic must be added. */ list_for_each_safe(p, n, &list->head) { va_pages = list_entry(p, struct va_pages_node, node); if (va_pages->pages->va >= gpu_va && (va_pages->pages->va + va_pages->pages->size) < vma->vm_end) { MSG_INFO("Found node: va=0x%llx,size=0x%llx,nents %d\n", va_pages->pages->va, va_pages->pages->size, va_pages->pages->pages->nents); for_each_sg(va_pages->pages->pages->sgl, sg, va_pages->pages->pages->nents, i) { if (va_pages->pages->va + (i * sg->length) == gpu_va) { MSG_INFO("Found page[%d]: dma 0x%llx\n", i, sg->dma_address); if (remap_pfn_range(vma, vma->vm_start, sg->dma_address, size, vma->vm_page_prot)) { MSG_ERR("Failed remap_pfn()\n"); return -EINVAL; } return 0; } } } } return -EINVAL; } /*---------------------------------------------------------------------------*/ static const struct file_operations amdp2ptest_fops = { .owner = THIS_MODULE, .unlocked_ioctl = amdp2ptest_unlocked_ioctl, .open = amdp2ptest_open, .release = amdp2ptest_release, .mmap = amdp2ptest_mmap, }; static struct miscdevice amdp2ptest_dev = { /* * We don't care what minor number we end up with, so tell the * kernel to just pick one. */ .minor = MISC_DYNAMIC_MINOR, /* * Name ourselves /dev/hello. */ .name = AMDP2PTEST_DEVICE_NAME, /* * What functions to call when a program performs file * operations on the device. */ .fops = &amdp2ptest_fops, /* Security attribute / access */ .mode = S_IRWXU | S_IRWXG | S_IRWXO }; static int __init amdp2ptest_init(void) { int result; result = amdkfd_query_rdma_interface(&rdma_interface); if (result < 0) { MSG_ERR("Can not get RDMA Interface (result = %d)\n", result); return result; } MSG_INFO("RDMA Interface %p\n", rdma_interface); MSG_INFO(" get_pages %p\n", rdma_interface->get_pages); MSG_INFO(" put_pages %p\n", rdma_interface->put_pages); MSG_INFO(" is_gpu_address %p\n", rdma_interface->is_gpu_address); MSG_INFO(" get_page_size %p\n", rdma_interface->get_page_size); /* * Create the device in the /sys/class/misc directory. * Udev will automatically create the /dev/xxxxx device using * the default rules. */ result = misc_register(&amdp2ptest_dev); if (result < 0) { MSG_ERR("Can not register device (result = %d)\n", result); return result; } return 0; } /* Note: cleanup_module is never called if registering failed */ static void __exit amdp2ptest_cleanup(void) { MSG_INFO("Unregistering\n"); misc_deregister(&amdp2ptest_dev); } module_init(amdp2ptest_init); module_exit(amdp2ptest_cleanup); ROCT-Thunk-Interface-rocm-5.7.0/tests/rdma/simple/drv/amdp2ptest.h000066400000000000000000000042121446477712600246430ustar00rootroot00000000000000/* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef AMDP2PTEST_H_ #define AMDP2PTEST_H_ #include #define AMDP2PTEST_IOCTL_MAGIC 'A' #define AMDP2PTEST_DEVICE_NAME "amdp2ptest" #define AMDP2PTEST_DEVICE_PATH "/dev/amdp2ptest" struct AMDRDMA_IOCTL_GET_PAGE_SIZE_PARAM { /* Input parameters */ uint64_t addr; uint64_t length; /* Output parameters */ uint64_t page_size; }; struct AMDRDMA_IOCTL_GET_PAGES_PARAM { /* Input parameters */ uint64_t addr; uint64_t length; uint64_t is_local; /* 1 if this is the pointer to local allocation */ /* Output parameters */ uint64_t cpu_ptr; }; struct AMDRDMA_IOCTL_PUT_PAGES_PARAM { /* Input parameters */ uint64_t addr; uint64_t length; }; #define AMD2P2PTEST_IOCTL_GET_PAGE_SIZE \ _IOWR(AMDP2PTEST_IOCTL_MAGIC, 1, struct AMDRDMA_IOCTL_GET_PAGE_SIZE_PARAM *) #define AMD2P2PTEST_IOCTL_GET_PAGES \ _IOWR(AMDP2PTEST_IOCTL_MAGIC, 2, struct AMDRDMA_IOCTL_GET_PAGES_PARAM *) #define AMD2P2PTEST_IOCTL_PUT_PAGES \ _IOW(AMDP2PTEST_IOCTL_MAGIC, 3, struct AMDRDMA_IOCTL_PUT_PAGES_PARAM *) #endif /* AMDP2PTEST_H */ ROCT-Thunk-Interface-rocm-5.7.0/tests/reopen/000077500000000000000000000000001446477712600206715ustar00rootroot00000000000000ROCT-Thunk-Interface-rocm-5.7.0/tests/reopen/CMakeLists.txt000066400000000000000000000003561446477712600234350ustar00rootroot00000000000000cmake_minimum_required (VERSION 2.6) project (kmtreopen) link_directories($ENV{ROOT_OF_ROOTS}/out/lib) include_directories($ENV{LIBHSAKMT_ROOT}/include) add_executable(kmtreopen kmtreopen.c) target_link_libraries(kmtreopen libdl.so) ROCT-Thunk-Interface-rocm-5.7.0/tests/reopen/kmtreopen.c000066400000000000000000000077601446477712600230530ustar00rootroot00000000000000#include #include #include #include HSAKMT_STATUS HSAKMTAPI (*pfn_hsaKmtOpenKFD)(void); HSAKMT_STATUS HSAKMTAPI (*pfn_hsaKmtCloseKFD)(void); HSAKMT_STATUS HSAKMTAPI (*pfn_hsaKmtGetVersion)(HsaVersionInfo* VersionInfo); HSAKMT_STATUS HSAKMTAPI (*pfn_hsaKmtAcquireSystemProperties)(HsaSystemProperties* SystemProperties); HSAKMT_STATUS HSAKMTAPI (*pfn_hsaKmtReleaseSystemProperties)(void); HsaVersionInfo g_versionInfo; HsaSystemProperties g_systemProperties; static void hsa_perror(const char *s, HSAKMT_STATUS status) { static const char *errorStrings[] = { [HSAKMT_STATUS_SUCCESS] = "Success", [HSAKMT_STATUS_ERROR] = "General error", [HSAKMT_STATUS_DRIVER_MISMATCH] = "Driver mismatch", [HSAKMT_STATUS_INVALID_PARAMETER] = "Invalid parameter", [HSAKMT_STATUS_INVALID_HANDLE] = "Invalid handle", [HSAKMT_STATUS_INVALID_NODE_UNIT] = "Invalid node or unit", [HSAKMT_STATUS_NO_MEMORY] = "No memory", [HSAKMT_STATUS_BUFFER_TOO_SMALL] = "Buffer too small", [HSAKMT_STATUS_NOT_IMPLEMENTED] = "Not implemented", [HSAKMT_STATUS_NOT_SUPPORTED] = "Not supported", [HSAKMT_STATUS_UNAVAILABLE] = "Unavailable", [HSAKMT_STATUS_KERNEL_IO_CHANNEL_NOT_OPENED] = "Kernel IO channel not opened", [HSAKMT_STATUS_KERNEL_COMMUNICATION_ERROR] = "Kernel communication error", [HSAKMT_STATUS_KERNEL_ALREADY_OPENED] = "Kernel already opened", [HSAKMT_STATUS_HSAMMU_UNAVAILABLE] = "HSA MMU unavailable", [HSAKMT_STATUS_WAIT_FAILURE] = "Wait failure", [HSAKMT_STATUS_WAIT_TIMEOUT] = "Wait timeout", [HSAKMT_STATUS_MEMORY_ALREADY_REGISTERED] = "Memory already registered", [HSAKMT_STATUS_MEMORY_NOT_REGISTERED] = "Memory not registered", [HSAKMT_STATUS_MEMORY_ALIGNMENT] = "Memory alignment error" }; if (status >= 0 && status <= HSAKMT_STATUS_MEMORY_ALIGNMENT) fprintf(stderr, "%s: %s\n", s, errorStrings[status]); else fprintf(stderr, "%s: Unknown error %d\n", s, status); } #define HSA_CHECK_RETURN(call) do { \ HSAKMT_STATUS __ret; \ printf(" Calling %s\n", #call); \ __ret = pfn_##call; \ if (__ret != HSAKMT_STATUS_SUCCESS) { \ hsa_perror(#call, __ret); \ return __ret; \ } \ } while(0) #define HSA_DLSYM(handle, func) do { \ pfn_##func = dlsym(handle, #func); \ if (pfn_##func == NULL) { \ fprintf(stderr, "dlsym failed: %s\n", dlerror()); \ return HSAKMT_STATUS_ERROR; \ } \ } while(0) static int runTest(void *handle) { HSA_DLSYM(handle, hsaKmtOpenKFD); HSA_DLSYM(handle, hsaKmtCloseKFD); HSA_DLSYM(handle, hsaKmtGetVersion); HSA_DLSYM(handle, hsaKmtAcquireSystemProperties); HSA_DLSYM(handle, hsaKmtReleaseSystemProperties); HSA_CHECK_RETURN(hsaKmtOpenKFD()); HSA_CHECK_RETURN(hsaKmtGetVersion(&g_versionInfo)); HSA_CHECK_RETURN(hsaKmtAcquireSystemProperties(&g_systemProperties)); HSA_CHECK_RETURN(hsaKmtReleaseSystemProperties()); HSA_CHECK_RETURN(hsaKmtCloseKFD()); return HSAKMT_STATUS_SUCCESS; } int main(int argc, char *argv[]) { void *handle; int i; for (i = 0; i < 5; i++) { printf("Iteration %d:\n Loading libhsakmt.so\n", i+1); handle = dlopen("libhsakmt.so", RTLD_LAZY); if (handle == NULL) { fprintf(stderr, "dlopen failed: %s\n", dlerror()); exit(1); } if (runTest(handle) != HSAKMT_STATUS_SUCCESS) exit(1); printf(" Unloading libhsakmt.so\n"); if (dlclose(handle) != 0) { fprintf(stderr, "dlclose failed: %s\n", dlerror()); exit(1); } } }