sha1-asm-0.5.1/.cargo_vcs_info.json0000644000000001120000000000000124420ustar { "git": { "sha1": "23540cbcf70408b6df14e5c5cd7cdbb82afe14ac" } } sha1-asm-0.5.1/CHANGELOG.md000064400000000000000000000007440000000000000130340ustar 00000000000000# Changelog All notable changes to this project will be documented in this file. The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/), and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). ## 0.5.1 (2021-07-16) ### Fixed - Builds on iOS/macOS ([#38]) [#38]: https://github.com/RustCrypto/asm-hashes/pull/38 ## 0.5.0 (2021-02-19) ## 0.4.4 ## 0.4.3 ## 0.4.2 ## 0.4.1 ## 0.4.0 ## 0.3.0 ## 0.2.1 ## 0.2.0 ## 0.1.0 sha1-asm-0.5.1/Cargo.toml0000644000000016360000000000000104540ustar # THIS FILE IS AUTOMATICALLY GENERATED BY CARGO # # When uploading crates to the registry Cargo will automatically # "normalize" Cargo.toml files for maximal compatibility # with all versions of Cargo and also rewrite `path` dependencies # to registry (e.g., crates.io) dependencies # # If you believe there's an error in this file please file an # issue against the rust-lang/cargo repository. If you're # editing this file be aware that the upstream Cargo.toml # will likely look very different (and much more reasonable) [package] edition = "2018" name = "sha1-asm" version = "0.5.1" authors = ["RustCrypto Developers"] description = "Assembly implementation of SHA-1 compression function" documentation = "https://docs.rs/sha1-asm" keywords = ["crypto", "sha1", "asm"] categories = ["cryptography", "no-std"] license = "MIT" repository = "https://github.com/RustCrypto/asm-hashes" [build-dependencies.cc] version = "1.0" sha1-asm-0.5.1/Cargo.toml.orig000064400000000000000000000006120000000000000141040ustar 00000000000000[package] name = "sha1-asm" version = "0.5.1" authors = ["RustCrypto Developers"] license = "MIT" description = "Assembly implementation of SHA-1 compression function" documentation = "https://docs.rs/sha1-asm" repository = "https://github.com/RustCrypto/asm-hashes" keywords = ["crypto", "sha1", "asm"] categories = ["cryptography", "no-std"] edition = "2018" [build-dependencies] cc = "1.0" sha1-asm-0.5.1/LICENSE000064400000000000000000000021030000000000000122170ustar 00000000000000Copyright (c) 2015 Project Nayuki Copyright (c) 2017 Artyom Pavlov Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. sha1-asm-0.5.1/benches/lib.rs000064400000000000000000000004440000000000000137430ustar 00000000000000#![no_std] #![feature(test)] extern crate test; use test::Bencher; #[bench] fn bench_compress(b: &mut Bencher) { let mut state = Default::default(); let data = [[0u8; 64]]; b.iter(|| { sha1_asm::compress(&mut state, &data); }); b.bytes = data.len() as u64; } sha1-asm-0.5.1/build.rs000064400000000000000000000013240000000000000126630ustar 00000000000000fn main() { let target_arch = std::env::var("CARGO_CFG_TARGET_ARCH").unwrap_or_default(); let target_vendor = std::env::var("CARGO_CFG_TARGET_VENDOR").unwrap_or_default(); let asm_path = if target_arch == "x86" { "src/x86.S" } else if target_arch == "x86_64" { "src/x64.S" } else if target_arch == "aarch64" && target_vendor == "apple" { "src/aarch64_apple.S" } else if target_arch == "aarch64" { "src/aarch64.S" } else { panic!("Unsupported target architecture"); }; let mut build = cc::Build::new(); if target_arch == "aarch64" { build.flag("-march=armv8-a+crypto"); } build.flag("-c").file(asm_path).compile("libsha1.a"); } sha1-asm-0.5.1/src/aarch64.S000064400000000000000000000116640000000000000133710ustar 00000000000000/* * SHA-1 hash in AArch64 assembly * * Copyright (c) 2020 Emmanuel Gil Peyrot . (MIT License) * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in * the Software without restriction, including without limitation the rights to * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * - The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * - The Software is provided "as is", without warranty of any kind, express or * implied, including but not limited to the warranties of merchantability, * fitness for a particular purpose and noninfringement. In no event shall the * authors or copyright holders be liable for any claim, damages or other * liability, whether in an action of contract, tort or otherwise, arising from, * out of or in connection with the Software or the use or other dealings in the * Software. */ /* void sha1_compress(uint32_t state[5], const uint8_t block[64]) */ .global sha1_compress sha1_compress: /* * Storage usage: * Bytes Location Description * 4 x0 state argument * 4 x1 block argument * 16 q0 W0 * 16 q1 W1 * 16 q2 W2 * 16 q3 W3 * 16 q4 k * 16 q5 Original ABCD * 16 q6 ABCD (with s3 being A) * 4 s16 E * 4 s17 e0 * 4 s18 e1 * 16 q19 wk */ // Load state in registers ldr q5, [x0] ldr s16, [x0, 16] mov v6.16b, v5.16b // Load block in registers ldr q0, [x1] ldr q1, [x1, 16] ldr q2, [x1, 32] ldr q3, [x1, 48] // TODO: only do that on little endian rev32 v0.16b, v0.16b rev32 v1.16b, v1.16b rev32 v2.16b, v2.16b rev32 v3.16b, v3.16b // k for the next five rounds adrp x1, .K0 ldr q4, [x1, #:lo12:.K0] // 0 sha1h s18, s6 add v19.4s, v0.4s, v4.4s sha1c q6, s16, v19.4s sha1su0 v0.4s, v1.4s, v2.4s // 1 sha1h s17, s6 add v19.4s, v1.4s, v4.4s sha1c q6, s18, v19.4s sha1su1 v0.4s, v3.4s sha1su0 v1.4s, v2.4s, v3.4s // 2 sha1h s18, s6 add v19.4s, v2.4s, v4.4s sha1c q6, s17, v19.4s sha1su1 v1.4s, v0.4s sha1su0 v2.4s, v3.4s, v0.4s // 3 sha1h s17, s6 add v19.4s, v3.4s, v4.4s sha1c q6, s18, v19.4s sha1su1 v2.4s, v1.4s sha1su0 v3.4s, v0.4s, v1.4s // 4 sha1h s18, s6 add v19.4s, v0.4s, v4.4s sha1c q6, s17, v19.4s sha1su1 v3.4s, v2.4s sha1su0 v0.4s, v1.4s, v2.4s // k for the next five rounds adrp x1, .K1 ldr q4, [x1, #:lo12:.K1] // 5 sha1h s17, s6 add v19.4s, v1.4s, v4.4s sha1p q6, s18, v19.4s sha1su1 v0.4s, v3.4s sha1su0 v1.4s, v2.4s, v3.4s // 6 sha1h s18, s6 add v19.4s, v2.4s, v4.4s sha1p q6, s17, v19.4s sha1su1 v1.4s, v0.4s sha1su0 v2.4s, v3.4s, v0.4s // 7 sha1h s17, s6 add v19.4s, v3.4s, v4.4s sha1p q6, s18, v19.4s sha1su1 v2.4s, v1.4s sha1su0 v3.4s, v0.4s, v1.4s // 8 sha1h s18, s6 add v19.4s, v0.4s, v4.4s sha1p q6, s17, v19.4s sha1su1 v3.4s, v2.4s sha1su0 v0.4s, v1.4s, v2.4s // 9 sha1h s17, s6 add v19.4s, v1.4s, v4.4s sha1p q6, s18, v19.4s sha1su1 v0.4s, v3.4s sha1su0 v1.4s, v2.4s, v3.4s // k for the next five rounds adrp x1, .K2 ldr q4, [x1, #:lo12:.K2] // 10 sha1h s18, s6 add v19.4s, v2.4s, v4.4s sha1m q6, s17, v19.4s sha1su1 v1.4s, v0.4s sha1su0 v2.4s, v3.4s, v0.4s // 11 sha1h s17, s6 add v19.4s, v3.4s, v4.4s sha1m q6, s18, v19.4s sha1su1 v2.4s, v1.4s sha1su0 v3.4s, v0.4s, v1.4s // 12 sha1h s18, s6 add v19.4s, v0.4s, v4.4s sha1m q6, s17, v19.4s sha1su1 v3.4s, v2.4s sha1su0 v0.4s, v1.4s, v2.4s // 13 sha1h s17, s6 add v19.4s, v1.4s, v4.4s sha1m q6, s18, v19.4s sha1su1 v0.4s, v3.4s sha1su0 v1.4s, v2.4s, v3.4s // 14 sha1h s18, s6 add v19.4s, v2.4s, v4.4s sha1m q6, s17, v19.4s sha1su1 v1.4s, v0.4s sha1su0 v2.4s, v3.4s, v0.4s // k for the next five rounds adrp x1, .K3 ldr q4, [x1, #:lo12:.K3] // 15 sha1h s17, s6 add v19.4s, v3.4s, v4.4s sha1p q6, s18, v19.4s sha1su1 v2.4s, v1.4s sha1su0 v3.4s, v0.4s, v1.4s // 16 sha1h s18, s6 add v19.4s, v0.4s, v4.4s sha1p q6, s17, v19.4s sha1su1 v3.4s, v2.4s // 17 sha1h s17, s6 add v19.4s, v1.4s, v4.4s sha1p q6, s18, v19.4s // 18 sha1h s18, s6 add v19.4s, v2.4s, v4.4s sha1p q6, s17, v19.4s // 19 sha1h s17, s6 add v19.4s, v3.4s, v4.4s sha1p q6, s18, v19.4s // Update state add v6.4s, v6.4s, v5.4s str q6, [x0] add v16.2s, v16.2s, v17.2s str s16, [x0, 16] ret .align 4 .K0: .word 0x5A827999 .word 0x5A827999 .word 0x5A827999 .word 0x5A827999 .K1: .word 0x6ED9EBA1 .word 0x6ED9EBA1 .word 0x6ED9EBA1 .word 0x6ED9EBA1 .K2: .word 0x8F1BBCDC .word 0x8F1BBCDC .word 0x8F1BBCDC .word 0x8F1BBCDC .K3: .word 0xCA62C1D6 .word 0xCA62C1D6 .word 0xCA62C1D6 .word 0xCA62C1D6 sha1-asm-0.5.1/src/aarch64_apple.S000064400000000000000000000117520000000000000145500ustar 00000000000000/* * SHA-1 hash in AArch64 assembly * * Copyright (c) 2020 Emmanuel Gil Peyrot . (MIT License) * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in * the Software without restriction, including without limitation the rights to * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * - The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * - The Software is provided "as is", without warranty of any kind, express or * implied, including but not limited to the warranties of merchantability, * fitness for a particular purpose and noninfringement. In no event shall the * authors or copyright holders be liable for any claim, damages or other * liability, whether in an action of contract, tort or otherwise, arising from, * out of or in connection with the Software or the use or other dealings in the * Software. */ /* void sha1_compress(uint32_t state[5], const uint8_t block[64]) */ .global _sha1_compress _sha1_compress: /* * Storage usage: * Bytes Location Description * 4 x0 state argument * 4 x1 block argument * 16 q0 W0 * 16 q1 W1 * 16 q2 W2 * 16 q3 W3 * 16 q4 k * 16 q5 Original ABCD * 16 q6 ABCD (with s3 being A) * 4 s16 E * 4 s17 e0 * 4 s18 e1 * 16 q19 wk */ // Load state in registers ldr q5, [x0] ldr s16, [x0, 16] mov v6.16b, v5.16b // Load block in registers ldr q0, [x1] ldr q1, [x1, 16] ldr q2, [x1, 32] ldr q3, [x1, 48] // TODO: only do that on little endian rev32 v0.16b, v0.16b rev32 v1.16b, v1.16b rev32 v2.16b, v2.16b rev32 v3.16b, v3.16b // k for the next five rounds adrp x1, .K0@PAGE ldr q4, [x1, #:lo12:.K0@PAGEOFF] // 0 sha1h s18, s6 add v19.4s, v0.4s, v4.4s sha1c q6, s16, v19.4s sha1su0 v0.4s, v1.4s, v2.4s // 1 sha1h s17, s6 add v19.4s, v1.4s, v4.4s sha1c q6, s18, v19.4s sha1su1 v0.4s, v3.4s sha1su0 v1.4s, v2.4s, v3.4s // 2 sha1h s18, s6 add v19.4s, v2.4s, v4.4s sha1c q6, s17, v19.4s sha1su1 v1.4s, v0.4s sha1su0 v2.4s, v3.4s, v0.4s // 3 sha1h s17, s6 add v19.4s, v3.4s, v4.4s sha1c q6, s18, v19.4s sha1su1 v2.4s, v1.4s sha1su0 v3.4s, v0.4s, v1.4s // 4 sha1h s18, s6 add v19.4s, v0.4s, v4.4s sha1c q6, s17, v19.4s sha1su1 v3.4s, v2.4s sha1su0 v0.4s, v1.4s, v2.4s // k for the next five rounds adrp x1, .K1@PAGE ldr q4, [x1, #:lo12:.K1@PAGEOFF] // 5 sha1h s17, s6 add v19.4s, v1.4s, v4.4s sha1p q6, s18, v19.4s sha1su1 v0.4s, v3.4s sha1su0 v1.4s, v2.4s, v3.4s // 6 sha1h s18, s6 add v19.4s, v2.4s, v4.4s sha1p q6, s17, v19.4s sha1su1 v1.4s, v0.4s sha1su0 v2.4s, v3.4s, v0.4s // 7 sha1h s17, s6 add v19.4s, v3.4s, v4.4s sha1p q6, s18, v19.4s sha1su1 v2.4s, v1.4s sha1su0 v3.4s, v0.4s, v1.4s // 8 sha1h s18, s6 add v19.4s, v0.4s, v4.4s sha1p q6, s17, v19.4s sha1su1 v3.4s, v2.4s sha1su0 v0.4s, v1.4s, v2.4s // 9 sha1h s17, s6 add v19.4s, v1.4s, v4.4s sha1p q6, s18, v19.4s sha1su1 v0.4s, v3.4s sha1su0 v1.4s, v2.4s, v3.4s // k for the next five rounds adrp x1, .K2@PAGE ldr q4, [x1, #:lo12:.K2@PAGEOFF] // 10 sha1h s18, s6 add v19.4s, v2.4s, v4.4s sha1m q6, s17, v19.4s sha1su1 v1.4s, v0.4s sha1su0 v2.4s, v3.4s, v0.4s // 11 sha1h s17, s6 add v19.4s, v3.4s, v4.4s sha1m q6, s18, v19.4s sha1su1 v2.4s, v1.4s sha1su0 v3.4s, v0.4s, v1.4s // 12 sha1h s18, s6 add v19.4s, v0.4s, v4.4s sha1m q6, s17, v19.4s sha1su1 v3.4s, v2.4s sha1su0 v0.4s, v1.4s, v2.4s // 13 sha1h s17, s6 add v19.4s, v1.4s, v4.4s sha1m q6, s18, v19.4s sha1su1 v0.4s, v3.4s sha1su0 v1.4s, v2.4s, v3.4s // 14 sha1h s18, s6 add v19.4s, v2.4s, v4.4s sha1m q6, s17, v19.4s sha1su1 v1.4s, v0.4s sha1su0 v2.4s, v3.4s, v0.4s // k for the next five rounds adrp x1, .K3@PAGE ldr q4, [x1, #:lo12:.K3@PAGEOFF] // 15 sha1h s17, s6 add v19.4s, v3.4s, v4.4s sha1p q6, s18, v19.4s sha1su1 v2.4s, v1.4s sha1su0 v3.4s, v0.4s, v1.4s // 16 sha1h s18, s6 add v19.4s, v0.4s, v4.4s sha1p q6, s17, v19.4s sha1su1 v3.4s, v2.4s // 17 sha1h s17, s6 add v19.4s, v1.4s, v4.4s sha1p q6, s18, v19.4s // 18 sha1h s18, s6 add v19.4s, v2.4s, v4.4s sha1p q6, s17, v19.4s // 19 sha1h s17, s6 add v19.4s, v3.4s, v4.4s sha1p q6, s18, v19.4s // Update state add v6.4s, v6.4s, v5.4s str q6, [x0] add v16.2s, v16.2s, v17.2s str s16, [x0, 16] ret .align 4 .K0: .word 0x5A827999 .word 0x5A827999 .word 0x5A827999 .word 0x5A827999 .K1: .word 0x6ED9EBA1 .word 0x6ED9EBA1 .word 0x6ED9EBA1 .word 0x6ED9EBA1 .K2: .word 0x8F1BBCDC .word 0x8F1BBCDC .word 0x8F1BBCDC .word 0x8F1BBCDC .K3: .word 0xCA62C1D6 .word 0xCA62C1D6 .word 0xCA62C1D6 .word 0xCA62C1D6 sha1-asm-0.5.1/src/lib.rs000064400000000000000000000016410000000000000131230ustar 00000000000000//! Assembly implementation of the [SHA-1] compression function. //! //! This crate is not intended for direct use, most users should //! prefer the [`sha-1`] crate with enabled `asm` feature instead. //! //! Only x86, x86-64, and AArch64 architectures are currently supported. //! //! [SHA-1]: https://en.wikipedia.org/wiki/SHA-1 //! [`sha-1`]: https://crates.io/crates/sha-1 #![no_std] #[cfg(not(any(target_arch = "x86_64", target_arch = "x86", target_arch = "aarch64")))] compile_error!("crate can only be used on x86, x86_64 and AArch64 architectures"); #[link(name = "sha1", kind = "static")] extern "C" { fn sha1_compress(state: &mut [u32; 5], block: &[u8; 64]); } /// Safe wrapper around assembly implementation of SHA-1 compression function #[inline] pub fn compress(state: &mut [u32; 5], blocks: &[[u8; 64]]) { for block in blocks { unsafe { sha1_compress(state, block); } } } sha1-asm-0.5.1/src/x64.S000064400000000000000000000176730000000000000125700ustar 00000000000000/* * SHA-1 hash in x86-64 assembly * * Copyright (c) 2015 Project Nayuki. (MIT License) * https://www.nayuki.io/page/fast-sha1-hash-implementation-in-x86-assembly * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in * the Software without restriction, including without limitation the rights to * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * - The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * - The Software is provided "as is", without warranty of any kind, express or * implied, including but not limited to the warranties of merchantability, * fitness for a particular purpose and noninfringement. In no event shall the * authors or copyright holders be liable for any claim, damages or other * liability, whether in an action of contract, tort or otherwise, arising from, * out of or in connection with the Software or the use or other dealings in the * Software. */ /* void sha1_compress(uint32_t state[5], const uint8_t block[64]) */ #ifdef __APPLE__ .globl _sha1_compress _sha1_compress: #else .globl sha1_compress sha1_compress: #endif /* * Storage usage: * Bytes Location Description * 4 eax SHA-1 state variable A * 4 ebx SHA-1 state variable B * 4 ecx SHA-1 state variable C * 4 edx SHA-1 state variable D * 4 ebp SHA-1 state variable E * 4 esi Temporary for calculation per round * 4 edi (Last 64 rounds) temporary for calculation per round * 8 rdi (First 16 rounds) base address of block array argument (read-only) * 8 r8 Base address of state array argument (read-only) * 8 rsp x86-64 stack pointer * 64 [rsp+0] Circular buffer of most recent 16 key schedule items, 4 bytes each * 16 xmm0 Caller's value of rbx (only low 64 bits are used) * 16 xmm1 Caller's value of rbp (only low 64 bits are used) */ #define ROUND0a(a, b, c, d, e, i) \ movl (i*4)(%rdi), %esi; \ bswapl %esi; \ movl %esi, (i*4)(%rsp); \ addl %esi, %e; \ movl %c, %esi; \ xorl %d, %esi; \ andl %b, %esi; \ xorl %d, %esi; \ ROUNDTAIL(a, b, e, i, 0x5A827999) #define SCHEDULE(i, e) \ movl (((i- 3)&0xF)*4)(%rsp), %esi; \ xorl (((i- 8)&0xF)*4)(%rsp), %esi; \ xorl (((i-14)&0xF)*4)(%rsp), %esi; \ xorl (((i-16)&0xF)*4)(%rsp), %esi; \ roll $1, %esi; \ addl %esi, %e; \ movl %esi, ((i&0xF)*4)(%rsp); #define ROUND0b(a, b, c, d, e, i) \ SCHEDULE(i, e) \ movl %c, %esi; \ xorl %d, %esi; \ andl %b, %esi; \ xorl %d, %esi; \ ROUNDTAIL(a, b, e, i, 0x5A827999) #define ROUND1(a, b, c, d, e, i) \ SCHEDULE(i, e) \ movl %b, %esi; \ xorl %c, %esi; \ xorl %d, %esi; \ ROUNDTAIL(a, b, e, i, 0x6ED9EBA1) #define ROUND2(a, b, c, d, e, i) \ SCHEDULE(i, e) \ movl %c, %esi; \ movl %c, %edi; \ orl %d, %esi; \ andl %b, %esi; \ andl %d, %edi; \ orl %edi, %esi; \ ROUNDTAIL(a, b, e, i, -0x70E44324) #define ROUND3(a, b, c, d, e, i) \ SCHEDULE(i, e) \ movl %b, %esi; \ xorl %c, %esi; \ xorl %d, %esi; \ ROUNDTAIL(a, b, e, i, -0x359D3E2A) #define ROUNDTAIL(a, b, e, i, k) \ roll $30, %b; \ leal k(%e,%esi), %e; \ movl %a, %esi; \ roll $5, %esi; \ addl %esi, %e; /* Save registers, allocate scratch space */ movq %rbx, %xmm0 movq %rbp, %xmm1 subq $64, %rsp /* Load arguments */ movq %rdi, %r8 movl 0(%rdi), %eax /* a */ movl 4(%rdi), %ebx /* b */ movl 8(%rdi), %ecx /* c */ movl 12(%rdi), %edx /* d */ movl 16(%rdi), %ebp /* e */ movq %rsi, %rdi /* 80 rounds of hashing */ ROUND0a(eax, ebx, ecx, edx, ebp, 0) ROUND0a(ebp, eax, ebx, ecx, edx, 1) ROUND0a(edx, ebp, eax, ebx, ecx, 2) ROUND0a(ecx, edx, ebp, eax, ebx, 3) ROUND0a(ebx, ecx, edx, ebp, eax, 4) ROUND0a(eax, ebx, ecx, edx, ebp, 5) ROUND0a(ebp, eax, ebx, ecx, edx, 6) ROUND0a(edx, ebp, eax, ebx, ecx, 7) ROUND0a(ecx, edx, ebp, eax, ebx, 8) ROUND0a(ebx, ecx, edx, ebp, eax, 9) ROUND0a(eax, ebx, ecx, edx, ebp, 10) ROUND0a(ebp, eax, ebx, ecx, edx, 11) ROUND0a(edx, ebp, eax, ebx, ecx, 12) ROUND0a(ecx, edx, ebp, eax, ebx, 13) ROUND0a(ebx, ecx, edx, ebp, eax, 14) ROUND0a(eax, ebx, ecx, edx, ebp, 15) ROUND0b(ebp, eax, ebx, ecx, edx, 16) ROUND0b(edx, ebp, eax, ebx, ecx, 17) ROUND0b(ecx, edx, ebp, eax, ebx, 18) ROUND0b(ebx, ecx, edx, ebp, eax, 19) ROUND1(eax, ebx, ecx, edx, ebp, 20) ROUND1(ebp, eax, ebx, ecx, edx, 21) ROUND1(edx, ebp, eax, ebx, ecx, 22) ROUND1(ecx, edx, ebp, eax, ebx, 23) ROUND1(ebx, ecx, edx, ebp, eax, 24) ROUND1(eax, ebx, ecx, edx, ebp, 25) ROUND1(ebp, eax, ebx, ecx, edx, 26) ROUND1(edx, ebp, eax, ebx, ecx, 27) ROUND1(ecx, edx, ebp, eax, ebx, 28) ROUND1(ebx, ecx, edx, ebp, eax, 29) ROUND1(eax, ebx, ecx, edx, ebp, 30) ROUND1(ebp, eax, ebx, ecx, edx, 31) ROUND1(edx, ebp, eax, ebx, ecx, 32) ROUND1(ecx, edx, ebp, eax, ebx, 33) ROUND1(ebx, ecx, edx, ebp, eax, 34) ROUND1(eax, ebx, ecx, edx, ebp, 35) ROUND1(ebp, eax, ebx, ecx, edx, 36) ROUND1(edx, ebp, eax, ebx, ecx, 37) ROUND1(ecx, edx, ebp, eax, ebx, 38) ROUND1(ebx, ecx, edx, ebp, eax, 39) ROUND2(eax, ebx, ecx, edx, ebp, 40) ROUND2(ebp, eax, ebx, ecx, edx, 41) ROUND2(edx, ebp, eax, ebx, ecx, 42) ROUND2(ecx, edx, ebp, eax, ebx, 43) ROUND2(ebx, ecx, edx, ebp, eax, 44) ROUND2(eax, ebx, ecx, edx, ebp, 45) ROUND2(ebp, eax, ebx, ecx, edx, 46) ROUND2(edx, ebp, eax, ebx, ecx, 47) ROUND2(ecx, edx, ebp, eax, ebx, 48) ROUND2(ebx, ecx, edx, ebp, eax, 49) ROUND2(eax, ebx, ecx, edx, ebp, 50) ROUND2(ebp, eax, ebx, ecx, edx, 51) ROUND2(edx, ebp, eax, ebx, ecx, 52) ROUND2(ecx, edx, ebp, eax, ebx, 53) ROUND2(ebx, ecx, edx, ebp, eax, 54) ROUND2(eax, ebx, ecx, edx, ebp, 55) ROUND2(ebp, eax, ebx, ecx, edx, 56) ROUND2(edx, ebp, eax, ebx, ecx, 57) ROUND2(ecx, edx, ebp, eax, ebx, 58) ROUND2(ebx, ecx, edx, ebp, eax, 59) ROUND3(eax, ebx, ecx, edx, ebp, 60) ROUND3(ebp, eax, ebx, ecx, edx, 61) ROUND3(edx, ebp, eax, ebx, ecx, 62) ROUND3(ecx, edx, ebp, eax, ebx, 63) ROUND3(ebx, ecx, edx, ebp, eax, 64) ROUND3(eax, ebx, ecx, edx, ebp, 65) ROUND3(ebp, eax, ebx, ecx, edx, 66) ROUND3(edx, ebp, eax, ebx, ecx, 67) ROUND3(ecx, edx, ebp, eax, ebx, 68) ROUND3(ebx, ecx, edx, ebp, eax, 69) ROUND3(eax, ebx, ecx, edx, ebp, 70) ROUND3(ebp, eax, ebx, ecx, edx, 71) ROUND3(edx, ebp, eax, ebx, ecx, 72) ROUND3(ecx, edx, ebp, eax, ebx, 73) ROUND3(ebx, ecx, edx, ebp, eax, 74) ROUND3(eax, ebx, ecx, edx, ebp, 75) ROUND3(ebp, eax, ebx, ecx, edx, 76) ROUND3(edx, ebp, eax, ebx, ecx, 77) ROUND3(ecx, edx, ebp, eax, ebx, 78) ROUND3(ebx, ecx, edx, ebp, eax, 79) /* Save updated state */ addl %eax, 0(%r8) addl %ebx, 4(%r8) addl %ecx, 8(%r8) addl %edx, 12(%r8) addl %ebp, 16(%r8) /* Restore registers */ movq %xmm0, %rbx movq %xmm1, %rbp addq $64, %rsp retq sha1-asm-0.5.1/src/x86.S000064400000000000000000000200320000000000000125530ustar 00000000000000/* * SHA-1 hash in x86 assembly * * Copyright (c) 2014 Project Nayuki. (MIT License) * https://www.nayuki.io/page/fast-sha1-hash-implementation-in-x86-assembly * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in * the Software without restriction, including without limitation the rights to * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * - The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * - The Software is provided "as is", without warranty of any kind, express or * implied, including but not limited to the warranties of merchantability, * fitness for a particular purpose and noninfringement. In no event shall the * authors or copyright holders be liable for any claim, damages or other * liability, whether in an action of contract, tort or otherwise, arising from, * out of or in connection with the Software or the use or other dealings in the * Software. */ /* void sha1_compress(uint32_t state[5], const uint8_t block[64]) */ #ifdef __APPLE__ .globl _sha1_compress _sha1_compress: #else .globl sha1_compress sha1_compress: #endif /* * Storage usage: * Bytes Location Description * 4 eax SHA-1 state variable A * 4 ebx SHA-1 state variable B * 4 ecx SHA-1 state variable C * 4 edx SHA-1 state variable D * 4 ebp SHA-1 state variable E * 4 esi Temporary for calculation per round * 4 edi (First 16 rounds) base address of block array argument (read-only); (last 64 rounds) temporary for calculation per round * 4 esp x86 stack pointer * 64 [esp+ 0] Circular buffer of most recent 16 key schedule items, 4 bytes each * 4 [esp+64] Caller's value of ebx * 4 [esp+68] Caller's value of esi * 4 [esp+72] Caller's value of edi * 4 [esp+76] Caller's value of ebp */ #define ROUND0a(a, b, c, d, e, i) \ movl (i*4)(%edi), %esi; \ bswapl %esi; \ movl %esi, (i*4)(%esp); \ addl %esi, %e; \ movl %c, %esi; \ xorl %d, %esi; \ andl %b, %esi; \ xorl %d, %esi; \ ROUNDTAIL(a, b, e, i, 0x5A827999) #define SCHEDULE(i, e) \ movl (((i- 3)&0xF)*4)(%esp), %esi; \ xorl (((i- 8)&0xF)*4)(%esp), %esi; \ xorl (((i-14)&0xF)*4)(%esp), %esi; \ xorl (((i-16)&0xF)*4)(%esp), %esi; \ roll $1, %esi; \ addl %esi, %e; \ movl %esi, ((i&0xF)*4)(%esp); #define ROUND0b(a, b, c, d, e, i) \ SCHEDULE(i, e) \ movl %c, %esi; \ xorl %d, %esi; \ andl %b, %esi; \ xorl %d, %esi; \ ROUNDTAIL(a, b, e, i, 0x5A827999) #define ROUND1(a, b, c, d, e, i) \ SCHEDULE(i, e) \ movl %b, %esi; \ xorl %c, %esi; \ xorl %d, %esi; \ ROUNDTAIL(a, b, e, i, 0x6ED9EBA1) #define ROUND2(a, b, c, d, e, i) \ SCHEDULE(i, e) \ movl %c, %esi; \ movl %c, %edi; \ orl %d, %esi; \ andl %b, %esi; \ andl %d, %edi; \ orl %edi, %esi; \ ROUNDTAIL(a, b, e, i, 0x8F1BBCDC) #define ROUND3(a, b, c, d, e, i) \ SCHEDULE(i, e) \ movl %b, %esi; \ xorl %c, %esi; \ xorl %d, %esi; \ ROUNDTAIL(a, b, e, i, 0xCA62C1D6) #define ROUNDTAIL(a, b, e, i, k) \ roll $30, %b; \ leal k(%e,%esi), %e; \ movl %a, %esi; \ roll $5, %esi; \ addl %esi, %e; /* Save registers */ subl $80, %esp movl %ebx, 64(%esp) movl %esi, 68(%esp) movl %edi, 72(%esp) movl %ebp, 76(%esp) /* Load arguments */ movl 84(%esp), %esi /* state */ movl 88(%esp), %edi /* block */ movl 0(%esi), %eax /* a */ movl 4(%esi), %ebx /* b */ movl 8(%esi), %ecx /* c */ movl 12(%esi), %edx /* d */ movl 16(%esi), %ebp /* e */ /* 80 rounds of hashing */ ROUND0a(eax, ebx, ecx, edx, ebp, 0) ROUND0a(ebp, eax, ebx, ecx, edx, 1) ROUND0a(edx, ebp, eax, ebx, ecx, 2) ROUND0a(ecx, edx, ebp, eax, ebx, 3) ROUND0a(ebx, ecx, edx, ebp, eax, 4) ROUND0a(eax, ebx, ecx, edx, ebp, 5) ROUND0a(ebp, eax, ebx, ecx, edx, 6) ROUND0a(edx, ebp, eax, ebx, ecx, 7) ROUND0a(ecx, edx, ebp, eax, ebx, 8) ROUND0a(ebx, ecx, edx, ebp, eax, 9) ROUND0a(eax, ebx, ecx, edx, ebp, 10) ROUND0a(ebp, eax, ebx, ecx, edx, 11) ROUND0a(edx, ebp, eax, ebx, ecx, 12) ROUND0a(ecx, edx, ebp, eax, ebx, 13) ROUND0a(ebx, ecx, edx, ebp, eax, 14) ROUND0a(eax, ebx, ecx, edx, ebp, 15) ROUND0b(ebp, eax, ebx, ecx, edx, 16) ROUND0b(edx, ebp, eax, ebx, ecx, 17) ROUND0b(ecx, edx, ebp, eax, ebx, 18) ROUND0b(ebx, ecx, edx, ebp, eax, 19) ROUND1(eax, ebx, ecx, edx, ebp, 20) ROUND1(ebp, eax, ebx, ecx, edx, 21) ROUND1(edx, ebp, eax, ebx, ecx, 22) ROUND1(ecx, edx, ebp, eax, ebx, 23) ROUND1(ebx, ecx, edx, ebp, eax, 24) ROUND1(eax, ebx, ecx, edx, ebp, 25) ROUND1(ebp, eax, ebx, ecx, edx, 26) ROUND1(edx, ebp, eax, ebx, ecx, 27) ROUND1(ecx, edx, ebp, eax, ebx, 28) ROUND1(ebx, ecx, edx, ebp, eax, 29) ROUND1(eax, ebx, ecx, edx, ebp, 30) ROUND1(ebp, eax, ebx, ecx, edx, 31) ROUND1(edx, ebp, eax, ebx, ecx, 32) ROUND1(ecx, edx, ebp, eax, ebx, 33) ROUND1(ebx, ecx, edx, ebp, eax, 34) ROUND1(eax, ebx, ecx, edx, ebp, 35) ROUND1(ebp, eax, ebx, ecx, edx, 36) ROUND1(edx, ebp, eax, ebx, ecx, 37) ROUND1(ecx, edx, ebp, eax, ebx, 38) ROUND1(ebx, ecx, edx, ebp, eax, 39) ROUND2(eax, ebx, ecx, edx, ebp, 40) ROUND2(ebp, eax, ebx, ecx, edx, 41) ROUND2(edx, ebp, eax, ebx, ecx, 42) ROUND2(ecx, edx, ebp, eax, ebx, 43) ROUND2(ebx, ecx, edx, ebp, eax, 44) ROUND2(eax, ebx, ecx, edx, ebp, 45) ROUND2(ebp, eax, ebx, ecx, edx, 46) ROUND2(edx, ebp, eax, ebx, ecx, 47) ROUND2(ecx, edx, ebp, eax, ebx, 48) ROUND2(ebx, ecx, edx, ebp, eax, 49) ROUND2(eax, ebx, ecx, edx, ebp, 50) ROUND2(ebp, eax, ebx, ecx, edx, 51) ROUND2(edx, ebp, eax, ebx, ecx, 52) ROUND2(ecx, edx, ebp, eax, ebx, 53) ROUND2(ebx, ecx, edx, ebp, eax, 54) ROUND2(eax, ebx, ecx, edx, ebp, 55) ROUND2(ebp, eax, ebx, ecx, edx, 56) ROUND2(edx, ebp, eax, ebx, ecx, 57) ROUND2(ecx, edx, ebp, eax, ebx, 58) ROUND2(ebx, ecx, edx, ebp, eax, 59) ROUND3(eax, ebx, ecx, edx, ebp, 60) ROUND3(ebp, eax, ebx, ecx, edx, 61) ROUND3(edx, ebp, eax, ebx, ecx, 62) ROUND3(ecx, edx, ebp, eax, ebx, 63) ROUND3(ebx, ecx, edx, ebp, eax, 64) ROUND3(eax, ebx, ecx, edx, ebp, 65) ROUND3(ebp, eax, ebx, ecx, edx, 66) ROUND3(edx, ebp, eax, ebx, ecx, 67) ROUND3(ecx, edx, ebp, eax, ebx, 68) ROUND3(ebx, ecx, edx, ebp, eax, 69) ROUND3(eax, ebx, ecx, edx, ebp, 70) ROUND3(ebp, eax, ebx, ecx, edx, 71) ROUND3(edx, ebp, eax, ebx, ecx, 72) ROUND3(ecx, edx, ebp, eax, ebx, 73) ROUND3(ebx, ecx, edx, ebp, eax, 74) ROUND3(eax, ebx, ecx, edx, ebp, 75) ROUND3(ebp, eax, ebx, ecx, edx, 76) ROUND3(edx, ebp, eax, ebx, ecx, 77) ROUND3(ecx, edx, ebp, eax, ebx, 78) ROUND3(ebx, ecx, edx, ebp, eax, 79) /* Save updated state */ movl 84(%esp), %esi addl %eax, 0(%esi) addl %ebx, 4(%esi) addl %ecx, 8(%esi) addl %edx, 12(%esi) addl %ebp, 16(%esi) /* Restore registers */ movl 64(%esp), %ebx movl 68(%esp), %esi movl 72(%esp), %edi movl 76(%esp), %ebp addl $80, %esp retl