target-features-0.1.6/.cargo_vcs_info.json0000644000000001550000000000100141430ustar { "git": { "sha1": "c459fffbd0c1c9a63c52b39d5779a93846515b9d" }, "path_in_vcs": "target-features" }target-features-0.1.6/.gitignore000064400000000000000000000000241046102023000147160ustar 00000000000000/target /Cargo.lock target-features-0.1.6/Cargo.lock0000644000000002370000000000100121170ustar # This file is automatically @generated by Cargo. # It is not intended for manual editing. version = 3 [[package]] name = "target-features" version = "0.1.6" target-features-0.1.6/Cargo.toml0000644000000015460000000000100121460ustar # THIS FILE IS AUTOMATICALLY GENERATED BY CARGO # # When uploading crates to the registry Cargo will automatically # "normalize" Cargo.toml files for maximal compatibility # with all versions of Cargo and also rewrite `path` dependencies # to registry (e.g., crates.io) dependencies. # # If you are reading this file be aware that the original Cargo.toml # will likely look very different (and much more reasonable). # See Cargo.toml.orig for the original contents. [package] edition = "2021" rust-version = "1.61" name = "target-features" version = "0.1.6" authors = ["Caleb Zulawski "] description = "Rust compiler target feature database" readme = "README.md" categories = [ "hardware-support", "no-std", ] license = "MIT OR Apache-2.0" repository = "https://github.com/calebzulawski/target-features" resolver = "1" [dependencies] target-features-0.1.6/Cargo.toml.orig000064400000000000000000000007331046102023000156240ustar 00000000000000[package] name = "target-features" authors = ["Caleb Zulawski "] version = "0.1.6" edition = "2021" rust-version = "1.61" license = "MIT OR Apache-2.0" description = "Rust compiler target feature database" repository = "https://github.com/calebzulawski/target-features" categories = ["hardware-support", "no-std"] readme = "README.md" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [dependencies] target-features-0.1.6/LICENSE-APACHE000064400000000000000000000261361046102023000146660ustar 00000000000000 Apache License Version 2.0, January 2004 http://www.apache.org/licenses/ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 1. 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See the License for the specific language governing permissions and limitations under the License. target-features-0.1.6/LICENSE-MIT000064400000000000000000000020361046102023000143670ustar 00000000000000Copyright 2022 Caleb Zulawski Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. target-features-0.1.6/README.md000064400000000000000000000015111046102023000142070ustar 00000000000000Target Features =============== [![Build Status](https://github.com/calebzulawski/target-features/workflows/Build/badge.svg?branch=master)](https://github.com/calebzulawski/target-features/actions) ![Rustc Version 1.61+](https://img.shields.io/badge/rustc-1.61+-lightgray.svg) [![License](https://img.shields.io/crates/l/target-features)](https://crates.io/crates/target-features) [![Crates.io](https://img.shields.io/crates/v/target-features)](https://crates.io/crates/target-features) [![Rust Documentation](https://img.shields.io/badge/api-rustdoc-blue.svg)](https://docs.rs/target-features) Target feature database for the Rust compiler. ## License This crate is distributed under the terms of both the MIT license and the Apache License (Version 2.0). See [LICENSE-APACHE](LICENSE-APACHE) and [LICENSE-MIT](LICENSE-MIT) for details. target-features-0.1.6/build.rs000064400000000000000000000163731046102023000144110ustar 00000000000000use std::{collections::HashMap, error::Error, fs::File, io::Write, path::Path}; fn main() -> Result<(), Box> { let rustc_version = include_str!("rustc-version.txt").trim(); let target_features = include_str!("target-features.txt"); let target_cpus = include_str!("target-cpus.txt"); let out_dir = std::env::var_os("OUT_DIR").unwrap(); // Parse the generated features file let mut lines = target_features.lines().peekable(); let mut features = Vec::new(); while lines.peek().is_some() { let feature = lines .next() .unwrap() .strip_prefix("feature =") .unwrap() .trim(); let arch = lines.next().unwrap().strip_prefix("arch =").unwrap().trim(); let implies = lines .next() .unwrap() .strip_prefix("implies =") .unwrap() .trim() .split(' ') .filter(|s| !s.is_empty()) .collect::>(); let description = lines .next() .unwrap() .strip_prefix("description =") .unwrap() .trim(); let _ = lines.next(); features.push((feature, arch, description, implies)); } // Parse the generated CPUs file let mut lines = target_cpus.lines().peekable(); let mut cpus = Vec::new(); while lines.peek().is_some() { let cpu = lines.next().unwrap().strip_prefix("cpu =").unwrap().trim(); let arch = lines.next().unwrap().strip_prefix("arch =").unwrap().trim(); let features = lines .next() .unwrap() .strip_prefix("features =") .unwrap() .trim() .split(' ') .filter(|s| !s.is_empty()) .collect::>(); let _ = lines.next(); cpus.push((cpu, arch, features)); } // Write the generated docs let mut rustc_docs = File::create(Path::new(&out_dir).join("generated.md"))?; writeln!(rustc_docs, "Generated with {rustc_version}.")?; // Write a module let mut module = File::create(Path::new(&out_dir).join("generated.rs"))?; // Generate the features array writeln!( module, "const FEATURES: &[(crate::Architecture, &str, &str, &[Feature])] = &[" )?; for (feature, arch, description, implies) in &features { let implies = implies .iter() .map(|implied_feature| { format!( "Feature({})", features .iter() .position(|(f, a, _, _)| implied_feature == f && arch == a) .unwrap() ) }) .collect::>() .join(", "); writeln!( module, " (crate::Architecture::{arch}, \"{feature}\", \"{description}\", &[{implies}])," )?; } writeln!(module, "];")?; // Generate the CPUs array writeln!( module, "const CPUS: &[(crate::Architecture, &str, &[Feature])] = &[" )?; for (cpu, arch, cpu_features) in &cpus { let cpu_features = cpu_features .iter() .map(|feature| { format!( "Feature({})", features .iter() .position(|(f, a, _, _)| feature == f && arch == a) .unwrap() ) }) .collect::>() .join(", "); writeln!( module, " (crate::Architecture::{arch}, \"{cpu}\", &[{cpu_features}])," )?; } writeln!(module, "];")?; let build_features = std::env::var("CARGO_CFG_TARGET_FEATURE") .map(|x| x.split(',').map(ToString::to_string).collect()) .unwrap_or_else(|_| Vec::new()); let build_arch = match std::env::var("CARGO_CFG_TARGET_ARCH").unwrap().as_str() { "arm" => "Arm", "aarch64" => "AArch64", "bpf" => "Bpf", "hexagon" => "Hexagon", "mips" | "mips64" => "Mips", "powerpc" | "powerpc64" => "PowerPC", "riscv32" | "riscv64" => "RiscV", "wasm32" | "wasm64" => "Wasm", "x86" | "x86_64" => "X86", _ => "Unsupported", }; writeln!(module, "/// The target of the current build.")?; writeln!(module, "#[allow(clippy::let_and_return)]")?; writeln!(module, "pub const CURRENT_TARGET: Target = {{")?; writeln!(module, " let arch = Architecture::{build_arch};")?; writeln!(module, " let target = Target::new(arch);")?; for feature in build_features { writeln!(module, " let target = if let Ok(feature) = Feature::new(arch, \"{feature}\") {{ target.with_feature(feature) }} else {{ target }};")?; } writeln!(module, " target")?; writeln!(module, "}};")?; // Generate the features docs let mut docs = File::create(Path::new(&out_dir).join("docs.rs"))?; let mut by_arch = HashMap::<_, (Vec<_>, Vec<_>)>::new(); for (feature, arch, description, implies) in features { by_arch .entry(arch) .or_default() .0 .push((feature, description, implies)); } for (cpu, arch, features) in cpus { by_arch.entry(arch).or_default().1.push((cpu, features)); } let mut by_arch = by_arch.drain().collect::>(); by_arch.sort(); for (arch, (features, cpus)) in by_arch.drain(..) { writeln!(docs, "/// {} documentation", arch.to_lowercase())?; writeln!(docs, "///")?; writeln!(docs, "/// ## Features")?; writeln!( docs, "/// | Feature | Description | Also Enables† |" )?; writeln!( docs, "/// | ------- | ----------- | ------------------------ |" )?; for (feature, description, implies) in features { write!(docs, "/// | `{feature}` | {description} | ")?; for (i, feature) in implies.into_iter().enumerate() { if i != 0 { write!(docs, ", ")?; } write!(docs, "`{feature}`")?; } writeln!(docs, " |")?; } writeln!(docs, "///")?; writeln!(docs, "/// † This is often empirical, rather than specified in any standard, i.e. all available CPUs with a particular feature also have another feature.")?; writeln!(docs, "///")?; writeln!(docs, "/// ## CPUs")?; writeln!(docs, "/// | CPU | Enabled Features |")?; writeln!(docs, "/// | --- | -------- |")?; for (cpu, features) in cpus { writeln!( docs, "/// | `{cpu}` | {} |", features .iter() .map(|f| format!("`{f}`")) .collect::>() .join(", ") )?; } writeln!(docs, "pub mod {} {{}}", arch.to_lowercase())?; } // Rerun build if the source features changed println!("cargo:rerun-if-changed=rustc-version.txt"); println!("cargo:rerun-if-changed=target-features.txt"); println!("cargo:rerun-if-changed=target-cpus.txt"); println!("cargo:rerun-if-changed=build.rs"); Ok(()) } target-features-0.1.6/examples/proof-token.rs000064400000000000000000000061641046102023000173700ustar 00000000000000// This example demonstrates using `Target` to create a "proof token type", a token that // demonstrates that particular target features have already been detected, and that those features // can be used safely. #![allow(unused, unused_macros, unused_imports)] use target_features::Target; /// Make sure proof tokens can't be improperly constructed mod unconstructible { pub struct Unconstructible(()); impl Unconstructible { pub unsafe fn new() -> Self { Self(()) } } } use unconstructible::Unconstructible; /// Proof of target feature support. /// /// # Safety /// The type must be implemented such that it's impossible to safely construct without ensuring the /// specified target features are supported. unsafe trait Proof: Sized { /// The proven target const TARGET: Target; /// Detect the support for the target features fn detect() -> Option; /// Assume the target features are supported /// /// # Safety /// Calling this is undefined if the target features are not supported unsafe fn assume() -> Self; } /// Make a proof token type for a particular set of features macro_rules! make_target_proof { { $vis:vis struct $proof:ident($($feature:tt),*); } => { $vis struct $proof(Unconstructible); unsafe impl Proof for $proof { // Build on the already-known target features const TARGET: Target = target_features::CURRENT_TARGET$(.with_feature_str($feature))*; fn detect() -> Option { if true $(&& is_x86_feature_detected!($feature))* { unsafe { Some(Self::assume()) } } else { None } } unsafe fn assume() -> Self { Self(Unconstructible::new()) } } } } /// A function that can only be called with the "avx" feature, or panics otherwise. #[cfg(target_arch = "x86_64")] fn safe_avx_fn(_: P) { #[target_feature(enable = "avx")] unsafe fn unsafe_avx_fn() { println!("called an avx function") } // Future improvements to const generics might make it possible to assert this at compile time. // Since P::TARGET is const, this assert disappears if the required features are present. assert!( P::TARGET.supports_feature_str("avx"), "avx feature not supported" ); unsafe { unsafe_avx_fn() } } #[cfg(target_arch = "x86_64")] fn main() { // The function can be called with the exact features make_target_proof! { struct Avx("avx"); } if let Some(proof) = Avx::detect() { safe_avx_fn(proof); } // The function can also be called with a target that implies the required features make_target_proof! { struct Avx2("avx2"); } if let Some(proof) = Avx2::detect() { safe_avx_fn(proof); } // This panics, unless compiled with something like `-Ctarget-feature=+avx` make_target_proof! { struct Aes("aes"); } if let Some(proof) = Aes::detect() { safe_avx_fn(proof); } } #[cfg(not(target_arch = "x86_64"))] fn main() {} target-features-0.1.6/rustc-version.txt000064400000000000000000000000541046102023000163150ustar 00000000000000rustc 1.78.0-nightly (f4b771bf1 2024-03-14) target-features-0.1.6/src/lib.rs000064400000000000000000000177231046102023000146470ustar 00000000000000//! # Target features //! A database of target features available to the Rust compiler. //! #![doc = include_str!(concat!(env!("OUT_DIR"), "/generated.md"))] #![no_std] include!(concat!(env!("OUT_DIR"), "/generated.rs")); /// List of features available for each architecture. pub mod docs { include!(concat!(env!("OUT_DIR"), "/docs.rs")); } mod simd; pub use simd::*; const fn str_eq(a: &str, b: &str) -> bool { let a = a.as_bytes(); let b = b.as_bytes(); if a.len() != b.len() { return false; } let mut i = 0; while i < a.len() { if a[i] != b[i] { return false; } i += 1; } true } /// A target architecture. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum Architecture { /// Arm Arm, /// AArch64 AArch64, /// BPF Bpf, /// Hexagon Hexagon, /// MIPS Mips, /// PowerPC PowerPC, /// RISC-V RiscV, /// WASM Wasm, /// x86 and x86-64 X86, /// Another target, which doesn't have features Unsupported, } impl Architecture { /// Create a new `Architecture` from its name. pub const fn from_str(architecture: &str) -> Self { if str_eq(architecture, "arm") { Self::Arm } else if str_eq(architecture, "aarch64") { Self::AArch64 } else if str_eq(architecture, "bpf") { Self::Bpf } else if str_eq(architecture, "hexagon") { Self::Hexagon } else if str_eq(architecture, "mips") || str_eq(architecture, "mips64") { Self::Mips } else if str_eq(architecture, "powerpc") || str_eq(architecture, "powerpc64") { Self::PowerPC } else if str_eq(architecture, "riscv32") || str_eq(architecture, "riscv64") { Self::RiscV } else if str_eq(architecture, "wasm32") || str_eq(architecture, "wasm64") { Self::Wasm } else if str_eq(architecture, "x86") || str_eq(architecture, "x86_64") { Self::X86 } else { Self::Unsupported } } } /// Returned by [`Feature::new`] when the requested feature can't be found. #[derive(Copy, Clone, Debug)] pub struct UnknownFeature; impl core::fmt::Display for UnknownFeature { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "unknown target feature") } } /// Returned by [`Target::from_cpu`] when the requested CPU can't be found. #[derive(Copy, Clone, Debug)] pub struct UnknownCpu; impl core::fmt::Display for UnknownCpu { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "unknown target CPU") } } /// A target feature. #[derive(Copy, Clone, PartialEq, Eq)] pub struct Feature(usize); impl core::fmt::Debug for Feature { fn fmt(&self, f: &mut core::fmt::Formatter) -> Result<(), core::fmt::Error> { f.debug_struct("Feature") .field("architecture", &self.architecture()) .field("name", &self.name()) .finish() } } impl Feature { /// Look up a feature. pub const fn new(architecture: Architecture, feature: &str) -> Result { let mut i = 0; while i < FEATURES.len() { if (architecture as u8) == (FEATURES[i].0 as u8) && str_eq(feature, FEATURES[i].1) { return Ok(Self(i)); } i += 1; } Err(UnknownFeature) } /// Get the name of the feature. pub const fn name(&self) -> &'static str { FEATURES[self.0].1 } /// Get the architecture this feature is for. pub const fn architecture(&self) -> Architecture { FEATURES[self.0].0 } /// Get a human-readable description of the feature. pub const fn description(&self) -> &'static str { FEATURES[self.0].2 } /// Return all features which are implied by the existence of this feature. /// /// For example, "avx2" implies the existence of "avx" on x86 architectures. pub const fn implies(&self) -> &'static [Feature] { FEATURES[self.0].3 } } /// Iterator returned by [`Target::features`]. pub struct FeaturesIter { target: Target, index: usize, } impl Iterator for FeaturesIter { type Item = Feature; fn next(&mut self) -> Option { while self.index < self.target.features.len() { let feature = if self.target.features[self.index] { Some(Feature(self.index)) } else { None }; self.index += 1; if feature.is_some() { return feature; } } None } } impl core::fmt::Debug for Target { fn fmt(&self, f: &mut core::fmt::Formatter) -> Result<(), core::fmt::Error> { struct FeaturesHelper(Target); impl core::fmt::Debug for FeaturesHelper { fn fmt(&self, f: &mut core::fmt::Formatter) -> Result<(), core::fmt::Error> { f.debug_list().entries(self.0.features()).finish() } } f.debug_struct("Target") .field("architecture", &self.architecture()) .field("features", &FeaturesHelper(*self)) .finish() } } /// A target architecture with optional features. #[derive(Copy, Clone, PartialEq, Eq)] pub struct Target { architecture: Architecture, features: [bool; FEATURES.len()], } impl Target { /// Create a target with no specified features. pub const fn new(architecture: Architecture) -> Self { Self { architecture, features: [false; FEATURES.len()], } } /// Create a target based on a particular CPU. pub const fn from_cpu(architecture: Architecture, cpu: &str) -> Result { let mut target = Self::new(architecture); let mut i = 0; while i < CPUS.len() { if architecture as u8 == CPUS[i].0 as u8 && str_eq(cpu, CPUS[i].1) { let mut j = 0; while j < CPUS[i].2.len() { target = target.with_feature(CPUS[i].2[j]); j += 1; } return Ok(target); } i += 1; } Err(UnknownCpu) } /// Returns the target architecture. pub const fn architecture(&self) -> Architecture { self.architecture } /// Returns an iterator over the features. pub const fn features(&self) -> FeaturesIter { FeaturesIter { target: *self, index: 0, } } /// Returns whether the target supports the specified feature. pub const fn supports_feature(&self, feature: Feature) -> bool { self.features[feature.0] } /// Returns whether the target supports the specified feature. /// /// # Panics /// Panics if the feature doesn't belong to the target architecture. pub const fn supports_feature_str(&self, feature: &str) -> bool { if let Ok(feature) = Feature::new(self.architecture, feature) { self.supports_feature(feature) } else { panic!("unknown feature"); } } /// Add a feature to the target. /// /// # Panics /// Panics if the feature doesn't belong to the target architecture. pub const fn with_feature(mut self, feature: Feature) -> Self { assert!(feature.architecture() as u8 == self.architecture as u8); self.features[feature.0] = true; let mut i = 0; let implies = feature.implies(); while i < implies.len() { self.features[implies[i].0] = true; i += 1; } self } /// Add a feature to the target. /// /// # Panics /// Panics if the requested feature name doesn't exist for the target architecture. pub const fn with_feature_str(self, feature: &str) -> Self { if let Ok(feature) = Feature::new(self.architecture, feature) { self.with_feature(feature) } else { panic!("unknown feature"); } } } target-features-0.1.6/src/simd.rs000064400000000000000000000113211046102023000150210ustar 00000000000000use crate::Architecture; #[doc(hidden)] pub enum SimdTypeImpl { Float32, Float64, Other, } /// Types which can be SIMD vector elements. pub trait SimdType { #[doc(hidden)] const IMPL: SimdTypeImpl; } impl SimdType for u8 { const IMPL: SimdTypeImpl = SimdTypeImpl::Other; } impl SimdType for u16 { const IMPL: SimdTypeImpl = SimdTypeImpl::Other; } impl SimdType for u32 { const IMPL: SimdTypeImpl = SimdTypeImpl::Other; } impl SimdType for u64 { const IMPL: SimdTypeImpl = SimdTypeImpl::Other; } impl SimdType for usize { const IMPL: SimdTypeImpl = SimdTypeImpl::Other; } impl SimdType for i8 { const IMPL: SimdTypeImpl = SimdTypeImpl::Other; } impl SimdType for i16 { const IMPL: SimdTypeImpl = SimdTypeImpl::Other; } impl SimdType for i32 { const IMPL: SimdTypeImpl = SimdTypeImpl::Other; } impl SimdType for i64 { const IMPL: SimdTypeImpl = SimdTypeImpl::Other; } impl SimdType for isize { const IMPL: SimdTypeImpl = SimdTypeImpl::Other; } impl SimdType for f32 { const IMPL: SimdTypeImpl = SimdTypeImpl::Float32; } impl SimdType for f64 { const IMPL: SimdTypeImpl = SimdTypeImpl::Float64; } impl SimdType for *const T { const IMPL: SimdTypeImpl = SimdTypeImpl::Other; } impl SimdType for *mut T { const IMPL: SimdTypeImpl = SimdTypeImpl::Other; } impl crate::Target { /// Returns a suggested number of elements for a SIMD vector of the provided type. /// /// The returned value is an approximation and not necessarily indicative of the /// optimal vector width. A few caveats: /// * Every instruction set is different, and this function doesn't take into account any /// particular operations--it's just a guess, and should be accurate at least for basic arithmetic. /// * Variable length vector instruction sets (ARM SVE and RISC-V V) only return the minimum /// vector length. pub const fn suggested_simd_width(&self) -> Option { let is_f32 = T::IMPL as u8 == SimdTypeImpl::Float32 as u8; let is_f64 = T::IMPL as u8 == SimdTypeImpl::Float64 as u8; let v128 = 16 / core::mem::size_of::(); let v256 = 32 / core::mem::size_of::(); let v512 = 64 / core::mem::size_of::(); let v1024 = 128 / core::mem::size_of::(); if let Architecture::Arm = self.architecture() { // Neon on arm doesn't support f64 if self.supports_feature_str("neon") && !is_f64 { Some(v128) } else { None } } else if let Architecture::AArch64 = self.architecture() { if self.supports_feature_str("neon") { Some(v128) } else { None } } else if let Architecture::Hexagon = self.architecture() { // HVX doesn't support floats if is_f32 || is_f64 { None } else if self.supports_feature_str("hvx-length128b") { Some(v1024) } else if self.supports_feature_str("hvx") { Some(v512) } else { None } } else if let Architecture::Mips = self.architecture() { if self.supports_feature_str("msa") { Some(v128) } else { None } } else if let Architecture::PowerPC = self.architecture() { // Altivec without VSX doesn't support f64 if self.supports_feature_str("vsx") || (self.supports_feature_str("altivec") && !is_f64) { Some(v128) } else { None } } else if let Architecture::RiscV = self.architecture() { // V provides at least 128-bit vectors if self.supports_feature_str("v") { Some(v128) } else { None } } else if let Architecture::Wasm = self.architecture() { if self.supports_feature_str("simd128") { Some(v128) } else { None } } else if let Architecture::X86 = self.architecture() { if self.supports_feature_str("avx512f") { Some(v512) } else if self.supports_feature_str("avx2") || (is_f32 || is_f64) && self.supports_feature_str("avx") { // AVX supports f32 and f64 Some(v256) } else if self.supports_feature_str("sse2") || is_f32 && self.supports_feature_str("sse") { // SSE supports f32 Some(v128) } else { None } } else { None } } } target-features-0.1.6/target-cpus.txt000064400000000000000000001227161046102023000157420ustar 00000000000000cpu = arm1020e arch = Arm features = v5te v6 vfp2 cpu = arm1020t arch = Arm features = v5te v6 vfp2 cpu = arm1022e arch = Arm features = v5te v6 vfp2 cpu = arm10e arch = Arm features = v5te v6 vfp2 cpu = arm10tdmi arch = Arm features = v5te v6 vfp2 cpu = arm1136j-s arch = Arm features = dsp v5te v6 vfp2 cpu = arm1136jf-s arch = Arm features = dsp v5te v6 vfp2 cpu = arm1156t2-s arch = Arm features = dsp thumb2 v5te v6 v6k v6t2 vfp2 cpu = arm1156t2f-s arch = Arm features = dsp thumb2 v5te v6 v6k v6t2 vfp2 cpu = arm1176jz-s arch = Arm features = trustzone v5te v6 v6k vfp2 cpu = arm1176jzf-s arch = Arm features = trustzone v5te v6 v6k vfp2 cpu = arm710t arch = Arm features = v5te v6 vfp2 cpu = arm720t arch = Arm features = v5te v6 vfp2 cpu = arm7tdmi arch = Arm features = v5te v6 vfp2 cpu = arm7tdmi-s arch = Arm features = v5te v6 vfp2 cpu = arm8 arch = Arm features = v5te v6 vfp2 cpu = arm810 arch = Arm features = v5te v6 vfp2 cpu = arm9 arch = Arm features = v5te v6 vfp2 cpu = arm920 arch = Arm features = v5te v6 vfp2 cpu = arm920t arch = Arm features = v5te v6 vfp2 cpu = arm922t arch = Arm features = v5te v6 vfp2 cpu = arm926ej-s arch = Arm features = v5te v6 vfp2 cpu = arm940t arch = Arm features = v5te v6 vfp2 cpu = arm946e-s arch = Arm features = v5te v6 vfp2 cpu = arm966e-s arch = Arm features = v5te v6 vfp2 cpu = arm968e-s arch = Arm features = v5te v6 vfp2 cpu = arm9e arch = Arm features = v5te v6 vfp2 cpu = arm9tdmi arch = Arm features = v5te v6 vfp2 cpu = cortex-a12 arch = Arm features = aclass dsp thumb2 trustzone v5te v6 v6k v6t2 v7 vfp2 virtualization cpu = cortex-a15 arch = Arm features = aclass dsp thumb2 trustzone v5te v6 v6k v6t2 v7 vfp2 virtualization cpu = cortex-a17 arch = Arm features = aclass dsp thumb2 trustzone v5te v6 v6k v6t2 v7 vfp2 virtualization cpu = cortex-a32 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a35 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a5 arch = Arm features = aclass dsp thumb2 trustzone v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-a53 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a55 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a57 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a7 arch = Arm features = aclass dsp thumb2 trustzone v5te v6 v6k v6t2 v7 vfp2 virtualization cpu = cortex-a710 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a72 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a73 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a75 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a76 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a76ae arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a77 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a78 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a78c arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-a8 arch = Arm features = aclass dsp thumb2 trustzone v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-a9 arch = Arm features = aclass dsp thumb2 trustzone v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-m0 arch = Arm features = mclass thumb-mode v5te v6 vfp2 cpu = cortex-m0plus arch = Arm features = mclass thumb-mode v5te v6 vfp2 cpu = cortex-m1 arch = Arm features = mclass thumb-mode v5te v6 vfp2 cpu = cortex-m23 arch = Arm features = mclass thumb-mode v5te v6 vfp2 cpu = cortex-m3 arch = Arm features = mclass thumb-mode thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-m33 arch = Arm features = dsp mclass thumb-mode thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-m35p arch = Arm features = dsp mclass thumb-mode thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-m4 arch = Arm features = dsp mclass thumb-mode thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-m52 arch = Arm features = dsp mclass thumb-mode thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-m55 arch = Arm features = dsp mclass thumb-mode thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-m7 arch = Arm features = dsp mclass thumb-mode thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-m85 arch = Arm features = dsp mclass thumb-mode thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-r4 arch = Arm features = dsp rclass thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-r4f arch = Arm features = dsp rclass thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-r5 arch = Arm features = dsp rclass thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-r52 arch = Arm features = crc dsp rclass thumb2 v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-r7 arch = Arm features = dsp rclass thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-r8 arch = Arm features = dsp rclass thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = cortex-x1 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cortex-x1c arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = cyclone arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = ep9312 arch = Arm features = v5te v6 vfp2 cpu = exynos-m3 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = exynos-m4 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = exynos-m5 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = generic arch = Arm features = v5te v6 vfp2 cpu = iwmmxt arch = Arm features = v5te v6 vfp2 cpu = krait arch = Arm features = aclass dsp thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = kryo arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = mpcore arch = Arm features = v5te v6 v6k vfp2 cpu = mpcorenovfp arch = Arm features = v5te v6 v6k vfp2 cpu = neoverse-n1 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = neoverse-n2 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = neoverse-v1 arch = Arm features = aclass crc dsp thumb2 trustzone v5te v6 v6k v6t2 v7 v8 vfp2 virtualization cpu = sc000 arch = Arm features = mclass thumb-mode v5te v6 vfp2 cpu = sc300 arch = Arm features = mclass thumb-mode thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = strongarm arch = Arm features = v5te v6 vfp2 cpu = strongarm110 arch = Arm features = v5te v6 vfp2 cpu = strongarm1100 arch = Arm features = v5te v6 vfp2 cpu = strongarm1110 arch = Arm features = v5te v6 vfp2 cpu = swift arch = Arm features = aclass dsp thumb2 v5te v6 v6k v6t2 v7 vfp2 cpu = xscale arch = Arm features = v5te v6 vfp2 cpu = a64fx arch = AArch64 features = crc dpb fcma fp16 lor lse neon pan pmuv3 ras rdm sha2 sve v8.1a v8.2a vh cpu = ampere1 arch = AArch64 features = aes bf16 bti crc dit dotprod dpb dpb2 fcma flagm frintts i8mm jsconv lor lse neon paca pacg pan pmuv3 rand ras rcpc rcpc2 rdm sb sha2 sha3 ssbs v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a vh cpu = ampere1a arch = AArch64 features = aes bf16 bti crc dit dotprod dpb dpb2 fcma flagm frintts i8mm jsconv lor lse mte neon paca pacg pan pmuv3 rand ras rcpc rcpc2 rdm sb sha2 sha3 sm4 ssbs v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a vh cpu = ampere1b arch = AArch64 features = aes bf16 bti crc dit dotprod dpb dpb2 fcma flagm fp16 frintts i8mm jsconv lor lse mte neon paca pacg pan pmuv3 rand ras rcpc rcpc2 rdm sb sha2 sha3 sm4 ssbs v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a v8.7a vh cpu = apple-a10 arch = AArch64 features = aes crc lor neon pan pmuv3 rdm sha2 vh cpu = apple-a11 arch = AArch64 features = aes crc dpb fp16 lor lse neon pan pmuv3 ras rdm sha2 v8.1a v8.2a vh cpu = apple-a12 arch = AArch64 features = aes crc dpb fcma fp16 jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rdm sha2 v8.1a v8.2a v8.3a vh cpu = apple-a13 arch = AArch64 features = aes crc dit dotprod dpb fcma fhm flagm fp16 jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sha2 sha3 v8.1a v8.2a v8.3a v8.4a vh cpu = apple-a14 arch = AArch64 features = aes crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb sha2 sha3 ssbs v8.1a v8.2a v8.3a v8.4a vh cpu = apple-a15 arch = AArch64 features = aes bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb sha2 sha3 ssbs v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a vh cpu = apple-a16 arch = AArch64 features = aes bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb sha2 sha3 ssbs v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a vh cpu = apple-a17 arch = AArch64 features = aes bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb sha2 sha3 ssbs v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a vh cpu = apple-a7 arch = AArch64 features = aes neon pmuv3 sha2 cpu = apple-a8 arch = AArch64 features = aes neon pmuv3 sha2 cpu = apple-a9 arch = AArch64 features = aes neon pmuv3 sha2 cpu = apple-latest arch = AArch64 features = aes bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb sha2 sha3 ssbs v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a vh cpu = apple-m1 arch = AArch64 features = aes crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb sha2 sha3 ssbs v8.1a v8.2a v8.3a v8.4a vh cpu = apple-m2 arch = AArch64 features = aes bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb sha2 sha3 ssbs v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a vh cpu = apple-m3 arch = AArch64 features = aes bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb sha2 sha3 ssbs v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a vh cpu = apple-s4 arch = AArch64 features = aes crc dpb fcma fp16 jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rdm sha2 v8.1a v8.2a v8.3a vh cpu = apple-s5 arch = AArch64 features = aes crc dpb fcma fp16 jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rdm sha2 v8.1a v8.2a v8.3a vh cpu = carmel arch = AArch64 features = aes crc dpb fp16 lor lse neon pan ras rdm sha2 v8.1a v8.2a vh cpu = cortex-a34 arch = AArch64 features = aes crc neon pmuv3 sha2 cpu = cortex-a35 arch = AArch64 features = aes crc neon pmuv3 sha2 cpu = cortex-a510 arch = AArch64 features = bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse mte neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb ssbs sve sve2 sve2-bitperm v8.1a v8.2a v8.3a v8.4a v8.5a vh cpu = cortex-a520 arch = AArch64 features = bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse mte neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb ssbs sve sve2 sve2-bitperm v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a v8.7a vh cpu = cortex-a53 arch = AArch64 features = aes crc neon pmuv3 sha2 cpu = cortex-a55 arch = AArch64 features = aes crc dotprod dpb fp16 lor lse neon pan pmuv3 ras rcpc rdm sha2 v8.1a v8.2a vh cpu = cortex-a57 arch = AArch64 features = aes crc neon pmuv3 sha2 cpu = cortex-a65 arch = AArch64 features = aes crc dotprod dpb fp16 lor lse neon pan pmuv3 ras rcpc rdm sha2 ssbs v8.1a v8.2a vh cpu = cortex-a65ae arch = AArch64 features = aes crc dotprod dpb fp16 lor lse neon pan pmuv3 ras rcpc rdm sha2 ssbs v8.1a v8.2a vh cpu = cortex-a710 arch = AArch64 features = bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse mte neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb ssbs sve sve2 sve2-bitperm v8.1a v8.2a v8.3a v8.4a v8.5a vh cpu = cortex-a715 arch = AArch64 features = bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse mte neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb spe ssbs sve sve2 sve2-bitperm v8.1a v8.2a v8.3a v8.4a v8.5a vh cpu = cortex-a72 arch = AArch64 features = aes crc neon pmuv3 sha2 cpu = cortex-a720 arch = AArch64 features = bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse mte neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb spe ssbs sve sve2 sve2-bitperm v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a v8.7a vh cpu = cortex-a73 arch = AArch64 features = aes crc neon pmuv3 sha2 cpu = cortex-a75 arch = AArch64 features = aes crc dotprod dpb fp16 lor lse neon pan pmuv3 ras rcpc rdm sha2 v8.1a v8.2a vh cpu = cortex-a76 arch = AArch64 features = aes crc dotprod dpb fp16 lor lse neon pan pmuv3 ras rcpc rdm sha2 ssbs v8.1a v8.2a vh cpu = cortex-a76ae arch = AArch64 features = aes crc dotprod dpb fp16 lor lse neon pan pmuv3 ras rcpc rdm sha2 ssbs v8.1a v8.2a vh cpu = cortex-a77 arch = AArch64 features = aes crc dotprod dpb fp16 lor lse neon pan pmuv3 ras rcpc rdm sha2 ssbs v8.1a v8.2a vh cpu = cortex-a78 arch = AArch64 features = aes crc dotprod dpb fp16 lor lse neon pan pmuv3 ras rcpc rdm sha2 spe ssbs v8.1a v8.2a vh cpu = cortex-a78c arch = AArch64 features = aes crc dotprod dpb flagm fp16 lor lse neon paca pacg pan pmuv3 ras rcpc rdm sha2 spe ssbs v8.1a v8.2a vh cpu = cortex-r82 arch = AArch64 features = crc dit dotprod dpb fcma fhm flagm fp16 jsconv lse neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb ssbs cpu = cortex-x1 arch = AArch64 features = aes crc dotprod dpb fp16 lor lse neon pan pmuv3 ras rcpc rdm sha2 spe ssbs v8.1a v8.2a vh cpu = cortex-x1c arch = AArch64 features = aes crc dotprod dpb flagm fp16 lor lse neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sha2 spe ssbs v8.1a v8.2a vh cpu = cortex-x2 arch = AArch64 features = bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse mte neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb ssbs sve sve2 sve2-bitperm v8.1a v8.2a v8.3a v8.4a v8.5a vh cpu = cortex-x3 arch = AArch64 features = bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse mte neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb spe ssbs sve sve2 sve2-bitperm v8.1a v8.2a v8.3a v8.4a v8.5a vh cpu = cortex-x4 arch = AArch64 features = bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse mte neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb spe ssbs sve sve2 sve2-bitperm v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a v8.7a vh cpu = cyclone arch = AArch64 features = aes neon pmuv3 sha2 cpu = exynos-m3 arch = AArch64 features = aes crc neon pmuv3 sha2 cpu = exynos-m4 arch = AArch64 features = aes crc dotprod dpb fp16 lor lse neon pan pmuv3 ras rdm sha2 v8.1a v8.2a vh cpu = exynos-m5 arch = AArch64 features = aes crc dotprod dpb fp16 lor lse neon pan pmuv3 ras rdm sha2 v8.1a v8.2a vh cpu = falkor arch = AArch64 features = aes crc neon pmuv3 rdm sha2 cpu = generic arch = AArch64 features = neon cpu = kryo arch = AArch64 features = aes crc neon pmuv3 sha2 cpu = neoverse-512tvb arch = AArch64 features = aes bf16 crc dit dotprod dpb dpb2 fcma fhm flagm fp16 i8mm jsconv lor lse neon paca pacg pan pmuv3 rand ras rcpc rcpc2 rdm sha2 spe ssbs sve v8.1a v8.2a v8.3a v8.4a vh cpu = neoverse-e1 arch = AArch64 features = aes crc dotprod dpb fp16 lor lse neon pan pmuv3 ras rcpc rdm sha2 ssbs v8.1a v8.2a vh cpu = neoverse-n1 arch = AArch64 features = aes crc dotprod dpb fp16 lor lse neon pan pmuv3 ras rcpc rdm sha2 spe ssbs v8.1a v8.2a vh cpu = neoverse-n2 arch = AArch64 features = bf16 bti crc dit dotprod dpb dpb2 fcma flagm fp16 frintts i8mm jsconv lor lse mte neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sb ssbs sve sve2 sve2-bitperm v8.1a v8.2a v8.3a v8.4a v8.5a vh cpu = neoverse-v1 arch = AArch64 features = aes bf16 crc dit dotprod dpb dpb2 fcma fhm flagm fp16 i8mm jsconv lor lse neon paca pacg pan pmuv3 rand ras rcpc rcpc2 rdm sha2 spe ssbs sve v8.1a v8.2a v8.3a v8.4a vh cpu = neoverse-v2 arch = AArch64 features = bf16 bti crc dit dotprod dpb dpb2 fcma fhm flagm fp16 frintts i8mm jsconv lor lse mte neon paca pacg pan pmuv3 rand ras rcpc rcpc2 rdm sb spe ssbs sve sve2 sve2-bitperm v8.1a v8.2a v8.3a v8.4a v8.5a vh cpu = saphira arch = AArch64 features = aes crc dit dotprod dpb fcma flagm jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rcpc2 rdm sha2 spe v8.1a v8.2a v8.3a v8.4a vh cpu = thunderx arch = AArch64 features = aes crc neon pmuv3 sha2 cpu = thunderx2t99 arch = AArch64 features = aes crc lor lse neon pan rdm sha2 v8.1a vh cpu = thunderx3t110 arch = AArch64 features = aes crc dpb fcma jsconv lor lse neon paca pacg pan pmuv3 ras rcpc rdm sha2 v8.1a v8.2a v8.3a vh cpu = thunderxt81 arch = AArch64 features = aes crc neon pmuv3 sha2 cpu = thunderxt83 arch = AArch64 features = aes crc neon pmuv3 sha2 cpu = thunderxt88 arch = AArch64 features = aes crc neon pmuv3 sha2 cpu = tsv110 arch = AArch64 features = aes crc dotprod dpb fcma fhm fp16 jsconv lor lse neon pan pmuv3 ras rdm sha2 spe v8.1a v8.2a vh cpu = generic arch = Bpf features = cpu = probe arch = Bpf features = cpu = v1 arch = Bpf features = cpu = v2 arch = Bpf features = cpu = v3 arch = Bpf features = alu32 cpu = v4 arch = Bpf features = alu32 cpu = generic arch = Hexagon features = hvx hvx-length128b cpu = hexagonv5 arch = Hexagon features = hvx hvx-length128b cpu = hexagonv55 arch = Hexagon features = hvx hvx-length128b cpu = hexagonv60 arch = Hexagon features = hvx hvx-length128b cpu = hexagonv62 arch = Hexagon features = hvx hvx-length128b cpu = hexagonv65 arch = Hexagon features = hvx hvx-length128b cpu = hexagonv66 arch = Hexagon features = hvx hvx-length128b cpu = hexagonv67 arch = Hexagon features = hvx hvx-length128b cpu = hexagonv67t arch = Hexagon features = hvx hvx-length128b cpu = hexagonv68 arch = Hexagon features = hvx hvx-length128b cpu = hexagonv69 arch = Hexagon features = hvx hvx-length128b cpu = hexagonv71 arch = Hexagon features = hvx hvx-length128b cpu = hexagonv71t arch = Hexagon features = hvx hvx-length128b cpu = hexagonv73 arch = Hexagon features = hvx hvx-length128b cpu = generic arch = Mips features = fp64 cpu = mips1 arch = Mips features = fp64 cpu = mips2 arch = Mips features = fp64 cpu = mips3 arch = Mips features = fp64 cpu = mips32 arch = Mips features = fp64 cpu = mips32r2 arch = Mips features = fp64 cpu = mips32r3 arch = Mips features = fp64 cpu = mips32r5 arch = Mips features = fp64 cpu = mips32r6 arch = Mips features = fp64 cpu = mips4 arch = Mips features = fp64 cpu = mips5 arch = Mips features = fp64 cpu = mips64 arch = Mips features = fp64 cpu = mips64r2 arch = Mips features = fp64 cpu = mips64r3 arch = Mips features = fp64 cpu = mips64r5 arch = Mips features = fp64 cpu = mips64r6 arch = Mips features = fp64 cpu = octeon arch = Mips features = fp64 cpu = octeon+ arch = Mips features = fp64 cpu = p5600 arch = Mips features = fp64 cpu = 440 arch = PowerPC features = cpu = 450 arch = PowerPC features = cpu = 601 arch = PowerPC features = cpu = 602 arch = PowerPC features = cpu = 603 arch = PowerPC features = cpu = 603e arch = PowerPC features = cpu = 603ev arch = PowerPC features = cpu = 604 arch = PowerPC features = cpu = 604e arch = PowerPC features = cpu = 620 arch = PowerPC features = cpu = 7400 arch = PowerPC features = altivec cpu = 7450 arch = PowerPC features = altivec cpu = 750 arch = PowerPC features = cpu = 970 arch = PowerPC features = altivec cpu = a2 arch = PowerPC features = cpu = e500 arch = PowerPC features = cpu = e500mc arch = PowerPC features = cpu = e5500 arch = PowerPC features = cpu = future arch = PowerPC features = altivec power10-vector power8-altivec power8-vector power9-altivec power9-vector vsx cpu = g3 arch = PowerPC features = cpu = g4 arch = PowerPC features = altivec cpu = g4+ arch = PowerPC features = altivec cpu = g5 arch = PowerPC features = altivec cpu = generic arch = PowerPC features = cpu = ppc arch = PowerPC features = cpu = ppc32 arch = PowerPC features = cpu = ppc64 arch = PowerPC features = altivec cpu = ppc64le arch = PowerPC features = altivec power8-altivec power8-vector vsx cpu = pwr10 arch = PowerPC features = altivec power10-vector power8-altivec power8-vector power9-altivec power9-vector vsx cpu = pwr3 arch = PowerPC features = altivec cpu = pwr4 arch = PowerPC features = altivec cpu = pwr5 arch = PowerPC features = altivec cpu = pwr5x arch = PowerPC features = altivec cpu = pwr6 arch = PowerPC features = altivec cpu = pwr6x arch = PowerPC features = altivec cpu = pwr7 arch = PowerPC features = altivec vsx cpu = pwr8 arch = PowerPC features = altivec power8-altivec power8-vector vsx cpu = pwr9 arch = PowerPC features = altivec power8-altivec power8-vector power9-altivec power9-vector vsx cpu = generic arch = RiscV features = a c d f m cpu = generic-rv32 arch = RiscV features = a c d f m cpu = generic-rv64 arch = RiscV features = a c d f m cpu = rocket arch = RiscV features = a c d f m cpu = rocket-rv32 arch = RiscV features = a c d f m cpu = rocket-rv64 arch = RiscV features = a c d f m cpu = sifive-7-series arch = RiscV features = a c d f m cpu = sifive-e20 arch = RiscV features = a c d f m cpu = sifive-e21 arch = RiscV features = a c d f m cpu = sifive-e24 arch = RiscV features = a c d f m cpu = sifive-e31 arch = RiscV features = a c d f m cpu = sifive-e34 arch = RiscV features = a c d f m cpu = sifive-e76 arch = RiscV features = a c d f m cpu = sifive-p450 arch = RiscV features = a c d f fast-unaligned-access m zba zbb zbs zfhmin cpu = sifive-p670 arch = RiscV features = a c d f fast-unaligned-access m v zba zbb zbs zfhmin cpu = sifive-s21 arch = RiscV features = a c d f m cpu = sifive-s51 arch = RiscV features = a c d f m cpu = sifive-s54 arch = RiscV features = a c d f m cpu = sifive-s76 arch = RiscV features = a c d f m cpu = sifive-u54 arch = RiscV features = a c d f m cpu = sifive-u74 arch = RiscV features = a c d f m cpu = sifive-x280 arch = RiscV features = a c d f m v zba zbb zfh zfhmin cpu = syntacore-scr1-base arch = RiscV features = a c d f m cpu = syntacore-scr1-max arch = RiscV features = a c d f m cpu = veyron-v1 arch = RiscV features = a c d f m zba zbb zbc zbs cpu = xiangshan-nanhu arch = RiscV features = a c d f m zba zbb zbc zbkb zbkc zbkx zbs zkn zknd zkne zknh zksed zksh cpu = bleeding-edge arch = Wasm features = atomics bulk-memory mutable-globals nontrapping-fptoint sign-ext simd128 cpu = generic arch = Wasm features = mutable-globals sign-ext cpu = mvp arch = Wasm features = cpu = alderlake arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = amdfam10 arch = X86 features = cmpxchg16b fxsr lahfsahf lzcnt popcnt prfchw sse sse2 sse3 sse4a cpu = arrowlake arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = arrowlake-s arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = arrowlake_s arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = athlon arch = X86 features = sse sse2 cpu = athlon-4 arch = X86 features = fxsr sse sse2 cpu = athlon-fx arch = X86 features = fxsr sse sse2 cpu = athlon-mp arch = X86 features = fxsr sse sse2 cpu = athlon-tbird arch = X86 features = sse sse2 cpu = athlon-xp arch = X86 features = fxsr sse sse2 cpu = athlon64 arch = X86 features = fxsr sse sse2 cpu = athlon64-sse3 arch = X86 features = cmpxchg16b fxsr sse sse2 sse3 cpu = atom arch = X86 features = cmpxchg16b fxsr lahfsahf movbe sse sse2 sse3 ssse3 cpu = atom_sse4_2 arch = X86 features = cmpxchg16b fxsr lahfsahf movbe pclmulqdq popcnt prfchw rdrand sse sse2 sse3 sse4.1 sse4.2 ssse3 cpu = atom_sse4_2_movbe arch = X86 features = aes cmpxchg16b fxsr lahfsahf movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsavec xsaveopt xsaves cpu = barcelona arch = X86 features = cmpxchg16b fxsr lahfsahf lzcnt popcnt prfchw sse sse2 sse3 sse4a cpu = bdver1 arch = X86 features = aes avx cmpxchg16b fxsr lahfsahf lzcnt pclmulqdq popcnt prfchw sse sse2 sse3 sse4.1 sse4.2 sse4a ssse3 xsave cpu = bdver2 arch = X86 features = aes avx bmi1 cmpxchg16b f16c fma fxsr lahfsahf lzcnt pclmulqdq popcnt prfchw sse sse2 sse3 sse4.1 sse4.2 sse4a ssse3 tbm xsave cpu = bdver3 arch = X86 features = aes avx bmi1 cmpxchg16b f16c fma fxsr lahfsahf lzcnt pclmulqdq popcnt prfchw sse sse2 sse3 sse4.1 sse4.2 sse4a ssse3 tbm xsave xsaveopt cpu = bdver4 arch = X86 features = aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand sse sse2 sse3 sse4.1 sse4.2 sse4a ssse3 tbm xsave xsaveopt cpu = bonnell arch = X86 features = cmpxchg16b fxsr lahfsahf movbe sse sse2 sse3 ssse3 cpu = broadwell arch = X86 features = adx avx avx2 bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = btver1 arch = X86 features = cmpxchg16b fxsr lahfsahf lzcnt popcnt prfchw sse sse2 sse3 sse4a ssse3 cpu = btver2 arch = X86 features = aes avx bmi1 cmpxchg16b f16c fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw sse sse2 sse3 sse4.1 sse4.2 sse4a ssse3 xsave xsaveopt cpu = c3 arch = X86 features = sse sse2 cpu = c3-2 arch = X86 features = fxsr sse sse2 cpu = cannonlake arch = X86 features = adx aes avx avx2 avx512bw avx512cd avx512dq avx512f avx512ifma avx512vbmi avx512vl bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsavec xsaveopt xsaves cpu = cascadelake arch = X86 features = adx aes avx avx2 avx512bw avx512cd avx512dq avx512f avx512vl avx512vnni bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsavec xsaveopt xsaves cpu = clearwaterforest arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = cooperlake arch = X86 features = adx aes avx avx2 avx512bf16 avx512bw avx512cd avx512dq avx512f avx512vl avx512vnni bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsavec xsaveopt xsaves cpu = core-avx-i arch = X86 features = avx cmpxchg16b f16c fxsr lahfsahf pclmulqdq popcnt rdrand sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = core-avx2 arch = X86 features = avx avx2 bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt rdrand sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = core2 arch = X86 features = cmpxchg16b fxsr lahfsahf sse sse2 sse3 ssse3 cpu = core_2_duo_sse4_1 arch = X86 features = cmpxchg16b fxsr lahfsahf sse sse2 sse3 sse4.1 ssse3 cpu = core_2_duo_ssse3 arch = X86 features = cmpxchg16b fxsr lahfsahf sse sse2 sse3 ssse3 cpu = core_2nd_gen_avx arch = X86 features = avx cmpxchg16b fxsr lahfsahf pclmulqdq popcnt sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = core_3rd_gen_avx arch = X86 features = avx cmpxchg16b f16c fxsr lahfsahf pclmulqdq popcnt rdrand sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = core_4th_gen_avx arch = X86 features = avx avx2 bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt rdrand sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = core_4th_gen_avx_tsx arch = X86 features = avx avx2 bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt rdrand sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = core_5th_gen_avx arch = X86 features = adx avx avx2 bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = core_5th_gen_avx_tsx arch = X86 features = adx avx avx2 bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = core_aes_pclmulqdq arch = X86 features = cmpxchg16b fxsr lahfsahf pclmulqdq popcnt sse sse2 sse3 sse4.1 sse4.2 ssse3 cpu = core_i7_sse4_2 arch = X86 features = cmpxchg16b fxsr lahfsahf popcnt sse sse2 sse3 sse4.1 sse4.2 ssse3 cpu = corei7 arch = X86 features = cmpxchg16b fxsr lahfsahf popcnt sse sse2 sse3 sse4.1 sse4.2 ssse3 cpu = corei7-avx arch = X86 features = avx cmpxchg16b fxsr lahfsahf pclmulqdq popcnt sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = emeraldrapids arch = X86 features = adx aes avx avx2 avx512bf16 avx512bitalg avx512bw avx512cd avx512dq avx512f avx512fp16 avx512ifma avx512vbmi avx512vbmi2 avx512vl avx512vnni avx512vpopcntdq bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = generic arch = X86 features = sse sse2 cpu = geode arch = X86 features = sse sse2 cpu = goldmont arch = X86 features = aes cmpxchg16b fxsr lahfsahf movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsavec xsaveopt xsaves cpu = goldmont-plus arch = X86 features = aes cmpxchg16b fxsr lahfsahf movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsavec xsaveopt xsaves cpu = goldmont_plus arch = X86 features = aes cmpxchg16b fxsr lahfsahf movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsavec xsaveopt xsaves cpu = gracemont arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = grandridge arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = graniterapids arch = X86 features = adx aes avx avx2 avx512bf16 avx512bitalg avx512bw avx512cd avx512dq avx512f avx512fp16 avx512ifma avx512vbmi avx512vbmi2 avx512vl avx512vnni avx512vpopcntdq bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = graniterapids-d arch = X86 features = adx aes avx avx2 avx512bf16 avx512bitalg avx512bw avx512cd avx512dq avx512f avx512fp16 avx512ifma avx512vbmi avx512vbmi2 avx512vl avx512vnni avx512vpopcntdq bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = graniterapids_d arch = X86 features = adx aes avx avx2 avx512bf16 avx512bitalg avx512bw avx512cd avx512dq avx512f avx512fp16 avx512ifma avx512vbmi avx512vbmi2 avx512vl avx512vnni avx512vpopcntdq bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = haswell arch = X86 features = avx avx2 bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt rdrand sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = i386 arch = X86 features = sse sse2 cpu = i486 arch = X86 features = sse sse2 cpu = i586 arch = X86 features = sse sse2 cpu = i686 arch = X86 features = sse sse2 cpu = icelake-client arch = X86 features = adx aes avx avx2 avx512bitalg avx512bw avx512cd avx512dq avx512f avx512ifma avx512vbmi avx512vbmi2 avx512vl avx512vnni avx512vpopcntdq bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = icelake-server arch = X86 features = adx aes avx avx2 avx512bitalg avx512bw avx512cd avx512dq avx512f avx512ifma avx512vbmi avx512vbmi2 avx512vl avx512vnni avx512vpopcntdq bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = icelake_client arch = X86 features = adx aes avx avx2 avx512bitalg avx512bw avx512cd avx512dq avx512f avx512ifma avx512vbmi avx512vbmi2 avx512vl avx512vnni avx512vpopcntdq bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = icelake_server arch = X86 features = adx aes avx avx2 avx512bitalg avx512bw avx512cd avx512dq avx512f avx512ifma avx512vbmi avx512vbmi2 avx512vl avx512vnni avx512vpopcntdq bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = ivybridge arch = X86 features = avx cmpxchg16b f16c fxsr lahfsahf pclmulqdq popcnt rdrand sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = k6 arch = X86 features = sse sse2 cpu = k6-2 arch = X86 features = sse sse2 cpu = k6-3 arch = X86 features = sse sse2 cpu = k8 arch = X86 features = fxsr sse sse2 cpu = k8-sse3 arch = X86 features = cmpxchg16b fxsr sse sse2 sse3 cpu = knl arch = X86 features = adx aes avx avx2 avx512cd avx512er avx512f avx512pf bmi1 bmi2 cmpxchg16b f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = knm arch = X86 features = adx aes avx avx2 avx512cd avx512er avx512f avx512pf avx512vpopcntdq bmi1 bmi2 cmpxchg16b f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = lakemont arch = X86 features = sse sse2 cpu = lunarlake arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = meteorlake arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = mic_avx512 arch = X86 features = adx aes avx avx2 avx512cd avx512er avx512f avx512pf bmi1 bmi2 cmpxchg16b f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = nehalem arch = X86 features = cmpxchg16b fxsr lahfsahf popcnt sse sse2 sse3 sse4.1 sse4.2 ssse3 cpu = nocona arch = X86 features = cmpxchg16b fxsr sse sse2 sse3 cpu = opteron arch = X86 features = fxsr sse sse2 cpu = opteron-sse3 arch = X86 features = cmpxchg16b fxsr sse sse2 sse3 cpu = pantherlake arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = penryn arch = X86 features = cmpxchg16b fxsr lahfsahf sse sse2 sse3 sse4.1 ssse3 cpu = pentium arch = X86 features = sse sse2 cpu = pentium-m arch = X86 features = fxsr sse sse2 cpu = pentium-mmx arch = X86 features = sse sse2 cpu = pentium2 arch = X86 features = fxsr sse sse2 cpu = pentium3 arch = X86 features = fxsr sse sse2 cpu = pentium3m arch = X86 features = fxsr sse sse2 cpu = pentium4 arch = X86 features = fxsr sse sse2 cpu = pentium4m arch = X86 features = fxsr sse sse2 cpu = pentium_4 arch = X86 features = fxsr sse sse2 cpu = pentium_4_sse3 arch = X86 features = fxsr sse sse2 sse3 cpu = pentium_ii arch = X86 features = fxsr sse sse2 cpu = pentium_iii arch = X86 features = fxsr sse sse2 cpu = pentium_iii_no_xmm_regs arch = X86 features = fxsr sse sse2 cpu = pentium_m arch = X86 features = fxsr sse sse2 cpu = pentium_mmx arch = X86 features = sse sse2 cpu = pentium_pro arch = X86 features = sse sse2 cpu = pentiumpro arch = X86 features = sse sse2 cpu = prescott arch = X86 features = fxsr sse sse2 sse3 cpu = raptorlake arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = rocketlake arch = X86 features = adx aes avx avx2 avx512bitalg avx512bw avx512cd avx512dq avx512f avx512ifma avx512vbmi avx512vbmi2 avx512vl avx512vnni avx512vpopcntdq bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = sandybridge arch = X86 features = avx cmpxchg16b fxsr lahfsahf pclmulqdq popcnt sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsaveopt cpu = sapphirerapids arch = X86 features = adx aes avx avx2 avx512bf16 avx512bitalg avx512bw avx512cd avx512dq avx512f avx512fp16 avx512ifma avx512vbmi avx512vbmi2 avx512vl avx512vnni avx512vpopcntdq bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = sierraforest arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = silvermont arch = X86 features = cmpxchg16b fxsr lahfsahf movbe pclmulqdq popcnt prfchw rdrand sse sse2 sse3 sse4.1 sse4.2 ssse3 cpu = skx arch = X86 features = adx aes avx avx2 avx512bw avx512cd avx512dq avx512f avx512vl bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsavec xsaveopt xsaves cpu = skylake arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsavec xsaveopt xsaves cpu = skylake-avx512 arch = X86 features = adx aes avx avx2 avx512bw avx512cd avx512dq avx512f avx512vl bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsavec xsaveopt xsaves cpu = skylake_avx512 arch = X86 features = adx aes avx avx2 avx512bw avx512cd avx512dq avx512f avx512vl bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsavec xsaveopt xsaves cpu = slm arch = X86 features = cmpxchg16b fxsr lahfsahf movbe pclmulqdq popcnt prfchw rdrand sse sse2 sse3 sse4.1 sse4.2 ssse3 cpu = tigerlake arch = X86 features = adx aes avx avx2 avx512bitalg avx512bw avx512cd avx512dq avx512f avx512ifma avx512vbmi avx512vbmi2 avx512vl avx512vnni avx512vp2intersect avx512vpopcntdq bmi1 bmi2 cmpxchg16b ermsb f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = tremont arch = X86 features = aes cmpxchg16b fxsr gfni lahfsahf movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave xsavec xsaveopt xsaves cpu = westmere arch = X86 features = cmpxchg16b fxsr lahfsahf pclmulqdq popcnt sse sse2 sse3 sse4.1 sse4.2 ssse3 cpu = winchip-c6 arch = X86 features = sse sse2 cpu = winchip2 arch = X86 features = sse sse2 cpu = x86-64 arch = X86 features = fxsr sse sse2 cpu = x86-64-v2 arch = X86 features = cmpxchg16b fxsr lahfsahf popcnt sse sse2 sse3 sse4.1 sse4.2 ssse3 cpu = x86-64-v3 arch = X86 features = avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr lahfsahf lzcnt movbe popcnt sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave cpu = x86-64-v4 arch = X86 features = avx avx2 avx512bw avx512cd avx512dq avx512f avx512vl bmi1 bmi2 cmpxchg16b f16c fma fxsr lahfsahf lzcnt movbe popcnt sse sse2 sse3 sse4.1 sse4.2 ssse3 xsave cpu = yonah arch = X86 features = fxsr sse sse2 sse3 cpu = znver1 arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 sse4a ssse3 xsave xsavec xsaveopt xsaves cpu = znver2 arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 sse4a ssse3 xsave xsavec xsaveopt xsaves cpu = znver3 arch = X86 features = adx aes avx avx2 bmi1 bmi2 cmpxchg16b f16c fma fxsr lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 sse4a ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves cpu = znver4 arch = X86 features = adx aes avx avx2 avx512bf16 avx512bitalg avx512bw avx512cd avx512dq avx512f avx512ifma avx512vbmi avx512vbmi2 avx512vl avx512vnni avx512vpopcntdq bmi1 bmi2 cmpxchg16b f16c fma fxsr gfni lahfsahf lzcnt movbe pclmulqdq popcnt prfchw rdrand rdseed sha sse sse2 sse3 sse4.1 sse4.2 sse4a ssse3 vaes vpclmulqdq xsave xsavec xsaveopt xsaves target-features-0.1.6/target-features.txt000064400000000000000000000516071046102023000166060ustar 00000000000000feature = aclass arch = Arm implies = description = Is application profile ('A' series). feature = aes arch = Arm implies = d32 neon vfp2 vfp3 description = Enable AES support. feature = crc arch = Arm implies = description = Enable support for CRC instructions. feature = d32 arch = Arm implies = description = Extend FP to 32 double registers. feature = dotprod arch = Arm implies = d32 neon vfp2 vfp3 description = Enable support for dot product instructions. feature = dsp arch = Arm implies = description = Supports DSP instructions in ARM and/or Thumb2. feature = fp-armv8 arch = Arm implies = d32 vfp2 vfp3 vfp4 description = Enable ARMv8 FP. feature = i8mm arch = Arm implies = d32 neon vfp2 vfp3 description = Enable Matrix Multiply Int8 Extension. feature = mclass arch = Arm implies = description = Is microcontroller profile ('M' series). feature = neon arch = Arm implies = d32 vfp2 vfp3 description = Enable NEON instructions. feature = rclass arch = Arm implies = description = Is realtime profile ('R' series). feature = sha2 arch = Arm implies = d32 neon vfp2 vfp3 description = Enable SHA1 and SHA256 support. feature = thumb-mode arch = Arm implies = description = Thumb mode. feature = thumb2 arch = Arm implies = description = Enable Thumb2 instructions. feature = trustzone arch = Arm implies = description = Enable support for TrustZone security extensions. feature = v5te arch = Arm implies = description = Support ARM v5TE, v5TEj, and v5TExp instructions. feature = v6 arch = Arm implies = v5te description = Support ARM v6 instructions. feature = v6k arch = Arm implies = v5te v6 description = Support ARM v6k instructions. feature = v6t2 arch = Arm implies = thumb2 v5te v6 v6k description = Support ARM v6t2 instructions. feature = v7 arch = Arm implies = thumb2 v5te v6 v6k v6t2 description = Support ARM v7 instructions. feature = v8 arch = Arm implies = thumb2 v5te v6 v6k v6t2 v7 description = Support ARM v8 instructions. feature = vfp2 arch = Arm implies = description = Enable VFP2 instructions. feature = vfp3 arch = Arm implies = d32 vfp2 description = Enable VFP3 instructions. feature = vfp4 arch = Arm implies = d32 vfp2 vfp3 description = Enable VFP4 instructions. feature = virtualization arch = Arm implies = description = Supports Virtualization extension. feature = crt-static arch = Arm implies = description = Enables C Run-time Libraries to be statically linked. feature = aes arch = AArch64 implies = neon description = Enable AES support (FEAT_AES, FEAT_PMULL). feature = bf16 arch = AArch64 implies = description = Enable BFloat16 Extension (FEAT_BF16). feature = bti arch = AArch64 implies = description = Enable Branch Target Identification (FEAT_BTI). feature = crc arch = AArch64 implies = description = Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32). feature = dit arch = AArch64 implies = description = Enable v8.4-A Data Independent Timing instructions (FEAT_DIT). feature = dotprod arch = AArch64 implies = description = Enable dot product support (FEAT_DotProd). feature = dpb arch = AArch64 implies = description = Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB). feature = dpb2 arch = AArch64 implies = description = Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2). feature = f32mm arch = AArch64 implies = fp16 neon sve description = Enable Matrix Multiply FP32 Extension (FEAT_F32MM). feature = f64mm arch = AArch64 implies = fp16 neon sve description = Enable Matrix Multiply FP64 Extension (FEAT_F64MM). feature = fcma arch = AArch64 implies = neon description = Enable v8.3-A Floating-point complex number support (FEAT_FCMA). feature = fhm arch = AArch64 implies = fp16 neon description = Enable FP16 FML instructions (FEAT_FHM). feature = flagm arch = AArch64 implies = description = Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM). feature = fp16 arch = AArch64 implies = neon description = Full FP16 (FEAT_FP16). feature = frintts arch = AArch64 implies = description = Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS). feature = i8mm arch = AArch64 implies = description = Enable Matrix Multiply Int8 Extension (FEAT_I8MM). feature = jsconv arch = AArch64 implies = neon description = Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT). feature = lor arch = AArch64 implies = description = Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR). feature = lse arch = AArch64 implies = description = Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE). feature = mte arch = AArch64 implies = description = Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2). feature = neon arch = AArch64 implies = description = Enable Advanced SIMD instructions (FEAT_AdvSIMD). feature = paca arch = AArch64 implies = pacg description = Enable v8.3-A Pointer Authentication extension (FEAT_PAuth). feature = pacg arch = AArch64 implies = paca description = Enable v8.3-A Pointer Authentication extension (FEAT_PAuth). feature = pan arch = AArch64 implies = description = Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN). feature = pmuv3 arch = AArch64 implies = description = Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3). feature = rand arch = AArch64 implies = description = Enable Random Number generation instructions (FEAT_RNG). feature = ras arch = AArch64 implies = description = Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1). feature = rcpc arch = AArch64 implies = description = Enable support for RCPC extension (FEAT_LRCPC). feature = rcpc2 arch = AArch64 implies = rcpc description = Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2). feature = rdm arch = AArch64 implies = description = Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM). feature = sb arch = AArch64 implies = description = Enable v8.5 Speculation Barrier (FEAT_SB). feature = sha2 arch = AArch64 implies = neon description = Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256). feature = sha3 arch = AArch64 implies = neon sha2 description = Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512). feature = sm4 arch = AArch64 implies = neon description = Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3). feature = spe arch = AArch64 implies = description = Enable Statistical Profiling extension (FEAT_SPE). feature = ssbs arch = AArch64 implies = description = Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2). feature = sve arch = AArch64 implies = fp16 neon description = Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE). feature = sve2 arch = AArch64 implies = fp16 neon sve description = Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2). feature = sve2-aes arch = AArch64 implies = aes fp16 neon sve sve2 description = Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128). feature = sve2-bitperm arch = AArch64 implies = fp16 neon sve sve2 description = Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm). feature = sve2-sha3 arch = AArch64 implies = fp16 neon sha2 sha3 sve sve2 description = Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3). feature = sve2-sm4 arch = AArch64 implies = fp16 neon sm4 sve sve2 description = Enable SM4 SVE2 instructions (FEAT_SVE_SM4). feature = tme arch = AArch64 implies = description = Enable Transactional Memory Extension (FEAT_TME). feature = v8.1a arch = AArch64 implies = crc lor lse pan rdm vh description = Support ARM v8.1a instructions. feature = v8.2a arch = AArch64 implies = crc dpb lor lse pan ras rdm v8.1a vh description = Support ARM v8.2a instructions. feature = v8.3a arch = AArch64 implies = crc dpb fcma jsconv lor lse neon paca pacg pan ras rcpc rdm v8.1a v8.2a vh description = Support ARM v8.3a instructions. feature = v8.4a arch = AArch64 implies = crc dit dotprod dpb fcma flagm jsconv lor lse neon paca pacg pan ras rcpc rcpc2 rdm v8.1a v8.2a v8.3a vh description = Support ARM v8.4a instructions. feature = v8.5a arch = AArch64 implies = bti crc dit dotprod dpb dpb2 fcma flagm frintts jsconv lor lse neon paca pacg pan ras rcpc rcpc2 rdm sb ssbs v8.1a v8.2a v8.3a v8.4a vh description = Support ARM v8.5a instructions. feature = v8.6a arch = AArch64 implies = bf16 bti crc dit dotprod dpb dpb2 fcma flagm frintts i8mm jsconv lor lse neon paca pacg pan ras rcpc rcpc2 rdm sb ssbs v8.1a v8.2a v8.3a v8.4a v8.5a vh description = Support ARM v8.6a instructions. feature = v8.7a arch = AArch64 implies = bf16 bti crc dit dotprod dpb dpb2 fcma flagm frintts i8mm jsconv lor lse neon paca pacg pan ras rcpc rcpc2 rdm sb ssbs v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a vh description = Support ARM v8.7a instructions. feature = vh arch = AArch64 implies = description = Enables ARM v8.1 Virtual Host extension (FEAT_VHE). feature = crt-static arch = AArch64 implies = description = Enables C Run-time Libraries to be statically linked. feature = alu32 arch = Bpf implies = description = Enable ALU32 instructions. feature = crt-static arch = Bpf implies = description = Enables C Run-time Libraries to be statically linked. feature = hvx arch = Hexagon implies = description = Hexagon HVX instructions. feature = hvx-length128b arch = Hexagon implies = hvx description = Hexagon HVX 128B instructions. feature = crt-static arch = Hexagon implies = description = Enables C Run-time Libraries to be statically linked. feature = fp64 arch = Mips implies = description = Support 64-bit FP registers. feature = msa arch = Mips implies = fp64 description = Mips MSA ASE. feature = virt arch = Mips implies = fp64 description = Mips Virtualization ASE. feature = crt-static arch = Mips implies = fp64 description = Enables C Run-time Libraries to be statically linked. feature = altivec arch = PowerPC implies = description = Enable Altivec instructions. feature = power10-vector arch = PowerPC implies = altivec power8-altivec power8-vector power9-altivec power9-vector vsx description = Enable POWER10 vector instructions. feature = power8-altivec arch = PowerPC implies = altivec description = Enable POWER8 Altivec instructions. feature = power8-vector arch = PowerPC implies = altivec power8-altivec vsx description = Enable POWER8 vector instructions. feature = power9-altivec arch = PowerPC implies = altivec power8-altivec description = Enable POWER9 Altivec instructions. feature = power9-vector arch = PowerPC implies = altivec power8-altivec power8-vector power9-altivec vsx description = Enable POWER9 vector instructions. feature = vsx arch = PowerPC implies = altivec description = Enable VSX instructions. feature = crt-static arch = PowerPC implies = description = Enables C Run-time Libraries to be statically linked. feature = a arch = RiscV implies = description = 'A' (Atomic Instructions). feature = c arch = RiscV implies = description = 'C' (Compressed Instructions). feature = d arch = RiscV implies = f description = 'D' (Double-Precision Floating-Point). feature = e arch = RiscV implies = description = Implements RV{32,64}E (provides 16 rather than 32 GPRs). feature = f arch = RiscV implies = description = 'F' (Single-Precision Floating-Point). feature = fast-unaligned-access arch = RiscV implies = description = Has reasonably performant unaligned loads and stores (both scalar and vector). feature = m arch = RiscV implies = description = 'M' (Integer Multiplication and Division). feature = relax arch = RiscV implies = description = Enable Linker relaxation.. feature = v arch = RiscV implies = d f description = 'V' (Vector Extension for Application Processors). feature = zba arch = RiscV implies = description = 'Zba' (Address Generation Instructions). feature = zbb arch = RiscV implies = description = 'Zbb' (Basic Bit-Manipulation). feature = zbc arch = RiscV implies = description = 'Zbc' (Carry-Less Multiplication). feature = zbkb arch = RiscV implies = description = 'Zbkb' (Bitmanip instructions for Cryptography). feature = zbkc arch = RiscV implies = description = 'Zbkc' (Carry-less multiply instructions for Cryptography). feature = zbkx arch = RiscV implies = description = 'Zbkx' (Crossbar permutation instructions). feature = zbs arch = RiscV implies = description = 'Zbs' (Single-Bit Instructions). feature = zdinx arch = RiscV implies = zfinx description = 'Zdinx' (Double in Integer). feature = zfh arch = RiscV implies = f zfhmin description = 'Zfh' (Half-Precision Floating-Point). feature = zfhmin arch = RiscV implies = f description = 'Zfhmin' (Half-Precision Floating-Point Minimal). feature = zfinx arch = RiscV implies = description = 'Zfinx' (Float in Integer). feature = zhinx arch = RiscV implies = zfinx zhinxmin description = 'Zhinx' (Half Float in Integer). feature = zhinxmin arch = RiscV implies = zfinx description = 'Zhinxmin' (Half Float in Integer Minimal). feature = zk arch = RiscV implies = zbkb zbkc zbkx zkn zknd zkne zknh zkr zkt description = 'Zk' (Standard scalar cryptography extension). feature = zkn arch = RiscV implies = zbkb zbkc zbkx zknd zkne zknh description = 'Zkn' (NIST Algorithm Suite). feature = zknd arch = RiscV implies = description = 'Zknd' (NIST Suite: AES Decryption). feature = zkne arch = RiscV implies = description = 'Zkne' (NIST Suite: AES Encryption). feature = zknh arch = RiscV implies = description = 'Zknh' (NIST Suite: Hash Function Instructions). feature = zkr arch = RiscV implies = description = 'Zkr' (Entropy Source Extension). feature = zks arch = RiscV implies = zbkb zbkc zbkx zksed zksh description = 'Zks' (ShangMi Algorithm Suite). feature = zksed arch = RiscV implies = description = 'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions). feature = zksh arch = RiscV implies = description = 'Zksh' (ShangMi Suite: SM3 Hash Function Instructions). feature = zkt arch = RiscV implies = description = 'Zkt' (Data Independent Execution Latency). feature = crt-static arch = RiscV implies = description = Enables C Run-time Libraries to be statically linked. feature = atomics arch = Wasm implies = description = Enable Atomics. feature = bulk-memory arch = Wasm implies = description = Enable bulk memory operations. feature = exception-handling arch = Wasm implies = description = Enable Wasm exception handling. feature = multivalue arch = Wasm implies = description = Enable multivalue blocks, instructions, and functions. feature = mutable-globals arch = Wasm implies = description = Enable mutable globals. feature = nontrapping-fptoint arch = Wasm implies = description = Enable non-trapping float-to-int conversion operators. feature = reference-types arch = Wasm implies = description = Enable reference types. feature = relaxed-simd arch = Wasm implies = description = Enable relaxed-simd instructions. feature = sign-ext arch = Wasm implies = description = Enable sign extension operators. feature = simd128 arch = Wasm implies = description = Enable 128-bit SIMD. feature = crt-static arch = Wasm implies = description = Enables C Run-time Libraries to be statically linked. feature = adx arch = X86 implies = description = Support ADX instructions. feature = aes arch = X86 implies = sse sse2 description = Enable AES instructions. feature = avx arch = X86 implies = sse sse2 sse3 sse4.1 ssse3 description = Enable AVX instructions. feature = avx2 arch = X86 implies = avx sse sse2 sse3 sse4.1 ssse3 description = Enable AVX2 instructions. feature = avx512bf16 arch = X86 implies = avx avx2 avx512bw avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Support bfloat16 floating point. feature = avx512bitalg arch = X86 implies = avx avx2 avx512bw avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 Bit Algorithms. feature = avx512bw arch = X86 implies = avx avx2 avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 Byte and Word Instructions. feature = avx512cd arch = X86 implies = avx avx2 avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 Conflict Detection Instructions. feature = avx512dq arch = X86 implies = avx avx2 avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 Doubleword and Quadword Instructions. feature = avx512er arch = X86 implies = avx avx2 avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 Exponential and Reciprocal Instructions. feature = avx512f arch = X86 implies = avx avx2 f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 instructions. feature = avx512fp16 arch = X86 implies = avx avx2 avx512bw avx512dq avx512f avx512vl f16c fma sse sse2 sse3 sse4.1 ssse3 description = Support 16-bit floating point. feature = avx512ifma arch = X86 implies = avx avx2 avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 Integer Fused Multiple-Add. feature = avx512pf arch = X86 implies = avx avx2 avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 PreFetch Instructions. feature = avx512vbmi arch = X86 implies = avx avx2 avx512bw avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 Vector Byte Manipulation Instructions. feature = avx512vbmi2 arch = X86 implies = avx avx2 avx512bw avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 further Vector Byte Manipulation Instructions. feature = avx512vl arch = X86 implies = avx avx2 avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 Vector Length eXtensions. feature = avx512vnni arch = X86 implies = avx avx2 avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 Vector Neural Network Instructions. feature = avx512vp2intersect arch = X86 implies = avx avx2 avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 vp2intersect. feature = avx512vpopcntdq arch = X86 implies = avx avx2 avx512f f16c fma sse sse2 sse3 sse4.1 ssse3 description = Enable AVX-512 Population Count Instructions. feature = bmi1 arch = X86 implies = description = Support BMI instructions. feature = bmi2 arch = X86 implies = description = Support BMI2 instructions. feature = cmpxchg16b arch = X86 implies = description = 64-bit with cmpxchg16b (this is true for most x86-64 chips, but not the first AMD chips). feature = ermsb arch = X86 implies = description = REP MOVS/STOS are fast. feature = f16c arch = X86 implies = avx sse sse2 sse3 sse4.1 ssse3 description = Support 16-bit floating point conversion instructions. feature = fma arch = X86 implies = avx sse sse2 sse3 sse4.1 ssse3 description = Enable three-operand fused multiple-add. feature = fxsr arch = X86 implies = description = Support fxsave/fxrestore instructions. feature = gfni arch = X86 implies = sse sse2 description = Enable Galois Field Arithmetic Instructions. feature = lahfsahf arch = X86 implies = description = Support LAHF and SAHF instructions in 64-bit mode. feature = lzcnt arch = X86 implies = description = Support LZCNT instruction. feature = movbe arch = X86 implies = description = Support MOVBE instruction. feature = pclmulqdq arch = X86 implies = sse sse2 description = Enable packed carry-less multiplication instructions. feature = popcnt arch = X86 implies = description = Support POPCNT instruction. feature = prfchw arch = X86 implies = description = Support PRFCHW instructions. feature = rdrand arch = X86 implies = description = Support RDRAND instruction. feature = rdseed arch = X86 implies = description = Support RDSEED instruction. feature = rtm arch = X86 implies = description = Support RTM instructions. feature = sha arch = X86 implies = sse sse2 description = Enable SHA instructions. feature = sse arch = X86 implies = description = Enable SSE instructions. feature = sse2 arch = X86 implies = sse description = Enable SSE2 instructions. feature = sse3 arch = X86 implies = sse sse2 description = Enable SSE3 instructions. feature = sse4.1 arch = X86 implies = sse sse2 sse3 ssse3 description = Enable SSE 4.1 instructions. feature = sse4.2 arch = X86 implies = sse sse2 sse3 sse4.1 ssse3 description = Enable SSE 4.2 instructions. feature = sse4a arch = X86 implies = sse sse2 sse3 description = Support SSE 4a instructions. feature = ssse3 arch = X86 implies = sse sse2 sse3 description = Enable SSSE3 instructions. feature = tbm arch = X86 implies = description = Enable TBM instructions. feature = vaes arch = X86 implies = aes avx avx2 sse sse2 sse3 sse4.1 ssse3 description = Promote selected AES instructions to AVX512/AVX registers. feature = vpclmulqdq arch = X86 implies = avx pclmulqdq sse sse2 sse3 sse4.1 ssse3 description = Enable vpclmulqdq instructions. feature = xsave arch = X86 implies = description = Support xsave instructions. feature = xsavec arch = X86 implies = xsave description = Support xsavec instructions. feature = xsaveopt arch = X86 implies = xsave description = Support xsaveopt instructions. feature = xsaves arch = X86 implies = xsave description = Support xsaves instructions. feature = crt-static arch = X86 implies = description = Enables C Run-time Libraries to be statically linked. target-features-0.1.6/tests/target.rs000064400000000000000000000014031046102023000157260ustar 00000000000000use target_features::{Architecture, Feature, Target}; #[test] fn cpu() { let mut features = Target::from_cpu(Architecture::X86, "x86-64-v2") .unwrap() .features() .map(|f| f.name()) .collect::>(); features.sort(); assert_eq!( &features, &[ "cmpxchg16b", "fxsr", "lahfsahf", "popcnt", "sse", "sse2", "sse3", "sse4.1", "sse4.2", "ssse3", ] ); } #[test] fn unknown_cpu() { let _ = Target::from_cpu(Architecture::X86, "this-doesn't-exist").unwrap_err(); } #[test] fn unknown_feature() { let _ = Feature::new(Architecture::X86, "this-doesn't-exist").unwrap_err(); }